/* Reload pseudo regs into hard regs for insns that require hard regs.
- Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
This file is part of GNU CC.
#include "machmode.h"
#include "hard-reg-set.h"
#include "rtl.h"
+#include "tm_p.h"
#include "obstack.h"
#include "insn-config.h"
#include "insn-flags.h"
#include "insn-codes.h"
#include "flags.h"
+#include "function.h"
#include "expr.h"
#include "regs.h"
#include "basic-block.h"
#include "real.h"
#include "toplev.h"
+#if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
+#define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
+#endif
+
/* This file contains the reload pass of the compiler, which is
run after register allocation has been done. It checks that
each insn is valid (operands required to be in registers really
/* This table is the inverse mapping of spill_regs:
indexed by hard reg number,
it contains the position of that reg in spill_regs,
- or -1 for something that is not in spill_regs.
+ or -1 for something that is not in spill_regs.
?!? This is no longer accurate. */
static short spill_reg_order[FIRST_PSEUDO_REGISTER];
#define obstack_chunk_alloc xmalloc
#define obstack_chunk_free free
-/* List of labels that must never be deleted. */
-extern rtx forced_labels;
-
/* List of insn_chain instructions, one for every insn that reload needs to
examine. */
struct insn_chain *reload_insn_chain;
static void delete_dead_insn PROTO((rtx));
static void alter_reg PROTO((int, int));
static void set_label_offsets PROTO((rtx, rtx, int));
+static void check_eliminable_occurrences PROTO((rtx));
+static void elimination_effects PROTO((rtx, enum machine_mode));
static int eliminate_regs_in_insn PROTO((rtx, int));
static void update_eliminable_offsets PROTO((void));
-static void mark_not_eliminable PROTO((rtx, rtx));
+static void mark_not_eliminable PROTO((rtx, rtx, void *));
static void set_initial_elim_offsets PROTO((void));
static void verify_initial_elim_offsets PROTO((void));
static void set_initial_label_offsets PROTO((void));
static int finish_spills PROTO((int, FILE *));
static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *));
static void scan_paradoxical_subregs PROTO((rtx));
-static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR));
+static int hard_reg_use_compare PROTO((const PTR, const PTR));
static void count_pseudo PROTO((struct hard_reg_n_uses *, int));
static void order_regs_for_reload PROTO((struct insn_chain *));
static void reload_as_needed PROTO((int));
-static void forget_old_reloads_1 PROTO((rtx, rtx));
-static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR));
+static void forget_old_reloads_1 PROTO((rtx, rtx, void *));
+static int reload_reg_class_lower PROTO((const PTR, const PTR));
static void mark_reload_reg_in_use PROTO((int, int, enum reload_type,
enum machine_mode));
static void clear_reload_reg_in_use PROTO((int, int, enum reload_type,
static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type));
static int allocate_reload_reg PROTO((struct insn_chain *, int, int,
int));
+static void choose_reload_regs_init PROTO((struct insn_chain *, rtx *));
static void choose_reload_regs PROTO((struct insn_chain *));
static void merge_assigned_reloads PROTO((rtx));
static void emit_reload_insns PROTO((struct insn_chain *));
static void delete_address_reloads PROTO((rtx, rtx));
static void delete_address_reloads_1 PROTO((rtx, rtx, rtx));
static rtx inc_for_reload PROTO((rtx, rtx, rtx, int));
-static int constraint_accepts_reg_p PROTO((char *, rtx));
+static int constraint_accepts_reg_p PROTO((const char *, rtx));
static void reload_cse_regs_1 PROTO((rtx));
static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int));
static int reload_cse_mem_conflict_p PROTO((rtx, rtx));
static void reload_cse_invalidate_mem PROTO((rtx));
-static void reload_cse_invalidate_rtx PROTO((rtx, rtx));
+static void reload_cse_invalidate_rtx PROTO((rtx, rtx, void *));
static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode));
static int reload_cse_noop_set_p PROTO((rtx, rtx));
static int reload_cse_simplify_set PROTO((rtx, rtx));
static int reload_cse_simplify_operands PROTO((rtx));
-static void reload_cse_check_clobber PROTO((rtx, rtx));
+static void reload_cse_check_clobber PROTO((rtx, rtx, void *));
static void reload_cse_record_set PROTO((rtx, rtx));
static void reload_combine PROTO((void));
static void reload_combine_note_use PROTO((rtx *, rtx));
-static void reload_combine_note_store PROTO((rtx, rtx));
+static void reload_combine_note_store PROTO((rtx, rtx, void *));
static void reload_cse_move2add PROTO((rtx));
-static void move2add_note_store PROTO((rtx, rtx));
+static void move2add_note_store PROTO((rtx, rtx, void *));
+#ifdef AUTO_INC_DEC
+static void add_auto_inc_notes PROTO((rtx, rtx));
+#endif
+static rtx gen_mode_int PROTO((enum machine_mode,
+ HOST_WIDE_INT));
+static void failed_reload PROTO((rtx, int));
+static int set_reload_reg PROTO((int, int));
+extern void dump_needs PROTO((struct insn_chain *, FILE *));
\f
/* Initialize the reload pass once per compilation. */
register rtx tem
= gen_rtx_MEM (Pmode,
gen_rtx_PLUS (Pmode,
- gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1),
+ gen_rtx_REG (Pmode,
+ LAST_VIRTUAL_REGISTER + 1),
GEN_INT (4)));
spill_indirect_levels = 0;
tem = gen_rtx_PLUS (Pmode,
gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
gen_rtx_REG (Pmode, i));
+
/* This way, we make sure that reg+reg is an offsettable address. */
tem = plus_constant (tem, 4);
if (unused_insn_chains == 0)
{
- c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
+ c = (struct insn_chain *)
+ obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack);
c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack);
}
if (r < 0)
{
/* reload_combine uses the information from
- basic_block_live_at_start, which might still contain registers
- that have not actually been allocated since they have an
- equivalence. */
+ BASIC_BLOCK->global_live_at_start, which might still
+ contain registers that have not actually been allocated
+ since they have an equivalence. */
if (! reload_completed)
abort ();
}
Record memory equivalents in reg_mem_equiv so they can
be substituted eventually by altering the REG-rtx's. */
- reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx));
- bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx));
- reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx));
- bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx));
- reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx));
- bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx));
- reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx));
- bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx));
- reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx));
- bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx));
- reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int));
- bzero ((char *) reg_max_ref_width, max_regno * sizeof (int));
- reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short));
- bcopy (reg_renumber, reg_old_renumber, max_regno * sizeof (short));
+ reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
+ reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
+ reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
+ reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
+ reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
+ reg_max_ref_width = (int *) xcalloc (max_regno, sizeof (int));
+ reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
+ bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
pseudo_forbidden_regs
= (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
pseudo_previous_regs
- = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
+ = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
CLEAR_HARD_REG_SET (bad_spill_regs_global);
- bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET));
/* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
Also find all paradoxical subregs and find largest such for each pseudo.
On machines with small register classes, record hard registers that
- are used for user variables. These can never be used for spills.
+ are used for user variables. These can never be used for spills.
Also look for a "constant" NOTE_INSN_SETJMP. This means that all
caller-saved registers must be marked live. */
for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
|| GET_CODE (insn) == CALL_INSN)
- note_stores (PATTERN (insn), mark_not_eliminable);
-
-#ifndef REGISTER_CONSTRAINTS
- /* If all the pseudo regs have hard regs,
- except for those that are never referenced,
- we know that no reloads are needed. */
- /* But that is not true if there are register constraints, since
- in that case some pseudos might be in the wrong kind of hard reg. */
-
- for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
- if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0)
- break;
-
- if (i == max_regno && num_eliminable == 0 && ! caller_save_needed)
- {
- free (real_known_ptr);
- free (real_at_ptr);
- free (reg_equiv_constant);
- free (reg_equiv_memory_loc);
- free (reg_equiv_mem);
- free (reg_equiv_init);
- free (reg_equiv_address);
- free (reg_max_ref_width);
- free (reg_old_renumber);
- free (pseudo_previous_regs);
- free (pseudo_forbidden_regs);
- return 0;
- }
-#endif
+ note_stores (PATTERN (insn), mark_not_eliminable, NULL);
maybe_fix_stack_asms ();
insns_need_reload = 0;
something_needs_elimination = 0;
-
+
/* Initialize to -1, which means take the first spill register. */
last_spill_reg = -1;
if (! frame_pointer_needed)
for (i = 0; i < n_basic_blocks; i++)
- CLEAR_REGNO_REG_SET (basic_block_live_at_start[i],
+ CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
HARD_FRAME_POINTER_REGNUM);
/* Come here (with failure set nonzero) if we can't get enough spill regs
{
rtx addr = 0;
int in_struct = 0;
+ int is_scalar = 0;
int is_readonly = 0;
if (reg_equiv_memory_loc[i])
{
in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
+ is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
}
if (reg_renumber[i] < 0)
{
rtx reg = regno_reg_rtx[i];
+ PUT_CODE (reg, MEM);
XEXP (reg, 0) = addr;
REG_USERVAR_P (reg) = 0;
RTX_UNCHANGING_P (reg) = is_readonly;
MEM_IN_STRUCT_P (reg) = in_struct;
+ MEM_SCALAR_P (reg) = is_scalar;
/* We have no alias information about this newly created
MEM. */
MEM_ALIAS_SET (reg) = 0;
- PUT_CODE (reg, MEM);
}
else if (reg_equiv_mem[i])
XEXP (reg_equiv_mem[i], 0) = addr;
/* Make a pass over all the insns and delete all USEs which we inserted
only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
- notes. Delete all CLOBBER insns and simplify (subreg (reg)) operands.
- Also remove all REG_RETVAL and REG_LIBCALL notes since they are no longer
- useful or accurate. */
+ notes. Delete all CLOBBER insns that don't refer to the return value
+ and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
+ REG_LIBCALL notes since they are no longer useful or accurate. Strip
+ and regenerate REG_INC notes that may have been moved around. */
for (insn = first; insn; insn = NEXT_INSN (insn))
if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
if ((GET_CODE (PATTERN (insn)) == USE
&& find_reg_note (insn, REG_EQUAL, NULL_RTX))
- || GET_CODE (PATTERN (insn)) == CLOBBER)
+ || (GET_CODE (PATTERN (insn)) == CLOBBER
+ && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
+ || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
{
PUT_CODE (insn, NOTE);
NOTE_SOURCE_FILE (insn) = 0;
{
if (REG_NOTE_KIND (*pnote) == REG_DEAD
|| REG_NOTE_KIND (*pnote) == REG_UNUSED
+ || REG_NOTE_KIND (*pnote) == REG_INC
|| REG_NOTE_KIND (*pnote) == REG_RETVAL
|| REG_NOTE_KIND (*pnote) == REG_LIBCALL)
*pnote = XEXP (*pnote, 1);
pnote = &XEXP (*pnote, 1);
}
+#ifdef AUTO_INC_DEC
+ add_auto_inc_notes (insn, PATTERN (insn));
+#endif
+
/* And simplify (subreg (reg)) if it appears as an operand. */
cleanup_subreg_operands (insn);
}
if (flag_stack_check && ! STACK_CHECK_BUILTIN)
{
HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
+ static int verbose_warned = 0;
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
size += UNITS_PER_WORD;
if (size > STACK_CHECK_MAX_FRAME_SIZE)
- warning ("frame size too large for reliable stack checking");
+ {
+ warning ("frame size too large for reliable stack checking");
+ if (! verbose_warned)
+ {
+ warning ("try reducing the number of local variables");
+ verbose_warned = 1;
+ }
+ }
}
/* Indicate that we no longer have known memory locations or constants. */
maybe_fix_stack_asms ()
{
#ifdef STACK_REGS
- char *constraints[MAX_RECOG_OPERANDS];
+ const char *constraints[MAX_RECOG_OPERANDS];
enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
struct insn_chain *chain;
}
/* Get the operand values and constraints out of the insn. */
- decode_asm_operands (pat, recog_operand, recog_operand_loc,
+ decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
constraints, operand_mode);
/* For every operand, see what registers are allowed. */
for (i = 0; i < noperands; i++)
{
- char *p = constraints[i];
+ const char *p = constraints[i];
/* For every alternative, we compute the class of registers allowed
for reloading in CLS, and merge its contents into the reg set
ALLOWED. */
default:
cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
-
+
}
}
}
int global;
{
struct insn_chain **pprev_reload = &insns_need_reload;
- struct insn_chain **pchain;
+ struct insn_chain *chain;
something_needs_elimination = 0;
- for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next)
+ for (chain = reload_insn_chain; chain != 0; chain = chain->next)
{
- rtx insn;
- struct insn_chain *chain;
+ rtx insn = chain->insn;
- chain = *pchain;
- insn = chain->insn;
+ /* Clear out the shortcuts, in case they were set last time through. */
+ chain->need_elim = 0;
+ chain->need_reload = 0;
+ chain->need_operand_change = 0;
/* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
include REG_LABEL), we need to see what effects this has on the
for (i = 0; i < n_reloads; i++)
{
register enum reg_class *p;
- enum reg_class class = reload_reg_class[i];
+ enum reg_class class = rld[i].class;
int size;
enum machine_mode mode;
struct needs *this_needs;
regs mentioned in the insn can be used for reloading.
Don't count optional reloads.
Don't count reloads that got combined with others. */
- if (reload_reg_rtx[i] != 0
- || reload_optional[i] != 0
- || (reload_out[i] == 0 && reload_in[i] == 0
- && ! reload_secondary_p[i]))
+ if (rld[i].reg_rtx != 0
+ || rld[i].optional != 0
+ || (rld[i].out == 0 && rld[i].in == 0
+ && ! rld[i].secondary_p))
continue;
- mode = reload_inmode[i];
- if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode))
- mode = reload_outmode[i];
- size = CLASS_MAX_NREGS (class, mode);
+ mode = rld[i].mode;
+ size = rld[i].nregs;
/* Decide which time-of-use to count this reload for. */
- switch (reload_when_needed[i])
+ switch (rld[i].when_needed)
{
case RELOAD_OTHER:
this_needs = &insn_needs.other;
this_needs = &insn_needs.other_addr;
break;
case RELOAD_FOR_INPUT_ADDRESS:
- this_needs = &insn_needs.in_addr[reload_opnum[i]];
+ this_needs = &insn_needs.in_addr[rld[i].opnum];
break;
case RELOAD_FOR_INPADDR_ADDRESS:
- this_needs = &insn_needs.in_addr_addr[reload_opnum[i]];
+ this_needs = &insn_needs.in_addr_addr[rld[i].opnum];
break;
case RELOAD_FOR_OUTPUT_ADDRESS:
- this_needs = &insn_needs.out_addr[reload_opnum[i]];
+ this_needs = &insn_needs.out_addr[rld[i].opnum];
break;
case RELOAD_FOR_OUTADDR_ADDRESS:
- this_needs = &insn_needs.out_addr_addr[reload_opnum[i]];
+ this_needs = &insn_needs.out_addr_addr[rld[i].opnum];
break;
case RELOAD_FOR_OPERAND_ADDRESS:
this_needs = &insn_needs.op_addr;
}
else if (size == 1)
{
- this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1;
+ this_needs->regs[(unsigned char)rld[i].nongroup][(int) class] += 1;
p = reg_class_superclasses[(int) class];
while (*p != LIM_REG_CLASSES)
- this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1;
+ this_needs->regs[(unsigned char)rld[i].nongroup][(int) *p++] += 1;
}
else
abort ();
return;
}
}
-
+
/* We know which hard regs to use, now mark the pseudos that live in them
as needing to be kicked out. */
EXECUTE_IF_SET_IN_REG_SET
struct insn_chain *chain;
FILE *dumpfile;
{
- static char *reg_class_names[] = REG_CLASS_NAMES;
+ static const char * const reg_class_names[] = REG_CLASS_NAMES;
int i;
struct needs *n = &chain->need;
fprintf (dumpfile,
";; Need %d group%s (%smode) of class %s.\n",
n->groups[i], n->groups[i] == 1 ? "" : "s",
- mode_name[(int) chain->group_mode[i]],
+ GET_MODE_NAME(chain->group_mode[i]),
reg_class_names[i]);
}
}
if (TEST_HARD_REG_BIT (bad_spill_regs, regno))
{
- static char *reg_class_names[] = REG_CLASS_NAMES;
+ static const char * const reg_class_names[] = REG_CLASS_NAMES;
if (asm_noperands (PATTERN (chain->insn)) < 0)
{
- /* The error message is still correct - we know only that it wasn't
- an asm statement that caused the problem, but one of the global
- registers declared by the users might have screwed us. */
+ /* The error message is still correct - we know only that it wasn't
+ an asm statement that caused the problem, but one of the global
+ registers declared by the users might have screwed us. */
error ("fixed or forbidden register %d (%s) was spilled for class %s.",
regno, reg_names[regno], reg_class_names[class]);
error ("This may be due to a compiler bug or to impossible asm");
stack_slot = gen_rtx_MEM (mode_for_size (total_size
* BITS_PER_UNIT,
MODE_INT, 1),
- plus_constant (XEXP (x, 0), adjust));
+ plus_constant (XEXP (x, 0), adjust));
}
spill_stack_slot[from_reg] = stack_slot;
spill_stack_slot_width[from_reg] = total_size;
if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
{
x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
- plus_constant (XEXP (x, 0), adjust));
+ plus_constant (XEXP (x, 0), adjust));
/* If this was shared among registers, must ensure we never
set it readonly since that can cause scheduling
if (p->offset != p->initial_offset)
p->can_eliminate = 0;
break;
-
+
default:
break;
}
}
\f
-/* Used for communication between the next two function to properly share
- the vector for an ASM_OPERANDS. */
-
-static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec;
-
/* Scan X and replace any eliminable registers (such as fp) with a
replacement (such as sp), plus an offset.
This means, do not set ref_outside_mem even if the reference
is outside of MEMs.
- If we see a modification to a register we know about, take the
- appropriate action (see case SET, below).
-
REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
replacements done assuming all offsets are at their initial values. If
they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
int regno;
rtx new;
int i, j;
- char *fmt;
+ const char *fmt;
int copied = 0;
if (! current_function_decl)
for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
ep++)
if (ep->from_rtx == x && ep->can_eliminate)
- {
- if (! mem_mode
- /* Refs inside notes don't count for this purpose. */
- && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
- || GET_CODE (insn) == INSN_LIST)))
- ep->ref_outside_mem = 1;
- return plus_constant (ep->to_rtx, ep->previous_offset);
- }
+ return plus_constant (ep->to_rtx, ep->previous_offset);
}
else if (reg_renumber[regno] < 0 && reg_equiv_constant
mem_mode, insn);
return x;
+ /* You might think handling MINUS in a manner similar to PLUS is a
+ good idea. It is not. It has been tried multiple times and every
+ time the change has had to have been reverted.
+
+ Other parts of reload know a PLUS is special (gen_reload for example)
+ and require special code to handle code a reloaded PLUS operand.
+
+ Also consider backends where the flags register is clobbered by a
+ MINUS, but we can emit a PLUS that does not clobber flags (ia32,
+ lea instruction comes to mind). If we try to reload a MINUS, we
+ may kill the flags register that was holding a useful value.
+
+ So, please before trying to handle MINUS, consider reload as a
+ whole instead of this little section as well as the backend issues. */
case PLUS:
/* If this is the sum of an eliminable register and a constant, rework
the sum. */
ep++)
if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
{
- if (! mem_mode
- /* Refs inside notes don't count for this purpose. */
- && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
- || GET_CODE (insn) == INSN_LIST)))
- ep->ref_outside_mem = 1;
-
/* The only time we want to replace a PLUS with a REG (this
occurs when the constant operand of the PLUS is the negative
of the offset) is when we are inside a MEM. We won't want
outermost PLUS. We will do this by doing register replacement in
our operands and seeing if a constant shows up in one of them.
- We assume here this is part of an address (or a "load address" insn)
- since an eliminable register is not likely to appear in any other
- context.
-
- If we have (plus (eliminable) (reg)), we want to produce
- (plus (plus (replacement) (reg) (const))). If this was part of a
- normal add insn, (plus (replacement) (reg)) will be pushed as a
- reload. This is the desired action. */
+ Note that there is no risk of modifying the structure of the insn,
+ since we only get called for its operands, thus we are either
+ modifying the address inside a MEM, or something like an address
+ operand of a load-address insn. */
{
rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
return x;
case MULT:
- /* If this is the product of an eliminable register and a
+ /* If this is the product of an eliminable register and a
constant, apply the distribute law and move the constant out
so that we have (plus (mult ..) ..). This is needed in order
to keep load-address insns valid. This case is pathological.
case CALL:
case COMPARE:
+ /* See comments before PLUS about handling MINUS. */
case MINUS:
case DIV: case UDIV:
case MOD: case UMOD:
{
new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
if (new != XEXP (x, 0))
- x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
+ {
+ /* If this is a REG_DEAD note, it is not valid anymore.
+ Using the eliminated version could result in creating a
+ REG_DEAD note for the stack or frame pointer. */
+ if (GET_MODE (x) == REG_DEAD)
+ return (XEXP (x, 1)
+ ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
+ : NULL_RTX);
+
+ x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
+ }
}
/* ... fall through ... */
case POST_INC:
case PRE_DEC:
case POST_DEC:
- for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
- if (ep->to_rtx == XEXP (x, 0))
- {
- int size = GET_MODE_SIZE (mem_mode);
-
- /* If more bytes than MEM_MODE are pushed, account for them. */
-#ifdef PUSH_ROUNDING
- if (ep->to_rtx == stack_pointer_rtx)
- size = PUSH_ROUNDING (size);
-#endif
- if (code == PRE_DEC || code == POST_DEC)
- ep->offset += size;
- else
- ep->offset -= size;
- }
-
- /* Fall through to generic unary operation case. */
case STRICT_LOW_PART:
case NEG: case NOT:
case SIGN_EXTEND: case ZERO_EXTEND:
&& reg_equiv_memory_loc != 0
&& reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
{
-#if 0
- new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))],
- mem_mode, insn);
-
- /* If we didn't change anything, we must retain the pseudo. */
- if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))])
- new = SUBREG_REG (x);
- else
- {
- /* In this case, we must show that the pseudo is used in this
- insn so that delete_output_reload will do the right thing. */
- if (insn != 0 && GET_CODE (insn) != EXPR_LIST
- && GET_CODE (insn) != INSN_LIST)
- REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode,
- SUBREG_REG (x)),
- insn))
- = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX);
-
- /* Ensure NEW isn't shared in case we have to reload it. */
- new = copy_rtx (new);
- }
-#else
new = SUBREG_REG (x);
-#endif
}
else
new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
#ifdef WORD_REGISTER_OPERATIONS
/* On these machines, combine can create rtl of the form
(set (subreg:m1 (reg:m2 R) 0) ...)
- where m1 < m2, and expects something interesting to
+ where m1 < m2, and expects something interesting to
happen to the entire word. Moreover, it will use the
(reg:m2 R) later, expecting all bits to be preserved.
- So if the number of words is the same, preserve the
+ So if the number of words is the same, preserve the
subreg so that push_reloads can see it. */
&& ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
#endif
return x;
- case USE:
- /* If using a register that is the source of an eliminate we still
- think can be performed, note it cannot be performed since we don't
- know how this register is used. */
- for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
- if (ep->from_rtx == XEXP (x, 0))
- ep->can_eliminate = 0;
-
- new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
- if (new != XEXP (x, 0))
- return gen_rtx_fmt_e (code, GET_MODE (x), new);
- return x;
-
- case CLOBBER:
- /* If clobbering a register that is the replacement register for an
- elimination we still think can be performed, note that it cannot
- be performed. Otherwise, we need not be concerned about it. */
- for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
- if (ep->to_rtx == XEXP (x, 0))
- ep->can_eliminate = 0;
-
- new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
- if (new != XEXP (x, 0))
- return gen_rtx_fmt_e (code, GET_MODE (x), new);
- return x;
-
- case ASM_OPERANDS:
- {
- rtx *temp_vec;
- /* Properly handle sharing input and constraint vectors. */
- if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec)
- {
- /* When we come to a new vector not seen before,
- scan all its elements; keep the old vector if none
- of them changes; otherwise, make a copy. */
- old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x);
- temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx));
- for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
- temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i),
- mem_mode, insn);
-
- for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++)
- if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i))
- break;
-
- if (i == ASM_OPERANDS_INPUT_LENGTH (x))
- new_asm_operands_vec = old_asm_operands_vec;
- else
- new_asm_operands_vec
- = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec);
- }
-
- /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
- if (new_asm_operands_vec == old_asm_operands_vec)
- return x;
-
- new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x),
- ASM_OPERANDS_OUTPUT_CONSTRAINT (x),
- ASM_OPERANDS_OUTPUT_IDX (x),
- new_asm_operands_vec,
- ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x),
- ASM_OPERANDS_SOURCE_FILE (x),
- ASM_OPERANDS_SOURCE_LINE (x));
- new->volatil = x->volatil;
- return new;
- }
-
- case SET:
- /* Check for setting a register that we know about. */
- if (GET_CODE (SET_DEST (x)) == REG)
- {
- /* See if this is setting the replacement register for an
- elimination.
-
- If DEST is the hard frame pointer, we do nothing because we
- assume that all assignments to the frame pointer are for
- non-local gotos and are being done at a time when they are valid
- and do not disturb anything else. Some machines want to
- eliminate a fake argument pointer (or even a fake frame pointer)
- with either the real frame or the stack pointer. Assignments to
- the hard frame pointer must not prevent this elimination. */
-
- for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
- ep++)
- if (ep->to_rtx == SET_DEST (x)
- && SET_DEST (x) != hard_frame_pointer_rtx)
- {
- /* If it is being incremented, adjust the offset. Otherwise,
- this elimination can't be done. */
- rtx src = SET_SRC (x);
-
- if (GET_CODE (src) == PLUS
- && XEXP (src, 0) == SET_DEST (x)
- && GET_CODE (XEXP (src, 1)) == CONST_INT)
- ep->offset -= INTVAL (XEXP (src, 1));
- else
- ep->can_eliminate = 0;
- }
-
- /* Now check to see we are assigning to a register that can be
- eliminated. If so, it must be as part of a PARALLEL, since we
- will not have been called if this is a single SET. So indicate
- that we can no longer eliminate this reg. */
- for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
- ep++)
- if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate)
- ep->can_eliminate = 0;
- }
-
- /* Now avoid the loop below in this common case. */
- {
- rtx new0 = eliminate_regs (SET_DEST (x), 0, insn);
- rtx new1 = eliminate_regs (SET_SRC (x), 0, insn);
-
- /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
- write a CLOBBER insn. */
- if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM
- && insn != 0 && GET_CODE (insn) != EXPR_LIST
- && GET_CODE (insn) != INSN_LIST)
- emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn);
-
- if (new0 != SET_DEST (x) || new1 != SET_SRC (x))
- return gen_rtx_SET (VOIDmode, new0, new1);
- }
-
- return x;
-
case MEM:
/* This is only for the benefit of the debugging backends, which call
eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
}
else
return x;
-
+
+ case USE:
+ case CLOBBER:
+ case ASM_OPERANDS:
+ case SET:
+ abort ();
+
default:
break;
}
new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
if (new != XVECEXP (x, i, j) && ! copied_vec)
{
- rtvec new_v = gen_rtvec_vv (XVECLEN (x, i),
- XVEC (x, i)->elem);
+ rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
+ XVEC (x, i)->elem);
if (! copied)
{
rtx new_x = rtx_alloc (code);
return x;
}
+
+/* Scan rtx X for modifications of elimination target registers. Update
+ the table of eliminables to reflect the changed state. MEM_MODE is
+ the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
+
+static void
+elimination_effects (x, mem_mode)
+ rtx x;
+ enum machine_mode mem_mode;
+
+{
+ enum rtx_code code = GET_CODE (x);
+ struct elim_table *ep;
+ int regno;
+ int i, j;
+ const char *fmt;
+
+ switch (code)
+ {
+ case CONST_INT:
+ case CONST_DOUBLE:
+ case CONST:
+ case SYMBOL_REF:
+ case CODE_LABEL:
+ case PC:
+ case CC0:
+ case ASM_INPUT:
+ case ADDR_VEC:
+ case ADDR_DIFF_VEC:
+ case RETURN:
+ return;
+
+ case ADDRESSOF:
+ abort ();
+
+ case REG:
+ regno = REGNO (x);
+
+ /* First handle the case where we encounter a bare register that
+ is eliminable. Replace it with a PLUS. */
+ if (regno < FIRST_PSEUDO_REGISTER)
+ {
+ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
+ ep++)
+ if (ep->from_rtx == x && ep->can_eliminate)
+ {
+ if (! mem_mode)
+ ep->ref_outside_mem = 1;
+ return;
+ }
+
+ }
+ else if (reg_renumber[regno] < 0 && reg_equiv_constant
+ && reg_equiv_constant[regno]
+ && ! CONSTANT_P (reg_equiv_constant[regno]))
+ elimination_effects (reg_equiv_constant[regno], mem_mode);
+ return;
+
+ case PRE_INC:
+ case POST_INC:
+ case PRE_DEC:
+ case POST_DEC:
+ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+ if (ep->to_rtx == XEXP (x, 0))
+ {
+ int size = GET_MODE_SIZE (mem_mode);
+
+ /* If more bytes than MEM_MODE are pushed, account for them. */
+#ifdef PUSH_ROUNDING
+ if (ep->to_rtx == stack_pointer_rtx)
+ size = PUSH_ROUNDING (size);
+#endif
+ if (code == PRE_DEC || code == POST_DEC)
+ ep->offset += size;
+ else
+ ep->offset -= size;
+ }
+
+ /* Fall through to generic unary operation case. */
+ case STRICT_LOW_PART:
+ case NEG: case NOT:
+ case SIGN_EXTEND: case ZERO_EXTEND:
+ case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
+ case FLOAT: case FIX:
+ case UNSIGNED_FIX: case UNSIGNED_FLOAT:
+ case ABS:
+ case SQRT:
+ case FFS:
+ elimination_effects (XEXP (x, 0), mem_mode);
+ return;
+
+ case SUBREG:
+ if (GET_CODE (SUBREG_REG (x)) == REG
+ && (GET_MODE_SIZE (GET_MODE (x))
+ <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
+ && reg_equiv_memory_loc != 0
+ && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
+ return;
+
+ elimination_effects (SUBREG_REG (x), mem_mode);
+ return;
+
+ case USE:
+ /* If using a register that is the source of an eliminate we still
+ think can be performed, note it cannot be performed since we don't
+ know how this register is used. */
+ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+ if (ep->from_rtx == XEXP (x, 0))
+ ep->can_eliminate = 0;
+
+ elimination_effects (XEXP (x, 0), mem_mode);
+ return;
+
+ case CLOBBER:
+ /* If clobbering a register that is the replacement register for an
+ elimination we still think can be performed, note that it cannot
+ be performed. Otherwise, we need not be concerned about it. */
+ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+ if (ep->to_rtx == XEXP (x, 0))
+ ep->can_eliminate = 0;
+
+ elimination_effects (XEXP (x, 0), mem_mode);
+ return;
+
+ case SET:
+ /* Check for setting a register that we know about. */
+ if (GET_CODE (SET_DEST (x)) == REG)
+ {
+ /* See if this is setting the replacement register for an
+ elimination.
+
+ If DEST is the hard frame pointer, we do nothing because we
+ assume that all assignments to the frame pointer are for
+ non-local gotos and are being done at a time when they are valid
+ and do not disturb anything else. Some machines want to
+ eliminate a fake argument pointer (or even a fake frame pointer)
+ with either the real frame or the stack pointer. Assignments to
+ the hard frame pointer must not prevent this elimination. */
+
+ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
+ ep++)
+ if (ep->to_rtx == SET_DEST (x)
+ && SET_DEST (x) != hard_frame_pointer_rtx)
+ {
+ /* If it is being incremented, adjust the offset. Otherwise,
+ this elimination can't be done. */
+ rtx src = SET_SRC (x);
+
+ if (GET_CODE (src) == PLUS
+ && XEXP (src, 0) == SET_DEST (x)
+ && GET_CODE (XEXP (src, 1)) == CONST_INT)
+ ep->offset -= INTVAL (XEXP (src, 1));
+ else
+ ep->can_eliminate = 0;
+ }
+ }
+
+ elimination_effects (SET_DEST (x), 0);
+ elimination_effects (SET_SRC (x), 0);
+ return;
+
+ case MEM:
+ if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
+ abort ();
+
+ /* Our only special processing is to pass the mode of the MEM to our
+ recursive call. */
+ elimination_effects (XEXP (x, 0), GET_MODE (x));
+ return;
+
+ default:
+ break;
+ }
+
+ fmt = GET_RTX_FORMAT (code);
+ for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
+ {
+ if (*fmt == 'e')
+ elimination_effects (XEXP (x, i), mem_mode);
+ else if (*fmt == 'E')
+ for (j = 0; j < XVECLEN (x, i); j++)
+ elimination_effects (XVECEXP (x, i, j), mem_mode);
+ }
+}
+
+/* Descend through rtx X and verify that no references to eliminable registers
+ remain. If any do remain, mark the involved register as not
+ eliminable. */
+static void
+check_eliminable_occurrences (x)
+ rtx x;
+{
+ const char *fmt;
+ int i;
+ enum rtx_code code;
+
+ if (x == 0)
+ return;
+
+ code = GET_CODE (x);
+
+ if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
+ {
+ struct elim_table *ep;
+
+ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
+ if (ep->from_rtx == x && ep->can_eliminate)
+ ep->can_eliminate = 0;
+ return;
+ }
+
+ fmt = GET_RTX_FORMAT (code);
+ for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
+ {
+ if (*fmt == 'e')
+ check_eliminable_occurrences (XEXP (x, i));
+ else if (*fmt == 'E')
+ {
+ int j;
+ for (j = 0; j < XVECLEN (x, i); j++)
+ check_eliminable_occurrences (XVECEXP (x, i, j));
+ }
+ }
+}
\f
/* Scan INSN and eliminate all eliminable registers in it.
rtx insn;
int replace;
{
+ int icode = recog_memoized (insn);
rtx old_body = PATTERN (insn);
+ int insn_is_asm = asm_noperands (old_body) >= 0;
rtx old_set = single_set (insn);
rtx new_body;
int val = 0;
+ int i, any_changes;
+ rtx substed_operand[MAX_RECOG_OPERANDS];
+ rtx orig_operand[MAX_RECOG_OPERANDS];
struct elim_table *ep;
+ if (! insn_is_asm && icode < 0)
+ {
+ if (GET_CODE (PATTERN (insn)) == USE
+ || GET_CODE (PATTERN (insn)) == CLOBBER
+ || GET_CODE (PATTERN (insn)) == ADDR_VEC
+ || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
+ || GET_CODE (PATTERN (insn)) == ASM_INPUT)
+ return 0;
+ abort ();
+ }
+
if (! replace)
push_obstacks (&reload_obstack, &reload_obstack);
If REPLACE isn't set, we can't delete this insn, but needn't
process it since it won't be used unless something changes. */
if (replace)
- delete_dead_insn (insn);
+ {
+ delete_dead_insn (insn);
+ return 1;
+ }
val = 1;
goto done;
}
}
}
- old_asm_operands_vec = 0;
+ /* Determine the effects of this insn on elimination offsets. */
+ elimination_effects (old_body, 0);
+
+ /* Eliminate all eliminable registers occurring in operands that
+ can be handled by reload. */
+ extract_insn (insn);
+ any_changes = 0;
+ for (i = 0; i < recog_data.n_operands; i++)
+ {
+ orig_operand[i] = recog_data.operand[i];
+ substed_operand[i] = recog_data.operand[i];
- /* Replace the body of this insn with a substituted form. If we changed
- something, return non-zero.
+ /* For an asm statement, every operand is eliminable. */
+ if (insn_is_asm || insn_data[icode].operand[i].eliminable)
+ {
+ /* Check for setting a register that we know about. */
+ if (recog_data.operand_type[i] != OP_IN
+ && GET_CODE (orig_operand[i]) == REG)
+ {
+ /* If we are assigning to a register that can be eliminated, it
+ must be as part of a PARALLEL, since the code above handles
+ single SETs. We must indicate that we can no longer
+ eliminate this reg. */
+ for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
+ ep++)
+ if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
+ ep->can_eliminate = 0;
+ }
- If we are replacing a body that was a (set X (plus Y Z)), try to
+ substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
+ replace ? insn : NULL_RTX);
+ if (substed_operand[i] != orig_operand[i])
+ val = any_changes = 1;
+ /* Terminate the search in check_eliminable_occurrences at
+ this point. */
+ *recog_data.operand_loc[i] = 0;
+
+ /* If an output operand changed from a REG to a MEM and INSN is an
+ insn, write a CLOBBER insn. */
+ if (recog_data.operand_type[i] != OP_IN
+ && GET_CODE (orig_operand[i]) == REG
+ && GET_CODE (substed_operand[i]) == MEM
+ && replace)
+ emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
+ insn);
+ }
+ }
+
+ for (i = 0; i < recog_data.n_dups; i++)
+ *recog_data.dup_loc[i]
+ = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
+
+ /* If any eliminable remain, they aren't eliminable anymore. */
+ check_eliminable_occurrences (old_body);
+
+ /* Substitute the operands; the new values are in the substed_operand
+ array. */
+ for (i = 0; i < recog_data.n_operands; i++)
+ *recog_data.operand_loc[i] = substed_operand[i];
+ for (i = 0; i < recog_data.n_dups; i++)
+ *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
+
+ /* If we are replacing a body that was a (set X (plus Y Z)), try to
re-recognize the insn. We do this in case we had a simple addition
but now can do this as a load-address. This saves an insn in this
- common case. */
+ common case.
+ If re-recognition fails, the old insn code number will still be used,
+ and some register operands may have changed into PLUS expressions.
+ These will be handled by find_reloads by loading them into a register
+ again.*/
- new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX);
- if (new_body != old_body)
+ if (val)
{
/* If we aren't replacing things permanently and we changed something,
make another copy to ensure that all the RTL is new. Otherwise
things can go wrong if find_reload swaps commutative operands
and one is inside RTL that has been copied while the other is not. */
-
- /* Don't copy an asm_operands because (1) there's no need and (2)
- copy_rtx can't do it properly when there are multiple outputs. */
- if (! replace && asm_noperands (old_body) < 0)
- new_body = copy_rtx (new_body);
+ new_body = old_body;
+ if (! replace)
+ {
+ new_body = copy_insn (old_body);
+ if (REG_NOTES (insn))
+ REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
+ }
+ PATTERN (insn) = new_body;
/* If we had a move insn but now we don't, rerecognize it. This will
cause spurious re-recognition if the old move had a PARALLEL since
the new one still will, but we can't call single_set without
having put NEW_BODY into the insn and the re-recognition won't
hurt in this rare case. */
- if (old_set != 0
+ /* ??? Why this huge if statement - why don't we just rerecognize the
+ thing always? */
+ if (! insn_is_asm
+ && old_set != 0
&& ((GET_CODE (SET_SRC (old_set)) == REG
&& (GET_CODE (new_body) != SET
|| GET_CODE (SET_SRC (new_body)) != REG))
/* If this was a load from or store to memory, compare
- the MEM in recog_operand to the one in the insn. If they
- are not equal, then rerecognize the insn. */
+ the MEM in recog_data.operand to the one in the insn.
+ If they are not equal, then rerecognize the insn. */
|| (old_set != 0
&& ((GET_CODE (SET_SRC (old_set)) == MEM
- && SET_SRC (old_set) != recog_operand[1])
+ && SET_SRC (old_set) != recog_data.operand[1])
|| (GET_CODE (SET_DEST (old_set)) == MEM
- && SET_DEST (old_set) != recog_operand[0])))
+ && SET_DEST (old_set) != recog_data.operand[0])))
/* If this was an add insn before, rerecognize. */
|| GET_CODE (SET_SRC (old_set)) == PLUS))
{
- if (! validate_change (insn, &PATTERN (insn), new_body, 0))
- /* If recognition fails, store the new body anyway.
- It's normal to have recognition failures here
- due to bizarre memory addresses; reloading will fix them. */
- PATTERN (insn) = new_body;
+ int new_icode = recog (PATTERN (insn), insn, 0);
+ if (new_icode < 0)
+ INSN_CODE (insn) = icode;
}
- else
- PATTERN (insn) = new_body;
+ }
- val = 1;
+ /* Restore the old body. If there were any changes to it, we made a copy
+ of it while the changes were still in place, so we'll correctly return
+ a modified insn below. */
+ if (! replace)
+ {
+ /* Restore the old body. */
+ for (i = 0; i < recog_data.n_operands; i++)
+ *recog_data.operand_loc[i] = orig_operand[i];
+ for (i = 0; i < recog_data.n_dups; i++)
+ *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
}
- /* Loop through all elimination pairs. See if any have changed.
+ /* Update all elimination pairs to reflect the status after the current
+ insn. The changes we make were determined by the earlier call to
+ elimination_effects.
We also detect a cases where register elimination cannot be done,
namely, if a register would be both changed and referenced outside a MEM
the insns of the function. */
static void
-mark_not_eliminable (dest, x)
+mark_not_eliminable (dest, x, data)
rtx dest;
rtx x;
+ void *data ATTRIBUTE_UNUSED;
{
register unsigned int i;
INITIAL_FRAME_POINTER_OFFSET (t);
if (t != reg_eliminate[0].initial_offset)
abort ();
-#endif
+#endif
}
/* Reset all offsets on eliminable registers to their initial values. */
#endif
if (!reg_eliminate)
- {
- reg_eliminate = (struct elim_table *)
- xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
- bzero ((PTR) reg_eliminate,
- sizeof(struct elim_table) * NUM_ELIMINABLE_REGS);
- }
-
+ reg_eliminate = (struct elim_table *)
+ xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
+
/* Does this function require a frame pointer? */
frame_pointer_needed = (! flag_omit_frame_pointer
static void
spill_hard_reg (regno, dumpfile, cant_eliminate)
register int regno;
- FILE *dumpfile;
+ FILE *dumpfile ATTRIBUTE_UNUSED;
int cant_eliminate;
{
register int i;
{
IOR_HARD_REG_SET (*set1, *set2);
}
-
+
/* After find_reload_regs has been run for all insn that need reloads,
and/or spill_hard_regs was called, this function is used to actually
spill pseudo registers and try to reallocate them. It also sets up the
/* Retry allocating the spilled pseudos. For each reg, merge the
various reg sets that indicate which hard regs can't be used,
and call retry_global_alloc.
- We change spill_pseudos here to only contain pseudos that did not
+ We change spill_pseudos here to only contain pseudos that did not
get a new hard register. */
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
if (reg_old_renumber[i] != reg_renumber[i])
int regno = reg_renumber[i];
if (reg_old_renumber[i] == regno)
continue;
-
+
alter_reg (i, reg_old_renumber[i]);
reg_old_renumber[i] = regno;
if (dumpfile)
return something_changed;
}
\f
-/* Find all paradoxical subregs within X and update reg_max_ref_width.
+/* Find all paradoxical subregs within X and update reg_max_ref_width.
Also mark any hard registers used to store user variables as
forbidden from being used for spill registers. */
register rtx x;
{
register int i;
- register char *fmt;
+ register const char *fmt;
register enum rtx_code code = GET_CODE (x);
switch (code)
reg_max_ref_width[REGNO (SUBREG_REG (x))]
= GET_MODE_SIZE (GET_MODE (x));
return;
-
+
default:
break;
}
\f
static int
hard_reg_use_compare (p1p, p2p)
- const GENERIC_PTR p1p;
- const GENERIC_PTR p2p;
-{
- struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p;
- struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p;
+ const PTR p1p;
+ const PTR p2p;
+{
+ const struct hard_reg_n_uses *p1 = (const struct hard_reg_n_uses *)p1p;
+ const struct hard_reg_n_uses *p2 = (const struct hard_reg_n_uses *)p2p;
int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno);
int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno);
if (bad1 && bad2)
nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
while (nregs-- > 0)
- n_uses[r++].uses += REG_N_REFS (reg);
+ n_uses[r++].uses += REG_N_REFS (reg);
}
/* Choose the order to consider regs for use as reload registers
based on how much trouble would be caused by spilling one.
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
- int j;
-
hard_reg_n_uses[i].regno = i;
hard_reg_n_uses[i].uses = 0;
if (fixed_regs[i]
|| REGNO_REG_SET_P (chain->live_before, i)
|| REGNO_REG_SET_P (chain->live_after, i))
- {
- SET_HARD_REG_BIT (bad_spill_regs, i);
- continue;
- }
+ SET_HARD_REG_BIT (bad_spill_regs, i);
+ }
- /* Now find out which pseudos are allocated to it, and update
- hard_reg_n_uses. */
- CLEAR_REG_SET (pseudos_counted);
+ /* Now compute hard_reg_n_uses. */
+ CLEAR_REG_SET (pseudos_counted);
- EXECUTE_IF_SET_IN_REG_SET
- (chain->live_before, FIRST_PSEUDO_REGISTER, j,
- {
- count_pseudo (hard_reg_n_uses, j);
- });
- EXECUTE_IF_SET_IN_REG_SET
- (chain->live_after, FIRST_PSEUDO_REGISTER, j,
- {
- count_pseudo (hard_reg_n_uses, j);
- });
- }
+ EXECUTE_IF_SET_IN_REG_SET
+ (chain->live_before, FIRST_PSEUDO_REGISTER, i,
+ {
+ count_pseudo (hard_reg_n_uses, i);
+ });
+ EXECUTE_IF_SET_IN_REG_SET
+ (chain->live_after, FIRST_PSEUDO_REGISTER, i,
+ {
+ count_pseudo (hard_reg_n_uses, i);
+ });
FREE_REG_SET (pseudos_counted);
bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
bzero ((char *) spill_reg_store, sizeof spill_reg_store);
- reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx));
- bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx));
- reg_has_output_reload = (char *) alloca (max_regno);
+ reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
+ reg_has_output_reload = (char *) xmalloc (max_regno);
CLEAR_HARD_REG_SET (reg_reloaded_valid);
set_initial_elim_offsets ();
Record the choices of reload reg in reload_reg_rtx. */
choose_reload_regs (chain);
- /* Merge any reloads that we didn't combine for fear of
+ /* Merge any reloads that we didn't combine for fear of
increasing the number of spill registers needed but now
discover can be safely merged. */
if (SMALL_REGISTER_CLASSES)
for this insn in order to be stored in
(obeying register constraints). That is correct; such reload
registers ARE still valid. */
- note_stores (oldpat, forget_old_reloads_1);
+ note_stores (oldpat, forget_old_reloads_1, NULL);
/* There may have been CLOBBER insns placed after INSN. So scan
between INSN and NEXT and use them to forget old reloads. */
for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
- note_stores (PATTERN (x), forget_old_reloads_1);
+ note_stores (PATTERN (x), forget_old_reloads_1, NULL);
#ifdef AUTO_INC_DEC
/* Likewise for regs altered by auto-increment in this insn.
which have been performed by subst_reloads above. */
for (i = n_reloads - 1; i >= 0; i--)
{
- rtx in_reg = reload_in_reg[i];
+ rtx in_reg = rld[i].in_reg;
if (in_reg)
{
enum rtx_code code = GET_CODE (in_reg);
or we can't use the reload register for inheritance. */
if ((code == POST_INC || code == POST_DEC)
&& TEST_HARD_REG_BIT (reg_reloaded_valid,
- REGNO (reload_reg_rtx[i]))
+ REGNO (rld[i].reg_rtx))
/* Make sure it is the inc/dec pseudo, and not
some other (e.g. output operand) pseudo. */
- && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])]
+ && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
== REGNO (XEXP (in_reg, 0))))
-
+
{
- rtx reload_reg = reload_reg_rtx[i];
+ rtx reload_reg = rld[i].reg_rtx;
enum machine_mode mode = GET_MODE (reload_reg);
int n = 0;
rtx p;
reload_reg, p);
break;
}
-
+
}
break;
}
if (n == 1)
- REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
- REG_NOTES (p));
+ {
+ REG_NOTES (p)
+ = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
+ REG_NOTES (p));
+ /* Mark this as having an output reload so that the
+ REG_INC processing code below won't invalidate
+ the reload for inheritance. */
+ SET_HARD_REG_BIT (reg_is_output_reload,
+ REGNO (reload_reg));
+ reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
+ }
else
- forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX);
+ forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
+ NULL);
+ }
+ else if ((code == PRE_INC || code == PRE_DEC)
+ && TEST_HARD_REG_BIT (reg_reloaded_valid,
+ REGNO (rld[i].reg_rtx))
+ /* Make sure it is the inc/dec pseudo, and not
+ some other (e.g. output operand) pseudo. */
+ && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
+ == REGNO (XEXP (in_reg, 0))))
+ {
+ SET_HARD_REG_BIT (reg_is_output_reload,
+ REGNO (rld[i].reg_rtx));
+ reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
}
}
}
-#if 0 /* ??? Is this code obsolete now? Need to check carefully. */
- /* Likewise for regs altered by auto-increment in this insn.
- But note that the reg-notes are not changed by reloading:
- they still contain the pseudo-regs, not the spill regs. */
+ /* If a pseudo that got a hard register is auto-incremented,
+ we must purge records of copying it into pseudos without
+ hard registers. */
for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
if (REG_NOTE_KIND (x) == REG_INC)
{
If so, its last-reload info is still valid
because it is based on this insn's reload. */
for (i = 0; i < n_reloads; i++)
- if (reload_out[i] == XEXP (x, 0))
+ if (rld[i].out == XEXP (x, 0))
break;
if (i == n_reloads)
- forget_old_reloads_1 (XEXP (x, 0), NULL_RTX);
+ forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
}
-#endif
#endif
}
/* A reload reg's contents are unknown after a label. */
&& INSN_CLOBBERS_REGNO_P (insn, i))
CLEAR_HARD_REG_BIT (reg_reloaded_valid, i);
#endif
-
-#ifdef USE_C_ALLOCA
- alloca (0);
-#endif
}
+
+ /* Clean up. */
+ free (reg_last_reload_reg);
+ free (reg_has_output_reload);
}
/* Discard all record of any value reloaded from X,
or it may be a pseudo reg that was reloaded from. */
static void
-forget_old_reloads_1 (x, ignored)
+forget_old_reloads_1 (x, ignored, data)
rtx x;
rtx ignored ATTRIBUTE_UNUSED;
+ void *data ATTRIBUTE_UNUSED;
{
register int regno;
int nr;
reg_last_reload_reg[regno + nr] = 0;
}
\f
-/* For each reload, the mode of the reload register. */
-static enum machine_mode reload_mode[MAX_RELOADS];
-
-/* For each reload, the largest number of registers it will require. */
-static int reload_nregs[MAX_RELOADS];
-
/* Comparison function for qsort to decide which of two reloads
should be handled first. *P1 and *P2 are the reload numbers. */
static int
reload_reg_class_lower (r1p, r2p)
- const GENERIC_PTR r1p;
- const GENERIC_PTR r2p;
+ const PTR r1p;
+ const PTR r2p;
{
- register int r1 = *(short *)r1p, r2 = *(short *)r2p;
+ register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
register int t;
/* Consider required reloads before optional ones. */
- t = reload_optional[r1] - reload_optional[r2];
+ t = rld[r1].optional - rld[r2].optional;
if (t != 0)
return t;
/* Count all solitary classes before non-solitary ones. */
- t = ((reg_class_size[(int) reload_reg_class[r2]] == 1)
- - (reg_class_size[(int) reload_reg_class[r1]] == 1));
+ t = ((reg_class_size[(int) rld[r2].class] == 1)
+ - (reg_class_size[(int) rld[r1].class] == 1));
if (t != 0)
return t;
/* Aside from solitaires, consider all multi-reg groups first. */
- t = reload_nregs[r2] - reload_nregs[r1];
+ t = rld[r2].nregs - rld[r1].nregs;
if (t != 0)
return t;
/* Consider reloads in order of increasing reg-class number. */
- t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2];
+ t = (int) rld[r1].class - (int) rld[r2].class;
if (t != 0)
return t;
more then what would be necessary if we used a HARD_REG_SET here.
But this should only happen very infrequently, so there should
be no reason to worry about it. */
-
+
start_regno = regno;
end_regno = regno + nregs;
if (check_opnum || check_any)
{
for (i = n_reloads - 1; i >= 0; i--)
{
- if (reload_when_needed[i] == type
- && (check_any || reload_opnum[i] == opnum)
- && reload_reg_rtx[i])
+ if (rld[i].when_needed == type
+ && (check_any || rld[i].opnum == opnum)
+ && rld[i].reg_rtx)
{
- int conflict_start = true_regnum (reload_reg_rtx[i]);
+ int conflict_start = true_regnum (rld[i].reg_rtx);
int conflict_end
= (conflict_start
- + HARD_REGNO_NREGS (conflict_start, reload_mode[i]));
+ + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
/* If there is an overlap with the first to-be-freed register,
adjust the interval start. */
case RELOAD_FOR_INPADDR_ADDRESS:
/* Can't use a register if it is used for an input address
- for this operand or used as an input in an earlier
- one. */
+ for this operand or used as an input in an earlier
+ one. */
if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
return 0;
case RELOAD_FOR_OUTADDR_ADDRESS:
/* Can't use a register if it is used for an output address
- for this operand or used as an output in this or a
- later operand. */
+ for this operand or used as an output in this or a
+ later operand. */
if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
return 0;
case RELOAD_FOR_OPADDR_ADDR:
for (i = 0; i < reload_n_operands; i++)
- if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
- return 0;
+ if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
+ return 0;
return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
return 1;
/* If this use is for part of the insn,
- its value reaches if no subsequent part uses the same register.
+ its value reaches if no subsequent part uses the same register.
Just like the above function, don't try to do this with lots
of fallthroughs. */
case RELOAD_FOR_INPUT:
/* Similar to input address, except we start at the next operand for
- both input and input address and we do not check for
+ both input and input address and we do not check for
RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
would conflict. */
reloads_conflict (r1, r2)
int r1, r2;
{
- enum reload_type r1_type = reload_when_needed[r1];
- enum reload_type r2_type = reload_when_needed[r2];
- int r1_opnum = reload_opnum[r1];
- int r2_opnum = reload_opnum[r2];
+ enum reload_type r1_type = rld[r1].when_needed;
+ enum reload_type r2_type = rld[r2].when_needed;
+ int r1_opnum = rld[r1].opnum;
+ int r2_opnum = rld[r2].opnum;
/* RELOAD_OTHER conflicts with everything. */
if (r2_type == RELOAD_OTHER)
switch (r1_type)
{
case RELOAD_FOR_INPUT:
- return (r2_type == RELOAD_FOR_INSN
+ return (r2_type == RELOAD_FOR_INSN
|| r2_type == RELOAD_FOR_OPERAND_ADDRESS
|| r2_type == RELOAD_FOR_OPADDR_ADDR
|| r2_type == RELOAD_FOR_INPUT
|| r2_type == RELOAD_FOR_OPERAND_ADDRESS);
case RELOAD_FOR_OPADDR_ADDR:
- return (r2_type == RELOAD_FOR_INPUT
+ return (r2_type == RELOAD_FOR_INPUT
|| r2_type == RELOAD_FOR_OPADDR_ADDR);
case RELOAD_FOR_OUTPUT:
return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
|| ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
|| r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
- && r2_opnum >= r1_opnum));
+ && r2_opnum <= r1_opnum));
case RELOAD_FOR_INSN:
return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
register. */
static int
reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
- ignore_address_reloads)
+ ignore_address_reloads)
int regno;
int opnum;
enum reload_type type;
int ignore_address_reloads;
{
int time1;
+ /* Set if we see an input reload that must not share its reload register
+ with any new earlyclobber, but might otherwise share the reload
+ register with an output or input-output reload. */
+ int check_earlyclobber = 0;
int i;
int copy = 0;
+ /* ??? reload_reg_used is abused to hold the registers that are not
+ available as spill registers, including hard registers that are
+ earlyclobbered in asms. As a temporary measure, reject anything
+ in reload_reg_used. */
+ if (TEST_HARD_REG_BIT (reload_reg_used, regno))
+ return 0;
+
if (out == const0_rtx)
{
copy = 1;
switch (type)
{
case RELOAD_FOR_OTHER_ADDRESS:
- time1 = 0;
+ /* RELOAD_FOR_OTHER_ADDRESS conflits with RELOAD_OTHER reloads. */
+ time1 = copy ? 0 : 1;
break;
case RELOAD_OTHER:
time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
break;
- /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
- RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
- respectively, to the time values for these, we get distinct time
- values. To get distinct time values for each operand, we have to
- multiply opnum by at least three. We round that up to four because
- multiply by four is often cheaper. */
+ /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
+ RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
+ respectively, to the time values for these, we get distinct time
+ values. To get distinct time values for each operand, we have to
+ multiply opnum by at least three. We round that up to four because
+ multiply by four is often cheaper. */
case RELOAD_FOR_INPADDR_ADDRESS:
time1 = opnum * 4 + 2;
break;
time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
break;
case RELOAD_FOR_OPADDR_ADDR:
- /* opnum * 4 + 4
- <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
+ /* opnum * 4 + 4
+ <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
time1 = MAX_RECOG_OPERANDS * 4 + 1;
break;
case RELOAD_FOR_OPERAND_ADDRESS:
for (i = 0; i < n_reloads; i++)
{
- rtx reg = reload_reg_rtx[i];
+ rtx reg = rld[i].reg_rtx;
if (reg && GET_CODE (reg) == REG
&& ((unsigned) regno - true_regnum (reg)
<= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
&& i != reloadnum)
{
- if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value)
- || reload_out[i] || out)
+ if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
+ || rld[i].out || out)
{
int time2;
- switch (reload_when_needed[i])
+ switch (rld[i].when_needed)
{
case RELOAD_FOR_OTHER_ADDRESS:
time2 = 0;
/* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
Then the address address is still needed to store
back the new address. */
- && ! reload_out[reloadnum])
+ && ! rld[reloadnum].out)
continue;
/* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
reloads go away. */
- if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
+ if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
&& ignore_address_reloads
/* Unless we are reloading an auto_inc expression. */
- && ! reload_out[reloadnum])
+ && ! rld[reloadnum].out)
continue;
- time2 = reload_opnum[i] * 4 + 2;
+ time2 = rld[i].opnum * 4 + 2;
break;
case RELOAD_FOR_INPUT_ADDRESS:
- if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i]
+ if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
&& ignore_address_reloads
- && ! reload_out[reloadnum])
+ && ! rld[reloadnum].out)
continue;
- time2 = reload_opnum[i] * 4 + 3;
+ time2 = rld[i].opnum * 4 + 3;
break;
case RELOAD_FOR_INPUT:
- time2 = reload_opnum[i] * 4 + 4;
+ time2 = rld[i].opnum * 4 + 4;
+ check_earlyclobber = 1;
break;
- /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
- == MAX_RECOG_OPERAND * 4 */
+ /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
+ == MAX_RECOG_OPERAND * 4 */
case RELOAD_FOR_OPADDR_ADDR:
if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
&& ignore_address_reloads
- && ! reload_out[reloadnum])
+ && ! rld[reloadnum].out)
continue;
time2 = MAX_RECOG_OPERANDS * 4 + 1;
break;
case RELOAD_FOR_OPERAND_ADDRESS:
time2 = MAX_RECOG_OPERANDS * 4 + 2;
+ check_earlyclobber = 1;
break;
case RELOAD_FOR_INSN:
time2 = MAX_RECOG_OPERANDS * 4 + 3;
break;
case RELOAD_FOR_OUTPUT:
- /* All RELOAD_FOR_OUTPUT reloads become live just after the
- instruction is executed. */
+ /* All RELOAD_FOR_OUTPUT reloads become live just after the
+ instruction is executed. */
time2 = MAX_RECOG_OPERANDS * 4 + 4;
break;
- /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
- the RELOAD_FOR_OUTPUT reloads, so assign it the same time
- value. */
+ /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
+ the RELOAD_FOR_OUTPUT reloads, so assign it the same time
+ value. */
case RELOAD_FOR_OUTADDR_ADDRESS:
if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
&& ignore_address_reloads
- && ! reload_out[reloadnum])
+ && ! rld[reloadnum].out)
continue;
- time2 = MAX_RECOG_OPERANDS * 4 + 4 + reload_opnum[i];
+ time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
break;
case RELOAD_FOR_OUTPUT_ADDRESS:
- time2 = MAX_RECOG_OPERANDS * 4 + 5 + reload_opnum[i];
+ time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
break;
case RELOAD_OTHER:
/* If there is no conflict in the input part, handle this
like an output reload. */
- if (! reload_in[i] || rtx_equal_p (reload_in[i], value))
+ if (! rld[i].in || rtx_equal_p (rld[i].in, value))
{
time2 = MAX_RECOG_OPERANDS * 4 + 4;
+ /* Earlyclobbered outputs must conflict with inputs. */
+ if (earlyclobber_operand_p (rld[i].out))
+ time2 = MAX_RECOG_OPERANDS * 4 + 3;
+
break;
}
time2 = 1;
return 0;
}
if ((time1 >= time2
- && (! reload_in[i] || reload_out[i]
- || ! rtx_equal_p (reload_in[i], value)))
- || (out && reload_out_reg[reloadnum]
+ && (! rld[i].in || rld[i].out
+ || ! rtx_equal_p (rld[i].in, value)))
+ || (out && rld[reloadnum].out_reg
&& time2 >= MAX_RECOG_OPERANDS * 4 + 3))
return 0;
}
}
}
+
+ /* Earlyclobbered outputs must conflict with inputs. */
+ if (check_earlyclobber && out && earlyclobber_operand_p (out))
+ return 0;
+
return 1;
}
+/* Give an error message saying we failed to find a reload for INSN,
+ and clear out reload R. */
+static void
+failed_reload (insn, r)
+ rtx insn;
+ int r;
+{
+ if (asm_noperands (PATTERN (insn)) < 0)
+ /* It's the compiler's fault. */
+ fatal_insn ("Could not find a spill register", insn);
+
+ /* It's the user's fault; the operand's mode and constraint
+ don't match. Disable this reload so we don't crash in final. */
+ error_for_asm (insn,
+ "`asm' operand constraint incompatible with operand size");
+ rld[r].in = 0;
+ rld[r].out = 0;
+ rld[r].reg_rtx = 0;
+ rld[r].optional = 1;
+ rld[r].secondary_p = 1;
+}
+
+/* I is the index in SPILL_REG_RTX of the reload register we are to allocate
+ for reload R. If it's valid, get an rtx for it. Return nonzero if
+ successful. */
+static int
+set_reload_reg (i, r)
+ int i, r;
+{
+ int regno;
+ rtx reg = spill_reg_rtx[i];
+
+ if (reg == 0 || GET_MODE (reg) != rld[r].mode)
+ spill_reg_rtx[i] = reg
+ = gen_rtx_REG (rld[r].mode, spill_regs[i]);
+
+ regno = true_regnum (reg);
+
+ /* Detect when the reload reg can't hold the reload mode.
+ This used to be one `if', but Sequent compiler can't handle that. */
+ if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
+ {
+ enum machine_mode test_mode = VOIDmode;
+ if (rld[r].in)
+ test_mode = GET_MODE (rld[r].in);
+ /* If rld[r].in has VOIDmode, it means we will load it
+ in whatever mode the reload reg has: to wit, rld[r].mode.
+ We have already tested that for validity. */
+ /* Aside from that, we need to test that the expressions
+ to reload from or into have modes which are valid for this
+ reload register. Otherwise the reload insns would be invalid. */
+ if (! (rld[r].in != 0 && test_mode != VOIDmode
+ && ! HARD_REGNO_MODE_OK (regno, test_mode)))
+ if (! (rld[r].out != 0
+ && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
+ {
+ /* The reg is OK. */
+ last_spill_reg = i;
+
+ /* Mark as in use for this insn the reload regs we use
+ for this. */
+ mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
+ rld[r].when_needed, rld[r].mode);
+
+ rld[r].reg_rtx = reg;
+ reload_spill_index[r] = spill_regs[i];
+ return 1;
+ }
+ }
+ return 0;
+}
+
/* Find a spill register to use as a reload register for reload R.
LAST_RELOAD is non-zero if this is the last reload for the insn being
processed.
- Set reload_reg_rtx[R] to the register allocated.
+ Set rld[R].reg_rtx to the register allocated.
If NOERROR is nonzero, we return 1 if successful,
or 0 if we couldn't find a spill reg and we didn't change anything. */
int noerror;
{
rtx insn = chain->insn;
- int i, pass, count, regno;
- rtx new;
+ int i, pass, count;
/* If we put this reload ahead, thinking it is a group,
then insist on finding a group. Otherwise we can grab a
Perhaps those classes should be avoided for reloading
by use of more alternatives. */
- int force_group = reload_nregs[r] > 1 && ! last_reload;
+ int force_group = rld[r].nregs > 1 && ! last_reload;
/* If we want a single register and haven't yet found one,
take any reg in the right class and not in use.
of leapfrogging each other. Don't do this, however, when we have
group needs and failure would be fatal; if we only have a relatively
small number of spill registers, and more than one of them has
- group needs, then by starting in the middle, we may end up
+ group needs, then by starting in the middle, we may end up
allocating the first one in such a way that we are not left with
sufficient groups to handle the rest. */
i = last_spill_reg;
else
i = -1;
-
+
for (count = 0; count < n_spills; count++)
{
- int class = (int) reload_reg_class[r];
+ int class = (int) rld[r].class;
int regnum;
i++;
i -= n_spills;
regnum = spill_regs[i];
- if ((reload_reg_free_p (regnum, reload_opnum[r],
- reload_when_needed[r])
- || (reload_in[r]
- /* We check reload_reg_used to make sure we
- don't clobber the return register. */
+ if ((reload_reg_free_p (regnum, rld[r].opnum,
+ rld[r].when_needed)
+ || (rld[r].in
+ /* We check reload_reg_used to make sure we
+ don't clobber the return register. */
&& ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
&& reload_reg_free_for_value_p (regnum,
- reload_opnum[r],
- reload_when_needed[r],
- reload_in[r],
- reload_out[r], r, 1)))
+ rld[r].opnum,
+ rld[r].when_needed,
+ rld[r].in,
+ rld[r].out, r, 1)))
&& TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
- && HARD_REGNO_MODE_OK (regnum, reload_mode[r])
+ && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
/* Look first for regs to share, then for unshared. But
don't share regs used for inherited reloads; they are
the ones we want to preserve. */
&& ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
regnum))))
{
- int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]);
+ int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
/* Avoid the problem where spilling a GENERAL_OR_FP_REG
(on 68000) got us two FP regs. If NR is 1,
we would reject both of them. */
if (force_group)
- nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]);
+ nr = rld[r].nregs;
/* If we need only one reg, we have already won. */
if (nr == 1)
{
if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum))
while (nr > 1)
{
- regno = regnum + nr - 1;
+ int regno = regnum + nr - 1;
if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
&& spill_reg_order[regno] >= 0
- && reload_reg_free_p (regno, reload_opnum[r],
- reload_when_needed[r])
+ && reload_reg_free_p (regno, rld[r].opnum,
+ rld[r].when_needed)
&& ! TEST_HARD_REG_BIT (chain->counted_for_nongroups,
regno)))
break;
goto failure;
}
- /* I is the index in SPILL_REG_RTX of the reload register we are to
- allocate. Get an rtx for it and find its register number. */
-
- new = spill_reg_rtx[i];
-
- if (new == 0 || GET_MODE (new) != reload_mode[r])
- spill_reg_rtx[i] = new
- = gen_rtx_REG (reload_mode[r], spill_regs[i]);
-
- regno = true_regnum (new);
-
- /* Detect when the reload reg can't hold the reload mode.
- This used to be one `if', but Sequent compiler can't handle that. */
- if (HARD_REGNO_MODE_OK (regno, reload_mode[r]))
- {
- enum machine_mode test_mode = VOIDmode;
- if (reload_in[r])
- test_mode = GET_MODE (reload_in[r]);
- /* If reload_in[r] has VOIDmode, it means we will load it
- in whatever mode the reload reg has: to wit, reload_mode[r].
- We have already tested that for validity. */
- /* Aside from that, we need to test that the expressions
- to reload from or into have modes which are valid for this
- reload register. Otherwise the reload insns would be invalid. */
- if (! (reload_in[r] != 0 && test_mode != VOIDmode
- && ! HARD_REGNO_MODE_OK (regno, test_mode)))
- if (! (reload_out[r] != 0
- && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r]))))
- {
- /* The reg is OK. */
- last_spill_reg = i;
-
- /* Mark as in use for this insn the reload regs we use
- for this. */
- mark_reload_reg_in_use (spill_regs[i], reload_opnum[r],
- reload_when_needed[r], reload_mode[r]);
-
- reload_reg_rtx[r] = new;
- reload_spill_index[r] = spill_regs[i];
- return 1;
- }
- }
+ if (set_reload_reg (i, r))
+ return 1;
/* The reg is not OK. */
if (noerror)
return 0;
failure:
- if (asm_noperands (PATTERN (insn)) < 0)
- /* It's the compiler's fault. */
- fatal_insn ("Could not find a spill register", insn);
-
- /* It's the user's fault; the operand's mode and constraint
- don't match. Disable this reload so we don't crash in final. */
- error_for_asm (insn,
- "`asm' operand constraint incompatible with operand size");
- reload_in[r] = 0;
- reload_out[r] = 0;
- reload_reg_rtx[r] = 0;
- reload_optional[r] = 1;
- reload_secondary_p[r] = 1;
+ failed_reload (insn, r);
return 1;
}
\f
-/* Assign hard reg targets for the pseudo-registers we must reload
- into hard regs for this insn.
- Also output the instructions to copy them in and out of the hard regs.
-
- For machines with register classes, we are responsible for
- finding a reload reg in the proper class. */
-
+/* Initialize all the tables needed to allocate reload registers.
+ CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
+ is the array we use to restore the reg_rtx field for every reload. */
static void
-choose_reload_regs (chain)
+choose_reload_regs_init (chain, save_reload_reg_rtx)
struct insn_chain *chain;
+ rtx *save_reload_reg_rtx;
{
- rtx insn = chain->insn;
- register int i, j;
- int max_group_size = 1;
- enum reg_class group_class = NO_REGS;
- int inheritance;
- int pass;
+ int i;
- rtx save_reload_reg_rtx[MAX_RELOADS];
- char save_reload_inherited[MAX_RELOADS];
- rtx save_reload_inheritance_insn[MAX_RELOADS];
- rtx save_reload_override_in[MAX_RELOADS];
- int save_reload_spill_index[MAX_RELOADS];
- HARD_REG_SET save_reload_reg_used;
- HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
- HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
- HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
- HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
- HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS];
- HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS];
- HARD_REG_SET save_reload_reg_used_in_op_addr;
- HARD_REG_SET save_reload_reg_used_in_op_addr_reload;
- HARD_REG_SET save_reload_reg_used_in_insn;
- HARD_REG_SET save_reload_reg_used_in_other_addr;
- HARD_REG_SET save_reload_reg_used_at_all;
+ for (i = 0; i < n_reloads; i++)
+ rld[i].reg_rtx = save_reload_reg_rtx[i];
bzero (reload_inherited, MAX_RELOADS);
bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
}
IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs);
-
-#if 0 /* Not needed, now that we can always retry without inheritance. */
- /* See if we have more mandatory reloads than spill regs.
- If so, then we cannot risk optimizations that could prevent
- reloads from sharing one spill register.
- Since we will try finding a better register than reload_reg_rtx
- unless it is equal to reload_in or reload_out, count such reloads. */
+ CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
- {
- int tem = 0;
- for (j = 0; j < n_reloads; j++)
- if (! reload_optional[j]
- && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j])
- && (reload_reg_rtx[j] == 0
- || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j])
- && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j]))))
- tem++;
- if (tem > n_spills)
- must_reuse = 1;
- }
-#endif
+ for (i = 0; i < n_reloads; i++)
+ /* If we have already decided to use a certain register,
+ don't use it in another way. */
+ if (rld[i].reg_rtx)
+ mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
+ rld[i].when_needed, rld[i].mode);
+}
+
+/* Assign hard reg targets for the pseudo-registers we must reload
+ into hard regs for this insn.
+ Also output the instructions to copy them in and out of the hard regs.
+
+ For machines with register classes, we are responsible for
+ finding a reload reg in the proper class. */
+
+static void
+choose_reload_regs (chain)
+ struct insn_chain *chain;
+{
+ rtx insn = chain->insn;
+ register int i, j;
+ int max_group_size = 1;
+ enum reg_class group_class = NO_REGS;
+ int inheritance;
+ int pass;
+
+ rtx save_reload_reg_rtx[MAX_RELOADS];
/* In order to be certain of getting the registers we need,
we must sort the reloads into order of increasing register class.
reload_order[j] = j;
reload_spill_index[j] = -1;
- reload_mode[j]
- = (reload_inmode[j] == VOIDmode
- || (GET_MODE_SIZE (reload_outmode[j])
- > GET_MODE_SIZE (reload_inmode[j])))
- ? reload_outmode[j] : reload_inmode[j];
-
- reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]);
-
- if (reload_nregs[j] > 1)
+ if (rld[j].nregs > 1)
{
- max_group_size = MAX (reload_nregs[j], max_group_size);
- group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class];
+ max_group_size = MAX (rld[j].nregs, max_group_size);
+ group_class = reg_class_superunion[(int)rld[j].class][(int)group_class];
}
- /* If we have already decided to use a certain register,
- don't use it in another way. */
- if (reload_reg_rtx[j])
- mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j],
- reload_when_needed[j], reload_mode[j]);
+ save_reload_reg_rtx[j] = rld[j].reg_rtx;
}
if (n_reloads > 1)
qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
- bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx,
- sizeof reload_reg_rtx);
- bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited);
- bcopy ((char *) reload_inheritance_insn,
- (char *) save_reload_inheritance_insn,
- sizeof reload_inheritance_insn);
- bcopy ((char *) reload_override_in, (char *) save_reload_override_in,
- sizeof reload_override_in);
- bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index,
- sizeof reload_spill_index);
- COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used);
- COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all);
- COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr,
- reload_reg_used_in_op_addr);
-
- COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload,
- reload_reg_used_in_op_addr_reload);
-
- COPY_HARD_REG_SET (save_reload_reg_used_in_insn,
- reload_reg_used_in_insn);
- COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr,
- reload_reg_used_in_other_addr);
-
- for (i = 0; i < reload_n_operands; i++)
- {
- COPY_HARD_REG_SET (save_reload_reg_used_in_output[i],
- reload_reg_used_in_output[i]);
- COPY_HARD_REG_SET (save_reload_reg_used_in_input[i],
- reload_reg_used_in_input[i]);
- COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i],
- reload_reg_used_in_input_addr[i]);
- COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i],
- reload_reg_used_in_inpaddr_addr[i]);
- COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i],
- reload_reg_used_in_output_addr[i]);
- COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i],
- reload_reg_used_in_outaddr_addr[i]);
- }
-
/* If -O, try first with inheritance, then turning it off.
If not -O, don't do inheritance.
Using inheritance when not optimizing leads to paradoxes
for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
{
+ choose_reload_regs_init (chain, save_reload_reg_rtx);
+
/* Process the reloads in order of preference just found.
Beyond this point, subregs can be found in reload_reg_rtx.
Then make a second pass over the reloads to allocate any reloads
that haven't been given registers yet. */
- CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
-
for (j = 0; j < n_reloads; j++)
{
register int r = reload_order[j];
+ rtx search_equiv = NULL_RTX;
/* Ignore reloads that got marked inoperative. */
- if (reload_out[r] == 0 && reload_in[r] == 0
- && ! reload_secondary_p[r])
+ if (rld[r].out == 0 && rld[r].in == 0
+ && ! rld[r].secondary_p)
continue;
/* If find_reloads chose to use reload_in or reload_out as a reload
found one since we might save an insn if we find the value lying
around.
Try also when reload_in is a pseudo without a hard reg. */
- if (reload_in[r] != 0 && reload_reg_rtx[r] != 0
- && (rtx_equal_p (reload_in[r], reload_reg_rtx[r])
- || (rtx_equal_p (reload_out[r], reload_reg_rtx[r])
- && GET_CODE (reload_in[r]) != MEM
- && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER)))
+ if (rld[r].in != 0 && rld[r].reg_rtx != 0
+ && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
+ || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
+ && GET_CODE (rld[r].in) != MEM
+ && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
continue;
#if 0 /* No longer needed for correct operation.
until we are sure that any non-optional reloads have been allocated.
The following code takes advantage of the fact that optional reloads
are at the end of reload_order. */
- if (reload_optional[r] != 0)
+ if (rld[r].optional != 0)
for (i = 0; i < j; i++)
- if ((reload_out[reload_order[i]] != 0
- || reload_in[reload_order[i]] != 0
- || reload_secondary_p[reload_order[i]])
- && ! reload_optional[reload_order[i]]
- && reload_reg_rtx[reload_order[i]] == 0)
+ if ((rld[reload_order[i]].out != 0
+ || rld[reload_order[i]].in != 0
+ || rld[reload_order[i]].secondary_p)
+ && ! rld[reload_order[i]].optional
+ && rld[reload_order[i]].reg_rtx == 0)
allocate_reload_reg (chain, reload_order[i], 0, inheritance);
#endif
{
int word = 0;
register int regno = -1;
- enum machine_mode mode;
+ enum machine_mode mode = VOIDmode;
- if (reload_in[r] == 0)
+ if (rld[r].in == 0)
;
- else if (GET_CODE (reload_in[r]) == REG)
+ else if (GET_CODE (rld[r].in) == REG)
{
- regno = REGNO (reload_in[r]);
- mode = GET_MODE (reload_in[r]);
+ regno = REGNO (rld[r].in);
+ mode = GET_MODE (rld[r].in);
}
- else if (GET_CODE (reload_in_reg[r]) == REG)
+ else if (GET_CODE (rld[r].in_reg) == REG)
{
- regno = REGNO (reload_in_reg[r]);
- mode = GET_MODE (reload_in_reg[r]);
+ regno = REGNO (rld[r].in_reg);
+ mode = GET_MODE (rld[r].in_reg);
}
- else if (GET_CODE (reload_in_reg[r]) == SUBREG
- && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG)
+ else if (GET_CODE (rld[r].in_reg) == SUBREG
+ && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
{
- word = SUBREG_WORD (reload_in_reg[r]);
- regno = REGNO (SUBREG_REG (reload_in_reg[r]));
+ word = SUBREG_WORD (rld[r].in_reg);
+ regno = REGNO (SUBREG_REG (rld[r].in_reg));
if (regno < FIRST_PSEUDO_REGISTER)
regno += word;
- mode = GET_MODE (reload_in_reg[r]);
+ mode = GET_MODE (rld[r].in_reg);
}
#ifdef AUTO_INC_DEC
- else if ((GET_CODE (reload_in_reg[r]) == PRE_INC
- || GET_CODE (reload_in_reg[r]) == PRE_DEC
- || GET_CODE (reload_in_reg[r]) == POST_INC
- || GET_CODE (reload_in_reg[r]) == POST_DEC)
- && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG)
+ else if ((GET_CODE (rld[r].in_reg) == PRE_INC
+ || GET_CODE (rld[r].in_reg) == PRE_DEC
+ || GET_CODE (rld[r].in_reg) == POST_INC
+ || GET_CODE (rld[r].in_reg) == POST_DEC)
+ && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
{
- regno = REGNO (XEXP (reload_in_reg[r], 0));
- mode = GET_MODE (XEXP (reload_in_reg[r], 0));
- reload_out[r] = reload_in[r];
+ regno = REGNO (XEXP (rld[r].in_reg, 0));
+ mode = GET_MODE (XEXP (rld[r].in_reg, 0));
+ rld[r].out = rld[r].in;
}
#endif
#if 0
/* This won't work, since REGNO can be a pseudo reg number.
Also, it takes much more hair to keep track of all the things
that can invalidate an inherited reload of part of a pseudoreg. */
- else if (GET_CODE (reload_in[r]) == SUBREG
- && GET_CODE (SUBREG_REG (reload_in[r])) == REG)
- regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]);
+ else if (GET_CODE (rld[r].in) == SUBREG
+ && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
+ regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
#endif
if (regno >= 0 && reg_last_reload_reg[regno] != 0)
{
- enum reg_class class = reload_reg_class[r], last_class;
+ enum reg_class class = rld[r].class, last_class;
rtx last_reg = reg_last_reload_reg[regno];
-
+
i = REGNO (last_reg) + word;
last_class = REGNO_REG_CLASS (i);
if ((GET_MODE_SIZE (GET_MODE (last_reg))
>= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD)
&& reg_reloaded_contents[i] == regno
&& TEST_HARD_REG_BIT (reg_reloaded_valid, i)
- && HARD_REGNO_MODE_OK (i, reload_mode[r])
+ && HARD_REGNO_MODE_OK (i, rld[r].mode)
&& (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
/* Even if we can't use this register as a reload
register, we might use it for reload_override_in,
#endif
))
- && (reload_nregs[r] == max_group_size
+ && (rld[r].nregs == max_group_size
|| ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
i))
- && reload_reg_free_for_value_p (i, reload_opnum[r],
- reload_when_needed[r],
- reload_in[r],
+ && reload_reg_free_for_value_p (i, rld[r].opnum,
+ rld[r].when_needed,
+ rld[r].in,
const0_rtx, r, 1))
{
/* If a group is needed, verify that all the subsequent
registers still have their values intact. */
int nr
- = HARD_REGNO_NREGS (i, reload_mode[r]);
+ = HARD_REGNO_NREGS (i, rld[r].mode);
int k;
for (k = 1; k < nr; k++)
if (i1 != n_earlyclobbers
|| ! (reload_reg_free_for_value_p
- (i, reload_opnum[r], reload_when_needed[r],
- reload_in[r], reload_out[r], r, 1))
+ (i, rld[r].opnum, rld[r].when_needed,
+ rld[r].in, rld[r].out, r, 1))
/* Don't use it if we'd clobber a pseudo reg. */
|| (TEST_HARD_REG_BIT (reg_used_in_insn, i)
- && reload_out[r]
+ && rld[r].out
&& ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
+ /* Don't clobber the frame pointer. */
+ || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
/* Don't really use the inherited spill reg
if we need it wider than we've got it. */
- || (GET_MODE_SIZE (reload_mode[r])
+ || (GET_MODE_SIZE (rld[r].mode)
> GET_MODE_SIZE (mode))
- || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
+ || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
i)
/* If find_reloads chose reload_out as reload
register, stay with it - that leaves the
inherited register for subsequent reloads. */
- || (reload_out[r] && reload_reg_rtx[r]
- && rtx_equal_p (reload_out[r],
- reload_reg_rtx[r])))
+ || (rld[r].out && rld[r].reg_rtx
+ && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
{
reload_override_in[r] = last_reg;
reload_inheritance_insn[r]
/* Mark the register as in use for this part of
the insn. */
mark_reload_reg_in_use (i,
- reload_opnum[r],
- reload_when_needed[r],
- reload_mode[r]);
- reload_reg_rtx[r] = last_reg;
+ rld[r].opnum,
+ rld[r].when_needed,
+ rld[r].mode);
+ rld[r].reg_rtx = last_reg;
reload_inherited[r] = 1;
reload_inheritance_insn[r]
= reg_reloaded_insn[i];
/* Here's another way to see if the value is already lying around. */
if (inheritance
- && reload_in[r] != 0
+ && rld[r].in != 0
&& ! reload_inherited[r]
- && reload_out[r] == 0
- && (CONSTANT_P (reload_in[r])
- || GET_CODE (reload_in[r]) == PLUS
- || GET_CODE (reload_in[r]) == REG
- || GET_CODE (reload_in[r]) == MEM)
- && (reload_nregs[r] == max_group_size
- || ! reg_classes_intersect_p (reload_reg_class[r], group_class)))
+ && rld[r].out == 0
+ && (CONSTANT_P (rld[r].in)
+ || GET_CODE (rld[r].in) == PLUS
+ || GET_CODE (rld[r].in) == REG
+ || GET_CODE (rld[r].in) == MEM)
+ && (rld[r].nregs == max_group_size
+ || ! reg_classes_intersect_p (rld[r].class, group_class)))
+ search_equiv = rld[r].in;
+ /* If this is an output reload from a simple move insn, look
+ if an equivalence for the input is available. */
+ else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
+ {
+ rtx set = single_set (insn);
+
+ if (set
+ && rtx_equal_p (rld[r].out, SET_DEST (set))
+ && CONSTANT_P (SET_SRC (set)))
+ search_equiv = SET_SRC (set);
+ }
+
+ if (search_equiv)
{
register rtx equiv
- = find_equiv_reg (reload_in[r], insn, reload_reg_class[r],
- -1, NULL_PTR, 0, reload_mode[r]);
- int regno;
+ = find_equiv_reg (search_equiv, insn, rld[r].class,
+ -1, NULL_PTR, 0, rld[r].mode);
+ int regno = 0;
if (equiv != 0)
{
address and not all machines support SUBREGs
there. */
regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
- equiv = gen_rtx_REG (reload_mode[r], regno);
+ equiv = gen_rtx_REG (rld[r].mode, regno);
}
else
abort ();
and of the desired class. */
if (equiv != 0
&& ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
- && ! reload_reg_free_for_value_p (regno, reload_opnum[r],
- reload_when_needed[r],
- reload_in[r],
- reload_out[r], r, 1))
- || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]],
+ && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
+ rld[r].when_needed,
+ rld[r].in,
+ rld[r].out, r, 1))
+ || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
regno)))
equiv = 0;
- if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r]))
+ if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
equiv = 0;
/* We found a register that contains the value we need.
if (equiv != 0 && regno_clobbered_p (regno, insn))
{
- switch (reload_when_needed[r])
+ switch (rld[r].when_needed)
{
case RELOAD_FOR_OTHER_ADDRESS:
case RELOAD_FOR_INPADDR_ADDRESS:
to load it, and use it as our reload reg. */
if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
{
- int nr = HARD_REGNO_NREGS (regno, reload_mode[r]);
+ int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
int k;
- reload_reg_rtx[r] = equiv;
+ rld[r].reg_rtx = equiv;
reload_inherited[r] = 1;
/* If reg_reloaded_valid is not set for this register,
i = spill_reg_order[regno + k];
if (i >= 0)
{
- mark_reload_reg_in_use (regno, reload_opnum[r],
- reload_when_needed[r],
- reload_mode[r]);
+ mark_reload_reg_in_use (regno, rld[r].opnum,
+ rld[r].when_needed,
+ rld[r].mode);
SET_HARD_REG_BIT (reload_reg_used_for_inherit,
regno + k);
}
/* If we found a register to use already, or if this is an optional
reload, we are done. */
- if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0)
+ if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
continue;
#if 0 /* No longer needed for correct operation. Might or might not
{
int s = reload_order[i];
- if ((reload_in[s] == 0 && reload_out[s] == 0
- && ! reload_secondary_p[s])
- || reload_optional[s])
+ if ((rld[s].in == 0 && rld[s].out == 0
+ && ! rld[s].secondary_p)
+ || rld[s].optional)
continue;
- if ((reload_reg_class[s] != reload_reg_class[r]
- && reg_classes_intersect_p (reload_reg_class[r],
- reload_reg_class[s]))
- || reload_nregs[s] < reload_nregs[r])
- break;
+ if ((rld[s].class != rld[r].class
+ && reg_classes_intersect_p (rld[r].class,
+ rld[s].class))
+ || rld[s].nregs < rld[r].nregs)
+ break;
}
if (i == n_reloads)
register int r = reload_order[j];
/* Ignore reloads that got marked inoperative. */
- if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r])
+ if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
continue;
/* Skip reloads that already have a register allocated or are
optional. */
- if (reload_reg_rtx[r] != 0 || reload_optional[r])
+ if (rld[r].reg_rtx != 0 || rld[r].optional)
continue;
if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance))
break;
/* Loop around and try without any inheritance. */
- /* First undo everything done by the failed attempt
- to allocate with inheritance. */
- bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx,
- sizeof reload_reg_rtx);
- bcopy ((char *) save_reload_inherited, (char *) reload_inherited,
- sizeof reload_inherited);
- bcopy ((char *) save_reload_inheritance_insn,
- (char *) reload_inheritance_insn,
- sizeof reload_inheritance_insn);
- bcopy ((char *) save_reload_override_in, (char *) reload_override_in,
- sizeof reload_override_in);
- bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index,
- sizeof reload_spill_index);
- COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used);
- COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all);
- COPY_HARD_REG_SET (reload_reg_used_in_op_addr,
- save_reload_reg_used_in_op_addr);
- COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload,
- save_reload_reg_used_in_op_addr_reload);
- COPY_HARD_REG_SET (reload_reg_used_in_insn,
- save_reload_reg_used_in_insn);
- COPY_HARD_REG_SET (reload_reg_used_in_other_addr,
- save_reload_reg_used_in_other_addr);
-
- for (i = 0; i < reload_n_operands; i++)
- {
- COPY_HARD_REG_SET (reload_reg_used_in_input[i],
- save_reload_reg_used_in_input[i]);
- COPY_HARD_REG_SET (reload_reg_used_in_output[i],
- save_reload_reg_used_in_output[i]);
- COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i],
- save_reload_reg_used_in_input_addr[i]);
- COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i],
- save_reload_reg_used_in_inpaddr_addr[i]);
- COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i],
- save_reload_reg_used_in_output_addr[i]);
- COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i],
- save_reload_reg_used_in_outaddr_addr[i]);
- }
}
/* If we thought we could inherit a reload, because it seemed that
{
register int r = reload_order[j];
rtx check_reg;
- if (reload_inherited[r] && reload_reg_rtx[r])
- check_reg = reload_reg_rtx[r];
+ if (reload_inherited[r] && rld[r].reg_rtx)
+ check_reg = rld[r].reg_rtx;
else if (reload_override_in[r]
&& (GET_CODE (reload_override_in[r]) == REG
- || GET_CODE (reload_override_in[r]) == SUBREG))
+ || GET_CODE (reload_override_in[r]) == SUBREG))
check_reg = reload_override_in[r];
else
continue;
if (! reload_reg_free_for_value_p (true_regnum (check_reg),
- reload_opnum[r],
- reload_when_needed[r],
- reload_in[r],
- (reload_inherited[r]
- ? reload_out[r] : const0_rtx),
+ rld[r].opnum,
+ rld[r].when_needed,
+ rld[r].in,
+ (reload_inherited[r]
+ ? rld[r].out : const0_rtx),
r, 1))
{
if (pass)
is mentioned in reload_in of the reload we are going to inherit.
A special case are auto_inc expressions; even if the input is
inherited, we still need the address for the output. We can
- recognize them because they have RELOAD_OUT set but not
- RELOAD_OUT_REG.
+ recognize them because they have RELOAD_OUT set to RELOAD_IN.
If we suceeded removing some reload and we are doing a preliminary
pass just to remove such reloads, make another pass, since the
removal of one reload might allow us to inherit another one. */
- else if ((! reload_out[r] || reload_out_reg[r])
- && remove_address_replacements (reload_in[r]) && pass)
+ else if (rld[r].in
+ && rld[r].out != rld[r].in
+ && remove_address_replacements (rld[r].in) && pass)
pass = 2;
}
}
actually override reload_in. */
for (j = 0; j < n_reloads; j++)
if (reload_override_in[j])
- reload_in[j] = reload_override_in[j];
+ rld[j].in = reload_override_in[j];
/* If this reload won't be done because it has been cancelled or is
optional and not inherited, clear reload_reg_rtx so other
routines (such as subst_reloads) don't get confused. */
for (j = 0; j < n_reloads; j++)
- if (reload_reg_rtx[j] != 0
- && ((reload_optional[j] && ! reload_inherited[j])
- || (reload_in[j] == 0 && reload_out[j] == 0
- && ! reload_secondary_p[j])))
+ if (rld[j].reg_rtx != 0
+ && ((rld[j].optional && ! reload_inherited[j])
+ || (rld[j].in == 0 && rld[j].out == 0
+ && ! rld[j].secondary_p)))
{
- int regno = true_regnum (reload_reg_rtx[j]);
+ int regno = true_regnum (rld[j].reg_rtx);
if (spill_reg_order[regno] >= 0)
- clear_reload_reg_in_use (regno, reload_opnum[j],
- reload_when_needed[j], reload_mode[j]);
- reload_reg_rtx[j] = 0;
+ clear_reload_reg_in_use (regno, rld[j].opnum,
+ rld[j].when_needed, rld[j].mode);
+ rld[j].reg_rtx = 0;
}
/* Record which pseudos and which spill regs have output reloads. */
i = reload_spill_index[r];
/* I is nonneg if this reload uses a register.
- If reload_reg_rtx[r] is 0, this is an optional reload
+ If rld[r].reg_rtx is 0, this is an optional reload
that we opted to ignore. */
- if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG
- && reload_reg_rtx[r] != 0)
+ if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
+ && rld[r].reg_rtx != 0)
{
- register int nregno = REGNO (reload_out_reg[r]);
+ register int nregno = REGNO (rld[r].out_reg);
int nr = 1;
if (nregno < FIRST_PSEUDO_REGISTER)
- nr = HARD_REGNO_NREGS (nregno, reload_mode[r]);
+ nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
while (--nr >= 0)
reg_has_output_reload[nregno + nr] = 1;
if (i >= 0)
{
- nr = HARD_REGNO_NREGS (i, reload_mode[r]);
+ nr = HARD_REGNO_NREGS (i, rld[r].mode);
while (--nr >= 0)
SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
}
- if (reload_when_needed[r] != RELOAD_OTHER
- && reload_when_needed[r] != RELOAD_FOR_OUTPUT
- && reload_when_needed[r] != RELOAD_FOR_INSN)
+ if (rld[r].when_needed != RELOAD_OTHER
+ && rld[r].when_needed != RELOAD_FOR_OUTPUT
+ && rld[r].when_needed != RELOAD_FOR_INSN)
abort ();
}
}
{
int regno;
- if (! reload_reg_rtx[r])
+ if (! rld[r].reg_rtx)
return;
- regno = true_regnum (reload_reg_rtx[r]);
- reload_reg_rtx[r] = 0;
+ regno = true_regnum (rld[r].reg_rtx);
+ rld[r].reg_rtx = 0;
if (spill_reg_order[regno] >= 0)
- clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r],
- reload_mode[r]);
+ clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
+ rld[r].mode);
reload_spill_index[r] = -1;
}
\f
/* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
reloads of the same item for fear that we might not have enough reload
registers. However, normally they will get the same reload register
- and hence actually need not be loaded twice.
+ and hence actually need not be loaded twice.
Here we check for the most common case of this phenomenon: when we have
a number of reloads for the same object, each of which were allocated
int max_input_address_opnum = -1;
int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
- if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER
- || reload_out[i] != 0 || reload_reg_rtx[i] == 0
- || reg_set_p (reload_reg_rtx[i], insn))
+ if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
+ || rld[i].out != 0 || rld[i].reg_rtx == 0
+ || reg_set_p (rld[i].reg_rtx, insn))
continue;
/* Look at all other reloads. Ensure that the only use of this
for (j = 0; j < n_reloads; j++)
{
- if (i == j || reload_reg_rtx[j] == 0
- || ! reg_overlap_mentioned_p (reload_reg_rtx[j],
- reload_reg_rtx[i]))
+ if (i == j || rld[j].reg_rtx == 0
+ || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
+ rld[i].reg_rtx))
continue;
- if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
- && reload_opnum[j] > max_input_address_opnum)
- max_input_address_opnum = reload_opnum[j];
+ if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
+ && rld[j].opnum > max_input_address_opnum)
+ max_input_address_opnum = rld[j].opnum;
/* If the reload regs aren't exactly the same (e.g, different modes)
or if the values are different, we can't merge this reload.
But if it is an input reload, we might still merge
RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
- if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
- || reload_out[j] != 0 || reload_in[j] == 0
- || ! rtx_equal_p (reload_in[i], reload_in[j]))
+ if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
+ || rld[j].out != 0 || rld[j].in == 0
+ || ! rtx_equal_p (rld[i].in, rld[j].in))
{
- if (reload_when_needed[j] != RELOAD_FOR_INPUT
- || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS
- || reload_opnum[i] > reload_opnum[j])
- && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS))
+ if (rld[j].when_needed != RELOAD_FOR_INPUT
+ || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
+ || rld[i].opnum > rld[j].opnum)
+ && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
break;
conflicting_input = 1;
- if (min_conflicting_input_opnum > reload_opnum[j])
- min_conflicting_input_opnum = reload_opnum[j];
+ if (min_conflicting_input_opnum > rld[j].opnum)
+ min_conflicting_input_opnum = rld[j].opnum;
}
}
&& max_input_address_opnum <= min_conflicting_input_opnum)
{
for (j = 0; j < n_reloads; j++)
- if (i != j && reload_reg_rtx[j] != 0
- && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j])
+ if (i != j && rld[j].reg_rtx != 0
+ && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
&& (! conflicting_input
- || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS
- || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS))
+ || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
+ || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
{
- reload_when_needed[i] = RELOAD_OTHER;
- reload_in[j] = 0;
+ rld[i].when_needed = RELOAD_OTHER;
+ rld[j].in = 0;
reload_spill_index[j] = -1;
transfer_replacements (i, j);
}
this test is equivalent to looking for reloads for this operand
number. */
- if (reload_when_needed[i] == RELOAD_OTHER)
+ if (rld[i].when_needed == RELOAD_OTHER)
for (j = 0; j < n_reloads; j++)
- if (reload_in[j] != 0
- && reload_when_needed[i] != RELOAD_OTHER
- && reg_overlap_mentioned_for_reload_p (reload_in[j],
- reload_in[i]))
- reload_when_needed[j]
- = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS
- || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS)
+ if (rld[j].in != 0
+ && rld[i].when_needed != RELOAD_OTHER
+ && reg_overlap_mentioned_for_reload_p (rld[j].in,
+ rld[i].in))
+ rld[j].when_needed
+ = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
+ || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
}
}
-}
+}
\f
/* Output insns to reload values in and out of the chosen reload regs. */
rtx this_reload_insn = 0;
int expect_occurrences = 1;
- if (reload_reg_rtx[j]
- && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
- new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0;
+ if (rld[j].reg_rtx
+ && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
+ new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
- old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM
- ? reload_in_reg[j] : reload_in[j]);
+ old = (rld[j].in && GET_CODE (rld[j].in) == MEM
+ ? rld[j].in_reg : rld[j].in);
if (old != 0
/* AUTO_INC reloads need to be handled even if inherited. We got an
AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
- && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j]))
- && ! rtx_equal_p (reload_reg_rtx[j], old)
- && reload_reg_rtx[j] != 0)
+ && (! reload_inherited[j] || (rld[j].out && ! rld[j].out_reg))
+ && ! rtx_equal_p (rld[j].reg_rtx, old)
+ && rld[j].reg_rtx != 0)
{
- register rtx reloadreg = reload_reg_rtx[j];
+ register rtx reloadreg = rld[j].reg_rtx;
rtx oldequiv = 0;
enum machine_mode mode;
rtx *where;
/* Determine the mode to reload in.
This is very tricky because we have three to choose from.
- There is the mode the insn operand wants (reload_inmode[J]).
+ There is the mode the insn operand wants (rld[J].inmode).
There is the mode of the reload register RELOADREG.
There is the intrinsic mode of the operand, which we could find
by stripping some SUBREGs.
mode = GET_MODE (old);
if (mode == VOIDmode)
- mode = reload_inmode[j];
+ mode = rld[j].inmode;
#ifdef SECONDARY_INPUT_RELOAD_CLASS
/* If we need a secondary register for this operation, see if
do this if the secondary register will be used as a scratch
register. */
- if (reload_secondary_in_reload[j] >= 0
- && reload_secondary_in_icode[j] == CODE_FOR_nothing
+ if (rld[j].secondary_in_reload >= 0
+ && rld[j].secondary_in_icode == CODE_FOR_nothing
&& optimize)
oldequiv
= find_equiv_reg (old, insn,
- reload_reg_class[reload_secondary_in_reload[j]],
+ rld[rld[j].secondary_in_reload].class,
-1, NULL_PTR, 0, mode);
#endif
/* Don't use OLDEQUIV if any other reload changes it at an
earlier stage of this insn or at this stage. */
- if (! reload_reg_free_for_value_p (regno, reload_opnum[j],
- reload_when_needed[j],
- reload_in[j], const0_rtx, j,
+ if (! reload_reg_free_for_value_p (regno, rld[j].opnum,
+ rld[j].when_needed,
+ rld[j].in, const0_rtx, j,
0))
oldequiv = 0;
or memory. */
if (oldequiv != 0
- && ((REGNO_REG_CLASS (regno) != reload_reg_class[j]
+ && ((REGNO_REG_CLASS (regno) != rld[j].class
&& (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
- reload_reg_class[j])
- >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1)))
+ rld[j].class)
+ >= MEMORY_MOVE_COST (mode, rld[j].class, 1)))
#ifdef SECONDARY_INPUT_RELOAD_CLASS
- || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
+ || (SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
mode, oldequiv)
!= NO_REGS)
#endif
#ifdef SECONDARY_MEMORY_NEEDED
|| SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
- reload_reg_class[j],
+ rld[j].class,
mode)
#endif
))
find the pseudo in RELOAD_IN_REG. */
if (oldequiv == 0
&& reload_override_in[j]
- && GET_CODE (reload_in_reg[j]) == REG)
+ && GET_CODE (rld[j].in_reg) == REG)
{
oldequiv = old;
- old = reload_in_reg[j];
+ old = rld[j].in_reg;
}
if (oldequiv == 0)
oldequiv = old;
&& GET_CODE (old) == REG
&& (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
|| rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
- reload_out_reg[j])))
+ rld[j].out_reg)))
delete_output_reload (insn, j, REGNO (oldequiv));
/* Encapsulate both RELOADREG and OLDEQUIV into that mode,
oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
/* Switch to the right place to emit the reload insns. */
- switch (reload_when_needed[j])
+ switch (rld[j].when_needed)
{
case RELOAD_OTHER:
where = &other_input_reload_insns;
break;
case RELOAD_FOR_INPUT:
- where = &input_reload_insns[reload_opnum[j]];
+ where = &input_reload_insns[rld[j].opnum];
break;
case RELOAD_FOR_INPUT_ADDRESS:
- where = &input_address_reload_insns[reload_opnum[j]];
+ where = &input_address_reload_insns[rld[j].opnum];
break;
case RELOAD_FOR_INPADDR_ADDRESS:
- where = &inpaddr_address_reload_insns[reload_opnum[j]];
+ where = &inpaddr_address_reload_insns[rld[j].opnum];
break;
case RELOAD_FOR_OUTPUT_ADDRESS:
- where = &output_address_reload_insns[reload_opnum[j]];
+ where = &output_address_reload_insns[rld[j].opnum];
break;
case RELOAD_FOR_OUTADDR_ADDRESS:
- where = &outaddr_address_reload_insns[reload_opnum[j]];
+ where = &outaddr_address_reload_insns[rld[j].opnum];
break;
case RELOAD_FOR_OPERAND_ADDRESS:
where = &operand_reload_insns;
special = 0;
/* Auto-increment addresses must be reloaded in a special way. */
- if (reload_out[j] && ! reload_out_reg[j])
+ if (rld[j].out && ! rld[j].out_reg)
{
/* We are not going to bother supporting the case where a
incremented register can't be copied directly from
OLDEQUIV since this seems highly unlikely. */
- if (reload_secondary_in_reload[j] >= 0)
+ if (rld[j].secondary_in_reload >= 0)
abort ();
if (reload_inherited[j])
oldequiv = reloadreg;
- old = XEXP (reload_in_reg[j], 0);
+ old = XEXP (rld[j].in_reg, 0);
if (optimize && GET_CODE (oldequiv) == REG
&& REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
special = 1;
/* Output a special code sequence for this case. */
new_spill_reg_store[REGNO (reloadreg)]
- = inc_for_reload (reloadreg, oldequiv, reload_out[j],
- reload_inc[j]);
+ = inc_for_reload (reloadreg, oldequiv, rld[j].out,
+ rld[j].inc);
}
/* If we are reloading a pseudo-register that was set by the previous
/* This is unsafe if some other reload
uses the same reg first. */
&& reload_reg_free_for_value_p (REGNO (reloadreg),
- reload_opnum[j],
- reload_when_needed[j],
- old, reload_out[j],
+ rld[j].opnum,
+ rld[j].when_needed,
+ old, rld[j].out,
j, 0))
{
rtx temp = PREV_INSN (insn);
/* Make sure we can access insn_operand_constraint. */
&& asm_noperands (PATTERN (temp)) < 0
/* This is unsafe if prev insn rejects our reload reg. */
- && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0],
+ && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
reloadreg)
/* This is unsafe if operand occurs more than once in current
insn. Perhaps some occurrences aren't reloaded. */
if (REG_N_DEATHS (REGNO (old)) == 1
&& REG_N_SETS (REGNO (old)) == 1)
{
- reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]);
+ reg_renumber[REGNO (old)] = REGNO (rld[j].reg_rtx);
alter_reg (REGNO (old), -1);
}
special = 1;
because we don't make such reloads when both the input and
output need secondary reload registers. */
- if (reload_secondary_in_reload[j] >= 0)
+ if (rld[j].secondary_in_reload >= 0)
{
- int secondary_reload = reload_secondary_in_reload[j];
+ int secondary_reload = rld[j].secondary_in_reload;
rtx real_oldequiv = oldequiv;
rtx real_old = old;
+ rtx tmp;
/* If OLDEQUIV is a pseudo with a MEM, get the real MEM
and similarly for OLD.
See comments in get_secondary_reload in reload.c. */
/* If it is a pseudo that cannot be replaced with its
equivalent MEM, we must fall back to reload_in, which
- will have all the necessary substitutions registered. */
-
- if (GET_CODE (oldequiv) == REG
- && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
- && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
+ will have all the necessary substitutions registered.
+ Likewise for a pseudo that can't be replaced with its
+ equivalent constant.
+
+ Take extra care for subregs of such pseudos. Note that
+ we cannot use reg_equiv_mem in this case because it is
+ not in the right mode. */
+
+ tmp = oldequiv;
+ if (GET_CODE (tmp) == SUBREG)
+ tmp = SUBREG_REG (tmp);
+ if (GET_CODE (tmp) == REG
+ && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
+ && (reg_equiv_memory_loc[REGNO (tmp)] != 0
+ || reg_equiv_constant[REGNO (tmp)] != 0))
{
- if (reg_equiv_address[REGNO (oldequiv)]
- || num_not_at_initial_offset)
- real_oldequiv = reload_in[j];
+ if (! reg_equiv_mem[REGNO (tmp)]
+ || num_not_at_initial_offset
+ || GET_CODE (oldequiv) == SUBREG)
+ real_oldequiv = rld[j].in;
else
- real_oldequiv = reg_equiv_mem[REGNO (oldequiv)];
+ real_oldequiv = reg_equiv_mem[REGNO (tmp)];
}
- if (GET_CODE (old) == REG
- && REGNO (old) >= FIRST_PSEUDO_REGISTER
- && reg_equiv_memory_loc[REGNO (old)] != 0)
+ tmp = old;
+ if (GET_CODE (tmp) == SUBREG)
+ tmp = SUBREG_REG (tmp);
+ if (GET_CODE (tmp) == REG
+ && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
+ && (reg_equiv_memory_loc[REGNO (tmp)] != 0
+ || reg_equiv_constant[REGNO (tmp)] != 0))
{
- if (reg_equiv_address[REGNO (old)]
- || num_not_at_initial_offset)
- real_old = reload_in[j];
+ if (! reg_equiv_mem[REGNO (tmp)]
+ || num_not_at_initial_offset
+ || GET_CODE (old) == SUBREG)
+ real_old = rld[j].in;
else
- real_old = reg_equiv_mem[REGNO (old)];
+ real_old = reg_equiv_mem[REGNO (tmp)];
}
- second_reload_reg = reload_reg_rtx[secondary_reload];
- icode = reload_secondary_in_icode[j];
+ second_reload_reg = rld[secondary_reload].reg_rtx;
+ icode = rld[j].secondary_in_icode;
if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
- || (reload_in[j] != 0 && reload_out[j] != 0))
+ || (rld[j].in != 0 && rld[j].out != 0))
{
enum reg_class new_class
- = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j],
+ = SECONDARY_INPUT_RELOAD_CLASS (rld[j].class,
mode, real_oldequiv);
if (new_class == NO_REGS)
{
new_icode = reload_in_optab[(int) mode];
if (new_icode != CODE_FOR_nothing
- && ((insn_operand_predicate[(int) new_icode][0]
- && ! ((*insn_operand_predicate[(int) new_icode][0])
+ && ((insn_data[(int) new_icode].operand[0].predicate
+ && ! ((*insn_data[(int) new_icode].operand[0].predicate)
(reloadreg, mode)))
- || (insn_operand_predicate[(int) new_icode][1]
- && ! ((*insn_operand_predicate[(int) new_icode][1])
+ || (insn_data[(int) new_icode].operand[1].predicate
+ && ! ((*insn_data[(int) new_icode].operand[1].predicate)
(real_oldequiv, mode)))))
new_icode = CODE_FOR_nothing;
if (new_icode == CODE_FOR_nothing)
new_mode = mode;
else
- new_mode = insn_operand_mode[(int) new_icode][2];
+ new_mode = insn_data[(int) new_icode].operand[2].mode;
if (GET_MODE (second_reload_reg) != new_mode)
{
to see if it is being used as a scratch or intermediate
register and generate code appropriately. If we need
a scratch register, use REAL_OLDEQUIV since the form of
- the insn may depend on the actual address if it is
+ the insn may depend on the actual address if it is
a MEM. */
if (second_reload_reg)
/* See if we need a scratch register to load the
intermediate register (a tertiary reload). */
enum insn_code tertiary_icode
- = reload_secondary_in_icode[secondary_reload];
+ = rld[secondary_reload].secondary_in_icode;
if (tertiary_icode != CODE_FOR_nothing)
{
rtx third_reload_reg
- = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]];
+ = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
emit_insn ((GEN_FCN (tertiary_icode)
(second_reload_reg, real_oldequiv,
}
else
gen_reload (second_reload_reg, real_oldequiv,
- reload_opnum[j],
- reload_when_needed[j]);
+ rld[j].opnum,
+ rld[j].when_needed);
oldequiv = second_reload_reg;
}
if ((GET_CODE (oldequiv) == REG
&& REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
- && reg_equiv_memory_loc[REGNO (oldequiv)] != 0)
+ && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
+ || reg_equiv_constant[REGNO (oldequiv)] != 0))
|| (GET_CODE (oldequiv) == SUBREG
&& GET_CODE (SUBREG_REG (oldequiv)) == REG
&& (REGNO (SUBREG_REG (oldequiv))
>= FIRST_PSEUDO_REGISTER)
- && (reg_equiv_memory_loc
- [REGNO (SUBREG_REG (oldequiv))] != 0)))
- real_oldequiv = reload_in[j];
- gen_reload (reloadreg, real_oldequiv, reload_opnum[j],
- reload_when_needed[j]);
+ && ((reg_equiv_memory_loc
+ [REGNO (SUBREG_REG (oldequiv))] != 0)
+ || (reg_equiv_constant
+ [REGNO (SUBREG_REG (oldequiv))] != 0))))
+ real_oldequiv = rld[j].in;
+ gen_reload (reloadreg, real_oldequiv, rld[j].opnum,
+ rld[j].when_needed);
}
}
reload_override_in[j] = oldequiv;
}
- /* When inheriting a wider reload, we have a MEM in reload_in[j],
+ /* When inheriting a wider reload, we have a MEM in rld[j].in,
e.g. inheriting a SImode output reload for
(mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
- if (optimize && reload_inherited[j] && reload_in[j]
- && GET_CODE (reload_in[j]) == MEM
- && GET_CODE (reload_in_reg[j]) == MEM
+ if (optimize && reload_inherited[j] && rld[j].in
+ && GET_CODE (rld[j].in) == MEM
+ && GET_CODE (rld[j].in_reg) == MEM
&& reload_spill_index[j] >= 0
&& TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
{
expect_occurrences
- = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1;
- reload_in[j]
+ = count_occurrences (PATTERN (insn), rld[j].in) == 1 ? 0 : -1;
+ rld[j].in
= regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
}
if (optimize
&& (reload_inherited[j] || reload_override_in[j])
- && reload_reg_rtx[j]
- && GET_CODE (reload_reg_rtx[j]) == REG
- && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0
+ && rld[j].reg_rtx
+ && GET_CODE (rld[j].reg_rtx) == REG
+ && spill_reg_store[REGNO (rld[j].reg_rtx)] != 0
#if 0
/* There doesn't seem to be any reason to restrict this to pseudos
and doing so loses in the case where we are copying from a
register of the wrong class. */
- && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
- >= FIRST_PSEUDO_REGISTER
+ && (REGNO (spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
+ >= FIRST_PSEUDO_REGISTER)
#endif
- /* The insn might have already some references to stackslots
- replaced by MEMs, while reload_out_reg still names the
- original pseudo. */
+ /* The insn might have already some references to stackslots
+ replaced by MEMs, while reload_out_reg still names the
+ original pseudo. */
&& (dead_or_set_p (insn,
- spill_reg_stored_to[REGNO (reload_reg_rtx[j])])
- || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])],
- reload_out_reg[j])))
- delete_output_reload (insn, j, REGNO (reload_reg_rtx[j]));
+ spill_reg_stored_to[REGNO (rld[j].reg_rtx)])
+ || rtx_equal_p (spill_reg_stored_to[REGNO (rld[j].reg_rtx)],
+ rld[j].out_reg)))
+ delete_output_reload (insn, j, REGNO (rld[j].reg_rtx));
/* Input-reloading is done. Now do output-reloading,
storing the value from the reload-register after the main insn
- if reload_out[j] is nonzero.
+ if rld[j].out is nonzero.
??? At some point we need to support handling output reloads of
JUMP_INSNs or insns that set cc0. */
not loaded in this same reload, see if we can eliminate a previous
store. */
{
- rtx pseudo = reload_out_reg[j];
-
+ rtx pseudo = rld[j].out_reg;
+
if (pseudo
&& GET_CODE (pseudo) == REG
- && ! rtx_equal_p (reload_in_reg[j], pseudo)
+ && ! rtx_equal_p (rld[j].in_reg, pseudo)
&& REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
&& reg_last_reload_reg[REGNO (pseudo)])
{
}
}
- old = reload_out_reg[j];
+ old = rld[j].out_reg;
if (old != 0
- && reload_reg_rtx[j] != old
- && reload_reg_rtx[j] != 0)
+ && rld[j].reg_rtx != old
+ && rld[j].reg_rtx != 0)
{
- register rtx reloadreg = reload_reg_rtx[j];
+ register rtx reloadreg = rld[j].reg_rtx;
#ifdef SECONDARY_OUTPUT_RELOAD_CLASS
register rtx second_reloadreg = 0;
#endif
if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
&& (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
{
- XEXP (note, 0) = reload_reg_rtx[j];
+ XEXP (note, 0) = rld[j].reg_rtx;
continue;
}
/* Likewise for a SUBREG of an operand that dies. */
SUBREG_REG (old))))
{
XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
- reload_reg_rtx[j]);
+ rld[j].reg_rtx);
continue;
}
else if (GET_CODE (old) == SCRATCH)
if (GET_CODE (insn) == JUMP_INSN)
abort ();
- if (reload_when_needed[j] == RELOAD_OTHER)
+ if (rld[j].when_needed == RELOAD_OTHER)
start_sequence ();
else
- push_to_sequence (output_reload_insns[reload_opnum[j]]);
+ push_to_sequence (output_reload_insns[rld[j].opnum]);
- old = reload_out[j];
+ old = rld[j].out;
/* Determine the mode to reload in.
See comments above (for input reloading). */
one, since it will be stored into OLD. We might need a secondary
register only for an input reload, so check again here. */
- if (reload_secondary_out_reload[j] >= 0)
+ if (rld[j].secondary_out_reload >= 0)
{
rtx real_old = old;
&& reg_equiv_mem[REGNO (old)] != 0)
real_old = reg_equiv_mem[REGNO (old)];
- if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j],
+ if((SECONDARY_OUTPUT_RELOAD_CLASS (rld[j].class,
mode, real_old)
!= NO_REGS))
{
second_reloadreg = reloadreg;
- reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]];
+ reloadreg = rld[rld[j].secondary_out_reload].reg_rtx;
/* See if RELOADREG is to be used as a scratch register
or as an intermediate register. */
- if (reload_secondary_out_icode[j] != CODE_FOR_nothing)
+ if (rld[j].secondary_out_icode != CODE_FOR_nothing)
{
- emit_insn ((GEN_FCN (reload_secondary_out_icode[j])
+ emit_insn ((GEN_FCN (rld[j].secondary_out_icode)
(real_old, second_reloadreg, reloadreg)));
special = 1;
}
/* See if we need both a scratch and intermediate reload
register. */
- int secondary_reload = reload_secondary_out_reload[j];
+ int secondary_reload = rld[j].secondary_out_reload;
enum insn_code tertiary_icode
- = reload_secondary_out_icode[secondary_reload];
+ = rld[secondary_reload].secondary_out_icode;
if (GET_MODE (reloadreg) != mode)
reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
if (tertiary_icode != CODE_FOR_nothing)
{
rtx third_reloadreg
- = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]];
+ = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
rtx tem;
/* Copy primary reload reg to secondary reload reg.
real_old = SUBREG_REG (real_old), reloadreg = tem;
gen_reload (reloadreg, second_reloadreg,
- reload_opnum[j], reload_when_needed[j]);
+ rld[j].opnum, rld[j].when_needed);
emit_insn ((GEN_FCN (tertiary_icode)
(real_old, reloadreg, third_reloadreg)));
special = 1;
OUT later. */
gen_reload (reloadreg, second_reloadreg,
- reload_opnum[j], reload_when_needed[j]);
+ rld[j].opnum, rld[j].when_needed);
}
}
}
|| rtx_equal_p (old, SET_DEST (set))
|| !reg_mentioned_p (old, SET_SRC (set))
|| !regno_clobbered_p (REGNO (old), insn))
- gen_reload (old, reloadreg, reload_opnum[j],
- reload_when_needed[j]);
+ gen_reload (old, reloadreg, rld[j].opnum,
+ rld[j].when_needed);
}
/* Look at all insns we emitted, just to be safe. */
clear any memory of reloaded copies of the pseudo reg.
If this output reload comes from a spill reg,
reg_has_output_reload will make this do nothing. */
- note_stores (pat, forget_old_reloads_1);
+ note_stores (pat, forget_old_reloads_1, NULL);
- if (reg_mentioned_p (reload_reg_rtx[j], pat))
+ if (reg_mentioned_p (rld[j].reg_rtx, pat))
{
rtx set = single_set (insn);
if (reload_spill_index[j] < 0
&& set
- && SET_SRC (set) == reload_reg_rtx[j])
+ && SET_SRC (set) == rld[j].reg_rtx)
{
int src = REGNO (SET_SRC (set));
if (find_regno_note (insn, REG_DEAD, src))
SET_HARD_REG_BIT (reg_reloaded_died, src);
}
- if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER)
+ if (REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
{
- int s = reload_secondary_out_reload[j];
+ int s = rld[j].secondary_out_reload;
set = single_set (p);
/* If this reload copies only to the secondary reload
register, the secondary reload does the actual
has and where the actual store to the pseudo is
made; leave new_spill_reg_store alone. */
else if (s >= 0
- && SET_SRC (set) == reload_reg_rtx[j]
- && SET_DEST (set) == reload_reg_rtx[s])
+ && SET_SRC (set) == rld[j].reg_rtx
+ && SET_DEST (set) == rld[s].reg_rtx)
{
/* Usually the next instruction will be the
secondary reload insn; if we can confirm
that it is, setting new_spill_reg_store to
that insn will allow an extra optimization. */
- rtx s_reg = reload_reg_rtx[s];
+ rtx s_reg = rld[s].reg_rtx;
rtx next = NEXT_INSN (p);
- reload_out[s] = reload_out[j];
- reload_out_reg[s] = reload_out_reg[j];
+ rld[s].out = rld[j].out;
+ rld[s].out_reg = rld[j].out_reg;
set = single_set (next);
if (set && SET_SRC (set) == s_reg
&& ! new_spill_reg_store[REGNO (s_reg)])
}
}
else
- new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p;
+ new_spill_reg_store[REGNO (rld[j].reg_rtx)] = p;
}
}
}
- if (reload_when_needed[j] == RELOAD_OTHER)
+ if (rld[j].when_needed == RELOAD_OTHER)
{
- emit_insns (other_output_reload_insns[reload_opnum[j]]);
- other_output_reload_insns[reload_opnum[j]] = get_insns ();
+ emit_insns (other_output_reload_insns[rld[j].opnum]);
+ other_output_reload_insns[rld[j].opnum] = get_insns ();
}
else
- output_reload_insns[reload_opnum[j]] = get_insns ();
+ output_reload_insns[rld[j].opnum] = get_insns ();
end_sequence ();
}
if (n_basic_blocks)
{
if (BLOCK_HEAD (chain->block) == insn)
- BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
+ BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
if (BLOCK_END (chain->block) == insn)
- BLOCK_END (chain->block) = PREV_INSN (following_insn);
+ BLOCK_END (chain->block) = PREV_INSN (following_insn);
}
/* For all the spill regs newly reloaded in this instruction,
register int i = reload_spill_index[r];
/* If this is a non-inherited input reload from a pseudo, we must
- clear any memory of a previous store to the same pseudo. Only do
- something if there will not be an output reload for the pseudo
- being reloaded. */
- if (reload_in_reg[r] != 0
- && ! (reload_inherited[r] || reload_override_in[r]))
- {
- rtx reg = reload_in_reg[r];
-
- if (GET_CODE (reg) == SUBREG)
+ clear any memory of a previous store to the same pseudo. Only do
+ something if there will not be an output reload for the pseudo
+ being reloaded. */
+ if (rld[r].in_reg != 0
+ && ! (reload_inherited[r] || reload_override_in[r]))
+ {
+ rtx reg = rld[r].in_reg;
+
+ if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
-
- if (GET_CODE (reg) == REG
+
+ if (GET_CODE (reg) == REG
&& REGNO (reg) >= FIRST_PSEUDO_REGISTER
&& ! reg_has_output_reload[REGNO (reg)])
{
int nregno = REGNO (reg);
if (reg_last_reload_reg[nregno])
- {
- int last_regno = REGNO (reg_last_reload_reg[nregno]);
+ {
+ int last_regno = REGNO (reg_last_reload_reg[nregno]);
- if (reg_reloaded_contents[last_regno] == nregno)
+ if (reg_reloaded_contents[last_regno] == nregno)
spill_reg_store[last_regno] = 0;
- }
+ }
}
}
-
+
/* I is nonneg if this reload used a register.
- If reload_reg_rtx[r] is 0, this is an optional reload
+ If rld[r].reg_rtx is 0, this is an optional reload
that we opted to ignore. */
- if (i >= 0 && reload_reg_rtx[r] != 0)
+ if (i >= 0 && rld[r].reg_rtx != 0)
{
int nr
- = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r]));
+ = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
int k;
int part_reaches_end = 0;
int all_reaches_end = 1;
of the value lives to the end. */
for (k = 0; k < nr; k++)
{
- if (reload_reg_reaches_end_p (i + k, reload_opnum[r],
- reload_when_needed[r]))
+ if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
+ rld[r].when_needed))
part_reaches_end = 1;
else
all_reaches_end = 0;
CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
/* Maybe the spill reg contains a copy of reload_out. */
- if (reload_out[r] != 0
- && (GET_CODE (reload_out[r]) == REG
+ if (rld[r].out != 0
+ && (GET_CODE (rld[r].out) == REG
#ifdef AUTO_INC_DEC
- || ! reload_out_reg[r]
+ || ! rld[r].out_reg
#endif
- || GET_CODE (reload_out_reg[r]) == REG))
+ || GET_CODE (rld[r].out_reg) == REG))
{
- rtx out = (GET_CODE (reload_out[r]) == REG
- ? reload_out[r]
- : reload_out_reg[r]
- ? reload_out_reg[r]
-/* AUTO_INC */ : XEXP (reload_in_reg[r], 0));
+ rtx out = (GET_CODE (rld[r].out) == REG
+ ? rld[r].out
+ : rld[r].out_reg
+ ? rld[r].out_reg
+/* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
register int nregno = REGNO (out);
int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
: HARD_REGNO_NREGS (nregno,
- GET_MODE (reload_reg_rtx[r])));
+ GET_MODE (rld[r].reg_rtx)));
spill_reg_store[i] = new_spill_reg_store[i];
spill_reg_stored_to[i] = out;
- reg_last_reload_reg[nregno] = reload_reg_rtx[r];
+ reg_last_reload_reg[nregno] = rld[r].reg_rtx;
/* If NREGNO is a hard register, it may occupy more than
- one register. If it does, say what is in the
+ one register. If it does, say what is in the
rest of the registers assuming that both registers
agree on how many words the object takes. If not,
invalidate the subsequent registers. */
for (k = 1; k < nnr; k++)
reg_last_reload_reg[nregno + k]
= (nr == nnr
- ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
- REGNO (reload_reg_rtx[r]) + k)
+ ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
+ REGNO (rld[r].reg_rtx) + k)
: 0);
/* Now do the inverse operation. */
/* Maybe the spill reg contains a copy of reload_in. Only do
something if there will not be an output reload for
the register being reloaded. */
- else if (reload_out_reg[r] == 0
- && reload_in[r] != 0
- && ((GET_CODE (reload_in[r]) == REG
- && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER
- && ! reg_has_output_reload[REGNO (reload_in[r])])
- || (GET_CODE (reload_in_reg[r]) == REG
- && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))
- && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn)))
+ else if (rld[r].out_reg == 0
+ && rld[r].in != 0
+ && ((GET_CODE (rld[r].in) == REG
+ && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
+ && ! reg_has_output_reload[REGNO (rld[r].in)])
+ || (GET_CODE (rld[r].in_reg) == REG
+ && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
+ && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
{
register int nregno;
int nnr;
- if (GET_CODE (reload_in[r]) == REG
- && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER)
- nregno = REGNO (reload_in[r]);
- else if (GET_CODE (reload_in_reg[r]) == REG)
- nregno = REGNO (reload_in_reg[r]);
+ if (GET_CODE (rld[r].in) == REG
+ && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
+ nregno = REGNO (rld[r].in);
+ else if (GET_CODE (rld[r].in_reg) == REG)
+ nregno = REGNO (rld[r].in_reg);
else
- nregno = REGNO (XEXP (reload_in_reg[r], 0));
+ nregno = REGNO (XEXP (rld[r].in_reg, 0));
nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
: HARD_REGNO_NREGS (nregno,
- GET_MODE (reload_reg_rtx[r])));
-
- reg_last_reload_reg[nregno] = reload_reg_rtx[r];
+ GET_MODE (rld[r].reg_rtx)));
+
+ reg_last_reload_reg[nregno] = rld[r].reg_rtx;
if (nregno < FIRST_PSEUDO_REGISTER)
for (k = 1; k < nnr; k++)
reg_last_reload_reg[nregno + k]
= (nr == nnr
- ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k],
- REGNO (reload_reg_rtx[r]) + k)
+ ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
+ REGNO (rld[r].reg_rtx) + k)
: 0);
/* Unless we inherited this reload, show we haven't
Previous stores of inherited auto_inc expressions
also have to be discarded. */
if (! reload_inherited[r]
- || (reload_out[r] && ! reload_out_reg[r]))
+ || (rld[r].out && ! rld[r].out_reg))
spill_reg_store[i] = 0;
for (k = 0; k < nr; k++)
{
for (k = 0; k < nr; k++)
if (reload_reg_reaches_end_p (i + k,
- reload_opnum[r],
- reload_when_needed[r]))
+ rld[r].opnum,
+ rld[r].when_needed))
CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
}
}
that invalidates any previous reloaded copy of it.
But forget_old_reloads_1 won't get to see it, because
it thinks only about the original insn. So invalidate it here. */
- if (i < 0 && reload_out[r] != 0
- && (GET_CODE (reload_out[r]) == REG
- || (GET_CODE (reload_out[r]) == MEM
- && GET_CODE (reload_out_reg[r]) == REG)))
+ if (i < 0 && rld[r].out != 0
+ && (GET_CODE (rld[r].out) == REG
+ || (GET_CODE (rld[r].out) == MEM
+ && GET_CODE (rld[r].out_reg) == REG)))
{
- rtx out = (GET_CODE (reload_out[r]) == REG
- ? reload_out[r] : reload_out_reg[r]);
+ rtx out = (GET_CODE (rld[r].out) == REG
+ ? rld[r].out : rld[r].out_reg);
register int nregno = REGNO (out);
if (nregno >= FIRST_PSEUDO_REGISTER)
{
- rtx src_reg, store_insn;
+ rtx src_reg, store_insn = NULL_RTX;
reg_last_reload_reg[nregno] = 0;
/* If we can find a hard register that is stored, record
the storing insn so that we may delete this insn with
delete_output_reload. */
- src_reg = reload_reg_rtx[r];
+ src_reg = rld[r].reg_rtx;
/* If this is an optional reload, try to find the source reg
from an input reload. */
if (! src_reg)
{
rtx set = single_set (insn);
- if (set && SET_DEST (set) == reload_out[r])
+ if (set && SET_DEST (set) == rld[r].out)
{
int k;
store_insn = insn;
for (k = 0; k < n_reloads; k++)
{
- if (reload_in[k] == src_reg)
+ if (rld[k].in == src_reg)
{
- src_reg = reload_reg_rtx[k];
+ src_reg = rld[k].reg_rtx;
break;
}
}
&& REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
{
int src_regno = REGNO (src_reg);
- int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]);
+ int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
/* The place where to find a death note varies with
PRESERVE_DEATH_INFO_REGNO_P . The condition is not
necessarily checked exactly in the code that moves
}
else
{
- int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r]));
+ int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
while (num_regs-- > 0)
reg_last_reload_reg[nregno + num_regs] = 0;
\f
/* Emit code to perform a reload from IN (which may be a reload register) to
OUT (which may also be a reload register). IN or OUT is from operand
- OPNUM with reload type TYPE.
+ OPNUM with reload type TYPE.
Returns first insn emitted. */
&& (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
in = SUBREG_REG (in), out = tem;
else if (GET_CODE (out) == SUBREG
- && (GET_MODE_SIZE (GET_MODE (out))
- > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
- && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
+ && (GET_MODE_SIZE (GET_MODE (out))
+ > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
+ && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
out = SUBREG_REG (out), in = tem;
/* How to do this reload can get quite tricky. Normally, we are being
delete_insns_since (last);
/* If that failed, we must use a conservative two-insn sequence.
- use move to copy constant, MEM, or pseudo register to the reload
- register since "move" will be able to handle an arbitrary operand,
- unlike add which can't, in general. Then add the registers.
+
+ Use a move to copy one operand into the reload register. Prefer
+ to reload a constant, MEM or pseudo since the move patterns can
+ handle an arbitrary operand. If OP1 is not a constant, MEM or
+ pseudo and OP1 is not a valid operand for an add instruction, then
+ reload OP1.
+
+ After reloading one of the operands into the reload register, add
+ the reload register to the output register.
If there is another way to do this for a specific machine, a
DEFINE_PEEPHOLE should be specified that recognizes the sequence
we emit below. */
+ code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
+
if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
|| (GET_CODE (op1) == REG
- && REGNO (op1) >= FIRST_PSEUDO_REGISTER))
+ && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
+ || (code != CODE_FOR_nothing
+ && ! ((*insn_data[code].operand[2].predicate)
+ (op1, insn_data[code].operand[2].mode))))
tem = op0, op0 = op1, op1 = tem;
gen_reload (out, op0, opnum, type);
int n_inherited = 0;
register rtx i1;
rtx substed;
-
+
/* Get the raw pseudo-register referred to. */
while (GET_CODE (reg) == SUBREG)
insn than it is inherited. */
for (k = n_reloads - 1; k >= 0; k--)
{
- rtx reg2 = reload_in[k];
+ rtx reg2 = rld[k].in;
if (! reg2)
continue;
if (GET_CODE (reg2) == MEM || reload_override_in[k])
- reg2 = reload_in_reg[k];
+ reg2 = rld[k].in_reg;
#ifdef AUTO_INC_DEC
- if (reload_out[k] && ! reload_out_reg[k])
- reg2 = XEXP (reload_in_reg[k], 0);
+ if (rld[k].out && ! rld[k].out_reg)
+ reg2 = XEXP (rld[k].in_reg, 0);
#endif
while (GET_CODE (reg2) == SUBREG)
reg2 = SUBREG_REG (reg2);
if (reload_inherited[k] || reload_override_in[k] || k == j)
{
n_inherited++;
- reg2 = reload_out_reg[k];
+ reg2 = rld[k].out_reg;
if (! reg2)
continue;
while (GET_CODE (reg2) == SUBREG)
See if the pseudo reg has been completely replaced
with reload regs. If so, delete the store insn
and forget we had a stack slot for the pseudo. */
- if (reload_out[j] != reload_in[j]
+ if (rld[j].out != rld[j].in
&& REG_N_DEATHS (REGNO (reg)) == 1
&& REG_N_SETS (REGNO (reg)) == 1
&& REG_BASIC_BLOCK (REGNO (reg)) >= 0
/* For the debugging info,
say the pseudo lives in this reload reg. */
- reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]);
+ reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
alter_reg (REGNO (reg), -1);
}
delete_address_reloads (output_reload_insn, insn);
if (code != REG)
{
- char *fmt= GET_RTX_FORMAT (code);
+ const char *fmt= GET_RTX_FORMAT (code);
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
{
if (fmt[i] == 'e')
if (i2 == current_insn)
{
for (j = n_reloads - 1; j >= 0; j--)
- if ((reload_reg_rtx[j] == dst && reload_inherited[j])
+ if ((rld[j].reg_rtx == dst && reload_inherited[j])
|| reload_override_in[j] == dst)
return;
for (j = n_reloads - 1; j >= 0; j--)
- if (reload_in[j] && reload_reg_rtx[j] == dst)
+ if (rld[j].in && rld[j].reg_rtx == dst)
break;
if (j >= 0)
break;
}
if (GET_CODE (i2) == JUMP_INSN)
break;
- if (reg_set_p (dst, PATTERN (i2)))
- break;
/* If DST is still live at CURRENT_INSN, check if it is used for
- any reload. */
+ any reload. Note that even if CURRENT_INSN sets DST, we still
+ have to check the reloads. */
if (i2 == current_insn)
{
for (j = n_reloads - 1; j >= 0; j--)
- if ((reload_reg_rtx[j] == dst && reload_inherited[j])
+ if ((rld[j].reg_rtx == dst && reload_inherited[j])
|| reload_override_in[j] == dst)
return;
/* ??? We can't finish the loop here, because dst might be
spill_hard_reg. There is no easy way to tell this, so we
have to scan till the end of the basic block. */
}
+ if (reg_set_p (dst, PATTERN (i2)))
+ break;
}
}
delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
gen_rtx_PLUS (GET_MODE (incloc),
incloc, inc)));
-
+
code = recog_memoized (add_insn);
if (code >= 0)
{
static int
constraint_accepts_reg_p (string, reg)
- char *string;
+ const char *string;
rtx reg;
{
int value = 0;
{
register int i, j;
register enum rtx_code code;
- register char *format_ptr;
+ register const char *format_ptr;
int count;
if (x == find)
if (SET_DEST (x) == find)
return count_occurrences (SET_SRC (x), find);
break;
-
+
default:
break;
}
&& refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR))
{
/* If this is the only entry on the list, clear
- reg_values[i]. Otherwise, just clear this entry on
- the list. */
+ reg_values[i]. Otherwise, just clear this entry on
+ the list. */
if (XEXP (x, 1) == 0 && x == reg_values[i])
{
reg_values[i] = 0;
rtx val;
{
enum rtx_code code;
- char *fmt;
+ const char *fmt;
int i;
code = GET_CODE (val);
&& reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0)))
{
/* If this is the only entry on the list, clear
- reg_values[i]. Otherwise, just clear this entry on
- the list. */
+ reg_values[i]. Otherwise, just clear this entry on
+ the list. */
if (XEXP (x, 1) == 0 && x == reg_values[i])
{
reg_values[i] = 0;
note_stores; it is ignored. */
static void
-reload_cse_invalidate_rtx (dest, ignore)
+reload_cse_invalidate_rtx (dest, ignore, data)
rtx dest;
rtx ignore ATTRIBUTE_UNUSED;
+ void *data ATTRIBUTE_UNUSED;
{
while (GET_CODE (dest) == STRICT_LOW_PART
|| GET_CODE (dest) == SIGN_EXTRACT
This function also detects cases where we load a value from memory
into two different registers, and (if memory is more expensive than
registers) changes it to simply copy the first register into the
- second register.
+ second register.
Another optimization is performed that scans the operands of each
instruction to see whether the value is already available in a
if (GET_CODE (insn) == CODE_LABEL)
{
/* Forget all the register values at a code label. We don't
- try to do anything clever around jumps. */
+ try to do anything clever around jumps. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
reg_values[i] = 0;
continue;
}
-#ifdef NON_SAVING_SETJMP
+#ifdef NON_SAVING_SETJMP
if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE
&& NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
{
reload_cse_invalidate_mem (callmem);
}
+
+ /* Forget all the register values at a volatile asm. */
+ if (GET_CODE (insn) == INSN
+ && GET_CODE (PATTERN (insn)) == ASM_OPERANDS
+ && MEM_VOLATILE_P (PATTERN (insn)))
+ for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
+ reg_values[i] = 0;
+
body = PATTERN (insn);
if (GET_CODE (body) == SET)
{
apply_change_group ();
else
reload_cse_simplify_operands (insn);
-
+
reload_cse_record_set (body, body);
}
else if (GET_CODE (body) == PARALLEL)
rtx value = NULL_RTX;
/* If every action in a PARALLEL is a noop, we can delete
- the entire PARALLEL. */
+ the entire PARALLEL. */
for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
{
rtx part = XVECEXP (body, 0, i);
/* We're done with this insn. */
continue;
}
-
+
/* It's not a no-op, but we can try to simplify it. */
for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
if (GET_CODE (XVECEXP (body, 0, i)) == SET)
reload_cse_simplify_operands (insn);
/* Look through the PARALLEL and record the values being
- set, if possible. Also handle any CLOBBERs. */
+ set, if possible. Also handle any CLOBBERs. */
for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
{
rtx x = XVECEXP (body, 0, i);
if (GET_CODE (x) == SET)
reload_cse_record_set (x, body);
else
- note_stores (x, reload_cse_invalidate_rtx);
+ note_stores (x, reload_cse_invalidate_rtx, NULL);
}
}
else
- note_stores (body, reload_cse_invalidate_rtx);
+ note_stores (body, reload_cse_invalidate_rtx, NULL);
#ifdef AUTO_INC_DEC
/* Clobber any registers which appear in REG_INC notes. We
- could keep track of the changes to their values, but it is
- unlikely to help. */
+ could keep track of the changes to their values, but it is
+ unlikely to help. */
{
rtx x;
for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
if (REG_NOTE_KIND (x) == REG_INC)
- reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX);
+ reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX, NULL);
}
#endif
/* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
- after we have processed the insn. */
+ after we have processed the insn. */
if (GET_CODE (insn) == CALL_INSN)
{
rtx x;
for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1))
if (GET_CODE (XEXP (x, 0)) == CLOBBER)
- reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX);
+ reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX,
+ NULL);
}
}
+ /* Clean up. */
+ end_alias_analysis ();
+
/* Free all the temporary structures we created, and go back to the
regular obstacks. */
obstack_free (&reload_obstack, firstobj);
static int
reload_cse_noop_set_p (set, insn)
rtx set;
- rtx insn;
+ rtx insn ATTRIBUTE_UNUSED;
{
rtx src, dest;
enum machine_mode dest_mode;
ret = 1;
/* Check for setting a register to a value which we already know
- is in the register. */
+ is in the register. */
else if (reload_cse_regno_equal_p (dreg, src, dest_mode))
ret = 1;
/* Check for setting a register DREG to another register SREG
- where SREG is equal to a value which is already in DREG. */
+ where SREG is equal to a value which is already in DREG. */
else if (sreg >= 0)
{
rtx x;
else if (GET_CODE (dest) == MEM)
{
/* Check for storing a register to memory when we know that the
- register is equivalent to the memory location. */
+ register is equivalent to the memory location. */
if (sreg >= 0
&& reload_cse_regno_equal_p (sreg, dest, dest_mode)
&& ! side_effects_p (dest))
gen_rtx_REG (dest_mode, i), 1);
/* Go back to the obstack we are using for temporary
- storage. */
+ storage. */
push_obstacks (&reload_obstack, &reload_obstack);
if (validated)
}
/* Try to replace operands in INSN with equivalent values that are already
- in registers. This can be viewed as optional reloading.
-
+ in registers. This can be viewed as optional reloading.
+
For each non-register operand in the insn, see if any hard regs are
known to be equivalent to that operand. Record the alternatives which
can accept these hard registers. Among all alternatives, select the
reload_cse_simplify_operands (insn)
rtx insn;
{
-#ifdef REGISTER_CONSTRAINTS
int i,j;
- char *constraints[MAX_RECOG_OPERANDS];
-
+ const char *constraints[MAX_RECOG_OPERANDS];
+
/* Vector recording how bad an alternative is. */
int *alternative_reject;
/* Vector recording how many registers can be introduced by choosing
/* Array of alternatives, sorted in order of decreasing desirability. */
int *alternative_order;
rtx reg = gen_rtx_REG (VOIDmode, -1);
-
+
extract_insn (insn);
- if (recog_n_alternatives == 0 || recog_n_operands == 0)
+ if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
return 0;
/* Figure out which alternative currently matches. */
if (! constrain_operands (1))
fatal_insn_not_found (insn);
- alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int));
- alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int));
- alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int));
- bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int));
- bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int));
+ alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
+ alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
+ alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
+ bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
+ bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
- for (i = 0; i < recog_n_operands; i++)
+ for (i = 0; i < recog_data.n_operands; i++)
{
enum machine_mode mode;
int regno;
- char *p;
+ const char *p;
- op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int));
- for (j = 0; j < recog_n_alternatives; j++)
+ op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
+ for (j = 0; j < recog_data.n_alternatives; j++)
op_alt_regno[i][j] = -1;
- p = constraints[i] = recog_constraints[i];
- mode = recog_operand_mode[i];
+ p = constraints[i] = recog_data.constraints[i];
+ mode = recog_data.operand_mode[i];
/* Add the reject values for each alternative given by the constraints
for this operand. */
/* We won't change operands which are already registers. We
also don't want to modify output operands. */
- regno = true_regnum (recog_operand[i]);
+ regno = true_regnum (recog_data.operand[i]);
if (regno >= 0
|| constraints[i][0] == '='
|| constraints[i][0] == '+')
{
int class = (int) NO_REGS;
- if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode))
+ if (! reload_cse_regno_equal_p (regno, recog_data.operand[i], mode))
continue;
REGNO (reg) = regno;
for (;;)
{
char c = *p++;
-
+
switch (c)
{
case '=': case '+': case '?':
case '#': case '&': case '!':
- case '*': case '%':
+ case '*': case '%':
case '0': case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
case 'm': case '<': case '>': case 'V': case 'o':
case 'E': case 'F': case 'G': case 'H':
case 's': case 'i': case 'n':
a cheap CONST_INT. */
if (op_alt_regno[i][j] == -1
&& reg_fits_class_p (reg, class, 0, mode)
- && (GET_CODE (recog_operand[i]) != CONST_INT
- || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET)))
+ && (GET_CODE (recog_data.operand[i]) != CONST_INT
+ || (rtx_cost (recog_data.operand[i], SET)
+ > rtx_cost (reg, SET))))
{
alternative_nregs[j]++;
op_alt_regno[i][j] = regno;
/* Record all alternatives which are better or equal to the currently
matching one in the alternative_order array. */
- for (i = j = 0; i < recog_n_alternatives; i++)
+ for (i = j = 0; i < recog_data.n_alternatives; i++)
if (alternative_reject[i] <= alternative_reject[which_alternative])
alternative_order[j++] = i;
- recog_n_alternatives = j;
+ recog_data.n_alternatives = j;
/* Sort it. Given a small number of alternatives, a dumb algorithm
won't hurt too much. */
- for (i = 0; i < recog_n_alternatives - 1; i++)
+ for (i = 0; i < recog_data.n_alternatives - 1; i++)
{
int best = i;
int best_reject = alternative_reject[alternative_order[i]];
int best_nregs = alternative_nregs[alternative_order[i]];
int tmp;
- for (j = i + 1; j < recog_n_alternatives; j++)
+ for (j = i + 1; j < recog_data.n_alternatives; j++)
{
int this_reject = alternative_reject[alternative_order[j]];
int this_nregs = alternative_nregs[alternative_order[j]];
best_nregs = this_nregs;
}
}
-
+
tmp = alternative_order[best];
alternative_order[best] = alternative_order[i];
alternative_order[i] = tmp;
}
-
+
/* Substitute the operands as determined by op_alt_regno for the best
alternative. */
j = alternative_order[0];
/* Pop back to the real obstacks while changing the insn. */
pop_obstacks ();
- for (i = 0; i < recog_n_operands; i++)
+ for (i = 0; i < recog_data.n_operands; i++)
{
- enum machine_mode mode = recog_operand_mode[i];
+ enum machine_mode mode = recog_data.operand_mode[i];
if (op_alt_regno[i][j] == -1)
continue;
- validate_change (insn, recog_operand_loc[i],
+ validate_change (insn, recog_data.operand_loc[i],
gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
}
- for (i = recog_n_dups - 1; i >= 0; i--)
+ for (i = recog_data.n_dups - 1; i >= 0; i--)
{
- int op = recog_dup_num[i];
- enum machine_mode mode = recog_operand_mode[op];
+ int op = recog_data.dup_num[i];
+ enum machine_mode mode = recog_data.operand_mode[op];
if (op_alt_regno[op][j] == -1)
continue;
- validate_change (insn, recog_dup_loc[i],
+ validate_change (insn, recog_data.dup_loc[i],
gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
}
push_obstacks (&reload_obstack, &reload_obstack);
return apply_change_group ();
-#else
- return 0;
-#endif
}
/* These two variables are used to pass information from
second argument, which is passed by note_stores, is ignored. */
static void
-reload_cse_check_clobber (dest, ignore)
+reload_cse_check_clobber (dest, ignore, data)
rtx dest;
rtx ignore ATTRIBUTE_UNUSED;
+ void *data ATTRIBUTE_UNUSED;
{
if (reg_overlap_mentioned_p (dest, reload_cse_check_src))
reload_cse_check_clobbered = 1;
x = XEXP (x, 0);
if (push_operand (x, GET_MODE (x)))
{
- reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX);
- reload_cse_invalidate_rtx (dest, NULL_RTX);
+ reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX, NULL);
+ reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
return;
}
|| side_effects_p (src)
|| side_effects_p (dest))
{
- reload_cse_invalidate_rtx (dest, NULL_RTX);
+ reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
return;
}
if (reg_mentioned_p (cc0_rtx, src)
|| reg_mentioned_p (cc0_rtx, dest))
{
- reload_cse_invalidate_rtx (dest, NULL_RTX);
+ reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
return;
}
#endif
reload_cse_check_clobbered = 0;
reload_cse_check_src = src;
- note_stores (x, reload_cse_check_clobber);
+ note_stores (x, reload_cse_check_clobber, NULL);
if (reload_cse_check_clobbered)
{
- reload_cse_invalidate_rtx (dest, NULL_RTX);
+ reload_cse_invalidate_rtx (dest, NULL_RTX, NULL);
return;
}
}
int i;
/* This is an assignment to a register. Update the value we
- have stored for the register. */
+ have stored for the register. */
if (sreg >= 0)
{
rtx x;
if (dest_mode == GET_MODE (XEXP (x, 0)))
tmp = XEXP (x, 0);
else if (GET_MODE_BITSIZE (dest_mode)
- > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
+ > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
continue;
else
tmp = gen_lowpart_common (dest_mode, XEXP (x, 0));
if (tmp)
reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp,
reg_values[dreg]);
- }
+ }
}
else
reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX);
/* We've changed DREG, so invalidate any values held by other
- registers that depend upon it. */
+ registers that depend upon it. */
reload_cse_invalidate_regno (dreg, dest_mode, 0);
/* If this assignment changes more than one hard register,
- forget anything we know about the others. */
+ forget anything we know about the others. */
for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++)
reg_values[dreg + i] = 0;
}
reload_cse_invalidate_mem (dest);
/* If we're storing a register to memory, add DEST to the list
- in REG_VALUES. */
+ in REG_VALUES. */
if (sreg >= 0 && ! side_effects_p (dest))
reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest,
reg_values[sreg]);
{
HARD_REG_SET live;
- REG_SET_TO_HARD_REG_SET (live, basic_block_live_at_start[i]);
- compute_use_by_pseudos (&live, basic_block_live_at_start[i]);
+ REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start);
+ compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start);
COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
IOR_HARD_REG_SET (ever_live_at_start, live);
}
/* We cannot do our optimization across labels. Invalidating all the use
information we have would be costly, so we just note where the label
- is and then later disable any optimization that would cross it. */
+ is and then later disable any optimization that would cross it. */
if (GET_CODE (insn) == CODE_LABEL)
last_label_ruid = reload_combine_ruid;
if (GET_CODE (insn) == BARRIER)
reload_combine_ruid++;
/* Look for (set (REGX) (CONST_INT))
- (set (REGX) (PLUS (REGX) (REGY)))
- ...
- ... (MEM (REGX)) ...
+ (set (REGX) (PLUS (REGX) (REGY)))
+ ...
+ ... (MEM (REGX)) ...
and convert it to
- (set (REGZ) (CONST_INT))
- ...
- ... (MEM (PLUS (REGZ) (REGY)))... .
+ (set (REGZ) (CONST_INT))
+ ...
+ ... (MEM (PLUS (REGZ) (REGY)))... .
First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
and that we know all uses of REGX before it dies. */
rtx prev = prev_nonnote_insn (insn);
rtx prev_set = prev ? single_set (prev) : NULL_RTX;
int regno = REGNO (reg);
- rtx const_reg;
+ rtx const_reg = NULL_RTX;
rtx reg_sum = NULL_RTX;
/* Now, we need an index register.
}
else
{
- /* Otherwise, look for a free index register. Since we have
- checked above that neiter REG nor BASE are index registers,
- if we find anything at all, it will be different from these
- two registers. */
- for (i = first_index_reg; i <= last_index_reg; i++)
+ /* Otherwise, look for a free index register. Since we have
+ checked above that neiter REG nor BASE are index registers,
+ if we find anything at all, it will be different from these
+ two registers. */
+ for (i = first_index_reg; i <= last_index_reg; i++)
{
if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)
&& reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
}
}
}
- note_stores (PATTERN (insn), reload_combine_note_store);
+ note_stores (PATTERN (insn), reload_combine_note_store, NULL);
if (GET_CODE (insn) == CALL_INSN)
{
rtx link;
/* Check if DST is a register or a subreg of a register; if it is,
update reg_state[regno].store_ruid and reg_state[regno].use_index
- accordingly. Called via note_stores from reload_combine.
- The second argument, SET, is ignored. */
+ accordingly. Called via note_stores from reload_combine. */
static void
-reload_combine_note_store (dst, set)
- rtx dst, set ATTRIBUTE_UNUSED;
+reload_combine_note_store (dst, set, data)
+ rtx dst, set;
+ void *data ATTRIBUTE_UNUSED;
{
int regno = 0;
int i;
if (GET_CODE (dst) != REG)
return;
regno += REGNO (dst);
+
/* note_stores might have stripped a STRICT_LOW_PART, so we have to be
- careful with registers / register parts that are not full words. */
- if (size < (unsigned) UNITS_PER_WORD)
+ careful with registers / register parts that are not full words.
+
+ Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
+ if (GET_CODE (set) != SET
+ || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
+ || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
+ || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
{
- reg_state[regno].use_index = -1;
- reg_state[regno].store_ruid = reload_combine_ruid;
+ for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
+ {
+ reg_state[i].use_index = -1;
+ reg_state[i].store_ruid = reload_combine_ruid;
+ }
}
else
{
- for (i = size / UNITS_PER_WORD - 1 + regno; i >= regno; i--)
+ for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--)
{
reg_state[i].store_ruid = reload_combine_ruid;
reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
{
rtx x = *xp;
enum rtx_code code = x->code;
- char *fmt;
+ const char *fmt;
int i, j;
rtx offset = const0_rtx; /* For the REG case below. */
break;
offset = XEXP (x, 1);
x = XEXP (x, 0);
- /* Fall through. */
+ /* Fall through. */
case REG:
{
int regno = REGNO (x);
reload_cse_move2add and move2add_note_store. */
static int move2add_luid;
+/* Generate a CONST_INT and force it in the range of MODE. */
+static rtx
+gen_mode_int (mode, value)
+ enum machine_mode mode;
+ HOST_WIDE_INT value;
+{
+ HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
+ int width = GET_MODE_BITSIZE (mode);
+
+ /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
+ sign extend it. */
+ if (width > 0 && width < HOST_BITS_PER_WIDE_INT
+ && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
+ cval |= (HOST_WIDE_INT) -1 << width;
+
+ return GEN_INT (cval);
+}
+
static void
reload_cse_move2add (first)
rtx first;
/* ??? We don't know how zero / sign extension is handled, hence
we can't go from a narrower to a wider mode. */
if (reg_set_luid[regno] > last_label_luid
- && (GET_MODE_SIZE (GET_MODE (reg))
- <= GET_MODE_SIZE (reg_mode[regno]))
- && GET_CODE (reg_offset[regno]) == CONST_INT)
+ && (GET_MODE_SIZE (GET_MODE (reg))
+ <= GET_MODE_SIZE (reg_mode[regno]))
+ && GET_CODE (reg_offset[regno]) == CONST_INT)
{
/* Try to transform (set (REGX) (CONST_INT A))
...
if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
{
int success = 0;
- rtx new_src = GEN_INT (INTVAL (src)
- - INTVAL (reg_offset[regno]));
+ rtx new_src
+ = gen_mode_int (GET_MODE (reg),
+ INTVAL (src) - INTVAL (reg_offset[regno]));
/* (set (reg) (plus (reg) (const_int 0))) is not canonical;
use (set (reg) (reg)) instead.
We don't delete this insn, nor do we convert it into a
&& reg_set_luid[regno] > reg_set_luid[REGNO (src)])
{
rtx next = next_nonnote_insn (insn);
- rtx set;
+ rtx set = NULL_RTX;
if (next)
set = single_set (next);
if (next
&& GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
{
rtx src3 = XEXP (SET_SRC (set), 1);
- rtx new_src = GEN_INT (INTVAL (src3)
- - INTVAL (reg_offset[regno]));
+ rtx new_src
+ = gen_mode_int (GET_MODE (reg),
+ INTVAL (src3)
+ - INTVAL (reg_offset[regno]));
int success = 0;
if (new_src == const0_rtx)
}
}
}
- note_stores (PATTERN (insn), move2add_note_store);
+ note_stores (PATTERN (insn), move2add_note_store, NULL);
/* If this is a CALL_INSN, all call used registers are stored with
unknown values. */
if (GET_CODE (insn) == CALL_INSN)
Update reg_set_luid, reg_offset and reg_base_reg accordingly.
Called from reload_cse_move2add via note_stores. */
static void
-move2add_note_store (dst, set)
+move2add_note_store (dst, set, data)
rtx dst, set;
+ void *data ATTRIBUTE_UNUSED;
{
int regno = 0;
int i;
regno += REGNO (dst);
- if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET)
+ if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
+ && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
+ && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
+ && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
{
rtx src = SET_SRC (set);
}
}
}
+
+#ifdef AUTO_INC_DEC
+static void
+add_auto_inc_notes (insn, x)
+ rtx insn;
+ rtx x;
+{
+ enum rtx_code code = GET_CODE (x);
+ const char *fmt;
+ int i, j;
+
+ if (code == MEM && auto_inc_p (XEXP (x, 0)))
+ {
+ REG_NOTES (insn)
+ = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
+ return;
+ }
+
+ /* Scan all the operand sub-expressions. */
+ fmt = GET_RTX_FORMAT (code);
+ for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
+ {
+ if (fmt[i] == 'e')
+ add_auto_inc_notes (insn, XEXP (x, i));
+ else if (fmt[i] == 'E')
+ for (j = XVECLEN (x, i) - 1; j >= 0; j--)
+ add_auto_inc_notes (insn, XVECEXP (x, i, j));
+ }
+}
+#endif
git://gcc.gnu.org / gcc.git / blobdiff