/* Provide required defaults for linker -e and -d switches. */
#define LINK_SPEC \
- "%{nostdlib:%{!e*:-e start}} -dc -dp %{static:-Bstatic} %{assert*}"
+ "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
/* Special flags to the Sun-4 assembler when using pipe for input. */
#define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}"
+/* Define macros to distinguish architectures. */
+#define CPP_SPEC "%{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__}"
+
/* Prevent error on `-sun4' and `-target sun4' options. */
/* This used to translate -dalign to -malign, but that is no good
because it can't turn off the usual meaning of making debugging dumps. */
#define CC1_SPEC "%{sun4:} %{target:}"
+#if 0
+/* Sparc ABI says that long double is 4 words.
+ ??? This doesn't work yet. */
+#define LONG_DOUBLE_TYPE_SIZE 128
+#endif
+
#define PTRDIFF_TYPE "int"
#define SIZE_TYPE "int"
#define WCHAR_TYPE "short unsigned int"
seem worth trying to fix. */
#define TARGET_FORCE_ALIGN (target_flags & 32)
+/* Nonzero means that we should generate code for a v8 sparc. */
+#define TARGET_V8 (target_flags & 64)
+
+/* Nonzero means that we should generate code for a sparclite. */
+#define TARGET_SPARCLITE (target_flags & 128)
+
/* Macro to define tables used to set the flags.
This is a list in braces of pairs in braces,
each pair being { "NAME", VALUE }
{"no-epilogue", -2}, \
{"hope-align", 16}, \
{"force-align", 48}, \
+ {"v8", 64}, \
+ {"no-v8", -64}, \
+ {"sparclite", 128}, \
+ {"no-sparclite", -128}, \
{ "", TARGET_DEFAULT}}
#define TARGET_DEFAULT 3
/* Boundary (in *bits*) on which stack pointer should be aligned. */
#define STACK_BOUNDARY 64
+/* ALIGN FRAMES on double word boundaries */
+
+#define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
+
/* Allocation boundary (in *bits*) for the code of a function. */
#define FUNCTION_BOUNDARY 32
/* No data type wants to be aligned rounder than this. */
#define BIGGEST_ALIGNMENT 64
+/* The best alignment to use in cases where we have a choice. */
+#define FASTEST_ALIGNMENT 64
+
/* Make strings word-aligned so strcpy from constants will be faster. */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
- (TREE_CODE (EXP) == STRING_CST \
- && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+ ((TREE_CODE (EXP) == STRING_CST \
+ && (ALIGN) < FASTEST_ALIGNMENT) \
+ ? FASTEST_ALIGNMENT : (ALIGN))
/* Make arrays of chars word-aligned for the same reasons. */
#define DATA_ALIGNMENT(TYPE, ALIGN) \
(TREE_CODE (TYPE) == ARRAY_TYPE \
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
- && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
+ && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
/* Set this nonzero if move instructions will actually fail to work
when given unaligned data. */
and are not available for the register allocator.
0 is used for the condition code and not to represent %g0, which is
hardwired to 0, so reg 0 is *not* fixed.
- 2 and 3 are free to use as temporaries.
- 4 through 7 are expected to become usefully defined in the future.
- Your milage may vary. */
+ g1 through g4 are free to use as temporaries.
+ g5 through g7 are reserved for the operating system. */
#define FIXED_REGISTERS \
- {0, 0, 0, 0, 1, 1, 1, 1, \
+ {0, 0, 0, 0, 0, 1, 1, 1, \
0, 0, 0, 0, 0, 0, 1, 0, \
0, 0, 0, 0, 0, 0, 0, 0, \
0, 0, 0, 0, 0, 0, 1, 1, \
#define INITIALIZE_PIC initialize_pic ()
#define FINALIZE_PIC finalize_pic ()
+/* Sparc ABI says that quad-precision floats and all structures are returned
+ in memory. We go along regarding floats, but for structures
+ we follow GCC's normal policy. Use -fpcc-struct-value
+ if you want to follow the ABI. */
+#define RETURN_IN_MEMORY(TYPE) \
+ (TYPE_MODE (TYPE) == TFmode)
+
/* Functions which return large structures get the address
to place the wanted value at offset 64 from the frame.
Must reserve 64 bytes for the in and local registers. */
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
in some cases it is preferable to use a more restrictive class. */
-#define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
+/* We can't load constants into FP registers. We can't load any FP constant
+ if an 'E' constraint fails to match it. */
+#define PREFERRED_RELOAD_CLASS(X,CLASS) \
+ (CONSTANT_P (X) \
+ && ((CLASS) == FP_REGS \
+ || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
+ && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
+ || HOST_BITS_PER_INT != BITS_PER_WORD))) \
+ ? NO_REGS : (CLASS))
/* Return the register class of a scratch register needed to load IN into
a register of class CLASS in MODE.
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
(flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS : NO_REGS)
+/* On SPARC it is not possible to directly move data between
+ GENERAL_REGS and FP_REGS. */
+#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
+ ((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
+ || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS))
+
+
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
/* On SPARC, this is the size of MODE in words. */
? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
: 0)
-/* The SPARC ABI stipulates passing struct arguments (of any size)
- by invisible reference. */
+/* The SPARC ABI stipulates passing struct arguments (of any size) and
+ quad-precision floats by invisible reference. */
#define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
- (TYPE && (TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE (TYPE) == UNION_TYPE))
+ ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
+ || TREE_CODE (TYPE) == UNION_TYPE)) \
+ || (MODE == TFmode))
/* If defined, a C expression that gives the alignment boundary, in
bits, of an argument with the specified mode and type. If it is
/* Output assembler code to FILE to increment profiler label # LABELNO
for profiling a function entry. */
-#define FUNCTION_PROFILER(FILE, LABELNO) \
- fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
- (LABELNO), (LABELNO))
+#define FUNCTION_PROFILER(FILE, LABELNO) \
+ do { \
+ fputs ("\tsethi %hi(", (FILE)); \
+ ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
+ fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \
+ ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
+ fputs ("),%o0,%o0\n", (FILE)); \
+ } while (0)
/* Output assembler code to FILE to initialize this source file's
basic block profiling info, if that has not already been done. */
+/* FIXME -- this does not parameterize how it generates labels (like the
+ above FUNCTION_PROFILER). Broken on Solaris-2. --gnu@cygnus.com */
#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
#define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
#define EXTRA_CONSTRAINT(OP, C) \
- ((C) == 'Q' ? \
- ((GET_CODE (OP) == MEM \
- && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
- && ! symbolic_memory_operand (OP, VOIDmode))) \
- : ((C) == 'R' ? \
- (GET_CODE (OP) == LO_SUM \
- && GET_CODE (XEXP (OP, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
- : ((C) == 'S' \
- ? CONSTANT_P (OP) || memory_address_p (Pmode, OP) : 0)))
-
+ ((C) == 'Q' \
+ ? ((GET_CODE (OP) == MEM \
+ && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
+ && ! symbolic_memory_operand (OP, VOIDmode)) \
+ || (reload_in_progress && GET_CODE (OP) == REG \
+ && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
+ : (C) == 'R' \
+ ? (GET_CODE (OP) == LO_SUM \
+ && GET_CODE (XEXP (OP, 0)) == REG \
+ && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
+ : (C) == 'S' \
+ ? (CONSTANT_P (OP) || memory_address_p (Pmode, OP)) \
+ : (C) == 'T' \
+ ? (mem_aligned_8 (OP)) \
+ : (C) == 'U' \
+ ? (register_ok_for_ldd (OP)) \
+ : 0)
+
#else
/* Nonzero if X is a hard reg that can be used as an index. */
: ((C) == 'S' \
? (CONSTANT_P (OP) \
|| (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\
- || strict_memory_address_p (Pmode, OP)) : 0)))
+ || strict_memory_address_p (Pmode, OP)) \
+ : ((C) == 'T' ? \
+ mem_aligned_8 (OP) && strict_memory_address_p (Pmode, OP) \
+ : ((C) == 'U' ? \
+ register_ok_for_ldd (OP) : 0)))))
#endif
\f
/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
If you change this, execute "rm explow.o recog.o reload.o". */
+#define RTX_OK_FOR_BASE_P(X) \
+ ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
+ || (GET_CODE (X) == SUBREG \
+ && GET_CODE (SUBREG_REG (X)) == REG \
+ && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
+
+#define RTX_OK_FOR_INDEX_P(X) \
+ ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
+ || (GET_CODE (X) == SUBREG \
+ && GET_CODE (SUBREG_REG (X)) == REG \
+ && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
+
+#define RTX_OK_FOR_OFFSET_P(X) \
+ (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
+
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
-{ if (GET_CODE (X) == REG) \
- { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \
+{ if (RTX_OK_FOR_BASE_P (X)) \
+ goto ADDR; \
else if (GET_CODE (X) == PLUS) \
{ \
- if (flag_pic && XEXP (X, 0) == pic_offset_table_rtx)\
+ register rtx op0 = XEXP (X, 0); \
+ register rtx op1 = XEXP (X, 1); \
+ if (flag_pic && op0 == pic_offset_table_rtx) \
{ \
- if (GET_CODE (XEXP (X, 1)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
+ if (RTX_OK_FOR_BASE_P (op1)) \
goto ADDR; \
else if (flag_pic == 1 \
- && GET_CODE (XEXP (X, 1)) != REG \
- && GET_CODE (XEXP (X, 1)) != LO_SUM \
- && GET_CODE (XEXP (X, 1)) != MEM) \
+ && GET_CODE (op1) != REG \
+ && GET_CODE (op1) != LO_SUM \
+ && GET_CODE (op1) != MEM) \
goto ADDR; \
} \
- else if (GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
+ else if (RTX_OK_FOR_BASE_P (op0)) \
{ \
- if (GET_CODE (XEXP (X, 1)) == REG \
- && REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
- goto ADDR; \
- if (GET_CODE (XEXP (X, 1)) == CONST_INT \
- && INTVAL (XEXP (X, 1)) >= -0x1000 \
- && INTVAL (XEXP (X, 1)) < 0x1000) \
+ if (RTX_OK_FOR_INDEX_P (op1) \
+ || RTX_OK_FOR_OFFSET_P (op1)) \
goto ADDR; \
} \
- else if (GET_CODE (XEXP (X, 1)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
+ else if (RTX_OK_FOR_BASE_P (op1)) \
{ \
- if (GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
- goto ADDR; \
- if (GET_CODE (XEXP (X, 0)) == CONST_INT \
- && INTVAL (XEXP (X, 0)) >= -0x1000 \
- && INTVAL (XEXP (X, 0)) < 0x1000) \
+ if (RTX_OK_FOR_INDEX_P (op0) \
+ || RTX_OK_FOR_OFFSET_P (op0)) \
goto ADDR; \
} \
} \
- else if (GET_CODE (X) == LO_SUM \
- && GET_CODE (XEXP (X, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
- && CONSTANT_P (XEXP (X, 1))) \
- goto ADDR; \
- else if (GET_CODE (X) == LO_SUM \
- && GET_CODE (XEXP (X, 0)) == SUBREG \
- && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG\
- && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0)))\
- && CONSTANT_P (XEXP (X, 1))) \
- goto ADDR; \
+ else if (GET_CODE (X) == LO_SUM) \
+ { \
+ register rtx op0 = XEXP (X, 0); \
+ register rtx op1 = XEXP (X, 1); \
+ if (RTX_OK_FOR_BASE_P (op0) \
+ && CONSTANT_P (op1)) \
+ goto ADDR; \
+ } \
else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
goto ADDR; \
}
/* Max number of bytes we can move from memory to memory
in one reasonably fast instruction. */
-#define MOVE_MAX 4
+#define MOVE_MAX 8
+
+/* This is the value of the error code EDOM for this machine,
+ used by the sqrt instruction. */
+#define TARGET_EDOM 33
+
+/* This is how to refer to the variable errno. */
+#define GEN_ERRNO_RTX \
+ gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
/* Define if normal loads of shorter-than-word items from memory clears
the rest of the bigs in the register. */
subtract insn is used to set the condition code. Different branches are
used in this case for some operations.
- We also have a mode to indicate that the relevant condition code is
- in the floating-point condition code. This really should be a separate
- register, but we don't want to go to 65 registers. */
-#define EXTRA_CC_MODES CC_NOOVmode, CCFPmode
+ We also have two modes to indicate that the relevant condition code is
+ in the floating-point condition code register. One for comparisons which
+ will generate an exception if the result is unordered (CCFPEmode) and
+ one for comparisons which will never trap (CCFPmode). This really should
+ be a separate register, but we don't want to go to 65 registers. */
+#define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
/* Define the names for the modes specified above. */
-#define EXTRA_CC_NAMES "CC_NOOV", "CCFP"
+#define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
- return the mode to be used for the comparison. For floating-point, CCFPmode
- should be used. CC_NOOVmode should be used when the first operand is a
+ return the mode to be used for the comparison. For floating-point,
+ CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
PLUS, MINUS, or NEG. CCmode should be used when no special processing is
needed. */
-#define SELECT_CC_MODE(OP,X) \
- (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
- : (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
- ? CC_NOOVmode : CCmode)
+#define SELECT_CC_MODE(OP,X,Y) \
+ (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
+ ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
+ : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
+ ? CC_NOOVmode : CCmode))
/* A function address in a call instruction
is a byte address (for indexing purposes)
of a switch statement. If the code is computed here,
return it with a return statement. Otherwise, break from the switch. */
-#define CONST_COSTS(RTX,CODE) \
+#define CONST_COSTS(RTX,CODE,OUTER_CODE) \
case CONST_INT: \
if (INTVAL (RTX) == 0) \
return 0; \
If we need more than 12 insns to do a multiply, then go out-of-line,
since the call overhead will be < 10% of the cost of the multiply. */
-#define RTX_COSTS(X,CODE) \
+#define RTX_COSTS(X,CODE,OUTER_CODE) \
case MULT: \
return COSTS_N_INSNS (25); \
case DIV: \
#define ASM_APP_OFF ""
+#define ASM_LONG ".word"
+#define ASM_SHORT ".half"
+#define ASM_BYTE_OP ".byte"
+
/* Output before read-only data. */
#define TEXT_SECTION_ASM_OP ".text"
be clobbered by an asm. No such register actually exists. Condition
codes are partly stored in the PSR and partly in the FSR. */
-#define ADDITIONAL_REGISTER_NAMES {"ccr", 0}
+#define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
/* How to renumber registers for dbx and gdb. */
#define ASM_OUTPUT_LABELREF(FILE,NAME) \
fprintf (FILE, "_%s", NAME)
-/* This is how to output an internal numbered label where
+/* This is how to output a definition of an internal numbered label where
PREFIX is the class of label and NUM is the number within the class. */
#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
fprintf (FILE, "%s%d:\n", PREFIX, NUM)
+/* This is how to output a reference to an internal numbered label where
+ PREFIX is the class of label and NUM is the number within the class. */
+/* FIXME: This should be used throughout gcc, and documented in the texinfo
+ files. There is no reason you should have to allocate a buffer and
+ `sprintf' to reference an internal label (as opposed to defining it). */
+
+#define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
+ fprintf (FILE, "%s%d", PREFIX, NUM)
+
/* This is how to store into the string LABEL
the symbol_ref name of an internal numbered label where
PREFIX is the class of label and NUM is the number within the class.
They reject 99e9999, but accept inf. */
#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
{ \
- if (REAL_VALUE_ISINF (VALUE)) \
- fprintf (FILE, "\t.double 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
- else if (REAL_VALUE_ISNAN (VALUE) \
- || REAL_VALUE_MINUS_ZERO (VALUE)) \
+ if (REAL_VALUE_ISINF (VALUE) \
+ || REAL_VALUE_ISNAN (VALUE) \
+ || REAL_VALUE_MINUS_ZERO (VALUE)) \
{ \
- union { double d; long l[2];} t; \
- t.d = (VALUE); \
- fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t.l[0], t.l[1]); \
+ long t[2]; \
+ REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
+ fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
+ ASM_LONG, t[0], ASM_LONG, t[1]); \
} \
else \
fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
#define ASM_OUTPUT_FLOAT(FILE,VALUE) \
{ \
- if (REAL_VALUE_ISINF (VALUE)) \
- fprintf (FILE, "\t.single 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
- else if (REAL_VALUE_ISNAN (VALUE) \
- || REAL_VALUE_MINUS_ZERO (VALUE)) \
+ if (REAL_VALUE_ISINF (VALUE) \
+ || REAL_VALUE_ISNAN (VALUE) \
+ || REAL_VALUE_MINUS_ZERO (VALUE)) \
{ \
- union { float f; long l;} t; \
- t.f = (VALUE); \
- fprintf (FILE, "\t.word 0x%lx\n", t.l); \
+ long t; \
+ REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
+ fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
} \
else \
fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
/* This is how to output an assembler line defining an `int' constant. */
#define ASM_OUTPUT_INT(FILE,VALUE) \
-( fprintf (FILE, "\t.word "), \
+( fprintf (FILE, "\t%s\t", ASM_LONG), \
output_addr_const (FILE, (VALUE)), \
fprintf (FILE, "\n"))
/* Likewise for `char' and `short' constants. */
#define ASM_OUTPUT_SHORT(FILE,VALUE) \
-( fprintf (FILE, "\t.half "), \
+( fprintf (FILE, "\t%s\t", ASM_SHORT), \
output_addr_const (FILE, (VALUE)), \
fprintf (FILE, "\n"))
#define ASM_OUTPUT_CHAR(FILE,VALUE) \
-( fprintf (FILE, "\t.byte "), \
+( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
output_addr_const (FILE, (VALUE)), \
fprintf (FILE, "\n"))
/* This is how to output an assembler line for a numeric constant byte. */
#define ASM_OUTPUT_BYTE(FILE,VALUE) \
- fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
+ fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
/* This is how to output an element of a case-vector that is absolute. */
#define TARGET_CR 015
#define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
- ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
+ ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' \
+ || (CHAR) == '(')
/* Print operand X (an rtx) in assembler syntax to file FILE.
CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
extern char *singlemove_string ();
extern char *output_move_double ();
+extern char *output_move_quad ();
extern char *output_fp_move_double ();
+extern char *output_fp_move_quad ();
extern char *output_block_move ();
extern char *output_scc_insn ();
extern char *output_cbranch ();
extern char *output_return ();
-extern char *output_floatsisf2 ();
-extern char *output_floatsidf2 ();
/* Defined in flags.h, but insn-emit.c does not include flags.h. */
git://gcc.gnu.org / gcc.git / blobdiff