/* Definitions of target machine for GNU compiler. Gmicro (TRON) version.
- Copyright (C) 1987, 88, 89, 95, 96, 1997 Free Software Foundation, Inc.
+ Copyright (C) 1987, 1988, 1989, 1995, 1996, 1997, 1998, 1999, 2000
+ Free Software Foundation, Inc.
Contributed by Masanobu Yuhara, Fujitsu Laboratories LTD.
(yuhara@flab.fujitsu.co.jp)
An empty string NAME is used to identify the default VALUE. */
#define TARGET_SWITCHES \
- { { "g300", 1}, \
- { "g200", 2}, \
- { "g100", 4}, \
- { "fpu", 8}, \
- { "soft-float", -8}, \
- { "rtd", 0x10}, \
- { "no-rtd", -0x10}, \
- { "regparm", 0x20}, \
- { "no-regparm", -0x20}, \
+ { { "g300", 1, _("Compile for Gmicro/300")}, \
+ { "g200", 2, _("Compile for Gmicro/200")}, \
+ { "g100", 4, _("Compile for Gmicro/100")}, \
+ { "fpu", 8, _("Use floating point co-processor")}, \
+ { "soft-float", -8, \
+ _("Do not use floating point co-processor")}, \
+ { "rtd", 0x10, _("Alternate calling convention")}, \
+ { "no-rtd", -0x10, _("Use normal calling convention")}, \
+ { "regparm", 0x20, NULL}, \
+ { "no-regparm", -0x20, NULL}, \
#if 0 /* Since we don't define PCC_BITFIELD_TYPE_MATTERS or use a large
STRUCTURE_SIZE_BOUNDARY, we must have bitfield instructions. */
- { "bitfield", 0x40}, \
- { "no-bitfield", -0x40}, \
+ { "bitfield", 0x40, _("Use bitfield instructions")}, \
+ { "no-bitfield", -0x40, \
+ _("Do not use bitfield instructions")}, \
#endif
- { "newreturn", 0x80}, \
- { "no-newreturn", -0x80}, \
- { "force-smov", 0x100}, \
- { "no-force-smov", -0x100}, \
- { "", TARGET_DEFAULT}}
+ { "newreturn", 0x80, _("Use alternative return sequence")}, \
+ { "no-newreturn", -0x80, _("Use normal return sequence")}, \
+ { "force-smov", 0x100, _("Always use string instruction")}, \
+ { "no-force-smov", -0x100, \
+ _("Use string instruction when appropriate")}, \
+ { "", TARGET_DEFAULT, NULL}}
/* Blow away G100 flag silently off TARGET_fpu (since we can't clear
Unaligned data is allowed on Gmicro, though the access is slow. */
#define STRICT_ALIGNMENT 1
-#define SLOW_UNALIGNED_ACCESS 1
+#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
/* Make strings word-aligned so strcpy from constants will be faster. */
#define CONSTANT_ALIGNMENT(EXP, ALIGN) \
/* This Macro is not defined now.
#define CONDITIONAL_REGISTER_USAGE */
-/* The Gmicro has no overlapping register */
-/* #define OVERLAPPING_REGNO_P(REGNO) */
-
-/* #define INSN_CLOBBERS_REGNO_P(INSN,REGNO) */
-/* #define PRESERVE_DEATH_INFO_REGNO_P(REGNO) */
-
/* Return number of consecutive hard regs needed starting at reg REGNO
to hold something of mode MODE.
This is ordinarily the length in words of a value of mode MODE
/* Define how to find the value returned by a library function
assuming the value has mode MODE. */
-#define LIBCALL_VALUE(MODE) \
- (gen_rtx (REG, (MODE), \
- ((TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode)) ? 16 : 0)))
+#define LIBCALL_VALUE(MODE) \
+ (gen_rtx_REG ((MODE), \
+ ((TARGET_FPU && ((MODE) == SFmode || (MODE) == DFmode)) \
+ ? 16 : 0)))
/* 1 if N is a possible register number for a function value.
It exists only to test register calling conventions. */
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
-((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
+((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0)
/* For an arg passed partly in registers and partly in memory,
this is the number of registers used.
{ register int regno; \
register int mask = 0; \
register int nregs = 0; \
- static char *reg_names[] = REGISTER_NAMES; \
+ static const char * const reg_names[] = REGISTER_NAMES; \
extern char call_used_regs[]; \
int fsize = ((SIZE) + 3) & -4; \
for (regno = 0; regno < 16; regno++) \
register int nregs, nfregs; \
int offset, foffset; \
extern char call_used_regs[]; \
- static char *reg_names[] = REGISTER_NAMES; \
+ static const char * const reg_names[] = REGISTER_NAMES; \
int fsize = ((SIZE) + 3) & -4; \
FUNCTION_EXTRA_EPILOGUE (FILE, SIZE); \
nfregs = 0; fmask = 0; \
else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 0) == frame_pointer_rtx) \
{ rtx other_reg = XEXP (ADDR, 1); \
offset = 0; \
- regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
+ regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
else if (GET_CODE (ADDR) == PLUS && XEXP (ADDR, 1) == frame_pointer_rtx) \
{ rtx other_reg = XEXP (ADDR, 0); \
offset = 0; \
- regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
+ regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
else if (GET_CODE (ADDR) == PLUS \
&& GET_CODE (XEXP (ADDR, 0)) == PLUS \
&& XEXP (XEXP (ADDR, 0), 0) == frame_pointer_rtx \
&& GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
{ rtx other_reg = XEXP (XEXP (ADDR, 0), 1); \
offset = INTVAL (XEXP (ADDR, 1)); \
- regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
+ regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
else if (GET_CODE (ADDR) == PLUS \
&& GET_CODE (XEXP (ADDR, 0)) == PLUS \
&& XEXP (XEXP (ADDR, 0), 1) == frame_pointer_rtx \
&& GET_CODE (XEXP (ADDR, 1)) == CONST_INT) \
{ rtx other_reg = XEXP (XEXP (ADDR, 0), 0); \
offset = INTVAL (XEXP (ADDR, 1)); \
- regs = gen_rtx (PLUS, Pmode, stack_pointer_rtx, other_reg); } \
+ regs = gen_rtx_PLUS (Pmode, stack_pointer_rtx, other_reg); } \
if (offset >= 0) \
{ int regno; \
extern char call_used_regs[]; \
\f
/* Addressing modes, and classification of registers for them. */
-/* #define HAVE_POST_INCREMENT */
-/* #define HAVE_POST_DECREMENT */
+/* #define HAVE_POST_INCREMENT 0 */
+/* #define HAVE_POST_DECREMENT 0 */
-/* #define HAVE_PRE_DECREMENT */
-/* #define HAVE_PRE_INCREMENT */
+/* #define HAVE_PRE_DECREMENT 0 */
+/* #define HAVE_PRE_INCREMENT 0 */
/* Macros to check register numbers against specific register classes. */
/* #define CASE_VECTOR_MODE HImode */
#define CASE_VECTOR_MODE SImode
-/* Define this if the tablejump instruction expects the table
- to contain offsets from the address of the table.
- Do not define this if the table should contain absolute addresses. */
-#define CASE_VECTOR_PC_RELATIVE
+/* Define as C expression which evaluates to nonzero if the tablejump
+ instruction expects the table to contain offsets from the address of the
+ table.
+ Do not define this if the table should contain absolute addresses. */
+#define CASE_VECTOR_PC_RELATIVE 1
/* Specify the tree operation to be used to convert reals to integers. */
#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
/* We assume that the store-condition-codes instructions store 0 for false
and some other value for true. This is the value stored for true. */
-/* #define STORE_FLAG_VALUE -1 */
+/* #define STORE_FLAG_VALUE (-1) */
/* When a prototype says `char' or `short', really pass an `int'. */
-#define PROMOTE_PROTOTYPES
+#define PROMOTE_PROTOTYPES 1
/* Specify the machine mode that pointers have.
After generation of rtl, the compiler makes no further distinction
/* This is how to output an element of a case-vector that is relative. */
-#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
+#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
fprintf (FILE, "\t.data.w L%d-L%d\n", VALUE, REL)
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