+2007-07-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * c-lex.c (c_lex_with_flags, lex_string): Constify.
+ * c-ppoutput.c (print_line, pp_dir_change): Likewise.
+ * c-typeck.c (free_all_tagged_tu_seen_up_to): Likewise.
+ * cfg.c (bb_copy_original_hash, bb_copy_original_eq): Likewise.
+ * cfgloop.c (loop_exit_hash, loop_exit_eq): Likewise.
+ * ddg.c (compare_sccs): Likewise.
+ * df-scan.c (df_ref_compare, df_mw_compare): Likewise.
+ * dfp.c (decimal_real_from_string, decimal_to_decnumber,
+ decimal_to_binary, decimal_do_compare, decimal_real_to_decimal,
+ decimal_do_fix_trunc, decimal_real_to_integer,
+ decimal_real_to_integer2, decimal_real_maxval): Likewise.
+ * dse.c (const_group_info_t): New.
+ (invariant_group_base_eq, invariant_group_base_hash): Constify.
+ * dwarf2out.c (const_dw_die_ref): New.
+ (decl_die_table_hash, decl_die_table_eq, file_info_cmp): Constify.
+ * tree-browser.c (TB_parent_eq): Likewise.
+ * unwind-dw2-fde.c (__register_frame_info_bases,
+ __deregister_frame_info_bases, fde_unencoded_compare, fde_split,
+ add_fdes, linear_search_fdes, binary_search_unencoded_fdes):
+ Likewise.
+ * unwind-dw2-fde.h (get_cie, next_fde): Likewise.
+ * unwind-dw2.c (uw_frame_state_for): Likewise.
+ * value-prof.c (histogram_hash, histogram_eq): Likewise.
+ * value-prof.h (const_histogram_value): New.
+
+2007-07-25 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.c (machine_function): Add
+ initialized_mips16_gp_pseudo_p.
+ (mips16_gp_pseudo_reg): Do not emit the initialization of
+ mips16_gp_pseudo_rtx when being called from the gimple cost-
+ calculation routines; emit it on the first use outside those
+ routines.
+
+2007-07-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
+
+ * coretypes.h (const_bitmap, const_rtx, const_rtvec, const_tree):
+ New.
+
+ * rtl.h (RTL_CHECK1, RTL_CHECK2, RTL_CHECKC1, RTL_CHECKC2,
+ RTVEC_ELT, XWINT, XCWINT, XCMWINT, XCNMPRV, BLOCK_SYMBOL_CHECK,
+ RTL_FLAG_CHECK1, RTL_FLAG_CHECK2, RTL_FLAG_CHECK3,
+ RTL_FLAG_CHECK4, RTL_FLAG_CHECK5, RTL_FLAG_CHECK6,
+ RTL_FLAG_CHECK7, RTL_FLAG_CHECK8, LABEL_KIND, SET_LABEL_KIND):
+ Preserve const-ness of parameters through use of __typeof(),
+ also constify and tidy.
+
+ * tree.h (TREE_CHECK, TREE_NOT_CHECK, TREE_CHECK2,
+ TREE_NOT_CHECK2, TREE_CHECK3, TREE_NOT_CHECK3, TREE_CHECK4,
+ NON_TREE_CHECK4, TREE_CHECK5, TREE_NOT_CHECK5,
+ CONTAINS_STRUCT_CHECK, TREE_CLASS_CHECK, TREE_RANGE_CHECK,
+ OMP_CLAUSE_SUBCODE_CHECK, OMP_CLAUSE_RANGE_CHECK, EXPR_CHECK,
+ GIMPLE_STMT_CHECK, NON_TYPE_CHECK, TREE_VEC_ELT_CHECK,
+ PHI_NODE_ELT_CHECK, OMP_CLAUSE_ELT_CHECK, TREE_OPERAND_CHECK,
+ TREE_OPERAND_CHECK_CODE, GIMPLE_STMT_OPERAND_CHECK,
+ TREE_RTL_OPERAND_CHECK, TREE_CHAIN, TREE_TYPE): Likewise.
+
+2007-07-25 Julian Brown <julian@codesourcery.com>
+ Mark Shinwell <shinwell@codesourcery.com>
+
+ * config/alpha/alpha.c (alpha_mangle_fundamental_type): Rename to...
+ (alpha_mangle_type): This.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/arm/arm-protos.h (arm_mangle_type): Add prototype.
+ * config/arm/arm.c (TARGET_MANGLE_TYPE): Define target hook.
+ (arm_init_neon_builtins): Fix comment.
+ (arm_mangle_map_entry): New.
+ (arm_mangle_map): New.
+ (arm_mangle_type): New.
+ * config/i386/i386.c (ix86_mangle_fundamental_type): Rename to...
+ (ix86_mangle_type): This. Use TYPE_MAIN_VARIANT and restrict
+ mangled types to VOID_TYPE, BOOLEAN_TYPE, INTEGER_TYPE, REAL_TYPE.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/ia64/ia64.c (ia64_mangle_fundamental_type): Rename to...
+ (ia64_mangle_type): This. Use TYPE_MAIN_VARIANT and restrict
+ mangled types to VOID_TYPE, BOOLEAN_TYPE, INTEGER_TYPE, REAL_TYPE.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/rs6000/rs6000.c (rs6000_mangle_fundamental_type): Rename
+ to...
+ (rs6000_mangle_type): This. Use TYPE_MAIN_VARIANT.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/s390/s390.c (s390_mangle_fundamental_type): Rename to...
+ (s390_mangle_type): This.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * config/sparc/sparc.c (sparc_mangle_fundamental_type): Rename to...
+ (sparc_mangle_type): This.
+ (TARGET_MANGLE_FUNDAMENTAL_TYPE): Don't define.
+ (TARGET_MANGLE_TYPE): Define this instead.
+ * cp/mangle.c (write_type): Call mangle_type target hook on all
+ types before mangling. Use original type, not main variant, as
+ argument.
+ * target-def.h (TARGET_MANGLE_FUNDAMENTAL_TYPE): Rename hook to...
+ (TARGET_MANGLE_TYPE): This.
+ * target.h (gcc_target): Rename mangle_fundamental_type to
+ mangle_type.
+ * doc/tm.texi (TARGET_MANGLE_FUNDAMENTAL_TYPE): Rename section to...
+ (TARGET_MANGLE_TYPE): This. Note slightly different semantics.
+
+2007-07-25 Julian Brown <julian@codesourcery.com>
+ Paul Brook <paul@codesourcery.com>
+ Joseph Myers <joseph@codesourcery.com>
+ Mark Shinwell <shinwell@codesourcery.com>
+
+ * Makefile.in (TEXI_GCC_FILES): Add arm-neon-intrinsics.texi.
+ * config.gcc (arm*-*-*): Add arm_neon.h to extra headers.
+ (with_fpu): Allow --with-fpu=neon.
+ * config/arm/aof.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
+ * config/arm/aout.h (ADDITIONAL_REGISTER_NAMES): Add Q0-Q15.
+ * config/arm/arm-modes.def (EI, OI, CI, XI): New modes.
+ * config/arm/arm-protos.h (neon_immediate_valid_for_move)
+ (neon_immediate_valid_for_logic, neon_output_logic_immediate)
+ (neon_pairwise_reduce, neon_expand_vector_init, neon_reinterpret)
+ (neon_emit_pair_result_insn, neon_disambiguate_copy)
+ (neon_vector_mem_operand, neon_struct_mem_operand, output_move_quad)
+ (output_move_neon): Add prototypes.
+ * config/arm/arm.c (FL_NEON): New flag for NEON processor capability.
+ (all_fpus): Add FPUTYPE_NEON.
+ (fp_model_for_fpu): Add NEON field.
+ (arm_return_in_memory): Return vectors <= 16 bytes in ARM registers.
+ (arm_arg_partial_bytes): Allow NEON vectors to be passed partially
+ in registers.
+ (arm_legitimate_address_p): Don't support fancy addressing for NEON
+ structure moves.
+ (thumb2_legitimate_address_p): Likewise.
+ (neon_valid_immediate): Recognize and prepare constants suitable for
+ NEON instructions.
+ (neon_immediate_valid_for_move): New function. Recognize and prepare
+ immediates for NEON move instructions.
+ (neon_immediate_valid_for_logic): New function. Recognize and
+ prepare immediates for NEON logic instructions.
+ (neon_output_logic_immediate): New function. Create asm string
+ suitable for outputting immediate logic instructions.
+ (neon_pairwise_reduce): New function. Implement reduction using
+ pairwise operations.
+ (neon_expand_vector_init): New function. Expand a (possibly
+ non-constant) vector initialization.
+ (neon_vector_mem_operand): New function. Memory operands supported
+ for quad-word loads/stores to/from ARM or NEON registers. Don't
+ allow base+offset addressing for core regs.
+ (neon_struct_mem_operand): New function. Valid mems for NEON
+ structure moves.
+ (coproc_secondary_reload_class): Enable NEON registers to be loaded
+ from neon_vector_mem_operand addresses without a secondary register.
+ (add_minipool_forward_ref): Handle >8-byte minipool entries.
+ (add_minipool_backward_ref): Likewise.
+ (dump_minipool): Likewise.
+ (push_minipool_fix): Likewise.
+ (output_move_quad): New function. Output quad-word moves, loads and
+ stores using ARM registers.
+ (output_move_vfp): Add support for vectors in VFP (NEON) D
+ registers.
+ (output_move_neon): Output a NEON load/store to/from a quadword
+ register.
+ (arm_print_operand): Implement new codes:
+ - 'c' for unadorned integers (without a # sign).
+ - 'J', 'K' for reg+2/reg+3, reg+3/reg+2 in little/big-endian
+ mode.
+ - 'e', 'f' for the low and high D parts of a NEON Q register.
+ - 'q' outputs a NEON Q register.
+ - 'h' outputs ranges of D registers for VLDM/VSTM etc.
+ - 'T' prints NEON opcode features from a coded bitmask.
+ - 'F' is similar to T, but signed/unsigned codes both print as
+ 'i'.
+ - 't' is similar to T, but 'u' is printed instead of 'p'.
+ - 'O' prints 'r' if NEON instruction should perform rounding (as
+ specified by bitmask), else prints nothing.
+ - '#' is a punctuation character to stop operand numbers from
+ running together with following digits in the assembler
+ strings for instructions (when using mode attributes).
+ (arm_assemble_integer): Handle extra NEON vector modes. Permute
+ constant vectors in big-endian mode, where necessary.
+ (arm_hard_regno_mode_ok): Allow vectors in VFP/NEON registers.
+ Handle EI, OI, CI, XI modes.
+ (ashlv4hi3, ashlv2si3, lshrv4hi3, lshrv2si3, ashrv4hi3)
+ (ashrv2si3): Rename IWMMXT2_BUILTINs to...
+ (ashlv4hi3_iwmmxt, ashlv2si3_iwmmxt, lshrv4hi3_iwmmxt)
+ (lshrv2si3_iwmmxt, ashrv4hi3_iwmmxt, ashrv2si3_iwmmxt): New names.
+ (neon_builtin_type_bits): Add enumeration, one bit for each vector
+ type.
+ (v8qi_UP, v4hi_UP, v2si_UP, v2sf_UP, di_UP, v16qi_UP, v8hi_UP)
+ (v4si_UP, v4sf_UP, v2di_UP, ti_UP, ei_UP, oi_UP, UP): Define macros
+ to turn v8qi, etc. into bits defined above.
+ (neon_itype): New enumeration. Classifications of NEON builtins.
+ (neon_builtin_datum): Define struct. Contains information about
+ a single builtin (with multiple modes).
+ (CF): Define helper macro for...
+ (VAR1...VAR10): Define builtins with a type, name and 1-10 different
+ modes.
+ (neon_builtin_data): New array. Define information about builtins
+ for use during initialization/expansion.
+ (arm_init_neon_builtins): New function.
+ (arm_init_builtins): Call arm_init_neon_builtins if TARGET_NEON is
+ true.
+ (neon_builtin_compare): New function.
+ (locate_neon_builtin_icode): New function. Find an insn code for a
+ builtin given a function code for that builtin. Also return type of
+ builtin (NEON_BINOP, NEON_UNOP etc.).
+ (builtin_arg): New enumeration. Types of arguments for builtins.
+ (arm_expand_neon_args): New function. Expand a generic NEON builtin.
+ Takes a variable argument list of builtin_arg types, terminated by
+ NEON_ARG_STOP.
+ (arm_expand_neon_builtin): New function. Expand a NEON builtin.
+ (neon_reinterpret): New function. Expand NEON reinterpret intrinsic.
+ (neon_emit_pair_result_insn): New function. Support returning pairs
+ of vectors via a pointer.
+ (neon_disambiguate_copy): New function. Set up operands for a
+ multi-word copy such that registers do not get clobbered.
+ (arm_expand_builtin): Call arm_expand_neon_builtin if fcode >=
+ ARM_BUILTIN_NEON_BASE.
+ (arm_file_start): Set float-abi attribute for NEON.
+ (arm_vector_mode_supported_p): Enable NEON vector modes.
+ (arm_mangle_map_entry): New.
+ (arm_mangle_map): New.
+ (arm_mangle_vector_type): New.
+ * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Define __ARM_NEON__
+ when appropriate.
+ (TARGET_NEON): New macro. Target supports NEON.
+ (fputype): Add FPUTYPE_NEON.
+ (UNITS_PER_SIMD_WORD): Define. Allow quad-word registers to be used
+ for vectorization based on command-line arg.
+ (NEON_REGNO_OK_FOR_NREGS): Define.
+ (VALID_NEON_DREG_MODE, VALID_NEON_QREG_MODE)
+ (VALID_NEON_STRUCT_MODE): Define.
+ (PRINT_OPERAND_PUNCT_VALID_P): '#' is valid punctuation.
+ (arm_builtins): Add ARM_BUILTIN_NEON_BASE.
+ * config/arm/arm.md (VUNSPEC_POOL_16): Insert constant for unspec.
+ (consttable_16): Add pattern for outputting 16-byte minipool
+ entries.
+ (movv2si, movv4hi, movv8qi): Remove blank expanders (redefined in
+ vec-common.md).
+ (vec-common.md, neon.md): Include md files.
+ * config/arm/arm.opt (mvectorize-with-neon-quad): Add option.
+ * config/arm/constraints.md (constraint "Dn", "Dl", "DL"): Define.
+ (memory_constraint "Ut", "Un", "Us"): Define.
+ * config/arm/iwmmxt.md (VMMX, VSHFT): New mode macros.
+ (MMX_char): New mode attribute.
+ (addv8qi3, addv4hi3, addv2si3): Remove. Replace with...
+ (*add<mode>3_iwmmxt): New insn pattern.
+ (subv8qi3, subv4hi3, subv2si3): Remove. Replace with...
+ (*sub<mode>3_iwmmxt): New insn pattern.
+ (mulv4hi3): Rename to...
+ (*mulv4hi3_iwmmxt): This.
+ (smaxv8qi3, smaxv4hi3, smaxv2si3, umaxv8qi3, umaxv4hi3)
+ (umaxv2si3, sminv8qi3, sminv4hi3, sminv2si3, uminv8qi3)
+ (uminv4hi3, uminv2si3): Remove. Replace with...
+ (*smax<mode>3_iwmmxt, *umax<mode>3_iwmmxt, *smin<mode>3_iwmmxt)
+ (*umin<mode>3_iwmmxt): These.
+ (ashrv4hi3, ashrv2si3, ashrdi3_iwmmxt): Replace with...
+ (ashr<mode>3_iwmmxt): This new pattern.
+ (lshrv4hi3, lshrv2si3, lshrdi3_iwmmxt): Replace with...
+ (lshr<mode>3_iwmmxt): This new pattern.
+ (ashlv4hi3, ashlv2si3, ashldi3_iwmmxt): Replace with...
+ (ashl<mode>3_iwmmxt): This new pattern.
+ * config/arm/neon-docgen.ml: New file. Generate documentation for
+ intrinsics.
+ * config/arm/neon-gen.ml: New file. Generate arm_neon.h header.
+ * config/arm/arm_neon.h: New (autogenerated).
+ * config/arm/neon-testgen.ml: New file. Generate NEON tests
+ automatically.
+ * config/arm/neon.md: New file. Define NEON instructions.
+ * config/arm/neon.ml: New file. Abstract description of NEON
+ instructions, used to generate arm_neon.h header, documentation and
+ tests.
+ * config/arm/t-arm (MD_INCLUDES): Add vec-common.md, neon.md.
+ * vec-common.md: New file. Shared parts for iWMMXt and NEON vector
+ support.
+ * doc/extend.texi (ARM Built-in Functions): Rename and remove
+ extraneous comma.
+ (ARM NEON Intrinsics): New subsection.
+ * doc/arm-neon-intrinsics.texi: New (autogenerated).
+
+2007-07-25 Danny Smith <dannysmith@users.sourceforge.net>
+
+ * config/i386/i386-protos.h (i386_pe_asm_file_end): Remove
+ prototype.
+
+2007-07-24 Jan Hubicka <jh@suse.cz>
+
+ * regclass.c (move_table): New type.
+ (move_cost, may_move_in_cost, may_move_out_cost): Use it.
+ (init_move_cost): Break out from ...
+ (init_reg_sets_1): ... here; simplify computation of
+ have_regs-of_mode and contains_reg_of_mode.
+ (record_reg_classes): Unswitch internal loops.
+ (copy_cost): Trigger lazy initialization of move cost
+ (record_address_regs): Likewise.
+
+2007-07-24 Daniel Berlin <dberlin@dberlin.org>
+
+ * config/darwin.c (darwin_override_options): Don't force on
+ flag_var_tracking_uninit when no debug info is requested.
+
+2007-07-25 Zdenek Dvorak <dvorakz@suse.cz>
+
+ * cfgloop.c (init_loops_structure): New function.
+ (flow_loops_find): Create root of the loop tree unconditionally.
+
+2007-07-24 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * tree-ssa-ccp.c (fold_const_aggregate_ref): Use fold_convert.
+
+2007-07-24 Jan Hubicka <jh@suse.cz>
+
+ * caller-save.c: Include ggc.h, gt-caller-save.h
+ (reg_save_code, reg_restore_code): Rename to ...
+ (cached_reg_save_code, cached_reg_restore_code): ... those.
+ (savepat, restpat, test_reg, test_mem, saveinsn, restinsn): New.
+ (reg_save_code, reg_restore_code): New functions.
+ (init_caller_save): Do not intialize
+ reg_save_code/reg_restore_code tables.
+ * Makeifle.in: (gt-caller-save.h): New.
+
+2007-07-24 Andreas Krebbel <krebbel1@de.ibm.com>
+
+ * tree-ssa-ifcombine.c (ifcombine_ifandif): Use a ONE operand
+ with the mode of the original operand instead of
+ integer_one_node.
+
+2007-07-23 Jan Hubicka <jH@suse.cz>
+
+ * i386.c (ix86_secondary_memory_needed): Break out to...
+ (inline_secondary_memory_needed): ... here.
+ (ix86_memory_move_cost): Break out to ...
+ (inline_memory_move_cost): ... here; add support for IN value of 2 for
+ maximum of input and output; fix handling of Q_REGS on 64bit.
+ (ix86_secondary_memory_needed): Microoptimize.
+
+2007-07-23 Sebastian Pop <sebpop@gmail.com>
+
+ * tree-data-ref.c (find_vertex_for_stmt, create_rdg_edge_for_ddr,
+ create_rdg_edges_for_scalar, create_rdg_edges, create_rdg_vertices,
+ stmts_from_loop, known_dependences_p, build_rdg): New.
+ * tree-data-ref.h: Depends on graphds.h.
+ (rdg_vertex, RDGV_STMT, rdg_dep_type, rdg_edge, RDGE_TYPE): New.
+ (build_rdg): Declared.
+ * Makefile.in (TREE_DATA_REF_H): Depends on graphds.h.
+
+2007-07-23 Daniel Berlin <dberlin@dberlin.org>
+
+ * tree-ssa-propagate.c (valid_gimple_expression_p): Match up with
+ ccp_min_invariant.
+
+2007-07-23 Peter Bergner <bergner@vnet.ibm.com>
+ Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/PR28690
+ * optabs.c (expand_binop): (emit_cmp_and_jump_insns): Allow EQ compares.
+ * rtlanal.c (commutative_operand_precedence): Prefer both REG_POINTER
+ and MEM_POINTER operands over REG and MEM operands.
+ (swap_commutative_operands_p): Change return value to bool.
+ * rtl.h: Update the corresponding prototype.
+ * tree-ssa-address.c (gen_addr_rtx): Use simplify_gen_binary
+ instead of gen_rtx_PLUS.
+ * simplify-rtx.c (simplify_plus_minus_op_data_cmp): Change return
+ value to bool. Change function arguments to rtx's and update code
+ to match.
+ (simplify_plus_minus): Update the simplify_plus_minus_op_data_cmp
+ calls to match the new declaration.
+ * simplify-rtx.c (simplify_associative_operation): Don't
+ reorder simplify_binary_operation arguments.
+
+2007-07-23 Richard Sandiford <richard@codesourcery.com>
+
+ * config/mips/mips.c (override_options): Use mips_costs to derive
+ the default branch cost.
+ * config/mips/mips.h (BRANCH_COST): Use mips_branch_cost rather
+ than mips_costs.
+ * config/mips/mips.opt (mbranch-cost=): New option.
+ * doc/invoke.texi (-mbranch-cost): Document new MIPS option.
+
2007-07-23 Richard Sandiford <richard@codesourcery.com>
* config/mips/mips.h (GR_REG_CLASS_P, COP_REG_CLASS_P): Delete.
(SECONDARY_MEMORY_NEEDED): Delete commented-out definition.
- * config/mips/mips.c (mips_init_libfuncs): Use reg_class_subset_p
+ * config/mips/mips.c (mips_register_move_cost): Use reg_class_subset_p
instead of GR_REG_CLASS_P and COP_REG_CLASS_P.
2007-07-23 Richard Sandiford <richard@codesourcery.com>
git://gcc.gnu.org / gcc.git / blobdiff