+2022-08-26 liuhongt <hongtao.liu@intel.com>
+
+ PR target/106704
+ * config/i386/i386-builtin.def (BDESC): Add
+ CODE_FOR_avx_blendvpd256/CODE_FOR_avx_blendvps256 to
+ corresponding builtins.
+ * config/i386/i386.cc (ix86_gimple_fold_builtin):
+ Don't fold IX86_BUILTIN_PBLENDVB256, IX86_BUILTIN_BLENDVPS256,
+ IX86_BUILTIN_BLENDVPD256 w/o TARGET_AVX2.
+
+2022-08-25 Chenghua Xu <xuchenghua@loongson.cn>
+
+ Backported from master:
+ 2022-08-25 Chenghua Xu <xuchenghua@loongson.cn>
+
+ PR target/106459
+ * config/loongarch/loongarch.cc (loongarch_build_integer):
+ Use HOST_WIDE_INT.
+ * config/loongarch/loongarch.h (IMM_REACH): Likewise.
+ (HWIT_1U): New Defined.
+ (LU12I_OPERAND): Use HOST_WIDE_INT.
+ (LU32I_OPERAND): Likewise.
+ (LU52I_OPERAND): Likewise.
+ (HWIT_UC_0xFFF): Likwise.
+
+2022-08-24 Kewen Lin <linkw@linux.ibm.com>
+
+ Backported from master:
+ 2022-08-16 Kewen Lin <linkw@linux.ibm.com>
+
+ PR tree-optimization/106322
+ * tree-vect-stmts.cc (vectorizable_call): Don't allow
+ vect_emulated_vector_p type for both vectype_in and vectype_out.
+
+2022-08-24 Kewen.Lin <linkw@gcc.gnu.org>
+
+ Backported from master:
+ 2022-08-16 Kewen.Lin <linkw@gcc.gnu.org>
+
+ PR target/103353
+ * config/rs6000/mma.md (define_expand movoo): Move TARGET_MMA condition
+ check to preparation statements and add handlings for !TARGET_MMA.
+ (define_expand movxo): Likewise.
+
+2022-08-23 Tobias Burnus <tobias@codesourcery.com>
+
+ Backported from master:
+ 2022-08-19 Tobias Burnus <tobias@codesourcery.com>
+
+ * config/gcn/mkoffload.cc (main): Add dbgobj to files_to_cleanup.
+
+2022-08-23 Tobias Burnus <tobias@codesourcery.com>
+
+ Backported from master:
+ 2022-08-17 Tobias Burnus <tobias@codesourcery.com>
+
+ PR middle-end/106548
+ * omp-low.cc (lower_rec_input_clauses): Use build_outer_var_ref
+ for 'simd' linear-step values that are variable.
+
+2022-08-19 Release Manager
+
+ * GCC 12.2.0 released.
+
+2022-08-17 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ Backported from master:
+ 2022-08-04 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * config/s390/vector.md (V_HW_FT): New iterator.
+ * config/s390/vx-builtins.md (vsel<mode>): Use V_HW_FT instead
+ of V_HW.
+
+2022-08-12 Peter Bergner <bergner@linux.ibm.com>
+
+ Backported from master:
+ 2022-07-26 Peter Bergner <bergner@linux.ibm.com>
+
+ PR c/106016
+ * expr.cc (count_type_elements): Handle OPAQUE_TYPE.
+
+2022-08-11 Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com>
+
+ Backported from master:
+ 2022-07-25 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64.md (rbit<mode>2): Rename this ...
+ (@aarch64_rbit<mode>): ... to this and change it in...
+ (ffs<mode>2,ctz<mode>2): ... here.
+ (@aarch64_rev16<mode>): New.
+ * config/aarch64/aarch64-builtins.cc: (aarch64_builtins):
+ Define the following enum AARCH64_REV16, AARCH64_REV16L,
+ AARCH64_REV16LL, AARCH64_RBIT, AARCH64_RBITL, AARCH64_RBITLL.
+ (aarch64_init_data_intrinsics): New.
+ (aarch64_general_init_builtins): Add call to
+ aarch64_init_data_intrinsics.
+ (aarch64_expand_builtin_data_intrinsic): New.
+ (aarch64_general_expand_builtin): Add call to
+ aarch64_expand_builtin_data_intrinsic.
+ * config/aarch64/arm_acle.h (__clz, __clzl, __clzll, __cls, __clsl,
+ __clsll, __rbit, __rbitl, __rbitll, __rev, __revl, __revll, __rev16,
+ __rev16l, __rev16ll, __ror, __rorl, __rorll, __revsh): New.
+
+2022-08-10 Tobias Burnus <tobias@codesourcery.com>
+
+ Backported from master:
+ 2022-08-09 Tobias Burnus <tobias@codesourcery.com>
+
+ PR middle-end/106492
+ * omp-low.cc (lower_rec_input_clauses): Add missing folding
+ to data type of linear-clause list item.
+
+2022-08-10 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-08-10 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/106513
+ * gimple-ssa-store-merging.cc (do_shift_rotate): Use uint64_t
+ for head_marker.
+
+2022-08-10 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-08-08 Richard Biener <rguenther@suse.de>
+
+ PR lto/106540
+ PR lto/106334
+ * lto-streamer-in.cc (lto_read_tree_1): Use lto_input_tree_1
+ to input DECL_INITIAL, avoiding to commit drefs.
+
+2022-08-05 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove code
+ setting -mblock-ops-vector-pair. Back port patch from trunk on 8/3.
+
+2022-08-02 Peter Bergner <bergner@linux.ibm.com>
+
+ Backported from master:
+ 2022-07-25 Peter Bergner <bergner@linux.ibm.com>
+ Kewen Lin <linkw@linux.ibm.com>
+
+ PR testsuite/106345
+ * config/rs6000/rs6000.h (DRIVER_SELF_SPECS): Adjust -mdejagnu-cpu
+ to filter out all -mtune options.
+
+2022-08-02 Kewen Lin <linkw@linux.ibm.com>
+
+ Backported from master:
+ 2022-07-26 Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/106091
+ * config/rs6000/rs6000-p8swap.cc (replace_swapped_aligned_store): Copy
+ REG_EH_REGION when replacing one store insn having it.
+ (replace_swapped_aligned_load): Likewise.
+
+2022-07-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-07-29 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/106449
+ * omp-expand.cc (expand_omp_simd): Fix up handling of pointer
+ iterators in non-rectangular simd loops. Unshare fd->loops[i].n2
+ or n2 before regimplifying it inside of a condition.
+
+2022-07-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-07-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/106261
+ * cgraphunit.cc (cgraph_node::assemble_thunks_and_aliases): Don't
+ output asm thunks for -dx.
+
+2022-07-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-07-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/106144
+ * wide-int.cc (wi::shifted_mask): If end >= prec, return right after
+ emitting element for shift or if shift is 0 first element after start.
+ (wide_int_cc_tests): Add tests for equivalency of wi::mask and
+ wi::shifted_mask with 0 start.
+
+2022-07-27 David Malcolm <dmalcolm@redhat.com>
+
+ * json.cc (string::print): Fix escaping of '\'.
+
+2022-07-27 David Malcolm <dmalcolm@redhat.com>
+
+ * doc/invoke.texi (-fdump-analyzer-feasibility): Mention the
+ fpath.txt output.
+
+2022-07-27 Maciej W. Rozycki <macro@embecosm.com>
+
+ Backported from master:
+ 2022-07-27 Maciej W. Rozycki <macro@embecosm.com>
+
+ * config/riscv/riscv.md (stack_protect_set_<mode>): Remove
+ duplicate backslashes.
+
+2022-07-27 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-07-26 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/106189
+ * gimple-array-bounds.cc (array_bounds_checker::check_mem_ref):
+ Divide using offset_ints.
+
+2022-07-27 Joseph Myers <joseph@codesourcery.com>
+
+ Backported from master:
+ 2022-06-30 Joseph Myers <joseph@codesourcery.com>
+
+ PR lto/106129
+ * lto-wrapper.cc (find_option): Add argument start.
+ (merge_and_complain): Loop over existing_opt_index and
+ existing_opt2_index for Xassembler check. Update calls to
+ find_option.
+ (find_and_merge_options): Add argument first to determine whether
+ to merge options with those passed in *opts.
+ (run_gcc): Update calls to find_and_merge_options.
+
+2022-07-27 Andrew Pinski <apinski@marvell.com>
+
+ Backported from master:
+ 2022-07-09 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/106087
+ * tree-ssa-dce.cc (simple_dce_from_worklist): Check
+ to make sure the statement is only defining one operand.
+
+2022-07-27 Tamar Christina <tamar.christina@arm.com>
+
+ Backported from master:
+ 2022-07-08 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/106063
+ * match.pd: Do not apply pattern after veclower is not supported.
+
+2022-07-27 Alexandre Oliva <oliva@adacore.com>
+
+ Backported from master:
+ 2022-06-03 Alexandre Oliva <oliva@adacore.com>
+
+ PR tree-optimization/105665
+ PR tree-optimization/100810
+ * tree-ssa-loop-ivopts.cc
+ (ssa_name_maybe_undef_p, ssa_name_set_maybe_undef): New.
+ (ssa_name_any_use_dominates_bb_p, mark_ssa_maybe_undefs): New.
+ (find_ssa_undef): Check precomputed flag and intervening uses.
+ (tree_ssa_iv_optimize): Call mark_ssa_maybe_undefs.
+
+2022-07-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+ Backported from master:
+ 2022-07-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+ * config/rs6000/rtems.h (CPLUSPLUS_CPP_SPEC): Undef.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-07-19 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/106331
+ * builtins.cc (get_memory_rtx): Compute alignment from
+ the original address and set MEM_OFFSET to unknown when
+ we create a MEM_EXPR from the base object of the address.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-07-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/106131
+ * tree-ssa-sccvn.cc (vn_reference_lookup_3): Force alias-set
+ zero when offsetting the read looking through an aggregate
+ copy.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-29 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/106112
+ * tree-ssa-sccvn.cc (valueized_wider_op): Properly extend
+ a constant operand according to its type.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-20 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/106027
+ * fold-const.cc (fold_to_nonsharp_ineq_using_bound): Use the
+ type of the prevailing comparison for the new comparison type.
+ (fold_binary_loc): Use proper types for the A < X && A + 1 > Y
+ to A < X && A >= Y folding.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105971
+ * tree-ssa-alias.cc (refs_may_alias_p_2): Put bail-out for
+ FUNCTION_DECL and LABEL_DECL refs after decl-decl disambiguation
+ to leak less surprising alias results.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105969
+ * gimple-ssa-sprintf.cc (get_origin_and_offset_r): Avoid division
+ by zero in overflow check.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-14 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105965
+ * match.pd (view_convert CONSTRUCTOR): Handle single-element
+ CTOR case.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-14 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105946
+ * tree-ssa-uninit.cc (maybe_warn_pass_by_reference):
+ Do not look at arguments not specified in the function call.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-07-11 Richard Biener <rguenthert@suse.de>
+
+ PR target/105459
+ * config/i386/i386-options.cc (ix86_set_current_function):
+ Rebuild the target optimization node whenever necessary,
+ not only when the optimization node didn't change.
+
+2022-07-14 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Do
+ not generate block copies with vector pair instructions if we are
+ tuning for power10. Back port from master branch.
+
+2022-07-14 Surya Kumari Jangala <jskumari@linux.vnet.ibm.com>
+
+ Backported from master:
+ 2022-06-14 Surya Kumari Jangala <jskumari@linux.ibm.com>
+
+ PR rtl-optimization/105041
+ * regrename.cc (check_new_reg_p): Use nregs value from du chain.
+
+2022-07-11 Martin Jambor <mjambor@suse.cz>
+
+ Backported from master:
+ 2022-07-04 Martin Jambor <mjambor@suse.cz>
+
+ PR tree-optimization/105860
+ * tree-sra.cc (build_reconstructed_reference): Start expr
+ traversal only just below the outermost union.
+
+2022-07-10 Xi Ruoyao <xry111@xry111.site>
+
+ Backported from master:
+ 2022-07-10 Xi Ruoyao <xry111@xry111.site>
+
+ * config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w
+ instead of mul.d.
+
+2022-07-09 Roger Sayle <roger@nextmovesoftware.com>
+ Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/105930
+ * config/i386/i386.md (*<any_or>di3_doubleword): Split after
+ reload. Use rtx_equal_p to avoid creating memory-to-memory moves,
+ and emit NOTE_INSN_DELETED if operand[2] is zero (i.e. with -O0).
+
+2022-07-08 Lulu Cheng <chenglulu@loongson.cn>
+
+ Backported from master:
+ 2022-07-08 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/loongarch.cc (loongarch_compute_frame_info):
+ Modify fp_sp_offset and gp_sp_offset's calculation method,
+ when frame->mask or frame->fmask is zero, don't minus UNITS_PER_WORD
+ or UNITS_PER_FP_REG.
+
+2022-07-04 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/106114
+ * gimple-range-fold.cc (fold_using_range::relation_fold_and_or): Check
+ statement operands instead of GORI cache.
+
+2022-07-04 Roger Sayle <roger@nextmovesoftware.com>
+ Marek Polacek <polacek@redhat.com>
+ Segher Boessenkool <segher@kernel.crashing.org>
+ Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/105991
+ * config/rs6000/rs6000.md (rotl<mode>3_insert_3): Check that
+ exact_log2 doesn't return -1 (or zero).
+ (plus_xor): New code iterator.
+ (*rotl<mode>3_insert_3_<code>): New define_insn_and_split.
+
+2022-07-04 Xi Ruoyao <xry111@xry111.site>
+
+ Backported from master:
+ 2022-07-03 Xi Ruoyao <xry111@xry111.site>
+ Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/loongarch.cc (loongarch_check_zero_div_p):
+ New static function.
+ (loongarch_idiv_insns): Use loongarch_check_zero_div_p instead
+ of TARGET_CHECK_ZERO_DIV.
+ (loongarch_output_division): Likewise.
+ * common/config/loongarch/loongarch-common.cc
+ (TARGET_DEFAULT_TARGET_FLAGS): Remove unneeded hook.
+ * doc/invoke.texi: Update to match the new behavior.
+
+2022-07-03 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR target/106122
+ * config/i386/i386.md (peephole2): Avoid generating pop %esp
+ when optimizing for size.
+
+2022-07-02 Sergei Trofimovich <siarheit@google.com>
+
+ Backported from master:
+ 2022-06-29 Sergei Trofimovich <siarheit@google.com>
+
+ PR c++/106102
+ * system.h: Introduce INCLUDE_PTHREAD_H macros to include <pthread.h>.
+
+2022-07-01 Vladimir Makarov <vmakarov@gcc.gnu.org>
+
+ Backported from master:
+ 2022-05-28 Vladimir Makarov <vmakarov@gcc.gnu.org>
+
+ PR target/103722
+ * config/sh/sh.cc (sh_register_move_cost): Avoid cost "2" (which
+ is special) for various scenarios.
+
+2022-06-29 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-11 Richard Biener <rguenther@suse.de>
+
+ PR bootstrap/105551
+ * opts.cc (finish_options): Also disable var-tracking if
+ !DWARF2_DEBUGGING_INFO.
+
+2022-06-29 Lulu Cheng <chenglulu@loongson.cn>
+
+ Backported from master:
+ 2022-06-29 Lulu Cheng <chenglulu@loongson.cn>
+
+ PR target/106097
+ * config/loongarch/loongarch.cc (loongarch_build_integer):
+ Remove undefined behavior from code.
+
+2022-06-28 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-06-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/106032
+ * ifcvt.cc (noce_try_sign_mask): Punt if !t_unconditional, and
+ t may_trap_or_fault_p, even if it is cheap.
+
+2022-06-28 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-06-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/106030
+ * expr.cc (expand_cond_expr_using_cmove): Pass NULL_RTX instead of
+ temp to expand_operands if mode has been promoted.
+
+2022-06-28 Xi Ruoyao <xry111@xry111.site>
+
+ Backported from master:
+ 2022-06-28 Xi Ruoyao <xry111@xry111.site>
+
+ PR target/106096
+ * config/loongarch/loongarch.h (REG_CLASS_CONTENTS): Exclude
+ $r13 from SIBCALL_REGS.
+ * config/loongarch/loongarch.cc (loongarch_regno_to_class):
+ Change $r13 to JIRL_REGS.
+
+2022-06-24 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ Backported from master:
+ 2022-06-24 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * config/tilepro/gen-mul-tables.cc (tilegx_emit): Adjust loop
+ condition to avoid overflow.
+
+2022-06-23 Martin Liska <mliska@suse.cz>
+
+ Backported from master:
+ 2022-06-23 Martin Liska <mliska@suse.cz>
+
+ PR ipa/105600
+ * ipa-icf.cc (sem_item_optimizer::filter_removed_items):
+ Skip variables with body_removed.
+
+2022-06-23 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ Backported from master:
+ 2022-06-21 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ PR tree-optimization/105736
+ * tree-object-size.cc (addr_object_size): Return size_unknown
+ when object offset computation returns an error.
+
+2022-06-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ Backported from master:
+ 2022-06-15 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/105254
+ PR tree-optimization/105940
+ Revert:
+ * config/aarch64/aarch64.cc
+ (aarch64_vector_costs::determine_suggested_unroll_factor): Take a
+ loop_vec_info as argument. Restrict the unroll factor to values
+ that divide the VF.
+ (aarch64_vector_costs::finish_cost): Update call accordingly.
+
+2022-06-23 Kewen Lin <linkw@linux.ibm.com>
+
+ Backported from master:
+ 2022-06-14 Kewen Lin <linkw@linux.ibm.com>
+
+ PR tree-optimization/105940
+ * tree-vect-loop.cc (vect_analyze_loop_2): Move the place of
+ applying suggested_unroll_factor after start_over.
+
+2022-06-21 H.J. Lu <hjl.tools@gmail.com>
+
+ Backported from master:
+ 2022-06-20 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/105960
+ * config/i386/i386.cc (ix86_function_ok_for_sibcall): Return
+ false if PIC register is used when calling ifunc functions.
+
+2022-06-20 Uros Bizjak <ubizjak@gmail.com>
+
+ Backported from master:
+ 2022-06-17 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/105209
+ * config/alpha/alpha-protos.h (alpha_store_data_bypass_p): New.
+ * config/alpha/alpha.cc (alpha_store_data_bypass_p): New function.
+ (alpha_store_data_bypass_p_1): Ditto.
+ * config/alpha/ev4.md: Use alpha_store_data_bypass_p instead
+ of generic store_data_bypass_p.
+ (ev4_ist_c): Remove insn reservation.
+
+2022-06-20 Uros Bizjak <ubizjak@gmail.com>
+
+ Backported from master:
+ 2022-06-17 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/105970
+ * config/i386/i386.cc (ix86_function_arg): Assert that
+ the mode of pointer argumet is equal to ptr_mode, not Pmode.
+
+2022-06-19 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-06-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/105998
+ * varasm.cc (narrowing_initializer_constant_valid_p): Check
+ SCALAR_INT_MODE_P instead of INTEGRAL_MODE_P, also break on
+ ! INTEGRAL_TYPE_P and do the same check also on op{0,1}'s type.
+
+2022-06-19 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-06-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/105951
+ * tree-ssa-ccp.cc (optimize_atomic_bit_test_and,
+ optimize_atomic_op_fetch_cmp_0): Remember gimple_call_fn (call)
+ as last argument to the internal functions.
+ * builtins.cc (expand_ifn_atomic_bit_test_and): Adjust for the
+ extra call argument to ifns. If expand_atomic_fetch_op fails for the
+ lhs == NULL_TREE case, fall through into the optab code with
+ gen_reg_rtx (mode) as target. If second expand_atomic_fetch_op
+ fails, construct a CALL_EXPR and expand that.
+ (expand_ifn_atomic_op_fetch_cmp_0): Adjust for the extra call argument
+ to ifns. If expand_atomic_fetch_op fails, construct a CALL_EXPR and
+ expand that.
+
+2022-06-19 Jan Hubicka <jh@suse.cz>
+
+ Backported from master:
+ 2022-06-14 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/105739
+ * ipa-prop.cc (ipa_load_from_parm_agg): Punt on volatile loads.
+
+2022-06-16 Richard Earnshaw <rearnsha@arm.com>
+
+ Backported from master:
+ 2022-06-15 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/105981
+ * config/arm/arm.cc (gen_cpymem_ldrd_strd): Rename low_reg and hi_reg
+ to first_reg and second_reg respectively. Initialize them correctly
+ when generating big-endian code.
+
+2022-06-15 Simon Wright <simon@pushface.org>
+
+ Backported from master:
+ 2022-06-12 Simon Wright <simon@pushface.org>
+
+ PR target/104871
+ * config/darwin-driver.cc (darwin_find_version_from_kernel): If the OS
+ version is darwin20 (macOS 11) or greater, truncate the version to the
+ major number.
+
+2022-06-15 Mark Mentovai <mark@mentovai.com>
+
+ Backported from master:
+ 2022-06-12 Mark Mentovai <mark@mentovai.com>
+
+ * config/darwin-c.cc: Make -mmacosx-version-min more future-proof.
+
+2022-06-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ Backported from master:
+ 2022-05-29 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR target/105599
+ * config/darwin.h: Move versions-specific handling of multiply_defined
+ from SUBTARGET_DRIVER_SELF_SPECS to LINK_SPEC.
+
+2022-06-15 liuhongt <hongtao.liu@intel.com>
+
+ PR target/105953
+ * config/i386/sse.md (*avx_cmp<mode>3_ltint_not): Force_reg
+ operands[3].
+
+2022-06-14 H.J. Lu <hjl.tools@gmail.com>
+
+ Backported from master:
+ 2022-06-13 H.J. Lu <hjl.tools@gmail.com>
+
+ * common/config/i386/cpuinfo.h (get_available_features): Require
+ AVX for F16C and VAES.
+
+2022-06-14 Philipp Tomsich <philipp.tomsich@vrull.eu>
+
+ Backported from master:
+ 2022-06-02 Philipp Tomsich <philipp.tomsich@vrull.eu>
+
+ * config/riscv/riscv.cc (riscv_build_integer_1): Rewrite value as
+ (-1 << 31) for the single-bit case, when operating on (1 << 31)
+ in SImode.
+ * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): Allow for
+ any single-bit value, moving the special case for (1 << 31) to
+ riscv_build_integer_1 (in riscv.c).
+
+2022-06-08 Max Filippov <jcmvbkbc@gmail.com>
+
+ Backported from master:
+ 2022-06-08 Max Filippov <jcmvbkbc@gmail.com>
+
+ PR target/105879
+ * config/xtensa/xtensa.md (movdi): Rename 'first' and 'second'
+ to 'lowpart' and 'highpart' so that they match 'gen_lowpart' and
+ 'gen_highpart' bitwise semantics and fix order of highpart and
+ lowpart depending on target endianness.
+
+2022-06-08 liuhongt <hongtao.liu@intel.com>
+
+ PR target/105854
+ * config/i386/sse.md (ssse3_palignrdi): Change alternative 2
+ from Yv to Yw.
+
+2022-06-02 Philipp Tomsich <philipp.tomsich@vrull.eu>
+
+ Backported from master:
+ 2022-05-13 Philipp Tomsich <philipp.tomsich@vrull.eu>
+ Manolis Tsamis <manolis.tsamis@vrull.eu>
+
+ * config/riscv/riscv.h (CLZ_DEFINED_VALUE_AT_ZERO): Implement.
+ (CTZ_DEFINED_VALUE_AT_ZERO): Same.
+ * doc/sourcebuild.texi: add documentation for RISC-V specific
+ test target keywords
+
+2022-06-02 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105786
+ * tree-loop-distribution.cc
+ (loop_distribution::transform_reduction_loop): Only do strlen
+ replacement for integer type reductions.
+
+2022-06-02 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-27 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105726
+ * gimple-ssa-warn-restrict.cc (builtin_memref::set_base_and_offset):
+ Constrain array-of-flexarray case more.
+
+2022-06-02 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-24 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105711
+ * expmed.cc (extract_bit_field_as_subreg): Add op0_mode parameter
+ and use it.
+ (extract_bit_field_1): Pass down the mode of op0 to
+ extract_bit_field_as_subreg.
+
+2022-06-02 Martin Sebor <msebor@redhat.com>
+
+ Backported from master:
+ 2022-05-24 Martin Sebor <msebor@redhat.com>
+ Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105604
+ * gimple-ssa-sprintf.cc (set_aggregate_size_and_offset): Add comments.
+ (get_origin_and_offset_r): Remove null handling. Handle variable array
+ sizes.
+ (get_origin_and_offset): Handle null argument here. Simplify.
+ (alias_offset): Update comment.
+ * pointer-query.cc (field_at_offset): Update comment. Handle members
+ of variable-length types.
+
+2022-06-02 Vineet Gupta <vineetg@rivosinc.com>
+
+ Backported from master:
+ 2022-05-24 Vineet Gupta <vineetg@rivosinc.com>
+
+ * config/riscv/riscv.cc: (struct riscv_tune_param): Add
+ fmv_cost.
+ (rocket_tune_info): Add default fmv_cost 8.
+ (sifive_7_tune_info): Ditto.
+ (thead_c906_tune_info): Ditto.
+ (optimize_size_tune_info): Ditto.
+ (riscv_register_move_cost): Use fmv_cost for int<->fp moves.
+
+2022-05-30 Martin Jambor <mjambor@suse.cz>
+
+ Backported from master:
+ 2022-05-27 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/105639
+ * ipa-prop.cc (propagate_controlled_uses): Check type of the
+ constant before adding a LOAD reference.
+
+2022-05-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-05-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/105729
+ * fold-const.cc (fold_unary_loc): Don't optimize (X &) ((Y *) z + w)
+ to (X &) z + w if -fsanitize=null during GENERIC folding.
+
+2022-05-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-05-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/105714
+ * asan.cc (has_stmt_been_instrumented_p): For assignments which
+ are both stores and loads, return true only if both destination
+ and source have been instrumented.
+
+2022-05-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-05-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/105635
+ * pointer-query.cc (gimple_parm_array_size): Return NULL if var
+ doesn't have pointer or reference type.
+
+2022-05-26 Simon Cook <simon.cook@embecosm.com>
+
+ Backported from master:
+ 2022-05-25 Simon Cook <simon.cook@embecosm.com>
+
+ * config/riscv/arch-canonicalize: Only add mafd extension if
+ base was rv32/rv64g.
+
+2022-05-26 Kito Cheng <kito.cheng@sifive.com>
+
+ Backported from master:
+ 2022-05-09 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/arch-canonicalize: Handle g correctly.
+
2022-05-24 Qing Zhao <qing.zhao@oracle.com>
Backported from master:
git://gcc.gnu.org / gcc.git / blobdiff