+2022-08-26 liuhongt <hongtao.liu@intel.com>
+
+ PR target/106704
+ * config/i386/i386-builtin.def (BDESC): Add
+ CODE_FOR_avx_blendvpd256/CODE_FOR_avx_blendvps256 to
+ corresponding builtins.
+ * config/i386/i386.cc (ix86_gimple_fold_builtin):
+ Don't fold IX86_BUILTIN_PBLENDVB256, IX86_BUILTIN_BLENDVPS256,
+ IX86_BUILTIN_BLENDVPD256 w/o TARGET_AVX2.
+
+2022-08-25 Chenghua Xu <xuchenghua@loongson.cn>
+
+ Backported from master:
+ 2022-08-25 Chenghua Xu <xuchenghua@loongson.cn>
+
+ PR target/106459
+ * config/loongarch/loongarch.cc (loongarch_build_integer):
+ Use HOST_WIDE_INT.
+ * config/loongarch/loongarch.h (IMM_REACH): Likewise.
+ (HWIT_1U): New Defined.
+ (LU12I_OPERAND): Use HOST_WIDE_INT.
+ (LU32I_OPERAND): Likewise.
+ (LU52I_OPERAND): Likewise.
+ (HWIT_UC_0xFFF): Likwise.
+
+2022-08-24 Kewen Lin <linkw@linux.ibm.com>
+
+ Backported from master:
+ 2022-08-16 Kewen Lin <linkw@linux.ibm.com>
+
+ PR tree-optimization/106322
+ * tree-vect-stmts.cc (vectorizable_call): Don't allow
+ vect_emulated_vector_p type for both vectype_in and vectype_out.
+
+2022-08-24 Kewen.Lin <linkw@gcc.gnu.org>
+
+ Backported from master:
+ 2022-08-16 Kewen.Lin <linkw@gcc.gnu.org>
+
+ PR target/103353
+ * config/rs6000/mma.md (define_expand movoo): Move TARGET_MMA condition
+ check to preparation statements and add handlings for !TARGET_MMA.
+ (define_expand movxo): Likewise.
+
+2022-08-23 Tobias Burnus <tobias@codesourcery.com>
+
+ Backported from master:
+ 2022-08-19 Tobias Burnus <tobias@codesourcery.com>
+
+ * config/gcn/mkoffload.cc (main): Add dbgobj to files_to_cleanup.
+
+2022-08-23 Tobias Burnus <tobias@codesourcery.com>
+
+ Backported from master:
+ 2022-08-17 Tobias Burnus <tobias@codesourcery.com>
+
+ PR middle-end/106548
+ * omp-low.cc (lower_rec_input_clauses): Use build_outer_var_ref
+ for 'simd' linear-step values that are variable.
+
+2022-08-19 Release Manager
+
+ * GCC 12.2.0 released.
+
+2022-08-17 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ Backported from master:
+ 2022-08-04 Ilya Leoshkevich <iii@linux.ibm.com>
+
+ * config/s390/vector.md (V_HW_FT): New iterator.
+ * config/s390/vx-builtins.md (vsel<mode>): Use V_HW_FT instead
+ of V_HW.
+
+2022-08-12 Peter Bergner <bergner@linux.ibm.com>
+
+ Backported from master:
+ 2022-07-26 Peter Bergner <bergner@linux.ibm.com>
+
+ PR c/106016
+ * expr.cc (count_type_elements): Handle OPAQUE_TYPE.
+
+2022-08-11 Andre Simoes Dias Vieira <andre.simoesdiasvieira@arm.com>
+
+ Backported from master:
+ 2022-07-25 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64.md (rbit<mode>2): Rename this ...
+ (@aarch64_rbit<mode>): ... to this and change it in...
+ (ffs<mode>2,ctz<mode>2): ... here.
+ (@aarch64_rev16<mode>): New.
+ * config/aarch64/aarch64-builtins.cc: (aarch64_builtins):
+ Define the following enum AARCH64_REV16, AARCH64_REV16L,
+ AARCH64_REV16LL, AARCH64_RBIT, AARCH64_RBITL, AARCH64_RBITLL.
+ (aarch64_init_data_intrinsics): New.
+ (aarch64_general_init_builtins): Add call to
+ aarch64_init_data_intrinsics.
+ (aarch64_expand_builtin_data_intrinsic): New.
+ (aarch64_general_expand_builtin): Add call to
+ aarch64_expand_builtin_data_intrinsic.
+ * config/aarch64/arm_acle.h (__clz, __clzl, __clzll, __cls, __clsl,
+ __clsll, __rbit, __rbitl, __rbitll, __rev, __revl, __revll, __rev16,
+ __rev16l, __rev16ll, __ror, __rorl, __rorll, __revsh): New.
+
+2022-08-10 Tobias Burnus <tobias@codesourcery.com>
+
+ Backported from master:
+ 2022-08-09 Tobias Burnus <tobias@codesourcery.com>
+
+ PR middle-end/106492
+ * omp-low.cc (lower_rec_input_clauses): Add missing folding
+ to data type of linear-clause list item.
+
+2022-08-10 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-08-10 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/106513
+ * gimple-ssa-store-merging.cc (do_shift_rotate): Use uint64_t
+ for head_marker.
+
+2022-08-10 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-08-08 Richard Biener <rguenther@suse.de>
+
+ PR lto/106540
+ PR lto/106334
+ * lto-streamer-in.cc (lto_read_tree_1): Use lto_input_tree_1
+ to input DECL_INITIAL, avoiding to commit drefs.
+
+2022-08-05 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove code
+ setting -mblock-ops-vector-pair. Back port patch from trunk on 8/3.
+
+2022-08-02 Peter Bergner <bergner@linux.ibm.com>
+
+ Backported from master:
+ 2022-07-25 Peter Bergner <bergner@linux.ibm.com>
+ Kewen Lin <linkw@linux.ibm.com>
+
+ PR testsuite/106345
+ * config/rs6000/rs6000.h (DRIVER_SELF_SPECS): Adjust -mdejagnu-cpu
+ to filter out all -mtune options.
+
+2022-08-02 Kewen Lin <linkw@linux.ibm.com>
+
+ Backported from master:
+ 2022-07-26 Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/106091
+ * config/rs6000/rs6000-p8swap.cc (replace_swapped_aligned_store): Copy
+ REG_EH_REGION when replacing one store insn having it.
+ (replace_swapped_aligned_load): Likewise.
+
+2022-07-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-07-29 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/106449
+ * omp-expand.cc (expand_omp_simd): Fix up handling of pointer
+ iterators in non-rectangular simd loops. Unshare fd->loops[i].n2
+ or n2 before regimplifying it inside of a condition.
+
+2022-07-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-07-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/106261
+ * cgraphunit.cc (cgraph_node::assemble_thunks_and_aliases): Don't
+ output asm thunks for -dx.
+
+2022-07-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-07-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/106144
+ * wide-int.cc (wi::shifted_mask): If end >= prec, return right after
+ emitting element for shift or if shift is 0 first element after start.
+ (wide_int_cc_tests): Add tests for equivalency of wi::mask and
+ wi::shifted_mask with 0 start.
+
+2022-07-27 David Malcolm <dmalcolm@redhat.com>
+
+ * json.cc (string::print): Fix escaping of '\'.
+
+2022-07-27 David Malcolm <dmalcolm@redhat.com>
+
+ * doc/invoke.texi (-fdump-analyzer-feasibility): Mention the
+ fpath.txt output.
+
+2022-07-27 Maciej W. Rozycki <macro@embecosm.com>
+
+ Backported from master:
+ 2022-07-27 Maciej W. Rozycki <macro@embecosm.com>
+
+ * config/riscv/riscv.md (stack_protect_set_<mode>): Remove
+ duplicate backslashes.
+
+2022-07-27 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-07-26 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/106189
+ * gimple-array-bounds.cc (array_bounds_checker::check_mem_ref):
+ Divide using offset_ints.
+
+2022-07-27 Joseph Myers <joseph@codesourcery.com>
+
+ Backported from master:
+ 2022-06-30 Joseph Myers <joseph@codesourcery.com>
+
+ PR lto/106129
+ * lto-wrapper.cc (find_option): Add argument start.
+ (merge_and_complain): Loop over existing_opt_index and
+ existing_opt2_index for Xassembler check. Update calls to
+ find_option.
+ (find_and_merge_options): Add argument first to determine whether
+ to merge options with those passed in *opts.
+ (run_gcc): Update calls to find_and_merge_options.
+
+2022-07-27 Andrew Pinski <apinski@marvell.com>
+
+ Backported from master:
+ 2022-07-09 Andrew Pinski <apinski@marvell.com>
+
+ PR tree-optimization/106087
+ * tree-ssa-dce.cc (simple_dce_from_worklist): Check
+ to make sure the statement is only defining one operand.
+
+2022-07-27 Tamar Christina <tamar.christina@arm.com>
+
+ Backported from master:
+ 2022-07-08 Tamar Christina <tamar.christina@arm.com>
+
+ PR tree-optimization/106063
+ * match.pd: Do not apply pattern after veclower is not supported.
+
+2022-07-27 Alexandre Oliva <oliva@adacore.com>
+
+ Backported from master:
+ 2022-06-03 Alexandre Oliva <oliva@adacore.com>
+
+ PR tree-optimization/105665
+ PR tree-optimization/100810
+ * tree-ssa-loop-ivopts.cc
+ (ssa_name_maybe_undef_p, ssa_name_set_maybe_undef): New.
+ (ssa_name_any_use_dominates_bb_p, mark_ssa_maybe_undefs): New.
+ (find_ssa_undef): Check precomputed flag and intervening uses.
+ (tree_ssa_iv_optimize): Call mark_ssa_maybe_undefs.
+
+2022-07-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+ Backported from master:
+ 2022-07-25 Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+ * config/rs6000/rtems.h (CPLUSPLUS_CPP_SPEC): Undef.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-07-19 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/106331
+ * builtins.cc (get_memory_rtx): Compute alignment from
+ the original address and set MEM_OFFSET to unknown when
+ we create a MEM_EXPR from the base object of the address.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-07-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/106131
+ * tree-ssa-sccvn.cc (vn_reference_lookup_3): Force alias-set
+ zero when offsetting the read looking through an aggregate
+ copy.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-29 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/106112
+ * tree-ssa-sccvn.cc (valueized_wider_op): Properly extend
+ a constant operand according to its type.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-20 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/106027
+ * fold-const.cc (fold_to_nonsharp_ineq_using_bound): Use the
+ type of the prevailing comparison for the new comparison type.
+ (fold_binary_loc): Use proper types for the A < X && A + 1 > Y
+ to A < X && A >= Y folding.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105971
+ * tree-ssa-alias.cc (refs_may_alias_p_2): Put bail-out for
+ FUNCTION_DECL and LABEL_DECL refs after decl-decl disambiguation
+ to leak less surprising alias results.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-15 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105969
+ * gimple-ssa-sprintf.cc (get_origin_and_offset_r): Avoid division
+ by zero in overflow check.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-14 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105965
+ * match.pd (view_convert CONSTRUCTOR): Handle single-element
+ CTOR case.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-14 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105946
+ * tree-ssa-uninit.cc (maybe_warn_pass_by_reference):
+ Do not look at arguments not specified in the function call.
+
+2022-07-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-07-11 Richard Biener <rguenthert@suse.de>
+
+ PR target/105459
+ * config/i386/i386-options.cc (ix86_set_current_function):
+ Rebuild the target optimization node whenever necessary,
+ not only when the optimization node didn't change.
+
+2022-07-14 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal): Do
+ not generate block copies with vector pair instructions if we are
+ tuning for power10. Back port from master branch.
+
+2022-07-14 Surya Kumari Jangala <jskumari@linux.vnet.ibm.com>
+
+ Backported from master:
+ 2022-06-14 Surya Kumari Jangala <jskumari@linux.ibm.com>
+
+ PR rtl-optimization/105041
+ * regrename.cc (check_new_reg_p): Use nregs value from du chain.
+
+2022-07-11 Martin Jambor <mjambor@suse.cz>
+
+ Backported from master:
+ 2022-07-04 Martin Jambor <mjambor@suse.cz>
+
+ PR tree-optimization/105860
+ * tree-sra.cc (build_reconstructed_reference): Start expr
+ traversal only just below the outermost union.
+
+2022-07-10 Xi Ruoyao <xry111@xry111.site>
+
+ Backported from master:
+ 2022-07-10 Xi Ruoyao <xry111@xry111.site>
+
+ * config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w
+ instead of mul.d.
+
+2022-07-09 Roger Sayle <roger@nextmovesoftware.com>
+ Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/105930
+ * config/i386/i386.md (*<any_or>di3_doubleword): Split after
+ reload. Use rtx_equal_p to avoid creating memory-to-memory moves,
+ and emit NOTE_INSN_DELETED if operand[2] is zero (i.e. with -O0).
+
+2022-07-08 Lulu Cheng <chenglulu@loongson.cn>
+
+ Backported from master:
+ 2022-07-08 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/loongarch.cc (loongarch_compute_frame_info):
+ Modify fp_sp_offset and gp_sp_offset's calculation method,
+ when frame->mask or frame->fmask is zero, don't minus UNITS_PER_WORD
+ or UNITS_PER_FP_REG.
+
+2022-07-04 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/106114
+ * gimple-range-fold.cc (fold_using_range::relation_fold_and_or): Check
+ statement operands instead of GORI cache.
+
+2022-07-04 Roger Sayle <roger@nextmovesoftware.com>
+ Marek Polacek <polacek@redhat.com>
+ Segher Boessenkool <segher@kernel.crashing.org>
+ Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/105991
+ * config/rs6000/rs6000.md (rotl<mode>3_insert_3): Check that
+ exact_log2 doesn't return -1 (or zero).
+ (plus_xor): New code iterator.
+ (*rotl<mode>3_insert_3_<code>): New define_insn_and_split.
+
+2022-07-04 Xi Ruoyao <xry111@xry111.site>
+
+ Backported from master:
+ 2022-07-03 Xi Ruoyao <xry111@xry111.site>
+ Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/loongarch.cc (loongarch_check_zero_div_p):
+ New static function.
+ (loongarch_idiv_insns): Use loongarch_check_zero_div_p instead
+ of TARGET_CHECK_ZERO_DIV.
+ (loongarch_output_division): Likewise.
+ * common/config/loongarch/loongarch-common.cc
+ (TARGET_DEFAULT_TARGET_FLAGS): Remove unneeded hook.
+ * doc/invoke.texi: Update to match the new behavior.
+
+2022-07-03 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR target/106122
+ * config/i386/i386.md (peephole2): Avoid generating pop %esp
+ when optimizing for size.
+
+2022-07-02 Sergei Trofimovich <siarheit@google.com>
+
+ Backported from master:
+ 2022-06-29 Sergei Trofimovich <siarheit@google.com>
+
+ PR c++/106102
+ * system.h: Introduce INCLUDE_PTHREAD_H macros to include <pthread.h>.
+
+2022-07-01 Vladimir Makarov <vmakarov@gcc.gnu.org>
+
+ Backported from master:
+ 2022-05-28 Vladimir Makarov <vmakarov@gcc.gnu.org>
+
+ PR target/103722
+ * config/sh/sh.cc (sh_register_move_cost): Avoid cost "2" (which
+ is special) for various scenarios.
+
+2022-06-29 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-11 Richard Biener <rguenther@suse.de>
+
+ PR bootstrap/105551
+ * opts.cc (finish_options): Also disable var-tracking if
+ !DWARF2_DEBUGGING_INFO.
+
+2022-06-29 Lulu Cheng <chenglulu@loongson.cn>
+
+ Backported from master:
+ 2022-06-29 Lulu Cheng <chenglulu@loongson.cn>
+
+ PR target/106097
+ * config/loongarch/loongarch.cc (loongarch_build_integer):
+ Remove undefined behavior from code.
+
+2022-06-28 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-06-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/106032
+ * ifcvt.cc (noce_try_sign_mask): Punt if !t_unconditional, and
+ t may_trap_or_fault_p, even if it is cheap.
+
+2022-06-28 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-06-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/106030
+ * expr.cc (expand_cond_expr_using_cmove): Pass NULL_RTX instead of
+ temp to expand_operands if mode has been promoted.
+
+2022-06-28 Xi Ruoyao <xry111@xry111.site>
+
+ Backported from master:
+ 2022-06-28 Xi Ruoyao <xry111@xry111.site>
+
+ PR target/106096
+ * config/loongarch/loongarch.h (REG_CLASS_CONTENTS): Exclude
+ $r13 from SIBCALL_REGS.
+ * config/loongarch/loongarch.cc (loongarch_regno_to_class):
+ Change $r13 to JIRL_REGS.
+
+2022-06-24 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ Backported from master:
+ 2022-06-24 Iain Buclaw <ibuclaw@gdcproject.org>
+
+ * config/tilepro/gen-mul-tables.cc (tilegx_emit): Adjust loop
+ condition to avoid overflow.
+
+2022-06-23 Martin Liska <mliska@suse.cz>
+
+ Backported from master:
+ 2022-06-23 Martin Liska <mliska@suse.cz>
+
+ PR ipa/105600
+ * ipa-icf.cc (sem_item_optimizer::filter_removed_items):
+ Skip variables with body_removed.
+
+2022-06-23 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ Backported from master:
+ 2022-06-21 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ PR tree-optimization/105736
+ * tree-object-size.cc (addr_object_size): Return size_unknown
+ when object offset computation returns an error.
+
+2022-06-23 Richard Sandiford <richard.sandiford@arm.com>
+
+ Backported from master:
+ 2022-06-15 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/105254
+ PR tree-optimization/105940
+ Revert:
+ * config/aarch64/aarch64.cc
+ (aarch64_vector_costs::determine_suggested_unroll_factor): Take a
+ loop_vec_info as argument. Restrict the unroll factor to values
+ that divide the VF.
+ (aarch64_vector_costs::finish_cost): Update call accordingly.
+
+2022-06-23 Kewen Lin <linkw@linux.ibm.com>
+
+ Backported from master:
+ 2022-06-14 Kewen Lin <linkw@linux.ibm.com>
+
+ PR tree-optimization/105940
+ * tree-vect-loop.cc (vect_analyze_loop_2): Move the place of
+ applying suggested_unroll_factor after start_over.
+
+2022-06-21 H.J. Lu <hjl.tools@gmail.com>
+
+ Backported from master:
+ 2022-06-20 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/105960
+ * config/i386/i386.cc (ix86_function_ok_for_sibcall): Return
+ false if PIC register is used when calling ifunc functions.
+
+2022-06-20 Uros Bizjak <ubizjak@gmail.com>
+
+ Backported from master:
+ 2022-06-17 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/105209
+ * config/alpha/alpha-protos.h (alpha_store_data_bypass_p): New.
+ * config/alpha/alpha.cc (alpha_store_data_bypass_p): New function.
+ (alpha_store_data_bypass_p_1): Ditto.
+ * config/alpha/ev4.md: Use alpha_store_data_bypass_p instead
+ of generic store_data_bypass_p.
+ (ev4_ist_c): Remove insn reservation.
+
+2022-06-20 Uros Bizjak <ubizjak@gmail.com>
+
+ Backported from master:
+ 2022-06-17 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/105970
+ * config/i386/i386.cc (ix86_function_arg): Assert that
+ the mode of pointer argumet is equal to ptr_mode, not Pmode.
+
+2022-06-19 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-06-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/105998
+ * varasm.cc (narrowing_initializer_constant_valid_p): Check
+ SCALAR_INT_MODE_P instead of INTEGRAL_MODE_P, also break on
+ ! INTEGRAL_TYPE_P and do the same check also on op{0,1}'s type.
+
+2022-06-19 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-06-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/105951
+ * tree-ssa-ccp.cc (optimize_atomic_bit_test_and,
+ optimize_atomic_op_fetch_cmp_0): Remember gimple_call_fn (call)
+ as last argument to the internal functions.
+ * builtins.cc (expand_ifn_atomic_bit_test_and): Adjust for the
+ extra call argument to ifns. If expand_atomic_fetch_op fails for the
+ lhs == NULL_TREE case, fall through into the optab code with
+ gen_reg_rtx (mode) as target. If second expand_atomic_fetch_op
+ fails, construct a CALL_EXPR and expand that.
+ (expand_ifn_atomic_op_fetch_cmp_0): Adjust for the extra call argument
+ to ifns. If expand_atomic_fetch_op fails, construct a CALL_EXPR and
+ expand that.
+
+2022-06-19 Jan Hubicka <jh@suse.cz>
+
+ Backported from master:
+ 2022-06-14 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/105739
+ * ipa-prop.cc (ipa_load_from_parm_agg): Punt on volatile loads.
+
+2022-06-16 Richard Earnshaw <rearnsha@arm.com>
+
+ Backported from master:
+ 2022-06-15 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/105981
+ * config/arm/arm.cc (gen_cpymem_ldrd_strd): Rename low_reg and hi_reg
+ to first_reg and second_reg respectively. Initialize them correctly
+ when generating big-endian code.
+
+2022-06-15 Simon Wright <simon@pushface.org>
+
+ Backported from master:
+ 2022-06-12 Simon Wright <simon@pushface.org>
+
+ PR target/104871
+ * config/darwin-driver.cc (darwin_find_version_from_kernel): If the OS
+ version is darwin20 (macOS 11) or greater, truncate the version to the
+ major number.
+
+2022-06-15 Mark Mentovai <mark@mentovai.com>
+
+ Backported from master:
+ 2022-06-12 Mark Mentovai <mark@mentovai.com>
+
+ * config/darwin-c.cc: Make -mmacosx-version-min more future-proof.
+
+2022-06-15 Iain Sandoe <iain@sandoe.co.uk>
+
+ Backported from master:
+ 2022-05-29 Iain Sandoe <iain@sandoe.co.uk>
+
+ PR target/105599
+ * config/darwin.h: Move versions-specific handling of multiply_defined
+ from SUBTARGET_DRIVER_SELF_SPECS to LINK_SPEC.
+
+2022-06-15 liuhongt <hongtao.liu@intel.com>
+
+ PR target/105953
+ * config/i386/sse.md (*avx_cmp<mode>3_ltint_not): Force_reg
+ operands[3].
+
+2022-06-14 H.J. Lu <hjl.tools@gmail.com>
+
+ Backported from master:
+ 2022-06-13 H.J. Lu <hjl.tools@gmail.com>
+
+ * common/config/i386/cpuinfo.h (get_available_features): Require
+ AVX for F16C and VAES.
+
+2022-06-14 Philipp Tomsich <philipp.tomsich@vrull.eu>
+
+ Backported from master:
+ 2022-06-02 Philipp Tomsich <philipp.tomsich@vrull.eu>
+
+ * config/riscv/riscv.cc (riscv_build_integer_1): Rewrite value as
+ (-1 << 31) for the single-bit case, when operating on (1 << 31)
+ in SImode.
+ * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): Allow for
+ any single-bit value, moving the special case for (1 << 31) to
+ riscv_build_integer_1 (in riscv.c).
+
+2022-06-08 Max Filippov <jcmvbkbc@gmail.com>
+
+ Backported from master:
+ 2022-06-08 Max Filippov <jcmvbkbc@gmail.com>
+
+ PR target/105879
+ * config/xtensa/xtensa.md (movdi): Rename 'first' and 'second'
+ to 'lowpart' and 'highpart' so that they match 'gen_lowpart' and
+ 'gen_highpart' bitwise semantics and fix order of highpart and
+ lowpart depending on target endianness.
+
+2022-06-08 liuhongt <hongtao.liu@intel.com>
+
+ PR target/105854
+ * config/i386/sse.md (ssse3_palignrdi): Change alternative 2
+ from Yv to Yw.
+
+2022-06-02 Philipp Tomsich <philipp.tomsich@vrull.eu>
+
+ Backported from master:
+ 2022-05-13 Philipp Tomsich <philipp.tomsich@vrull.eu>
+ Manolis Tsamis <manolis.tsamis@vrull.eu>
+
+ * config/riscv/riscv.h (CLZ_DEFINED_VALUE_AT_ZERO): Implement.
+ (CTZ_DEFINED_VALUE_AT_ZERO): Same.
+ * doc/sourcebuild.texi: add documentation for RISC-V specific
+ test target keywords
+
+2022-06-02 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-06-01 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105786
+ * tree-loop-distribution.cc
+ (loop_distribution::transform_reduction_loop): Only do strlen
+ replacement for integer type reductions.
+
+2022-06-02 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-27 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105726
+ * gimple-ssa-warn-restrict.cc (builtin_memref::set_base_and_offset):
+ Constrain array-of-flexarray case more.
+
+2022-06-02 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-24 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105711
+ * expmed.cc (extract_bit_field_as_subreg): Add op0_mode parameter
+ and use it.
+ (extract_bit_field_1): Pass down the mode of op0 to
+ extract_bit_field_as_subreg.
+
+2022-06-02 Martin Sebor <msebor@redhat.com>
+
+ Backported from master:
+ 2022-05-24 Martin Sebor <msebor@redhat.com>
+ Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105604
+ * gimple-ssa-sprintf.cc (set_aggregate_size_and_offset): Add comments.
+ (get_origin_and_offset_r): Remove null handling. Handle variable array
+ sizes.
+ (get_origin_and_offset): Handle null argument here. Simplify.
+ (alias_offset): Update comment.
+ * pointer-query.cc (field_at_offset): Update comment. Handle members
+ of variable-length types.
+
+2022-06-02 Vineet Gupta <vineetg@rivosinc.com>
+
+ Backported from master:
+ 2022-05-24 Vineet Gupta <vineetg@rivosinc.com>
+
+ * config/riscv/riscv.cc: (struct riscv_tune_param): Add
+ fmv_cost.
+ (rocket_tune_info): Add default fmv_cost 8.
+ (sifive_7_tune_info): Ditto.
+ (thead_c906_tune_info): Ditto.
+ (optimize_size_tune_info): Ditto.
+ (riscv_register_move_cost): Use fmv_cost for int<->fp moves.
+
+2022-05-30 Martin Jambor <mjambor@suse.cz>
+
+ Backported from master:
+ 2022-05-27 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/105639
+ * ipa-prop.cc (propagate_controlled_uses): Check type of the
+ constant before adding a LOAD reference.
+
+2022-05-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-05-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/105729
+ * fold-const.cc (fold_unary_loc): Don't optimize (X &) ((Y *) z + w)
+ to (X &) z + w if -fsanitize=null during GENERIC folding.
+
+2022-05-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-05-25 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/105714
+ * asan.cc (has_stmt_been_instrumented_p): For assignments which
+ are both stores and loads, return true only if both destination
+ and source have been instrumented.
+
+2022-05-30 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-05-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR c/105635
+ * pointer-query.cc (gimple_parm_array_size): Return NULL if var
+ doesn't have pointer or reference type.
+
+2022-05-26 Simon Cook <simon.cook@embecosm.com>
+
+ Backported from master:
+ 2022-05-25 Simon Cook <simon.cook@embecosm.com>
+
+ * config/riscv/arch-canonicalize: Only add mafd extension if
+ base was rv32/rv64g.
+
+2022-05-26 Kito Cheng <kito.cheng@sifive.com>
+
+ Backported from master:
+ 2022-05-09 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/arch-canonicalize: Handle g correctly.
+
+2022-05-24 Qing Zhao <qing.zhao@oracle.com>
+
+ Backported from master:
+ 2022-05-09 Qing Zhao <qing.zhao@oracle.com>
+
+ PR target/101891
+ * config/i386/i386.cc (zero_call_used_regno_mode): use V2SImode
+ as a generic MMX mode instead of V4HImode.
+ (zero_all_mm_registers): Use SET to zero instead of MOV for
+ zeroing scratch registers.
+ (ix86_zero_call_used_regs): Likewise.
+
+2022-05-24 Bruno Haible <bruno@clisp.org>
+
+ Backported from master:
+ 2022-05-24 Bruno Haible <bruno@clisp.org>
+
+ PR other/105527
+ * doc/install.texi (Configuration): Add more details about --with-zstd.
+ Document --with-zstd-include and --with-zstd-lib
+
+2022-05-24 Martin Liska <mliska@suse.cz>
+
+ Backported from master:
+ 2022-05-11 Martin Liska <mliska@suse.cz>
+
+ PR other/105527
+ * doc/install.texi: Document the configure option --with-zstd.
+
+2022-05-20 Peter Bergner <bergner@linux.ibm.com>
+
+ Backported from master:
+ 2022-05-18 Peter Bergner <bergner@linux.ibm.com>
+ Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/105556
+ * config/rs6000/mma.md (mma_<vv>, mma_<avv>, mma_<pv>, mma_<apv>,
+ mma_<vvi4i4i8>, mma_<avvi4i4i8>, mma_<vvi4i4i2>, mma_<avvi4i4i2>,
+ mma_<vvi4i4>, mma_<avvi4i4>, mma_<pvi4i2>, mma_<apvi4i2>,
+ mma_<vvi4i4i4>, mma_<avvi4i4i4>): Replace "wa" constraints with "v,?wa".
+ Update other operands accordingly.
+
+2022-05-20 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/103116
+ * tree-vect-stmts.cc (get_group_load_store_type): Handle the
+ case we need peeling for gaps even though GROUP_GAP is zero.
+
+2022-05-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-17 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105618
+ * tree-ssa-sink.cc (statement_sink_location): For virtual
+ PHI uses ignore those defining the used virtual operand.
+
+2022-05-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-12 Richard Biener <rguenther@suse.de>
+
+ PR rtl-optimization/105577
+ * dse.cc (rest_of_handle_dse): Make sure to purge dead EH
+ edges before running fast DCE via df_analyze.
+
+2022-05-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105562
+ * tree-ssa-sccvn.cc (vn_reference_lookup_3): Disambiguate
+ against all CLOBBER defs if there's not an obvious must-alias
+ and we are not doing redundant store elimination.
+ (vn_walk_cb_data::redundant_store_removal_p): New field.
+ (vn_reference_lookup_pieces): Initialize it.
+ (vn_reference_lookup): Add argument to specify if we are
+ doing redundant store removal.
+ (eliminate_dom_walker::eliminate_stmt): Specify we do.
+ * tree-ssa-sccvn.h (vn_reference_lookup): Adjust.
+
+2022-05-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-11 Richard Biener <rguenther@suse.de>
+
+ PR rtl-optimization/105559
+ * cfgrtl.cc (delete_insn_and_edges): Only perform search to BB_END
+ for non-debug insns.
+
+2022-05-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-10 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105537
+ * toplev.cc (process_options): Move flag_var_tracking
+ handling ...
+ * opts.cc (finish_options): ... here.
+
+2022-05-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-10 Richard Biener <rguenther@suse.de>
+
+ * flags.h (dwarf_debuginfo_p): Add opts argument, guard
+ API with !GENERATOR_FILE.
+ * opts.cc (global_options): Poison.
+ (global_options_set): Likewise.
+ (finish_options): Refer to options via opts.
+
+2022-05-19 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-04-29 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105431
+ * tree-ssa-math-opts.cc (powi_as_mults_1): Make n unsigned.
+ (powi_as_mults): Use absu_hwi.
+ (gimple_expand_builtin_powi): Remove now pointless n != -n
+ check.
+
+2022-05-18 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/105458
+ * value-relation.cc (path_oracle::register_relation): Merge, then check
+ for equivalence.
+
+2022-05-16 Sebastian Pop <spop@amazon.com>
+
+ PR target/105162
+ * config/aarch64/aarch64-protos.h (atomic_ool_names): Increase dimension
+ of str array.
+ * config/aarch64/aarch64.cc (aarch64_atomic_ool_func): Call
+ memmodel_from_int and handle MEMMODEL_SYNC_*.
+ (DEF0): Add __aarch64_*_sync functions.
+
+2022-05-16 Eric Botcazou <ebotcazou@adacore.com>
+
+ * dwarf2out.cc (loc_list_from_tree_1) <TRUTH_NOT_EXPR>: Do a logical
+ instead of a bitwise negation.
+ <COND_EXPR>: Swap the operands if the condition is TRUTH_NOT_EXPR.
+
+2022-05-13 Eric Botcazou <ebotcazou@adacore.com>
+
+ * tree-sra.cc (sra_modify_assign): Check that scalar storage order
+ is the same on the LHS and RHS before rewriting one with the model
+ of the other.
+
+2022-05-13 Alexandre Oliva <oliva@adacore.com>
+
+ Backported from master:
+ 2022-05-13 Alexandre Oliva <oliva@adacore.com>
+
+ PR rtl-optimization/105455
+ * gimple-harden-conditionals.cc (insert_check_and_trap): Set
+ probabilities for newly-conditional edges.
+
+2022-05-11 Martin Jambor <mjambor@suse.cz>
+
+ Backported from master:
+ 2022-04-29 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/100413
+ * cgraph.cc (cgraph_node::remove): Release body of the node this
+ is clone_of if appropriate.
+
+2022-05-10 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-05-10 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/105528
+ * gimple-isel.cc (gimple_expand_vec_set_expr): After gsi_remove
+ set *gsi to gsi_for_stmt (ass_stmt). Fix up function comment.
+
+2022-05-10 Eric Botcazou <ebotcazou@adacore.com>
+
+ PR target/105292
+ * config/sparc/sparc.cc (sparc_vectorize_vec_perm_const): Return
+ true only for 8-byte vector modes.
+
+2022-05-06 Michael Meissner <meissner@linux.ibm.com>
+
+ Backported from master:
+ 2022-05-06 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/102059
+ * config/rs6000/rs6000.cc (rs6000_can_inline_p): Ignore -mpower8-fusion
+ and -mpower10-fusion options for inlining purposes.
+
+2022-05-06 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-04-29 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105376
+ * tree.cc (build_real): Special case dconst* arguments
+ for decimal floating point types.
+
+2022-05-06 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-05 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105484
+ * gimple-isel.cc (gimple_expand_vec_set_expr): Clean EH, return
+ whether the CFG changed.
+ (gimple_expand_vec_exprs): When the CFG changed, clean it up.
+
+2022-05-06 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-03 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105461
+ * opts.cc (finish_options): Match the condition to
+ disable flag_var_tracking to that of process_options.
+
+2022-05-06 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-03 Richard Biener <rguenther@suse.de>
+
+ * opts.cc: #undef OPTIONS_SET_P.
+ (finish_options): Use opts_set instead of OPTIONS_SET_P.
+
+2022-05-06 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-02 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105437
+ * tree-vect-slp.cc (vect_schedule_slp_node): Handle the
+ case where last_stmt alters control flow.
+
+2022-05-06 Richard Biener <rguenther@suse.de>
+
+ Backported from master:
+ 2022-05-03 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105394
+ * tree-vect-generic.cc (expand_vector_condition): Adjust
+ comp_width for non-integer mode masks as well.
+
+2022-05-06 Release Manager
+
+ * GCC 12.1.0 released.
+
+2022-05-02 Jakub Jelinek <jakub@redhat.com>
+
+ Backported from master:
+ 2022-05-02 Jakub Jelinek <jakub@redhat.com>
+
+ * system.h: Include initializer_list.
+
+2022-04-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR lto/105399
+ * cgraph.cc (cgraph_node::verify_node): Don't verify
+ semantic_interposition flag against
+ opt_for_fn (decl, flag_semantic_interposition) for aliases in lto1.
+
+2022-04-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105331
+ * config/i386/i386.cc (ix86_gimplify_va_arg): Mark va_arg_tmp
+ temporary TREE_ADDRESSABLE before trying to gimplify ADDR_EXPR
+ of it.
+
+2022-04-28 Jonathan Wakely <jwakely@redhat.com>
+
+ * doc/install.texi (Configuration): Remove misleading text
+ around LE PowerPC Linux multilibs.
+
+2022-04-28 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
+
+ PR d/103528
+ * doc/install.texi (Tools/packages necessary for building GCC)
+ (GDC): Document libphobos requirement.
+ (Host/target specific installation notes for GCC, *-*-solaris2*):
+ Document libphobos and GDC specifics.
+
+2022-04-28 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105219
+ * tree-vect-loop.cc (vect_transform_loop): Disable
+ special code narrowing the vectorized epilogue max
+ iterations when peeling for alignment or gaps was in effect.
+
+2022-04-28 Xi Ruoyao <xry111@mengyan1223.wang>
+
+ * config/loongarch/loongarch.cc
+ (loongarch_flatten_aggregate_field): Ignore empty fields for
+ RECORD_TYPE.
+
+2022-04-27 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/loongarch.md: Add fdiv define_expand template,
+ then generate floating-point division and floating-point reciprocal
+ instructions.
+
+2022-04-27 Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/loongarch.md: Add '(clobber (mem:BLK (scratch)))'
+ to PLV instruction templates.
+
+2022-04-27 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/104492
+ * gimple-ssa-warn-access.cc
+ (pass_waccess::warn_invalid_pointer): Exclude equality compare
+ diagnostics for all kind of invalidations.
+ (pass_waccess::check_dangling_uses): Fix post-dominator query.
+ (pass_waccess::check_pointer_uses): Likewise.
+
+2022-04-27 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ PR target/102024
+ * config/s390/s390-protos.h (s390_function_arg_vector): Remove
+ prototype.
+ * config/s390/s390.cc (s390_single_field_struct_p): New function.
+ (s390_function_arg_vector): Invoke s390_single_field_struct_p.
+ (s390_function_arg_float): Likewise.
+
+2022-04-27 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/105396
+ * asan.cc (asan_redzone_buffer::emit_redzone_byte): Handle the case
+ where offset is bigger than off but smaller than m_prev_offset + 32
+ bits by pushing one or more 0 bytes. Sink the
+ m_shadow_bytes.safe_push (value); flush_if_full (); statements from
+ all cases to the end of the function.
+
+2022-04-27 Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/105271
+ * config/rs6000/rs6000-builtins.def (NEG_V2DI): Move to [power8-vector]
+ stanza.
+
+2022-04-26 Thomas Schwinge <thomas@codesourcery.com>
+
+ * config/gcn/gcn.cc (gcn_print_lds_decl): Make "gang-private
+ data-share memory exhausted" error more verbose.
+
+2022-04-26 Martin Liska <mliska@suse.cz>
+
+ PR lto/105364
+ * lto-wrapper.cc (print_lto_docs_link): Use global_dc.
+ (run_gcc): Parse OPT_fdiagnostics_urls_.
+ (main): Initialize global_dc.
+
+2022-04-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/105314
+ * ifcvt.cc (noce_try_store_flag_mask): Don't require that the non-zero
+ operand is equal to if_info->x, instead use the non-zero operand
+ as one of the operands of AND with if_info->x as target.
+
+2022-04-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/105374
+ * tree-ssa-reassoc.cc (eliminate_redundant_comparison): Punt if
+ !fold_convertible_p rather than assuming fold_convert must succeed.
+
+2022-04-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105367
+ * config/i386/i386.cc (ix86_veclibabi_svml, ix86_veclibabi_acml): Pass
+ el_mode == DFmode ? double_type_node : float_type_node instead of
+ TREE_TYPE (type_in) as first arguments to mathfn_built_in.
+
+2022-04-25 David Malcolm <dmalcolm@redhat.com>
+
+ PR analyzer/104308
+ * gimple-fold.cc (gimple_fold_builtin_memory_op): Explicitly set
+ the location of new_stmt in all places that don't already set it,
+ whether explicitly, or via a call to gsi_replace.
+
+2022-04-25 Paul A. Clarke <pc@us.ibm.com>
+
+ * doc/extend.texi (Other Builtins): Correct reference to 'modff'.
+
+2022-04-25 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/105276
+ * gimple-range.cc (gimple_ranger::prefill_stmt_dependencies): Include
+ existing global range with calculated value.
+
+2022-04-25 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105368
+ * tree-ssa-math-opts.cc (powi_cost): Use absu_hwi.
+
+2022-04-25 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/100810
+ * tree-ssa-loop-ivopts.cc (struct iv_cand): Add involves_undefs flag.
+ (find_ssa_undef): New function.
+ (add_candidate_1): Avoid adding derived candidates with
+ undefined SSA names and mark the original ones.
+ (determine_group_iv_cost_generic): Reject rewriting
+ uses with a different IV when that involves undefined SSA names.
+
+2022-04-25 Steven G. Kargl <kargl@gcc.gnu.org>
+
+ PR target/89125
+ * config/freebsd.h: Define TARGET_LIBC_HAS_FUNCTION to be
+ bsd_libc_has_function.
+ * targhooks.cc (bsd_libc_has_function): New function.
+ Expand the supported math functions to inclue C99 libm.
+ * targhooks.h (bsd_libc_has_function): New Prototype.
+
+2022-04-25 Richard Biener <rguenther@suse.de>
+
+ PR rtl-optimization/105231
+ * combine.cc (distribute_notes): Assert that a REG_EH_REGION
+ with landing pad > 0 is from i3. Put any REG_EH_REGION note
+ on i3 or drop it if the insn can not trap.
+ (try_combine): Ensure that we can merge REG_EH_REGION notes
+ with non-call exceptions. Ensure we are not splitting a
+ trapping part of an insn with non-call exceptions when there
+ is any REG_EH_REGION note to preserve.
+
+2022-04-25 Hongyu Wang <hongyu.wang@intel.com>
+
+ PR target/105339
+ * config/i386/avx512fintrin.h (_mm512_scalef_round_pd):
+ Add parentheses for parameters and djust format.
+ (_mm512_mask_scalef_round_pd): Ditto.
+ (_mm512_maskz_scalef_round_pd): Ditto.
+ (_mm512_scalef_round_ps): Ditto.
+ (_mm512_mask_scalef_round_ps): Ditto.
+ (_mm512_maskz_scalef_round_ps): Ditto.
+ (_mm_scalef_round_sd): Use _mm_undefined_pd.
+ (_mm_scalef_round_ss): Use _mm_undefined_ps.
+ (_mm_mask_scalef_round_sd): New macro.
+ (_mm_mask_scalef_round_ss): Ditto.
+ (_mm_maskz_scalef_round_sd): Ditto.
+ (_mm_maskz_scalef_round_ss): Ditto.
+
+2022-04-23 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105338
+ * config/i386/i386-expand.cc (ix86_expand_int_movcc): Handle
+ op0 == cst1 ? op0 : op3 like op0 == cst1 ? cst1 : op3 for the non-cmov
+ cases.
+
+2022-04-22 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/105334
+ * config/rs6000/rs6000.md (pack<mode> for FMOVE128): New expander.
+ (pack<mode> for FMOVE128): Rename and split the insn_and_split to...
+ (pack<mode>_hard for FMOVE128): ... this...
+ (pack<mode>_soft for FMOVE128): ... and this.
+
+2022-04-22 Paul A. Clarke <pc@us.ibm.com>
+
+ * doc/extend.texi: Correct "This" to "These".
+
+2022-04-22 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/105333
+ * rtlanal.cc (replace_rtx): Use simplify_subreg or
+ simplify_unary_operation if CONST_SCALAR_INT_P rather than just
+ CONST_INT_P.
+
+2022-04-21 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/103197
+ PR target/102146
+ * config/rs6000/rs6000.md (zero_extendqi<mode>2 for EXTQI): Disparage
+ the "Z" alternatives in {l,st}{f,xs}iwzx.
+ (zero_extendhi<mode>2 for EXTHI): Ditto.
+ (zero_extendsi<mode>2 for EXTSI): Ditto.
+ (*movsi_internal1): Ditto.
+ (*mov<mode>_internal1 for QHI): Ditto.
+ (movsd_hardfloat): Ditto.
+
+2022-04-21 Martin Liska <mliska@suse.cz>
+
+ * configure.ac: Enable compressed debug sections for mold
+ linker.
+ * configure: Regenerate.
+
+2022-04-21 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/105203
+ * emit-rtl.cc (emit_copy_of_insn_after): Don't call mark_jump_label
+ on DEBUG_INSNs.
+
+2022-04-20 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/104912
+ * tree-vect-loop-manip.cc (vect_loop_versioning): Split
+ the cost model check to a separate BB to make sure it is
+ checked first and not combined with other version checks.
+
+2022-04-20 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105312
+ * gimple-isel.cc (gimple_expand_vec_cond_expr): Query both
+ VCOND and VCONDU for EQ and NE.
+
+2022-04-20 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103818
+ * ipa-modref-tree.cc (modref_access_node::closer_pair_p): Use
+ poly_offset_int to avoid overflow.
+ (modref_access_node::update2): likewise.
+
+2022-04-20 Jakub Jelinek <jakub@redhat.com>
+
+ PR ipa/105306
+ * cgraph.cc (cgraph_node::create): Set node->semantic_interposition
+ to opt_for_fn (decl, flag_semantic_interposition).
+ * cgraphclones.cc (cgraph_node::create_clone): Copy over
+ semantic_interposition flag.
+
+2022-04-19 Sergei Trofimovich <siarheit@google.com>
+
+ PR gcov-profile/105282
+ * value-prof.cc (stream_out_histogram_value): Allow negative counts
+ on HIST_TYPE_INDIR_CALL.
+
+2022-04-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105257
+ * config/sparc/sparc.cc (epilogue_renumber): If ORIGINAL_REGNO,
+ use gen_raw_REG instead of gen_rtx_REG and copy over also
+ ORIGINAL_REGNO. Use return 0; instead of /* fallthrough */.
+
+2022-04-19 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/104010
+ PR tree-optimization/103941
+ * tree-vect-slp.cc (vect_bb_slp_scalar_cost): When
+ we run into stmts in patterns continue walking those
+ for uses outside of the vectorized region instead of
+ marking the lane live.
+
+2022-04-18 Hans-Peter Nilsson <hp@axis.com>
+
+ * doc/install.texi <CRIS>: Remove references to removed websites and
+ adjust for cris-*-elf being the only remaining toolchain.
+
+2022-04-18 Hans-Peter Nilsson <hp@axis.com>
+
+ * doc/invoke.texi <CRIS>: Remove references to options for removed
+ subtarget cris-axis-linux-gnu and tweak wording accordingly.
+
+2022-04-16 Gerald Pfeifer <gerald@pfeifer.com>
+
+ * doc/install.texi (Specific): Adjust mingw-w64 download link.
+
+2022-04-15 Hongyu Wang <hongyu.wang@intel.com>
+
+ * config/i386/smmintrin.h: Correct target pragma from sse4.1
+ and sse4.2 to crc32 for crc32 intrinsics.
+
+2022-04-14 Indu Bhagat <indu.bhagat@oracle.com>
+
+ PR debug/105089
+ * ctfc.cc (ctf_dvd_ignore_insert): New function.
+ (ctf_dvd_ignore_lookup): Likewise.
+ (ctf_add_variable): Keep track of non-defining decl DIEs.
+ (new_ctf_container): Initialize the new hash-table.
+ (ctfc_delete_container): Empty hash-table.
+ * ctfc.h (struct ctf_container): Add new hash-table.
+ (ctf_dvd_ignore_lookup): New declaration.
+ (ctf_add_variable): Add additional argument.
+ * ctfout.cc (ctf_dvd_preprocess_cb): Skip adding CTF variable
+ record for non-defining decl for which a defining decl exists
+ in the same TU.
+ (ctf_preprocess): Defer updating the number of global objts
+ until here.
+ (output_ctf_header): Use ctfc_vars_list_count as some CTF
+ variables may not make it to the final output.
+ (output_ctf_vars): Likewise.
+ * dwarf2ctf.cc (gen_ctf_variable): Skip generating CTF variable
+ if this is known to be a non-defining decl DIE.
+
+2022-04-14 Indu Bhagat <indu.bhagat@oracle.com>
+
+ * ctfc.h (struct ctf_container): Introduce a new member.
+ * ctfout.cc (ctf_list_add_ctf_vars): Use it instead of static
+ variable.
+
+2022-04-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105247
+ * simplify-rtx.cc (simplify_const_binary_operation): For shifts
+ or rotates by VOIDmode constant integer shift count use word_mode
+ for the operand if int_mode is narrower than word.
+
+2022-04-14 Robin Dapp <rdapp@linux.ibm.com>
+
+ * config/s390/s390.cc (s390_get_sched_attrmask): Add z16.
+ (s390_get_unit_mask): Likewise.
+ (s390_is_fpd): Likewise.
+ (s390_is_fxd): Likewise.
+ * config/s390/s390.h (s390_tune_attr): Set max tune level to z16.
+ * config/s390/s390.md (z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14,z15):
+ Add z16.
+ (z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14,z15,z16):
+ Likewise.
+ * config/s390/3931.md: New file.
+
+2022-04-13 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/105254
+ * config/aarch64/aarch64.cc
+ (aarch64_vector_costs::determine_suggested_unroll_factor): Take a
+ loop_vec_info as argument. Restrict the unroll factor to values
+ that divide the VF.
+ (aarch64_vector_costs::finish_cost): Update call accordingly.
+
+2022-04-13 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105263
+ * tree-ssa-reassoc.cc (try_special_add_to_ops): Do not consume
+ negates in multiplication chains with DFP.
+
+2022-04-13 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/105253
+ * tree.cc (tree_builtin_call_types_compatible_p): If PROP_gimple,
+ use useless_type_conversion_p checks instead of TYPE_MAIN_VARIANT
+ comparisons or tree_nop_conversion_p checks.
+
+2022-04-13 Hongyu Wang <hongyu.wang@intel.com>
+
+ PR target/103069
+ * config/i386/i386-expand.cc (ix86_expand_cmpxchg_loop):
+ Add missing set to target_val at pause label.
+
+2022-04-13 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105234
+ * attribs.cc (decl_attributes): Don't set
+ DECL_FUNCTION_SPECIFIC_TARGET if target_option_default_node is
+ NULL.
+
+2022-04-13 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105250
+ * fold-const.cc (fold_convertible_p): Revert
+ r12-7979-geaaf77dd85c333, instead check for size equality
+ of the vector types involved.
+
+2022-04-13 Richard Biener <rguenther@suse.de>
+
+ Revert:
+ 2022-04-13 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/104912
+ * tree-vect-loop-manip.cc (vect_loop_versioning): Split
+ the cost model check to a separate BB to make sure it is
+ checked first and not combined with other version checks.
+
+2022-04-13 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/104912
+ * tree-vect-loop-manip.cc (vect_loop_versioning): Split
+ the cost model check to a separate BB to make sure it is
+ checked first and not combined with other version checks.
+
+2022-04-13 Jakub Jelinek <jakub@redhat.com>
+
+ * tree-scalar-evolution.cc (expression_expensive_p): Fix a comment typo.
+
+2022-04-12 Antoni Boucher <bouanto@zoho.com>
+
+ PR jit/104072
+ * reginfo.cc: New functions (clear_global_regs_cache,
+ reginfo_cc_finalize) to avoid an issue where compiling the same
+ code multiple times gives an error about assigning the same
+ register to 2 global variables.
+ * rtl.h: New function (reginfo_cc_finalize).
+ * toplev.cc: Call it.
+
+2022-04-12 Antoni Boucher <bouanto@zoho.com>
+
+ PR jit/104071
+ * toplev.cc: Call the new function tree_cc_finalize in
+ toplev::finalize.
+ * tree.cc: New functions (clear_nonstandard_integer_type_cache
+ and tree_cc_finalize) to clear the cache of non-standard integer
+ types to avoid having issues with some optimizations of
+ bitcast where the SSA_NAME will have a size of a cached
+ integer type that should have been invalidated, causing a
+ comparison of integer constant to fail.
+ * tree.h: New function (tree_cc_finalize).
+
+2022-04-12 Thomas Schwinge <thomas@codesourcery.com>
+
+ PR target/97348
+ * config/nvptx/nvptx.h (ASM_SPEC): Don't set.
+ * config/nvptx/nvptx.opt (misa): Adjust comment.
+
+2022-04-12 Thomas Schwinge <thomas@codesourcery.com>
+
+ Revert:
+ 2022-03-03 Tom de Vries <tdevries@suse.de>
+
+ * config/nvptx/nvptx.h (ASM_SPEC): Add %{misa=sm_30:--no-verify}.
+
+2022-04-12 Thomas Schwinge <thomas@codesourcery.com>
+
+ Revert:
+ 2022-03-31 Tom de Vries <tdevries@suse.de>
+
+ * config/nvptx/nvptx.h (ASM_SPEC): Use "-m sm_35" for -misa=sm_30.
+
+2022-04-12 Richard Biener <rguenther@suse.de>
+
+ PR ipa/104303
+ * tree-ssa-dce.cc (mark_stmt_if_obviously_necessary): Do not
+ include local escaped memory as obviously necessary stores.
+
+2022-04-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105235
+ * tree-ssa-math-opts.cc (execute_cse_conv_1): Clean EH and
+ return whether the CFG changed.
+ (execute_cse_sincos_1): Adjust.
+
+2022-04-12 Przemyslaw Wirkus <Przemyslaw.Wirkus@arm.com>
+
+ PR target/104144
+ * config/arm/t-aprofile (MULTI_ARCH_OPTS_A): Remove Armv9-a options.
+ (MULTI_ARCH_DIRS_A): Remove Armv9-a diretories.
+ (MULTILIB_REQUIRED): Don't require Armv9-a libraries.
+ (MULTILIB_MATCHES): Treat Armv9-a as equivalent to Armv8-a.
+ (MULTILIB_REUSE): Remove remap rules for Armv9-a.
+ * config/arm/t-multilib (v9_a_nosimd_variants): Delete.
+ (MULTILIB_MATCHES): Remove mappings for v9_a_nosimd_variants.
+
+2022-04-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105232
+ * tree.cc (component_ref_size): Bail out for too large
+ or non-constant sizes.
+
+2022-04-12 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105226
+ * tree-vect-loop-manip.cc (vect_loop_versioning): Verify
+ we can split the exit of an outer loop we choose to version.
+
+2022-04-12 Jakub Jelinek <jakub@redhat.com>
+
+ * config/i386/i386-expand.cc (ix86_emit_i387_sinh, ix86_emit_i387_cosh,
+ ix86_emit_i387_tanh, ix86_emit_i387_asinh, ix86_emit_i387_acosh,
+ ix86_emit_i387_atanh, ix86_emit_i387_log1p, ix86_emit_i387_round,
+ ix86_emit_swdivsf, ix86_emit_swsqrtsf,
+ ix86_expand_atomic_fetch_op_loop, ix86_expand_cmpxchg_loop):
+ Formatting fix.
+ * config/i386/i386.cc (warn_once_call_ms2sysv_xlogues): Likewise.
+
+2022-04-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105214
+ * config/i386/i386-expand.cc (ix86_emit_i387_log1p): Call
+ do_pending_stack_adjust.
+
+2022-04-12 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/105211
+ * builtins.cc (expand_builtin_int_roundingfn_2): If mathfn_built_in_1
+ fails for TREE_TYPE (arg), retry it with
+ TREE_VALUE (TYPE_ARG_TYPES (TREE_TYPE (fndecl))) and if even that
+ fails, emit call normally.
+
+2022-04-12 Andreas Krebbel <krebbel@linux.ibm.com>
+
+ * common/config/s390/s390-common.cc: Rename PF_ARCH14 to PF_Z16.
+ * config.gcc: Add z16 as march/mtune switch.
+ * config/s390/driver-native.cc (s390_host_detect_local_cpu):
+ Recognize z16 with -march=native.
+ * config/s390/s390-opts.h (enum processor_type): Rename
+ PROCESSOR_ARCH14 to PROCESSOR_3931_Z16.
+ * config/s390/s390.cc (PROCESSOR_ARCH14): Rename to ...
+ (PROCESSOR_3931_Z16): ... throughout the file.
+ (s390_processor processor_table): Add z16 as cpu string.
+ * config/s390/s390.h (enum processor_flags): Rename PF_ARCH14 to
+ PF_Z16.
+ (TARGET_CPU_ARCH14): Rename to ...
+ (TARGET_CPU_Z16): ... this.
+ (TARGET_CPU_ARCH14_P): Rename to ...
+ (TARGET_CPU_Z16_P): ... this.
+ (TARGET_ARCH14): Rename to ...
+ (TARGET_Z16): ... this.
+ (TARGET_ARCH14_P): Rename to ...
+ (TARGET_Z16_P): ... this.
+ * config/s390/s390.md (cpu_facility): Rename arch14 to z16 and
+ check TARGET_Z16 instead of TARGET_ARCH14.
+ * config/s390/s390.opt: Add z16 to processor_type.
+ * doc/invoke.texi: Document z16 and arch14.
+
+2022-04-12 chenglulu <chenglulu@loongson.cn>
+
+ * config/loongarch/loongarch.cc: Fix bug for
+ tmpdir-g++.dg-struct-layout-1/t033.
+
+2022-04-11 Peter Bergner <bergner@linux.ibm.com>
+
+ PR target/104894
+ * config/rs6000/rs6000.cc (rs6000_sibcall_aix): Handle pcrel sibcalls
+ to longcall functions.
+
+2022-04-11 Jason Merrill <jason@redhat.com>
+
+ * ipa-free-lang-data.cc (free_lang_data_in_decl): Fix typos.
+
+2022-04-11 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/105213
+ PR target/103623
+ * config/rs6000/rs6000.md (unpack<mode>_nodm): Add m,r,i alternative.
+
+2022-04-11 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/105218
+ * tree-ssa-phiopt.cc (value_replacement): If middle_bb has
+ more than one predecessor or phi's bb more than 2 predecessors,
+ reset phi result uses instead of adding a debug temp.
+
+2022-04-11 Kito Cheng <kito.cheng@sifive.com>
+
+ PR target/104853
+ * config.gcc: Pass -misa-spec to arch-canonicalize and
+ multilib-generator.
+ * config/riscv/arch-canonicalize: Adding -misa-spec option.
+ (SUPPORTED_ISA_SPEC): New.
+ (arch_canonicalize): New argument `isa_spec`.
+ Handle multiple ISA spec versions.
+ * config/riscv/multilib-generator: Adding -misa-spec option.
+
+2022-04-11 Kito Cheng <kito.cheng@sifive.com>
+
+ * config/riscv/arch-canonicalize: Add TODO item.
+ (IMPLIED_EXT): Sync.
+ (arch_canonicalize): Checking until no change.
+
+2022-04-11 Tamar Christina <tamar.christina@arm.com>
+
+ PR target/105197
+ * tree-vect-stmts.cc (vectorizable_condition): Prevent cond swap when
+ not masked.
+
+2022-04-11 Jason Merrill <jason@redhat.com>
+
+ PR c++/100370
+ * pointer-query.cc (compute_objsize_r) [POINTER_PLUS_EXPR]: Require
+ deref == -1.
+
+2022-04-11 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/104639
+ * tree-ssa-phiopt.cc: Include tree-ssa-propagate.h.
+ (value_replacement): Optimize (x != cst1 ? x : cst2) != cst3
+ into x != cst3.
+
+2022-04-11 Jeff Law <jeffreyalaw@gmail.com>
+
+ * config/bfin/bfin.md (rol_one): Fix pattern to indicate the
+ sign bit of the source ends up in CC.
+
+2022-04-09 Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/103376
+ * cgraphunit.cc (cgraph_node::analyze): update semantic_interposition
+ flag.
+
+2022-04-09 Jan Hubicka <hubicka@ucw.cz>
+
+ * ipa-modref.cc (ipa_merge_modref_summary_after_inlining): Propagate
+ nondeterministic and side_effects flags.
+
+2022-04-08 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ PR target/105157
+ * config.gcc: Shift ext_mask by TARGET_CPU_NBITS.
+ * config/aarch64/aarch64.h (TARGET_CPU_NBITS): New macro.
+ (TARGET_CPU_MASK): Likewise.
+ (TARGET_CPU_DEFAULT): Use TARGET_CPU_NBITS.
+ * config/aarch64/aarch64.cc (aarch64_get_tune_cpu): Use TARGET_CPU_MASK.
+ (aarch64_get_arch): Likewise.
+ (aarch64_override_options): Use TARGET_CPU_NBITS.
+
+2022-04-08 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105198
+ * tree-predcom.cc (find_looparound_phi): Check whether
+ the found memory location of the entry value is clobbered
+ inbetween the value we want to use and loop entry.
+
+2022-04-08 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/105189
+ * fold-const.cc (make_range_step): Fix up handling of
+ (unsigned) x +[low, -] ranges for signed x if low fits into
+ typeof (x).
+
+2022-04-08 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105175
+ * tree-vect-stmts.cc (vectorizable_operation): Suppress
+ -Wvector-operation-performance if using emulated vectors.
+ * tree-vect-generic.cc (expand_vector_piecewise): Do not diagnose
+ -Wvector-operation-performance when suppressed.
+ (expand_vector_parallel): Likewise.
+ (expand_vector_comparison): Likewise.
+ (expand_vector_condition): Likewise.
+ (lower_vec_perm): Likewise.
+ (expand_vector_conversion): Likewise.
+
+2022-04-07 Tamar Christina <tamar.christina@arm.com>
+
+ PR target/104409
+ * config/aarch64/aarch64-builtins.cc (handle_arm_acle_h): New.
+ (aarch64_general_init_builtins): Move LS64 code.
+ * config/aarch64/aarch64-c.cc (aarch64_pragma_aarch64): Support
+ arm_acle.h
+ * config/aarch64/aarch64-protos.h (handle_arm_acle_h): New.
+ * config/aarch64/arm_acle.h: Add pragma GCC aarch64 "arm_acle.h".
+
+2022-04-07 Richard Biener <rguenther@suse.de>
+ Jan Hubicka <hubicka@ucw.cz>
+
+ PR ipa/104303
+ * tree-ssa-alias.h (ptr_deref_may_alias_global_p,
+ ref_may_alias_global_p, ref_may_alias_global_p,
+ stmt_may_clobber_global_p, pt_solution_includes_global): Add
+ bool parameters indicating whether escaped locals should be
+ considered global.
+ * tree-ssa-structalias.cc (pt_solution_includes_global):
+ When the new escaped_nonlocal_p flag is true also consider
+ pt->vars_contains_escaped.
+ * tree-ssa-alias.cc (ptr_deref_may_alias_global_p):
+ Pass down new escaped_nonlocal_p flag.
+ (ref_may_alias_global_p): Likewise.
+ (stmt_may_clobber_global_p): Likewise.
+ (ref_may_alias_global_p_1): Likewise. For decls also
+ query the escaped solution if true.
+ (ref_may_access_global_memory_p): Remove.
+ (modref_may_conflict): Use ref_may_alias_global_p with
+ escaped locals considered global.
+ (ref_maybe_used_by_stmt_p): Adjust.
+ * ipa-fnsummary.cc (points_to_local_or_readonly_memory_p):
+ Likewise.
+ * tree-ssa-dse.cc (dse_classify_store): Likewise.
+ * trans-mem.cc (thread_private_new_memory): Likewise, but
+ consider escaped locals global.
+ * tree-ssa-dce.cc (mark_stmt_if_obviously_necessary): Likewise.
+
+2022-04-07 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105185
+ * tree-ssa-sccvn.cc (visit_reference_op_call): Simplify
+ modref query again.
+
+2022-04-07 Tamar Christina <tamar.christina@arm.com>
+
+ PR target/104049
+ * config/aarch64/aarch64-simd.md
+ (aarch64_reduc_plus_internal<mode>): Fix RTL and rename to...
+ (reduc_plus_scal_<mode>): ... This.
+ (reduc_plus_scal_v4sf): Moved.
+ (aarch64_reduc_plus_internalv2si): Fix RTL and rename to...
+ (reduc_plus_scal_v2si): ... This.
+
+2022-04-07 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/102586
+ * langhooks.h (struct lang_hooks_for_types): Add classtype_as_base
+ langhook.
+ * langhooks-def.h (LANG_HOOKS_CLASSTYPE_AS_BASE): Define.
+ (LANG_HOOKS_FOR_TYPES_INITIALIZER): Add it.
+ * gimple-fold.cc (clear_padding_type): Use ftype instead of
+ TREE_TYPE (field) some more. For artificial FIELD_DECLs without
+ name try the lang_hooks.types.classtype_as_base langhook and
+ if it returns non-NULL, use that instead of ftype for recursive call.
+
+2022-04-07 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/105150
+ * tree.cc (tree_builtin_call_types_compatible_p): New function.
+ (get_call_combined_fn): Use it.
+
+2022-04-07 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105165
+ * tree-complex.cc (expand_complex_asm): Sorry for asm goto
+ _Complex outputs.
+
+2022-04-07 liuhongt <hongtao.liu@intel.com>
+
+ * config/i386/sse.md (<sse2_avx2>_andnot<mode>3_mask):
+ Removed.
+ (<sse>_andnot<mode>3<mask_name>): Disable V*HFmode patterns
+ for mask_applied.
+ (<code><mode>3<mask_name>): Ditto.
+ (*<code><mode>3<mask_name>): Ditto.
+ (VFB_128_256): Adjust condition of V8HF/V16HFmode according to
+ real instruction.
+ (VFB_512): Ditto.
+ (VFB): Ditto.
+
+2022-04-06 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/104985
+ * combine.cc (struct undo): Add where.regno member.
+ (do_SUBST_MODE): Rename to ...
+ (subst_mode): ... this. Change first argument from rtx * into int,
+ operate on regno_reg_rtx[regno] and save regno into where.regno.
+ (SUBST_MODE): Remove.
+ (try_combine): Use subst_mode instead of SUBST_MODE, change first
+ argument from regno_reg_rtx[whatever] to whatever. For UNDO_MODE, use
+ regno_reg_rtx[undo->where.regno] instead of *undo->where.r.
+ (undo_to_marker): For UNDO_MODE, use regno_reg_rtx[undo->where.regno]
+ instead of *undo->where.r.
+ (simplify_set): Use subst_mode instead of SUBST_MODE, change first
+ argument from regno_reg_rtx[whatever] to whatever.
+
+2022-04-06 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105069
+ * config/sh/sh.opt (mdiv=): Add Save.
+
+2022-04-06 Martin Liska <mliska@suse.cz>
+
+ PR driver/105096
+ * common.opt: Document properly based on what it does.
+ * gcc.cc (display_help): Unify with what we have in common.opt.
+ * opts.cc (common_handle_option): Do not print undocumented
+ options.
+
+2022-04-06 Xi Ruoyao <xry111@mengyan1223.wang>
+
+ * config/mips/mips.cc (mips_fpr_return_fields): Ignore
+ cxx17_empty_base_field_p fields and set an indicator.
+ (mips_return_in_msb): Adjust for mips_fpr_return_fields change.
+ (mips_function_value_1): Inform psABI change about C++17 empty
+ bases.
+
+2022-04-06 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/105150
+ * gimple.cc (gimple_builtin_call_types_compatible_p): Use
+ builtin_decl_explicit here...
+ (gimple_call_builtin_p, gimple_call_combined_fn): ... rather than
+ here.
+
+2022-04-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105173
+ * tree-ssa-reassoc.cc (find_insert_point): Get extra
+ insert_before output argument and compute it.
+ (insert_stmt_before_use): Adjust.
+ (rewrite_expr_tree): Likewise.
+
+2022-04-06 Richard Biener <rguenther@suse.de>
+
+ PR ipa/105166
+ * ipa-modref-tree.cc (modref_access_node::get_ao_ref ): Bail
+ out for non-pointer arguments.
+
+2022-04-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105163
+ * tree-ssa-reassoc.cc (repropagate_negates): Avoid propagating
+ negated abnormals.
+
+2022-04-06 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/105150
+ * gimple.cc (gimple_call_builtin_p, gimple_call_combined_fn):
+ For BUILT_IN_NORMAL calls, call gimple_builtin_call_types_compatible_p
+ preferrably on builtin_decl_explicit decl rather than fndecl.
+ * tree-ssa-strlen.cc (valid_builtin_call): Don't call
+ gimple_builtin_call_types_compatible_p here.
+
+2022-04-06 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR tree-optimization/103761
+ * tree-vect-stmts.cc (check_load_store_for_partial_vectors): Replace
+ the ncopies parameter with an slp_node parameter. Calculate the
+ number of vectors based on it and vectype. Rename lambda to
+ group_memory_nvectors.
+ (vectorizable_store, vectorizable_load): Update calls accordingly.
+
+2022-04-06 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Document it.
+
+2022-04-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105148
+ * tree-ssa-loop-ivopts.cc (idx_record_use): Walk raw operands
+ 2 and 3 of ARRAY_REFs.
+
+2022-04-06 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/sse.md (ANDNOT_MODE): New mode iterator for TF and V1TI.
+ (*andnottf3): Replace with...
+ (*andnot<mode>3): New define_insn using ANDNOT_MODE.
+
+2022-04-06 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105142
+ * gimple-fold.h (maybe_fold_and_comparisons): Add defaulted
+ basic-block parameter.
+ (maybe_fold_or_comparisons): Likewise.
+ * gimple-fold.cc (follow_outer_ssa_edges): New.
+ (maybe_fold_comparisons_from_match_pd): Use follow_outer_ssa_edges
+ when an outer condition basic-block is specified.
+ (and_comparisons_1, and_var_with_comparison,
+ and_var_with_comparison_1, or_comparisons_1,
+ or_var_with_comparison, or_var_with_comparison_1): Receive and pass
+ down the outer condition basic-block.
+ * tree-ssa-ifcombine.cc (ifcombine_ifandif): Pass down the
+ basic-block of the outer condition.
+
+2022-04-06 Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/105002
+ * config/rs6000/rs6000.cc (rs6000_maybe_emit_maxc_minc): Support more
+ comparison codes UNLT/UNLE/UNGT/UNGE.
+
+2022-04-05 David Malcolm <dmalcolm@redhat.com>
+
+ * doc/extend.texi (Common Function Attributes): Document that
+ 'access' does not imply 'nonnull'.
+
+2022-04-05 Uroš Bizjak <ubizjak@gmail.com>
+
+ PR target/105139
+ * config/i386/mmx.md (*movv2qi_internal):
+ Change insn mode of alternative 5 to HF for TARGET_AVX512FP16.
+
+2022-04-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ * config/aarch64/aarch64.md (aarch64_cpymemdi): Turn into a
+ define_expand and turn operands 0 and 1 from REGs to MEMs.
+ (*aarch64_cpymemdi): New pattern.
+ (aarch64_setmemdi): Turn into a define_expand and turn operand 0
+ from a REG to a MEM.
+ (*aarch64_setmemdi): New pattern.
+ * config/aarch64/aarch64.cc (aarch64_expand_cpymem_mops): Use
+ copy_to_mode_reg on all three registers. Replace the original
+ MEM addresses rather than creating wild reads and writes.
+ (aarch64_expand_setmem_mops): Likewise for the size and for the
+ destination memory and address.
+
+2022-04-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/103147
+ * config/aarch64/aarch64-protos.h (aarch64_simd_switcher): New class.
+ * config/aarch64/aarch64-sve-builtins.h (sve_switcher): Inherit
+ from aarch64_simd_switcher.
+ * config/aarch64/aarch64-builtins.cc (aarch64_simd_tuple_modes):
+ New variable.
+ (aarch64_lookup_simd_builtin_type): Use it instead of TYPE_MODE.
+ (register_tuple_type): Add more asserts. Expect the alignment
+ of the structure to be subject to flag_pack_struct and
+ maximum_field_alignment. Set aarch64_simd_tuple_modes.
+ (aarch64_simd_switcher::aarch64_simd_switcher): New function.
+ (aarch64_simd_switcher::~aarch64_simd_switcher): Likewise.
+ (handle_arm_neon_h): Hold an aarch64_simd_switcher throughout.
+ (aarch64_general_init_builtins): Hold an aarch64_simd_switcher
+ while calling aarch64_init_simd_builtins.
+ * config/aarch64/aarch64-sve-builtins.cc (sve_switcher::sve_switcher)
+ (sve_switcher::~sve_switcher): Remove code now performed by
+ aarch64_simd_switcher.
+
+2022-04-05 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR target/104897
+ * config/aarch64/aarch64-sve-builtins.cc
+ (function_resolver::infer_vector_or_tuple_type): Use error_n
+ for "%d vectors" messages.
+
+2022-04-05 Chung-Lin Tang <cltang@codesourcery.com>
+
+ * omp-low.cc (lower_omp_target): Use outer context looked-up 'var' as
+ argument to lang_hooks.decls.omp_array_data, instead of 'ovar' from
+ current clause.
+
+2022-04-05 Richard Biener <rguenther@suse.de>
+
+ PR c/105151
+ * passes.def (pass_walloca): Move early instance into
+ pass_build_ssa_passes to make SSA form available.
+
+2022-04-05 liuhongt <hongtao.liu@intel.com>
+
+ PR target/101908
+ * config/i386/i386.cc (ix86_split_stlf_stall_load): New
+ function
+ (ix86_reorg): Call ix86_split_stlf_stall_load.
+ * config/i386/i386.opt (-param=x86-stlf-window-ninsns=): New
+ param.
+
+2022-04-05 Alexandre Oliva <oliva@adacore.com>
+
+ * targhooks.cc (default_zero_call_used_regs): Attempt to group
+ regs that the target refuses to use in their natural modes.
+ (zcur_select_mode_rtx): New.
+ * regs.h (struct target_regs): Add x_hard_regno_max_nregs.
+ (hard_regno_max_nregs): Define.
+ * reginfo.cc (init_reg_modes_target): Set hard_regno_max_nregs.
+
+2022-04-04 Alex Coplan <alex.coplan@arm.com>
+
+ * doc/match-and-simplify.texi: Fix typos.
+
+2022-04-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105144
+ * config/aarch64/t-aarch64 (s-aarch64-tune-md): Do move-if-change
+ only if configured with --enable-maintainer-mode, otherwise compare
+ tmp-aarch64-tune.md with $(srcdir)/config/aarch64/aarch64-tune.md and
+ if they differ, emit a message and fail.
+
+2022-04-04 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105144
+ * config/aarch64/t-aarch64 (s-mddeps): Depend on s-aarch64-tune-md.
+ * config/aarch64/aarch64-tune.md: Regenerated.
+
+2022-04-04 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105132
+ * tree-vect-stmts.cc (vectorizable_operation): Check that
+ the input vectors have the same number of elements.
+
+2022-04-04 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105140
+ * fold-const.cc (fold_convertible_p): Allow a TYPE_P arg.
+
+2022-04-03 Jeff Law <jeffreyalaw@gmail.com>
+
+ PR target/104987
+ * config/iq2000/iq2000.md (bbi): New attribute, default to no.
+ (delay slot descripts): Use different delay slot description when
+ the insn as the "bbi" attribute.
+ (bbi, bbin patterns): Set the bbi attribute to yes.
+
+2022-04-03 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/105123
+ * config/i386/i386-expand.cc (ix86_expand_vector_init_general): Avoid
+ using word as target for expand_simple_binop when doing ASHIFT and
+ IOR.
+
+2022-04-02 Xi Ruoyao <xry111@mengyan1223.wang>
+
+ * config/mips/mips.cc (mips_function_arg): Check if DECL_SIZE is
+ NULL before dereferencing it.
+
+2022-04-01 Qing Zhao <qing.zhao@oracle.com>
+
+ * config/i386/i386.cc (zero_all_st_registers): Return the value of
+ num_of_st.
+ (ix86_zero_call_used_regs): Update zeroed_hardregs set according to
+ the return value of zero_all_st_registers.
+ * doc/tm.texi: Update the documentation of TARGET_ZERO_CALL_USED_REGS.
+ * function.cc (gen_call_used_regs_seq): Add an assertion.
+ * target.def: Update the documentation of TARGET_ZERO_CALL_USED_REGS.
+
+2022-04-01 Xi Ruoyao <xry111@mengyan1223.wang>
+
+ PR target/102024
+ * config/mips/mips.cc (mips_function_arg): Ignore zero-width
+ fields, and inform if it causes a psABI change.
+
+2022-04-01 Xi Ruoyao <xry111@mengyan1223.wang>
+
+ PR target/102024
+ * config/mips/mips.cc (mips_fpr_return_fields): Detect C++
+ zero-width bit-fields and set up an indicator.
+ (mips_return_in_msb): Adapt for mips_fpr_return_fields change.
+ (mips_function_value_1): Diagnose when the presense of a C++
+ zero-width bit-field changes function returning in GCC 12.
+
+2022-04-01 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/104645
+ * tree-ssa-phiopt.cc (value_replacement): If assign has
+ CONVERT_EXPR_CODE_P rhs_code, treat it like a preparation
+ statement with constant evaluation.
+
+2022-04-01 YunQiang Su <yunqiang.su@cipunited.com>
+
+ * config/mips/mips.cc (mips_expand_prologue):
+ IPL is 8bit for MCU ASE.
+
+2022-03-31 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ PR target/104004
+ * config/rs6000/rs6000-builtins.def (MFFSL): Mark nosoft.
+ (MTFSB0): Likewise.
+ (MTFSB1): Likewise.
+ (SET_FPSCR_RN): Likewise.
+ (SET_FPSCR_DRN): Mark nosoft and no32bit.
+
+2022-03-31 Thomas Schwinge <thomas@codesourcery.com>
+
+ * doc/options.texi (Option file format): Clarifications around
+ option definition records' help texts.
+
+2022-03-31 Thomas Schwinge <thomas@codesourcery.com>
+
+ * optc-gen.awk <END>: Fix "Multiple different help strings" error
+ diagnostic.
+
+2022-03-31 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64.cc (aarch64_vector_costs): Define
+ determine_suggested_unroll_factor and m_has_avg.
+ (determine_suggested_unroll_factor): New function.
+ (aarch64_vector_costs::add_stmt_cost): Check for a qualifying pattern
+ to set m_nosve_pattern.
+ (aarch64_vector_costs::finish_costs): Use
+ determine_suggested_unroll_factor.
+ * config/aarch64/aarch64.opt (aarch64-vect-unroll-limit): New.
+ * doc/invoke.texi: (aarch64-vect-unroll-limit): Document new option.
+
+2022-03-31 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/103083
+ * ipa-prop.h (ipa_ancestor_jf_data): New flag keep_null;
+ (ipa_get_jf_ancestor_keep_null): New function.
+ * ipa-prop.cc (ipa_set_ancestor_jf): Initialize keep_null field of the
+ ancestor function.
+ (compute_complex_assign_jump_func): Pass false to keep_null
+ parameter of ipa_set_ancestor_jf.
+ (compute_complex_ancestor_jump_func): Pass true to keep_null
+ parameter of ipa_set_ancestor_jf.
+ (update_jump_functions_after_inlining): Carry over keep_null from the
+ original ancestor jump-function or merge them.
+ (ipa_write_jump_function): Stream keep_null flag.
+ (ipa_read_jump_function): Likewise.
+ (ipa_print_node_jump_functions_for_edge): Print the new flag.
+ * ipa-cp.cc (class ipcp_bits_lattice): Make various getters const. New
+ member function known_nonzero_p.
+ (ipcp_bits_lattice::known_nonzero_p): New.
+ (ipcp_bits_lattice::meet_with_1): New parameter drop_all_ones,
+ observe it.
+ (ipcp_bits_lattice::meet_with): Likewise.
+ (propagate_bits_across_jump_function): Simplify. Pass true in
+ drop_all_ones when it is necessary.
+ (propagate_aggs_across_jump_function): Take care of keep_null
+ flag.
+ (ipa_get_jf_ancestor_result): Propagate NULL accross keep_null
+ jump functions.
+
+2022-03-31 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/102513
+ * ipa-cp.cc (decide_whether_version_node): Skip scalar values
+ which do not fit the known value_range.
+
+2022-03-31 Martin Jambor <mjambor@suse.cz>
+
+ PR ipa/103171
+ * ipa-prop.cc (propagate_controlled_uses): Add a LOAD reference
+ always when an ADDR_EXPR constant is known to reach a load because
+ of inlining, not just when removing an ADDR reference.
+
+2022-03-31 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105109
+ * tree-ssa.cc (execute_update_addresses_taken): Suppress
+ diagnostics on the load of the other complex component.
+
+2022-03-31 Tom de Vries <tdevries@suse.de>
+
+ * config/nvptx/nvptx.h (ASM_SPEC): Use "-m sm_35" for -misa=sm_30.
+
+2022-03-31 Richard Biener <rguenther@suse.de>
+
+ PR rtl-optimization/105091
+ * gimple-expr.cc (mark_addressable): Handle TARGET_MEM_REF
+ bases.
+
+2022-03-31 Richard Biener <rguenther@suse.de>
+
+ Revert:
+ 2021-09-13 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/102125
+ * gimple-fold.c (gimple_fold_builtin_memory_op): Allow folding
+ memcpy if the size is not more than MOVE_MAX * MOVE_RATIO.
+
+2022-03-31 Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+ * gcov-io.cc (gcov_read_string): Reword documentation comment.
+
+2022-03-30 Bill Schmidt <wschmidt@linux.ibm.com>
+
+ * config/rs6000/rs6000-builtins.def (NEG_V16QI): Move to [altivec]
+ stanza.
+ (NEG_V4SF): Likewise.
+ (NEG_V4SI): Likewise.
+ (NEG_V8HI): Likewise.
+ (NEG_V2DF): Move to [vsx] stanza.
+ (NEG_V2DI): Likewise.
+
+2022-03-30 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR middle-end/105032
+ * lra-assigns.cc (find_reload_regno_insns): Modify loop condition.
+
+2022-03-30 Tom de Vries <tdevries@suse.de>
+ Tobias Burnus <tobias@codesourcery.com>
+
+ * doc/invoke.texi (march): Document __PTX_SM__.
+ (mptx): Document __PTX_ISA_VERSION_MAJOR__ and
+ __PTX_ISA_VERSION_MINOR__.
+
+2022-03-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR sanitizer/105093
+ * ubsan.cc (instrument_object_size): If t is equal to inner and
+ is a decl other than global var, punt. When emitting call to
+ UBSAN_OBJECT_SIZE ifn, make sure base is addressable.
+
+2022-03-30 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/105094
+ * gimple-ssa-store-merging.cc (mem_valid_for_store_merging): Punt if
+ bitsize <= 0 rather than just == 0.
+
+2022-03-30 Tom de Vries <tdevries@suse.de>
+
+ * doc/invoke.texi (misa, mptx): Update.
+ (march, march-map): Add.
+
+2022-03-30 Thomas Schwinge <thomas@codesourcery.com>
+
+ * opt-functions.awk (n_args): New function.
+ (lang_enabled_by): Merge function into...
+ * optc-gen.awk <END>: ... sole user here.
+ Improve diagnostics.
+
+2022-03-29 Marek Polacek <polacek@redhat.com>
+ Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/103597
+ * gimplify.cc (collect_fallthrough_labels): Don't push UNUSED_LABEL_Ps
+ into labels. Maybe set prev to the statement preceding UNUSED_LABEL_P.
+ (gimplify_cond_expr): Set UNUSED_LABEL_P.
+ * tree.h (UNUSED_LABEL_P): New.
+
+2022-03-29 Michael Meissner <meissner@linux.ibm.com>
+
+ * config/rs6000/vsx.md (vsx_extract_<mode>): Allow destination to
+ be any VSX register.
+
+2022-03-29 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/102024
+ * config/aarch64/aarch64.cc (aapcs_vfp_sub_candidate): Handle
+ zero-sized bit-fields. Detect cases where a warning may be needed.
+ (aarch64_vfp_is_call_or_return_candidate): Emit a note if a
+ zero-sized bit-field has caused parameter passing to change.
+
+2022-03-29 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/102024
+ * config/arm/arm.cc (aapcs_vfp_sub_candidate): Handle zero-sized
+ bit-fields. Detect cases where a warning may be needed.
+ (aapcs_vfp_is_call_or_return_candidate): Emit a note if
+ a zero-sized bit-field has caused parameter passing to change.
+
+2022-03-29 Richard Earnshaw <rearnsha@arm.com>
+
+ PR target/96882
+ * config/arm/arm.cc (arm_get_pcs_model): Disable selection of
+ ARM_PCS_AAPCS_LOCAL.
+
+2022-03-29 Tom de Vries <tdevries@suse.de>
+
+ PR target/104857
+ * config/nvptx/nvptx-c.cc (nvptx_cpu_cpp_builtins): Emit
+ __PTX_ISA_VERSION_MAJOR__ and __PTX_ISA_VERSION_MINOR__.
+ * config/nvptx/nvptx.cc (ptx_version_to_number): New function.
+ * config/nvptx/nvptx-protos.h (ptx_version_to_number): Declare.
+
+2022-03-29 Tom de Vries <tdevries@suse.de>
+
+ * config/nvptx/nvptx.opt (m64): Update help text to reflect that it
+ is ignored.
+
+2022-03-29 Tom de Vries <tdevries@suse.de>
+
+ PR target/104714
+ * config/nvptx/nvptx.opt (march-map=*): Add aliases.
+
+2022-03-29 Jan Hubicka <hubicka@ucw.cz>
+
+ * config/i386/i386-builtins.cc (ix86_vectorize_builtin_gather): Test
+ TARGET_USE_GATHER_2PARTS and TARGET_USE_GATHER_4PARTS.
+ * config/i386/i386.h (TARGET_USE_GATHER_2PARTS): New macro.
+ (TARGET_USE_GATHER_4PARTS): New macro.
+ * config/i386/x86-tune.def (X86_TUNE_USE_GATHER_2PARTS): New tune
+ (X86_TUNE_USE_GATHER_4PARTS): New tune
+
+2022-03-29 Tom de Vries <tdevries@suse.de>
+
+ * config/nvptx/nvptx.opt (march): Add alias of misa.
+
+2022-03-29 Chenghua Xu <xuchenghua@loongson.cn>
+ Lulu Cheng <chenglulu@loongson.cn>
+
+ * doc/install.texi: Add LoongArch options section.
+ * doc/invoke.texi: Add LoongArch options section.
+ * doc/md.texi: Add LoongArch options section.
+
+2022-03-29 Chenghua Xu <xuchenghua@loongson.cn>
+ Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/loongarch-c.cc
+
+2022-03-29 Chenghua Xu <xuchenghua@loongson.cn>
+ Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/larchintrin.h: New file.
+ * config/loongarch/loongarch-builtins.cc: New file.
+
+2022-03-29 Chenghua Xu <xuchenghua@loongson.cn>
+ Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/host-linux.cc: Add LoongArch support.
+ * config/loongarch/loongarch-protos.h: New file.
+ * config/loongarch/loongarch-tune.h: Likewise.
+ * config/loongarch/loongarch.cc: Likewise.
+ * config/loongarch/loongarch.h: Likewise.
+
+2022-03-29 Chenghua Xu <xuchenghua@loongson.cn>
+ Lulu Cheng <chenglulu@loongson.cn>
+
+ * config/loongarch/constraints.md: New file.
+ * config/loongarch/generic.md: New file.
+ * config/loongarch/la464.md: New file.
+ * config/loongarch/loongarch-ftypes.def: New file.
+ * config/loongarch/loongarch-modes.def: New file.
+ * config/loongarch/loongarch.md: New file.
+ * config/loongarch/predicates.md: New file.
+ * config/loongarch/sync.md: New file.
+
+2022-03-29 Chenghua Xu <xuchenghua@loongson.cn>
+ Lulu Cheng <chenglulu@loongson.cn>
+
+ * configure: Regenerate file.
+
+2022-03-29 Chenghua Xu <xuchenghua@loongson.cn>
+ Lulu Cheng <chenglulu@loongson.cn>
+
+ * common/config/loongarch/loongarch-common.cc: New file.
+ * config/loongarch/genopts/genstr.sh: New file.
+ * config/loongarch/genopts/loongarch-strings: New file.
+ * config/loongarch/genopts/loongarch.opt.in: New file.
+ * config/loongarch/loongarch-str.h: New file.
+ * config/loongarch/gnu-user.h: New file.
+ * config/loongarch/linux.h: New file.
+ * config/loongarch/loongarch-cpu.cc: New file.
+ * config/loongarch/loongarch-cpu.h: New file.
+ * config/loongarch/loongarch-def.c: New file.
+ * config/loongarch/loongarch-def.h: New file.
+ * config/loongarch/loongarch-driver.cc: New file.
+ * config/loongarch/loongarch-driver.h: New file.
+ * config/loongarch/loongarch-opts.cc: New file.
+ * config/loongarch/loongarch-opts.h: New file.
+ * config/loongarch/loongarch.opt: New file.
+ * config/loongarch/t-linux: New file.
+ * config/loongarch/t-loongarch: New file.
+ * config.gcc: Add LoongArch support.
+ * configure.ac: Add LoongArch support.
+
+2022-03-29 Thomas Schwinge <thomas@codesourcery.com>
+
+ * opt-functions.awk (lang_enabled_by): Fix 'enabledby_negargs'
+ typo.
+
+2022-03-29 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105080
+ * tree-ssa-strlen.cc (printf_strlen_execute): Always init
+ loops and SCEV.
+
+2022-03-28 Indu Bhagat <indu.bhagat@oracle.com>
+
+ * ctfout.cc (ctf_preprocess): Use ctfc_get_num_ctf_vars instead.
+ (output_ctf_vars): Likewise.
+
+2022-03-28 Jason Merrill <jason@redhat.com>
+
+ PR c++/59426
+ * doc/extend.texi: Refer to __is_trivial instead of __is_pod.
+
+2022-03-28 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/105068
+ * config/i386/sse.md (*ssse3_pshufbv8qi3): Also replace "Yv" with
+ "Yw" in clobber.
+
+2022-03-28 Tom de Vries <tdevries@suse.de>
+
+ PR target/104818
+ * config/nvptx/gen-opt.sh (ptx_isa): Improve help text.
+ * config/nvptx/nvptx-gen.opt: Regenerate.
+ * config/nvptx/nvptx.opt (misa, mptx, ptx_version): Improve help text.
+ * config/nvptx/t-nvptx (s-nvptx-gen-opt): Add missing dependency on
+ gen-opt.sh.
+
+2022-03-28 David Malcolm <dmalcolm@redhat.com>
+
+ PR analyzer/104308
+ * gimple-fold.cc (gimple_fold_builtin_memory_op): When optimizing
+ to loads then stores, set the location of the new load stmt.
+
+2022-03-28 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105070
+ * tree-switch-conversion.h
+ (bit_test_cluster::hoist_edge_and_branch_if_true): Add location
+ argument.
+ * tree-switch-conversion.cc
+ (bit_test_cluster::hoist_edge_and_branch_if_true): Annotate
+ cond with location.
+ (bit_test_cluster::emit): Annotate all generated expressions
+ with location.
+
+2022-03-28 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64-cores.def: Update Neoverse N2 core entry.
+
+2022-03-28 liuhongt <hongtao.liu@intel.com>
+
+ PR target/105066
+ * config/i386/sse.md (vec_set<mode>_0): Change attr "isa" of
+ alternative 4 from sse4_noavx to noavx.
+
+2022-03-28 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/105056
+ * tree-predcom.cc (component::component): Initialize also comp_step.
+
+2022-03-27 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/105068
+ * config/i386/sse.md (*ssse3_pshufbv8qi3): Replace "Yv" with
+ "Yw".
+
+2022-03-26 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR middle-end/104885
+ * calls.cc (mark_stack_region_used): Check that the region
+ is within the allocated size of stack_usage_map.
+
+2022-03-26 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/103775
+ * recog.cc (check_invalid_inc_dec): New function.
+ (insn_invalid_p): Return 1 if REG_INC operand overlaps
+ any stored REGs.
+
+2022-03-26 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/105058
+ * config/i386/sse.md (loadiwkey): Replace "v" with "x".
+ (aes<aesklvariant>u8): Likewise.
+
+2022-03-26 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/105052
+ * config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3):
+ Replace "Yv" with "x".
+ (ssse3_ph<plusminus_mnemonic>dv2si3): Likewise.
+ (ssse3_psign<mode>3): Likewise.
+
+2022-03-26 Hans-Peter Nilsson <hp@axis.com>
+
+ * reload.cc (find_reloads): Align comment with code where
+ considering the intersection of register classes then tweaking the
+ regclass for the current alternative or rejecting it.
+
+2022-03-25 Christophe Lyon <christohe.lyon@arm.com>
+
+ PR target/104882
+ Revert
+ 2021-06-11 Christophe Lyon <christophe.lyon@linaro.org>
+
+ * config/arm/mve.md (mve_vec_unpack<US>_lo_<mode>): Delete.
+ (mve_vec_unpack<US>_hi_<mode>): Delete.
+ (@mve_vec_pack_trunc_lo_<mode>): Delete.
+ (mve_vmovntq_<supf><mode>): Remove '@' prefix.
+ * config/arm/neon.md (vec_unpack<US>_hi_<mode>): Move back
+ from vec-common.md.
+ (vec_unpack<US>_lo_<mode>): Likewise.
+ (vec_pack_trunc_<mode>): Rename from
+ neon_quad_vec_pack_trunc_<mode>.
+ * config/arm/vec-common.md (vec_unpack<US>_hi_<mode>): Delete.
+ (vec_unpack<US>_lo_<mode>): Delete.
+ (vec_pack_trunc_<mode>): Delete.
+
+2022-03-25 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR middle-end/104971
+ * lra-lives.cc (process_bb_lives): Check hard_regs_live for hard
+ regs to clear remove_p flag.
+
+2022-03-25 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105053
+ * tree-vect-loop.cc (vect_create_epilog_for_reduction): Pick
+ the correct live-out stmt for a reduction chain.
+
+2022-03-25 Richard Biener <rguenther@suse.de>
+
+ PR middle-end/105049
+ * tree.cc (uniform_vector_p): Recurse for VECTOR_CST or
+ CONSTRUCTOR first elements.
+
+2022-03-25 Tobias Burnus <tobias@codesourcery.com>
+
+ PR analyzer/103533
+ * doc/invoke.texi (Static Analyzer Options): Move
+ @ignore block after @gccoptlist's '}' for 'make pdf'.
+
+2022-03-25 David Malcolm <dmalcolm@redhat.com>
+
+ PR analyzer/104954
+ * doc/invoke.texi (Static Analyzer Options): Add
+ -fdump-analyzer-untracked.
+
+2022-03-25 Avinash Sonawane <rootkea@gmail.com>
+
+ PR analyzer/103533
+ * doc/invoke.texi: Document that enabling taint analyzer
+ checker disables some warnings from `-fanalyzer`.
+
+2022-03-24 Alexandre Oliva <oliva@adacore.com>
+
+ PR debug/104564
+ * gimple-harden-conditionals.cc (detach_value): Keep temps
+ anonymous.
+
+2022-03-24 Alexandre Oliva <oliva@adacore.com>
+
+ PR middle-end/104975
+ * gimple-harden-conditionals.cc
+ (pass_harden_compares::execute): Force split in case of
+ multiple edges.
+
+2022-03-24 Jakub Jelinek <jakub@redhat.com>
+
+ PR c++/105035
+ * fold-const.cc (operand_equal_p) <case COMPONENT_REF>: If either
+ field0 or field1 is not a FIELD_DECL, return false.
+
+2022-03-24 Richard Biener <rguenther@suse.de>
+
+ * tree-predcom.cc (chain::chain): Add CTOR.
+ (component::component): Likewise.
+ (pcom_worker::release_chain): Use delete.
+ (release_components): Likewise.
+ (pcom_worker::filter_suitable_components): Likewise.
+ (pcom_worker::split_data_refs_to_components): Use new.
+ (make_invariant_chain): Likewise.
+ (make_rooted_chain): Likewise.
+ (pcom_worker::combine_chains): Likewise.
+ * tree-vect-loop.cc (vect_create_epilog_for_reduction):
+ Make sure to release previously constructed scalar_results.
+ * tree-vect-stmts.cc (vectorizable_load): Use auto_vec
+ for vec_offsets.
+ * vr-values.cc (simplify_using_ranges::~simplify_using_ranges):
+ Release m_flag_set_edges.
+
+2022-03-24 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ PR tree-optimization/104970
+ * tree-object-size.cc (parm_object_size): Restrict size
+ computation scenarios to explicit access attributes.
+
+2022-03-24 Kewen Lin <linkw@linux.ibm.com>
+
+ PR target/104967
+ * config/rs6000/rs6000-c.cc (find_instance): Skip instances with null
+ function types.
+
+2022-03-23 Richard Biener <rguenther@suse.de>
+
+ PR target/102125
+ * gimple-fold.cc (gimple_fold_builtin_memory_op): Allow the
+ use of movmisalign when either the source or destination
+ decl is properly aligned.
+
+2022-03-23 Richard Biener <rguenther@suse.de>
+
+ PR rtl-optimization/105028
+ * ira-color.cc (form_threads_from_copies): Remove unnecessary
+ copying of the sorted_copies tail.
+
+2022-03-23 Martin Liska <mliska@suse.cz>
+
+ * config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
+ Use %qs in format.
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal):
+ Reword the error message.
+
+2022-03-23 liuhongt <hongtao.liu@intel.com>
+
+ PR target/104976
+ * config/i386/sse.md (ssePSmodelower): New.
+ (*avx_cmp<mode>3_ltint_not): Force_reg operand before
+ lowpart_subreg to avoid NULL_RTX.
+ (<avx512>_fmaddc_<mode>_mask1<round_expand_name>,
+ <avx512>_fcmaddc_<mode>_mask1<round_expand_name>,
+ fma_<mode>_fmaddc_bcst, fma_<mode>_fcmaddc_bcst,
+ <avx512>_<complexopname>_<mode>_mask<round_name>,
+ avx512fp16_fcmaddcsh_v8hf_mask1<round_expand_name>,
+ avx512fp16_fcmaddcsh_v8hf_mask3<round_expand_name>,
+ avx512fp16_fmaddcsh_v8hf_mask3<round_expand_name>,
+ avx512fp16_fmaddcsh_v8hf_mask3<round_expand_name>,
+ float<floatunssuffix><mode>v4hf2,
+ float<floatunssuffix>v2div2hf2,
+ fix<fixunssuffix>_truncv4hf<mode>2,
+ fix<fixunssuffix>_truncv2hfv2di2, extendv4hf<mode>2,
+ extendv2hfv2df2,
+ trunc<mode>v4hf2,truncv2dfv2hf2,
+ *avx512bw_permvar_truncv16siv16hi_1,
+ *avx512bw_permvar_truncv16siv16hi_1_hf,
+ *avx512f_permvar_truncv8siv8hi_1,
+ *avx512f_permvar_truncv8siv8hi_1_hf,
+ *avx512f_vpermvar_truncv8div8si_1,
+ *avx512f_permvar_truncv32hiv32qi_1,
+ *avx512f_permvar_truncv16hiv16qi_1,
+ *avx512f_permvar_truncv4div4si_1,
+ *avx512f_pshufb_truncv8hiv8qi_1,
+ *avx512f_pshufb_truncv4siv4hi_1,
+ *avx512f_pshufd_truncv2div2si_1,
+ sdot_prod<mode>, avx2_pblend<ssemodesuffix>_1,
+ ashrv2di3,ashrv2di3,usdot_prod<mode>): Ditto.
+
+2022-03-22 Tom de Vries <tdevries@suse.de>
+
+ PR target/104925
+ * config/nvptx/nvptx.md (define_insn "nvptx_uniform_warp_check"):
+ Use % as register prefix.
+
+2022-03-22 Tom de Vries <tdevries@suse.de>
+
+ * config/nvptx/nvptx.cc (nvptx_scalar_mode_supported_p)
+ (nvptx_libgcc_floating_mode_supported_p): Only enable HFmode for
+ mexperimental.
+
+2022-03-22 Tom de Vries <tdevries@suse.de>
+
+ * config/nvptx/nvptx.opt (mexperimental): New option.
+
+2022-03-22 Tom de Vries <tdevries@suse.de>
+
+ PR target/104957
+ * config/nvptx/nvptx-protos.h (nvptx_asm_output_def_from_decls): Declare.
+ * config/nvptx/nvptx.cc (write_fn_proto_1): Don't add function marker
+ for alias.
+ (SET_ASM_OP, NVPTX_ASM_OUTPUT_DEF): New macro def.
+ (nvptx_asm_output_def_from_decls): New function.
+ * config/nvptx/nvptx.h (ASM_OUTPUT_DEF): New macro def, define to
+ gcc_unreachable ().
+ (ASM_OUTPUT_DEF_FROM_DECLS): New macro def, define to
+ nvptx_asm_output_def_from_decls.
+ * config/nvptx/nvptx.opt (malias): New opt.
+
+2022-03-22 Tom de Vries <tdevries@suse.de>
+
+ PR target/104916
+ PR target/104783
+ * config/nvptx/nvptx.md (define_expand "omp_simt_exit"): Emit warp
+ sync (or uniform warp check for mptx < 6.0).
+
+2022-03-22 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/105012
+ * tree-if-conv.cc (ifcvt_local_dce): Only call
+ dse_classify_store when we have a VDEF.
+
+2022-03-22 Martin Liska <mliska@suse.cz>
+
+ PR target/104902
+ * config/nvptx/nvptx.cc (handle_ptx_version_option):
+ Fix option wrapping in an error message.
+
+2022-03-22 Martin Liska <mliska@suse.cz>
+
+ PR target/104903
+ * config/rs6000/rs6000-c.cc (altivec_resolve_overloaded_builtin):
+ Wrap const keyword.
+
+2022-03-22 Martin Liska <mliska@suse.cz>
+
+ * config/v850/v850-c.cc (pop_data_area): Fix typo in pragma
+ name.
+
+2022-03-22 Martin Liska <mliska@suse.cz>
+
+ PR target/104898
+ * config/rs6000/rs6000.cc (rs6000_option_override_internal):
+ Use %qs instead of (%qs).
+
+2022-03-22 Martin Liska <mliska@suse.cz>
+
+ PR target/104898
+ * config/i386/i386-options.cc (ix86_option_override_internal):
+ Use '%qs' instead of '(%qs)'.
+
+2022-03-22 Martin Liska <mliska@suse.cz>
+
+ PR target/104898
+ * config/aarch64/aarch64.cc (aarch64_handle_attr_arch):
+ Use 'qs' and remove usage '(%qs)'.
+ (aarch64_handle_attr_cpu): Likewise.
+ (aarch64_handle_attr_tune): Likewise.
+ (aarch64_handle_attr_isa_flags): Likewise.
+
+2022-03-22 Tamar Christina <tamar.christina@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64.cc (neoversev1_regmove_cost): New tuning
+ struct.
+ (neoversev1_tunings): Use neoversev1_regmove_cost and update store_int
+ cost.
+ (neoverse512tvb_tunings): Likewise.
+
+2022-03-22 Tamar Christina <tamar.christina@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64.cc (demeter_addrcost_table,
+ demeter_regmove_cost, demeter_advsimd_vector_cost,
+ demeter_sve_vector_cost, demeter_scalar_issue_info,
+ demeter_advsimd_issue_info, demeter_sve_issue_info,
+ demeter_vec_issue_info, demeter_vector_cost,
+ demeter_tunings): New tuning structs.
+ (aarch64_ve_op_count::rename_cycles_per_iter): Enable for demeter
+ tuning.
+ * config/aarch64/aarch64-cores.def: Add entry for demeter.
+ * config/aarch64/aarch64-tune.md (tune): Add demeter to list.
+
+2022-03-22 Tamar Christina <tamar.christina@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64-protos.h (struct cpu_memmov_cost): New struct.
+ (struct tune_params): Change type of memmov_cost to use cpu_memmov_cost.
+ * config/aarch64/aarch64.cc (aarch64_memory_move_cost): Update all
+ tunings to use cpu_memmov_cost struct.
+
+2022-03-22 Tamar Christina <tamar.christina@arm.com>
+ Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64.cc (neoversen2_addrcost_table,
+ neoversen2_regmove_cost, neoversen2_advsimd_vector_cost,
+ neoversen2_sve_vector_cost, neoversen2_scalar_issue_info,
+ neoversen2_advsimd_issue_info, neoversen2_sve_issue_info,
+ neoversen2_vec_issue_info, neoversen2_tunings): New structs.
+ (neoversen2_tunings): Use new structs and update tuning flags.
+ (aarch64_vec_op_count::rename_cycles_per_iter): Enable for neoversen2
+ tuning.
+
+2022-03-22 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/aarch64/aarch64.h (AARCH64_FL_FOR_ARCH9): Add FP16 feature
+ bit.
+
+2022-03-22 liuhongt <hongtao.liu@intel.com>
+
+ PR target/104982
+ * config/i386/i386.md (*jcc_bt<mode>_mask): Extend the
+ following splitter to reversed condition.
+
+2022-03-22 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/104989
+ * calls.cc (expand_call): Don't set ECF_NORETURN in flags after
+ sorry for passing too large argument, instead set sibcall_failure
+ for pass == 0, or a new normal_failure flag otherwise. If
+ normal_failure is set, don't assert all stack has been deallocated
+ at the end and throw away the whole insn sequence.
+
+2022-03-22 Qian Jianhua <qianjh@cn.fujitsu.com>
+
+ * print-tree.cc: Change array length
+
+2022-03-22 Hongyu Wang <hongyu.wang@intel.com>
+
+ PR target/104978
+ * config/i386/sse.md
+ (avx512fp16_fmaddcsh_v8hf_mask1<round_expand_name):
+ Use avx512f_movsf_mask instead of vmovaps or vblend, and
+ force_reg before lowpart_subreg.
+ (avx512fp16_fcmaddcsh_v8hf_mask1<round_expand_name): Likewise.
+
+2022-03-21 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/105000
+ * common/config/i386/i386-common.cc
+ (OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET): Replace
+ OPTION_MASK_ISA2_AVX512F_UNSET with OPTION_MASK_ISA2_SSE_UNSET.
+
+2022-03-21 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/104998
+ * common/config/i386/cpuinfo.h (get_available_features): Pass
+ 0x19 to __cpuid for bit_AESKLE. Enable FEATURE_AESKLE only if
+ bit_AESKLE is set.
+
+2022-03-21 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR middle-end/104869
+ * rtl-ssa/accesses.h (clobber_group::prev_clobber): Declare.
+ (clobber_group::next_clobber): Likewise.
+ (def_lookup::prev_def): Rename to...
+ (def_lookup::last_def_of_prev_group): ...this.
+ (def_lookup::next_def): Rename to...
+ (def_lookup::first_def_of_next_group): ...this.
+ (def_lookup::matching_or_prev_def): Rename to...
+ (def_lookup::matching_set_or_last_def_of_prev_group): ...this.
+ (def_lookup::matching_or_next_def): Rename to...
+ (def_lookup::matching_set_or_first_def_of_next_group): ...this.
+ (def_lookup::prev_def): New function, taking the lookup insn as
+ argument.
+ (def_lookup::next_def): Likewise.
+ * rtl-ssa/member-fns.inl (def_lookup::prev_def): Rename to...
+ (def_lookup::last_def_of_prev_group): ...this.
+ (def_lookup::next_def): Rename to...
+ (def_lookup::first_def_of_next_group): ...this.
+ (def_lookup::matching_or_prev_def): Rename to...
+ (def_lookup::matching_set_or_last_def_of_prev_group): ...this.
+ (def_lookup::matching_or_next_def): Rename to...
+ (def_lookup::matching_set_or_first_def_of_next_group): ...this.
+ * rtl-ssa/movement.h (restrict_movement_for_dead_range): Update after
+ above renaming.
+ * rtl-ssa/accesses.cc (clobber_group::prev_clobber): New function.
+ (clobber_group::next_clobber): Likewise.
+ (def_lookup::prev_def): Likewise.
+ (def_lookup::next_def): Likewise.
+ (function_info::make_use_available): Pass the lookup insn to
+ def_lookup::prev_def and def_lookup::next_def.
+
+2022-03-21 Martin Liska <mliska@suse.cz>
+
+ * doc/invoke.texi: Document min-pagesize parameter.
+
+2022-03-21 Richard Biener <rguenther@suse.de>
+
+ * tree-ssa-loop-niter.cc (estimate_numbers_of_iterations): Dump
+ we are estimating niter of loop.
+
+2022-03-21 Kito Cheng <kito.cheng@sifive.com>
+
+ * common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
+ Update flag name and mask name.
+ * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Define
+ misc macro for vector extensions.
+ * config/riscv/riscv-opts.h (MASK_VECTOR_EEW_32): Rename to ...
+ (MASK_VECTOR_ELEN_32): ... this.
+ (MASK_VECTOR_EEW_64): Rename to ...
+ (MASK_VECTOR_ELEN_64): ... this.
+ (MASK_VECTOR_EEW_FP_32): Rename to ...
+ (MASK_VECTOR_ELEN_FP_32): ... this.
+ (MASK_VECTOR_EEW_FP_64): Rename to ...
+ (MASK_VECTOR_ELEN_FP_64): ... this.
+ (TARGET_VECTOR_ELEN_32): New.
+ (TARGET_VECTOR_ELEN_64): Ditto.
+ (TARGET_VECTOR_ELEN_FP_32): Ditto.
+ (TARGET_VECTOR_ELEN_FP_64): Ditto.
+ (TARGET_MIN_VLEN): Ditto.
+ * config/riscv/riscv.opt (riscv_vector_eew_flags): Rename to ...
+ (riscv_vector_elen_flags): ... this.
+
+2022-03-21 Hongyu Wang <hongyu.wang@intel.com>
+
+ PR target/104977
+ * config/i386/sse.md
+ (avx512fp16_fma<complexopname>sh_v8hf<mask_scalarcz_name><round_scalarcz_name>):
+ Correct round operand for intel dialect.
+
+2022-03-19 Arthur Cohen <arthur.cohen@embecosm.com>
+
+ * diagnostic.cc (diagnostic_cc_tests): Rename to...
+ (c_diagnostic_cc_tests): ...this.
+ * opt-problem.cc (opt_problem_cc_tests): Rename to...
+ (c_opt_problem_cc_tests): ...this.
+ * selftest-run-tests.cc (selftest::run_tests): No longer run
+ opt_problem_cc_tests or diagnostic_cc_tests.
+ * selftest.h (diagnostic_cc_tests): Remove declaration.
+ (opt_problem_cc_tests): Likewise.
+
+2022-03-19 Marc Nieper-Wißkirchen <marc@nieper-wisskirchen.de>
+
+ PR jit/63854
+ * hash-traits.h (struct typed_const_free_remove): New.
+ (struct free_string_hash): New.
+ * pass_manager.h: Use free_string_hash.
+ * passes.cc (pass_manager::register_pass_name): Use free_string_hash.
+ (pass_manager::~pass_manager): Delete allocated m_name_to_pass_map.
+
+2022-03-19 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/104971
+ * config/i386/i386-expand.cc
+ (ix86_expand_builtin) <case IX86_BUILTIN_READ_FLAGS>: If ignore,
+ don't push/pop anything and just return const0_rtx.
+
+2022-03-18 Vladimir N. Makarov <vmakarov@redhat.com>
+
+ PR rtl-optimization/104961
+ * lra-assigns.cc (find_reload_regno_insns): Process reload pseudo clobber.
+
+2022-03-18 Jason Merrill <jason@redhat.com>
+
+ * tree.h (IDENTIFIER_LENGTH): Add comment.
+
+2022-03-18 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/99578
+ PR middle-end/100680
+ PR tree-optimization/100834
+ * params.opt (--param=min-pagesize=): New parameter.
+ * pointer-query.cc
+ (compute_objsize_r) <case ARRAY_REF>: Formatting fix.
+ (compute_objsize_r) <case INTEGER_CST>: Use maximum object size instead
+ of zero for pointer constants equal or larger than min-pagesize.
+
+2022-03-18 Tom de Vries <tdevries@suse.de>
+
+ * gimplify.cc (gimplify_omp_for): Set location using 'input_location'.
+ Set gfor location only when dealing with a OMP_TASKLOOP.
+
+2022-03-18 Tom de Vries <tdevries@suse.de>
+
+ * gimplify.cc (gimplify_omp_for): Set taskloop location.
+
+2022-03-18 Tom de Vries <tdevries@suse.de>
+
+ PR target/104952
+ * omp-low.cc (lower_rec_input_clauses): Make sure GOMP_SIMT_XCHG_BFLY
+ is executed unconditionally.
+
+2022-03-18 liuhongt <hongtao.liu@intel.com>
+
+ PR target/104974
+ * config/i386/i386.md (*movhi_internal): Set attr type from HI
+ to HF for alternative 12 under TARGET_AVX512FP16.
+
+2022-03-18 Cui,Lili <lili.cui@intel.com>
+
+ PR target/104963
+ * config/i386/i386.h (PTA_SAPPHIRERAPIDS): change it to base on ICX.
+ * doc/invoke.texi: Update documents for Intel sapphirerapids.
+
+2022-03-17 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR target/86722
+ PR tree-optimization/90356
+ * config/i386/i386.md (*movtf_internal): Don't guard
+ standard_sse_constant_p clause by optimize_function_for_size_p.
+ (*movdf_internal): Likewise.
+ (*movsf_internal): Likewise.
+
+2022-03-17 Andrew MacLeod <amacleod@redhat.com>
+
+ PR tree-optimization/102943
+ * gimple-range-cache.cc (ranger_cache::range_from_dom): Find range via
+ dominators and apply intermediary outgoing edge ranges.
+
+2022-03-17 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/104960
+ * passes.def: Add pass parameter to pass_sink_code, mark
+ last one to unsplit edges.
+ * tree-ssa-sink.cc (pass_sink_code::set_pass_param): New.
+ (pass_sink_code::execute): Always execute TODO_cleanup_cfg
+ when we need to unsplit edges.
+
+2022-03-17 Jakub Jelinek <jakub@redhat.com>
+
+ PR middle-end/103984
+ * gimplify.cc (gimplify_target_expr): Gimplify type sizes and
+ TARGET_EXPR_INITIAL into a temporary sequence, then push clobbers
+ and asan unpoisioning, then append the temporary sequence and
+ finally the TARGET_EXPR_CLEANUP clobbers.
+
+2022-03-16 Roger Sayle <roger@nextmovesoftware.com>
+
+ * config/i386/sse.md: Delete corrupt character/typo.
+
+2022-03-16 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR target/94680
+ * config/i386/sse.md (sse2_movq128): New define_expand to
+ preserve previous named instruction.
+ (*sse2_movq128_<mode>): Renamed from sse2_movq128, and
+ generalized to VI8F_128 (both V2DI and V2DF).
+
+2022-03-16 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ PR tree-optimization/104941
+ * tree-object-size.cc (size_for_offset): Make useless conversion
+ check lighter and assign result of fold_convert to OFFSET.
+
+2022-03-16 H.J. Lu <hjl.tools@gmail.com>
+
+ PR target/104890
+ * config/i386/x86gprintrin.h: Also check _SOFT_FLOAT before
+ pushing target("general-regs-only").
+
+2022-03-16 Kito Cheng <kito.cheng@sifive.com>
+
+ * common/config/riscv/riscv-common.cc (riscv_ext_version_table):
+ Add version info for zk, zks and zkn.
+
+2022-03-16 LiaoShihua <shihua@iscas.ac.cn>
+
+ * common/config/riscv/riscv-common.cc
+ (riscv_combine_info): New.
+ (riscv_subset_list::handle_combine_ext): Combine back into zk to
+ maintain the canonical order in isa strings.
+ (riscv_subset_list::parse): Ditto.
+ * config/riscv/riscv-subset.h (handle_combine_ext): New.
+
+2022-03-16 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/102008
+ * passes.def: Move the added code sinking pass before the
+ preceeding phiopt pass.
+
+2022-03-16 Patrick Palka <ppalka@redhat.com>
+
+ PR c++/96780
+ * doc/invoke.texi (C++ Dialect Options): Document
+ -ffold-simple-inlines.
+
+2022-03-16 Siddhesh Poyarekar <siddhesh@gotplt.org>
+
+ PR tree-optimization/104942
+ * tree-object-size.cc (alloc_object_size): Remove STRIP_NOPS.
+
+2022-03-16 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/104910
+ * config/aarch64/aarch64.cc (aarch64_load_symref_appropriately): Copy
+ imm rtx.
+
+2022-03-16 Roger Sayle <roger@nextmovesoftware.com>
+ Richard Biener <rguenther@suse.de>
+
+ * gimple-match-head.cc (single_use): Implement inline using a
+ single loop.
+
+2022-03-16 Roger Sayle <roger@nextmovesoftware.com>
+
+ * match.pd (X CMP X -> true): Test tree_expr_maybe_nan_p
+ instead of HONOR_NANS.
+ (X LTGT X -> false): Enable if X is not tree_expr_maybe_nan_p, as
+ this can't trap/signal.
+
+2022-03-16 liuhongt <hongtao.liu@intel.com>
+
+ PR target/104946
+ * config/i386/i386-builtin.def (BDESC): Add
+ CODE_FOR_sse4_1_blendvpd for IX86_BUILTIN_BLENDVPD.
+ * config/i386/i386.cc (ix86_gimple_fold_builtin): Don't fold
+ __builtin_ia32_blendvpd w/o sse4.2
+
+2022-03-15 Peter Bergner <bergner@linux.ibm.com>
+
+ PR target/104923
+ * config/rs6000/predicates.md (mma_disassemble_output_operand): Restrict
+ acceptable MEM addresses.
+
+2022-03-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/91229
+ * config/riscv/riscv.cc (riscv_pass_aggregate_in_fpr_pair_p,
+ riscv_pass_aggregate_in_fpr_and_gpr_p): Pass OPT_Wpsabi instead of 0
+ to warning calls.
+
+2022-03-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/104890
+ * config/i386/i386.h (LIBGCC2_UNWIND_ATTRIBUTE): Use no-mmx,no-sse
+ instead of general-regs-only.
+
+2022-03-15 Roger Sayle <roger@nextmovesoftware.com>
+ Marc Glisse <marc.glisse@inria.fr>
+ Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/101895
+ * match.pd (vec_same_elem_p): Handle CONSTRUCTOR_EXPR def.
+ (plus (vec_perm (mult ...) ...) ...): New reordering simplification.
+
+2022-03-15 Jakub Jelinek <jakub@redhat.com>
+
+ PR rtl-optimization/104814
+ * ifcvt.cc (find_if_case_1, find_if_case_2): Punt if test_bb doesn't
+ end with onlyjump_p. Assume BB_END (test_bb) is always non-NULL.
+
+2022-03-15 Martin Sebor <msebor@redhat.com>
+
+ PR middle-end/104436
+ * gimple-ssa-warn-access.cc (pass_waccess::check_dangling_stores):
+ Check for warning suppression. Avoid by-value arguments transformed
+ into by-transparent-reference.
+
+2022-03-14 Roger Sayle <roger@nextmovesoftware.com>
+ Uroš Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (peephole2 xorl;movb -> movzbl): Disable
+ transformation when *zero_extend<mode>si2 is not available.
+
+2022-03-14 Xi Ruoyao <xry111@mengyan1223.wang>
+
+ * config/mips/mips.h (SUBTARGET_SHADOW_OFFSET): Define.
+ * config/mips/mips.cc (mips_option_override): Make
+ -fsanitize=address imply -fasynchronous-unwind-tables. This is
+ needed by libasan for stack backtrace on MIPS.
+ (mips_asan_shadow_offset): Return SUBTARGET_SHADOW_OFFSET.
+
+2022-03-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/104778
+ * lra.cc (lra_substitute_pseudo): For debug_p mode, simplify
+ SUBREG, ZERO_EXTEND, SIGN_EXTEND, FLOAT or UNSIGNED_FLOAT if recursive
+ call simplified the first operand into VOIDmode constant.
+
+2022-03-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR tree-optimization/102586
+ * doc/extend.texi (__builtin_clear_padding): Clearify that for C++
+ argument type should be pointer to trivially-copyable type unless it
+ is address of a variable or parameter.
+
+2022-03-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR target/99754
+ * config/i386/emmintrin.h (_mm_loadu_si32): Put loaded value into
+ first rather than last element of the vector, use __m32_u to do
+ a really unaligned load, use just 0 instead of (int)0.
+ (_mm_loadu_si16): Put loaded value into first rather than last
+ element of the vector, use __m16_u to do a really unaligned load,
+ use just 0 instead of (short)0.
+
+2022-03-14 Jakub Jelinek <jakub@redhat.com>
+
+ PR other/104899
+ * config/bfin/bfin.cc (bfin_handle_longcall_attribute): Fix a typo
+ in diagnostic message - cannott -> cannot. Use %< and %> around
+ names of attribute. Avoid too long line.
+ * range-op.cc (operator_logical_and::op1_range): Fix up a typo
+ in comment - cannott -> cannot. Use 2 spaces after . instead of one.
+
+2022-03-14 liuhongt <hongtao.liu@intel.com>
+
+ PR target/104666
+ * config/i386/i386-expand.cc
+ (ix86_check_builtin_isa_match): New func.
+ (ix86_expand_builtin): Move code to
+ ix86_check_builtin_isa_match and call it.
+ * config/i386/i386-protos.h
+ (ix86_check_builtin_isa_match): Declare.
+ * config/i386/i386.cc (ix86_gimple_fold_builtin): Don't fold
+ builtin into gimple when isa mismatches.
+
+2022-03-13 Tobias Burnus <tobias@codesourcery.com>
+
+ * doc/invoke.texi: Fix typos.
+ * doc/tm.texi.in: Remove duplicated word.
+ * doc/tm.texi: Regenerate.
+
+2022-03-12 Segher Boessenkool <segher@kernel.crashing.org>
+
+ PR target/104829
+ * config/rs6000/rs6000.cc (rs6000_machine_from_flags): Don't output
+ "ppc" and "ppc64" based on rs6000_cpu.
+
+2022-03-12 Thomas Schwinge <thomas@codesourcery.com>
+
+ PR middle-end/100280
+ PR middle-end/104892
+ * omp-oacc-kernels-decompose.cc (omp_oacc_kernels_decompose_1):
+ Remove special handling of 'GOMP_MAP_FORCE_TOFROM'.
+
+2022-03-12 Thomas Schwinge <thomas@codesourcery.com>
+
+ PR middle-end/100280
+ PR middle-end/104086
+ * omp-oacc-kernels-decompose.cc (omp_oacc_kernels_decompose_1):
+ Mark variables used in 'present' clauses as addressable.
+ * omp-low.cc (scan_sharing_clauses) <OMP_CLAUSE_MAP>: Gracefully
+ handle duplicate 'OMP_CLAUSE_MAP_DECL_MAKE_ADDRESSABLE'.
+
+2022-03-12 Thomas Schwinge <thomas@codesourcery.com>
+
+ PR other/65095
+ * tree-core.h (user_omp_claus_code_name): Declare function.
+ * tree.cc (user_omp_clause_code_name): New function.
+
+2022-03-12 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR middle-end/98420
+ * match.pd (minus @0 @0): Additional checks for -fno-rounding-math
+ (the defaut) or -fno-signed-zeros.
+
+2022-03-12 Michael Meissner <meissner@linux.ibm.com>
+
+ PR target/104868
+ * config/rs6000/vsx.md (extendditi2): Use a 'b' constraint when
+ moving from a GPR register to an Altivec register.
+
+2022-03-11 Roger Sayle <roger@nextmovesoftware.com>
+
+ PR tree-optimization/98335
+ * config/i386/i386.md (peephole2): Eliminate redundant insv.
+ Combine movl followed by movb. Transform xorl followed by
+ a suitable movb or movw into the equivalent movz[bw]l.
+
+2022-03-11 Roger Sayle <roger@nextmovesoftware.com>
+ Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/98335
+ * builtins.cc (get_object_alignment_2): Export.
+ * builtins.h (get_object_alignment_2): Likewise.
+ * tree-ssa-alias.cc (ao_ref_alignment): New.
+ * tree-ssa-alias.h (ao_ref_alignment): Declare.
+ * tree-ssa-dse.cc (compute_trims): Improve logic deciding whether
+ to align head/tail, writing more bytes but using fewer store insns.
+
+2022-03-11 Richard Biener <rguenther@suse.de>
+
+ PR tree-optimization/104880
+ * tree-ssa.cc (execute_update_address_taken): Remember if we
+ optimistically made something not addressable and
+ prepare to undo it.
+
+2022-03-11 Richard Biener <rguenther@suse.de>
+
+ PR target/104762
+ * config/i386/i386.cc (ix86_builtin_vectorization_cost): Do not
+ cost the first lane of SSE pieces as inserts for vec_construct.
+
2022-03-10 Roger Sayle <roger@nextmovesoftware.com>
PR c++/84964
git://gcc.gnu.org / gcc.git / blobdiff