gcc/testsuite/gcc.target/riscv/rvv/base/vlse_tum-3.c

   1 /* { dg-do compile } */
   2 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
   3
   4 #include "riscv_vector.h"
   5
   6 vint8mf8_t
   7 test___riscv_vlse8_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,int8_t* base,ptrdiff_t bstride,size_t vl)
   8 {
   9   return __riscv_vlse8_v_i8mf8_tum(mask,merge,base,bstride,32);
  10 }
  11
  12 vint8mf4_t
  13 test___riscv_vlse8_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,int8_t* base,ptrdiff_t bstride,size_t vl)
  14 {
  15   return __riscv_vlse8_v_i8mf4_tum(mask,merge,base,bstride,32);
  16 }
  17
  18 vint8mf2_t
  19 test___riscv_vlse8_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,int8_t* base,ptrdiff_t bstride,size_t vl)
  20 {
  21   return __riscv_vlse8_v_i8mf2_tum(mask,merge,base,bstride,32);
  22 }
  23
  24 vint8m1_t
  25 test___riscv_vlse8_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,int8_t* base,ptrdiff_t bstride,size_t vl)
  26 {
  27   return __riscv_vlse8_v_i8m1_tum(mask,merge,base,bstride,32);
  28 }
  29
  30 vint8m2_t
  31 test___riscv_vlse8_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,int8_t* base,ptrdiff_t bstride,size_t vl)
  32 {
  33   return __riscv_vlse8_v_i8m2_tum(mask,merge,base,bstride,32);
  34 }
  35
  36 vint8m4_t
  37 test___riscv_vlse8_v_i8m4_tum(vbool2_t mask,vint8m4_t merge,int8_t* base,ptrdiff_t bstride,size_t vl)
  38 {
  39   return __riscv_vlse8_v_i8m4_tum(mask,merge,base,bstride,32);
  40 }
  41
  42 vint8m8_t
  43 test___riscv_vlse8_v_i8m8_tum(vbool1_t mask,vint8m8_t merge,int8_t* base,ptrdiff_t bstride,size_t vl)
  44 {
  45   return __riscv_vlse8_v_i8m8_tum(mask,merge,base,bstride,32);
  46 }
  47
  48 vuint8mf8_t
  49 test___riscv_vlse8_v_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,uint8_t* base,ptrdiff_t bstride,size_t vl)
  50 {
  51   return __riscv_vlse8_v_u8mf8_tum(mask,merge,base,bstride,32);
  52 }
  53
  54 vuint8mf4_t
  55 test___riscv_vlse8_v_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,uint8_t* base,ptrdiff_t bstride,size_t vl)
  56 {
  57   return __riscv_vlse8_v_u8mf4_tum(mask,merge,base,bstride,32);
  58 }
  59
  60 vuint8mf2_t
  61 test___riscv_vlse8_v_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,uint8_t* base,ptrdiff_t bstride,size_t vl)
  62 {
  63   return __riscv_vlse8_v_u8mf2_tum(mask,merge,base,bstride,32);
  64 }
  65
  66 vuint8m1_t
  67 test___riscv_vlse8_v_u8m1_tum(vbool8_t mask,vuint8m1_t merge,uint8_t* base,ptrdiff_t bstride,size_t vl)
  68 {
  69   return __riscv_vlse8_v_u8m1_tum(mask,merge,base,bstride,32);
  70 }
  71
  72 vuint8m2_t
  73 test___riscv_vlse8_v_u8m2_tum(vbool4_t mask,vuint8m2_t merge,uint8_t* base,ptrdiff_t bstride,size_t vl)
  74 {
  75   return __riscv_vlse8_v_u8m2_tum(mask,merge,base,bstride,32);
  76 }
  77
  78 vuint8m4_t
  79 test___riscv_vlse8_v_u8m4_tum(vbool2_t mask,vuint8m4_t merge,uint8_t* base,ptrdiff_t bstride,size_t vl)
  80 {
  81   return __riscv_vlse8_v_u8m4_tum(mask,merge,base,bstride,32);
  82 }
  83
  84 vuint8m8_t
  85 test___riscv_vlse8_v_u8m8_tum(vbool1_t mask,vuint8m8_t merge,uint8_t* base,ptrdiff_t bstride,size_t vl)
  86 {
  87   return __riscv_vlse8_v_u8m8_tum(mask,merge,base,bstride,32);
  88 }
  89
  90 vint16mf4_t
  91 test___riscv_vlse16_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,int16_t* base,ptrdiff_t bstride,size_t vl)
  92 {
  93   return __riscv_vlse16_v_i16mf4_tum(mask,merge,base,bstride,32);
  94 }
  95
  96 vint16mf2_t
  97 test___riscv_vlse16_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,int16_t* base,ptrdiff_t bstride,size_t vl)
  98 {
  99   return __riscv_vlse16_v_i16mf2_tum(mask,merge,base,bstride,32);
 100 }
 101
 102 vint16m1_t
 103 test___riscv_vlse16_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,int16_t* base,ptrdiff_t bstride,size_t vl)
 104 {
 105   return __riscv_vlse16_v_i16m1_tum(mask,merge,base,bstride,32);
 106 }
 107
 108 vint16m2_t
 109 test___riscv_vlse16_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,int16_t* base,ptrdiff_t bstride,size_t vl)
 110 {
 111   return __riscv_vlse16_v_i16m2_tum(mask,merge,base,bstride,32);
 112 }
 113
 114 vint16m4_t
 115 test___riscv_vlse16_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,int16_t* base,ptrdiff_t bstride,size_t vl)
 116 {
 117   return __riscv_vlse16_v_i16m4_tum(mask,merge,base,bstride,32);
 118 }
 119
 120 vint16m8_t
 121 test___riscv_vlse16_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,int16_t* base,ptrdiff_t bstride,size_t vl)
 122 {
 123   return __riscv_vlse16_v_i16m8_tum(mask,merge,base,bstride,32);
 124 }
 125
 126 vuint16mf4_t
 127 test___riscv_vlse16_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,uint16_t* base,ptrdiff_t bstride,size_t vl)
 128 {
 129   return __riscv_vlse16_v_u16mf4_tum(mask,merge,base,bstride,32);
 130 }
 131
 132 vuint16mf2_t
 133 test___riscv_vlse16_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,uint16_t* base,ptrdiff_t bstride,size_t vl)
 134 {
 135   return __riscv_vlse16_v_u16mf2_tum(mask,merge,base,bstride,32);
 136 }
 137
 138 vuint16m1_t
 139 test___riscv_vlse16_v_u16m1_tum(vbool16_t mask,vuint16m1_t merge,uint16_t* base,ptrdiff_t bstride,size_t vl)
 140 {
 141   return __riscv_vlse16_v_u16m1_tum(mask,merge,base,bstride,32);
 142 }
 143
 144 vuint16m2_t
 145 test___riscv_vlse16_v_u16m2_tum(vbool8_t mask,vuint16m2_t merge,uint16_t* base,ptrdiff_t bstride,size_t vl)
 146 {
 147   return __riscv_vlse16_v_u16m2_tum(mask,merge,base,bstride,32);
 148 }
 149
 150 vuint16m4_t
 151 test___riscv_vlse16_v_u16m4_tum(vbool4_t mask,vuint16m4_t merge,uint16_t* base,ptrdiff_t bstride,size_t vl)
 152 {
 153   return __riscv_vlse16_v_u16m4_tum(mask,merge,base,bstride,32);
 154 }
 155
 156 vuint16m8_t
 157 test___riscv_vlse16_v_u16m8_tum(vbool2_t mask,vuint16m8_t merge,uint16_t* base,ptrdiff_t bstride,size_t vl)
 158 {
 159   return __riscv_vlse16_v_u16m8_tum(mask,merge,base,bstride,32);
 160 }
 161
 162 vint32mf2_t
 163 test___riscv_vlse32_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,int32_t* base,ptrdiff_t bstride,size_t vl)
 164 {
 165   return __riscv_vlse32_v_i32mf2_tum(mask,merge,base,bstride,32);
 166 }
 167
 168 vint32m1_t
 169 test___riscv_vlse32_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,int32_t* base,ptrdiff_t bstride,size_t vl)
 170 {
 171   return __riscv_vlse32_v_i32m1_tum(mask,merge,base,bstride,32);
 172 }
 173
 174 vint32m2_t
 175 test___riscv_vlse32_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,int32_t* base,ptrdiff_t bstride,size_t vl)
 176 {
 177   return __riscv_vlse32_v_i32m2_tum(mask,merge,base,bstride,32);
 178 }
 179
 180 vint32m4_t
 181 test___riscv_vlse32_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,int32_t* base,ptrdiff_t bstride,size_t vl)
 182 {
 183   return __riscv_vlse32_v_i32m4_tum(mask,merge,base,bstride,32);
 184 }
 185
 186 vint32m8_t
 187 test___riscv_vlse32_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,int32_t* base,ptrdiff_t bstride,size_t vl)
 188 {
 189   return __riscv_vlse32_v_i32m8_tum(mask,merge,base,bstride,32);
 190 }
 191
 192 vuint32mf2_t
 193 test___riscv_vlse32_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,uint32_t* base,ptrdiff_t bstride,size_t vl)
 194 {
 195   return __riscv_vlse32_v_u32mf2_tum(mask,merge,base,bstride,32);
 196 }
 197
 198 vuint32m1_t
 199 test___riscv_vlse32_v_u32m1_tum(vbool32_t mask,vuint32m1_t merge,uint32_t* base,ptrdiff_t bstride,size_t vl)
 200 {
 201   return __riscv_vlse32_v_u32m1_tum(mask,merge,base,bstride,32);
 202 }
 203
 204 vuint32m2_t
 205 test___riscv_vlse32_v_u32m2_tum(vbool16_t mask,vuint32m2_t merge,uint32_t* base,ptrdiff_t bstride,size_t vl)
 206 {
 207   return __riscv_vlse32_v_u32m2_tum(mask,merge,base,bstride,32);
 208 }
 209
 210 vuint32m4_t
 211 test___riscv_vlse32_v_u32m4_tum(vbool8_t mask,vuint32m4_t merge,uint32_t* base,ptrdiff_t bstride,size_t vl)
 212 {
 213   return __riscv_vlse32_v_u32m4_tum(mask,merge,base,bstride,32);
 214 }
 215
 216 vuint32m8_t
 217 test___riscv_vlse32_v_u32m8_tum(vbool4_t mask,vuint32m8_t merge,uint32_t* base,ptrdiff_t bstride,size_t vl)
 218 {
 219   return __riscv_vlse32_v_u32m8_tum(mask,merge,base,bstride,32);
 220 }
 221
 222 vfloat32mf2_t
 223 test___riscv_vlse32_v_f32mf2_tum(vbool64_t mask,vfloat32mf2_t merge,float* base,ptrdiff_t bstride,size_t vl)
 224 {
 225   return __riscv_vlse32_v_f32mf2_tum(mask,merge,base,bstride,32);
 226 }
 227
 228 vfloat32m1_t
 229 test___riscv_vlse32_v_f32m1_tum(vbool32_t mask,vfloat32m1_t merge,float* base,ptrdiff_t bstride,size_t vl)
 230 {
 231   return __riscv_vlse32_v_f32m1_tum(mask,merge,base,bstride,32);
 232 }
 233
 234 vfloat32m2_t
 235 test___riscv_vlse32_v_f32m2_tum(vbool16_t mask,vfloat32m2_t merge,float* base,ptrdiff_t bstride,size_t vl)
 236 {
 237   return __riscv_vlse32_v_f32m2_tum(mask,merge,base,bstride,32);
 238 }
 239
 240 vfloat32m4_t
 241 test___riscv_vlse32_v_f32m4_tum(vbool8_t mask,vfloat32m4_t merge,float* base,ptrdiff_t bstride,size_t vl)
 242 {
 243   return __riscv_vlse32_v_f32m4_tum(mask,merge,base,bstride,32);
 244 }
 245
 246 vfloat32m8_t
 247 test___riscv_vlse32_v_f32m8_tum(vbool4_t mask,vfloat32m8_t merge,float* base,ptrdiff_t bstride,size_t vl)
 248 {
 249   return __riscv_vlse32_v_f32m8_tum(mask,merge,base,bstride,32);
 250 }
 251
 252 vint64m1_t
 253 test___riscv_vlse64_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,int64_t* base,ptrdiff_t bstride,size_t vl)
 254 {
 255   return __riscv_vlse64_v_i64m1_tum(mask,merge,base,bstride,32);
 256 }
 257
 258 vint64m2_t
 259 test___riscv_vlse64_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,int64_t* base,ptrdiff_t bstride,size_t vl)
 260 {
 261   return __riscv_vlse64_v_i64m2_tum(mask,merge,base,bstride,32);
 262 }
 263
 264 vint64m4_t
 265 test___riscv_vlse64_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,int64_t* base,ptrdiff_t bstride,size_t vl)
 266 {
 267   return __riscv_vlse64_v_i64m4_tum(mask,merge,base,bstride,32);
 268 }
 269
 270 vint64m8_t
 271 test___riscv_vlse64_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,int64_t* base,ptrdiff_t bstride,size_t vl)
 272 {
 273   return __riscv_vlse64_v_i64m8_tum(mask,merge,base,bstride,32);
 274 }
 275
 276 vuint64m1_t
 277 test___riscv_vlse64_v_u64m1_tum(vbool64_t mask,vuint64m1_t merge,uint64_t* base,ptrdiff_t bstride,size_t vl)
 278 {
 279   return __riscv_vlse64_v_u64m1_tum(mask,merge,base,bstride,32);
 280 }
 281
 282 vuint64m2_t
 283 test___riscv_vlse64_v_u64m2_tum(vbool32_t mask,vuint64m2_t merge,uint64_t* base,ptrdiff_t bstride,size_t vl)
 284 {
 285   return __riscv_vlse64_v_u64m2_tum(mask,merge,base,bstride,32);
 286 }
 287
 288 vuint64m4_t
 289 test___riscv_vlse64_v_u64m4_tum(vbool16_t mask,vuint64m4_t merge,uint64_t* base,ptrdiff_t bstride,size_t vl)
 290 {
 291   return __riscv_vlse64_v_u64m4_tum(mask,merge,base,bstride,32);
 292 }
 293
 294 vuint64m8_t
 295 test___riscv_vlse64_v_u64m8_tum(vbool8_t mask,vuint64m8_t merge,uint64_t* base,ptrdiff_t bstride,size_t vl)
 296 {
 297   return __riscv_vlse64_v_u64m8_tum(mask,merge,base,bstride,32);
 298 }
 299
 300 vfloat64m1_t
 301 test___riscv_vlse64_v_f64m1_tum(vbool64_t mask,vfloat64m1_t merge,double* base,ptrdiff_t bstride,size_t vl)
 302 {
 303   return __riscv_vlse64_v_f64m1_tum(mask,merge,base,bstride,32);
 304 }
 305
 306 vfloat64m2_t
 307 test___riscv_vlse64_v_f64m2_tum(vbool32_t mask,vfloat64m2_t merge,double* base,ptrdiff_t bstride,size_t vl)
 308 {
 309   return __riscv_vlse64_v_f64m2_tum(mask,merge,base,bstride,32);
 310 }
 311
 312 vfloat64m4_t
 313 test___riscv_vlse64_v_f64m4_tum(vbool16_t mask,vfloat64m4_t merge,double* base,ptrdiff_t bstride,size_t vl)
 314 {
 315   return __riscv_vlse64_v_f64m4_tum(mask,merge,base,bstride,32);
 316 }
 317
 318 vfloat64m8_t
 319 test___riscv_vlse64_v_f64m8_tum(vbool8_t mask,vfloat64m8_t merge,double* base,ptrdiff_t bstride,size_t vl)
 320 {
 321   return __riscv_vlse64_v_f64m8_tum(mask,merge,base,bstride,32);
 322 }
 323
 324 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 325 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 326 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 327 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 328 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 329 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 330 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vlse8\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 331 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vlse16\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 332 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vlse16\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 333 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vlse16\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 334 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vlse16\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 335 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vlse16\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 336 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vlse16\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 2 } } */
 337 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 3 } } */
 338 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 3 } } */
 339 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 3 } } */
 340 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 3 } } */
 341 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vlse32\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 3 } } */
 342 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 3 } } */
 343 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 3 } } */
 344 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 3 } } */
 345 /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),[a-x0-9]+,\s*v0.t} 3 } } */