gcc/testsuite/g++.target/riscv/rvv/base/vnsrl_vv_tumu-2.C

   1 /* { dg-do compile } */
   2 /* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
   3
   4 #include "riscv_vector.h"
   5
   6 vuint8mf8_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint16mf4_t op1,vuint8mf8_t shift,size_t vl)
   7 {
   8     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
   9 }
  10
  11
  12 vuint8mf4_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint16mf2_t op1,vuint8mf4_t shift,size_t vl)
  13 {
  14     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  15 }
  16
  17
  18 vuint8mf2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint16m1_t op1,vuint8mf2_t shift,size_t vl)
  19 {
  20     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  21 }
  22
  23
  24 vuint8m1_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint16m2_t op1,vuint8m1_t shift,size_t vl)
  25 {
  26     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  27 }
  28
  29
  30 vuint8m2_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint16m4_t op1,vuint8m2_t shift,size_t vl)
  31 {
  32     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  33 }
  34
  35
  36 vuint8m4_t test___riscv_vnsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint16m8_t op1,vuint8m4_t shift,size_t vl)
  37 {
  38     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  39 }
  40
  41
  42 vuint16mf4_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint32mf2_t op1,vuint16mf4_t shift,size_t vl)
  43 {
  44     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  45 }
  46
  47
  48 vuint16mf2_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint32m1_t op1,vuint16mf2_t shift,size_t vl)
  49 {
  50     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  51 }
  52
  53
  54 vuint16m1_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint32m2_t op1,vuint16m1_t shift,size_t vl)
  55 {
  56     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  57 }
  58
  59
  60 vuint16m2_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint32m4_t op1,vuint16m2_t shift,size_t vl)
  61 {
  62     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  63 }
  64
  65
  66 vuint16m4_t test___riscv_vnsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint32m8_t op1,vuint16m4_t shift,size_t vl)
  67 {
  68     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  69 }
  70
  71
  72 vuint32mf2_t test___riscv_vnsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint64m1_t op1,vuint32mf2_t shift,size_t vl)
  73 {
  74     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  75 }
  76
  77
  78 vuint32m1_t test___riscv_vnsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint64m2_t op1,vuint32m1_t shift,size_t vl)
  79 {
  80     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  81 }
  82
  83
  84 vuint32m2_t test___riscv_vnsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint64m4_t op1,vuint32m2_t shift,size_t vl)
  85 {
  86     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  87 }
  88
  89
  90 vuint32m4_t test___riscv_vnsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint64m8_t op1,vuint32m4_t shift,size_t vl)
  91 {
  92     return __riscv_vnsrl_tumu(mask,merge,op1,shift,31);
  93 }
  94
  95
  96
  97 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
  98 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
  99 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 100 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 101 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 102 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 103 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 104 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 105 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 106 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 107 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 108 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 109 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 110 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
 111 /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnsrl\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */