1 /* Instruction scheduling pass.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 Enhanced by, and currently maintained by, Jim Wilson (wilson@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Instruction scheduling pass.
24 This pass implements list scheduling within basic blocks. It is
25 run after flow analysis, but before register allocation. The
26 scheduler works as follows:
28 We compute insn priorities based on data dependencies. Flow
29 analysis only creates a fraction of the data-dependencies we must
30 observe: namely, only those dependencies which the combiner can be
31 expected to use. For this pass, we must therefore create the
32 remaining dependencies we need to observe: register dependencies,
33 memory dependencies, dependencies to keep function calls in order,
34 and the dependence between a conditional branch and the setting of
35 condition codes are all dealt with here.
37 The scheduler first traverses the data flow graph, starting with
38 the last instruction, and proceeding to the first, assigning
39 values to insn_priority as it goes. This sorts the instructions
40 topologically by data dependence.
42 Once priorities have been established, we order the insns using
43 list scheduling. This works as follows: starting with a list of
44 all the ready insns, and sorted according to priority number, we
45 schedule the insn from the end of the list by placing its
46 predecessors in the list according to their priority order. We
47 consider this insn scheduled by setting the pointer to the "end" of
48 the list to point to the previous insn. When an insn has no
49 predecessors, we either queue it until sufficient time has elapsed
50 or add it to the ready list. As the instructions are scheduled or
51 when stalls are introduced, the queue advances and dumps insns into
52 the ready list. When all insns down to the lowest priority have
53 been scheduled, the critical path of the basic block has been made
54 as short as possible. The remaining insns are then scheduled in
57 Function unit conflicts are resolved during reverse list scheduling
58 by tracking the time when each insn is committed to the schedule
59 and from that, the time the function units it uses must be free.
60 As insns on the ready list are considered for scheduling, those
61 that would result in a blockage of the already committed insns are
62 queued until no blockage will result. Among the remaining insns on
63 the ready list to be considered, the first one with the largest
64 potential for causing a subsequent blockage is chosen.
66 The following list shows the order in which we want to break ties
67 among insns in the ready list:
69 1. choose insn with lowest conflict cost, ties broken by
70 2. choose insn with the longest path to end of bb, ties broken by
71 3. choose insn that kills the most registers, ties broken by
72 4. choose insn that conflicts with the most ready insns, or finally
73 5. choose insn with lowest UID.
75 Memory references complicate matters. Only if we can be certain
76 that memory references are not part of the data dependency graph
77 (via true, anti, or output dependence), can we move operations past
78 memory references. To first approximation, reads can be done
79 independently, while writes introduce dependencies. Better
80 approximations will yield fewer dependencies.
82 Dependencies set up by memory references are treated in exactly the
83 same way as other dependencies, by using LOG_LINKS.
85 Having optimized the critical path, we may have also unduly
86 extended the lifetimes of some registers. If an operation requires
87 that constants be loaded into registers, it is certainly desirable
88 to load those constants as early as necessary, but no earlier.
89 I.e., it will not do to load up a bunch of registers at the
90 beginning of a basic block only to use them at the end, if they
91 could be loaded later, since this may result in excessive register
94 Note that since branches are never in basic blocks, but only end
95 basic blocks, this pass will not do any branch scheduling. But
96 that is ok, since we can use GNU's delayed branch scheduling
97 pass to take care of this case.
99 Also note that no further optimizations based on algebraic identities
100 are performed, so this pass would be a good one to perform instruction
101 splitting, such as breaking up a multiply instruction into shifts
102 and adds where that is profitable.
104 Given the memory aliasing analysis that this pass should perform,
105 it should be possible to remove redundant stores to memory, and to
106 load values from registers instead of hitting memory.
108 This pass must update information that subsequent passes expect to be
109 correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
110 reg_n_calls_crossed, and reg_live_length. Also, basic_block_head,
113 The information in the line number notes is carefully retained by this
114 pass. All other NOTE insns are grouped in their same relative order at
115 the beginning of basic blocks that have been scheduled. */
120 #include "basic-block.h"
122 #include "hard-reg-set.h"
124 #include "insn-config.h"
125 #include "insn-attr.h"
127 #ifdef INSN_SCHEDULING
128 /* Arrays set up by scheduling for the same respective purposes as
129 similar-named arrays set up by flow analysis. We work with these
130 arrays during the scheduling pass so we can compare values against
133 Values of these arrays are copied at the end of this pass into the
134 arrays set up by flow analysis. */
135 static short *sched_reg_n_deaths
;
136 static int *sched_reg_n_calls_crossed
;
137 static int *sched_reg_live_length
;
139 /* Element N is the next insn that sets (hard or pseudo) register
140 N within the current basic block; or zero, if there is no
141 such insn. Needed for new registers which may be introduced
142 by splitting insns. */
143 static rtx
*reg_last_uses
;
144 static rtx
*reg_last_sets
;
146 /* Vector indexed by INSN_UID giving the original ordering of the insns. */
147 static int *insn_luid
;
148 #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)])
150 /* Vector indexed by INSN_UID giving each instruction a priority. */
151 static int *insn_priority
;
152 #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
154 static short *insn_costs
;
155 #define INSN_COST(INSN) insn_costs[INSN_UID (INSN)]
157 /* Vector indexed by INSN_UID giving an encoding of the function units
159 static short *insn_units
;
160 #define INSN_UNIT(INSN) insn_units[INSN_UID (INSN)]
162 /* Vector indexed by INSN_UID giving an encoding of the blockage range
163 function. The unit and the range are encoded. */
164 static unsigned int *insn_blockage
;
165 #define INSN_BLOCKAGE(INSN) insn_blockage[INSN_UID (INSN)]
167 #define BLOCKAGE_MASK ((1 << BLOCKAGE_BITS) - 1)
168 #define ENCODE_BLOCKAGE(U,R) \
169 ((((U) << UNIT_BITS) << BLOCKAGE_BITS \
170 | MIN_BLOCKAGE_COST (R)) << BLOCKAGE_BITS \
171 | MAX_BLOCKAGE_COST (R))
172 #define UNIT_BLOCKED(B) ((B) >> (2 * BLOCKAGE_BITS))
173 #define BLOCKAGE_RANGE(B) \
174 (((((B) >> BLOCKAGE_BITS) & BLOCKAGE_MASK) << (HOST_BITS_PER_INT / 2)) \
175 | (B) & BLOCKAGE_MASK)
177 /* Encodings of the `<name>_unit_blockage_range' function. */
178 #define MIN_BLOCKAGE_COST(R) ((R) >> (HOST_BITS_PER_INT / 2))
179 #define MAX_BLOCKAGE_COST(R) ((R) & ((1 << (HOST_BITS_PER_INT / 2)) - 1))
181 #define DONE_PRIORITY -1
182 #define MAX_PRIORITY 0x7fffffff
183 #define TAIL_PRIORITY 0x7ffffffe
184 #define LAUNCH_PRIORITY 0x7f000001
185 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
186 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
188 /* Vector indexed by INSN_UID giving number of insns referring to this insn. */
189 static int *insn_ref_count
;
190 #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)])
192 /* Vector indexed by INSN_UID giving line-number note in effect for each
193 insn. For line-number notes, this indicates whether the note may be
195 static rtx
*line_note
;
196 #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)])
198 /* Vector indexed by basic block number giving the starting line-number
199 for each basic block. */
200 static rtx
*line_note_head
;
202 /* List of important notes we must keep around. This is a pointer to the
203 last element in the list. */
204 static rtx note_list
;
206 /* Regsets telling whether a given register is live or dead before the last
207 scheduled insn. Must scan the instructions once before scheduling to
208 determine what registers are live or dead at the end of the block. */
209 static regset bb_dead_regs
;
210 static regset bb_live_regs
;
212 /* Regset telling whether a given register is live after the insn currently
213 being scheduled. Before processing an insn, this is equal to bb_live_regs
214 above. This is used so that we can find registers that are newly born/dead
215 after processing an insn. */
216 static regset old_live_regs
;
218 /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns
219 during the initial scan and reused later. If there are not exactly as
220 many REG_DEAD notes in the post scheduled code as there were in the
221 prescheduled code then we trigger an abort because this indicates a bug. */
222 static rtx dead_notes
;
226 /* An instruction is ready to be scheduled when all insns following it
227 have already been scheduled. It is important to ensure that all
228 insns which use its result will not be executed until its result
229 has been computed. An insn is maintained in one of four structures:
231 (P) the "Pending" set of insns which cannot be scheduled until
232 their dependencies have been satisfied.
233 (Q) the "Queued" set of insns that can be scheduled when sufficient
235 (R) the "Ready" list of unscheduled, uncommitted insns.
236 (S) the "Scheduled" list of insns.
238 Initially, all insns are either "Pending" or "Ready" depending on
239 whether their dependencies are satisfied.
241 Insns move from the "Ready" list to the "Scheduled" list as they
242 are committed to the schedule. As this occurs, the insns in the
243 "Pending" list have their dependencies satisfied and move to either
244 the "Ready" list or the "Queued" set depending on whether
245 sufficient time has passed to make them ready. As time passes,
246 insns move from the "Queued" set to the "Ready" list. Insns may
247 move from the "Ready" list to the "Queued" set if they are blocked
248 due to a function unit conflict.
250 The "Pending" list (P) are the insns in the LOG_LINKS of the unscheduled
251 insns, i.e., those that are ready, queued, and pending.
252 The "Queued" set (Q) is implemented by the variable `insn_queue'.
253 The "Ready" list (R) is implemented by the variables `ready' and
255 The "Scheduled" list (S) is the new insn chain built by this pass.
257 The transition (R->S) is implemented in the scheduling loop in
258 `schedule_block' when the best insn to schedule is chosen.
259 The transition (R->Q) is implemented in `schedule_select' when an
260 insn is found to to have a function unit conflict with the already
262 The transitions (P->R and P->Q) are implemented in `schedule_insn' as
263 insns move from the ready list to the scheduled list.
264 The transition (Q->R) is implemented at the top of the scheduling
265 loop in `schedule_block' as time passes or stalls are introduced. */
267 /* Implement a circular buffer to delay instructions until sufficient
268 time has passed. INSN_QUEUE_SIZE is a power of two larger than
269 MAX_BLOCKAGE and MAX_READY_COST computed by genattr.c. This is the
270 longest time an isnsn may be queued. */
271 static rtx insn_queue
[INSN_QUEUE_SIZE
];
272 static int q_ptr
= 0;
273 static int q_size
= 0;
274 #define NEXT_Q(X) (((X)+1) & (INSN_QUEUE_SIZE-1))
275 #define NEXT_Q_AFTER(X,C) (((X)+C) & (INSN_QUEUE_SIZE-1))
277 /* Vector indexed by INSN_UID giving the minimum clock tick at which
278 the insn becomes ready. This is used to note timing constraints for
279 insns in the pending list. */
280 static int *insn_tick
;
281 #define INSN_TICK(INSN) (insn_tick[INSN_UID (INSN)])
283 /* Forward declarations. */
284 static void sched_analyze_2 ();
285 static void schedule_block ();
287 /* Main entry point of this file. */
288 void schedule_insns ();
289 #endif /* INSN_SCHEDULING */
291 #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
293 /* Vector indexed by N giving the initial (unchanging) value known
294 for pseudo-register N. */
295 static rtx
*reg_known_value
;
297 /* Vector recording for each reg_known_value whether it is due to a
298 REG_EQUIV note. Future passes (viz., reload) may replace the
299 pseudo with the equivalent expression and so we account for the
300 dependences that would be introduced if that happens. */
301 /* ??? This is a problem only on the Convex. The REG_EQUIV notes created in
302 assign_parms mention the arg pointer, and there are explicit insns in the
303 RTL that modify the arg pointer. Thus we must ensure that such insns don't
304 get scheduled across each other because that would invalidate the REG_EQUIV
305 notes. One could argue that the REG_EQUIV notes are wrong, but solving
306 the problem in the scheduler will likely give better code, so we do it
308 static char *reg_known_equiv_p
;
310 /* Indicates number of valid entries in reg_known_value. */
311 static int reg_known_value_size
;
317 if (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
318 && REGNO (x
) <= reg_known_value_size
)
319 return reg_known_value
[REGNO (x
)];
320 else if (GET_CODE (x
) == PLUS
)
322 rtx x0
= canon_rtx (XEXP (x
, 0));
323 rtx x1
= canon_rtx (XEXP (x
, 1));
325 if (x0
!= XEXP (x
, 0) || x1
!= XEXP (x
, 1))
327 /* We can tolerate LO_SUMs being offset here; these
328 rtl are used for nothing other than comparisons. */
329 if (GET_CODE (x0
) == CONST_INT
)
330 return plus_constant_for_output (x1
, INTVAL (x0
));
331 else if (GET_CODE (x1
) == CONST_INT
)
332 return plus_constant_for_output (x0
, INTVAL (x1
));
333 return gen_rtx (PLUS
, GET_MODE (x
), x0
, x1
);
339 /* Set up all info needed to perform alias analysis on memory references. */
342 init_alias_analysis ()
344 int maxreg
= max_reg_num ();
349 reg_known_value_size
= maxreg
;
352 = (rtx
*) oballoc ((maxreg
-FIRST_PSEUDO_REGISTER
) * sizeof (rtx
))
353 - FIRST_PSEUDO_REGISTER
;
354 bzero (reg_known_value
+FIRST_PSEUDO_REGISTER
,
355 (maxreg
-FIRST_PSEUDO_REGISTER
) * sizeof (rtx
));
358 = (char *) oballoc ((maxreg
-FIRST_PSEUDO_REGISTER
) * sizeof (char))
359 - FIRST_PSEUDO_REGISTER
;
360 bzero (reg_known_equiv_p
+FIRST_PSEUDO_REGISTER
,
361 (maxreg
-FIRST_PSEUDO_REGISTER
) * sizeof (char));
363 /* Fill in the entries with known constant values. */
364 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
365 if ((set
= single_set (insn
)) != 0
366 && GET_CODE (SET_DEST (set
)) == REG
367 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
368 && (((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
369 && reg_n_sets
[REGNO (SET_DEST (set
))] == 1)
370 || (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != 0)
371 && GET_CODE (XEXP (note
, 0)) != EXPR_LIST
)
373 int regno
= REGNO (SET_DEST (set
));
374 reg_known_value
[regno
] = XEXP (note
, 0);
375 reg_known_equiv_p
[regno
] = REG_NOTE_KIND (note
) == REG_EQUIV
;
378 /* Fill in the remaining entries. */
379 while (--maxreg
>= FIRST_PSEUDO_REGISTER
)
380 if (reg_known_value
[maxreg
] == 0)
381 reg_known_value
[maxreg
] = regno_reg_rtx
[maxreg
];
384 /* Return 1 if X and Y are identical-looking rtx's.
386 We use the data in reg_known_value above to see if two registers with
387 different numbers are, in fact, equivalent. */
390 rtx_equal_for_memref_p (x
, y
)
395 register enum rtx_code code
;
398 if (x
== 0 && y
== 0)
400 if (x
== 0 || y
== 0)
409 /* Rtx's of different codes cannot be equal. */
410 if (code
!= GET_CODE (y
))
413 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
414 (REG:SI x) and (REG:HI x) are NOT equivalent. */
416 if (GET_MODE (x
) != GET_MODE (y
))
419 /* REG, LABEL_REF, and SYMBOL_REF can be compared nonrecursively. */
422 return REGNO (x
) == REGNO (y
);
423 if (code
== LABEL_REF
)
424 return XEXP (x
, 0) == XEXP (y
, 0);
425 if (code
== SYMBOL_REF
)
426 return XSTR (x
, 0) == XSTR (y
, 0);
428 /* Compare the elements. If any pair of corresponding elements
429 fail to match, return 0 for the whole things. */
431 fmt
= GET_RTX_FORMAT (code
);
432 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
437 if (XWINT (x
, i
) != XWINT (y
, i
))
443 if (XINT (x
, i
) != XINT (y
, i
))
449 /* Two vectors must have the same length. */
450 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
453 /* And the corresponding elements must match. */
454 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
455 if (rtx_equal_for_memref_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
)) == 0)
460 if (rtx_equal_for_memref_p (XEXP (x
, i
), XEXP (y
, i
)) == 0)
466 if (strcmp (XSTR (x
, i
), XSTR (y
, i
)))
471 /* These are just backpointers, so they don't matter. */
477 /* It is believed that rtx's at this level will never
478 contain anything but integers and other rtx's,
479 except for within LABEL_REFs and SYMBOL_REFs. */
487 /* Given an rtx X, find a SYMBOL_REF or LABEL_REF within
488 X and return it, or return 0 if none found. */
491 find_symbolic_term (x
)
495 register enum rtx_code code
;
499 if (code
== SYMBOL_REF
|| code
== LABEL_REF
)
501 if (GET_RTX_CLASS (code
) == 'o')
504 fmt
= GET_RTX_FORMAT (code
);
505 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
511 t
= find_symbolic_term (XEXP (x
, i
));
515 else if (fmt
[i
] == 'E')
521 /* Return nonzero if X and Y (memory addresses) could reference the
522 same location in memory. C is an offset accumulator. When
523 C is nonzero, we are testing aliases between X and Y + C.
524 XSIZE is the size in bytes of the X reference,
525 similarly YSIZE is the size in bytes for Y.
527 If XSIZE or YSIZE is zero, we do not know the amount of memory being
528 referenced (the reference was BLKmode), so make the most pessimistic
531 We recognize the following cases of non-conflicting memory:
533 (1) addresses involving the frame pointer cannot conflict
534 with addresses involving static variables.
535 (2) static variables with different addresses cannot conflict.
537 Nice to notice that varying addresses cannot conflict with fp if no
538 local variables had their addresses taken, but that's too hard now. */
540 /* ??? In Fortran, references to a array parameter can never conflict with
541 another array parameter. */
544 memrefs_conflict_p (xsize
, x
, ysize
, y
, c
)
549 if (GET_CODE (x
) == HIGH
)
551 else if (GET_CODE (x
) == LO_SUM
)
555 if (GET_CODE (y
) == HIGH
)
557 else if (GET_CODE (y
) == LO_SUM
)
562 if (rtx_equal_for_memref_p (x
, y
))
563 return (xsize
== 0 || ysize
== 0 ||
564 (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0));
566 if (y
== frame_pointer_rtx
|| y
== stack_pointer_rtx
)
570 y
= x
; ysize
= xsize
;
571 x
= t
; xsize
= tsize
;
574 if (x
== frame_pointer_rtx
|| x
== stack_pointer_rtx
)
581 if (GET_CODE (y
) == PLUS
582 && canon_rtx (XEXP (y
, 0)) == x
583 && (y1
= canon_rtx (XEXP (y
, 1)))
584 && GET_CODE (y1
) == CONST_INT
)
587 return (xsize
== 0 || ysize
== 0
588 || (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0));
591 if (GET_CODE (y
) == PLUS
592 && (y1
= canon_rtx (XEXP (y
, 0)))
599 if (GET_CODE (x
) == PLUS
)
601 /* The fact that X is canonicalized means that this
602 PLUS rtx is canonicalized. */
603 rtx x0
= XEXP (x
, 0);
604 rtx x1
= XEXP (x
, 1);
606 if (GET_CODE (y
) == PLUS
)
608 /* The fact that Y is canonicalized means that this
609 PLUS rtx is canonicalized. */
610 rtx y0
= XEXP (y
, 0);
611 rtx y1
= XEXP (y
, 1);
613 if (rtx_equal_for_memref_p (x1
, y1
))
614 return memrefs_conflict_p (xsize
, x0
, ysize
, y0
, c
);
615 if (rtx_equal_for_memref_p (x0
, y0
))
616 return memrefs_conflict_p (xsize
, x1
, ysize
, y1
, c
);
617 if (GET_CODE (x1
) == CONST_INT
)
618 if (GET_CODE (y1
) == CONST_INT
)
619 return memrefs_conflict_p (xsize
, x0
, ysize
, y0
,
620 c
- INTVAL (x1
) + INTVAL (y1
));
622 return memrefs_conflict_p (xsize
, x0
, ysize
, y
, c
- INTVAL (x1
));
623 else if (GET_CODE (y1
) == CONST_INT
)
624 return memrefs_conflict_p (xsize
, x
, ysize
, y0
, c
+ INTVAL (y1
));
626 /* Handle case where we cannot understand iteration operators,
627 but we notice that the base addresses are distinct objects. */
628 x
= find_symbolic_term (x
);
631 y
= find_symbolic_term (y
);
634 return rtx_equal_for_memref_p (x
, y
);
636 else if (GET_CODE (x1
) == CONST_INT
)
637 return memrefs_conflict_p (xsize
, x0
, ysize
, y
, c
- INTVAL (x1
));
639 else if (GET_CODE (y
) == PLUS
)
641 /* The fact that Y is canonicalized means that this
642 PLUS rtx is canonicalized. */
643 rtx y0
= XEXP (y
, 0);
644 rtx y1
= XEXP (y
, 1);
646 if (GET_CODE (y1
) == CONST_INT
)
647 return memrefs_conflict_p (xsize
, x
, ysize
, y0
, c
+ INTVAL (y1
));
652 if (GET_CODE (x
) == GET_CODE (y
))
653 switch (GET_CODE (x
))
657 /* Handle cases where we expect the second operands to be the
658 same, and check only whether the first operand would conflict
661 rtx x1
= canon_rtx (XEXP (x
, 1));
662 rtx y1
= canon_rtx (XEXP (y
, 1));
663 if (! rtx_equal_for_memref_p (x1
, y1
))
665 x0
= canon_rtx (XEXP (x
, 0));
666 y0
= canon_rtx (XEXP (y
, 0));
667 if (rtx_equal_for_memref_p (x0
, y0
))
668 return (xsize
== 0 || ysize
== 0
669 || (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0));
671 /* Can't properly adjust our sizes. */
672 if (GET_CODE (x1
) != CONST_INT
)
674 xsize
/= INTVAL (x1
);
675 ysize
/= INTVAL (x1
);
677 return memrefs_conflict_p (xsize
, x0
, ysize
, y0
, c
);
683 if (GET_CODE (x
) == CONST_INT
&& GET_CODE (y
) == CONST_INT
)
685 c
+= (INTVAL (y
) - INTVAL (x
));
686 return (xsize
== 0 || ysize
== 0
687 || (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0));
690 if (GET_CODE (x
) == CONST
)
692 if (GET_CODE (y
) == CONST
)
693 return memrefs_conflict_p (xsize
, canon_rtx (XEXP (x
, 0)),
694 ysize
, canon_rtx (XEXP (y
, 0)), c
);
696 return memrefs_conflict_p (xsize
, canon_rtx (XEXP (x
, 0)),
699 if (GET_CODE (y
) == CONST
)
700 return memrefs_conflict_p (xsize
, x
, ysize
,
701 canon_rtx (XEXP (y
, 0)), c
);
704 return (rtx_equal_for_memref_p (x
, y
)
705 && (xsize
== 0 || ysize
== 0
706 || (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0)));
713 /* Functions to compute memory dependencies.
715 Since we process the insns in execution order, we can build tables
716 to keep track of what registers are fixed (and not aliased), what registers
717 are varying in known ways, and what registers are varying in unknown
720 If both memory references are volatile, then there must always be a
721 dependence between the two references, since their order can not be
722 changed. A volatile and non-volatile reference can be interchanged
725 A MEM_IN_STRUCT reference at a non-QImode varying address can never
726 conflict with a non-MEM_IN_STRUCT reference at a fixed address. We must
727 allow QImode aliasing because the ANSI C standard allows character
728 pointers to alias anything. We are assuming that characters are
729 always QImode here. */
731 /* Read dependence: X is read after read in MEM takes place. There can
732 only be a dependence here if both reads are volatile. */
735 read_dependence (mem
, x
)
739 return MEM_VOLATILE_P (x
) && MEM_VOLATILE_P (mem
);
742 /* True dependence: X is read after store in MEM takes place. */
745 true_dependence (mem
, x
)
749 /* If X is an unchanging read, then it can't possibly conflict with any
750 non-unchanging store. It may conflict with an unchanging write though,
751 because there may be a single store to this address to initialize it.
752 Just fall through to the code below to resolve the case where we have
753 both an unchanging read and an unchanging write. This won't handle all
754 cases optimally, but the possible performance loss should be
756 if (RTX_UNCHANGING_P (x
) && ! RTX_UNCHANGING_P (mem
))
759 return ((MEM_VOLATILE_P (x
) && MEM_VOLATILE_P (mem
))
760 || (memrefs_conflict_p (SIZE_FOR_MODE (mem
), XEXP (mem
, 0),
761 SIZE_FOR_MODE (x
), XEXP (x
, 0), 0)
762 && ! (MEM_IN_STRUCT_P (mem
) && rtx_addr_varies_p (mem
)
763 && GET_MODE (mem
) != QImode
764 && ! MEM_IN_STRUCT_P (x
) && ! rtx_addr_varies_p (x
))
765 && ! (MEM_IN_STRUCT_P (x
) && rtx_addr_varies_p (x
)
766 && GET_MODE (x
) != QImode
767 && ! MEM_IN_STRUCT_P (mem
) && ! rtx_addr_varies_p (mem
))));
770 /* Anti dependence: X is written after read in MEM takes place. */
773 anti_dependence (mem
, x
)
777 /* If MEM is an unchanging read, then it can't possibly conflict with
778 the store to X, because there is at most one store to MEM, and it must
779 have occured somewhere before MEM. */
780 if (RTX_UNCHANGING_P (mem
))
783 return ((MEM_VOLATILE_P (x
) && MEM_VOLATILE_P (mem
))
784 || (memrefs_conflict_p (SIZE_FOR_MODE (mem
), XEXP (mem
, 0),
785 SIZE_FOR_MODE (x
), XEXP (x
, 0), 0)
786 && ! (MEM_IN_STRUCT_P (mem
) && rtx_addr_varies_p (mem
)
787 && GET_MODE (mem
) != QImode
788 && ! MEM_IN_STRUCT_P (x
) && ! rtx_addr_varies_p (x
))
789 && ! (MEM_IN_STRUCT_P (x
) && rtx_addr_varies_p (x
)
790 && GET_MODE (x
) != QImode
791 && ! MEM_IN_STRUCT_P (mem
) && ! rtx_addr_varies_p (mem
))));
794 /* Output dependence: X is written after store in MEM takes place. */
797 output_dependence (mem
, x
)
801 return ((MEM_VOLATILE_P (x
) && MEM_VOLATILE_P (mem
))
802 || (memrefs_conflict_p (SIZE_FOR_MODE (mem
), XEXP (mem
, 0),
803 SIZE_FOR_MODE (x
), XEXP (x
, 0), 0)
804 && ! (MEM_IN_STRUCT_P (mem
) && rtx_addr_varies_p (mem
)
805 && GET_MODE (mem
) != QImode
806 && ! MEM_IN_STRUCT_P (x
) && ! rtx_addr_varies_p (x
))
807 && ! (MEM_IN_STRUCT_P (x
) && rtx_addr_varies_p (x
)
808 && GET_MODE (x
) != QImode
809 && ! MEM_IN_STRUCT_P (mem
) && ! rtx_addr_varies_p (mem
))));
812 /* Helper functions for instruction scheduling. */
814 /* Add ELEM wrapped in an INSN_LIST with reg note kind DEP_TYPE to the
815 LOG_LINKS of INSN, if not already there. DEP_TYPE indicates the type
816 of dependence that this link represents. */
819 add_dependence (insn
, elem
, dep_type
)
822 enum reg_note dep_type
;
826 /* Don't depend an insn on itself. */
830 /* If elem is part of a sequence that must be scheduled together, then
831 make the dependence point to the last insn of the sequence.
832 When HAVE_cc0, it is possible for NOTEs to exist between users and
833 setters of the condition codes, so we must skip past notes here.
834 Otherwise, NOTEs are impossible here. */
836 next
= NEXT_INSN (elem
);
839 while (next
&& GET_CODE (next
) == NOTE
)
840 next
= NEXT_INSN (next
);
843 if (next
&& SCHED_GROUP_P (next
))
845 /* Notes will never intervene here though, so don't bother checking
847 while (NEXT_INSN (next
) && SCHED_GROUP_P (NEXT_INSN (next
)))
848 next
= NEXT_INSN (next
);
850 /* Again, don't depend an insn on itself. */
854 /* Make the dependence to NEXT, the last insn of the group, instead
855 of the original ELEM. */
859 /* Check that we don't already have this dependence. */
860 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
861 if (XEXP (link
, 0) == elem
)
863 /* If this is a more restrictive type of dependence than the existing
864 one, then change the existing dependence to this type. */
865 if ((int) dep_type
< (int) REG_NOTE_KIND (link
))
866 PUT_REG_NOTE_KIND (link
, dep_type
);
869 /* Might want to check one level of transitivity to save conses. */
871 link
= rtx_alloc (INSN_LIST
);
872 /* Insn dependency, not data dependency. */
873 PUT_REG_NOTE_KIND (link
, dep_type
);
874 XEXP (link
, 0) = elem
;
875 XEXP (link
, 1) = LOG_LINKS (insn
);
876 LOG_LINKS (insn
) = link
;
879 /* Remove ELEM wrapped in an INSN_LIST from the LOG_LINKS
880 of INSN. Abort if not found. */
882 remove_dependence (insn
, elem
)
889 for (prev
= 0, link
= LOG_LINKS (insn
); link
;
890 prev
= link
, link
= XEXP (link
, 1))
892 if (XEXP (link
, 0) == elem
)
895 XEXP (prev
, 1) = XEXP (link
, 1);
897 LOG_LINKS (insn
) = XEXP (link
, 1);
907 #ifndef INSN_SCHEDULING
908 void schedule_insns () {}
914 /* Computation of memory dependencies. */
916 /* The *_insns and *_mems are paired lists. Each pending memory operation
917 will have a pointer to the MEM rtx on one list and a pointer to the
918 containing insn on the other list in the same place in the list. */
920 /* We can't use add_dependence like the old code did, because a single insn
921 may have multiple memory accesses, and hence needs to be on the list
922 once for each memory access. Add_dependence won't let you add an insn
923 to a list more than once. */
925 /* An INSN_LIST containing all insns with pending read operations. */
926 static rtx pending_read_insns
;
928 /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
929 static rtx pending_read_mems
;
931 /* An INSN_LIST containing all insns with pending write operations. */
932 static rtx pending_write_insns
;
934 /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
935 static rtx pending_write_mems
;
937 /* Indicates the combined length of the two pending lists. We must prevent
938 these lists from ever growing too large since the number of dependencies
939 produced is at least O(N*N), and execution time is at least O(4*N*N), as
940 a function of the length of these pending lists. */
942 static int pending_lists_length
;
944 /* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */
946 static rtx unused_insn_list
;
948 /* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */
950 static rtx unused_expr_list
;
952 /* The last insn upon which all memory references must depend.
953 This is an insn which flushed the pending lists, creating a dependency
954 between it and all previously pending memory references. This creates
955 a barrier (or a checkpoint) which no memory reference is allowed to cross.
957 This includes all non constant CALL_INSNs. When we do interprocedural
958 alias analysis, this restriction can be relaxed.
959 This may also be an INSN that writes memory if the pending lists grow
962 static rtx last_pending_memory_flush
;
964 /* The last function call we have seen. All hard regs, and, of course,
965 the last function call, must depend on this. */
967 static rtx last_function_call
;
969 /* The LOG_LINKS field of this is a list of insns which use a pseudo register
970 that does not already cross a call. We create dependencies between each
971 of those insn and the next call insn, to ensure that they won't cross a call
972 after scheduling is done. */
974 static rtx sched_before_next_call
;
976 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
977 so that insns independent of the last scheduled insn will be preferred
978 over dependent instructions. */
980 static rtx last_scheduled_insn
;
982 /* Process an insn's memory dependencies. There are four kinds of
985 (0) read dependence: read follows read
986 (1) true dependence: read follows write
987 (2) anti dependence: write follows read
988 (3) output dependence: write follows write
990 We are careful to build only dependencies which actually exist, and
991 use transitivity to avoid building too many links. */
993 /* Return the INSN_LIST containing INSN in LIST, or NULL
994 if LIST does not contain INSN. */
997 find_insn_list (insn
, list
)
1003 if (XEXP (list
, 0) == insn
)
1005 list
= XEXP (list
, 1);
1010 /* Compute the function units used by INSN. This caches the value
1011 returned by function_units_used. A function unit is encoded as the
1012 unit number if the value is non-negative and the compliment of a
1013 mask if the value is negative. A function unit index is the
1014 non-negative encoding. */
1020 register int unit
= INSN_UNIT (insn
);
1024 recog_memoized (insn
);
1026 /* A USE insn, or something else we don't need to understand.
1027 We can't pass these directly to function_units_used because it will
1028 trigger a fatal error for unrecognizable insns. */
1029 if (INSN_CODE (insn
) < 0)
1033 unit
= function_units_used (insn
);
1034 /* Increment non-negative values so we can cache zero. */
1035 if (unit
>= 0) unit
++;
1037 /* We only cache 16 bits of the result, so if the value is out of
1038 range, don't cache it. */
1039 if (FUNCTION_UNITS_SIZE
< HOST_BITS_PER_SHORT
1041 || (~unit
& ((1 << (HOST_BITS_PER_SHORT
- 1)) - 1)) == 0)
1042 INSN_UNIT (insn
) = unit
;
1044 return (unit
> 0 ? unit
- 1 : unit
);
1047 /* Compute the blockage range for executing INSN on UNIT. This caches
1048 the value returned by the blockage_range_function for the unit.
1049 These values are encoded in an int where the upper half gives the
1050 minimum value and the lower half gives the maximum value. */
1052 __inline
static unsigned int
1053 blockage_range (unit
, insn
)
1057 unsigned int blockage
= INSN_BLOCKAGE (insn
);
1060 if (UNIT_BLOCKED (blockage
) != unit
+ 1)
1062 range
= function_units
[unit
].blockage_range_function (insn
);
1063 /* We only cache the blockage range for one unit and then only if
1065 if (HOST_BITS_PER_INT
>= UNIT_BITS
+ 2 * BLOCKAGE_BITS
)
1066 INSN_BLOCKAGE (insn
) = ENCODE_BLOCKAGE (unit
+ 1, range
);
1069 range
= BLOCKAGE_RANGE (blockage
);
1074 /* A vector indexed by function unit instance giving the last insn to use
1075 the unit. The value of the function unit instance index for unit U
1076 instance I is (U + I * FUNCTION_UNITS_SIZE). */
1077 static rtx unit_last_insn
[FUNCTION_UNITS_SIZE
* MAX_MULTIPLICITY
];
1079 /* A vector indexed by function unit instance giving the minimum time when
1080 the unit will unblock based on the maximum blockage cost. */
1081 static int unit_tick
[FUNCTION_UNITS_SIZE
* MAX_MULTIPLICITY
];
1083 /* A vector indexed by function unit number giving the number of insns
1084 that remain to use the unit. */
1085 static int unit_n_insns
[FUNCTION_UNITS_SIZE
];
1087 /* Reset the function unit state to the null state. */
1094 bzero (unit_last_insn
, sizeof (unit_last_insn
));
1095 bzero (unit_tick
, sizeof (unit_tick
));
1096 bzero (unit_n_insns
, sizeof (unit_n_insns
));
1099 /* Record an insn as one that will use the units encoded by UNIT. */
1101 __inline
static void
1108 unit_n_insns
[unit
]++;
1110 for (i
= 0, unit
= ~unit
; unit
; i
++, unit
>>= 1)
1111 if ((unit
& 1) != 0)
1115 /* Return the actual hazard cost of executing INSN on the unit UNIT,
1116 instance INSTANCE at time CLOCK if the previous actual hazard cost
1120 actual_hazard_this_instance (unit
, instance
, insn
, clock
, cost
)
1121 int unit
, instance
, clock
, cost
;
1125 int tick
= unit_tick
[instance
];
1127 if (tick
- clock
> cost
)
1129 /* The scheduler is operating in reverse, so INSN is the executing
1130 insn and the unit's last insn is the candidate insn. We want a
1131 more exact measure of the blockage if we execute INSN at CLOCK
1132 given when we committed the execution of the unit's last insn.
1134 The blockage value is given by either the unit's max blockage
1135 constant, blockage range function, or blockage function. Use
1136 the most exact form for the given unit. */
1138 if (function_units
[unit
].blockage_range_function
)
1140 if (function_units
[unit
].blockage_function
)
1141 tick
+= (function_units
[unit
].blockage_function
1142 (insn
, unit_last_insn
[instance
])
1143 - function_units
[unit
].max_blockage
);
1145 tick
+= ((int) MAX_BLOCKAGE_COST (blockage_range (unit
, insn
))
1146 - function_units
[unit
].max_blockage
);
1148 if (tick
- clock
> cost
)
1149 cost
= tick
- clock
;
1154 /* Record INSN as having begun execution on the units encoded by UNIT at
1157 __inline
static void
1158 schedule_unit (unit
, insn
, clock
)
1166 int instance
= unit
;
1167 #if MAX_MULTIPLICITY > 1
1168 /* Find the first free instance of the function unit and use that
1169 one. We assume that one is free. */
1170 for (i
= function_units
[unit
].multiplicity
- 1; i
> 0; i
--)
1172 if (! actual_hazard_this_instance (unit
, instance
, insn
, clock
, 0))
1174 instance
+= FUNCTION_UNITS_SIZE
;
1177 unit_last_insn
[instance
] = insn
;
1178 unit_tick
[instance
] = (clock
+ function_units
[unit
].max_blockage
);
1181 for (i
= 0, unit
= ~unit
; unit
; i
++, unit
>>= 1)
1182 if ((unit
& 1) != 0)
1183 schedule_unit (i
, insn
, clock
);
1186 /* Return the actual hazard cost of executing INSN on the units encoded by
1187 UNIT at time CLOCK if the previous actual hazard cost was COST. */
1190 actual_hazard (unit
, insn
, clock
, cost
)
1191 int unit
, clock
, cost
;
1198 /* Find the instance of the function unit with the minimum hazard. */
1199 int instance
= unit
;
1200 int best
= instance
;
1201 int best_cost
= actual_hazard_this_instance (unit
, instance
, insn
,
1205 #if MAX_MULTIPLICITY > 1
1206 if (best_cost
> cost
)
1208 for (i
= function_units
[unit
].multiplicity
- 1; i
> 0; i
--)
1210 instance
+= FUNCTION_UNITS_SIZE
;
1211 this_cost
= actual_hazard_this_instance (unit
, instance
, insn
,
1213 if (this_cost
< best_cost
)
1216 best_cost
= this_cost
;
1217 if (this_cost
<= cost
)
1223 cost
= MAX (cost
, best_cost
);
1226 for (i
= 0, unit
= ~unit
; unit
; i
++, unit
>>= 1)
1227 if ((unit
& 1) != 0)
1228 cost
= actual_hazard (i
, insn
, clock
, cost
);
1233 /* Return the potential hazard cost of executing an instruction on the
1234 units encoded by UNIT if the previous potential hazard cost was COST.
1235 An insn with a large blockage time is chosen in preference to one
1236 with a smaller time; an insn that uses a unit that is more likely
1237 to be used is chosen in preference to one with a unit that is less
1238 used. We are trying to minimize a subsequent actual hazard. */
1241 potential_hazard (unit
, insn
, cost
)
1246 unsigned int minb
, maxb
;
1250 minb
= maxb
= function_units
[unit
].max_blockage
;
1253 if (function_units
[unit
].blockage_range_function
)
1255 maxb
= minb
= blockage_range (unit
, insn
);
1256 maxb
= MAX_BLOCKAGE_COST (maxb
);
1257 minb
= MIN_BLOCKAGE_COST (minb
);
1262 /* Make the number of instructions left dominate. Make the
1263 minimum delay dominate the maximum delay. If all these
1264 are the same, use the unit number to add an arbitrary
1265 ordering. Other terms can be added. */
1266 ncost
= minb
* 0x40 + maxb
;
1267 ncost
*= (unit_n_insns
[unit
] - 1) * 0x1000 + unit
;
1274 for (i
= 0, unit
= ~unit
; unit
; i
++, unit
>>= 1)
1275 if ((unit
& 1) != 0)
1276 cost
= potential_hazard (i
, insn
, cost
);
1281 /* Compute cost of executing INSN given the dependence LINK on the insn USED.
1282 This is the number of virtual cycles taken between instruction issue and
1283 instruction results. */
1286 insn_cost (insn
, link
, used
)
1287 rtx insn
, link
, used
;
1289 register int cost
= INSN_COST (insn
);
1293 recog_memoized (insn
);
1295 /* A USE insn, or something else we don't need to understand.
1296 We can't pass these directly to result_ready_cost because it will
1297 trigger a fatal error for unrecognizable insns. */
1298 if (INSN_CODE (insn
) < 0)
1300 INSN_COST (insn
) = 1;
1305 cost
= result_ready_cost (insn
);
1310 INSN_COST (insn
) = cost
;
1314 /* A USE insn should never require the value used to be computed. This
1315 allows the computation of a function's result and parameter values to
1316 overlap the return and call. */
1317 recog_memoized (used
);
1318 if (INSN_CODE (used
) < 0)
1319 LINK_COST_FREE (link
) = 1;
1321 /* If some dependencies vary the cost, compute the adjustment. Most
1322 commonly, the adjustment is complete: either the cost is ignored
1323 (in the case of an output- or anti-dependence), or the cost is
1324 unchanged. These values are cached in the link as LINK_COST_FREE
1325 and LINK_COST_ZERO. */
1327 if (LINK_COST_FREE (link
))
1330 else if (! LINK_COST_ZERO (link
))
1334 ADJUST_COST (used
, link
, insn
, ncost
);
1336 LINK_COST_FREE (link
) = ncost
= 1;
1338 LINK_COST_ZERO (link
) = 1;
1345 /* Compute the priority number for INSN. */
1351 if (insn
&& GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1355 int this_priority
= INSN_PRIORITY (insn
);
1358 if (this_priority
> 0)
1359 return this_priority
;
1363 /* Nonzero if these insns must be scheduled together. */
1364 if (SCHED_GROUP_P (insn
))
1367 while (SCHED_GROUP_P (prev
))
1369 prev
= PREV_INSN (prev
);
1370 INSN_REF_COUNT (prev
) += 1;
1374 for (prev
= LOG_LINKS (insn
); prev
; prev
= XEXP (prev
, 1))
1376 rtx x
= XEXP (prev
, 0);
1378 /* A dependence pointing to a note is always obsolete, because
1379 sched_analyze_insn will have created any necessary new dependences
1380 which replace it. Notes can be created when instructions are
1381 deleted by insn splitting, or by register allocation. */
1382 if (GET_CODE (x
) == NOTE
)
1384 remove_dependence (insn
, x
);
1388 /* Clear the link cost adjustment bits. */
1389 LINK_COST_FREE (prev
) = 0;
1391 LINK_COST_ZERO (prev
) = 0;
1394 /* This priority calculation was chosen because it results in the
1395 least instruction movement, and does not hurt the performance
1396 of the resulting code compared to the old algorithm.
1397 This makes the sched algorithm more stable, which results
1398 in better code, because there is less register pressure,
1399 cross jumping is more likely to work, and debugging is easier.
1401 When all instructions have a latency of 1, there is no need to
1402 move any instructions. Subtracting one here ensures that in such
1403 cases all instructions will end up with a priority of one, and
1404 hence no scheduling will be done.
1406 The original code did not subtract the one, and added the
1407 insn_cost of the current instruction to its priority (e.g.
1408 move the insn_cost call down to the end). */
1410 if (REG_NOTE_KIND (prev
) == 0)
1411 /* Data dependence. */
1412 prev_priority
= priority (x
) + insn_cost (x
, prev
, insn
) - 1;
1414 /* Anti or output dependence. Don't add the latency of this
1415 insn's result, because it isn't being used. */
1416 prev_priority
= priority (x
);
1418 if (prev_priority
> max_priority
)
1419 max_priority
= prev_priority
;
1420 INSN_REF_COUNT (x
) += 1;
1423 prepare_unit (insn_unit (insn
));
1424 INSN_PRIORITY (insn
) = max_priority
;
1425 return INSN_PRIORITY (insn
);
1430 /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
1431 them to the unused_*_list variables, so that they can be reused. */
1434 free_pending_lists ()
1436 register rtx link
, prev_link
;
1438 if (pending_read_insns
)
1440 prev_link
= pending_read_insns
;
1441 link
= XEXP (prev_link
, 1);
1446 link
= XEXP (link
, 1);
1449 XEXP (prev_link
, 1) = unused_insn_list
;
1450 unused_insn_list
= pending_read_insns
;
1451 pending_read_insns
= 0;
1454 if (pending_write_insns
)
1456 prev_link
= pending_write_insns
;
1457 link
= XEXP (prev_link
, 1);
1462 link
= XEXP (link
, 1);
1465 XEXP (prev_link
, 1) = unused_insn_list
;
1466 unused_insn_list
= pending_write_insns
;
1467 pending_write_insns
= 0;
1470 if (pending_read_mems
)
1472 prev_link
= pending_read_mems
;
1473 link
= XEXP (prev_link
, 1);
1478 link
= XEXP (link
, 1);
1481 XEXP (prev_link
, 1) = unused_expr_list
;
1482 unused_expr_list
= pending_read_mems
;
1483 pending_read_mems
= 0;
1486 if (pending_write_mems
)
1488 prev_link
= pending_write_mems
;
1489 link
= XEXP (prev_link
, 1);
1494 link
= XEXP (link
, 1);
1497 XEXP (prev_link
, 1) = unused_expr_list
;
1498 unused_expr_list
= pending_write_mems
;
1499 pending_write_mems
= 0;
1503 /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
1504 The MEM is a memory reference contained within INSN, which we are saving
1505 so that we can do memory aliasing on it. */
1508 add_insn_mem_dependence (insn_list
, mem_list
, insn
, mem
)
1509 rtx
*insn_list
, *mem_list
, insn
, mem
;
1513 if (unused_insn_list
)
1515 link
= unused_insn_list
;
1516 unused_insn_list
= XEXP (link
, 1);
1519 link
= rtx_alloc (INSN_LIST
);
1520 XEXP (link
, 0) = insn
;
1521 XEXP (link
, 1) = *insn_list
;
1524 if (unused_expr_list
)
1526 link
= unused_expr_list
;
1527 unused_expr_list
= XEXP (link
, 1);
1530 link
= rtx_alloc (EXPR_LIST
);
1531 XEXP (link
, 0) = mem
;
1532 XEXP (link
, 1) = *mem_list
;
1535 pending_lists_length
++;
1538 /* Make a dependency between every memory reference on the pending lists
1539 and INSN, thus flushing the pending lists. */
1542 flush_pending_lists (insn
)
1547 while (pending_read_insns
)
1549 add_dependence (insn
, XEXP (pending_read_insns
, 0), REG_DEP_ANTI
);
1551 link
= pending_read_insns
;
1552 pending_read_insns
= XEXP (pending_read_insns
, 1);
1553 XEXP (link
, 1) = unused_insn_list
;
1554 unused_insn_list
= link
;
1556 link
= pending_read_mems
;
1557 pending_read_mems
= XEXP (pending_read_mems
, 1);
1558 XEXP (link
, 1) = unused_expr_list
;
1559 unused_expr_list
= link
;
1561 while (pending_write_insns
)
1563 add_dependence (insn
, XEXP (pending_write_insns
, 0), REG_DEP_ANTI
);
1565 link
= pending_write_insns
;
1566 pending_write_insns
= XEXP (pending_write_insns
, 1);
1567 XEXP (link
, 1) = unused_insn_list
;
1568 unused_insn_list
= link
;
1570 link
= pending_write_mems
;
1571 pending_write_mems
= XEXP (pending_write_mems
, 1);
1572 XEXP (link
, 1) = unused_expr_list
;
1573 unused_expr_list
= link
;
1575 pending_lists_length
= 0;
1577 if (last_pending_memory_flush
)
1578 add_dependence (insn
, last_pending_memory_flush
, REG_DEP_ANTI
);
1580 last_pending_memory_flush
= insn
;
1583 /* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated
1584 by the write to the destination of X, and reads of everything mentioned. */
1587 sched_analyze_1 (x
, insn
)
1592 register rtx dest
= SET_DEST (x
);
1597 while (GET_CODE (dest
) == STRICT_LOW_PART
|| GET_CODE (dest
) == SUBREG
1598 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SIGN_EXTRACT
)
1600 if (GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SIGN_EXTRACT
)
1602 /* The second and third arguments are values read by this insn. */
1603 sched_analyze_2 (XEXP (dest
, 1), insn
);
1604 sched_analyze_2 (XEXP (dest
, 2), insn
);
1606 dest
= SUBREG_REG (dest
);
1609 if (GET_CODE (dest
) == REG
)
1611 register int offset
, bit
, i
;
1613 regno
= REGNO (dest
);
1615 /* A hard reg in a wide mode may really be multiple registers.
1616 If so, mark all of them just like the first. */
1617 if (regno
< FIRST_PSEUDO_REGISTER
)
1619 i
= HARD_REGNO_NREGS (regno
, GET_MODE (dest
));
1624 for (u
= reg_last_uses
[regno
+i
]; u
; u
= XEXP (u
, 1))
1625 add_dependence (insn
, XEXP (u
, 0), REG_DEP_ANTI
);
1626 reg_last_uses
[regno
+ i
] = 0;
1627 if (reg_last_sets
[regno
+ i
])
1628 add_dependence (insn
, reg_last_sets
[regno
+ i
],
1630 reg_last_sets
[regno
+ i
] = insn
;
1631 if ((call_used_regs
[i
] || global_regs
[i
])
1632 && last_function_call
)
1633 /* Function calls clobber all call_used regs. */
1634 add_dependence (insn
, last_function_call
, REG_DEP_ANTI
);
1641 for (u
= reg_last_uses
[regno
]; u
; u
= XEXP (u
, 1))
1642 add_dependence (insn
, XEXP (u
, 0), REG_DEP_ANTI
);
1643 reg_last_uses
[regno
] = 0;
1644 if (reg_last_sets
[regno
])
1645 add_dependence (insn
, reg_last_sets
[regno
], REG_DEP_OUTPUT
);
1646 reg_last_sets
[regno
] = insn
;
1648 /* Pseudos that are REG_EQUIV to something may be replaced
1649 by that during reloading. We need only add dependencies for
1650 the address in the REG_EQUIV note. */
1651 if (! reload_completed
1652 && reg_known_equiv_p
[regno
]
1653 && GET_CODE (reg_known_value
[regno
]) == MEM
)
1654 sched_analyze_2 (XEXP (reg_known_value
[regno
], 0), insn
);
1656 /* Don't let it cross a call after scheduling if it doesn't
1657 already cross one. */
1658 if (reg_n_calls_crossed
[regno
] == 0 && last_function_call
)
1659 add_dependence (insn
, last_function_call
, REG_DEP_ANTI
);
1662 else if (GET_CODE (dest
) == MEM
)
1664 /* Writing memory. */
1666 if (pending_lists_length
> 32)
1668 /* Flush all pending reads and writes to prevent the pending lists
1669 from getting any larger. Insn scheduling runs too slowly when
1670 these lists get long. The number 32 was chosen because it
1671 seems like a reasonable number. When compiling GCC with itself,
1672 this flush occurs 8 times for sparc, and 10 times for m88k using
1674 flush_pending_lists (insn
);
1678 rtx pending
, pending_mem
;
1680 pending
= pending_read_insns
;
1681 pending_mem
= pending_read_mems
;
1684 /* If a dependency already exists, don't create a new one. */
1685 if (! find_insn_list (XEXP (pending
, 0), LOG_LINKS (insn
)))
1686 if (anti_dependence (XEXP (pending_mem
, 0), dest
))
1687 add_dependence (insn
, XEXP (pending
, 0), REG_DEP_ANTI
);
1689 pending
= XEXP (pending
, 1);
1690 pending_mem
= XEXP (pending_mem
, 1);
1693 pending
= pending_write_insns
;
1694 pending_mem
= pending_write_mems
;
1697 /* If a dependency already exists, don't create a new one. */
1698 if (! find_insn_list (XEXP (pending
, 0), LOG_LINKS (insn
)))
1699 if (output_dependence (XEXP (pending_mem
, 0), dest
))
1700 add_dependence (insn
, XEXP (pending
, 0), REG_DEP_OUTPUT
);
1702 pending
= XEXP (pending
, 1);
1703 pending_mem
= XEXP (pending_mem
, 1);
1706 if (last_pending_memory_flush
)
1707 add_dependence (insn
, last_pending_memory_flush
, REG_DEP_ANTI
);
1709 add_insn_mem_dependence (&pending_write_insns
, &pending_write_mems
,
1712 sched_analyze_2 (XEXP (dest
, 0), insn
);
1715 /* Analyze reads. */
1716 if (GET_CODE (x
) == SET
)
1717 sched_analyze_2 (SET_SRC (x
), insn
);
1720 /* Analyze the uses of memory and registers in rtx X in INSN. */
1723 sched_analyze_2 (x
, insn
)
1729 register enum rtx_code code
;
1735 code
= GET_CODE (x
);
1744 /* Ignore constants. Note that we must handle CONST_DOUBLE here
1745 because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
1746 this does not mean that this insn is using cc0. */
1754 /* There may be a note before this insn now, but all notes will
1755 be removed before we actually try to schedule the insns, so
1756 it won't cause a problem later. We must avoid it here though. */
1758 /* User of CC0 depends on immediately preceding insn. */
1759 SCHED_GROUP_P (insn
) = 1;
1761 /* Make a copy of all dependencies on the immediately previous insn,
1762 and add to this insn. This is so that all the dependencies will
1763 apply to the group. Remove an explicit dependence on this insn
1764 as SCHED_GROUP_P now represents it. */
1766 prev
= PREV_INSN (insn
);
1767 while (GET_CODE (prev
) == NOTE
)
1768 prev
= PREV_INSN (prev
);
1770 if (find_insn_list (prev
, LOG_LINKS (insn
)))
1771 remove_dependence (insn
, prev
);
1773 for (link
= LOG_LINKS (prev
); link
; link
= XEXP (link
, 1))
1774 add_dependence (insn
, XEXP (link
, 0), REG_NOTE_KIND (link
));
1782 int regno
= REGNO (x
);
1783 if (regno
< FIRST_PSEUDO_REGISTER
)
1787 i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
1790 reg_last_uses
[regno
+ i
]
1791 = gen_rtx (INSN_LIST
, VOIDmode
,
1792 insn
, reg_last_uses
[regno
+ i
]);
1793 if (reg_last_sets
[regno
+ i
])
1794 add_dependence (insn
, reg_last_sets
[regno
+ i
], 0);
1795 if ((call_used_regs
[regno
+ i
] || global_regs
[regno
+ i
])
1796 && last_function_call
)
1797 /* Function calls clobber all call_used regs. */
1798 add_dependence (insn
, last_function_call
, REG_DEP_ANTI
);
1803 reg_last_uses
[regno
]
1804 = gen_rtx (INSN_LIST
, VOIDmode
, insn
, reg_last_uses
[regno
]);
1805 if (reg_last_sets
[regno
])
1806 add_dependence (insn
, reg_last_sets
[regno
], 0);
1808 /* Pseudos that are REG_EQUIV to something may be replaced
1809 by that during reloading. We need only add dependencies for
1810 the address in the REG_EQUIV note. */
1811 if (! reload_completed
1812 && reg_known_equiv_p
[regno
]
1813 && GET_CODE (reg_known_value
[regno
]) == MEM
)
1814 sched_analyze_2 (XEXP (reg_known_value
[regno
], 0), insn
);
1816 /* If the register does not already cross any calls, then add this
1817 insn to the sched_before_next_call list so that it will still
1818 not cross calls after scheduling. */
1819 if (reg_n_calls_crossed
[regno
] == 0)
1820 add_dependence (sched_before_next_call
, insn
, REG_DEP_ANTI
);
1827 /* Reading memory. */
1829 rtx pending
, pending_mem
;
1831 pending
= pending_read_insns
;
1832 pending_mem
= pending_read_mems
;
1835 /* If a dependency already exists, don't create a new one. */
1836 if (! find_insn_list (XEXP (pending
, 0), LOG_LINKS (insn
)))
1837 if (read_dependence (XEXP (pending_mem
, 0), x
))
1838 add_dependence (insn
, XEXP (pending
, 0), REG_DEP_ANTI
);
1840 pending
= XEXP (pending
, 1);
1841 pending_mem
= XEXP (pending_mem
, 1);
1844 pending
= pending_write_insns
;
1845 pending_mem
= pending_write_mems
;
1848 /* If a dependency already exists, don't create a new one. */
1849 if (! find_insn_list (XEXP (pending
, 0), LOG_LINKS (insn
)))
1850 if (true_dependence (XEXP (pending_mem
, 0), x
))
1851 add_dependence (insn
, XEXP (pending
, 0), 0);
1853 pending
= XEXP (pending
, 1);
1854 pending_mem
= XEXP (pending_mem
, 1);
1856 if (last_pending_memory_flush
)
1857 add_dependence (insn
, last_pending_memory_flush
, REG_DEP_ANTI
);
1859 /* Always add these dependencies to pending_reads, since
1860 this insn may be followed by a write. */
1861 add_insn_mem_dependence (&pending_read_insns
, &pending_read_mems
,
1864 /* Take advantage of tail recursion here. */
1865 sched_analyze_2 (XEXP (x
, 0), insn
);
1871 case UNSPEC_VOLATILE
:
1876 /* Traditional and volatile asm instructions must be considered to use
1877 and clobber all hard registers and all of memory. So must
1878 TRAP_IF and UNSPEC_VOLATILE operations. */
1879 if (code
!= ASM_OPERANDS
|| MEM_VOLATILE_P (x
))
1881 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1883 for (u
= reg_last_uses
[i
]; u
; u
= XEXP (u
, 1))
1884 if (GET_CODE (PATTERN (XEXP (u
, 0))) != USE
)
1885 add_dependence (insn
, XEXP (u
, 0), REG_DEP_ANTI
);
1886 reg_last_uses
[i
] = 0;
1887 if (reg_last_sets
[i
]
1888 && GET_CODE (PATTERN (reg_last_sets
[i
])) != USE
)
1889 add_dependence (insn
, reg_last_sets
[i
], 0);
1890 reg_last_sets
[i
] = insn
;
1893 flush_pending_lists (insn
);
1896 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
1897 We can not just fall through here since then we would be confused
1898 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
1899 traditional asms unlike their normal usage. */
1901 if (code
== ASM_OPERANDS
)
1903 for (j
= 0; j
< ASM_OPERANDS_INPUT_LENGTH (x
); j
++)
1904 sched_analyze_2 (ASM_OPERANDS_INPUT (x
, j
), insn
);
1914 /* These both read and modify the result. We must handle them as writes
1915 to get proper dependencies for following instructions. We must handle
1916 them as reads to get proper dependencies from this to previous
1917 instructions. Thus we need to pass them to both sched_analyze_1
1918 and sched_analyze_2. We must call sched_analyze_2 first in order
1919 to get the proper antecedent for the read. */
1920 sched_analyze_2 (XEXP (x
, 0), insn
);
1921 sched_analyze_1 (x
, insn
);
1925 /* Other cases: walk the insn. */
1926 fmt
= GET_RTX_FORMAT (code
);
1927 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1930 sched_analyze_2 (XEXP (x
, i
), insn
);
1931 else if (fmt
[i
] == 'E')
1932 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1933 sched_analyze_2 (XVECEXP (x
, i
, j
), insn
);
1937 /* Analyze an INSN with pattern X to find all dependencies. */
1940 sched_analyze_insn (x
, insn
)
1943 register RTX_CODE code
= GET_CODE (x
);
1946 if (code
== SET
|| code
== CLOBBER
)
1947 sched_analyze_1 (x
, insn
);
1948 else if (code
== PARALLEL
)
1951 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1953 code
= GET_CODE (XVECEXP (x
, 0, i
));
1954 if (code
== SET
|| code
== CLOBBER
)
1955 sched_analyze_1 (XVECEXP (x
, 0, i
), insn
);
1957 sched_analyze_2 (XVECEXP (x
, 0, i
), insn
);
1961 sched_analyze_2 (x
, insn
);
1963 /* Handle function calls. */
1964 if (GET_CODE (insn
) == CALL_INSN
)
1969 /* When scheduling instructions, we make sure calls don't lose their
1970 accompanying USE insns by depending them one on another in order. */
1972 prev_dep_insn
= insn
;
1973 dep_insn
= PREV_INSN (insn
);
1974 while (GET_CODE (dep_insn
) == INSN
1975 && GET_CODE (PATTERN (dep_insn
)) == USE
)
1977 SCHED_GROUP_P (prev_dep_insn
) = 1;
1979 /* Make a copy of all dependencies on dep_insn, and add to insn.
1980 This is so that all of the dependencies will apply to the
1983 for (link
= LOG_LINKS (dep_insn
); link
; link
= XEXP (link
, 1))
1984 add_dependence (insn
, XEXP (link
, 0), REG_NOTE_KIND (link
));
1986 prev_dep_insn
= dep_insn
;
1987 dep_insn
= PREV_INSN (dep_insn
);
1992 /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
1993 for every dependency. */
1996 sched_analyze (head
, tail
)
2000 register int n_insns
= 0;
2002 register int luid
= 0;
2004 for (insn
= head
; ; insn
= NEXT_INSN (insn
))
2006 INSN_LUID (insn
) = luid
++;
2008 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
)
2010 sched_analyze_insn (PATTERN (insn
), insn
);
2013 else if (GET_CODE (insn
) == CALL_INSN
)
2019 /* Any instruction using a hard register which may get clobbered
2020 by a call needs to be marked as dependent on this call.
2021 This prevents a use of a hard return reg from being moved
2022 past a void call (i.e. it does not explicitly set the hard
2025 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2026 if (call_used_regs
[i
] || global_regs
[i
])
2028 for (u
= reg_last_uses
[i
]; u
; u
= XEXP (u
, 1))
2029 if (GET_CODE (PATTERN (XEXP (u
, 0))) != USE
)
2030 add_dependence (insn
, XEXP (u
, 0), REG_DEP_ANTI
);
2031 reg_last_uses
[i
] = 0;
2032 if (reg_last_sets
[i
]
2033 && GET_CODE (PATTERN (reg_last_sets
[i
])) != USE
)
2034 add_dependence (insn
, reg_last_sets
[i
], REG_DEP_ANTI
);
2035 reg_last_sets
[i
] = insn
;
2036 /* Insn, being a CALL_INSN, magically depends on
2037 `last_function_call' already. */
2040 /* For each insn which shouldn't cross a call, add a dependence
2041 between that insn and this call insn. */
2042 x
= LOG_LINKS (sched_before_next_call
);
2045 add_dependence (insn
, XEXP (x
, 0), REG_DEP_ANTI
);
2048 LOG_LINKS (sched_before_next_call
) = 0;
2050 sched_analyze_insn (PATTERN (insn
), insn
);
2052 /* We don't need to flush memory for a function call which does
2053 not involve memory. */
2054 if (! CONST_CALL_P (insn
))
2056 /* In the absence of interprocedural alias analysis,
2057 we must flush all pending reads and writes, and
2058 start new dependencies starting from here. */
2059 flush_pending_lists (insn
);
2062 /* Depend this function call (actually, the user of this
2063 function call) on all hard register clobberage. */
2064 last_function_call
= insn
;
2073 /* Called when we see a set of a register. If death is true, then we are
2074 scanning backwards. Mark that register as unborn. If nobody says
2075 otherwise, that is how things will remain. If death is false, then we
2076 are scanning forwards. Mark that register as being born. */
2079 sched_note_set (b
, x
, death
)
2084 register int regno
, j
;
2085 register rtx reg
= SET_DEST (x
);
2091 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == STRICT_LOW_PART
2092 || GET_CODE (reg
) == SIGN_EXTRACT
|| GET_CODE (reg
) == ZERO_EXTRACT
)
2094 /* Must treat modification of just one hardware register of a multi-reg
2095 value or just a byte field of a register exactly the same way that
2096 mark_set_1 in flow.c does, i.e. anything except a paradoxical subreg
2097 does not kill the entire register. */
2098 if (GET_CODE (reg
) != SUBREG
2099 || REG_SIZE (SUBREG_REG (reg
)) > REG_SIZE (reg
))
2102 reg
= SUBREG_REG (reg
);
2105 if (GET_CODE (reg
) != REG
)
2108 /* Global registers are always live, so the code below does not apply
2111 regno
= REGNO (reg
);
2112 if (regno
>= FIRST_PSEUDO_REGISTER
|| ! global_regs
[regno
])
2114 register int offset
= regno
/ REGSET_ELT_BITS
;
2115 register REGSET_ELT_TYPE bit
2116 = (REGSET_ELT_TYPE
) 1 << (regno
% REGSET_ELT_BITS
);
2120 /* If we only set part of the register, then this set does not
2125 /* Try killing this register. */
2126 if (regno
< FIRST_PSEUDO_REGISTER
)
2128 int j
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
2131 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
2132 bit
= (REGSET_ELT_TYPE
) 1 << ((regno
+ j
) % REGSET_ELT_BITS
);
2134 bb_live_regs
[offset
] &= ~bit
;
2135 bb_dead_regs
[offset
] |= bit
;
2140 bb_live_regs
[offset
] &= ~bit
;
2141 bb_dead_regs
[offset
] |= bit
;
2146 /* Make the register live again. */
2147 if (regno
< FIRST_PSEUDO_REGISTER
)
2149 int j
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
2152 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
2153 bit
= (REGSET_ELT_TYPE
) 1 << ((regno
+ j
) % REGSET_ELT_BITS
);
2155 bb_live_regs
[offset
] |= bit
;
2156 bb_dead_regs
[offset
] &= ~bit
;
2161 bb_live_regs
[offset
] |= bit
;
2162 bb_dead_regs
[offset
] &= ~bit
;
2168 /* Macros and functions for keeping the priority queue sorted, and
2169 dealing with queueing and unqueueing of instructions. */
2171 #define SCHED_SORT(READY, NEW_READY, OLD_READY) \
2172 do { if ((NEW_READY) - (OLD_READY) == 1) \
2173 swap_sort (READY, NEW_READY); \
2174 else if ((NEW_READY) - (OLD_READY) > 1) \
2175 qsort (READY, NEW_READY, sizeof (rtx), rank_for_schedule); } \
2178 /* Returns a positive value if y is preferred; returns a negative value if
2179 x is preferred. Should never return 0, since that will make the sort
2183 rank_for_schedule (x
, y
)
2189 int tmp_class
, tmp2_class
;
2192 /* Choose the instruction with the highest priority, if different. */
2193 if (value
= INSN_PRIORITY (tmp
) - INSN_PRIORITY (tmp2
))
2196 if (last_scheduled_insn
)
2198 /* Classify the instructions into three classes:
2199 1) Data dependent on last schedule insn.
2200 2) Anti/Output dependent on last scheduled insn.
2201 3) Independent of last scheduled insn, or has latency of one.
2202 Choose the insn from the highest numbered class if different. */
2203 link
= find_insn_list (tmp
, LOG_LINKS (last_scheduled_insn
));
2204 if (link
== 0 || insn_cost (tmp
, link
, last_scheduled_insn
) == 1)
2206 else if (REG_NOTE_KIND (link
) == 0) /* Data dependence. */
2211 link
= find_insn_list (tmp2
, LOG_LINKS (last_scheduled_insn
));
2212 if (link
== 0 || insn_cost (tmp2
, link
, last_scheduled_insn
) == 1)
2214 else if (REG_NOTE_KIND (link
) == 0) /* Data dependence. */
2219 if (value
= tmp_class
- tmp2_class
)
2223 /* If insns are equally good, sort by INSN_LUID (original insn order),
2224 so that we make the sort stable. This minimizes instruction movement,
2225 thus minimizing sched's effect on debugging and cross-jumping. */
2226 return INSN_LUID (tmp
) - INSN_LUID (tmp2
);
2229 /* Resort the array A in which only element at index N may be out of order. */
2231 __inline
static void
2239 while (i
>= 0 && rank_for_schedule (a
+i
, &insn
) >= 0)
2247 static int max_priority
;
2249 /* Add INSN to the insn queue so that it fires at least N_CYCLES
2250 before the currently executing insn. */
2252 __inline
static void
2253 queue_insn (insn
, n_cycles
)
2257 int next_q
= NEXT_Q_AFTER (q_ptr
, n_cycles
);
2258 NEXT_INSN (insn
) = insn_queue
[next_q
];
2259 insn_queue
[next_q
] = insn
;
2263 /* Return nonzero if PAT is the pattern of an insn which makes a
2267 birthing_insn_p (pat
)
2272 if (reload_completed
== 1)
2275 if (GET_CODE (pat
) == SET
2276 && GET_CODE (SET_DEST (pat
)) == REG
)
2278 rtx dest
= SET_DEST (pat
);
2279 int i
= REGNO (dest
);
2280 int offset
= i
/ REGSET_ELT_BITS
;
2281 REGSET_ELT_TYPE bit
= (REGSET_ELT_TYPE
) 1 << (i
% REGSET_ELT_BITS
);
2283 /* It would be more accurate to use refers_to_regno_p or
2284 reg_mentioned_p to determine when the dest is not live before this
2287 if (bb_live_regs
[offset
] & bit
)
2288 return (reg_n_sets
[i
] == 1);
2292 if (GET_CODE (pat
) == PARALLEL
)
2294 for (j
= 0; j
< XVECLEN (pat
, 0); j
++)
2295 if (birthing_insn_p (XVECEXP (pat
, 0, j
)))
2301 /* PREV is an insn that is ready to execute. Adjust its priority if that
2302 will help shorten register lifetimes. */
2304 __inline
static void
2305 adjust_priority (prev
)
2308 /* Trying to shorten register lives after reload has completed
2309 is useless and wrong. It gives inaccurate schedules. */
2310 if (reload_completed
== 0)
2315 /* ??? This code has no effect, because REG_DEAD notes are removed
2316 before we ever get here. */
2317 for (note
= REG_NOTES (prev
); note
; note
= XEXP (note
, 1))
2318 if (REG_NOTE_KIND (note
) == REG_DEAD
)
2321 /* Defer scheduling insns which kill registers, since that
2322 shortens register lives. Prefer scheduling insns which
2323 make registers live for the same reason. */
2327 INSN_PRIORITY (prev
) >>= 3;
2330 INSN_PRIORITY (prev
) >>= 2;
2334 INSN_PRIORITY (prev
) >>= 1;
2337 if (birthing_insn_p (PATTERN (prev
)))
2339 int max
= max_priority
;
2341 if (max
> INSN_PRIORITY (prev
))
2342 INSN_PRIORITY (prev
) = max
;
2349 /* INSN is the "currently executing insn". Launch each insn which was
2350 waiting on INSN (in the backwards dataflow sense). READY is a
2351 vector of insns which are ready to fire. N_READY is the number of
2352 elements in READY. CLOCK is the current virtual cycle. */
2355 schedule_insn (insn
, ready
, n_ready
, clock
)
2362 int new_ready
= n_ready
;
2364 if (MAX_BLOCKAGE
> 1)
2365 schedule_unit (insn_unit (insn
), insn
, clock
);
2367 if (LOG_LINKS (insn
) == 0)
2370 /* This is used by the function adjust_priority above. */
2372 max_priority
= MAX (INSN_PRIORITY (ready
[0]), INSN_PRIORITY (insn
));
2374 max_priority
= INSN_PRIORITY (insn
);
2376 for (link
= LOG_LINKS (insn
); link
!= 0; link
= XEXP (link
, 1))
2378 rtx prev
= XEXP (link
, 0);
2379 int cost
= insn_cost (prev
, link
, insn
);
2381 if ((INSN_REF_COUNT (prev
) -= 1) != 0)
2383 /* We satisfied one requirement to fire PREV. Record the earliest
2384 time when PREV can fire. No need to do this if the cost is 1,
2385 because PREV can fire no sooner than the next cycle. */
2387 INSN_TICK (prev
) = MAX (INSN_TICK (prev
), clock
+ cost
);
2391 /* We satisfied the last requirement to fire PREV. Ensure that all
2392 timing requirements are satisfied. */
2393 if (INSN_TICK (prev
) - clock
> cost
)
2394 cost
= INSN_TICK (prev
) - clock
;
2396 /* Adjust the priority of PREV and either put it on the ready
2397 list or queue it. */
2398 adjust_priority (prev
);
2400 ready
[new_ready
++] = prev
;
2402 queue_insn (prev
, cost
);
2409 /* Given N_READY insns in the ready list READY at time CLOCK, queue
2410 those that are blocked due to function unit hazards and rearrange
2411 the remaining ones to minimize subsequent function unit hazards. */
2414 schedule_select (ready
, n_ready
, clock
, file
)
2419 int pri
= INSN_PRIORITY (ready
[0]);
2420 int i
, j
, k
, q
, cost
, best_cost
, best_insn
= 0, new_ready
= n_ready
;
2423 /* Work down the ready list in groups of instructions with the same
2424 priority value. Queue insns in the group that are blocked and
2425 select among those that remain for the one with the largest
2426 potential hazard. */
2427 for (i
= 0; i
< n_ready
; i
= j
)
2430 for (j
= i
+ 1; j
< n_ready
; j
++)
2431 if ((pri
= INSN_PRIORITY (ready
[j
])) != opri
)
2434 /* Queue insns in the group that are blocked. */
2435 for (k
= i
, q
= 0; k
< j
; k
++)
2438 if ((cost
= actual_hazard (insn_unit (insn
), insn
, clock
, 0)) != 0)
2442 queue_insn (insn
, cost
);
2444 fprintf (file
, "\n;; blocking insn %d for %d cycles",
2445 INSN_UID (insn
), cost
);
2450 /* Check the next group if all insns were queued. */
2454 /* If more than one remains, select the first one with the largest
2455 potential hazard. */
2456 else if (j
- i
- q
> 1)
2459 for (k
= i
; k
< j
; k
++)
2461 if ((insn
= ready
[k
]) == 0)
2463 if ((cost
= potential_hazard (insn_unit (insn
), insn
, 0))
2471 /* We have found a suitable insn to schedule. */
2475 /* Move the best insn to be front of the ready list. */
2480 fprintf (file
, ", now");
2481 for (i
= 0; i
< n_ready
; i
++)
2483 fprintf (file
, " %d", INSN_UID (ready
[i
]));
2484 fprintf (file
, "\n;; insn %d has a greater potential hazard",
2485 INSN_UID (ready
[best_insn
]));
2487 for (i
= best_insn
; i
> 0; i
--)
2490 ready
[i
-1] = ready
[i
];
2495 /* Compact the ready list. */
2496 if (new_ready
< n_ready
)
2497 for (i
= j
= 0; i
< n_ready
; i
++)
2499 ready
[j
++] = ready
[i
];
2504 /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the
2508 create_reg_dead_note (reg
, insn
)
2511 rtx link
= dead_notes
;
2514 /* In theory, we should not end up with more REG_DEAD reg notes than we
2515 started with. In practice, this can occur as the result of bugs in
2516 flow, combine and/or sched. */
2521 link
= rtx_alloc (EXPR_LIST
);
2522 PUT_REG_NOTE_KIND (link
, REG_DEAD
);
2526 dead_notes
= XEXP (dead_notes
, 1);
2528 XEXP (link
, 0) = reg
;
2529 XEXP (link
, 1) = REG_NOTES (insn
);
2530 REG_NOTES (insn
) = link
;
2533 /* Subroutine on attach_deaths_insn--handles the recursive search
2534 through INSN. If SET_P is true, then x is being modified by the insn. */
2537 attach_deaths (x
, insn
, set_p
)
2544 register enum rtx_code code
;
2550 code
= GET_CODE (x
);
2562 /* Get rid of the easy cases first. */
2567 /* If the register dies in this insn, queue that note, and mark
2568 this register as needing to die. */
2569 /* This code is very similar to mark_used_1 (if set_p is false)
2570 and mark_set_1 (if set_p is true) in flow.c. */
2572 register int regno
= REGNO (x
);
2573 register int offset
= regno
/ REGSET_ELT_BITS
;
2574 register REGSET_ELT_TYPE bit
2575 = (REGSET_ELT_TYPE
) 1 << (regno
% REGSET_ELT_BITS
);
2576 REGSET_ELT_TYPE all_needed
= (old_live_regs
[offset
] & bit
);
2577 REGSET_ELT_TYPE some_needed
= (old_live_regs
[offset
] & bit
);
2582 if (regno
< FIRST_PSEUDO_REGISTER
)
2586 n
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
2589 some_needed
|= (old_live_regs
[(regno
+ n
) / REGSET_ELT_BITS
]
2590 & ((REGSET_ELT_TYPE
) 1
2591 << ((regno
+ n
) % REGSET_ELT_BITS
)));
2592 all_needed
&= (old_live_regs
[(regno
+ n
) / REGSET_ELT_BITS
]
2593 & ((REGSET_ELT_TYPE
) 1
2594 << ((regno
+ n
) % REGSET_ELT_BITS
)));
2598 /* If it wasn't live before we started, then add a REG_DEAD note.
2599 We must check the previous lifetime info not the current info,
2600 because we may have to execute this code several times, e.g.
2601 once for a clobber (which doesn't add a note) and later
2602 for a use (which does add a note).
2604 Always make the register live. We must do this even if it was
2605 live before, because this may be an insn which sets and uses
2606 the same register, in which case the register has already been
2607 killed, so we must make it live again.
2609 Global registers are always live, and should never have a REG_DEAD
2610 note added for them, so none of the code below applies to them. */
2612 if (regno
>= FIRST_PSEUDO_REGISTER
|| ! global_regs
[regno
])
2614 /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2615 STACK_POINTER_REGNUM, since these are always considered to be
2616 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2617 if (regno
!= FRAME_POINTER_REGNUM
2618 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2619 && ! (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
2621 && regno
!= STACK_POINTER_REGNUM
)
2623 if (! all_needed
&& ! dead_or_set_p (insn
, x
))
2625 /* If none of the words in X is needed, make a REG_DEAD
2626 note. Otherwise, we must make partial REG_DEAD
2629 create_reg_dead_note (x
, insn
);
2634 /* Don't make a REG_DEAD note for a part of a
2635 register that is set in the insn. */
2636 for (i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
)) - 1;
2638 if ((old_live_regs
[(regno
+ i
) / REGSET_ELT_BITS
]
2639 & ((REGSET_ELT_TYPE
) 1
2640 << ((regno
+i
) % REGSET_ELT_BITS
))) == 0
2641 && ! dead_or_set_regno_p (insn
, regno
+ i
))
2642 create_reg_dead_note (gen_rtx (REG
, word_mode
,
2649 if (regno
< FIRST_PSEUDO_REGISTER
)
2651 int j
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
2654 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
2656 = (REGSET_ELT_TYPE
) 1 << ((regno
+ j
) % REGSET_ELT_BITS
);
2658 bb_dead_regs
[offset
] &= ~bit
;
2659 bb_live_regs
[offset
] |= bit
;
2664 bb_dead_regs
[offset
] &= ~bit
;
2665 bb_live_regs
[offset
] |= bit
;
2672 /* Handle tail-recursive case. */
2673 attach_deaths (XEXP (x
, 0), insn
, 0);
2677 case STRICT_LOW_PART
:
2678 /* These two cases preserve the value of SET_P, so handle them
2680 attach_deaths (XEXP (x
, 0), insn
, set_p
);
2685 /* This case preserves the value of SET_P for the first operand, but
2686 clears it for the other two. */
2687 attach_deaths (XEXP (x
, 0), insn
, set_p
);
2688 attach_deaths (XEXP (x
, 1), insn
, 0);
2689 attach_deaths (XEXP (x
, 2), insn
, 0);
2693 /* Other cases: walk the insn. */
2694 fmt
= GET_RTX_FORMAT (code
);
2695 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2698 attach_deaths (XEXP (x
, i
), insn
, 0);
2699 else if (fmt
[i
] == 'E')
2700 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2701 attach_deaths (XVECEXP (x
, i
, j
), insn
, 0);
2706 /* After INSN has executed, add register death notes for each register
2707 that is dead after INSN. */
2710 attach_deaths_insn (insn
)
2713 rtx x
= PATTERN (insn
);
2714 register RTX_CODE code
= GET_CODE (x
);
2718 attach_deaths (SET_SRC (x
), insn
, 0);
2720 /* A register might die here even if it is the destination, e.g.
2721 it is the target of a volatile read and is otherwise unused.
2722 Hence we must always call attach_deaths for the SET_DEST. */
2723 attach_deaths (SET_DEST (x
), insn
, 1);
2725 else if (code
== PARALLEL
)
2728 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2730 code
= GET_CODE (XVECEXP (x
, 0, i
));
2733 attach_deaths (SET_SRC (XVECEXP (x
, 0, i
)), insn
, 0);
2735 attach_deaths (SET_DEST (XVECEXP (x
, 0, i
)), insn
, 1);
2737 /* Flow does not add REG_DEAD notes to registers that die in
2738 clobbers, so we can't either. */
2739 else if (code
!= CLOBBER
)
2740 attach_deaths (XVECEXP (x
, 0, i
), insn
, 0);
2743 /* Flow does not add REG_DEAD notes to registers that die in
2744 clobbers, so we can't either. */
2745 else if (code
!= CLOBBER
)
2746 attach_deaths (x
, insn
, 0);
2749 /* Delete notes beginning with INSN and maybe put them in the chain
2750 of notes ended by NOTE_LIST.
2751 Returns the insn following the notes. */
2754 unlink_notes (insn
, tail
)
2757 rtx prev
= PREV_INSN (insn
);
2759 while (insn
!= tail
&& GET_CODE (insn
) == NOTE
)
2761 rtx next
= NEXT_INSN (insn
);
2762 /* Delete the note from its current position. */
2764 NEXT_INSN (prev
) = next
;
2766 PREV_INSN (next
) = prev
;
2768 if (write_symbols
!= NO_DEBUG
&& NOTE_LINE_NUMBER (insn
) > 0)
2769 /* Record line-number notes so they can be reused. */
2770 LINE_NOTE (insn
) = insn
;
2773 /* Insert the note at the end of the notes list. */
2774 PREV_INSN (insn
) = note_list
;
2776 NEXT_INSN (note_list
) = insn
;
2785 /* Data structure for keeping track of register information
2786 during that register's life. */
2790 short offset
; short bit
;
2791 short live_length
; short calls_crossed
;
2794 /* Constructor for `sometimes' data structure. */
2797 new_sometimes_live (regs_sometimes_live
, offset
, bit
, sometimes_max
)
2798 struct sometimes
*regs_sometimes_live
;
2802 register struct sometimes
*p
;
2803 register int regno
= offset
* REGSET_ELT_BITS
+ bit
;
2806 /* There should never be a register greater than max_regno here. If there
2807 is, it means that a define_split has created a new pseudo reg. This
2808 is not allowed, since there will not be flow info available for any
2809 new register, so catch the error here. */
2810 if (regno
>= max_regno
)
2813 p
= ®s_sometimes_live
[sometimes_max
];
2817 p
->calls_crossed
= 0;
2819 return sometimes_max
;
2822 /* Count lengths of all regs we are currently tracking,
2823 and find new registers no longer live. */
2826 finish_sometimes_live (regs_sometimes_live
, sometimes_max
)
2827 struct sometimes
*regs_sometimes_live
;
2832 for (i
= 0; i
< sometimes_max
; i
++)
2834 register struct sometimes
*p
= ®s_sometimes_live
[i
];
2837 regno
= p
->offset
* REGSET_ELT_BITS
+ p
->bit
;
2839 sched_reg_live_length
[regno
] += p
->live_length
;
2840 sched_reg_n_calls_crossed
[regno
] += p
->calls_crossed
;
2844 /* Use modified list scheduling to rearrange insns in basic block
2845 B. FILE, if nonzero, is where we dump interesting output about
2849 schedule_block (b
, file
)
2856 int i
, j
, n_ready
= 0, new_ready
, n_insns
= 0;
2857 int sched_n_insns
= 0;
2859 #define NEED_NOTHING 0
2864 /* HEAD and TAIL delimit the region being scheduled. */
2865 rtx head
= basic_block_head
[b
];
2866 rtx tail
= basic_block_end
[b
];
2867 /* PREV_HEAD and NEXT_TAIL are the boundaries of the insns
2868 being scheduled. When the insns have been ordered,
2869 these insns delimit where the new insns are to be
2870 spliced back into the insn chain. */
2874 /* Keep life information accurate. */
2875 register struct sometimes
*regs_sometimes_live
;
2879 fprintf (file
, ";;\t -- basic block number %d from %d to %d --\n",
2880 b
, INSN_UID (basic_block_head
[b
]), INSN_UID (basic_block_end
[b
]));
2883 reg_last_uses
= (rtx
*) alloca (i
* sizeof (rtx
));
2884 bzero (reg_last_uses
, i
* sizeof (rtx
));
2885 reg_last_sets
= (rtx
*) alloca (i
* sizeof (rtx
));
2886 bzero (reg_last_sets
, i
* sizeof (rtx
));
2889 /* Remove certain insns at the beginning from scheduling,
2890 by advancing HEAD. */
2892 /* At the start of a function, before reload has run, don't delay getting
2893 parameters from hard registers into pseudo registers. */
2894 if (reload_completed
== 0 && b
== 0)
2897 && GET_CODE (head
) == NOTE
2898 && NOTE_LINE_NUMBER (head
) != NOTE_INSN_FUNCTION_BEG
)
2899 head
= NEXT_INSN (head
);
2901 && GET_CODE (head
) == INSN
2902 && GET_CODE (PATTERN (head
)) == SET
)
2904 rtx src
= SET_SRC (PATTERN (head
));
2905 while (GET_CODE (src
) == SUBREG
2906 || GET_CODE (src
) == SIGN_EXTEND
2907 || GET_CODE (src
) == ZERO_EXTEND
2908 || GET_CODE (src
) == SIGN_EXTRACT
2909 || GET_CODE (src
) == ZERO_EXTRACT
)
2910 src
= XEXP (src
, 0);
2911 if (GET_CODE (src
) != REG
2912 || REGNO (src
) >= FIRST_PSEUDO_REGISTER
)
2914 /* Keep this insn from ever being scheduled. */
2915 INSN_REF_COUNT (head
) = 1;
2916 head
= NEXT_INSN (head
);
2920 /* Don't include any notes or labels at the beginning of the
2921 basic block, or notes at the ends of basic blocks. */
2922 while (head
!= tail
)
2924 if (GET_CODE (head
) == NOTE
)
2925 head
= NEXT_INSN (head
);
2926 else if (GET_CODE (tail
) == NOTE
)
2927 tail
= PREV_INSN (tail
);
2928 else if (GET_CODE (head
) == CODE_LABEL
)
2929 head
= NEXT_INSN (head
);
2932 /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
2933 to schedule this block. */
2935 && (GET_CODE (head
) == NOTE
|| GET_CODE (head
) == CODE_LABEL
))
2939 /* This short-cut doesn't work. It does not count call insns crossed by
2940 registers in reg_sometimes_live. It does not mark these registers as
2941 dead if they die in this block. It does not mark these registers live
2942 (or create new reg_sometimes_live entries if necessary) if they are born
2945 The easy solution is to just always schedule a block. This block only
2946 has one insn, so this won't slow down this pass by much. */
2952 /* Now HEAD through TAIL are the insns actually to be rearranged;
2953 Let PREV_HEAD and NEXT_TAIL enclose them. */
2954 prev_head
= PREV_INSN (head
);
2955 next_tail
= NEXT_INSN (tail
);
2957 /* Initialize basic block data structures. */
2959 pending_read_insns
= 0;
2960 pending_read_mems
= 0;
2961 pending_write_insns
= 0;
2962 pending_write_mems
= 0;
2963 pending_lists_length
= 0;
2964 last_pending_memory_flush
= 0;
2965 last_function_call
= 0;
2966 last_scheduled_insn
= 0;
2968 LOG_LINKS (sched_before_next_call
) = 0;
2970 n_insns
+= sched_analyze (head
, tail
);
2973 free_pending_lists ();
2977 /* Allocate vector to hold insns to be rearranged (except those
2978 insns which are controlled by an insn with SCHED_GROUP_P set).
2979 All these insns are included between ORIG_HEAD and ORIG_TAIL,
2980 as those variables ultimately are set up. */
2981 ready
= (rtx
*) alloca ((n_insns
+1) * sizeof (rtx
));
2983 /* TAIL is now the last of the insns to be rearranged.
2984 Put those insns into the READY vector. */
2987 /* For all branches, calls, uses, and cc0 setters, force them to remain
2988 in order at the end of the block by adding dependencies and giving
2989 the last a high priority. There may be notes present, and prev_head
2992 Branches must obviously remain at the end. Calls should remain at the
2993 end since moving them results in worse register allocation. Uses remain
2994 at the end to ensure proper register allocation. cc0 setters remaim
2995 at the end because they can't be moved away from their cc0 user. */
2997 while (GET_CODE (insn
) == CALL_INSN
|| GET_CODE (insn
) == JUMP_INSN
2998 || (GET_CODE (insn
) == INSN
2999 && (GET_CODE (PATTERN (insn
)) == USE
3001 || sets_cc0_p (PATTERN (insn
))
3004 || GET_CODE (insn
) == NOTE
)
3006 if (GET_CODE (insn
) != NOTE
)
3011 ready
[n_ready
++] = insn
;
3012 INSN_PRIORITY (insn
) = TAIL_PRIORITY
- i
;
3013 INSN_REF_COUNT (insn
) = 0;
3015 else if (! find_insn_list (insn
, LOG_LINKS (last
)))
3017 add_dependence (last
, insn
, REG_DEP_ANTI
);
3018 INSN_REF_COUNT (insn
)++;
3022 /* Skip over insns that are part of a group. */
3023 while (SCHED_GROUP_P (insn
))
3025 insn
= prev_nonnote_insn (insn
);
3030 insn
= PREV_INSN (insn
);
3031 /* Don't overrun the bounds of the basic block. */
3032 if (insn
== prev_head
)
3036 /* Assign priorities to instructions. Also check whether they
3037 are in priority order already. If so then I will be nonnegative.
3038 We use this shortcut only before reloading. */
3040 i
= reload_completed
? DONE_PRIORITY
: MAX_PRIORITY
;
3043 for (; insn
!= prev_head
; insn
= PREV_INSN (insn
))
3045 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
3048 if (INSN_REF_COUNT (insn
) == 0)
3051 ready
[n_ready
++] = insn
;
3054 /* Make this dependent on the last of the instructions
3055 that must remain in order at the end of the block. */
3056 add_dependence (last
, insn
, REG_DEP_ANTI
);
3057 INSN_REF_COUNT (insn
) = 1;
3060 if (SCHED_GROUP_P (insn
))
3062 while (SCHED_GROUP_P (insn
))
3064 insn
= PREV_INSN (insn
);
3065 while (GET_CODE (insn
) == NOTE
)
3066 insn
= PREV_INSN (insn
);
3074 if (INSN_PRIORITY (insn
) < i
)
3075 i
= INSN_PRIORITY (insn
);
3076 else if (INSN_PRIORITY (insn
) > i
)
3083 /* This short-cut doesn't work. It does not count call insns crossed by
3084 registers in reg_sometimes_live. It does not mark these registers as
3085 dead if they die in this block. It does not mark these registers live
3086 (or create new reg_sometimes_live entries if necessary) if they are born
3089 The easy solution is to just always schedule a block. These blocks tend
3090 to be very short, so this doesn't slow down this pass by much. */
3092 /* If existing order is good, don't bother to reorder. */
3093 if (i
!= DONE_PRIORITY
)
3096 fprintf (file
, ";; already scheduled\n");
3098 if (reload_completed
== 0)
3100 for (i
= 0; i
< sometimes_max
; i
++)
3101 regs_sometimes_live
[i
].live_length
+= n_insns
;
3103 finish_sometimes_live (regs_sometimes_live
, sometimes_max
);
3105 free_pending_lists ();
3110 /* Scan all the insns to be scheduled, removing NOTE insns
3111 and register death notes.
3112 Line number NOTE insns end up in NOTE_LIST.
3113 Register death notes end up in DEAD_NOTES.
3115 Recreate the register life information for the end of this basic
3118 if (reload_completed
== 0)
3120 bcopy (basic_block_live_at_start
[b
], bb_live_regs
, regset_bytes
);
3121 bzero (bb_dead_regs
, regset_bytes
);
3125 /* This is the first block in the function. There may be insns
3126 before head that we can't schedule. We still need to examine
3127 them though for accurate register lifetime analysis. */
3129 /* We don't want to remove any REG_DEAD notes as the code below
3132 for (insn
= basic_block_head
[b
]; insn
!= head
;
3133 insn
= NEXT_INSN (insn
))
3134 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
3136 /* See if the register gets born here. */
3137 /* We must check for registers being born before we check for
3138 registers dying. It is possible for a register to be born
3139 and die in the same insn, e.g. reading from a volatile
3140 memory location into an otherwise unused register. Such
3141 a register must be marked as dead after this insn. */
3142 if (GET_CODE (PATTERN (insn
)) == SET
3143 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3144 sched_note_set (b
, PATTERN (insn
), 0);
3145 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
3148 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
3149 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == SET
3150 || GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == CLOBBER
)
3151 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 0);
3153 /* ??? This code is obsolete and should be deleted. It
3154 is harmless though, so we will leave it in for now. */
3155 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
3156 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == USE
)
3157 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 0);
3160 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
3162 if ((REG_NOTE_KIND (link
) == REG_DEAD
3163 || REG_NOTE_KIND (link
) == REG_UNUSED
)
3164 /* Verify that the REG_NOTE has a legal value. */
3165 && GET_CODE (XEXP (link
, 0)) == REG
)
3167 register int regno
= REGNO (XEXP (link
, 0));
3168 register int offset
= regno
/ REGSET_ELT_BITS
;
3169 register REGSET_ELT_TYPE bit
3170 = (REGSET_ELT_TYPE
) 1 << (regno
% REGSET_ELT_BITS
);
3172 if (regno
< FIRST_PSEUDO_REGISTER
)
3174 int j
= HARD_REGNO_NREGS (regno
,
3175 GET_MODE (XEXP (link
, 0)));
3178 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
3179 bit
= ((REGSET_ELT_TYPE
) 1
3180 << ((regno
+ j
) % REGSET_ELT_BITS
));
3182 bb_live_regs
[offset
] &= ~bit
;
3183 bb_dead_regs
[offset
] |= bit
;
3188 bb_live_regs
[offset
] &= ~bit
;
3189 bb_dead_regs
[offset
] |= bit
;
3197 /* If debugging information is being produced, keep track of the line
3198 number notes for each insn. */
3199 if (write_symbols
!= NO_DEBUG
)
3201 /* We must use the true line number for the first insn in the block
3202 that was computed and saved at the start of this pass. We can't
3203 use the current line number, because scheduling of the previous
3204 block may have changed the current line number. */
3205 rtx line
= line_note_head
[b
];
3207 for (insn
= basic_block_head
[b
];
3209 insn
= NEXT_INSN (insn
))
3210 if (GET_CODE (insn
) == NOTE
&& NOTE_LINE_NUMBER (insn
) > 0)
3213 LINE_NOTE (insn
) = line
;
3216 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
3218 rtx prev
, next
, link
;
3220 /* Farm out notes. This is needed to keep the debugger from
3221 getting completely deranged. */
3222 if (GET_CODE (insn
) == NOTE
)
3225 insn
= unlink_notes (insn
, next_tail
);
3230 if (insn
== next_tail
)
3234 if (reload_completed
== 0
3235 && GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
3237 /* See if the register gets born here. */
3238 /* We must check for registers being born before we check for
3239 registers dying. It is possible for a register to be born and
3240 die in the same insn, e.g. reading from a volatile memory
3241 location into an otherwise unused register. Such a register
3242 must be marked as dead after this insn. */
3243 if (GET_CODE (PATTERN (insn
)) == SET
3244 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3245 sched_note_set (b
, PATTERN (insn
), 0);
3246 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
3249 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
3250 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == SET
3251 || GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == CLOBBER
)
3252 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 0);
3254 /* ??? This code is obsolete and should be deleted. It
3255 is harmless though, so we will leave it in for now. */
3256 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
3257 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == USE
)
3258 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 0);
3261 /* Need to know what registers this insn kills. */
3262 for (prev
= 0, link
= REG_NOTES (insn
); link
; link
= next
)
3266 next
= XEXP (link
, 1);
3267 if ((REG_NOTE_KIND (link
) == REG_DEAD
3268 || REG_NOTE_KIND (link
) == REG_UNUSED
)
3269 /* Verify that the REG_NOTE has a legal value. */
3270 && GET_CODE (XEXP (link
, 0)) == REG
)
3272 register int regno
= REGNO (XEXP (link
, 0));
3273 register int offset
= regno
/ REGSET_ELT_BITS
;
3274 register REGSET_ELT_TYPE bit
3275 = (REGSET_ELT_TYPE
) 1 << (regno
% REGSET_ELT_BITS
);
3277 /* Only unlink REG_DEAD notes; leave REG_UNUSED notes
3279 if (REG_NOTE_KIND (link
) == REG_DEAD
)
3282 XEXP (prev
, 1) = next
;
3284 REG_NOTES (insn
) = next
;
3285 XEXP (link
, 1) = dead_notes
;
3291 if (regno
< FIRST_PSEUDO_REGISTER
)
3293 int j
= HARD_REGNO_NREGS (regno
,
3294 GET_MODE (XEXP (link
, 0)));
3297 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
3298 bit
= ((REGSET_ELT_TYPE
) 1
3299 << ((regno
+ j
) % REGSET_ELT_BITS
));
3301 bb_live_regs
[offset
] &= ~bit
;
3302 bb_dead_regs
[offset
] |= bit
;
3307 bb_live_regs
[offset
] &= ~bit
;
3308 bb_dead_regs
[offset
] |= bit
;
3317 if (reload_completed
== 0)
3319 /* Keep track of register lives. */
3320 old_live_regs
= (regset
) alloca (regset_bytes
);
3322 = (struct sometimes
*) alloca (max_regno
* sizeof (struct sometimes
));
3325 /* Start with registers live at end. */
3326 for (j
= 0; j
< regset_size
; j
++)
3328 REGSET_ELT_TYPE live
= bb_live_regs
[j
];
3329 old_live_regs
[j
] = live
;
3332 register REGSET_ELT_TYPE bit
;
3333 for (bit
= 0; bit
< REGSET_ELT_BITS
; bit
++)
3334 if (live
& ((REGSET_ELT_TYPE
) 1 << bit
))
3335 sometimes_max
= new_sometimes_live (regs_sometimes_live
, j
,
3336 bit
, sometimes_max
);
3341 SCHED_SORT (ready
, n_ready
, 1);
3345 fprintf (file
, ";; ready list initially:\n;; ");
3346 for (i
= 0; i
< n_ready
; i
++)
3347 fprintf (file
, "%d ", INSN_UID (ready
[i
]));
3348 fprintf (file
, "\n\n");
3350 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
3351 if (INSN_PRIORITY (insn
) > 0)
3352 fprintf (file
, ";; insn[%4d]: priority = %4d, ref_count = %4d\n",
3353 INSN_UID (insn
), INSN_PRIORITY (insn
),
3354 INSN_REF_COUNT (insn
));
3357 /* Now HEAD and TAIL are going to become disconnected
3358 entirely from the insn chain. */
3361 /* Q_SIZE will always be zero here. */
3362 q_ptr
= 0; clock
= 0;
3363 bzero (insn_queue
, sizeof (insn_queue
));
3365 /* Now, perform list scheduling. */
3367 /* Where we start inserting insns is after TAIL. */
3370 new_needs
= (NEXT_INSN (prev_head
) == basic_block_head
[b
]
3371 ? NEED_HEAD
: NEED_NOTHING
);
3372 if (PREV_INSN (next_tail
) == basic_block_end
[b
])
3373 new_needs
|= NEED_TAIL
;
3375 new_ready
= n_ready
;
3376 while (sched_n_insns
< n_insns
)
3378 q_ptr
= NEXT_Q (q_ptr
); clock
++;
3380 /* Add all pending insns that can be scheduled without stalls to the
3382 for (insn
= insn_queue
[q_ptr
]; insn
; insn
= NEXT_INSN (insn
))
3385 fprintf (file
, ";; launching %d before %d with no stalls at T-%d\n",
3386 INSN_UID (insn
), INSN_UID (last
), clock
);
3387 ready
[new_ready
++] = insn
;
3390 insn_queue
[q_ptr
] = 0;
3392 /* If there are no ready insns, stall until one is ready and add all
3393 of the pending insns at that point to the ready list. */
3396 register int stalls
;
3398 for (stalls
= 1; stalls
< INSN_QUEUE_SIZE
; stalls
++)
3399 if (insn
= insn_queue
[NEXT_Q_AFTER (q_ptr
, stalls
)])
3401 for (; insn
; insn
= NEXT_INSN (insn
))
3404 fprintf (file
, ";; launching %d before %d with %d stalls at T-%d\n",
3405 INSN_UID (insn
), INSN_UID (last
), stalls
, clock
);
3406 ready
[new_ready
++] = insn
;
3409 insn_queue
[NEXT_Q_AFTER (q_ptr
, stalls
)] = 0;
3413 q_ptr
= NEXT_Q_AFTER (q_ptr
, stalls
); clock
+= stalls
;
3416 /* There should be some instructions waiting to fire. */
3422 fprintf (file
, ";; ready list at T-%d:", clock
);
3423 for (i
= 0; i
< new_ready
; i
++)
3424 fprintf (file
, " %d (%x)",
3425 INSN_UID (ready
[i
]), INSN_PRIORITY (ready
[i
]));
3428 /* Sort the ready list and choose the best insn to schedule. Select
3429 which insn should issue in this cycle and queue those that are
3430 blocked by function unit hazards.
3432 N_READY holds the number of items that were scheduled the last time,
3433 minus the one instruction scheduled on the last loop iteration; it
3434 is not modified for any other reason in this loop. */
3436 SCHED_SORT (ready
, new_ready
, n_ready
);
3437 if (MAX_BLOCKAGE
> 1)
3439 new_ready
= schedule_select (ready
, new_ready
, clock
, file
);
3443 fprintf (file
, "\n");
3444 /* We must set n_ready here, to ensure that sorting always
3445 occurs when we come back to the SCHED_SORT line above. */
3450 n_ready
= new_ready
;
3451 last_scheduled_insn
= insn
= ready
[0];
3453 /* The first insn scheduled becomes the new tail. */
3459 fprintf (file
, ", now");
3460 for (i
= 0; i
< n_ready
; i
++)
3461 fprintf (file
, " %d", INSN_UID (ready
[i
]));
3462 fprintf (file
, "\n");
3465 if (DONE_PRIORITY_P (insn
))
3468 if (reload_completed
== 0)
3470 /* Process this insn, and each insn linked to this one which must
3471 be immediately output after this insn. */
3474 /* First we kill registers set by this insn, and then we
3475 make registers used by this insn live. This is the opposite
3476 order used above because we are traversing the instructions
3479 /* Strictly speaking, we should scan REG_UNUSED notes and make
3480 every register mentioned there live, however, we will just
3481 kill them again immediately below, so there doesn't seem to
3482 be any reason why we bother to do this. */
3484 /* See if this is the last notice we must take of a register. */
3485 if (GET_CODE (PATTERN (insn
)) == SET
3486 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3487 sched_note_set (b
, PATTERN (insn
), 1);
3488 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
3491 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
3492 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == SET
3493 || GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == CLOBBER
)
3494 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 1);
3497 /* This code keeps life analysis information up to date. */
3498 if (GET_CODE (insn
) == CALL_INSN
)
3500 register struct sometimes
*p
;
3502 /* A call kills all call used and global registers, except
3503 for those mentioned in the call pattern which will be
3504 made live again later. */
3505 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3506 if (call_used_regs
[i
] || global_regs
[i
])
3508 register int offset
= i
/ REGSET_ELT_BITS
;
3509 register REGSET_ELT_TYPE bit
3510 = (REGSET_ELT_TYPE
) 1 << (i
% REGSET_ELT_BITS
);
3512 bb_live_regs
[offset
] &= ~bit
;
3513 bb_dead_regs
[offset
] |= bit
;
3516 /* Regs live at the time of a call instruction must not
3517 go in a register clobbered by calls. Record this for
3518 all regs now live. Note that insns which are born or
3519 die in a call do not cross a call, so this must be done
3520 after the killings (above) and before the births
3522 p
= regs_sometimes_live
;
3523 for (i
= 0; i
< sometimes_max
; i
++, p
++)
3524 if (bb_live_regs
[p
->offset
]
3525 & ((REGSET_ELT_TYPE
) 1 << p
->bit
))
3526 p
->calls_crossed
+= 1;
3529 /* Make every register used live, and add REG_DEAD notes for
3530 registers which were not live before we started. */
3531 attach_deaths_insn (insn
);
3533 /* Find registers now made live by that instruction. */
3534 for (i
= 0; i
< regset_size
; i
++)
3536 REGSET_ELT_TYPE diff
= bb_live_regs
[i
] & ~old_live_regs
[i
];
3540 old_live_regs
[i
] |= diff
;
3541 for (bit
= 0; bit
< REGSET_ELT_BITS
; bit
++)
3542 if (diff
& ((REGSET_ELT_TYPE
) 1 << bit
))
3544 = new_sometimes_live (regs_sometimes_live
, i
, bit
,
3549 /* Count lengths of all regs we are worrying about now,
3550 and handle registers no longer live. */
3552 for (i
= 0; i
< sometimes_max
; i
++)
3554 register struct sometimes
*p
= ®s_sometimes_live
[i
];
3555 int regno
= p
->offset
*REGSET_ELT_BITS
+ p
->bit
;
3557 p
->live_length
+= 1;
3559 if ((bb_live_regs
[p
->offset
]
3560 & ((REGSET_ELT_TYPE
) 1 << p
->bit
)) == 0)
3562 /* This is the end of one of this register's lifetime
3563 segments. Save the lifetime info collected so far,
3564 and clear its bit in the old_live_regs entry. */
3565 sched_reg_live_length
[regno
] += p
->live_length
;
3566 sched_reg_n_calls_crossed
[regno
] += p
->calls_crossed
;
3567 old_live_regs
[p
->offset
]
3568 &= ~((REGSET_ELT_TYPE
) 1 << p
->bit
);
3570 /* Delete the reg_sometimes_live entry for this reg by
3571 copying the last entry over top of it. */
3572 *p
= regs_sometimes_live
[--sometimes_max
];
3573 /* ...and decrement i so that this newly copied entry
3574 will be processed. */
3580 insn
= PREV_INSN (insn
);
3582 while (SCHED_GROUP_P (link
));
3584 /* Set INSN back to the insn we are scheduling now. */
3588 /* Schedule INSN. Remove it from the ready list. */
3593 NEXT_INSN (insn
) = last
;
3594 PREV_INSN (last
) = insn
;
3597 /* Everything that precedes INSN now either becomes "ready", if
3598 it can execute immediately before INSN, or "pending", if
3599 there must be a delay. Give INSN high enough priority that
3600 at least one (maybe more) reg-killing insns can be launched
3601 ahead of all others. Mark INSN as scheduled by changing its
3603 INSN_PRIORITY (insn
) = LAUNCH_PRIORITY
;
3604 new_ready
= schedule_insn (insn
, ready
, n_ready
, clock
);
3605 INSN_PRIORITY (insn
) = DONE_PRIORITY
;
3607 /* Schedule all prior insns that must not be moved. */
3608 if (SCHED_GROUP_P (insn
))
3610 /* Disable these insns from being launched. */
3612 while (SCHED_GROUP_P (link
))
3614 /* Disable these insns from being launched by anybody. */
3615 link
= PREV_INSN (link
);
3616 INSN_REF_COUNT (link
) = 0;
3619 /* None of these insns can move forward into delay slots. */
3620 while (SCHED_GROUP_P (insn
))
3622 insn
= PREV_INSN (insn
);
3623 new_ready
= schedule_insn (insn
, ready
, new_ready
, clock
);
3624 INSN_PRIORITY (insn
) = DONE_PRIORITY
;
3627 NEXT_INSN (insn
) = last
;
3628 PREV_INSN (last
) = insn
;
3636 if (reload_completed
== 0)
3637 finish_sometimes_live (regs_sometimes_live
, sometimes_max
);
3639 /* HEAD is now the first insn in the chain of insns that
3640 been scheduled by the loop above.
3641 TAIL is the last of those insns. */
3644 /* NOTE_LIST is the end of a chain of notes previously found
3645 among the insns. Insert them at the beginning of the insns. */
3648 rtx note_head
= note_list
;
3649 while (PREV_INSN (note_head
))
3650 note_head
= PREV_INSN (note_head
);
3652 PREV_INSN (head
) = note_list
;
3653 NEXT_INSN (note_list
) = head
;
3657 /* In theory, there should be no REG_DEAD notes leftover at the end.
3658 In practice, this can occur as the result of bugs in flow, combine.c,
3659 and/or sched.c. The values of the REG_DEAD notes remaining are
3660 meaningless, because dead_notes is just used as a free list. */
3662 if (dead_notes
!= 0)
3666 if (new_needs
& NEED_HEAD
)
3667 basic_block_head
[b
] = head
;
3668 PREV_INSN (head
) = prev_head
;
3669 NEXT_INSN (prev_head
) = head
;
3671 if (new_needs
& NEED_TAIL
)
3672 basic_block_end
[b
] = tail
;
3673 NEXT_INSN (tail
) = next_tail
;
3674 PREV_INSN (next_tail
) = tail
;
3676 /* Restore the line-number notes of each insn. */
3677 if (write_symbols
!= NO_DEBUG
)
3679 rtx line
, note
, prev
, new;
3682 head
= basic_block_head
[b
];
3683 next_tail
= NEXT_INSN (basic_block_end
[b
]);
3685 /* Determine the current line-number. We want to know the current
3686 line number of the first insn of the block here, in case it is
3687 different from the true line number that was saved earlier. If
3688 different, then we need a line number note before the first insn
3689 of this block. If it happens to be the same, then we don't want to
3690 emit another line number note here. */
3691 for (line
= head
; line
; line
= PREV_INSN (line
))
3692 if (GET_CODE (line
) == NOTE
&& NOTE_LINE_NUMBER (line
) > 0)
3695 /* Walk the insns keeping track of the current line-number and inserting
3696 the line-number notes as needed. */
3697 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
3698 if (GET_CODE (insn
) == NOTE
&& NOTE_LINE_NUMBER (insn
) > 0)
3700 else if (! (GET_CODE (insn
) == NOTE
3701 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_DELETED
)
3702 && (note
= LINE_NOTE (insn
)) != 0
3705 || NOTE_LINE_NUMBER (note
) != NOTE_LINE_NUMBER (line
)
3706 || NOTE_SOURCE_FILE (note
) != NOTE_SOURCE_FILE (line
)))
3709 prev
= PREV_INSN (insn
);
3710 if (LINE_NOTE (note
))
3712 /* Re-use the original line-number note. */
3713 LINE_NOTE (note
) = 0;
3714 PREV_INSN (note
) = prev
;
3715 NEXT_INSN (prev
) = note
;
3716 PREV_INSN (insn
) = note
;
3717 NEXT_INSN (note
) = insn
;
3722 new = emit_note_after (NOTE_LINE_NUMBER (note
), prev
);
3723 NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note
);
3727 fprintf (file
, ";; added %d line-number notes\n", notes
);
3732 fprintf (file
, ";; total time = %d\n;; new basic block head = %d\n;; new basic block end = %d\n\n",
3733 clock
, INSN_UID (basic_block_head
[b
]), INSN_UID (basic_block_end
[b
]));
3736 /* Yow! We're done! */
3737 free_pending_lists ();
3742 /* Subroutine of split_hard_reg_notes. Searches X for any reference to
3743 REGNO, returning the rtx of the reference found if any. Otherwise,
3747 regno_use_in (regno
, x
)
3755 if (GET_CODE (x
) == REG
&& REGNO (x
) == regno
)
3758 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3759 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3763 if (tem
= regno_use_in (regno
, XEXP (x
, i
)))
3766 else if (fmt
[i
] == 'E')
3767 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3768 if (tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
)))
3775 /* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are
3776 needed for the hard register mentioned in the note. This can happen
3777 if the reference to the hard register in the original insn was split into
3778 several smaller hard register references in the split insns. */
3781 split_hard_reg_notes (note
, first
, last
, orig_insn
)
3782 rtx note
, first
, last
, orig_insn
;
3784 rtx reg
, temp
, link
;
3785 int n_regs
, i
, new_reg
;
3788 /* Assume that this is a REG_DEAD note. */
3789 if (REG_NOTE_KIND (note
) != REG_DEAD
)
3792 reg
= XEXP (note
, 0);
3794 n_regs
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
3796 /* ??? Could add check here to see whether, the hard register is referenced
3797 in the same mode as in the original insn. If so, then it has not been
3798 split, and the rest of the code below is unnecessary. */
3800 for (i
= 1; i
< n_regs
; i
++)
3802 new_reg
= REGNO (reg
) + i
;
3804 /* Check for references to new_reg in the split insns. */
3805 for (insn
= last
; ; insn
= PREV_INSN (insn
))
3807 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
3808 && (temp
= regno_use_in (new_reg
, PATTERN (insn
))))
3810 /* Create a new reg dead note here. */
3811 link
= rtx_alloc (EXPR_LIST
);
3812 PUT_REG_NOTE_KIND (link
, REG_DEAD
);
3813 XEXP (link
, 0) = temp
;
3814 XEXP (link
, 1) = REG_NOTES (insn
);
3815 REG_NOTES (insn
) = link
;
3818 /* It isn't mentioned anywhere, so no new reg note is needed for
3826 /* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an
3827 insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */
3830 new_insn_dead_notes (pat
, insn
, last
, orig_insn
)
3831 rtx pat
, insn
, last
, orig_insn
;
3835 /* PAT is either a CLOBBER or a SET here. */
3836 dest
= XEXP (pat
, 0);
3838 while (GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SUBREG
3839 || GET_CODE (dest
) == STRICT_LOW_PART
3840 || GET_CODE (dest
) == SIGN_EXTRACT
)
3841 dest
= XEXP (dest
, 0);
3843 if (GET_CODE (dest
) == REG
)
3845 for (tem
= last
; tem
!= insn
; tem
= PREV_INSN (tem
))
3847 if (GET_RTX_CLASS (GET_CODE (tem
)) == 'i'
3848 && reg_overlap_mentioned_p (dest
, PATTERN (tem
))
3849 && (set
= single_set (tem
)))
3851 rtx tem_dest
= SET_DEST (set
);
3853 while (GET_CODE (tem_dest
) == ZERO_EXTRACT
3854 || GET_CODE (tem_dest
) == SUBREG
3855 || GET_CODE (tem_dest
) == STRICT_LOW_PART
3856 || GET_CODE (tem_dest
) == SIGN_EXTRACT
)
3857 tem_dest
= XEXP (tem_dest
, 0);
3859 if (tem_dest
!= dest
)
3861 /* Use the same scheme as combine.c, don't put both REG_DEAD
3862 and REG_UNUSED notes on the same insn. */
3863 if (! find_regno_note (tem
, REG_UNUSED
, REGNO (dest
))
3864 && ! find_regno_note (tem
, REG_DEAD
, REGNO (dest
)))
3866 rtx note
= rtx_alloc (EXPR_LIST
);
3867 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
3868 XEXP (note
, 0) = dest
;
3869 XEXP (note
, 1) = REG_NOTES (tem
);
3870 REG_NOTES (tem
) = note
;
3872 /* The reg only dies in one insn, the last one that uses
3876 else if (reg_overlap_mentioned_p (dest
, SET_SRC (set
)))
3877 /* We found an instruction that both uses the register,
3878 and sets it, so no new REG_NOTE is needed for this set. */
3882 /* If this is a set, it must die somewhere, unless it is the dest of
3883 the original insn, and hence is live after the original insn. Abort
3884 if it isn't supposed to be live after the original insn.
3886 If this is a clobber, then just add a REG_UNUSED note. */
3889 int live_after_orig_insn
= 0;
3890 rtx pattern
= PATTERN (orig_insn
);
3893 if (GET_CODE (pat
) == CLOBBER
)
3895 rtx note
= rtx_alloc (EXPR_LIST
);
3896 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
3897 XEXP (note
, 0) = dest
;
3898 XEXP (note
, 1) = REG_NOTES (insn
);
3899 REG_NOTES (insn
) = note
;
3903 /* The original insn could have multiple sets, so search the
3904 insn for all sets. */
3905 if (GET_CODE (pattern
) == SET
)
3907 if (reg_overlap_mentioned_p (dest
, SET_DEST (pattern
)))
3908 live_after_orig_insn
= 1;
3910 else if (GET_CODE (pattern
) == PARALLEL
)
3912 for (i
= 0; i
< XVECLEN (pattern
, 0); i
++)
3913 if (GET_CODE (XVECEXP (pattern
, 0, i
)) == SET
3914 && reg_overlap_mentioned_p (dest
,
3915 SET_DEST (XVECEXP (pattern
,
3917 live_after_orig_insn
= 1;
3920 if (! live_after_orig_insn
)
3926 /* Subroutine of update_flow_info. Update the value of reg_n_sets for all
3927 registers modified by X. INC is -1 if the containing insn is being deleted,
3928 and is 1 if the containing insn is a newly generated insn. */
3931 update_n_sets (x
, inc
)
3935 rtx dest
= SET_DEST (x
);
3937 while (GET_CODE (dest
) == STRICT_LOW_PART
|| GET_CODE (dest
) == SUBREG
3938 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SIGN_EXTRACT
)
3939 dest
= SUBREG_REG (dest
);
3941 if (GET_CODE (dest
) == REG
)
3943 int regno
= REGNO (dest
);
3945 if (regno
< FIRST_PSEUDO_REGISTER
)
3948 int endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (dest
));
3950 for (i
= regno
; i
< endregno
; i
++)
3951 reg_n_sets
[i
] += inc
;
3954 reg_n_sets
[regno
] += inc
;
3958 /* Updates all flow-analysis related quantities (including REG_NOTES) for
3959 the insns from FIRST to LAST inclusive that were created by splitting
3960 ORIG_INSN. NOTES are the original REG_NOTES. */
3963 update_flow_info (notes
, first
, last
, orig_insn
)
3970 rtx orig_dest
, temp
;
3973 /* Get and save the destination set by the original insn. */
3975 orig_dest
= single_set (orig_insn
);
3977 orig_dest
= SET_DEST (orig_dest
);
3979 /* Move REG_NOTES from the original insn to where they now belong. */
3981 for (note
= notes
; note
; note
= next
)
3983 next
= XEXP (note
, 1);
3984 switch (REG_NOTE_KIND (note
))
3988 /* Move these notes from the original insn to the last new insn where
3989 the register is now set. */
3991 for (insn
= last
; ; insn
= PREV_INSN (insn
))
3993 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
3994 && reg_mentioned_p (XEXP (note
, 0), PATTERN (insn
)))
3996 XEXP (note
, 1) = REG_NOTES (insn
);
3997 REG_NOTES (insn
) = note
;
3999 /* Sometimes need to convert REG_UNUSED notes to REG_DEAD
4001 /* ??? This won't handle multiple word registers correctly,
4002 but should be good enough for now. */
4003 if (REG_NOTE_KIND (note
) == REG_UNUSED
4004 && ! dead_or_set_p (insn
, XEXP (note
, 0)))
4005 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
4007 /* The reg only dies in one insn, the last one that uses
4011 /* It must die somewhere, fail it we couldn't find where it died.
4013 If this is a REG_UNUSED note, then it must be a temporary
4014 register that was not needed by this instantiation of the
4015 pattern, so we can safely ignore it. */
4018 if (REG_NOTE_KIND (note
) != REG_UNUSED
)
4025 /* If this note refers to a multiple word hard register, it may
4026 have been split into several smaller hard register references.
4027 Check to see if there are any new register references that
4028 need REG_NOTES added for them. */
4029 temp
= XEXP (note
, 0);
4030 if (REG_NOTE_KIND (note
) == REG_DEAD
4031 && GET_CODE (temp
) == REG
4032 && REGNO (temp
) < FIRST_PSEUDO_REGISTER
4033 && HARD_REGNO_NREGS (REGNO (temp
), GET_MODE (temp
)))
4034 split_hard_reg_notes (note
, first
, last
, orig_insn
);
4038 /* This note applies to the dest of the original insn. Find the
4039 first new insn that now has the same dest, and move the note
4045 for (insn
= first
; ; insn
= NEXT_INSN (insn
))
4047 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
4048 && (temp
= single_set (insn
))
4049 && rtx_equal_p (SET_DEST (temp
), orig_dest
))
4051 XEXP (note
, 1) = REG_NOTES (insn
);
4052 REG_NOTES (insn
) = note
;
4053 /* The reg is only zero before one insn, the first that
4057 /* It must be set somewhere, fail if we couldn't find where it
4066 /* A REG_EQUIV or REG_EQUAL note on an insn with more than one
4067 set is meaningless. Just drop the note. */
4071 case REG_NO_CONFLICT
:
4072 /* These notes apply to the dest of the original insn. Find the last
4073 new insn that now has the same dest, and move the note there. */
4078 for (insn
= last
; ; insn
= PREV_INSN (insn
))
4080 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
4081 && (temp
= single_set (insn
))
4082 && rtx_equal_p (SET_DEST (temp
), orig_dest
))
4084 XEXP (note
, 1) = REG_NOTES (insn
);
4085 REG_NOTES (insn
) = note
;
4086 /* Only put this note on one of the new insns. */
4090 /* The original dest must still be set someplace. Abort if we
4091 couldn't find it. */
4098 /* Move a REG_LIBCALL note to the first insn created, and update
4099 the corresponding REG_RETVAL note. */
4100 XEXP (note
, 1) = REG_NOTES (first
);
4101 REG_NOTES (first
) = note
;
4103 insn
= XEXP (note
, 0);
4104 note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
);
4106 XEXP (note
, 0) = first
;
4110 /* Move a REG_RETVAL note to the last insn created, and update
4111 the corresponding REG_LIBCALL note. */
4112 XEXP (note
, 1) = REG_NOTES (last
);
4113 REG_NOTES (last
) = note
;
4115 insn
= XEXP (note
, 0);
4116 note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
4118 XEXP (note
, 0) = last
;
4122 /* This should be moved to whichever instruction is a JUMP_INSN. */
4124 for (insn
= last
; ; insn
= PREV_INSN (insn
))
4126 if (GET_CODE (insn
) == JUMP_INSN
)
4128 XEXP (note
, 1) = REG_NOTES (insn
);
4129 REG_NOTES (insn
) = note
;
4130 /* Only put this note on one of the new insns. */
4133 /* Fail if we couldn't find a JUMP_INSN. */
4140 /* This should be moved to whichever instruction now has the
4141 increment operation. */
4145 /* Should be moved to the new insn(s) which use the label. */
4146 for (insn
= first
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
4147 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
4148 && reg_mentioned_p (XEXP (note
, 0), PATTERN (insn
)))
4149 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_LABEL
,
4150 XEXP (note
, 0), REG_NOTES (insn
));
4155 /* These two notes will never appear until after reorg, so we don't
4156 have to handle them here. */
4162 /* Each new insn created, except the last, has a new set. If the destination
4163 is a register, then this reg is now live across several insns, whereas
4164 previously the dest reg was born and died within the same insn. To
4165 reflect this, we now need a REG_DEAD note on the insn where this
4168 Similarly, the new insns may have clobbers that need REG_UNUSED notes. */
4170 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
4175 pat
= PATTERN (insn
);
4176 if (GET_CODE (pat
) == SET
|| GET_CODE (pat
) == CLOBBER
)
4177 new_insn_dead_notes (pat
, insn
, last
, orig_insn
);
4178 else if (GET_CODE (pat
) == PARALLEL
)
4180 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
4181 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
4182 || GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
)
4183 new_insn_dead_notes (XVECEXP (pat
, 0, i
), insn
, last
, orig_insn
);
4187 /* If any insn, except the last, uses the register set by the last insn,
4188 then we need a new REG_DEAD note on that insn. In this case, there
4189 would not have been a REG_DEAD note for this register in the original
4190 insn because it was used and set within one insn.
4192 There is no new REG_DEAD note needed if the last insn uses the register
4193 that it is setting. */
4195 set
= single_set (last
);
4198 rtx dest
= SET_DEST (set
);
4200 while (GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SUBREG
4201 || GET_CODE (dest
) == STRICT_LOW_PART
4202 || GET_CODE (dest
) == SIGN_EXTRACT
)
4203 dest
= XEXP (dest
, 0);
4205 if (GET_CODE (dest
) == REG
4206 && ! reg_overlap_mentioned_p (dest
, SET_SRC (set
)))
4208 for (insn
= PREV_INSN (last
); ; insn
= PREV_INSN (insn
))
4210 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
4211 && reg_mentioned_p (dest
, PATTERN (insn
))
4212 && (set
= single_set (insn
)))
4214 rtx insn_dest
= SET_DEST (set
);
4216 while (GET_CODE (insn_dest
) == ZERO_EXTRACT
4217 || GET_CODE (insn_dest
) == SUBREG
4218 || GET_CODE (insn_dest
) == STRICT_LOW_PART
4219 || GET_CODE (insn_dest
) == SIGN_EXTRACT
)
4220 insn_dest
= XEXP (insn_dest
, 0);
4222 if (insn_dest
!= dest
)
4224 note
= rtx_alloc (EXPR_LIST
);
4225 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
4226 XEXP (note
, 0) = dest
;
4227 XEXP (note
, 1) = REG_NOTES (insn
);
4228 REG_NOTES (insn
) = note
;
4229 /* The reg only dies in one insn, the last one
4240 /* If the original dest is modifying a multiple register target, and the
4241 original instruction was split such that the original dest is now set
4242 by two or more SUBREG sets, then the split insns no longer kill the
4243 destination of the original insn.
4245 In this case, if there exists an instruction in the same basic block,
4246 before the split insn, which uses the original dest, and this use is
4247 killed by the original insn, then we must remove the REG_DEAD note on
4248 this insn, because it is now superfluous.
4250 This does not apply when a hard register gets split, because the code
4251 knows how to handle overlapping hard registers properly. */
4252 if (orig_dest
&& GET_CODE (orig_dest
) == REG
)
4254 int found_orig_dest
= 0;
4255 int found_split_dest
= 0;
4257 for (insn
= first
; ; insn
= NEXT_INSN (insn
))
4259 set
= single_set (insn
);
4262 if (GET_CODE (SET_DEST (set
)) == REG
4263 && REGNO (SET_DEST (set
)) == REGNO (orig_dest
))
4265 found_orig_dest
= 1;
4268 else if (GET_CODE (SET_DEST (set
)) == SUBREG
4269 && SUBREG_REG (SET_DEST (set
)) == orig_dest
)
4271 found_split_dest
= 1;
4280 if (found_split_dest
)
4282 /* Search backwards from FIRST, looking for the first insn that uses
4283 the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN.
4284 If we find an insn, and it has a REG_DEAD note, then delete the
4287 for (insn
= first
; insn
; insn
= PREV_INSN (insn
))
4289 if (GET_CODE (insn
) == CODE_LABEL
4290 || GET_CODE (insn
) == JUMP_INSN
)
4292 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
4293 && reg_mentioned_p (orig_dest
, insn
))
4295 note
= find_regno_note (insn
, REG_DEAD
, REGNO (orig_dest
));
4297 remove_note (insn
, note
);
4301 else if (! found_orig_dest
)
4303 /* This should never happen. */
4308 /* Update reg_n_sets. This is necessary to prevent local alloc from
4309 converting REG_EQUAL notes to REG_EQUIV when splitting has modified
4310 a reg from set once to set multiple times. */
4313 rtx x
= PATTERN (orig_insn
);
4314 RTX_CODE code
= GET_CODE (x
);
4316 if (code
== SET
|| code
== CLOBBER
)
4317 update_n_sets (x
, -1);
4318 else if (code
== PARALLEL
)
4321 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
4323 code
= GET_CODE (XVECEXP (x
, 0, i
));
4324 if (code
== SET
|| code
== CLOBBER
)
4325 update_n_sets (XVECEXP (x
, 0, i
), -1);
4329 for (insn
= first
; ; insn
= NEXT_INSN (insn
))
4332 code
= GET_CODE (x
);
4334 if (code
== SET
|| code
== CLOBBER
)
4335 update_n_sets (x
, 1);
4336 else if (code
== PARALLEL
)
4339 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
4341 code
= GET_CODE (XVECEXP (x
, 0, i
));
4342 if (code
== SET
|| code
== CLOBBER
)
4343 update_n_sets (XVECEXP (x
, 0, i
), 1);
4353 /* The one entry point in this file. DUMP_FILE is the dump file for
4357 schedule_insns (dump_file
)
4360 int max_uid
= MAX_INSNS_PER_SPLIT
* (get_max_uid () + 1);
4364 /* Taking care of this degenerate case makes the rest of
4365 this code simpler. */
4366 if (n_basic_blocks
== 0)
4369 /* Create an insn here so that we can hang dependencies off of it later. */
4370 sched_before_next_call
4371 = gen_rtx (INSN
, VOIDmode
, 0, NULL_RTX
, NULL_RTX
,
4372 NULL_RTX
, 0, NULL_RTX
, 0);
4374 /* Initialize the unused_*_lists. We can't use the ones left over from
4375 the previous function, because gcc has freed that memory. We can use
4376 the ones left over from the first sched pass in the second pass however,
4377 so only clear them on the first sched pass. The first pass is before
4378 reload if flag_schedule_insns is set, otherwise it is afterwards. */
4380 if (reload_completed
== 0 || ! flag_schedule_insns
)
4382 unused_insn_list
= 0;
4383 unused_expr_list
= 0;
4386 /* We create no insns here, only reorder them, so we
4387 remember how far we can cut back the stack on exit. */
4389 /* Allocate data for this pass. See comments, above,
4390 for what these vectors do. */
4391 insn_luid
= (int *) alloca (max_uid
* sizeof (int));
4392 insn_priority
= (int *) alloca (max_uid
* sizeof (int));
4393 insn_tick
= (int *) alloca (max_uid
* sizeof (int));
4394 insn_costs
= (short *) alloca (max_uid
* sizeof (short));
4395 insn_units
= (short *) alloca (max_uid
* sizeof (short));
4396 insn_blockage
= (unsigned int *) alloca (max_uid
* sizeof (unsigned int));
4397 insn_ref_count
= (int *) alloca (max_uid
* sizeof (int));
4399 if (reload_completed
== 0)
4401 sched_reg_n_deaths
= (short *) alloca (max_regno
* sizeof (short));
4402 sched_reg_n_calls_crossed
= (int *) alloca (max_regno
* sizeof (int));
4403 sched_reg_live_length
= (int *) alloca (max_regno
* sizeof (int));
4404 bb_dead_regs
= (regset
) alloca (regset_bytes
);
4405 bb_live_regs
= (regset
) alloca (regset_bytes
);
4406 bzero (sched_reg_n_calls_crossed
, max_regno
* sizeof (int));
4407 bzero (sched_reg_live_length
, max_regno
* sizeof (int));
4408 bcopy (reg_n_deaths
, sched_reg_n_deaths
, max_regno
* sizeof (short));
4409 init_alias_analysis ();
4413 sched_reg_n_deaths
= 0;
4414 sched_reg_n_calls_crossed
= 0;
4415 sched_reg_live_length
= 0;
4418 if (! flag_schedule_insns
)
4419 init_alias_analysis ();
4422 if (write_symbols
!= NO_DEBUG
)
4426 line_note
= (rtx
*) alloca (max_uid
* sizeof (rtx
));
4427 bzero (line_note
, max_uid
* sizeof (rtx
));
4428 line_note_head
= (rtx
*) alloca (n_basic_blocks
* sizeof (rtx
));
4429 bzero (line_note_head
, n_basic_blocks
* sizeof (rtx
));
4431 /* Determine the line-number at the start of each basic block.
4432 This must be computed and saved now, because after a basic block's
4433 predecessor has been scheduled, it is impossible to accurately
4434 determine the correct line number for the first insn of the block. */
4436 for (b
= 0; b
< n_basic_blocks
; b
++)
4437 for (line
= basic_block_head
[b
]; line
; line
= PREV_INSN (line
))
4438 if (GET_CODE (line
) == NOTE
&& NOTE_LINE_NUMBER (line
) > 0)
4440 line_note_head
[b
] = line
;
4445 bzero (insn_luid
, max_uid
* sizeof (int));
4446 bzero (insn_priority
, max_uid
* sizeof (int));
4447 bzero (insn_tick
, max_uid
* sizeof (int));
4448 bzero (insn_costs
, max_uid
* sizeof (short));
4449 bzero (insn_units
, max_uid
* sizeof (short));
4450 bzero (insn_blockage
, max_uid
* sizeof (unsigned int));
4451 bzero (insn_ref_count
, max_uid
* sizeof (int));
4453 /* Schedule each basic block, block by block. */
4455 if (NEXT_INSN (basic_block_end
[n_basic_blocks
-1]) == 0
4456 || (GET_CODE (basic_block_end
[n_basic_blocks
-1]) != NOTE
4457 && GET_CODE (basic_block_end
[n_basic_blocks
-1]) != CODE_LABEL
))
4458 emit_note_after (NOTE_INSN_DELETED
, basic_block_end
[n_basic_blocks
-1]);
4460 for (b
= 0; b
< n_basic_blocks
; b
++)
4467 for (insn
= basic_block_head
[b
]; ; insn
= next
)
4472 /* Can't use `next_real_insn' because that
4473 might go across CODE_LABELS and short-out basic blocks. */
4474 next
= NEXT_INSN (insn
);
4475 if (GET_CODE (insn
) != INSN
)
4477 if (insn
== basic_block_end
[b
])
4483 /* Don't split no-op move insns. These should silently disappear
4484 later in final. Splitting such insns would break the code
4485 that handles REG_NO_CONFLICT blocks. */
4486 set
= single_set (insn
);
4487 if (set
&& rtx_equal_p (SET_SRC (set
), SET_DEST (set
)))
4489 if (insn
== basic_block_end
[b
])
4492 /* Nops get in the way while scheduling, so delete them now if
4493 register allocation has already been done. It is too risky
4494 to try to do this before register allocation, and there are
4495 unlikely to be very many nops then anyways. */
4496 if (reload_completed
)
4498 PUT_CODE (insn
, NOTE
);
4499 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
4500 NOTE_SOURCE_FILE (insn
) = 0;
4506 /* Split insns here to get max fine-grain parallelism. */
4507 prev
= PREV_INSN (insn
);
4508 if (reload_completed
== 0)
4510 rtx last
, first
= PREV_INSN (insn
);
4511 rtx notes
= REG_NOTES (insn
);
4513 last
= try_split (PATTERN (insn
), insn
, 1);
4516 /* try_split returns the NOTE that INSN became. */
4517 first
= NEXT_INSN (first
);
4518 update_flow_info (notes
, first
, last
, insn
);
4520 PUT_CODE (insn
, NOTE
);
4521 NOTE_SOURCE_FILE (insn
) = 0;
4522 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
4523 if (insn
== basic_block_head
[b
])
4524 basic_block_head
[b
] = first
;
4525 if (insn
== basic_block_end
[b
])
4527 basic_block_end
[b
] = last
;
4533 if (insn
== basic_block_end
[b
])
4537 schedule_block (b
, dump_file
);
4544 /* Reposition the prologue and epilogue notes in case we moved the
4545 prologue/epilogue insns. */
4546 if (reload_completed
)
4547 reposition_prologue_and_epilogue_notes (get_insns ());
4549 if (write_symbols
!= NO_DEBUG
)
4552 rtx insn
= get_insns ();
4553 int active_insn
= 0;
4556 /* Walk the insns deleting redundant line-number notes. Many of these
4557 are already present. The remainder tend to occur at basic
4558 block boundaries. */
4559 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
4560 if (GET_CODE (insn
) == NOTE
&& NOTE_LINE_NUMBER (insn
) > 0)
4562 /* If there are no active insns following, INSN is redundant. */
4563 if (active_insn
== 0)
4566 NOTE_SOURCE_FILE (insn
) = 0;
4567 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
4569 /* If the line number is unchanged, LINE is redundant. */
4571 && NOTE_LINE_NUMBER (line
) == NOTE_LINE_NUMBER (insn
)
4572 && NOTE_SOURCE_FILE (line
) == NOTE_SOURCE_FILE (insn
))
4575 NOTE_SOURCE_FILE (line
) = 0;
4576 NOTE_LINE_NUMBER (line
) = NOTE_INSN_DELETED
;
4583 else if (! ((GET_CODE (insn
) == NOTE
4584 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_DELETED
)
4585 || (GET_CODE (insn
) == INSN
4586 && (GET_CODE (PATTERN (insn
)) == USE
4587 || GET_CODE (PATTERN (insn
)) == CLOBBER
))))
4590 if (dump_file
&& notes
)
4591 fprintf (dump_file
, ";; deleted %d line-number notes\n", notes
);
4594 if (reload_completed
== 0)
4597 for (regno
= 0; regno
< max_regno
; regno
++)
4598 if (sched_reg_live_length
[regno
])
4602 if (reg_live_length
[regno
] > sched_reg_live_length
[regno
])
4604 ";; register %d life shortened from %d to %d\n",
4605 regno
, reg_live_length
[regno
],
4606 sched_reg_live_length
[regno
]);
4607 /* Negative values are special; don't overwrite the current
4608 reg_live_length value if it is negative. */
4609 else if (reg_live_length
[regno
] < sched_reg_live_length
[regno
]
4610 && reg_live_length
[regno
] >= 0)
4612 ";; register %d life extended from %d to %d\n",
4613 regno
, reg_live_length
[regno
],
4614 sched_reg_live_length
[regno
]);
4616 if (reg_n_calls_crossed
[regno
]
4617 && ! sched_reg_n_calls_crossed
[regno
])
4619 ";; register %d no longer crosses calls\n", regno
);
4620 else if (! reg_n_calls_crossed
[regno
]
4621 && sched_reg_n_calls_crossed
[regno
])
4623 ";; register %d now crosses calls\n", regno
);
4625 /* Negative values are special; don't overwrite the current
4626 reg_live_length value if it is negative. */
4627 if (reg_live_length
[regno
] >= 0)
4628 reg_live_length
[regno
] = sched_reg_live_length
[regno
];
4629 reg_n_calls_crossed
[regno
] = sched_reg_n_calls_crossed
[regno
];
4633 #endif /* INSN_SCHEDULING */