1 /* Instruction scheduling pass.
2 Copyright (C) 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 Enhanced by, and currently maintained by, Jim Wilson (wilson@cygnus.com)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Instruction scheduling pass.
24 This pass implements list scheduling within basic blocks. It is
25 run after flow analysis, but before register allocation. The
26 scheduler works as follows:
28 We compute insn priorities based on data dependencies. Flow
29 analysis only creates a fraction of the data-dependencies we must
30 observe: namely, only those dependencies which the combiner can be
31 expected to use. For this pass, we must therefore create the
32 remaining dependencies we need to observe: register dependencies,
33 memory dependencies, dependencies to keep function calls in order,
34 and the dependence between a conditional branch and the setting of
35 condition codes are all dealt with here.
37 The scheduler first traverses the data flow graph, starting with
38 the last instruction, and proceeding to the first, assigning
39 values to insn_priority as it goes. This sorts the instructions
40 topologically by data dependence.
42 Once priorities have been established, we order the insns using
43 list scheduling. This works as follows: starting with a list of
44 all the ready insns, and sorted according to priority number, we
45 schedule the insn from the end of the list by placing its
46 predecessors in the list according to their priority order. We
47 consider this insn scheduled by setting the pointer to the "end" of
48 the list to point to the previous insn. When an insn has no
49 predecessors, we also add it to the ready list. When all insns down
50 to the lowest priority have been scheduled, the critical path of the
51 basic block has been made as short as possible. The remaining insns
52 are then scheduled in remaining slots.
54 The following list shows the order in which we want to break ties:
56 1. choose insn with lowest conflict cost, ties broken by
57 2. choose insn with the longest path to end of bb, ties broken by
58 3. choose insn that kills the most registers, ties broken by
59 4. choose insn that conflicts with the most ready insns, or finally
60 5. choose insn with lowest UID.
62 Memory references complicate matters. Only if we can be certain
63 that memory references are not part of the data dependency graph
64 (via true, anti, or output dependence), can we move operations past
65 memory references. To first approximation, reads can be done
66 independently, while writes introduce dependencies. Better
67 approximations will yield fewer dependencies.
69 Dependencies set up by memory references are treated in exactly the
70 same way as other dependencies, by using LOG_LINKS.
72 Having optimized the critical path, we may have also unduly
73 extended the lifetimes of some registers. If an operation requires
74 that constants be loaded into registers, it is certainly desirable
75 to load those constants as early as necessary, but no earlier.
76 I.e., it will not do to load up a bunch of registers at the
77 beginning of a basic block only to use them at the end, if they
78 could be loaded later, since this may result in excessive register
81 Note that since branches are never in basic blocks, but only end
82 basic blocks, this pass will not do any branch scheduling. But
83 that is ok, since we can use GNU's delayed branch scheduling
84 pass to take care of this case.
86 Also note that no further optimizations based on algebraic identities
87 are performed, so this pass would be a good one to perform instruction
88 splitting, such as breaking up a multiply instruction into shifts
89 and adds where that is profitable.
91 Given the memory aliasing analysis that this pass should perform,
92 it should be possible to remove redundant stores to memory, and to
93 load values from registers instead of hitting memory.
95 This pass must update information that subsequent passes expect to be
96 correct. Namely: reg_n_refs, reg_n_sets, reg_n_deaths,
97 reg_n_calls_crossed, and reg_live_length. Also, basic_block_head,
100 The information in the line number notes is carefully retained by this
101 pass. All other NOTE insns are grouped in their same relative order at
102 the beginning of basic blocks that have been scheduled. */
107 #include "basic-block.h"
109 #include "hard-reg-set.h"
111 #include "insn-config.h"
112 #include "insn-attr.h"
114 /* Arrays set up by scheduling for the same respective purposes as
115 similar-named arrays set up by flow analysis. We work with these
116 arrays during the scheduling pass so we can compare values against
119 Values of these arrays are copied at the end of this pass into the
120 arrays set up by flow analysis. */
121 static short *sched_reg_n_deaths
;
122 static int *sched_reg_n_calls_crossed
;
123 static int *sched_reg_live_length
;
125 /* Element N is the next insn that sets (hard or pseudo) register
126 N within the current basic block; or zero, if there is no
127 such insn. Needed for new registers which may be introduced
128 by splitting insns. */
129 static rtx
*reg_last_uses
;
130 static rtx
*reg_last_sets
;
132 /* Vector indexed by INSN_UID giving the original ordering of the insns. */
133 static int *insn_luid
;
134 #define INSN_LUID(INSN) (insn_luid[INSN_UID (INSN)])
136 /* Vector indexed by INSN_UID giving each instruction a priority. */
137 static int *insn_priority
;
138 #define INSN_PRIORITY(INSN) (insn_priority[INSN_UID (INSN)])
140 #define DONE_PRIORITY -1
141 #define MAX_PRIORITY 0x7fffffff
142 #define TAIL_PRIORITY 0x7ffffffe
143 #define LAUNCH_PRIORITY 0x7f000001
144 #define DONE_PRIORITY_P(INSN) (INSN_PRIORITY (INSN) < 0)
145 #define LOW_PRIORITY_P(INSN) ((INSN_PRIORITY (INSN) & 0x7f000000) == 0)
147 /* Vector indexed by INSN_UID giving number of insns referring to this insn. */
148 static int *insn_ref_count
;
149 #define INSN_REF_COUNT(INSN) (insn_ref_count[INSN_UID (INSN)])
151 /* Vector indexed by INSN_UID giving line-number note in effect for each
152 insn. For line-number notes, this indicates whether the note may be
154 static rtx
*line_note
;
155 #define LINE_NOTE(INSN) (line_note[INSN_UID (INSN)])
157 /* Vector indexed by basic block number giving the starting line-number
158 for each basic block. */
159 static rtx
*line_note_head
;
161 /* List of important notes we must keep around. This is a pointer to the
162 last element in the list. */
163 static rtx note_list
;
165 /* Regsets telling whether a given register is live or dead before the last
166 scheduled insn. Must scan the instructions once before scheduling to
167 determine what registers are live or dead at the end of the block. */
168 static regset bb_dead_regs
;
169 static regset bb_live_regs
;
171 /* Regset telling whether a given register is live after the insn currently
172 being scheduled. Before processing an insn, this is equal to bb_live_regs
173 above. This is used so that we can find regsiters that are newly born/dead
174 after processing an insn. */
175 static regset old_live_regs
;
177 /* The chain of REG_DEAD notes. REG_DEAD notes are removed from all insns
178 during the initial scan and reused later. If there are not exactly as
179 many REG_DEAD notes in the post scheduled code as there were in the
180 prescheduled code then we trigger an abort because this indicates a bug. */
181 static rtx dead_notes
;
185 /* An instruction is ready to be scheduled when all insns following it
186 have already been scheduled. It is important to ensure that all
187 insns which use its result will not be executed until its result
188 has been computed. We maintain three lists (conceptually):
190 (1) a "Ready" list of unscheduled, uncommitted insns
191 (2) a "Scheduled" list of scheduled insns
192 (3) a "Pending" list of insns which can be scheduled, but
195 Insns move from the "Ready" list to the "Pending" list when
196 all insns following them have been scheduled.
198 Insns move from the "Pending" list to the "Scheduled" list
199 when there is sufficient space in the pipeline to prevent
200 stalls between the insn and scheduled insns which use it.
202 The "Pending" list acts as a buffer to prevent insns
205 The "Ready" list is implemented by the variable `ready'.
206 The "Pending" list are the insns in the LOG_LINKS of ready insns.
207 The "Scheduled" list is the new insn chain built by this pass. */
209 /* Implement a circular buffer from which instructions are issued. */
211 static rtx insn_queue
[Q_SIZE
];
212 static int q_ptr
= 0;
213 static int q_size
= 0;
214 #define NEXT_Q(X) (((X)+1) & (Q_SIZE-1))
215 #define NEXT_Q_AFTER(X,C) (((X)+C) & (Q_SIZE-1))
217 /* Forward declarations. */
218 static void sched_analyze_2 ();
219 static void schedule_block ();
221 /* Main entry point of this file. */
222 void schedule_insns ();
224 #define SIZE_FOR_MODE(X) (GET_MODE_SIZE (GET_MODE (X)))
226 /* Vector indexed by N giving the initial (unchanging) value known
227 for pseudo-register N. */
228 static rtx
*reg_known_value
;
230 /* Indicates number of valid entries in reg_known_value. */
231 static int reg_known_value_size
;
237 if (GET_CODE (x
) == REG
&& REGNO (x
) >= FIRST_PSEUDO_REGISTER
238 && REGNO (x
) <= reg_known_value_size
)
239 return reg_known_value
[REGNO (x
)];
240 else if (GET_CODE (x
) == PLUS
)
242 rtx x0
= canon_rtx (XEXP (x
, 0));
243 rtx x1
= canon_rtx (XEXP (x
, 1));
245 if (x0
!= XEXP (x
, 0) || x1
!= XEXP (x
, 1))
247 /* We can tolerate LO_SUMs being offset here; these
248 rtl are used for nothing other than comparisons. */
249 if (GET_CODE (x0
) == CONST_INT
)
250 return plus_constant_for_output (x1
, INTVAL (x0
));
251 else if (GET_CODE (x1
) == CONST_INT
)
252 return plus_constant_for_output (x0
, INTVAL (x1
));
253 return gen_rtx (PLUS
, GET_MODE (x
), x0
, x1
);
259 /* Set up all info needed to perform alias analysis on memory references. */
262 init_alias_analysis ()
264 int maxreg
= max_reg_num ();
269 reg_known_value_size
= maxreg
;
272 = (rtx
*) oballoc ((maxreg
-FIRST_PSEUDO_REGISTER
) * sizeof (rtx
))
273 - FIRST_PSEUDO_REGISTER
;
274 bzero (reg_known_value
+FIRST_PSEUDO_REGISTER
,
275 (maxreg
-FIRST_PSEUDO_REGISTER
) * sizeof (rtx
));
277 /* Fill in the entries with known constant values. */
278 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
279 if ((set
= single_set (insn
)) != 0
280 && GET_CODE (SET_DEST (set
)) == REG
281 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
282 && (((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
283 && reg_n_sets
[REGNO (SET_DEST (set
))] == 1)
284 || (note
= find_reg_note (insn
, REG_EQUIV
, 0)) != 0)
285 && GET_CODE (XEXP (note
, 0)) != EXPR_LIST
)
286 reg_known_value
[REGNO (SET_DEST (set
))] = XEXP (note
, 0);
288 /* Fill in the remaining entries. */
289 while (--maxreg
>= FIRST_PSEUDO_REGISTER
)
290 if (reg_known_value
[maxreg
] == 0)
291 reg_known_value
[maxreg
] = regno_reg_rtx
[maxreg
];
294 /* Return 1 if X and Y are identical-looking rtx's.
296 We use the data in reg_known_value above to see if two registers with
297 different numbers are, in fact, equivalent. */
300 rtx_equal_for_memref_p (x
, y
)
305 register enum rtx_code code
;
308 if (x
== 0 && y
== 0)
310 if (x
== 0 || y
== 0)
319 /* Rtx's of different codes cannot be equal. */
320 if (code
!= GET_CODE (y
))
323 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
324 (REG:SI x) and (REG:HI x) are NOT equivalent. */
326 if (GET_MODE (x
) != GET_MODE (y
))
329 /* REG, LABEL_REF, and SYMBOL_REF can be compared nonrecursively. */
332 return REGNO (x
) == REGNO (y
);
333 if (code
== LABEL_REF
)
334 return XEXP (x
, 0) == XEXP (y
, 0);
335 if (code
== SYMBOL_REF
)
336 return XSTR (x
, 0) == XSTR (y
, 0);
338 /* Compare the elements. If any pair of corresponding elements
339 fail to match, return 0 for the whole things. */
341 fmt
= GET_RTX_FORMAT (code
);
342 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
348 if (XINT (x
, i
) != XINT (y
, i
))
354 /* Two vectors must have the same length. */
355 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
358 /* And the corresponding elements must match. */
359 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
360 if (rtx_equal_for_memref_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
)) == 0)
365 if (rtx_equal_for_memref_p (XEXP (x
, i
), XEXP (y
, i
)) == 0)
371 if (strcmp (XSTR (x
, i
), XSTR (y
, i
)))
376 /* These are just backpointers, so they don't matter. */
382 /* It is believed that rtx's at this level will never
383 contain anything but integers and other rtx's,
384 except for within LABEL_REFs and SYMBOL_REFs. */
392 /* Given an rtx X, find a SYMBOL_REF or LABEL_REF within
393 X and return it, or return 0 if none found. */
396 find_symbolic_term (x
)
400 register enum rtx_code code
;
404 if (code
== SYMBOL_REF
|| code
== LABEL_REF
)
406 if (GET_RTX_CLASS (code
) == 'o')
409 fmt
= GET_RTX_FORMAT (code
);
410 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
416 t
= find_symbolic_term (XEXP (x
, i
));
420 else if (fmt
[i
] == 'E')
426 /* Return nonzero if X and Y (memory addresses) could reference the
427 same location in memory. C is an offset accumulator. When
428 C is nonzero, we are testing aliases between X and Y + C.
429 XSIZE is the size in bytes of the X reference,
430 similarly YSIZE is the size in bytes for Y.
432 If XSIZE or YSIZE is zero, we do not know the amount of memory being
433 referenced (the reference was BLKmode), so make the most pessimistic
436 We recognize the following cases of non-conflicting memory:
438 (1) addresses involving the frame pointer cannot conflict
439 with addresses involving static variables.
440 (2) static variables with different addresses cannot conflict.
442 Nice to notice that varying addresses cannot confict with fp if no
443 local variables had their addresses taken, but that's too hard now. */
446 memrefs_conflict_p (xsize
, x
, ysize
, y
, c
)
451 if (GET_CODE (x
) == HIGH
)
453 else if (GET_CODE (x
) == LO_SUM
)
457 if (GET_CODE (y
) == HIGH
)
459 else if (GET_CODE (y
) == LO_SUM
)
464 if (rtx_equal_for_memref_p (x
, y
))
465 return (xsize
== 0 || ysize
== 0 ||
466 (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0));
468 if (y
== frame_pointer_rtx
|| y
== stack_pointer_rtx
)
472 y
= x
; ysize
= xsize
;
473 x
= t
; xsize
= tsize
;
476 if (x
== frame_pointer_rtx
|| x
== stack_pointer_rtx
)
483 if (GET_CODE (y
) == PLUS
484 && canon_rtx (XEXP (y
, 0)) == x
485 && (y1
= canon_rtx (XEXP (y
, 1)))
486 && GET_CODE (y1
) == CONST_INT
)
489 return (xsize
== 0 || ysize
== 0
490 || (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0));
493 if (GET_CODE (y
) == PLUS
494 && (y1
= canon_rtx (XEXP (y
, 0)))
501 if (GET_CODE (x
) == PLUS
)
503 /* The fact that X is canonnicallized means that this
504 PLUS rtx is canonnicallized. */
505 rtx x0
= XEXP (x
, 0);
506 rtx x1
= XEXP (x
, 1);
508 if (GET_CODE (y
) == PLUS
)
510 /* The fact that Y is canonnicallized means that this
511 PLUS rtx is canonnicallized. */
512 rtx y0
= XEXP (y
, 0);
513 rtx y1
= XEXP (y
, 1);
515 if (rtx_equal_for_memref_p (x1
, y1
))
516 return memrefs_conflict_p (xsize
, x0
, ysize
, y0
, c
);
517 if (rtx_equal_for_memref_p (x0
, y0
))
518 return memrefs_conflict_p (xsize
, x1
, ysize
, y1
, c
);
519 if (GET_CODE (x1
) == CONST_INT
)
520 if (GET_CODE (y1
) == CONST_INT
)
521 return memrefs_conflict_p (xsize
, x0
, ysize
, y0
,
522 c
- INTVAL (x1
) + INTVAL (y1
));
524 return memrefs_conflict_p (xsize
, x0
, ysize
, y
, c
- INTVAL (x1
));
525 else if (GET_CODE (y1
) == CONST_INT
)
526 return memrefs_conflict_p (xsize
, x
, ysize
, y0
, c
+ INTVAL (y1
));
528 /* Handle case where we cannot understand iteration operators,
529 but we notice that the base addresses are distinct objects. */
530 x
= find_symbolic_term (x
);
533 y
= find_symbolic_term (y
);
536 return rtx_equal_for_memref_p (x
, y
);
538 else if (GET_CODE (x1
) == CONST_INT
)
539 return memrefs_conflict_p (xsize
, x0
, ysize
, y
, c
- INTVAL (x1
));
541 else if (GET_CODE (y
) == PLUS
)
543 /* The fact that Y is canonnicallized means that this
544 PLUS rtx is canonnicallized. */
545 rtx y0
= XEXP (y
, 0);
546 rtx y1
= XEXP (y
, 1);
548 if (GET_CODE (y1
) == CONST_INT
)
549 return memrefs_conflict_p (xsize
, x
, ysize
, y0
, c
+ INTVAL (y1
));
554 if (GET_CODE (x
) == GET_CODE (y
))
555 switch (GET_CODE (x
))
559 /* Handle cases where we expect the second operands to be the
560 same, and check only whether the first operand would conflict
563 rtx x1
= canon_rtx (XEXP (x
, 1));
564 rtx y1
= canon_rtx (XEXP (y
, 1));
565 if (! rtx_equal_for_memref_p (x1
, y1
))
567 x0
= canon_rtx (XEXP (x
, 0));
568 y0
= canon_rtx (XEXP (y
, 0));
569 if (rtx_equal_for_memref_p (x0
, y0
))
570 return (xsize
== 0 || ysize
== 0
571 || (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0));
573 /* Can't properly adjust our sizes. */
574 if (GET_CODE (x1
) != CONST_INT
)
576 xsize
/= INTVAL (x1
);
577 ysize
/= INTVAL (x1
);
579 return memrefs_conflict_p (xsize
, x0
, ysize
, y0
, c
);
585 if (GET_CODE (x
) == CONST_INT
&& GET_CODE (y
) == CONST_INT
)
587 c
+= (INTVAL (y
) - INTVAL (x
));
588 return (xsize
== 0 || ysize
== 0
589 || (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0));
592 if (GET_CODE (x
) == CONST
)
594 if (GET_CODE (y
) == CONST
)
595 return memrefs_conflict_p (xsize
, canon_rtx (XEXP (x
, 0)),
596 ysize
, canon_rtx (XEXP (y
, 0)), c
);
598 return memrefs_conflict_p (xsize
, canon_rtx (XEXP (x
, 0)),
601 if (GET_CODE (y
) == CONST
)
602 return memrefs_conflict_p (xsize
, x
, ysize
,
603 canon_rtx (XEXP (y
, 0)), c
);
606 return (rtx_equal_for_memref_p (x
, y
)
607 && (xsize
== 0 || ysize
== 0
608 || (c
>= 0 && xsize
> c
) || (c
< 0 && ysize
+c
> 0)));
615 /* Functions to compute memory dependencies.
617 Since we process the insns in execution order, we can build tables
618 to keep track of what registers are fixed (and not aliased), what registers
619 are varying in known ways, and what registers are varying in unknown
622 If both memory references are volatile, then there must always be a
623 dependence between the two references, since their order can not be
624 changed. A volatile and non-volatile reference can be interchanged
627 A MEM_IN_STRUCT reference at a varying address can never conflict with a
628 non-MEM_IN_STRUCT reference at a fixed address. */
630 /* Read dependence: X is read after read in MEM takes place. There can
631 only be a dependence here if both reads are volatile. */
634 read_dependence (mem
, x
)
638 return MEM_VOLATILE_P (x
) && MEM_VOLATILE_P (mem
);
641 /* True dependence: X is read after store in MEM takes place. */
644 true_dependence (mem
, x
)
648 if (RTX_UNCHANGING_P (x
))
651 return ((MEM_VOLATILE_P (x
) && MEM_VOLATILE_P (mem
))
652 || (memrefs_conflict_p (SIZE_FOR_MODE (mem
), XEXP (mem
, 0),
653 SIZE_FOR_MODE (x
), XEXP (x
, 0), 0)
654 && ! (MEM_IN_STRUCT_P (mem
) && rtx_addr_varies_p (mem
)
655 && ! MEM_IN_STRUCT_P (x
) && ! rtx_addr_varies_p (x
))
656 && ! (MEM_IN_STRUCT_P (x
) && rtx_addr_varies_p (x
)
657 && ! MEM_IN_STRUCT_P (mem
) && ! rtx_addr_varies_p (mem
))));
660 /* Anti dependence: X is written after read in MEM takes place. */
663 anti_dependence (mem
, x
)
667 if (RTX_UNCHANGING_P (mem
))
670 return ((MEM_VOLATILE_P (x
) && MEM_VOLATILE_P (mem
))
671 || (memrefs_conflict_p (SIZE_FOR_MODE (mem
), XEXP (mem
, 0),
672 SIZE_FOR_MODE (x
), XEXP (x
, 0), 0)
673 && ! (MEM_IN_STRUCT_P (mem
) && rtx_addr_varies_p (mem
)
674 && ! MEM_IN_STRUCT_P (x
) && ! rtx_addr_varies_p (x
))
675 && ! (MEM_IN_STRUCT_P (x
) && rtx_addr_varies_p (x
)
676 && ! MEM_IN_STRUCT_P (mem
) && ! rtx_addr_varies_p (mem
))));
679 /* Output dependence: X is written after store in MEM takes place. */
682 output_dependence (mem
, x
)
686 return ((MEM_VOLATILE_P (x
) && MEM_VOLATILE_P (mem
))
687 || (memrefs_conflict_p (SIZE_FOR_MODE (mem
), XEXP (mem
, 0),
688 SIZE_FOR_MODE (x
), XEXP (x
, 0), 0)
689 && ! (MEM_IN_STRUCT_P (mem
) && rtx_addr_varies_p (mem
)
690 && ! MEM_IN_STRUCT_P (x
) && ! rtx_addr_varies_p (x
))
691 && ! (MEM_IN_STRUCT_P (x
) && rtx_addr_varies_p (x
)
692 && ! MEM_IN_STRUCT_P (mem
) && ! rtx_addr_varies_p (mem
))));
695 #ifndef INSN_SCHEDULING
696 void schedule_insns () {}
702 /* Computation of memory dependencies. */
704 /* The *_insns and *_mems are paired lists. Each pending memory operation
705 will have a pointer to the MEM rtx on one list and a pointer to the
706 containing insn on the other list in the same place in the list. */
708 /* We can't use add_dependence like the old code did, because a single insn
709 may have multiple memory accesses, and hence needs to be on the list
710 once for each memory access. Add_dependence won't let you add an insn
711 to a list more than once. */
713 /* An INSN_LIST containing all insns with pending read operations. */
714 static rtx pending_read_insns
;
716 /* An EXPR_LIST containing all MEM rtx's which are pending reads. */
717 static rtx pending_read_mems
;
719 /* An INSN_LIST containing all insns with pending write operations. */
720 static rtx pending_write_insns
;
722 /* An EXPR_LIST containing all MEM rtx's which are pending writes. */
723 static rtx pending_write_mems
;
725 /* Indicates the combined length of the two pending lists. We must prevent
726 these lists from ever growing too large since the number of dependencies
727 produced is at least O(N*N), and execution time is at least O(4*N*N), as
728 a function of the length of these pending lists. */
730 static int pending_lists_length
;
732 /* An INSN_LIST containing all INSN_LISTs allocated but currently unused. */
734 static rtx unused_insn_list
;
736 /* An EXPR_LIST containing all EXPR_LISTs allocated but currently unused. */
738 static rtx unused_expr_list
;
740 /* The last insn upon which all memory references must depend.
741 This is an insn which flushed the pending lists, creating a dependency
742 between it and all previously pending memory references. This creates
743 a barrier (or a checkpoint) which no memory reference is allowed to cross.
745 This includes all non constant CALL_INSNs. When we do interprocedural
746 alias analysis, this restriction can be relaxed.
747 This may also be an INSN that writes memory if the pending lists grow
750 static rtx last_pending_memory_flush
;
752 /* The last function call we have seen. All hard regs, and, of course,
753 the last function call, must depend on this. */
755 static rtx last_function_call
;
757 /* The LOG_LINKS field of this is a list of insns which use a pseudo register
758 that does not already cross a call. We create dependencies between each
759 of those insn and the next call insn, to ensure that they won't cross a call
760 after scheduling is done. */
762 static rtx sched_before_next_call
;
764 /* Pointer to the last instruction scheduled. Used by rank_for_schedule,
765 so that insns independent of the last scheduled insn will be preferred
766 over dependent instructions. */
768 static rtx last_scheduled_insn
;
770 /* Process an insn's memory dependencies. There are four kinds of
773 (0) read dependence: read follows read
774 (1) true dependence: read follows write
775 (2) anti dependence: write follows read
776 (3) output dependence: write follows write
778 We are careful to build only dependencies which actually exist, and
779 use transitivity to avoid building too many links. */
781 /* Return the INSN_LIST containing INSN in LIST, or NULL
782 if LIST does not contain INSN. */
785 find_insn_list (insn
, list
)
791 if (XEXP (list
, 0) == insn
)
793 list
= XEXP (list
, 1);
798 /* Compute cost of executing INSN. This is the number of virtual
799 cycles taken between instruction issue and instruction results. */
807 recog_memoized (insn
);
809 /* A USE insn, or something else we don't need to understand.
810 We can't pass these directly to result_ready_cost because it will trigger
811 a fatal error for unrecognizable insns. */
812 if (INSN_CODE (insn
) < 0)
816 cost
= result_ready_cost (insn
);
825 /* Compute the priority number for INSN. */
831 if (insn
&& GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
835 int this_priority
= INSN_PRIORITY (insn
);
838 if (this_priority
> 0)
839 return this_priority
;
843 /* Nonzero if these insns must be scheduled together. */
844 if (SCHED_GROUP_P (insn
))
847 while (SCHED_GROUP_P (prev
))
849 prev
= PREV_INSN (prev
);
850 INSN_REF_COUNT (prev
) += 1;
854 for (prev
= LOG_LINKS (insn
); prev
; prev
= XEXP (prev
, 1))
856 rtx x
= XEXP (prev
, 0);
858 /* A dependence pointing to a note is always obsolete, because
859 sched_analyze_insn will have created any necessary new dependences
860 which replace it. Notes can be created when instructions are
861 deleted by insn splitting, or by register allocation. */
862 if (GET_CODE (x
) == NOTE
)
864 remove_dependence (insn
, x
);
868 /* This priority calculation was chosen because it results in the
869 least instruction movement, and does not hurt the performance
870 of the resulting code compared to the old algorithm.
871 This makes the sched algorithm more stable, which results
872 in better code, because there is less register pressure,
873 cross jumping is more likely to work, and debugging is easier.
875 When all instructions have a latency of 1, there is no need to
876 move any instructions. Subtracting one here ensures that in such
877 cases all instructions will end up with a priority of one, and
878 hence no scheduling will be done.
880 The original code did not subtract the one, and added the
881 insn_cost of the current instruction to its priority (e.g.
882 move the insn_cost call down to the end). */
884 if (REG_NOTE_KIND (prev
) == 0)
885 /* Data dependence. */
886 prev_priority
= priority (x
) + insn_cost (x
) - 1;
888 /* Anti or output dependence. Don't add the latency of this
889 insn's result, because it isn't being used. */
890 prev_priority
= priority (x
);
892 if (prev_priority
> max_priority
)
893 max_priority
= prev_priority
;
894 INSN_REF_COUNT (x
) += 1;
897 INSN_PRIORITY (insn
) = max_priority
;
898 return INSN_PRIORITY (insn
);
903 /* Remove all INSN_LISTs and EXPR_LISTs from the pending lists and add
904 them to the unused_*_list variables, so that they can be reused. */
907 free_pending_lists ()
909 register rtx link
, prev_link
;
911 if (pending_read_insns
)
913 prev_link
= pending_read_insns
;
914 link
= XEXP (prev_link
, 1);
919 link
= XEXP (link
, 1);
922 XEXP (prev_link
, 1) = unused_insn_list
;
923 unused_insn_list
= pending_read_insns
;
924 pending_read_insns
= 0;
927 if (pending_write_insns
)
929 prev_link
= pending_write_insns
;
930 link
= XEXP (prev_link
, 1);
935 link
= XEXP (link
, 1);
938 XEXP (prev_link
, 1) = unused_insn_list
;
939 unused_insn_list
= pending_write_insns
;
940 pending_write_insns
= 0;
943 if (pending_read_mems
)
945 prev_link
= pending_read_mems
;
946 link
= XEXP (prev_link
, 1);
951 link
= XEXP (link
, 1);
954 XEXP (prev_link
, 1) = unused_expr_list
;
955 unused_expr_list
= pending_read_mems
;
956 pending_read_mems
= 0;
959 if (pending_write_mems
)
961 prev_link
= pending_write_mems
;
962 link
= XEXP (prev_link
, 1);
967 link
= XEXP (link
, 1);
970 XEXP (prev_link
, 1) = unused_expr_list
;
971 unused_expr_list
= pending_write_mems
;
972 pending_write_mems
= 0;
976 /* Add an INSN and MEM reference pair to a pending INSN_LIST and MEM_LIST.
977 The MEM is a memory reference contained within INSN, which we are saving
978 so that we can do memory aliasing on it. */
981 add_insn_mem_dependence (insn_list
, mem_list
, insn
, mem
)
982 rtx
*insn_list
, *mem_list
, insn
, mem
;
986 if (unused_insn_list
)
988 link
= unused_insn_list
;
989 unused_insn_list
= XEXP (link
, 1);
992 link
= rtx_alloc (INSN_LIST
);
993 XEXP (link
, 0) = insn
;
994 XEXP (link
, 1) = *insn_list
;
997 if (unused_expr_list
)
999 link
= unused_expr_list
;
1000 unused_expr_list
= XEXP (link
, 1);
1003 link
= rtx_alloc (EXPR_LIST
);
1004 XEXP (link
, 0) = mem
;
1005 XEXP (link
, 1) = *mem_list
;
1008 pending_lists_length
++;
1011 /* Make a dependency between every memory reference on the pending lists
1012 and INSN, thus flushing the pending lists. */
1015 flush_pending_lists (insn
)
1020 while (pending_read_insns
)
1022 add_dependence (insn
, XEXP (pending_read_insns
, 0), REG_DEP_ANTI
);
1024 link
= pending_read_insns
;
1025 pending_read_insns
= XEXP (pending_read_insns
, 1);
1026 XEXP (link
, 1) = unused_insn_list
;
1027 unused_insn_list
= link
;
1029 link
= pending_read_mems
;
1030 pending_read_mems
= XEXP (pending_read_mems
, 1);
1031 XEXP (link
, 1) = unused_expr_list
;
1032 unused_expr_list
= link
;
1034 while (pending_write_insns
)
1036 add_dependence (insn
, XEXP (pending_write_insns
, 0), REG_DEP_ANTI
);
1038 link
= pending_write_insns
;
1039 pending_write_insns
= XEXP (pending_write_insns
, 1);
1040 XEXP (link
, 1) = unused_insn_list
;
1041 unused_insn_list
= link
;
1043 link
= pending_write_mems
;
1044 pending_write_mems
= XEXP (pending_write_mems
, 1);
1045 XEXP (link
, 1) = unused_expr_list
;
1046 unused_expr_list
= link
;
1048 pending_lists_length
= 0;
1050 if (last_pending_memory_flush
)
1051 add_dependence (insn
, last_pending_memory_flush
, REG_DEP_ANTI
);
1053 last_pending_memory_flush
= insn
;
1056 /* Analyze a single SET or CLOBBER rtx, X, creating all dependencies generated
1057 by the write to the destination of X, and reads of everything mentioned. */
1060 sched_analyze_1 (x
, insn
)
1065 register rtx dest
= SET_DEST (x
);
1070 while (GET_CODE (dest
) == STRICT_LOW_PART
|| GET_CODE (dest
) == SUBREG
1071 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SIGN_EXTRACT
)
1073 if (GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SIGN_EXTRACT
)
1075 /* The second and third arguments are values read by this insn. */
1076 sched_analyze_2 (XEXP (dest
, 1), insn
);
1077 sched_analyze_2 (XEXP (dest
, 2), insn
);
1079 dest
= SUBREG_REG (dest
);
1082 if (GET_CODE (dest
) == REG
)
1084 register int offset
, bit
, i
;
1086 regno
= REGNO (dest
);
1088 /* A hard reg in a wide mode may really be multiple registers.
1089 If so, mark all of them just like the first. */
1090 if (regno
< FIRST_PSEUDO_REGISTER
)
1092 i
= HARD_REGNO_NREGS (regno
, GET_MODE (dest
));
1097 for (u
= reg_last_uses
[regno
+i
]; u
; u
= XEXP (u
, 1))
1098 add_dependence (insn
, XEXP (u
, 0), REG_DEP_ANTI
);
1099 reg_last_uses
[regno
+ i
] = 0;
1100 if (reg_last_sets
[regno
+ i
])
1101 add_dependence (insn
, reg_last_sets
[regno
+ i
],
1103 reg_last_sets
[regno
+ i
] = insn
;
1104 if ((call_used_regs
[i
] || global_regs
[i
])
1105 && last_function_call
)
1106 /* Function calls clobber all call_used regs. */
1107 add_dependence (insn
, last_function_call
, REG_DEP_ANTI
);
1114 for (u
= reg_last_uses
[regno
]; u
; u
= XEXP (u
, 1))
1115 add_dependence (insn
, XEXP (u
, 0), REG_DEP_ANTI
);
1116 reg_last_uses
[regno
] = 0;
1117 if (reg_last_sets
[regno
])
1118 add_dependence (insn
, reg_last_sets
[regno
], REG_DEP_OUTPUT
);
1119 reg_last_sets
[regno
] = insn
;
1121 /* Don't let it cross a call after scheduling if it doesn't
1122 already cross one. */
1123 if (reg_n_calls_crossed
[regno
] == 0 && last_function_call
)
1124 add_dependence (insn
, last_function_call
, REG_DEP_ANTI
);
1127 else if (GET_CODE (dest
) == MEM
)
1129 /* Writing memory. */
1131 if (pending_lists_length
> 32)
1133 /* Flush all pending reads and writes to prevent the pending lists
1134 from getting any larger. Insn scheduling runs too slowly when
1135 these lists get long. The number 32 was chosen because it
1136 seems like a resonable number. When compiling GCC with itself,
1137 this flush occurs 8 times for sparc, and 10 times for m88k using
1139 flush_pending_lists (insn
);
1143 rtx pending
, pending_mem
;
1145 pending
= pending_read_insns
;
1146 pending_mem
= pending_read_mems
;
1149 /* If a dependency already exists, don't create a new one. */
1150 if (! find_insn_list (XEXP (pending
, 0), LOG_LINKS (insn
)))
1151 if (anti_dependence (XEXP (pending_mem
, 0), dest
, insn
))
1152 add_dependence (insn
, XEXP (pending
, 0), REG_DEP_ANTI
);
1154 pending
= XEXP (pending
, 1);
1155 pending_mem
= XEXP (pending_mem
, 1);
1158 pending
= pending_write_insns
;
1159 pending_mem
= pending_write_mems
;
1162 /* If a dependency already exists, don't create a new one. */
1163 if (! find_insn_list (XEXP (pending
, 0), LOG_LINKS (insn
)))
1164 if (output_dependence (XEXP (pending_mem
, 0), dest
))
1165 add_dependence (insn
, XEXP (pending
, 0), REG_DEP_OUTPUT
);
1167 pending
= XEXP (pending
, 1);
1168 pending_mem
= XEXP (pending_mem
, 1);
1171 if (last_pending_memory_flush
)
1172 add_dependence (insn
, last_pending_memory_flush
, REG_DEP_ANTI
);
1174 add_insn_mem_dependence (&pending_write_insns
, &pending_write_mems
,
1177 sched_analyze_2 (XEXP (dest
, 0), insn
);
1180 /* Analyze reads. */
1181 if (GET_CODE (x
) == SET
)
1182 sched_analyze_2 (SET_SRC (x
), insn
);
1185 /* Analyze the uses of memory and registers in rtx X in INSN. */
1188 sched_analyze_2 (x
, insn
)
1194 register enum rtx_code code
;
1200 code
= GET_CODE (x
);
1209 /* Ignore constants. Note that we must handle CONST_DOUBLE here
1210 because it may have a cc0_rtx in its CONST_DOUBLE_CHAIN field, but
1211 this does not mean that this insn is using cc0. */
1219 /* There may be a note before this insn now, but all notes will
1220 be removed before we actually try to schedule the insns, so
1221 it won't cause a problem later. We must avoid it here though. */
1223 /* User of CC0 depends on immediately preceding insn.
1224 SCHED_GROUP_P (insn) = 1;
1226 /* Make a copy of all dependencies on the immediately previous insn,
1227 and add to this insn. This is so that all the dependencies will
1228 apply to the group. */
1230 prev
= PREV_INSN (insn
);
1231 while (GET_CODE (prev
) == NOTE
)
1232 prev
= PREV_INSN (prev
);
1234 for (link
= LOG_LINKS (prev
); link
; link
= XEXP (link
, 1))
1235 add_dependence (insn
, XEXP (link
, 0), GET_MODE (link
));
1243 int regno
= REGNO (x
);
1244 if (regno
< FIRST_PSEUDO_REGISTER
)
1248 i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
1251 reg_last_uses
[regno
+ i
]
1252 = gen_rtx (INSN_LIST
, VOIDmode
,
1253 insn
, reg_last_uses
[regno
+ i
]);
1254 if (reg_last_sets
[regno
+ i
])
1255 add_dependence (insn
, reg_last_sets
[regno
+ i
], 0);
1256 if ((call_used_regs
[regno
+ i
] || global_regs
[regno
+ i
])
1257 && last_function_call
)
1258 /* Function calls clobber all call_used regs. */
1259 add_dependence (insn
, last_function_call
, REG_DEP_ANTI
);
1264 reg_last_uses
[regno
]
1265 = gen_rtx (INSN_LIST
, VOIDmode
, insn
, reg_last_uses
[regno
]);
1266 if (reg_last_sets
[regno
])
1267 add_dependence (insn
, reg_last_sets
[regno
], 0);
1269 /* If the register does not already cross any calls, then add this
1270 insn to the sched_before_next_call list so that it will still
1271 not cross calls after scheduling. */
1272 if (reg_n_calls_crossed
[regno
] == 0)
1273 add_dependence (sched_before_next_call
, insn
, REG_DEP_ANTI
);
1280 /* Reading memory. */
1282 /* Don't create a dependence for memory references which are known to
1283 be unchanging, such as constant pool accesses. These will never
1284 conflict with any other memory access. */
1285 if (RTX_UNCHANGING_P (x
) == 0)
1287 rtx pending
, pending_mem
;
1289 pending
= pending_read_insns
;
1290 pending_mem
= pending_read_mems
;
1293 /* If a dependency already exists, don't create a new one. */
1294 if (! find_insn_list (XEXP (pending
, 0), LOG_LINKS (insn
)))
1295 if (read_dependence (XEXP (pending_mem
, 0), x
))
1296 add_dependence (insn
, XEXP (pending
, 0), REG_DEP_ANTI
);
1298 pending
= XEXP (pending
, 1);
1299 pending_mem
= XEXP (pending_mem
, 1);
1302 pending
= pending_write_insns
;
1303 pending_mem
= pending_write_mems
;
1306 /* If a dependency already exists, don't create a new one. */
1307 if (! find_insn_list (XEXP (pending
, 0), LOG_LINKS (insn
)))
1308 if (true_dependence (XEXP (pending_mem
, 0), x
))
1309 add_dependence (insn
, XEXP (pending
, 0), 0);
1311 pending
= XEXP (pending
, 1);
1312 pending_mem
= XEXP (pending_mem
, 1);
1314 if (last_pending_memory_flush
)
1315 add_dependence (insn
, last_pending_memory_flush
, REG_DEP_ANTI
);
1317 /* Always add these dependencies to pending_reads, since
1318 this insn may be followed by a write. */
1319 add_insn_mem_dependence (&pending_read_insns
, &pending_read_mems
,
1322 /* Take advantage of tail recursion here. */
1323 sched_analyze_2 (XEXP (x
, 0), insn
);
1329 case UNSPEC_VOLATILE
:
1333 /* Traditional and volatile asm instructions must be considered to use
1334 and clobber all hard registers and all of memory. So must
1335 UNSPEC_VOLATILE operations. */
1336 if ((code
== ASM_OPERANDS
&& MEM_VOLATILE_P (x
)) || code
== ASM_INPUT
1337 || code
== UNSPEC_VOLATILE
)
1339 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1341 for (u
= reg_last_uses
[i
]; u
; u
= XEXP (u
, 1))
1342 if (GET_CODE (PATTERN (XEXP (u
, 0))) != USE
)
1343 add_dependence (insn
, XEXP (u
, 0), REG_DEP_ANTI
);
1344 reg_last_uses
[i
] = 0;
1345 if (reg_last_sets
[i
]
1346 && GET_CODE (PATTERN (reg_last_sets
[i
])) != USE
)
1347 add_dependence (insn
, reg_last_sets
[i
], 0);
1348 reg_last_sets
[i
] = insn
;
1351 flush_pending_lists (insn
);
1354 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
1355 We can not just fall through here since then we would be confused
1356 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
1357 traditional asms unlike their normal usage. */
1359 if (code
== ASM_OPERANDS
)
1361 for (j
= 0; j
< ASM_OPERANDS_INPUT_LENGTH (x
); j
++)
1362 sched_analyze_2 (ASM_OPERANDS_INPUT (x
, j
), insn
);
1372 /* These read and modify the result; just consider them writes. */
1373 sched_analyze_1 (x
, insn
);
1377 /* Other cases: walk the insn. */
1378 fmt
= GET_RTX_FORMAT (code
);
1379 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1382 sched_analyze_2 (XEXP (x
, i
), insn
);
1383 else if (fmt
[i
] == 'E')
1384 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1385 sched_analyze_2 (XVECEXP (x
, i
, j
), insn
);
1389 /* Analyze an INSN with pattern X to find all dependencies. */
1392 sched_analyze_insn (x
, insn
)
1395 register RTX_CODE code
= GET_CODE (x
);
1398 if (code
== SET
|| code
== CLOBBER
)
1399 sched_analyze_1 (x
, insn
);
1400 else if (code
== PARALLEL
)
1403 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
1405 code
= GET_CODE (XVECEXP (x
, 0, i
));
1406 if (code
== SET
|| code
== CLOBBER
)
1407 sched_analyze_1 (XVECEXP (x
, 0, i
), insn
);
1409 sched_analyze_2 (XVECEXP (x
, 0, i
), insn
);
1413 sched_analyze_2 (x
, insn
);
1415 /* Handle function calls. */
1416 if (GET_CODE (insn
) == CALL_INSN
)
1421 /* When scheduling instructions, we make sure calls don't lose their
1422 accompanying USE insns by depending them one on another in order. */
1424 prev_dep_insn
= insn
;
1425 dep_insn
= PREV_INSN (insn
);
1426 while (GET_CODE (dep_insn
) == INSN
1427 && GET_CODE (PATTERN (dep_insn
)) == USE
)
1429 SCHED_GROUP_P (prev_dep_insn
) = 1;
1431 /* Make a copy of all dependencies on dep_insn, and add to insn.
1432 This is so that all of the dependencies will apply to the
1435 for (link
= LOG_LINKS (dep_insn
); link
; link
= XEXP (link
, 1))
1436 add_dependence (insn
, XEXP (link
, 0), GET_MODE (link
));
1438 prev_dep_insn
= dep_insn
;
1439 dep_insn
= PREV_INSN (dep_insn
);
1444 /* Analyze every insn between HEAD and TAIL inclusive, creating LOG_LINKS
1445 for every dependency. */
1448 sched_analyze (head
, tail
)
1452 register int n_insns
= 0;
1454 register int luid
= 0;
1456 for (insn
= head
; ; insn
= NEXT_INSN (insn
))
1458 INSN_LUID (insn
) = luid
++;
1460 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
)
1462 sched_analyze_insn (PATTERN (insn
), insn
);
1465 else if (GET_CODE (insn
) == CALL_INSN
)
1471 /* Any instruction using a hard register which may get clobbered
1472 by a call needs to be marked as dependent on this call.
1473 This prevents a use of a hard return reg from being moved
1474 past a void call (i.e. it does not explicitly set the hard
1477 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1478 if (call_used_regs
[i
] || global_regs
[i
])
1480 for (u
= reg_last_uses
[i
]; u
; u
= XEXP (u
, 1))
1481 if (GET_CODE (PATTERN (XEXP (u
, 0))) != USE
)
1482 add_dependence (insn
, XEXP (u
, 0), REG_DEP_ANTI
);
1483 reg_last_uses
[i
] = 0;
1484 if (reg_last_sets
[i
]
1485 && GET_CODE (PATTERN (reg_last_sets
[i
])) != USE
)
1486 add_dependence (insn
, reg_last_sets
[i
], REG_DEP_ANTI
);
1487 reg_last_sets
[i
] = insn
;
1488 /* Insn, being a CALL_INSN, magically depends on
1489 `last_function_call' already. */
1492 /* For each insn which shouldn't cross a call, add a dependence
1493 between that insn and this call insn. */
1494 x
= LOG_LINKS (sched_before_next_call
);
1497 add_dependence (insn
, XEXP (x
, 0), REG_DEP_ANTI
);
1500 LOG_LINKS (sched_before_next_call
) = 0;
1502 sched_analyze_insn (PATTERN (insn
), insn
);
1504 /* We don't need to flush memory for a function call which does
1505 not involve memory. */
1506 if (! CONST_CALL_P (insn
))
1508 /* In the absence of interprocedural alias analysis,
1509 we must flush all pending reads and writes, and
1510 start new dependencies starting from here. */
1511 flush_pending_lists (insn
);
1514 /* Depend this function call (actually, the user of this
1515 function call) on all hard register clobberage. */
1516 last_function_call
= insn
;
1525 /* Called when we see a set of a register. If death is true, then we are
1526 scanning backwards. Mark that register as unborn. If nobody says
1527 otherwise, that is how things will remain. If death is false, then we
1528 are scanning forwards. Mark that register as being born. */
1531 sched_note_set (b
, x
, death
)
1536 register int regno
, j
;
1537 register rtx reg
= SET_DEST (x
);
1543 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == STRICT_LOW_PART
1544 || GET_CODE (reg
) == SIGN_EXTRACT
|| GET_CODE (reg
) == ZERO_EXTRACT
)
1546 /* Must treat modification of just one hardware register of a multi-reg
1547 value or just a byte field of a register exactly the same way that
1548 mark_set_1 in flow.c does. */
1549 if (GET_CODE (reg
) == ZERO_EXTRACT
1550 || GET_CODE (reg
) == SIGN_EXTRACT
1551 || (GET_CODE (reg
) == SUBREG
1552 && REG_SIZE (SUBREG_REG (reg
)) > REG_SIZE (reg
)))
1555 reg
= SUBREG_REG (reg
);
1558 if (GET_CODE (reg
) != REG
)
1561 /* Global registers are always live, so the code below does not apply
1564 regno
= REGNO (reg
);
1565 if (regno
>= FIRST_PSEUDO_REGISTER
|| ! global_regs
[regno
])
1567 register int offset
= regno
/ REGSET_ELT_BITS
;
1568 register int bit
= 1 << (regno
% REGSET_ELT_BITS
);
1572 /* If we only set part of the register, then this set does not
1577 /* Try killing this register. */
1578 if (regno
< FIRST_PSEUDO_REGISTER
)
1580 int j
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
1583 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
1584 bit
= 1 << ((regno
+ j
) % REGSET_ELT_BITS
);
1586 bb_live_regs
[offset
] &= ~bit
;
1587 bb_dead_regs
[offset
] |= bit
;
1592 bb_live_regs
[offset
] &= ~bit
;
1593 bb_dead_regs
[offset
] |= bit
;
1598 /* Make the register live again. */
1599 if (regno
< FIRST_PSEUDO_REGISTER
)
1601 int j
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
1604 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
1605 bit
= 1 << ((regno
+ j
) % REGSET_ELT_BITS
);
1607 bb_live_regs
[offset
] |= bit
;
1608 bb_dead_regs
[offset
] &= ~bit
;
1613 bb_live_regs
[offset
] |= bit
;
1614 bb_dead_regs
[offset
] &= ~bit
;
1620 /* Macros and functions for keeping the priority queue sorted, and
1621 dealing with queueing and unqueueing of instructions. */
1623 #define SCHED_SORT(READY, NEW_READY, OLD_READY) \
1624 do { if ((NEW_READY) - (OLD_READY) == 1) \
1625 swap_sort (READY, NEW_READY); \
1626 else if ((NEW_READY) - (OLD_READY) > 1) \
1627 qsort (READY, NEW_READY, sizeof (rtx), rank_for_schedule); } \
1630 /* Returns a positive value if y is preferred; returns a negative value if
1631 x is preferred. Should never return 0, since that will make the sort
1635 rank_for_schedule (x
, y
)
1640 rtx tmp_dep
, tmp2_dep
;
1641 int tmp_class
, tmp2_class
;
1644 /* Choose the instruction with the highest priority, if different. */
1645 if (value
= INSN_PRIORITY (tmp
) - INSN_PRIORITY (tmp2
))
1648 if (last_scheduled_insn
)
1650 /* Classify the instructions into three classes:
1651 1) Data dependent on last schedule insn.
1652 2) Anti/Output dependent on last scheduled insn.
1653 3) Independent of last scheduled insn, or has latency of one.
1654 Choose the insn from the highest numbered class if different. */
1655 tmp_dep
= find_insn_list (tmp
, LOG_LINKS (last_scheduled_insn
));
1656 if (tmp_dep
== 0 || insn_cost (tmp
) == 1)
1658 else if (REG_NOTE_KIND (tmp_dep
) == 0)
1663 tmp2_dep
= find_insn_list (tmp2
, LOG_LINKS (last_scheduled_insn
));
1664 if (tmp2_dep
== 0 || insn_cost (tmp2
) == 1)
1666 else if (REG_NOTE_KIND (tmp2_dep
) == 0)
1671 if (value
= tmp_class
- tmp2_class
)
1675 /* If insns are equally good, sort by INSN_LUID (original insn order),
1676 so that we make the sort stable. This minimizes instruction movement,
1677 thus minimizing sched's effect on debugging and cross-jumping. */
1678 return INSN_LUID (tmp
) - INSN_LUID (tmp2
);
1681 /* Resort the array A in which only element at index N may be out of order. */
1683 __inline
static void
1691 while (i
>= 0 && rank_for_schedule (a
+i
, &insn
) >= 0)
1699 static int max_priority
;
1701 /* Add INSN to the insn queue so that it fires at least N_CYCLES
1702 before the currently executing insn. */
1704 __inline
static void
1705 queue_insn (insn
, n_cycles
)
1709 int next_q
= NEXT_Q_AFTER (q_ptr
, n_cycles
);
1710 NEXT_INSN (insn
) = insn_queue
[next_q
];
1711 insn_queue
[next_q
] = insn
;
1715 /* Return nonzero if PAT is the pattern of an insn which makes a
1719 birthing_insn_p (pat
)
1724 if (reload_completed
== 1)
1727 if (GET_CODE (pat
) == SET
1728 && GET_CODE (SET_DEST (pat
)) == REG
)
1730 rtx dest
= SET_DEST (pat
);
1731 int i
= REGNO (dest
);
1732 int offset
= i
/ REGSET_ELT_BITS
;
1733 int bit
= 1 << (i
% REGSET_ELT_BITS
);
1735 /* It would be more accurate to use refers_to_regno_p or
1736 reg_mentioned_p to determine when the dest is not live before this
1739 if (bb_live_regs
[offset
] & bit
)
1740 return (reg_n_sets
[i
] == 1);
1744 if (GET_CODE (pat
) == PARALLEL
)
1746 for (j
= 0; j
< XVECLEN (pat
, 0); j
++)
1747 if (birthing_insn_p (XVECEXP (pat
, 0, j
)))
1753 /* If PREV is an insn which is immediately ready to execute, return 1,
1754 otherwise return 0. We may adjust its priority if that will help shorten
1755 register lifetimes. */
1761 rtx pat
= PATTERN (prev
);
1763 /* MAX of (a) number of cycles needed by prev
1764 (b) number of cycles before needed resources are free. */
1765 int n_cycles
= insn_cost (prev
);
1768 /* Trying to shorten register lives after reload has completed
1769 is useless and wrong. It gives inaccurate schedules. */
1770 if (reload_completed
== 0)
1772 for (note
= REG_NOTES (prev
); note
; note
= XEXP (note
, 1))
1773 if (REG_NOTE_KIND (note
) == REG_DEAD
)
1776 /* Defer scheduling insns which kill registers, since that
1777 shortens register lives. Prefer scheduling insns which
1778 make registers live for the same reason. */
1782 INSN_PRIORITY (prev
) >>= 3;
1785 INSN_PRIORITY (prev
) >>= 2;
1789 INSN_PRIORITY (prev
) >>= 1;
1792 if (birthing_insn_p (pat
))
1794 int max
= max_priority
;
1796 if (max
> INSN_PRIORITY (prev
))
1797 INSN_PRIORITY (prev
) = max
;
1805 queue_insn (prev
, n_cycles
);
1809 /* INSN is the "currently executing insn". Launch each insn which was
1810 waiting on INSN (in the backwards dataflow sense). READY is a
1811 vector of insns which are ready to fire. N_READY is the number of
1812 elements in READY. */
1815 launch_links (insn
, ready
, n_ready
)
1821 int new_ready
= n_ready
;
1823 if (LOG_LINKS (insn
) == 0)
1826 /* This is used by the function launch_link above. */
1828 max_priority
= MAX (INSN_PRIORITY (ready
[0]), INSN_PRIORITY (insn
));
1830 max_priority
= INSN_PRIORITY (insn
);
1832 for (link
= LOG_LINKS (insn
); link
!= 0; link
= XEXP (link
, 1))
1834 rtx prev
= XEXP (link
, 0);
1836 if ((INSN_REF_COUNT (prev
) -= 1) == 0 && launch_link (prev
))
1837 ready
[new_ready
++] = prev
;
1843 /* Add a REG_DEAD note for REG to INSN, reusing a REG_DEAD note from the
1847 create_reg_dead_note (reg
, insn
)
1850 rtx link
= dead_notes
;
1853 /* In theory, we should not end up with more REG_DEAD reg notes than we
1854 started with. In practice, this can occur as the result of bugs in
1855 flow, combine and/or sched. */
1860 link
= rtx_alloc (EXPR_LIST
);
1861 PUT_REG_NOTE_KIND (link
, REG_DEAD
);
1865 dead_notes
= XEXP (dead_notes
, 1);
1867 XEXP (link
, 0) = reg
;
1868 XEXP (link
, 1) = REG_NOTES (insn
);
1869 REG_NOTES (insn
) = link
;
1872 /* Subroutine on attach_deaths_insn--handles the recursive search
1873 through INSN. If SET_P is true, then x is being modified by the insn. */
1876 attach_deaths (x
, insn
, set_p
)
1883 register enum rtx_code code
;
1889 code
= GET_CODE (x
);
1901 /* Get rid of the easy cases first. */
1906 /* If the register dies in this insn, queue that note, and mark
1907 this register as needing to die. */
1908 /* This code is very similar to mark_used_1 (if set_p is false)
1909 and mark_set_1 (if set_p is true) in flow.c. */
1911 register int regno
= REGNO (x
);
1912 register int offset
= regno
/ REGSET_ELT_BITS
;
1913 register int bit
= 1 << (regno
% REGSET_ELT_BITS
);
1914 int all_needed
= (old_live_regs
[offset
] & bit
);
1915 int some_needed
= (old_live_regs
[offset
] & bit
);
1920 if (regno
< FIRST_PSEUDO_REGISTER
)
1924 n
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
1927 some_needed
|= (old_live_regs
[(regno
+ n
) / REGSET_ELT_BITS
]
1928 & 1 << ((regno
+ n
) % REGSET_ELT_BITS
));
1929 all_needed
&= (old_live_regs
[(regno
+ n
) / REGSET_ELT_BITS
]
1930 & 1 << ((regno
+ n
) % REGSET_ELT_BITS
));
1934 /* If it wasn't live before we started, then add a REG_DEAD note.
1935 We must check the previous lifetime info not the current info,
1936 because we may have to execute this code several times, e.g.
1937 once for a clobber (which doesn't add a note) and later
1938 for a use (which does add a note).
1940 Always make the register live. We must do this even if it was
1941 live before, because this may be an insn which sets and uses
1942 the same register, in which case the register has already been
1943 killed, so we must make it live again.
1945 Global registers are always live, and should never have a REG_DEAD
1946 note added for them, so none of the code below applies to them. */
1948 if (regno
>= FIRST_PSEUDO_REGISTER
|| ! global_regs
[regno
])
1950 /* Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1951 STACK_POINTER_REGNUM, since these are always considered to be
1952 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1953 if (regno
!= FRAME_POINTER_REGNUM
1954 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1955 && ! (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
1957 && regno
!= STACK_POINTER_REGNUM
)
1959 if (! all_needed
&& ! dead_or_set_p (insn
, x
))
1961 /* If none of the words in X is needed, make a REG_DEAD
1962 note. Otherwise, we must make partial REG_DEAD
1965 create_reg_dead_note (x
, insn
);
1970 /* Don't make a REG_DEAD note for a part of a
1971 register that is set in the insn. */
1972 for (i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
)) - 1;
1974 if ((old_live_regs
[(regno
+ i
) / REGSET_ELT_BITS
]
1975 & 1 << ((regno
+i
) % REGSET_ELT_BITS
)) == 0
1976 && ! dead_or_set_regno_p (insn
, regno
+ i
))
1977 create_reg_dead_note (gen_rtx (REG
, word_mode
,
1984 if (regno
< FIRST_PSEUDO_REGISTER
)
1986 int j
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
1989 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
1990 bit
= 1 << ((regno
+ j
) % REGSET_ELT_BITS
);
1992 bb_dead_regs
[offset
] &= ~bit
;
1993 bb_live_regs
[offset
] |= bit
;
1998 bb_dead_regs
[offset
] &= ~bit
;
1999 bb_live_regs
[offset
] |= bit
;
2006 /* Handle tail-recursive case. */
2007 attach_deaths (XEXP (x
, 0), insn
, 0);
2011 case STRICT_LOW_PART
:
2012 /* These two cases preserve the value of SET_P, so handle them
2014 attach_deaths (XEXP (x
, 0), insn
, set_p
);
2019 /* This case preserves the value of SET_P for the first operand, but
2020 clears it for the other two. */
2021 attach_deaths (XEXP (x
, 0), insn
, set_p
);
2022 attach_deaths (XEXP (x
, 1), insn
, 0);
2023 attach_deaths (XEXP (x
, 2), insn
, 0);
2027 /* Other cases: walk the insn. */
2028 fmt
= GET_RTX_FORMAT (code
);
2029 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2032 attach_deaths (XEXP (x
, i
), insn
, 0);
2033 else if (fmt
[i
] == 'E')
2034 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2035 attach_deaths (XVECEXP (x
, i
, j
), insn
, 0);
2040 /* After INSN has executed, add register death notes for each register
2041 that is dead after INSN. */
2044 attach_deaths_insn (insn
)
2047 rtx x
= PATTERN (insn
);
2048 register RTX_CODE code
= GET_CODE (x
);
2052 attach_deaths (SET_SRC (x
), insn
, 0);
2054 /* A register might die here even if it is the destination, e.g.
2055 it is the target of a volatile read and is otherwise unused.
2056 Hence we must always call attach_deaths for the SET_DEST. */
2057 attach_deaths (SET_DEST (x
), insn
, 1);
2059 else if (code
== PARALLEL
)
2062 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
2064 code
= GET_CODE (XVECEXP (x
, 0, i
));
2067 attach_deaths (SET_SRC (XVECEXP (x
, 0, i
)), insn
, 0);
2069 attach_deaths (SET_DEST (XVECEXP (x
, 0, i
)), insn
, 1);
2071 else if (code
== CLOBBER
)
2072 attach_deaths (XEXP (XVECEXP (x
, 0, i
), 0), insn
, 1);
2074 attach_deaths (XVECEXP (x
, 0, i
), insn
, 0);
2077 else if (code
== CLOBBER
)
2078 attach_deaths (XEXP (x
, 0), insn
, 1);
2080 attach_deaths (x
, insn
, 0);
2083 /* Delete notes beginning with INSN and maybe put them in the chain
2084 of notes ended by NOTE_LIST.
2085 Returns the insn following the notes. */
2088 unlink_notes (insn
, tail
)
2091 rtx prev
= PREV_INSN (insn
);
2093 while (insn
!= tail
&& GET_CODE (insn
) == NOTE
)
2095 rtx next
= NEXT_INSN (insn
);
2096 /* Delete the note from its current position. */
2098 NEXT_INSN (prev
) = next
;
2100 PREV_INSN (next
) = prev
;
2102 if (write_symbols
!= NO_DEBUG
&& NOTE_LINE_NUMBER (insn
) > 0)
2103 /* Record line-number notes so they can be reused. */
2104 LINE_NOTE (insn
) = insn
;
2107 /* Insert the note at the end of the notes list. */
2108 PREV_INSN (insn
) = note_list
;
2110 NEXT_INSN (note_list
) = insn
;
2119 /* Data structure for keeping track of register information
2120 during that register's life. */
2124 short offset
; short bit
;
2125 short live_length
; short calls_crossed
;
2128 /* Constructor for `sometimes' data structure. */
2131 new_sometimes_live (regs_sometimes_live
, offset
, bit
, sometimes_max
)
2132 struct sometimes
*regs_sometimes_live
;
2136 register struct sometimes
*p
;
2137 register int regno
= offset
* REGSET_ELT_BITS
+ bit
;
2140 /* There should never be a register greater than max_regno here. If there
2141 is, it means that a define_split has created a new pseudo reg. This
2142 is not allowed, since there will not be flow info available for any
2143 new register, so catch the error here. */
2144 if (regno
>= max_regno
)
2147 p
= ®s_sometimes_live
[sometimes_max
];
2151 p
->calls_crossed
= 0;
2153 return sometimes_max
;
2156 /* Count lengths of all regs we are currently tracking,
2157 and find new registers no longer live. */
2160 finish_sometimes_live (regs_sometimes_live
, sometimes_max
)
2161 struct sometimes
*regs_sometimes_live
;
2166 for (i
= 0; i
< sometimes_max
; i
++)
2168 register struct sometimes
*p
= ®s_sometimes_live
[i
];
2171 regno
= p
->offset
* REGSET_ELT_BITS
+ p
->bit
;
2173 sched_reg_live_length
[regno
] += p
->live_length
;
2174 sched_reg_n_calls_crossed
[regno
] += p
->calls_crossed
;
2178 /* Use modified list scheduling to rearrange insns in basic block
2179 B. FILE, if nonzero, is where we dump interesting output about
2183 schedule_block (b
, file
)
2190 int i
, j
, n_ready
= 0, new_ready
, n_insns
= 0;
2191 int sched_n_insns
= 0;
2192 #define NEED_NOTHING 0
2197 /* HEAD and TAIL delimit the region being scheduled. */
2198 rtx head
= basic_block_head
[b
];
2199 rtx tail
= basic_block_end
[b
];
2200 /* PREV_HEAD and NEXT_TAIL are the boundaries of the insns
2201 being scheduled. When the insns have been ordered,
2202 these insns delimit where the new insns are to be
2203 spliced back into the insn chain. */
2207 /* Keep life information accurate. */
2208 register struct sometimes
*regs_sometimes_live
;
2212 fprintf (file
, ";;\t -- basic block number %d from %d to %d --\n",
2213 b
, INSN_UID (basic_block_head
[b
]), INSN_UID (basic_block_end
[b
]));
2216 reg_last_uses
= (rtx
*) alloca (i
* sizeof (rtx
));
2217 bzero (reg_last_uses
, i
* sizeof (rtx
));
2218 reg_last_sets
= (rtx
*) alloca (i
* sizeof (rtx
));
2219 bzero (reg_last_sets
, i
* sizeof (rtx
));
2221 /* Remove certain insns at the beginning from scheduling,
2222 by advancing HEAD. */
2224 /* At the start of a function, before reload has run, don't delay getting
2225 parameters from hard registers into pseudo registers. */
2226 if (reload_completed
== 0 && b
== 0)
2229 && GET_CODE (head
) == NOTE
2230 && NOTE_LINE_NUMBER (head
) != NOTE_INSN_FUNCTION_BEG
)
2231 head
= NEXT_INSN (head
);
2233 && GET_CODE (head
) == INSN
2234 && GET_CODE (PATTERN (head
)) == SET
)
2236 rtx src
= SET_SRC (PATTERN (head
));
2237 while (GET_CODE (src
) == SUBREG
2238 || GET_CODE (src
) == SIGN_EXTEND
2239 || GET_CODE (src
) == ZERO_EXTEND
2240 || GET_CODE (src
) == SIGN_EXTRACT
2241 || GET_CODE (src
) == ZERO_EXTRACT
)
2242 src
= XEXP (src
, 0);
2243 if (GET_CODE (src
) != REG
2244 || REGNO (src
) >= FIRST_PSEUDO_REGISTER
)
2246 /* Keep this insn from ever being scheduled. */
2247 INSN_REF_COUNT (head
) = 1;
2248 head
= NEXT_INSN (head
);
2252 /* Don't include any notes or labels at the beginning of the
2253 basic block, or notes at the ends of basic blocks. */
2254 while (head
!= tail
)
2256 if (GET_CODE (head
) == NOTE
)
2257 head
= NEXT_INSN (head
);
2258 else if (GET_CODE (tail
) == NOTE
)
2259 tail
= PREV_INSN (tail
);
2260 else if (GET_CODE (head
) == CODE_LABEL
)
2261 head
= NEXT_INSN (head
);
2264 /* If the only insn left is a NOTE or a CODE_LABEL, then there is no need
2265 to schedule this block. */
2267 && (GET_CODE (head
) == NOTE
|| GET_CODE (head
) == CODE_LABEL
))
2271 /* This short-cut doesn't work. It does not count call insns crossed by
2272 registers in reg_sometimes_live. It does not mark these registers as
2273 dead if they die in this block. It does not mark these registers live
2274 (or create new reg_sometimes_live entries if necessary) if they are born
2277 The easy solution is to just always schedule a block. This block only
2278 has one insn, so this won't slow down this pass by much. */
2284 /* Exclude certain insns at the end of the basic block by advancing TAIL. */
2285 /* This isn't correct. Instead of advancing TAIL, should assign very
2286 high priorities to these insns to guarantee that they get scheduled last.
2287 If these insns are ignored, as is currently done, the register life info
2288 may be incorrectly computed. */
2289 if (GET_CODE (tail
) == INSN
2290 && GET_CODE (PATTERN (tail
)) == USE
2291 && next_nonnote_insn (tail
) == 0)
2293 /* Don't try to reorder any USE insns at the end of a function.
2294 They must be last to ensure proper register allocation.
2295 Exclude them all from scheduling. */
2298 /* If we are down to one USE insn, then there are no insns to
2303 tail
= prev_nonnote_insn (tail
);
2305 while (GET_CODE (tail
) == INSN
2306 && GET_CODE (PATTERN (tail
)) == USE
);
2309 /* This short-cut does not work. See comment above. */
2314 else if (GET_CODE (tail
) == JUMP_INSN
2315 && SCHED_GROUP_P (tail
) == 0
2316 && GET_CODE (PREV_INSN (tail
)) == INSN
2317 && GET_CODE (PATTERN (PREV_INSN (tail
))) == USE
2318 && REG_FUNCTION_VALUE_P (XEXP (PATTERN (PREV_INSN (tail
)), 0)))
2320 /* Don't let the setting of the function's return value register
2321 move from this jump. For the same reason we want to get the
2322 parameters into pseudo registers as quickly as possible, we
2323 want to set the function's return value register as late as
2326 /* If this is the only insn in the block, then there is no need to
2327 schedule the block. */
2331 tail
= PREV_INSN (tail
);
2335 tail
= prev_nonnote_insn (tail
);
2338 /* This shortcut does not work. See comment above. */
2345 /* This is probably wrong. Instead of doing this, should give this insn
2346 a very high priority to guarantee that it gets scheduled last. */
2347 /* Can not separate an insn that sets the condition code from one that
2348 uses it. So we must leave an insn that sets cc0 where it is. */
2349 if (sets_cc0_p (PATTERN (tail
)))
2350 tail
= PREV_INSN (tail
);
2353 /* Now HEAD through TAIL are the insns actually to be rearranged;
2354 Let PREV_HEAD and NEXT_TAIL enclose them. */
2355 prev_head
= PREV_INSN (head
);
2356 next_tail
= NEXT_INSN (tail
);
2358 /* Initialize basic block data structures. */
2360 pending_read_insns
= 0;
2361 pending_read_mems
= 0;
2362 pending_write_insns
= 0;
2363 pending_write_mems
= 0;
2364 pending_lists_length
= 0;
2365 last_pending_memory_flush
= 0;
2366 last_function_call
= 0;
2367 last_scheduled_insn
= 0;
2369 LOG_LINKS (sched_before_next_call
) = 0;
2371 n_insns
+= sched_analyze (head
, tail
);
2374 free_pending_lists ();
2378 /* Allocate vector to hold insns to be rearranged (except those
2379 insns which are controlled by an insn with SCHED_GROUP_P set).
2380 All these insns are included between ORIG_HEAD and ORIG_TAIL,
2381 as those variables ultimately are set up. */
2382 ready
= (rtx
*) alloca ((n_insns
+1) * sizeof (rtx
));
2384 /* TAIL is now the last of the insns to be rearranged.
2385 Put those insns into the READY vector. */
2388 /* If the last insn is a branch, force it to be the last insn after
2389 scheduling. Also, don't try to reorder calls at the ends the basic
2390 block -- this will only lead to worse register allocation. */
2391 if (GET_CODE (tail
) == CALL_INSN
|| GET_CODE (tail
) == JUMP_INSN
)
2394 ready
[n_ready
++] = tail
;
2395 INSN_PRIORITY (tail
) = TAIL_PRIORITY
;
2396 INSN_REF_COUNT (tail
) = 0;
2397 insn
= PREV_INSN (tail
);
2400 /* Assign priorities to instructions. Also check whether they
2401 are in priority order already. If so then I will be nonnegative.
2402 We use this shortcut only before reloading. */
2404 i
= reload_completed
? DONE_PRIORITY
: MAX_PRIORITY
;
2407 for (; insn
!= prev_head
; insn
= PREV_INSN (insn
))
2409 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
2412 if (INSN_REF_COUNT (insn
) == 0)
2413 ready
[n_ready
++] = insn
;
2414 if (SCHED_GROUP_P (insn
))
2416 while (SCHED_GROUP_P (insn
))
2418 insn
= PREV_INSN (insn
);
2419 while (GET_CODE (insn
) == NOTE
)
2420 insn
= PREV_INSN (insn
);
2428 if (INSN_PRIORITY (insn
) < i
)
2429 i
= INSN_PRIORITY (insn
);
2430 else if (INSN_PRIORITY (insn
) > i
)
2437 /* This short-cut doesn't work. It does not count call insns crossed by
2438 registers in reg_sometimes_live. It does not mark these registers as
2439 dead if they die in this block. It does not mark these registers live
2440 (or create new reg_sometimes_live entries if necessary) if they are born
2443 The easy solution is to just always schedule a block. These blocks tend
2444 to be very short, so this doesn't slow down this pass by much. */
2446 /* If existing order is good, don't bother to reorder. */
2447 if (i
!= DONE_PRIORITY
)
2450 fprintf (file
, ";; already scheduled\n");
2452 if (reload_completed
== 0)
2454 for (i
= 0; i
< sometimes_max
; i
++)
2455 regs_sometimes_live
[i
].live_length
+= n_insns
;
2457 finish_sometimes_live (regs_sometimes_live
, sometimes_max
);
2459 free_pending_lists ();
2464 /* Scan all the insns to be scheduled, removing NOTE insns
2465 and register death notes.
2466 Line number NOTE insns end up in NOTE_LIST.
2467 Register death notes end up in DEAD_NOTES.
2469 Recreate the register life information for the end of this basic
2472 if (reload_completed
== 0)
2474 bcopy (basic_block_live_at_start
[b
], bb_live_regs
, regset_bytes
);
2475 bzero (bb_dead_regs
, regset_bytes
);
2479 /* This is the first block in the function. There may be insns
2480 before head that we can't schedule. We still need to examine
2481 them though for accurate register lifetime analysis. */
2483 /* We don't want to remove any REG_DEAD notes as the code below
2486 for (insn
= basic_block_head
[b
]; insn
!= head
;
2487 insn
= NEXT_INSN (insn
))
2488 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
2490 /* See if the register gets born here. */
2491 /* We must check for registers being born before we check for
2492 registers dying. It is possible for a register to be born
2493 and die in the same insn, e.g. reading from a volatile
2494 memory location into an otherwise unused register. Such
2495 a register must be marked as dead after this insn. */
2496 if (GET_CODE (PATTERN (insn
)) == SET
2497 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
2498 sched_note_set (b
, PATTERN (insn
), 0);
2499 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
2502 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
2503 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == SET
2504 || GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == CLOBBER
)
2505 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 0);
2507 /* ??? This code is obsolete and should be deleted. It
2508 is harmless though, so we will leave it in for now. */
2509 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
2510 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == USE
)
2511 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 0);
2514 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2516 if ((REG_NOTE_KIND (link
) == REG_DEAD
2517 || REG_NOTE_KIND (link
) == REG_UNUSED
)
2518 /* Verify that the REG_NOTE has a legal value. */
2519 && GET_CODE (XEXP (link
, 0)) == REG
)
2521 register int regno
= REGNO (XEXP (link
, 0));
2522 register int offset
= regno
/ REGSET_ELT_BITS
;
2523 register int bit
= 1 << (regno
% REGSET_ELT_BITS
);
2525 if (regno
< FIRST_PSEUDO_REGISTER
)
2527 int j
= HARD_REGNO_NREGS (regno
,
2528 GET_MODE (XEXP (link
, 0)));
2531 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
2532 bit
= 1 << ((regno
+ j
) % REGSET_ELT_BITS
);
2534 bb_live_regs
[offset
] &= ~bit
;
2535 bb_dead_regs
[offset
] |= bit
;
2540 bb_live_regs
[offset
] &= ~bit
;
2541 bb_dead_regs
[offset
] |= bit
;
2549 /* If debugging information is being produced, keep track of the line
2550 number notes for each insn. */
2551 if (write_symbols
!= NO_DEBUG
)
2553 /* We must use the true line number for the first insn in the block
2554 that was computed and saved at the start of this pass. We can't
2555 use the current line number, because scheduling of the previous
2556 block may have changed the current line number. */
2557 rtx line
= line_note_head
[b
];
2559 for (insn
= basic_block_head
[b
];
2561 insn
= NEXT_INSN (insn
))
2562 if (GET_CODE (insn
) == NOTE
&& NOTE_LINE_NUMBER (insn
) > 0)
2565 LINE_NOTE (insn
) = line
;
2568 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
2570 rtx prev
, next
, link
;
2572 /* Farm out notes. This is needed to keep the debugger from
2573 getting completely deranged. */
2574 if (GET_CODE (insn
) == NOTE
)
2577 insn
= unlink_notes (insn
, next_tail
);
2582 if (insn
== next_tail
)
2586 if (reload_completed
== 0
2587 && GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
2589 /* See if the register gets born here. */
2590 /* We must check for registers being born before we check for
2591 registers dying. It is possible for a register to be born and
2592 die in the same insn, e.g. reading from a volatile memory
2593 location into an otherwise unused register. Such a register
2594 must be marked as dead after this insn. */
2595 if (GET_CODE (PATTERN (insn
)) == SET
2596 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
2597 sched_note_set (b
, PATTERN (insn
), 0);
2598 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
2601 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
2602 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == SET
2603 || GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == CLOBBER
)
2604 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 0);
2606 /* ??? This code is obsolete and should be deleted. It
2607 is harmless though, so we will leave it in for now. */
2608 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
2609 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == USE
)
2610 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 0);
2613 /* Need to know what registers this insn kills. */
2614 for (prev
= 0, link
= REG_NOTES (insn
); link
; link
= next
)
2618 next
= XEXP (link
, 1);
2619 if ((REG_NOTE_KIND (link
) == REG_DEAD
2620 || REG_NOTE_KIND (link
) == REG_UNUSED
)
2621 /* Verify that the REG_NOTE has a legal value. */
2622 && GET_CODE (XEXP (link
, 0)) == REG
)
2624 register int regno
= REGNO (XEXP (link
, 0));
2625 register int offset
= regno
/ REGSET_ELT_BITS
;
2626 register int bit
= 1 << (regno
% REGSET_ELT_BITS
);
2628 /* Only unlink REG_DEAD notes; leave REG_UNUSED notes
2630 if (REG_NOTE_KIND (link
) == REG_DEAD
)
2633 XEXP (prev
, 1) = next
;
2635 REG_NOTES (insn
) = next
;
2636 XEXP (link
, 1) = dead_notes
;
2642 if (regno
< FIRST_PSEUDO_REGISTER
)
2644 int j
= HARD_REGNO_NREGS (regno
,
2645 GET_MODE (XEXP (link
, 0)));
2648 offset
= (regno
+ j
) / REGSET_ELT_BITS
;
2649 bit
= 1 << ((regno
+ j
) % REGSET_ELT_BITS
);
2651 bb_live_regs
[offset
] &= ~bit
;
2652 bb_dead_regs
[offset
] |= bit
;
2657 bb_live_regs
[offset
] &= ~bit
;
2658 bb_dead_regs
[offset
] |= bit
;
2667 if (reload_completed
== 0)
2669 /* Keep track of register lives. */
2670 old_live_regs
= (regset
) alloca (regset_bytes
);
2672 = (struct sometimes
*) alloca (max_regno
* sizeof (struct sometimes
));
2675 /* Start with registers live at end. */
2676 for (j
= 0; j
< regset_size
; j
++)
2678 int live
= bb_live_regs
[j
];
2679 old_live_regs
[j
] = live
;
2683 for (bit
= 0; bit
< REGSET_ELT_BITS
; bit
++)
2684 if (live
& (1 << bit
))
2685 sometimes_max
= new_sometimes_live (regs_sometimes_live
, j
,
2686 bit
, sometimes_max
);
2691 SCHED_SORT (ready
, n_ready
, 1);
2695 fprintf (file
, ";; ready list initially:\n;; ");
2696 for (i
= 0; i
< n_ready
; i
++)
2697 fprintf (file
, "%d ", INSN_UID (ready
[i
]));
2698 fprintf (file
, "\n\n");
2700 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
2701 if (INSN_PRIORITY (insn
) > 0)
2702 fprintf (file
, ";; insn[%4d]: priority = %4d, ref_count = %4d\n",
2703 INSN_UID (insn
), INSN_PRIORITY (insn
),
2704 INSN_REF_COUNT (insn
));
2707 /* Now HEAD and TAIL are going to become disconnected
2708 entirely from the insn chain. */
2711 /* Q_SIZE will always be zero here. */
2713 bzero (insn_queue
, sizeof (insn_queue
));
2715 /* Now, perform list scheduling. */
2717 /* Where we start inserting insns is after TAIL. */
2720 new_needs
= (NEXT_INSN (prev_head
) == basic_block_head
[b
]
2721 ? NEED_HEAD
: NEED_NOTHING
);
2722 if (PREV_INSN (next_tail
) == basic_block_end
[b
])
2723 new_needs
|= NEED_TAIL
;
2725 new_ready
= n_ready
;
2726 while (sched_n_insns
< n_insns
)
2728 q_ptr
= NEXT_Q (q_ptr
);
2730 /* Add all pending insns that can be scheduled without stalls to the
2732 for (insn
= insn_queue
[q_ptr
]; insn
; insn
= NEXT_INSN (insn
))
2735 fprintf (file
, ";; launching %d before %d with no stalls\n",
2736 INSN_UID (insn
), INSN_UID (last
));
2737 ready
[new_ready
++] = insn
;
2740 insn_queue
[q_ptr
] = 0;
2742 /* If there are no ready insns, stall until one is ready and add all
2743 of the pending insns at that point to the ready list. */
2746 register int stalls
;
2748 for (stalls
= 1; stalls
< Q_SIZE
; stalls
++)
2749 if (insn
= insn_queue
[NEXT_Q_AFTER (q_ptr
, stalls
)])
2751 for (; insn
; insn
= NEXT_INSN (insn
))
2754 fprintf (file
, ";; issue insn %d before %d with %d stalls\n",
2755 INSN_UID (insn
), INSN_UID (last
), stalls
);
2756 ready
[new_ready
++] = insn
;
2759 insn_queue
[NEXT_Q_AFTER (q_ptr
, stalls
)] = 0;
2764 /* This looks logically correct, but on the SPEC benchmark set on
2765 the SPARC, I get better code without it. */
2766 q_ptr
= NEXT_Q_AFTER (q_ptr
, stalls
);
2770 /* There should be some instructions waiting to fire. */
2774 /* Sort the ready list and choose the best insn to schedule.
2775 N_READY holds the number of items that were scheduled the last time,
2776 minus the one instruction scheduled on the last loop iteration; it
2777 is not modified for any other reason in this loop. */
2778 SCHED_SORT (ready
, new_ready
, n_ready
);
2779 n_ready
= new_ready
;
2780 last_scheduled_insn
= insn
= ready
[0];
2782 if (DONE_PRIORITY_P (insn
))
2785 if (reload_completed
== 0)
2787 /* Process this insn, and each insn linked to this one which must
2788 be immediately output after this insn. */
2791 /* First we kill registers set by this insn, and then we
2792 make registers used by this insn live. This is the opposite
2793 order used above because we are traversing the instructions
2796 /* Strictly speaking, we should scan REG_UNUSED notes and make
2797 every register mentioned there live, however, we will just
2798 kill them again immediately below, so there doesn't seem to
2799 be any reason why we bother to do this. */
2801 /* See if this is the last notice we must take of a register. */
2802 if (GET_CODE (PATTERN (insn
)) == SET
2803 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
2804 sched_note_set (b
, PATTERN (insn
), 1);
2805 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
2808 for (j
= XVECLEN (PATTERN (insn
), 0) - 1; j
>= 0; j
--)
2809 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == SET
2810 || GET_CODE (XVECEXP (PATTERN (insn
), 0, j
)) == CLOBBER
)
2811 sched_note_set (b
, XVECEXP (PATTERN (insn
), 0, j
), 1);
2814 /* This code keeps life analysis information up to date. */
2815 if (GET_CODE (insn
) == CALL_INSN
)
2817 register struct sometimes
*p
;
2819 /* A call kills all call used and global registers, except
2820 for those mentioned in the call pattern which will be
2821 made live again later. */
2822 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2823 if (call_used_regs
[i
] || global_regs
[i
])
2825 register int offset
= i
/ REGSET_ELT_BITS
;
2826 register int bit
= 1 << (i
% REGSET_ELT_BITS
);
2828 bb_live_regs
[offset
] &= ~bit
;
2829 bb_dead_regs
[offset
] |= bit
;
2832 /* Regs live at the time of a call instruction must not
2833 go in a register clobbered by calls. Record this for
2834 all regs now live. Note that insns which are born or
2835 die in a call do not cross a call, so this must be done
2836 after the killings (above) and before the births
2838 p
= regs_sometimes_live
;
2839 for (i
= 0; i
< sometimes_max
; i
++, p
++)
2840 if (bb_live_regs
[p
->offset
] & (1 << p
->bit
))
2841 p
->calls_crossed
+= 1;
2844 /* Make every register used live, and add REG_DEAD notes for
2845 registers which were not live before we started. */
2846 attach_deaths_insn (insn
);
2848 /* Find registers now made live by that instruction. */
2849 for (i
= 0; i
< regset_size
; i
++)
2851 int diff
= bb_live_regs
[i
] & ~old_live_regs
[i
];
2855 old_live_regs
[i
] |= diff
;
2856 for (bit
= 0; bit
< REGSET_ELT_BITS
; bit
++)
2857 if (diff
& (1 << bit
))
2859 = new_sometimes_live (regs_sometimes_live
, i
, bit
,
2864 /* Count lengths of all regs we are worrying about now,
2865 and handle registers no longer live. */
2867 for (i
= 0; i
< sometimes_max
; i
++)
2869 register struct sometimes
*p
= ®s_sometimes_live
[i
];
2870 int regno
= p
->offset
*REGSET_ELT_BITS
+ p
->bit
;
2872 p
->live_length
+= 1;
2874 if ((bb_live_regs
[p
->offset
] & (1 << p
->bit
)) == 0)
2876 /* This is the end of one of this register's lifetime
2877 segments. Save the lifetime info collected so far,
2878 and clear its bit in the old_live_regs entry. */
2879 sched_reg_live_length
[regno
] += p
->live_length
;
2880 sched_reg_n_calls_crossed
[regno
] += p
->calls_crossed
;
2881 old_live_regs
[p
->offset
] &= ~(1 << p
->bit
);
2883 /* Delete the reg_sometimes_live entry for this reg by
2884 copying the last entry over top of it. */
2885 *p
= regs_sometimes_live
[--sometimes_max
];
2886 /* ...and decrement i so that this newly copied entry
2887 will be processed. */
2893 insn
= PREV_INSN (insn
);
2895 while (SCHED_GROUP_P (link
));
2897 /* Set INSN back to the insn we are scheduling now. */
2901 /* Schedule INSN. Remove it from the ready list. */
2906 NEXT_INSN (insn
) = last
;
2907 PREV_INSN (last
) = insn
;
2910 /* Everything that precedes INSN now either becomes "ready", if
2911 it can execute immediately before INSN, or "pending", if
2912 there must be a delay. Give INSN high enough priority that
2913 at least one (maybe more) reg-killing insns can be launched
2914 ahead of all others. Mark INSN as scheduled by changing its
2916 INSN_PRIORITY (insn
) = LAUNCH_PRIORITY
;
2917 new_ready
= launch_links (insn
, ready
, n_ready
);
2918 INSN_PRIORITY (insn
) = DONE_PRIORITY
;
2920 /* Schedule all prior insns that must not be moved. */
2921 if (SCHED_GROUP_P (insn
))
2923 /* Disable these insns from being launched. */
2925 while (SCHED_GROUP_P (link
))
2927 /* Disable these insns from being launched by anybody. */
2928 link
= PREV_INSN (link
);
2929 INSN_REF_COUNT (link
) = 0;
2932 /* None of these insns can move forward into delay slots. */
2933 while (SCHED_GROUP_P (insn
))
2935 insn
= PREV_INSN (insn
);
2936 new_ready
= launch_links (insn
, ready
, new_ready
);
2937 INSN_PRIORITY (insn
) = DONE_PRIORITY
;
2940 NEXT_INSN (insn
) = last
;
2941 PREV_INSN (last
) = insn
;
2949 if (reload_completed
== 0)
2950 finish_sometimes_live (regs_sometimes_live
, sometimes_max
);
2952 /* HEAD is now the first insn in the chain of insns that
2953 been scheduled by the loop above.
2954 TAIL is the last of those insns. */
2957 /* NOTE_LIST is the end of a chain of notes previously found
2958 among the insns. Insert them at the beginning of the insns. */
2961 rtx note_head
= note_list
;
2962 while (PREV_INSN (note_head
))
2963 note_head
= PREV_INSN (note_head
);
2965 PREV_INSN (head
) = note_list
;
2966 NEXT_INSN (note_list
) = head
;
2970 /* In theory, there should be no REG_DEAD notes leftover at the end.
2971 In practice, this can occur as the result of bugs in flow, combine.c,
2972 and/or sched.c. The values of the REG_DEAD notes remaining are
2973 meaningless, because dead_notes is just used as a free list. */
2975 if (dead_notes
!= 0)
2979 if (new_needs
& NEED_HEAD
)
2980 basic_block_head
[b
] = head
;
2981 PREV_INSN (head
) = prev_head
;
2982 NEXT_INSN (prev_head
) = head
;
2984 if (new_needs
& NEED_TAIL
)
2985 basic_block_end
[b
] = tail
;
2986 NEXT_INSN (tail
) = next_tail
;
2987 PREV_INSN (next_tail
) = tail
;
2989 /* Restore the line-number notes of each insn. */
2990 if (write_symbols
!= NO_DEBUG
)
2992 rtx line
, note
, prev
, new;
2995 head
= basic_block_head
[b
];
2996 next_tail
= NEXT_INSN (basic_block_end
[b
]);
2998 /* Determine the current line-number. We want to know the current
2999 line number of the first insn of the block here, in case it is
3000 different from the true line number that was saved earlier. If
3001 different, then we need a line number note before the first insn
3002 of this block. If it happens to be the same, then we don't want to
3003 emit another line number note here. */
3004 for (line
= head
; line
; line
= PREV_INSN (line
))
3005 if (GET_CODE (line
) == NOTE
&& NOTE_LINE_NUMBER (line
) > 0)
3008 /* Walk the insns keeping track of the current line-number and inserting
3009 the line-number notes as needed. */
3010 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
3011 if (GET_CODE (insn
) == NOTE
&& NOTE_LINE_NUMBER (insn
) > 0)
3013 else if (! (GET_CODE (insn
) == NOTE
3014 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_DELETED
)
3015 && (note
= LINE_NOTE (insn
)) != 0
3018 || NOTE_LINE_NUMBER (note
) != NOTE_LINE_NUMBER (line
)
3019 || NOTE_SOURCE_FILE (note
) != NOTE_SOURCE_FILE (line
)))
3022 prev
= PREV_INSN (insn
);
3023 if (LINE_NOTE (note
))
3025 /* Re-use the orignal line-number note. */
3026 LINE_NOTE (note
) = 0;
3027 PREV_INSN (note
) = prev
;
3028 NEXT_INSN (prev
) = note
;
3029 PREV_INSN (insn
) = note
;
3030 NEXT_INSN (note
) = insn
;
3035 new = emit_note_after (NOTE_LINE_NUMBER (note
), prev
);
3036 NOTE_SOURCE_FILE (new) = NOTE_SOURCE_FILE (note
);
3040 fprintf (file
, ";; added %d line-number notes\n", notes
);
3045 fprintf (file
, ";; new basic block head = %d\n;; new basic block end = %d\n\n",
3046 INSN_UID (basic_block_head
[b
]), INSN_UID (basic_block_end
[b
]));
3049 /* Yow! We're done! */
3050 free_pending_lists ();
3055 /* Subroutine of split_hard_reg_notes. Searches X for any reference to
3056 REGNO, returning the rtx of the reference found if any. Otherwise,
3060 regno_use_in (regno
, x
)
3068 if (GET_CODE (x
) == REG
&& REGNO (x
) == regno
)
3071 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3072 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3076 if (tem
= regno_use_in (regno
, XEXP (x
, i
)))
3079 else if (fmt
[i
] == 'E')
3080 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3081 if (tem
= regno_use_in (regno
, XVECEXP (x
, i
, j
)))
3088 /* Subroutine of update_flow_info. Determines whether any new REG_NOTEs are
3089 needed for the hard register mentioned in the note. This can happen
3090 if the reference to the hard register in the original insn was split into
3091 several smaller hard register references in the split insns. */
3094 split_hard_reg_notes (note
, first
, last
, orig_insn
)
3095 rtx note
, first
, last
, orig_insn
;
3097 rtx reg
, temp
, link
;
3098 int n_regs
, i
, new_reg
;
3101 /* Assume that this is a REG_DEAD note. */
3102 if (REG_NOTE_KIND (note
) != REG_DEAD
)
3105 reg
= XEXP (note
, 0);
3107 n_regs
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
3109 /* ??? Could add check here to see whether, the hard register is referenced
3110 in the same mode as in the original insn. If so, then it has not been
3111 split, and the rest of the code below is unnecessary. */
3113 for (i
= 1; i
< n_regs
; i
++)
3115 new_reg
= REGNO (reg
) + i
;
3117 /* Check for references to new_reg in the split insns. */
3118 for (insn
= last
; ; insn
= PREV_INSN (insn
))
3120 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
3121 && (temp
= regno_use_in (new_reg
, PATTERN (insn
))))
3123 /* Create a new reg dead note here. */
3124 link
= rtx_alloc (EXPR_LIST
);
3125 PUT_REG_NOTE_KIND (link
, REG_DEAD
);
3126 XEXP (link
, 0) = temp
;
3127 XEXP (link
, 1) = REG_NOTES (insn
);
3128 REG_NOTES (insn
) = link
;
3131 /* It isn't mentioned anywhere, so no new reg note is needed for
3139 /* Subroutine of update_flow_info. Determines whether a SET or CLOBBER in an
3140 insn created by splitting needs a REG_DEAD or REG_UNUSED note added. */
3143 new_insn_dead_notes (pat
, insn
, last
, orig_insn
)
3144 rtx pat
, insn
, last
, orig_insn
;
3148 /* PAT is either a CLOBBER or a SET here. */
3149 dest
= XEXP (pat
, 0);
3151 while (GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SUBREG
3152 || GET_CODE (dest
) == STRICT_LOW_PART
3153 || GET_CODE (dest
) == SIGN_EXTRACT
)
3154 dest
= XEXP (dest
, 0);
3156 if (GET_CODE (dest
) == REG
)
3158 for (tem
= last
; tem
!= insn
; tem
= PREV_INSN (tem
))
3160 if (GET_RTX_CLASS (GET_CODE (tem
)) == 'i'
3161 && reg_overlap_mentioned_p (dest
, PATTERN (tem
))
3162 && (set
= single_set (tem
)))
3164 rtx tem_dest
= SET_DEST (set
);
3166 while (GET_CODE (tem_dest
) == ZERO_EXTRACT
3167 || GET_CODE (tem_dest
) == SUBREG
3168 || GET_CODE (tem_dest
) == STRICT_LOW_PART
3169 || GET_CODE (tem_dest
) == SIGN_EXTRACT
)
3170 tem_dest
= XEXP (tem_dest
, 0);
3172 if (tem_dest
!= dest
)
3174 /* Use the same scheme as combine.c, don't put both REG_DEAD
3175 and REG_UNUSED notes on the same insn. */
3176 if (! find_regno_note (tem
, REG_UNUSED
, REGNO (dest
))
3177 && ! find_regno_note (tem
, REG_DEAD
, REGNO (dest
)))
3179 rtx note
= rtx_alloc (EXPR_LIST
);
3180 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
3181 XEXP (note
, 0) = dest
;
3182 XEXP (note
, 1) = REG_NOTES (tem
);
3183 REG_NOTES (tem
) = note
;
3185 /* The reg only dies in one insn, the last one that uses
3189 else if (reg_overlap_mentioned_p (dest
, SET_SRC (set
)))
3190 /* We found an instruction that both uses the register,
3191 and sets it, so no new REG_NOTE is needed for this set. */
3195 /* If this is a set, it must die somewhere, unless it is the dest of
3196 the original insn, and hence is live after the original insn. Abort
3197 if it isn't supposed to be live after the original insn.
3199 If this is a clobber, then just add a REG_UNUSED note. */
3202 int live_after_orig_insn
= 0;
3203 rtx pattern
= PATTERN (orig_insn
);
3206 if (GET_CODE (pat
) == CLOBBER
)
3208 rtx note
= rtx_alloc (EXPR_LIST
);
3209 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
3210 XEXP (note
, 0) = dest
;
3211 XEXP (note
, 1) = REG_NOTES (insn
);
3212 REG_NOTES (insn
) = note
;
3216 /* The original insn could have multiple sets, so search the
3217 insn for all sets. */
3218 if (GET_CODE (pattern
) == SET
)
3220 if (reg_overlap_mentioned_p (dest
, SET_DEST (pattern
)))
3221 live_after_orig_insn
= 1;
3223 else if (GET_CODE (pattern
) == PARALLEL
)
3225 for (i
= 0; i
< XVECLEN (pattern
, 0); i
++)
3226 if (GET_CODE (XVECEXP (pattern
, 0, i
)) == SET
3227 && reg_overlap_mentioned_p (dest
,
3228 SET_DEST (XVECEXP (pattern
,
3230 live_after_orig_insn
= 1;
3233 if (! live_after_orig_insn
)
3239 /* Subroutine of update_flow_info. Update the value of reg_n_sets for all
3240 registers modified by X. INC is -1 if the containing insn is being deleted,
3241 and is 1 if the containing insn is a newly generated insn. */
3244 update_n_sets (x
, inc
)
3248 rtx dest
= SET_DEST (x
);
3250 while (GET_CODE (dest
) == STRICT_LOW_PART
|| GET_CODE (dest
) == SUBREG
3251 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SIGN_EXTRACT
)
3252 dest
= SUBREG_REG (dest
);
3254 if (GET_CODE (dest
) == REG
)
3256 int regno
= REGNO (dest
);
3258 if (regno
< FIRST_PSEUDO_REGISTER
)
3261 int endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (dest
));
3263 for (i
= regno
; i
< endregno
; i
++)
3264 reg_n_sets
[i
] += inc
;
3267 reg_n_sets
[regno
] += inc
;
3271 /* Updates all flow-analysis related quantities (including REG_NOTES) for
3272 the insns from FIRST to LAST inclusive that were created by splitting
3273 ORIG_INSN. NOTES are the original REG_NOTES. */
3276 update_flow_info (notes
, first
, last
, orig_insn
)
3283 rtx orig_dest
, temp
;
3286 /* Get and save the destination set by the original insn. */
3288 orig_dest
= single_set (orig_insn
);
3290 orig_dest
= SET_DEST (orig_dest
);
3292 /* Move REG_NOTES from the original insn to where they now belong. */
3294 for (note
= notes
; note
; note
= next
)
3296 next
= XEXP (note
, 1);
3297 switch (REG_NOTE_KIND (note
))
3301 /* Move these notes from the original insn to the last new insn where
3302 the register is now set. */
3304 for (insn
= last
; ; insn
= PREV_INSN (insn
))
3306 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
3307 && reg_mentioned_p (XEXP (note
, 0), PATTERN (insn
)))
3309 XEXP (note
, 1) = REG_NOTES (insn
);
3310 REG_NOTES (insn
) = note
;
3312 /* Sometimes need to convert REG_UNUSED notes to REG_DEAD
3314 /* ??? This won't handle mutiple word registers correctly,
3315 but should be good enough for now. */
3316 if (REG_NOTE_KIND (note
) == REG_UNUSED
3317 && ! dead_or_set_p (insn
, XEXP (note
, 0)))
3318 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
3320 /* The reg only dies in one insn, the last one that uses
3324 /* It must die somewhere, fail it we couldn't find where it died.
3326 If this is a REG_UNUSED note, then it must be a temporary
3327 register that was not needed by this instantiation of the
3328 pattern, so we can safely ignore it. */
3331 if (REG_NOTE_KIND (note
) != REG_UNUSED
)
3338 /* If this note refers to a multiple word hard register, it may
3339 have been split into several smaller hard register references.
3340 Check to see if there are any new register references that
3341 need REG_NOTES added for them. */
3342 temp
= XEXP (note
, 0);
3343 if (REG_NOTE_KIND (note
) == REG_DEAD
3344 && GET_CODE (temp
) == REG
3345 && REGNO (temp
) < FIRST_PSEUDO_REGISTER
3346 && HARD_REGNO_NREGS (REGNO (temp
), GET_MODE (temp
)))
3347 split_hard_reg_notes (note
, first
, last
, orig_insn
);
3351 /* This note applies to the dest of the original insn. Find the
3352 first new insn that now has the same dest, and move the note
3358 for (insn
= first
; ; insn
= NEXT_INSN (insn
))
3360 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
3361 && (temp
= single_set (insn
))
3362 && rtx_equal_p (SET_DEST (temp
), orig_dest
))
3364 XEXP (note
, 1) = REG_NOTES (insn
);
3365 REG_NOTES (insn
) = note
;
3366 /* The reg is only zero before one insn, the first that
3370 /* It must be set somewhere, fail if we couldn't find where it
3379 /* A REG_EQUIV or REG_EQUAL note on an insn with more than one
3380 set is meaningless. Just drop the note. */
3384 case REG_NO_CONFLICT
:
3385 /* These notes apply to the dest of the original insn. Find the last
3386 new insn that now has the same dest, and move the note there. */
3391 for (insn
= last
; ; insn
= PREV_INSN (insn
))
3393 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
3394 && (temp
= single_set (insn
))
3395 && rtx_equal_p (SET_DEST (temp
), orig_dest
))
3397 XEXP (note
, 1) = REG_NOTES (insn
);
3398 REG_NOTES (insn
) = note
;
3399 /* Only put this note on one of the new insns. */
3403 /* The original dest must still be set someplace. Abort if we
3404 couldn't find it. */
3411 /* Move a REG_LIBCALL note to the first insn created, and update
3412 the corresponding REG_RETVAL note. */
3413 XEXP (note
, 1) = REG_NOTES (first
);
3414 REG_NOTES (first
) = note
;
3416 insn
= XEXP (note
, 0);
3417 note
= find_reg_note (insn
, REG_RETVAL
, 0);
3419 XEXP (note
, 0) = first
;
3423 /* Move a REG_RETVAL note to the last insn created, and update
3424 the corresponding REG_LIBCALL note. */
3425 XEXP (note
, 1) = REG_NOTES (last
);
3426 REG_NOTES (last
) = note
;
3428 insn
= XEXP (note
, 0);
3429 note
= find_reg_note (insn
, REG_LIBCALL
, 0);
3431 XEXP (note
, 0) = last
;
3435 /* This should be moved to whichever instruction is a JUMP_INSN. */
3437 for (insn
= last
; ; insn
= PREV_INSN (insn
))
3439 if (GET_CODE (insn
) == JUMP_INSN
)
3441 XEXP (note
, 1) = REG_NOTES (insn
);
3442 REG_NOTES (insn
) = note
;
3443 /* Only put this note on one of the new insns. */
3446 /* Fail if we couldn't find a JUMP_INSN. */
3453 /* This should be moved to whichever instruction now has the
3454 increment operation. */
3458 /* Should be moved to the new insn(s) which use the label. */
3459 for (insn
= first
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
3460 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
3461 && reg_mentioned_p (XEXP (note
, 0), PATTERN (insn
)))
3462 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_LABEL
,
3463 XEXP (note
, 0), REG_NOTES (insn
));
3468 /* These two notes will never appear until after reorg, so we don't
3469 have to handle them here. */
3475 /* Each new insn created, except the last, has a new set. If the destination
3476 is a register, then this reg is now live across several insns, whereas
3477 previously the dest reg was born and died within the same insn. To
3478 reflect this, we now need a REG_DEAD note on the insn where this
3481 Similarly, the new insns may have clobbers that need REG_UNUSED notes. */
3483 for (insn
= first
; insn
!= last
; insn
= NEXT_INSN (insn
))
3488 pat
= PATTERN (insn
);
3489 if (GET_CODE (pat
) == SET
|| GET_CODE (pat
) == CLOBBER
)
3490 new_insn_dead_notes (pat
, insn
, last
, orig_insn
);
3491 else if (GET_CODE (pat
) == PARALLEL
)
3493 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
3494 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
3495 || GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
)
3496 new_insn_dead_notes (XVECEXP (pat
, 0, i
), insn
, last
, orig_insn
);
3500 /* If any insn, except the last, uses the register set by the last insn,
3501 then we need a new REG_DEAD note on that insn. In this case, there
3502 would not have been a REG_DEAD note for this register in the original
3503 insn because it was used and set within one insn.
3505 There is no new REG_DEAD note needed if the last insn uses the register
3506 that it is setting. */
3508 set
= single_set (last
);
3511 rtx dest
= SET_DEST (set
);
3513 while (GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == SUBREG
3514 || GET_CODE (dest
) == STRICT_LOW_PART
3515 || GET_CODE (dest
) == SIGN_EXTRACT
)
3516 dest
= XEXP (dest
, 0);
3518 if (GET_CODE (dest
) == REG
3519 && ! reg_overlap_mentioned_p (dest
, SET_SRC (set
)))
3521 for (insn
= PREV_INSN (last
); ; insn
= PREV_INSN (insn
))
3523 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
3524 && reg_mentioned_p (dest
, PATTERN (insn
))
3525 && (set
= single_set (insn
)))
3527 rtx insn_dest
= SET_DEST (set
);
3529 while (GET_CODE (insn_dest
) == ZERO_EXTRACT
3530 || GET_CODE (insn_dest
) == SUBREG
3531 || GET_CODE (insn_dest
) == STRICT_LOW_PART
3532 || GET_CODE (insn_dest
) == SIGN_EXTRACT
)
3533 insn_dest
= XEXP (insn_dest
, 0);
3535 if (insn_dest
!= dest
)
3537 note
= rtx_alloc (EXPR_LIST
);
3538 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
3539 XEXP (note
, 0) = dest
;
3540 XEXP (note
, 1) = REG_NOTES (insn
);
3541 REG_NOTES (insn
) = note
;
3542 /* The reg only dies in one insn, the last one
3553 /* If the original dest is modifying a multiple register target, and the
3554 original instruction was split such that the original dest is now set
3555 by two or more SUBREG sets, then the split insns no longer kill the
3556 destination of the original insn.
3558 In this case, if there exists an instruction in the same basic block,
3559 before the split insn, which uses the original dest, and this use is
3560 killed by the original insn, then we must remove the REG_DEAD note on
3561 this insn, because it is now superfluous.
3563 This does not apply when a hard register gets split, because the code
3564 knows how to handle overlapping hard registers properly. */
3565 if (orig_dest
&& GET_CODE (orig_dest
) == REG
)
3567 int found_orig_dest
= 0;
3568 int found_split_dest
= 0;
3570 for (insn
= first
; ; insn
= NEXT_INSN (insn
))
3572 set
= single_set (insn
);
3575 if (GET_CODE (SET_DEST (set
)) == REG
3576 && REGNO (SET_DEST (set
)) == REGNO (orig_dest
))
3578 found_orig_dest
= 1;
3581 else if (GET_CODE (SET_DEST (set
)) == SUBREG
3582 && SUBREG_REG (SET_DEST (set
)) == orig_dest
)
3584 found_split_dest
= 1;
3593 if (found_split_dest
)
3595 /* Search backwards from FIRST, looking for the first insn that uses
3596 the original dest. Stop if we pass a CODE_LABEL or a JUMP_INSN.
3597 If we find an insn, and it has a REG_DEAD note, then delete the
3600 for (insn
= first
; insn
; insn
= PREV_INSN (insn
))
3602 if (GET_CODE (insn
) == CODE_LABEL
3603 || GET_CODE (insn
) == JUMP_INSN
)
3605 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
3606 && reg_mentioned_p (orig_dest
, insn
))
3608 note
= find_regno_note (insn
, REG_DEAD
, REGNO (orig_dest
));
3610 remove_note (insn
, note
);
3614 else if (! found_orig_dest
)
3616 /* This should never happen. */
3621 /* Update reg_n_sets. This is necessary to prevent local alloc from
3622 converting REG_EQUAL notes to REG_EQUIV when splitting has modified
3623 a reg from set once to set multiple times. */
3626 rtx x
= PATTERN (orig_insn
);
3627 RTX_CODE code
= GET_CODE (x
);
3629 if (code
== SET
|| code
== CLOBBER
)
3630 update_n_sets (x
, -1);
3631 else if (code
== PARALLEL
)
3634 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
3636 code
= GET_CODE (XVECEXP (x
, 0, i
));
3637 if (code
== SET
|| code
== CLOBBER
)
3638 update_n_sets (XVECEXP (x
, 0, i
), -1);
3642 for (insn
= first
; ; insn
= NEXT_INSN (insn
))
3645 code
= GET_CODE (x
);
3647 if (code
== SET
|| code
== CLOBBER
)
3648 update_n_sets (x
, 1);
3649 else if (code
== PARALLEL
)
3652 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; i
--)
3654 code
= GET_CODE (XVECEXP (x
, 0, i
));
3655 if (code
== SET
|| code
== CLOBBER
)
3656 update_n_sets (XVECEXP (x
, 0, i
), 1);
3666 /* The one entry point in this file. DUMP_FILE is the dump file for
3670 schedule_insns (dump_file
)
3673 int max_uid
= MAX_INSNS_PER_SPLIT
* (get_max_uid () + 1);
3677 /* Taking care of this degenerate case makes the rest of
3678 this code simpler. */
3679 if (n_basic_blocks
== 0)
3682 /* Create an insn here so that we can hang dependencies off of it later. */
3683 sched_before_next_call
= gen_rtx (INSN
, VOIDmode
, 0, 0, 0, 0, 0, 0, 0);
3685 /* Initialize the unused_*_lists. We can't use the ones left over from
3686 the previous function, because gcc has freed that memory. We can use
3687 the ones left over from the first sched pass in the second pass however,
3688 so only clear them on the first sched pass. The first pass is before
3689 reload if flag_schedule_insns is set, otherwise it is afterwards. */
3691 if (reload_completed
== 0 || ! flag_schedule_insns
)
3693 unused_insn_list
= 0;
3694 unused_expr_list
= 0;
3697 /* We create no insns here, only reorder them, so we
3698 remember how far we can cut back the stack on exit. */
3700 /* Allocate data for this pass. See comments, above,
3701 for what these vectors do. */
3702 /* ??? Instruction splitting below may create new instructions, so these
3703 arrays must be bigger than just max_uid. */
3704 insn_luid
= (int *) alloca (max_uid
* sizeof (int));
3705 insn_priority
= (int *) alloca (max_uid
* sizeof (int));
3706 insn_ref_count
= (int *) alloca (max_uid
* sizeof (int));
3708 if (reload_completed
== 0)
3710 sched_reg_n_deaths
= (short *) alloca (max_regno
* sizeof (short));
3711 sched_reg_n_calls_crossed
= (int *) alloca (max_regno
* sizeof (int));
3712 sched_reg_live_length
= (int *) alloca (max_regno
* sizeof (int));
3713 bb_dead_regs
= (regset
) alloca (regset_bytes
);
3714 bb_live_regs
= (regset
) alloca (regset_bytes
);
3715 bzero (sched_reg_n_calls_crossed
, max_regno
* sizeof (int));
3716 bzero (sched_reg_live_length
, max_regno
* sizeof (int));
3717 bcopy (reg_n_deaths
, sched_reg_n_deaths
, max_regno
* sizeof (short));
3718 init_alias_analysis ();
3722 sched_reg_n_deaths
= 0;
3723 sched_reg_n_calls_crossed
= 0;
3724 sched_reg_live_length
= 0;
3727 if (! flag_schedule_insns
)
3728 init_alias_analysis ();
3731 if (write_symbols
!= NO_DEBUG
)
3735 line_note
= (rtx
*) alloca (max_uid
* sizeof (rtx
));
3736 bzero (line_note
, max_uid
* sizeof (rtx
));
3737 line_note_head
= (rtx
*) alloca (n_basic_blocks
* sizeof (rtx
));
3738 bzero (line_note_head
, n_basic_blocks
* sizeof (rtx
));
3740 /* Determine the line-number at the start of each basic block.
3741 This must be computed and saved now, because after a basic block's
3742 predecessor has been scheduled, it is impossible to accurately
3743 determine the correct line number for the first insn of the block. */
3745 for (b
= 0; b
< n_basic_blocks
; b
++)
3746 for (line
= basic_block_head
[b
]; line
; line
= PREV_INSN (line
))
3747 if (GET_CODE (line
) == NOTE
&& NOTE_LINE_NUMBER (line
) > 0)
3749 line_note_head
[b
] = line
;
3754 bzero (insn_luid
, max_uid
* sizeof (int));
3755 bzero (insn_priority
, max_uid
* sizeof (int));
3756 bzero (insn_ref_count
, max_uid
* sizeof (int));
3758 /* Schedule each basic block, block by block. */
3760 if (NEXT_INSN (basic_block_end
[n_basic_blocks
-1]) == 0
3761 || (GET_CODE (basic_block_end
[n_basic_blocks
-1]) != NOTE
3762 && GET_CODE (basic_block_end
[n_basic_blocks
-1]) != CODE_LABEL
))
3763 emit_note_after (NOTE_INSN_DELETED
, basic_block_end
[n_basic_blocks
-1]);
3765 for (b
= 0; b
< n_basic_blocks
; b
++)
3772 for (insn
= basic_block_head
[b
]; ; insn
= next
)
3777 /* Can't use `next_real_insn' because that
3778 might go across CODE_LABELS and short-out basic blocks. */
3779 next
= NEXT_INSN (insn
);
3780 if (GET_CODE (insn
) != INSN
)
3782 if (insn
== basic_block_end
[b
])
3788 /* Don't split no-op move insns. These should silently disappear
3789 later in final. Splitting such insns would break the code
3790 that handles REG_NO_CONFLICT blocks. */
3791 set
= single_set (insn
);
3792 if (set
&& rtx_equal_p (SET_SRC (set
), SET_DEST (set
)))
3794 if (insn
== basic_block_end
[b
])
3797 /* Nops get in the way while scheduling, so delete them now if
3798 register allocation has already been done. It is too risky
3799 to try to do this before register allocation, and there are
3800 unlikely to be very many nops then anyways. */
3801 if (reload_completed
)
3803 PUT_CODE (insn
, NOTE
);
3804 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
3805 NOTE_SOURCE_FILE (insn
) = 0;
3811 /* Split insns here to get max fine-grain parallelism. */
3812 prev
= PREV_INSN (insn
);
3813 if (reload_completed
== 0)
3815 rtx last
, first
= PREV_INSN (insn
);
3816 rtx notes
= REG_NOTES (insn
);
3818 last
= try_split (PATTERN (insn
), insn
, 1);
3821 /* try_split returns the NOTE that INSN became. */
3822 first
= NEXT_INSN (first
);
3823 update_flow_info (notes
, first
, last
, insn
);
3825 PUT_CODE (insn
, NOTE
);
3826 NOTE_SOURCE_FILE (insn
) = 0;
3827 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
3828 if (insn
== basic_block_head
[b
])
3829 basic_block_head
[b
] = first
;
3830 if (insn
== basic_block_end
[b
])
3832 basic_block_end
[b
] = last
;
3838 if (insn
== basic_block_end
[b
])
3842 schedule_block (b
, dump_file
);
3849 if (write_symbols
!= NO_DEBUG
)
3852 rtx insn
= get_insns ();
3853 int active_insn
= 0;
3856 /* Walk the insns deleting redundant line-number notes. Many of these
3857 are already present. The remainder tend to occur at basic
3858 block boundaries. */
3859 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
3860 if (GET_CODE (insn
) == NOTE
&& NOTE_LINE_NUMBER (insn
) > 0)
3862 /* If there are no active insns following, INSN is redundant. */
3863 if (active_insn
== 0)
3866 NOTE_SOURCE_FILE (insn
) = 0;
3867 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
3869 /* If the line number is unchanged, LINE is redundant. */
3871 && NOTE_LINE_NUMBER (line
) == NOTE_LINE_NUMBER (insn
)
3872 && NOTE_SOURCE_FILE (line
) == NOTE_SOURCE_FILE (insn
))
3875 NOTE_SOURCE_FILE (line
) = 0;
3876 NOTE_LINE_NUMBER (line
) = NOTE_INSN_DELETED
;
3883 else if (! ((GET_CODE (insn
) == NOTE
3884 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_DELETED
)
3885 || (GET_CODE (insn
) == INSN
3886 && (GET_CODE (PATTERN (insn
)) == USE
3887 || GET_CODE (PATTERN (insn
)) == CLOBBER
))))
3890 if (dump_file
&& notes
)
3891 fprintf (dump_file
, ";; deleted %d line-number notes\n", notes
);
3894 if (reload_completed
== 0)
3897 for (regno
= 0; regno
< max_regno
; regno
++)
3898 if (sched_reg_live_length
[regno
])
3902 if (reg_live_length
[regno
] > sched_reg_live_length
[regno
])
3904 ";; register %d life shortened from %d to %d\n",
3905 regno
, reg_live_length
[regno
],
3906 sched_reg_live_length
[regno
]);
3907 /* Negative values are special; don't overwrite the current
3908 reg_live_length value if it is negative. */
3909 else if (reg_live_length
[regno
] < sched_reg_live_length
[regno
]
3910 && reg_live_length
[regno
] >= 0)
3912 ";; register %d life extended from %d to %d\n",
3913 regno
, reg_live_length
[regno
],
3914 sched_reg_live_length
[regno
]);
3916 if (reg_n_calls_crossed
[regno
]
3917 && ! sched_reg_n_calls_crossed
[regno
])
3919 ";; register %d no longer crosses calls\n", regno
);
3920 else if (! reg_n_calls_crossed
[regno
]
3921 && sched_reg_n_calls_crossed
[regno
])
3923 ";; register %d now crosses calls\n", regno
);
3925 /* Negative values are special; don't overwrite the current
3926 reg_live_length value if it is negative. */
3927 if (reg_live_length
[regno
] >= 0)
3928 reg_live_length
[regno
] = sched_reg_live_length
[regno
];
3929 reg_n_calls_crossed
[regno
] = sched_reg_n_calls_crossed
[regno
];
3933 #endif /* INSN_SCHEDULING */