1 /* Perform instruction reorganizations for delay slot filling.
2 Copyright (C) 1992, 1993 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@nyu.edu).
4 Hacked by Michael Tiemann (tiemann@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22 /* Instruction reorganization pass.
24 This pass runs after register allocation and final jump
25 optimization. It should be the last pass to run before peephole.
26 It serves primarily to fill delay slots of insns, typically branch
27 and call insns. Other insns typically involve more complicated
28 interactions of data dependencies and resource constraints, and
29 are better handled by scheduling before register allocation (by the
30 function `schedule_insns').
32 The Branch Penalty is the number of extra cycles that are needed to
33 execute a branch insn. On an ideal machine, branches take a single
34 cycle, and the Branch Penalty is 0. Several RISC machines approach
35 branch delays differently:
37 The MIPS and AMD 29000 have a single branch delay slot. Most insns
38 (except other branches) can be used to fill this slot. When the
39 slot is filled, two insns execute in two cycles, reducing the
40 branch penalty to zero.
42 The Motorola 88000 conditionally exposes its branch delay slot,
43 so code is shorter when it is turned off, but will run faster
44 when useful insns are scheduled there.
46 The IBM ROMP has two forms of branch and call insns, both with and
47 without a delay slot. Much like the 88k, insns not using the delay
48 slot can be shorted (2 bytes vs. 4 bytes), but will run slowed.
50 The SPARC always has a branch delay slot, but its effects can be
51 annulled when the branch is not taken. This means that failing to
52 find other sources of insns, we can hoist an insn from the branch
53 target that would only be safe to execute knowing that the branch
56 The HP-PA always has a branch delay slot. For unconditional branches
57 its effects can be annulled when the branch is taken. The effects
58 of the delay slot in a conditional branch can be nullified for forward
59 taken branches, or for untaken backward branches. This means
60 we can hoist insns from the fall-through path for forward branches or
61 steal insns from the target of backward branches.
63 Three techniques for filling delay slots have been implemented so far:
65 (1) `fill_simple_delay_slots' is the simplest, most efficient way
66 to fill delay slots. This pass first looks for insns which come
67 from before the branch and which are safe to execute after the
68 branch. Then it searches after the insn requiring delay slots or,
69 in the case of a branch, for insns that are after the point at
70 which the branch merges into the fallthrough code, if such a point
71 exists. When such insns are found, the branch penalty decreases
72 and no code expansion takes place.
74 (2) `fill_eager_delay_slots' is more complicated: it is used for
75 scheduling conditional jumps, or for scheduling jumps which cannot
76 be filled using (1). A machine need not have annulled jumps to use
77 this strategy, but it helps (by keeping more options open).
78 `fill_eager_delay_slots' tries to guess the direction the branch
79 will go; if it guesses right 100% of the time, it can reduce the
80 branch penalty as much as `fill_simple_delay_slots' does. If it
81 guesses wrong 100% of the time, it might as well schedule nops (or
82 on the m88k, unexpose the branch slot). When
83 `fill_eager_delay_slots' takes insns from the fall-through path of
84 the jump, usually there is no code expansion; when it takes insns
85 from the branch target, there is code expansion if it is not the
86 only way to reach that target.
88 (3) `relax_delay_slots' uses a set of rules to simplify code that
89 has been reorganized by (1) and (2). It finds cases where
90 conditional test can be eliminated, jumps can be threaded, extra
91 insns can be eliminated, etc. It is the job of (1) and (2) to do a
92 good job of scheduling locally; `relax_delay_slots' takes care of
93 making the various individual schedules work well together. It is
94 especially tuned to handle the control flow interactions of branch
95 insns. It does nothing for insns with delay slots that do not
98 On machines that use CC0, we are very conservative. We will not make
99 a copy of an insn involving CC0 since we want to maintain a 1-1
100 correspondence between the insn that sets and uses CC0. The insns are
101 allowed to be separated by placing an insn that sets CC0 (but not an insn
102 that uses CC0; we could do this, but it doesn't seem worthwhile) in a
103 delay slot. In that case, we point each insn at the other with REG_CC_USER
104 and REG_CC_SETTER notes. Note that these restrictions affect very few
105 machines because most RISC machines with delay slots will not use CC0
106 (the RT is the only known exception at this point).
110 The Acorn Risc Machine can conditionally execute most insns, so
111 it is profitable to move single insns into a position to execute
112 based on the condition code of the previous insn.
114 The HP-PA can conditionally nullify insns, providing a similar
115 effect to the ARM, differing mostly in which insn is "in charge". */
120 #include "insn-config.h"
121 #include "conditions.h"
122 #include "hard-reg-set.h"
123 #include "basic-block.h"
125 #include "insn-flags.h"
130 #include "insn-attr.h"
134 #define obstack_chunk_alloc xmalloc
135 #define obstack_chunk_free free
137 #ifndef ANNUL_IFTRUE_SLOTS
138 #define eligible_for_annul_true(INSN, SLOTS, TRIAL, FLAGS) 0
140 #ifndef ANNUL_IFFALSE_SLOTS
141 #define eligible_for_annul_false(INSN, SLOTS, TRIAL, FLAGS) 0
144 /* Insns which have delay slots that have not yet been filled. */
146 static struct obstack unfilled_slots_obstack
;
147 static rtx
*unfilled_firstobj
;
149 /* Define macros to refer to the first and last slot containing unfilled
150 insns. These are used because the list may move and its address
151 should be recomputed at each use. */
153 #define unfilled_slots_base \
154 ((rtx *) obstack_base (&unfilled_slots_obstack))
156 #define unfilled_slots_next \
157 ((rtx *) obstack_next_free (&unfilled_slots_obstack))
159 /* This structure is used to indicate which hardware resources are set or
160 needed by insns so far. */
164 char memory
; /* Insn sets or needs a memory location. */
165 char volatil
; /* Insn sets or needs a volatile memory loc. */
166 char cc
; /* Insn sets or needs the condition codes. */
167 HARD_REG_SET regs
; /* Which registers are set or needed. */
170 /* Macro to clear all resources. */
171 #define CLEAR_RESOURCE(RES) \
172 do { (RES)->memory = (RES)->volatil = (RES)->cc = 0; \
173 CLEAR_HARD_REG_SET ((RES)->regs); } while (0)
175 /* Indicates what resources are required at the beginning of the epilogue. */
176 static struct resources start_of_epilogue_needs
;
178 /* Indicates what resources are required at function end. */
179 static struct resources end_of_function_needs
;
181 /* Points to the label before the end of the function. */
182 static rtx end_of_function_label
;
184 /* This structure is used to record liveness information at the targets or
185 fallthrough insns of branches. We will most likely need the information
186 at targets again, so save them in a hash table rather than recomputing them
191 int uid
; /* INSN_UID of target. */
192 struct target_info
*next
; /* Next info for same hash bucket. */
193 HARD_REG_SET live_regs
; /* Registers live at target. */
194 int block
; /* Basic block number containing target. */
195 int bb_tick
; /* Generation count of basic block info. */
198 #define TARGET_HASH_PRIME 257
200 /* Define the hash table itself. */
201 static struct target_info
**target_hash_table
;
203 /* For each basic block, we maintain a generation number of its basic
204 block info, which is updated each time we move an insn from the
205 target of a jump. This is the generation number indexed by block
208 static int *bb_ticks
;
210 /* Mapping between INSN_UID's and position in the code since INSN_UID's do
211 not always monotonically increase. */
212 static int *uid_to_ruid
;
214 /* Highest valid index in `uid_to_ruid'. */
217 static void mark_referenced_resources
PROTO((rtx
, struct resources
*, int));
218 static void mark_set_resources
PROTO((rtx
, struct resources
*, int, int));
219 static int stop_search_p
PROTO((rtx
, int));
220 static int resource_conflicts_p
PROTO((struct resources
*,
221 struct resources
*));
222 static int insn_references_resource_p
PROTO((rtx
, struct resources
*, int));
223 static int insn_sets_resources_p
PROTO((rtx
, struct resources
*, int));
224 static rtx find_end_label
PROTO((void));
225 static rtx emit_delay_sequence
PROTO((rtx
, rtx
, int, int));
226 static rtx add_to_delay_list
PROTO((rtx
, rtx
));
227 static void delete_from_delay_slot
PROTO((rtx
));
228 static void delete_scheduled_jump
PROTO((rtx
));
229 static void note_delay_statistics
PROTO((int, int));
230 static rtx optimize_skip
PROTO((rtx
));
231 static int get_jump_flags
PROTO((rtx
, rtx
));
232 static int rare_destination
PROTO((rtx
));
233 static int mostly_true_jump
PROTO((rtx
, rtx
));
234 static rtx get_branch_condition
PROTO((rtx
, rtx
));
235 static int condition_dominates_p
PROTO((rtx
, rtx
));
236 static rtx steal_delay_list_from_target
PROTO((rtx
, rtx
, rtx
, rtx
,
240 int, int *, int *, rtx
*));
241 static rtx steal_delay_list_from_fallthrough
PROTO((rtx
, rtx
, rtx
, rtx
,
246 static void try_merge_delay_insns
PROTO((rtx
, rtx
));
247 static int redundant_insn_p
PROTO((rtx
, rtx
, rtx
));
248 static int own_thread_p
PROTO((rtx
, rtx
, int));
249 static int find_basic_block
PROTO((rtx
));
250 static void update_block
PROTO((rtx
, rtx
));
251 static int reorg_redirect_jump
PROTO((rtx
, rtx
));
252 static void update_reg_dead_notes
PROTO((rtx
, rtx
));
253 static void update_live_status
PROTO((rtx
, rtx
));
254 static rtx next_insn_no_annul
PROTO((rtx
));
255 static void mark_target_live_regs
PROTO((rtx
, struct resources
*));
256 static void fill_simple_delay_slots
PROTO((rtx
, int));
257 static rtx fill_slots_from_thread
PROTO((rtx
, rtx
, rtx
, rtx
, int, int,
258 int, int, int, int *));
259 static void fill_eager_delay_slots
PROTO((rtx
));
260 static void relax_delay_slots
PROTO((rtx
));
261 static void make_return_insns
PROTO((rtx
));
263 /* Given X, some rtl, and RES, a pointer to a `struct resource', mark
264 which resources are references by the insn. If INCLUDE_CALLED_ROUTINE
265 is TRUE, resources used by the called routine will be included for
269 mark_referenced_resources (x
, res
, include_delayed_effects
)
271 register struct resources
*res
;
272 register int include_delayed_effects
;
274 register enum rtx_code code
= GET_CODE (x
);
276 register char *format_ptr
;
278 /* Handle leaf items for which we set resource flags. Also, special-case
279 CALL, SET and CLOBBER operators. */
291 if (GET_CODE (SUBREG_REG (x
)) != REG
)
292 mark_referenced_resources (SUBREG_REG (x
), res
, 0);
295 int regno
= REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
);
296 int last_regno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
297 for (i
= regno
; i
< last_regno
; i
++)
298 SET_HARD_REG_BIT (res
->regs
, i
);
303 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (x
), GET_MODE (x
)); i
++)
304 SET_HARD_REG_BIT (res
->regs
, REGNO (x
) + i
);
308 /* If this memory shouldn't change, it really isn't referencing
310 if (! RTX_UNCHANGING_P (x
))
312 res
->volatil
= MEM_VOLATILE_P (x
);
314 /* Mark registers used to access memory. */
315 mark_referenced_resources (XEXP (x
, 0), res
, 0);
322 case UNSPEC_VOLATILE
:
324 /* Traditional asm's are always volatile. */
329 res
->volatil
= MEM_VOLATILE_P (x
);
331 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
332 We can not just fall through here since then we would be confused
333 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
334 traditional asms unlike their normal usage. */
336 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
337 mark_referenced_resources (ASM_OPERANDS_INPUT (x
, i
), res
, 0);
341 /* The first operand will be a (MEM (xxx)) but doesn't really reference
342 memory. The second operand may be referenced, though. */
343 mark_referenced_resources (XEXP (XEXP (x
, 0), 0), res
, 0);
344 mark_referenced_resources (XEXP (x
, 1), res
, 0);
348 /* Usually, the first operand of SET is set, not referenced. But
349 registers used to access memory are referenced. SET_DEST is
350 also referenced if it is a ZERO_EXTRACT or SIGN_EXTRACT. */
352 mark_referenced_resources (SET_SRC (x
), res
, 0);
355 if (GET_CODE (x
) == SIGN_EXTRACT
|| GET_CODE (x
) == ZERO_EXTRACT
)
356 mark_referenced_resources (x
, res
, 0);
357 else if (GET_CODE (x
) == SUBREG
)
359 if (GET_CODE (x
) == MEM
)
360 mark_referenced_resources (XEXP (x
, 0), res
, 0);
367 if (include_delayed_effects
)
369 /* A CALL references memory, the frame pointer if it exists, the
370 stack pointer, any global registers and any registers given in
371 USE insns immediately in front of the CALL.
373 However, we may have moved some of the parameter loading insns
374 into the delay slot of this CALL. If so, the USE's for them
375 don't count and should be skipped. */
376 rtx insn
= PREV_INSN (x
);
381 /* If we are part of a delay slot sequence, point at the SEQUENCE. */
382 if (NEXT_INSN (insn
) != x
)
384 sequence
= PATTERN (NEXT_INSN (insn
));
385 seq_size
= XVECLEN (sequence
, 0);
386 if (GET_CODE (sequence
) != SEQUENCE
)
391 SET_HARD_REG_BIT (res
->regs
, STACK_POINTER_REGNUM
);
392 if (frame_pointer_needed
)
393 SET_HARD_REG_BIT (res
->regs
, FRAME_POINTER_REGNUM
);
395 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
397 SET_HARD_REG_BIT (res
->regs
, i
);
399 /* Skip any labels between the CALL_INSN and possible USE insns. */
400 while (GET_CODE (insn
) == CODE_LABEL
)
401 insn
= PREV_INSN (insn
);
403 for ( ; (insn
&& GET_CODE (insn
) == INSN
404 && GET_CODE (PATTERN (insn
)) == USE
);
405 insn
= PREV_INSN (insn
))
407 for (i
= 1; i
< seq_size
; i
++)
409 rtx slot_pat
= PATTERN (XVECEXP (sequence
, 0, i
));
410 if (GET_CODE (slot_pat
) == SET
411 && rtx_equal_p (SET_DEST (slot_pat
),
412 XEXP (PATTERN (insn
), 0)))
416 mark_referenced_resources (XEXP (PATTERN (insn
), 0), res
, 0);
420 /* ... fall through to other INSN processing ... */
425 #ifdef INSN_REFERENCES_ARE_DELAYED
426 if (! include_delayed_effects
427 && INSN_REFERENCES_ARE_DELAYED (x
))
431 /* No special processing, just speed up. */
432 mark_referenced_resources (PATTERN (x
), res
, include_delayed_effects
);
436 /* Process each sub-expression and flag what it needs. */
437 format_ptr
= GET_RTX_FORMAT (code
);
438 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
439 switch (*format_ptr
++)
442 mark_referenced_resources (XEXP (x
, i
), res
, include_delayed_effects
);
446 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
447 mark_referenced_resources (XVECEXP (x
, i
, j
), res
,
448 include_delayed_effects
);
453 /* Given X, a part of an insn, and a pointer to a `struct resource', RES,
454 indicate which resources are modified by the insn. If INCLUDE_CALLED_ROUTINE
455 is nonzero, also mark resources potentially set by the called routine.
457 If IN_DEST is nonzero, it means we are inside a SET. Otherwise,
458 objects are being referenced instead of set.
460 We never mark the insn as modifying the condition code unless it explicitly
461 SETs CC0 even though this is not totally correct. The reason for this is
462 that we require a SET of CC0 to immediately precede the reference to CC0.
463 So if some other insn sets CC0 as a side-effect, we know it cannot affect
464 our computation and thus may be placed in a delay slot. */
467 mark_set_resources (x
, res
, in_dest
, include_delayed_effects
)
469 register struct resources
*res
;
471 int include_delayed_effects
;
473 register enum rtx_code code
;
475 register char *format_ptr
;
493 /* These don't set any resources. */
502 /* Called routine modifies the condition code, memory, any registers
503 that aren't saved across calls, global registers and anything
504 explicitly CLOBBERed immediately after the CALL_INSN. */
506 if (include_delayed_effects
)
508 rtx next
= NEXT_INSN (x
);
510 res
->cc
= res
->memory
= 1;
511 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
512 if (call_used_regs
[i
] || global_regs
[i
])
513 SET_HARD_REG_BIT (res
->regs
, i
);
515 /* Skip any possible labels between the CALL_INSN and CLOBBERs. */
516 while (GET_CODE (next
) == CODE_LABEL
)
517 next
= NEXT_INSN (next
);
519 for (; (next
&& GET_CODE (next
) == INSN
520 && GET_CODE (PATTERN (next
)) == CLOBBER
);
521 next
= NEXT_INSN (next
))
522 mark_set_resources (XEXP (PATTERN (next
), 0), res
, 1, 0);
525 /* ... and also what it's RTL says it modifies, if anything. */
530 /* An insn consisting of just a CLOBBER (or USE) is just for flow
531 and doesn't actually do anything, so we ignore it. */
533 #ifdef INSN_SETS_ARE_DELAYED
534 if (! include_delayed_effects
535 && INSN_SETS_ARE_DELAYED (x
))
540 if (GET_CODE (x
) != USE
&& GET_CODE (x
) != CLOBBER
)
545 /* If the source of a SET is a CALL, this is actually done by
546 the called routine. So only include it if we are to include the
547 effects of the calling routine. */
549 mark_set_resources (SET_DEST (x
), res
,
550 (include_delayed_effects
551 || GET_CODE (SET_SRC (x
)) != CALL
),
554 mark_set_resources (SET_SRC (x
), res
, 0, 0);
558 mark_set_resources (XEXP (x
, 0), res
, 1, 0);
562 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
563 if (! (INSN_ANNULLED_BRANCH_P (XVECEXP (x
, 0, 0))
564 && INSN_FROM_TARGET_P (XVECEXP (x
, 0, i
))))
565 mark_set_resources (XVECEXP (x
, 0, i
), res
, 0,
566 include_delayed_effects
);
573 mark_set_resources (XEXP (x
, 0), res
, 1, 0);
577 mark_set_resources (XEXP (x
, 0), res
, in_dest
, 0);
578 mark_set_resources (XEXP (x
, 1), res
, 0, 0);
579 mark_set_resources (XEXP (x
, 2), res
, 0, 0);
586 res
->volatil
= MEM_VOLATILE_P (x
);
589 mark_set_resources (XEXP (x
, 0), res
, 0, 0);
594 for (i
= 0; i
< HARD_REGNO_NREGS (REGNO (x
), GET_MODE (x
)); i
++)
595 SET_HARD_REG_BIT (res
->regs
, REGNO (x
) + i
);
599 /* Process each sub-expression and flag what it needs. */
600 format_ptr
= GET_RTX_FORMAT (code
);
601 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
602 switch (*format_ptr
++)
605 mark_set_resources (XEXP (x
, i
), res
, in_dest
, include_delayed_effects
);
609 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
610 mark_set_resources (XVECEXP (x
, i
, j
), res
, in_dest
,
611 include_delayed_effects
);
616 /* Return TRUE if this insn should stop the search for insn to fill delay
617 slots. LABELS_P indicates that labels should terminate the search.
618 In all cases, jumps terminate the search. */
621 stop_search_p (insn
, labels_p
)
628 switch (GET_CODE (insn
))
642 /* OK unless it contains a delay slot or is an `asm' insn of some type.
643 We don't know anything about these. */
644 return (GET_CODE (PATTERN (insn
)) == SEQUENCE
645 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
646 || asm_noperands (PATTERN (insn
)) >= 0);
653 /* Return TRUE if any resources are marked in both RES1 and RES2 or if either
654 resource set contains a volatile memory reference. Otherwise, return FALSE. */
657 resource_conflicts_p (res1
, res2
)
658 struct resources
*res1
, *res2
;
660 if ((res1
->cc
&& res2
->cc
) || (res1
->memory
&& res2
->memory
)
661 || res1
->volatil
|| res2
->volatil
)
665 return (res1
->regs
& res2
->regs
) != HARD_CONST (0);
670 for (i
= 0; i
< HARD_REG_SET_LONGS
; i
++)
671 if ((res1
->regs
[i
] & res2
->regs
[i
]) != 0)
678 /* Return TRUE if any resource marked in RES, a `struct resources', is
679 referenced by INSN. If INCLUDE_CALLED_ROUTINE is set, return if the called
680 routine is using those resources.
682 We compute this by computing all the resources referenced by INSN and
683 seeing if this conflicts with RES. It might be faster to directly check
684 ourselves, and this is the way it used to work, but it means duplicating
685 a large block of complex code. */
688 insn_references_resource_p (insn
, res
, include_delayed_effects
)
690 register struct resources
*res
;
691 int include_delayed_effects
;
693 struct resources insn_res
;
695 CLEAR_RESOURCE (&insn_res
);
696 mark_referenced_resources (insn
, &insn_res
, include_delayed_effects
);
697 return resource_conflicts_p (&insn_res
, res
);
700 /* Return TRUE if INSN modifies resources that are marked in RES.
701 INCLUDE_CALLED_ROUTINE is set if the actions of that routine should be
702 included. CC0 is only modified if it is explicitly set; see comments
703 in front of mark_set_resources for details. */
706 insn_sets_resource_p (insn
, res
, include_delayed_effects
)
708 register struct resources
*res
;
709 int include_delayed_effects
;
711 struct resources insn_sets
;
713 CLEAR_RESOURCE (&insn_sets
);
714 mark_set_resources (insn
, &insn_sets
, 0, include_delayed_effects
);
715 return resource_conflicts_p (&insn_sets
, res
);
718 /* Find a label at the end of the function or before a RETURN. If there is
726 /* If we found one previously, return it. */
727 if (end_of_function_label
)
728 return end_of_function_label
;
730 /* Otherwise, see if there is a label at the end of the function. If there
731 is, it must be that RETURN insns aren't needed, so that is our return
732 label and we don't have to do anything else. */
734 insn
= get_last_insn ();
735 while (GET_CODE (insn
) == NOTE
736 || (GET_CODE (insn
) == INSN
737 && (GET_CODE (PATTERN (insn
)) == USE
738 || GET_CODE (PATTERN (insn
)) == CLOBBER
)))
739 insn
= PREV_INSN (insn
);
741 /* When a target threads its epilogue we might already have a
742 suitable return insn. If so put a label before it for the
743 end_of_function_label. */
744 if (GET_CODE (insn
) == BARRIER
745 && GET_CODE (PREV_INSN (insn
)) == JUMP_INSN
746 && GET_CODE (PATTERN (PREV_INSN (insn
))) == RETURN
)
748 rtx temp
= PREV_INSN (PREV_INSN (insn
));
749 end_of_function_label
= gen_label_rtx ();
750 LABEL_NUSES (end_of_function_label
) = 0;
752 /* Put the label before an USE insns that may proceed the RETURN insn. */
753 while (GET_CODE (temp
) == USE
)
754 temp
= PREV_INSN (temp
);
756 emit_label_after (end_of_function_label
, temp
);
759 else if (GET_CODE (insn
) == CODE_LABEL
)
760 end_of_function_label
= insn
;
763 /* Otherwise, make a new label and emit a RETURN and BARRIER,
765 end_of_function_label
= gen_label_rtx ();
766 LABEL_NUSES (end_of_function_label
) = 0;
767 emit_label (end_of_function_label
);
771 /* The return we make may have delay slots too. */
772 rtx insn
= gen_return ();
773 insn
= emit_jump_insn (insn
);
775 if (num_delay_slots (insn
) > 0)
776 obstack_ptr_grow (&unfilled_slots_obstack
, insn
);
781 /* Show one additional use for this label so it won't go away until
783 ++LABEL_NUSES (end_of_function_label
);
785 return end_of_function_label
;
788 /* Put INSN and LIST together in a SEQUENCE rtx of LENGTH, and replace
789 the pattern of INSN with the SEQUENCE.
791 Chain the insns so that NEXT_INSN of each insn in the sequence points to
792 the next and NEXT_INSN of the last insn in the sequence points to
793 the first insn after the sequence. Similarly for PREV_INSN. This makes
794 it easier to scan all insns.
796 Returns the SEQUENCE that replaces INSN. */
799 emit_delay_sequence (insn
, list
, length
, avail
)
809 /* Allocate the the rtvec to hold the insns and the SEQUENCE. */
810 rtvec seqv
= rtvec_alloc (length
+ 1);
811 rtx seq
= gen_rtx (SEQUENCE
, VOIDmode
, seqv
);
812 rtx seq_insn
= make_insn_raw (seq
);
813 rtx first
= get_insns ();
814 rtx last
= get_last_insn ();
816 /* Make a copy of the insn having delay slots. */
817 rtx delay_insn
= copy_rtx (insn
);
819 /* If INSN is followed by a BARRIER, delete the BARRIER since it will only
820 confuse further processing. Update LAST in case it was the last insn.
821 We will put the BARRIER back in later. */
822 if (NEXT_INSN (insn
) && GET_CODE (NEXT_INSN (insn
)) == BARRIER
)
824 delete_insn (NEXT_INSN (insn
));
825 last
= get_last_insn ();
829 /* Splice our SEQUENCE into the insn stream where INSN used to be. */
830 NEXT_INSN (seq_insn
) = NEXT_INSN (insn
);
831 PREV_INSN (seq_insn
) = PREV_INSN (insn
);
834 set_new_first_and_last_insn (first
, seq_insn
);
836 PREV_INSN (NEXT_INSN (seq_insn
)) = seq_insn
;
839 set_new_first_and_last_insn (seq_insn
, last
);
841 NEXT_INSN (PREV_INSN (seq_insn
)) = seq_insn
;
843 /* Build our SEQUENCE and rebuild the insn chain. */
844 XVECEXP (seq
, 0, 0) = delay_insn
;
845 INSN_DELETED_P (delay_insn
) = 0;
846 PREV_INSN (delay_insn
) = PREV_INSN (seq_insn
);
848 for (li
= list
; li
; li
= XEXP (li
, 1), i
++)
850 rtx tem
= XEXP (li
, 0);
853 /* Show that this copy of the insn isn't deleted. */
854 INSN_DELETED_P (tem
) = 0;
856 XVECEXP (seq
, 0, i
) = tem
;
857 PREV_INSN (tem
) = XVECEXP (seq
, 0, i
- 1);
858 NEXT_INSN (XVECEXP (seq
, 0, i
- 1)) = tem
;
860 /* Remove any REG_DEAD notes because we can't rely on them now
861 that the insn has been moved. */
862 for (note
= REG_NOTES (tem
); note
; note
= XEXP (note
, 1))
863 if (REG_NOTE_KIND (note
) == REG_DEAD
)
864 XEXP (note
, 0) = const0_rtx
;
867 NEXT_INSN (XVECEXP (seq
, 0, length
)) = NEXT_INSN (seq_insn
);
869 /* If the previous insn is a SEQUENCE, update the NEXT_INSN pointer on the
870 last insn in that SEQUENCE to point to us. Similarly for the first
871 insn in the following insn if it is a SEQUENCE. */
873 if (PREV_INSN (seq_insn
) && GET_CODE (PREV_INSN (seq_insn
)) == INSN
874 && GET_CODE (PATTERN (PREV_INSN (seq_insn
))) == SEQUENCE
)
875 NEXT_INSN (XVECEXP (PATTERN (PREV_INSN (seq_insn
)), 0,
876 XVECLEN (PATTERN (PREV_INSN (seq_insn
)), 0) - 1))
879 if (NEXT_INSN (seq_insn
) && GET_CODE (NEXT_INSN (seq_insn
)) == INSN
880 && GET_CODE (PATTERN (NEXT_INSN (seq_insn
))) == SEQUENCE
)
881 PREV_INSN (XVECEXP (PATTERN (NEXT_INSN (seq_insn
)), 0, 0)) = seq_insn
;
883 /* If there used to be a BARRIER, put it back. */
885 emit_barrier_after (seq_insn
);
893 /* Add INSN to DELAY_LIST and return the head of the new list. The list must
894 be in the order in which the insns are to be executed. */
897 add_to_delay_list (insn
, delay_list
)
901 /* If we have an empty list, just make a new list element. If
902 INSN has it's block number recorded, clear it since we may
903 be moving the insn to a new block. */
907 struct target_info
*tinfo
;
909 for (tinfo
= target_hash_table
[INSN_UID (insn
) % TARGET_HASH_PRIME
];
910 tinfo
; tinfo
= tinfo
->next
)
911 if (tinfo
->uid
== INSN_UID (insn
))
917 return gen_rtx (INSN_LIST
, VOIDmode
, insn
, NULL_RTX
);
920 /* Otherwise this must be an INSN_LIST. Add INSN to the end of the
922 XEXP (delay_list
, 1) = add_to_delay_list (insn
, XEXP (delay_list
, 1));
927 /* Delete INSN from the the delay slot of the insn that it is in. This may
928 produce an insn without anything in its delay slots. */
931 delete_from_delay_slot (insn
)
934 rtx trial
, seq_insn
, seq
, prev
;
938 /* We first must find the insn containing the SEQUENCE with INSN in its
939 delay slot. Do this by finding an insn, TRIAL, where
940 PREV_INSN (NEXT_INSN (TRIAL)) != TRIAL. */
943 PREV_INSN (NEXT_INSN (trial
)) == trial
;
944 trial
= NEXT_INSN (trial
))
947 seq_insn
= PREV_INSN (NEXT_INSN (trial
));
948 seq
= PATTERN (seq_insn
);
950 /* Create a delay list consisting of all the insns other than the one
951 we are deleting (unless we were the only one). */
952 if (XVECLEN (seq
, 0) > 2)
953 for (i
= 1; i
< XVECLEN (seq
, 0); i
++)
954 if (XVECEXP (seq
, 0, i
) != insn
)
955 delay_list
= add_to_delay_list (XVECEXP (seq
, 0, i
), delay_list
);
957 /* Delete the old SEQUENCE, re-emit the insn that used to have the delay
958 list, and rebuild the delay list if non-empty. */
959 prev
= PREV_INSN (seq_insn
);
960 trial
= XVECEXP (seq
, 0, 0);
961 delete_insn (seq_insn
);
962 add_insn_after (trial
, prev
);
964 if (GET_CODE (trial
) == JUMP_INSN
965 && (simplejump_p (trial
) || GET_CODE (PATTERN (trial
)) == RETURN
))
966 emit_barrier_after (trial
);
968 /* If there are any delay insns, remit them. Otherwise clear the
971 trial
= emit_delay_sequence (trial
, delay_list
, XVECLEN (seq
, 0) - 2, 0);
973 INSN_ANNULLED_BRANCH_P (trial
) = 0;
975 INSN_FROM_TARGET_P (insn
) = 0;
977 /* Show we need to fill this insn again. */
978 obstack_ptr_grow (&unfilled_slots_obstack
, trial
);
981 /* Delete INSN, a JUMP_INSN. If it is a conditional jump, we must track down
982 the insn that sets CC0 for it and delete it too. */
985 delete_scheduled_jump (insn
)
988 /* Delete the insn that sets cc0 for us. On machines without cc0, we could
989 delete the insn that sets the condition code, but it is hard to find it.
990 Since this case is rare anyway, don't bother trying; there would likely
991 be other insns that became dead anyway, which we wouldn't know to
995 if (reg_mentioned_p (cc0_rtx
, insn
))
997 rtx note
= find_reg_note (insn
, REG_CC_SETTER
, NULL_RTX
);
999 /* If a reg-note was found, it points to an insn to set CC0. This
1000 insn is in the delay list of some other insn. So delete it from
1001 the delay list it was in. */
1004 if (! FIND_REG_INC_NOTE (XEXP (note
, 0), NULL_RTX
)
1005 && sets_cc0_p (PATTERN (XEXP (note
, 0))) == 1)
1006 delete_from_delay_slot (XEXP (note
, 0));
1010 /* The insn setting CC0 is our previous insn, but it may be in
1011 a delay slot. It will be the last insn in the delay slot, if
1013 rtx trial
= previous_insn (insn
);
1014 if (GET_CODE (trial
) == NOTE
)
1015 trial
= prev_nonnote_insn (trial
);
1016 if (sets_cc0_p (PATTERN (trial
)) != 1
1017 || FIND_REG_INC_NOTE (trial
, 0))
1019 if (PREV_INSN (NEXT_INSN (trial
)) == trial
)
1020 delete_insn (trial
);
1022 delete_from_delay_slot (trial
);
1030 /* Counters for delay-slot filling. */
1032 #define NUM_REORG_FUNCTIONS 2
1033 #define MAX_DELAY_HISTOGRAM 3
1034 #define MAX_REORG_PASSES 2
1036 static int num_insns_needing_delays
[NUM_REORG_FUNCTIONS
][MAX_REORG_PASSES
];
1038 static int num_filled_delays
[NUM_REORG_FUNCTIONS
][MAX_DELAY_HISTOGRAM
+1][MAX_REORG_PASSES
];
1040 static int reorg_pass_number
;
1043 note_delay_statistics (slots_filled
, index
)
1044 int slots_filled
, index
;
1046 num_insns_needing_delays
[index
][reorg_pass_number
]++;
1047 if (slots_filled
> MAX_DELAY_HISTOGRAM
)
1048 slots_filled
= MAX_DELAY_HISTOGRAM
;
1049 num_filled_delays
[index
][slots_filled
][reorg_pass_number
]++;
1052 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
1054 /* Optimize the following cases:
1056 1. When a conditional branch skips over only one instruction,
1057 use an annulling branch and put that insn in the delay slot.
1058 Use either a branch that annuls when the condition if true or
1059 invert the test with a branch that annuls when the condition is
1060 false. This saves insns, since otherwise we must copy an insn
1063 (orig) (skip) (otherwise)
1064 Bcc.n L1 Bcc',a L1 Bcc,a L1'
1071 2. When a conditional branch skips over only one instruction,
1072 and after that, it unconditionally branches somewhere else,
1073 perform the similar optimization. This saves executing the
1074 second branch in the case where the inverted condition is true.
1081 INSN is a JUMP_INSN.
1083 This should be expanded to skip over N insns, where N is the number
1084 of delay slots required. */
1087 optimize_skip (insn
)
1090 register rtx trial
= next_nonnote_insn (insn
);
1091 rtx next_trial
= next_active_insn (trial
);
1096 flags
= get_jump_flags (insn
, JUMP_LABEL (insn
));
1099 || GET_CODE (trial
) != INSN
1100 || GET_CODE (PATTERN (trial
)) == SEQUENCE
1101 || recog_memoized (trial
) < 0
1102 || (! eligible_for_annul_false (insn
, 0, trial
, flags
)
1103 && ! eligible_for_annul_true (insn
, 0, trial
, flags
)))
1106 /* There are two cases where we are just executing one insn (we assume
1107 here that a branch requires only one insn; this should be generalized
1108 at some point): Where the branch goes around a single insn or where
1109 we have one insn followed by a branch to the same label we branch to.
1110 In both of these cases, inverting the jump and annulling the delay
1111 slot give the same effect in fewer insns. */
1112 if ((next_trial
== next_active_insn (JUMP_LABEL (insn
)))
1114 && GET_CODE (next_trial
) == JUMP_INSN
1115 && JUMP_LABEL (insn
) == JUMP_LABEL (next_trial
)
1116 && (simplejump_p (next_trial
)
1117 || GET_CODE (PATTERN (next_trial
)) == RETURN
)))
1119 if (eligible_for_annul_false (insn
, 0, trial
, flags
))
1121 if (invert_jump (insn
, JUMP_LABEL (insn
)))
1122 INSN_FROM_TARGET_P (trial
) = 1;
1123 else if (! eligible_for_annul_true (insn
, 0, trial
, flags
))
1127 delay_list
= add_to_delay_list (trial
, NULL_RTX
);
1128 next_trial
= next_active_insn (trial
);
1129 update_block (trial
, trial
);
1130 delete_insn (trial
);
1132 /* Also, if we are targeting an unconditional
1133 branch, thread our jump to the target of that branch. Don't
1134 change this into a RETURN here, because it may not accept what
1135 we have in the delay slot. We'll fix this up later. */
1136 if (next_trial
&& GET_CODE (next_trial
) == JUMP_INSN
1137 && (simplejump_p (next_trial
)
1138 || GET_CODE (PATTERN (next_trial
)) == RETURN
))
1140 target_label
= JUMP_LABEL (next_trial
);
1141 if (target_label
== 0)
1142 target_label
= find_end_label ();
1143 reorg_redirect_jump (insn
, target_label
);
1146 INSN_ANNULLED_BRANCH_P (insn
) = 1;
1154 /* Encode and return branch direction and prediction information for
1155 INSN assuming it will jump to LABEL.
1157 Non conditional branches return no direction information and
1158 are predicted as very likely taken. */
1160 get_jump_flags (insn
, label
)
1165 /* get_jump_flags can be passed any insn with delay slots, these may
1166 be INSNs, CALL_INSNs, or JUMP_INSNs. Only JUMP_INSNs have branch
1167 direction information, and only if they are conditional jumps.
1169 If LABEL is zero, then there is no way to determine the branch
1171 if (GET_CODE (insn
) == JUMP_INSN
1172 && condjump_p (insn
)
1173 && INSN_UID (insn
) <= max_uid
1175 && INSN_UID (label
) <= max_uid
)
1177 = (uid_to_ruid
[INSN_UID (label
)] > uid_to_ruid
[INSN_UID (insn
)])
1178 ? ATTR_FLAG_forward
: ATTR_FLAG_backward
;
1179 /* No valid direction information. */
1183 /* If insn is a conditional branch call mostly_true_jump to get
1184 determine the branch prediction.
1186 Non conditional branches are predicted as very likely taken. */
1187 if (GET_CODE (insn
) == JUMP_INSN
1188 && condjump_p (insn
))
1192 prediction
= mostly_true_jump (insn
, get_branch_condition (insn
, label
));
1196 flags
|= (ATTR_FLAG_very_likely
| ATTR_FLAG_likely
);
1199 flags
|= ATTR_FLAG_likely
;
1202 flags
|= ATTR_FLAG_unlikely
;
1205 flags
|= (ATTR_FLAG_very_unlikely
| ATTR_FLAG_unlikely
);
1213 flags
|= (ATTR_FLAG_very_likely
| ATTR_FLAG_likely
);
1218 /* Return 1 if DEST is a destination that will be branched to rarely (the
1219 return point of a function); return 2 if DEST will be branched to very
1220 rarely (a call to a function that doesn't return). Otherwise,
1224 rare_destination (insn
)
1229 for (; insn
; insn
= NEXT_INSN (insn
))
1231 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
1232 insn
= XVECEXP (PATTERN (insn
), 0, 0);
1234 switch (GET_CODE (insn
))
1239 /* A BARRIER can either be after a JUMP_INSN or a CALL_INSN. We
1240 don't scan past JUMP_INSNs, so any barrier we find here must
1241 have been after a CALL_INSN and hence mean the call doesn't
1245 if (GET_CODE (PATTERN (insn
)) == RETURN
)
1247 else if (simplejump_p (insn
)
1248 && jump_count
++ < 10)
1249 insn
= JUMP_LABEL (insn
);
1255 /* If we got here it means we hit the end of the function. So this
1256 is an unlikely destination. */
1261 /* Return truth value of the statement that this branch
1262 is mostly taken. If we think that the branch is extremely likely
1263 to be taken, we return 2. If the branch is slightly more likely to be
1264 taken, return 1. If the branch is slightly less likely to be taken,
1265 return 0 and if the branch is highly unlikely to be taken, return -1.
1267 CONDITION, if non-zero, is the condition that JUMP_INSN is testing. */
1270 mostly_true_jump (jump_insn
, condition
)
1271 rtx jump_insn
, condition
;
1273 rtx target_label
= JUMP_LABEL (jump_insn
);
1275 int rare_dest
= rare_destination (target_label
);
1276 int rare_fallthrough
= rare_destination (NEXT_INSN (jump_insn
));
1278 /* If this is a branch outside a loop, it is highly unlikely. */
1279 if (GET_CODE (PATTERN (jump_insn
)) == SET
1280 && GET_CODE (SET_SRC (PATTERN (jump_insn
))) == IF_THEN_ELSE
1281 && ((GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn
)), 1)) == LABEL_REF
1282 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn
)), 1)))
1283 || (GET_CODE (XEXP (SET_SRC (PATTERN (jump_insn
)), 2)) == LABEL_REF
1284 && LABEL_OUTSIDE_LOOP_P (XEXP (SET_SRC (PATTERN (jump_insn
)), 2)))))
1289 /* If this is the test of a loop, it is very likely true. We scan
1290 backwards from the target label. If we find a NOTE_INSN_LOOP_BEG
1291 before the next real insn, we assume the branch is to the top of
1293 for (insn
= PREV_INSN (target_label
);
1294 insn
&& GET_CODE (insn
) == NOTE
;
1295 insn
= PREV_INSN (insn
))
1296 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
1299 /* If this is a jump to the test of a loop, it is likely true. We scan
1300 forwards from the target label. If we find a NOTE_INSN_LOOP_VTOP
1301 before the next real insn, we assume the branch is to the loop branch
1303 for (insn
= NEXT_INSN (target_label
);
1304 insn
&& GET_CODE (insn
) == NOTE
;
1305 insn
= PREV_INSN (insn
))
1306 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_VTOP
)
1310 /* Look at the relative rarities of the fallthough and destination. If
1311 they differ, we can predict the branch that way. */
1313 switch (rare_fallthrough
- rare_dest
)
1327 /* If we couldn't figure out what this jump was, assume it won't be
1328 taken. This should be rare. */
1332 /* EQ tests are usually false and NE tests are usually true. Also,
1333 most quantities are positive, so we can make the appropriate guesses
1334 about signed comparisons against zero. */
1335 switch (GET_CODE (condition
))
1338 /* Unconditional branch. */
1346 if (XEXP (condition
, 1) == const0_rtx
)
1351 if (XEXP (condition
, 1) == const0_rtx
)
1356 /* Predict backward branches usually take, forward branches usually not. If
1357 we don't know whether this is forward or backward, assume the branch
1358 will be taken, since most are. */
1359 return (target_label
== 0 || INSN_UID (jump_insn
) > max_uid
1360 || INSN_UID (target_label
) > max_uid
1361 || (uid_to_ruid
[INSN_UID (jump_insn
)]
1362 > uid_to_ruid
[INSN_UID (target_label
)]));;
1365 /* Return the condition under which INSN will branch to TARGET. If TARGET
1366 is zero, return the condition under which INSN will return. If INSN is
1367 an unconditional branch, return const_true_rtx. If INSN isn't a simple
1368 type of jump, or it doesn't go to TARGET, return 0. */
1371 get_branch_condition (insn
, target
)
1375 rtx pat
= PATTERN (insn
);
1378 if (GET_CODE (pat
) == RETURN
)
1379 return target
== 0 ? const_true_rtx
: 0;
1381 else if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
1384 src
= SET_SRC (pat
);
1385 if (GET_CODE (src
) == LABEL_REF
&& XEXP (src
, 0) == target
)
1386 return const_true_rtx
;
1388 else if (GET_CODE (src
) == IF_THEN_ELSE
1389 && ((target
== 0 && GET_CODE (XEXP (src
, 1)) == RETURN
)
1390 || (GET_CODE (XEXP (src
, 1)) == LABEL_REF
1391 && XEXP (XEXP (src
, 1), 0) == target
))
1392 && XEXP (src
, 2) == pc_rtx
)
1393 return XEXP (src
, 0);
1395 else if (GET_CODE (src
) == IF_THEN_ELSE
1396 && ((target
== 0 && GET_CODE (XEXP (src
, 2)) == RETURN
)
1397 || (GET_CODE (XEXP (src
, 2)) == LABEL_REF
1398 && XEXP (XEXP (src
, 2), 0) == target
))
1399 && XEXP (src
, 1) == pc_rtx
)
1400 return gen_rtx (reverse_condition (GET_CODE (XEXP (src
, 0))),
1401 GET_MODE (XEXP (src
, 0)),
1402 XEXP (XEXP (src
, 0), 0), XEXP (XEXP (src
, 0), 1));
1407 /* Return non-zero if CONDITION is more strict than the condition of
1408 INSN, i.e., if INSN will always branch if CONDITION is true. */
1411 condition_dominates_p (condition
, insn
)
1415 rtx other_condition
= get_branch_condition (insn
, JUMP_LABEL (insn
));
1416 enum rtx_code code
= GET_CODE (condition
);
1417 enum rtx_code other_code
;
1419 if (rtx_equal_p (condition
, other_condition
)
1420 || other_condition
== const_true_rtx
)
1423 else if (condition
== const_true_rtx
|| other_condition
== 0)
1426 other_code
= GET_CODE (other_condition
);
1427 if (GET_RTX_LENGTH (code
) != 2 || GET_RTX_LENGTH (other_code
) != 2
1428 || ! rtx_equal_p (XEXP (condition
, 0), XEXP (other_condition
, 0))
1429 || ! rtx_equal_p (XEXP (condition
, 1), XEXP (other_condition
, 1)))
1432 return comparison_dominates_p (code
, other_code
);
1435 /* Return non-zero if redirecting JUMP to NEWLABEL does not invalidate
1436 any insns already in the delay slot of JUMP. */
1439 redirect_with_delay_slots_safe_p (jump
, newlabel
, seq
)
1440 rtx jump
, newlabel
, seq
;
1442 int flags
, slots
, i
;
1443 rtx pat
= PATTERN (seq
);
1445 /* Make sure all the delay slots of this jump would still
1446 be valid after threading the jump. If they are still
1447 valid, then return non-zero. */
1449 flags
= get_jump_flags (jump
, newlabel
);
1450 for (i
= 1; i
< XVECLEN (pat
, 0); i
++)
1452 #ifdef ANNUL_IFFALSE_SLOTS
1453 (INSN_ANNULLED_BRANCH_P (jump
)
1454 && INSN_FROM_TARGET_P (XVECEXP (pat
, 0, i
)))
1455 ? eligible_for_annul_false (jump
, i
- 1,
1456 XVECEXP (pat
, 0, i
), flags
) :
1458 #ifdef ANNUL_IFTRUE_SLOTS
1459 (INSN_ANNULLED_BRANCH_P (jump
)
1460 && ! INSN_FROM_TARGET_P (XVECEXP (pat
, 0, i
)))
1461 ? eligible_for_annul_true (jump
, i
- 1,
1462 XVECEXP (pat
, 0, i
), flags
) :
1464 eligible_for_delay (jump
, i
-1, XVECEXP (pat
, 0, i
), flags
)))
1467 return (i
== XVECLEN (pat
, 0));
1471 /* INSN branches to an insn whose pattern SEQ is a SEQUENCE. Given that
1472 the condition tested by INSN is CONDITION and the resources shown in
1473 OTHER_NEEDED are needed after INSN, see whether INSN can take all the insns
1474 from SEQ's delay list, in addition to whatever insns it may execute
1475 (in DELAY_LIST). SETS and NEEDED are denote resources already set and
1476 needed while searching for delay slot insns. Return the concatenated
1477 delay list if possible, otherwise, return 0.
1479 SLOTS_TO_FILL is the total number of slots required by INSN, and
1480 PSLOTS_FILLED points to the number filled so far (also the number of
1481 insns in DELAY_LIST). It is updated with the number that have been
1482 filled from the SEQUENCE, if any.
1484 PANNUL_P points to a non-zero value if we already know that we need
1485 to annul INSN. If this routine determines that annulling is needed,
1486 it may set that value non-zero.
1488 PNEW_THREAD points to a location that is to receive the place at which
1489 execution should continue. */
1492 steal_delay_list_from_target (insn
, condition
, seq
, delay_list
,
1493 sets
, needed
, other_needed
,
1494 slots_to_fill
, pslots_filled
, pannul_p
,
1496 rtx insn
, condition
;
1499 struct resources
*sets
, *needed
, *other_needed
;
1506 int slots_remaining
= slots_to_fill
- *pslots_filled
;
1507 int total_slots_filled
= *pslots_filled
;
1508 rtx new_delay_list
= 0;
1509 int must_annul
= *pannul_p
;
1512 /* We can't do anything if there are more delay slots in SEQ than we
1513 can handle, or if we don't know that it will be a taken branch.
1515 We know that it will be a taken branch if it is either an unconditional
1516 branch or a conditional branch with a stricter branch condition. */
1518 if (XVECLEN (seq
, 0) - 1 > slots_remaining
1519 || ! condition_dominates_p (condition
, XVECEXP (seq
, 0, 0)))
1522 for (i
= 1; i
< XVECLEN (seq
, 0); i
++)
1524 rtx trial
= XVECEXP (seq
, 0, i
);
1527 if (insn_references_resource_p (trial
, sets
, 0)
1528 || insn_sets_resource_p (trial
, needed
, 0)
1529 || insn_sets_resource_p (trial
, sets
, 0)
1531 /* If TRIAL sets CC0, we can't copy it, so we can't steal this
1533 || find_reg_note (trial
, REG_CC_USER
, NULL_RTX
)
1535 /* If TRIAL is from the fallthrough code of an annulled branch insn
1536 in SEQ, we cannot use it. */
1537 || (INSN_ANNULLED_BRANCH_P (XVECEXP (seq
, 0, 0))
1538 && ! INSN_FROM_TARGET_P (trial
)))
1541 /* If this insn was already done (usually in a previous delay slot),
1542 pretend we put it in our delay slot. */
1543 if (redundant_insn_p (trial
, insn
, new_delay_list
))
1546 /* We will end up re-vectoring this branch, so compute flags
1547 based on jumping to the new label. */
1548 flags
= get_jump_flags (insn
, JUMP_LABEL (XVECEXP (seq
, 0, 0)));
1551 && ((condition
== const_true_rtx
1552 || (! insn_sets_resource_p (trial
, other_needed
, 0)
1553 && ! may_trap_p (PATTERN (trial
)))))
1554 ? eligible_for_delay (insn
, total_slots_filled
, trial
, flags
)
1556 eligible_for_annul_false (insn
, total_slots_filled
, trial
, flags
)))
1558 temp
= copy_rtx (trial
);
1559 INSN_FROM_TARGET_P (temp
) = 1;
1560 new_delay_list
= add_to_delay_list (temp
, new_delay_list
);
1561 total_slots_filled
++;
1563 if (--slots_remaining
== 0)
1570 /* Show the place to which we will be branching. */
1571 *pnew_thread
= next_active_insn (JUMP_LABEL (XVECEXP (seq
, 0, 0)));
1573 /* Add any new insns to the delay list and update the count of the
1574 number of slots filled. */
1575 *pslots_filled
= total_slots_filled
;
1576 *pannul_p
= must_annul
;
1578 if (delay_list
== 0)
1579 return new_delay_list
;
1581 for (temp
= new_delay_list
; temp
; temp
= XEXP (temp
, 1))
1582 delay_list
= add_to_delay_list (XEXP (temp
, 0), delay_list
);
1587 /* Similar to steal_delay_list_from_target except that SEQ is on the
1588 fallthrough path of INSN. Here we only do something if the delay insn
1589 of SEQ is an unconditional branch. In that case we steal its delay slot
1590 for INSN since unconditional branches are much easier to fill. */
1593 steal_delay_list_from_fallthrough (insn
, condition
, seq
,
1594 delay_list
, sets
, needed
, other_needed
,
1595 slots_to_fill
, pslots_filled
, pannul_p
)
1596 rtx insn
, condition
;
1599 struct resources
*sets
, *needed
, *other_needed
;
1607 flags
= get_jump_flags (insn
, JUMP_LABEL (insn
));
1609 /* We can't do anything if SEQ's delay insn isn't an
1610 unconditional branch. */
1612 if (! simplejump_p (XVECEXP (seq
, 0, 0))
1613 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) != RETURN
)
1616 for (i
= 1; i
< XVECLEN (seq
, 0); i
++)
1618 rtx trial
= XVECEXP (seq
, 0, i
);
1620 /* If TRIAL sets CC0, stealing it will move it too far from the use
1622 if (insn_references_resource_p (trial
, sets
, 0)
1623 || insn_sets_resource_p (trial
, needed
, 0)
1624 || insn_sets_resource_p (trial
, sets
, 0)
1626 || sets_cc0_p (PATTERN (trial
))
1632 /* If this insn was already done, we don't need it. */
1633 if (redundant_insn_p (trial
, insn
, delay_list
))
1635 delete_from_delay_slot (trial
);
1640 && ((condition
== const_true_rtx
1641 || (! insn_sets_resource_p (trial
, other_needed
, 0)
1642 && ! may_trap_p (PATTERN (trial
)))))
1643 ? eligible_for_delay (insn
, *pslots_filled
, trial
, flags
)
1645 eligible_for_annul_true (insn
, *pslots_filled
, trial
, flags
)))
1647 delete_from_delay_slot (trial
);
1648 delay_list
= add_to_delay_list (trial
, delay_list
);
1650 if (++(*pslots_filled
) == slots_to_fill
)
1660 /* Try merging insns starting at THREAD which match exactly the insns in
1663 If all insns were matched and the insn was previously annulling, the
1664 annul bit will be cleared.
1666 For each insn that is merged, if the branch is or will be non-annulling,
1667 we delete the merged insn. */
1670 try_merge_delay_insns (insn
, thread
)
1673 rtx trial
, next_trial
;
1674 rtx delay_insn
= XVECEXP (PATTERN (insn
), 0, 0);
1675 int annul_p
= INSN_ANNULLED_BRANCH_P (delay_insn
);
1676 int slot_number
= 1;
1677 int num_slots
= XVECLEN (PATTERN (insn
), 0);
1678 rtx next_to_match
= XVECEXP (PATTERN (insn
), 0, slot_number
);
1679 struct resources set
, needed
;
1680 rtx merged_insns
= 0;
1684 flags
= get_jump_flags (delay_insn
, JUMP_LABEL (delay_insn
));
1686 CLEAR_RESOURCE (&needed
);
1687 CLEAR_RESOURCE (&set
);
1689 /* If this is not an annulling branch, take into account anything needed in
1690 NEXT_TO_MATCH. This prevents two increments from being incorrectly
1691 folded into one. If we are annulling, this would be the correct
1692 thing to do. (The alternative, looking at things set in NEXT_TO_MATCH
1693 will essentially disable this optimization. This method is somewhat of
1694 a kludge, but I don't see a better way.) */
1696 mark_referenced_resources (next_to_match
, &needed
, 1);
1698 for (trial
= thread
; !stop_search_p (trial
, 1); trial
= next_trial
)
1700 rtx pat
= PATTERN (trial
);
1702 next_trial
= next_nonnote_insn (trial
);
1704 /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */
1705 if (GET_CODE (trial
) == INSN
1706 && (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
))
1709 if (GET_CODE (next_to_match
) == GET_CODE (trial
)
1711 /* We can't share an insn that sets cc0. */
1712 && ! sets_cc0_p (pat
)
1714 && ! insn_references_resource_p (trial
, &set
, 1)
1715 && ! insn_sets_resource_p (trial
, &set
, 1)
1716 && ! insn_sets_resource_p (trial
, &needed
, 1)
1717 && (trial
= try_split (pat
, trial
, 0)) != 0
1718 && rtx_equal_p (PATTERN (next_to_match
), PATTERN (trial
))
1719 /* Have to test this condition if annul condition is different
1720 from (and less restrictive than) non-annulling one. */
1721 && eligible_for_delay (delay_insn
, slot_number
- 1, trial
, flags
))
1723 next_trial
= next_nonnote_insn (trial
);
1727 update_block (trial
, thread
);
1728 delete_insn (trial
);
1729 INSN_FROM_TARGET_P (next_to_match
) = 0;
1732 merged_insns
= gen_rtx (INSN_LIST
, VOIDmode
, trial
, merged_insns
);
1734 if (++slot_number
== num_slots
)
1737 next_to_match
= XVECEXP (PATTERN (insn
), 0, slot_number
);
1739 mark_referenced_resources (next_to_match
, &needed
, 1);
1742 mark_set_resources (trial
, &set
, 0, 1);
1743 mark_referenced_resources (trial
, &needed
, 1);
1746 /* See if we stopped on a filled insn. If we did, try to see if its
1747 delay slots match. */
1748 if (slot_number
!= num_slots
1749 && trial
&& GET_CODE (trial
) == INSN
1750 && GET_CODE (PATTERN (trial
)) == SEQUENCE
1751 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (PATTERN (trial
), 0, 0)))
1753 rtx pat
= PATTERN (trial
);
1755 for (i
= 1; i
< XVECLEN (pat
, 0); i
++)
1757 rtx dtrial
= XVECEXP (pat
, 0, i
);
1759 if (! insn_references_resource_p (dtrial
, &set
, 1)
1760 && ! insn_sets_resource_p (dtrial
, &set
, 1)
1761 && ! insn_sets_resource_p (dtrial
, &needed
, 1)
1763 && ! sets_cc0_p (PATTERN (dtrial
))
1765 && rtx_equal_p (PATTERN (next_to_match
), PATTERN (dtrial
))
1766 && eligible_for_delay (delay_insn
, slot_number
- 1, dtrial
, flags
))
1770 update_block (dtrial
, thread
);
1771 delete_from_delay_slot (dtrial
);
1772 INSN_FROM_TARGET_P (next_to_match
) = 0;
1775 merged_insns
= gen_rtx (INSN_LIST
, SImode
, dtrial
,
1778 if (++slot_number
== num_slots
)
1781 next_to_match
= XVECEXP (PATTERN (insn
), 0, slot_number
);
1786 /* If all insns in the delay slot have been matched and we were previously
1787 annulling the branch, we need not any more. In that case delete all the
1788 merged insns. Also clear the INSN_FROM_TARGET_P bit of each insn the
1789 the delay list so that we know that it isn't only being used at the
1791 if (next_to_match
== 0 && annul_p
)
1793 for (; merged_insns
; merged_insns
= XEXP (merged_insns
, 1))
1795 if (GET_MODE (merged_insns
) == SImode
)
1797 update_block (XEXP (merged_insns
, 0), thread
);
1798 delete_from_delay_slot (XEXP (merged_insns
, 0));
1802 update_block (XEXP (merged_insns
, 0), thread
);
1803 delete_insn (XEXP (merged_insns
, 0));
1807 INSN_ANNULLED_BRANCH_P (delay_insn
) = 0;
1809 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1810 INSN_FROM_TARGET_P (XVECEXP (PATTERN (insn
), 0, i
)) = 0;
1814 /* See if INSN is redundant with an insn in front of TARGET. Often this
1815 is called when INSN is a candidate for a delay slot of TARGET.
1816 DELAY_LIST are insns that will be placed in delay slots of TARGET in front
1817 of INSN. Often INSN will be redundant with an insn in a delay slot of
1818 some previous insn. This happens when we have a series of branches to the
1819 same label; in that case the first insn at the target might want to go
1820 into each of the delay slots.
1822 If we are not careful, this routine can take up a significant fraction
1823 of the total compilation time (4%), but only wins rarely. Hence we
1824 speed this routine up by making two passes. The first pass goes back
1825 until it hits a label and sees if it find an insn with an identical
1826 pattern. Only in this (relatively rare) event does it check for
1829 We do not split insns we encounter. This could cause us not to find a
1830 redundant insn, but the cost of splitting seems greater than the possible
1831 gain in rare cases. */
1834 redundant_insn_p (insn
, target
, delay_list
)
1839 rtx target_main
= target
;
1840 rtx ipat
= PATTERN (insn
);
1842 struct resources needed
, set
;
1845 /* Scan backwards looking for a match. */
1846 for (trial
= PREV_INSN (target
); trial
; trial
= PREV_INSN (trial
))
1848 if (GET_CODE (trial
) == CODE_LABEL
)
1851 if (GET_RTX_CLASS (GET_CODE (trial
)) != 'i')
1854 pat
= PATTERN (trial
);
1855 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
1858 if (GET_CODE (pat
) == SEQUENCE
)
1860 /* Stop for a CALL and its delay slots because it is difficult to
1861 track its resource needs correctly. */
1862 if (GET_CODE (XVECEXP (pat
, 0, 0)) == CALL_INSN
)
1865 /* Stop for an INSN or JUMP_INSN with delayed effects and its delay
1866 slots because it is difficult to track its resource needs
1869 #ifdef INSN_SETS_ARE_DELAYED
1870 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat
, 0, 0)))
1874 #ifdef INSN_REFERENCES_ARE_DELAYED
1875 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat
, 0, 0)))
1879 /* See if any of the insns in the delay slot match, updating
1880 resource requirements as we go. */
1881 for (i
= XVECLEN (pat
, 0) - 1; i
> 0; i
--)
1882 if (GET_CODE (XVECEXP (pat
, 0, i
)) == GET_CODE (insn
)
1883 && rtx_equal_p (PATTERN (XVECEXP (pat
, 0, i
)), ipat
))
1886 /* If found a match, exit this loop early. */
1891 else if (GET_CODE (trial
) == GET_CODE (insn
) && rtx_equal_p (pat
, ipat
))
1895 /* If we didn't find an insn that matches, return 0. */
1899 /* See what resources this insn sets and needs. If they overlap, or
1900 if this insn references CC0, it can't be redundant. */
1902 CLEAR_RESOURCE (&needed
);
1903 CLEAR_RESOURCE (&set
);
1904 mark_set_resources (insn
, &set
, 0, 1);
1905 mark_referenced_resources (insn
, &needed
, 1);
1907 /* If TARGET is a SEQUENCE, get the main insn. */
1908 if (GET_CODE (target
) == INSN
&& GET_CODE (PATTERN (target
)) == SEQUENCE
)
1909 target_main
= XVECEXP (PATTERN (target
), 0, 0);
1911 if (resource_conflicts_p (&needed
, &set
)
1913 || reg_mentioned_p (cc0_rtx
, ipat
)
1915 /* The insn requiring the delay may not set anything needed or set by
1917 || insn_sets_resource_p (target_main
, &needed
, 1)
1918 || insn_sets_resource_p (target_main
, &set
, 1))
1921 /* Insns we pass may not set either NEEDED or SET, so merge them for
1923 needed
.memory
|= set
.memory
;
1924 IOR_HARD_REG_SET (needed
.regs
, set
.regs
);
1926 /* This insn isn't redundant if it conflicts with an insn that either is
1927 or will be in a delay slot of TARGET. */
1931 if (insn_sets_resource_p (XEXP (delay_list
, 0), &needed
, 1))
1933 delay_list
= XEXP (delay_list
, 1);
1936 if (GET_CODE (target
) == INSN
&& GET_CODE (PATTERN (target
)) == SEQUENCE
)
1937 for (i
= 1; i
< XVECLEN (PATTERN (target
), 0); i
++)
1938 if (insn_sets_resource_p (XVECEXP (PATTERN (target
), 0, i
), &needed
, 1))
1941 /* Scan backwards until we reach a label or an insn that uses something
1942 INSN sets or sets something insn uses or sets. */
1944 for (trial
= PREV_INSN (target
);
1945 trial
&& GET_CODE (trial
) != CODE_LABEL
;
1946 trial
= PREV_INSN (trial
))
1948 if (GET_CODE (trial
) != INSN
&& GET_CODE (trial
) != CALL_INSN
1949 && GET_CODE (trial
) != JUMP_INSN
)
1952 pat
= PATTERN (trial
);
1953 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
1956 if (GET_CODE (pat
) == SEQUENCE
)
1958 /* If this is a CALL_INSN and its delay slots, it is hard to track
1959 the resource needs properly, so give up. */
1960 if (GET_CODE (XVECEXP (pat
, 0, 0)) == CALL_INSN
)
1963 /* If this this is an INSN or JUMP_INSN with delayed effects, it
1964 is hard to track the resource needs properly, so give up. */
1966 #ifdef INSN_SETS_ARE_DELAYED
1967 if (INSN_SETS_ARE_DELAYED (XVECEXP (pat
, 0, 0)))
1971 #ifdef INSN_REFERENCES_ARE_DELAYED
1972 if (INSN_REFERENCES_ARE_DELAYED (XVECEXP (pat
, 0, 0)))
1976 /* See if any of the insns in the delay slot match, updating
1977 resource requirements as we go. */
1978 for (i
= XVECLEN (pat
, 0) - 1; i
> 0; i
--)
1980 rtx candidate
= XVECEXP (pat
, 0, i
);
1982 /* If an insn will be annulled if the branch is false, it isn't
1983 considered as a possible duplicate insn. */
1984 if (rtx_equal_p (PATTERN (candidate
), ipat
)
1985 && ! (INSN_ANNULLED_BRANCH_P (XVECEXP (pat
, 0, 0))
1986 && INSN_FROM_TARGET_P (candidate
)))
1988 /* Show that this insn will be used in the sequel. */
1989 INSN_FROM_TARGET_P (candidate
) = 0;
1993 /* Unless this is an annulled insn from the target of a branch,
1994 we must stop if it sets anything needed or set by INSN. */
1995 if ((! INSN_ANNULLED_BRANCH_P (XVECEXP (pat
, 0, 0))
1996 || ! INSN_FROM_TARGET_P (candidate
))
1997 && insn_sets_resource_p (candidate
, &needed
, 1))
2002 /* If the insn requiring the delay slot conflicts with INSN, we
2004 if (insn_sets_resource_p (XVECEXP (pat
, 0, 0), &needed
, 1))
2009 /* See if TRIAL is the same as INSN. */
2010 pat
= PATTERN (trial
);
2011 if (rtx_equal_p (pat
, ipat
))
2014 /* Can't go any further if TRIAL conflicts with INSN. */
2015 if (insn_sets_resource_p (trial
, &needed
, 1))
2023 /* Return 1 if THREAD can only be executed in one way. If LABEL is non-zero,
2024 it is the target of the branch insn being scanned. If ALLOW_FALLTHROUGH
2025 is non-zero, we are allowed to fall into this thread; otherwise, we are
2028 If LABEL is used more than one or we pass a label other than LABEL before
2029 finding an active insn, we do not own this thread. */
2032 own_thread_p (thread
, label
, allow_fallthrough
)
2035 int allow_fallthrough
;
2040 /* We don't own the function end. */
2044 /* Get the first active insn, or THREAD, if it is an active insn. */
2045 active_insn
= next_active_insn (PREV_INSN (thread
));
2047 for (insn
= thread
; insn
!= active_insn
; insn
= NEXT_INSN (insn
))
2048 if (GET_CODE (insn
) == CODE_LABEL
2049 && (insn
!= label
|| LABEL_NUSES (insn
) != 1))
2052 if (allow_fallthrough
)
2055 /* Ensure that we reach a BARRIER before any insn or label. */
2056 for (insn
= prev_nonnote_insn (thread
);
2057 insn
== 0 || GET_CODE (insn
) != BARRIER
;
2058 insn
= prev_nonnote_insn (insn
))
2060 || GET_CODE (insn
) == CODE_LABEL
2061 || (GET_CODE (insn
) == INSN
2062 && GET_CODE (PATTERN (insn
)) != USE
2063 && GET_CODE (PATTERN (insn
)) != CLOBBER
))
2069 /* Find the number of the basic block that starts closest to INSN. Return -1
2070 if we couldn't find such a basic block. */
2073 find_basic_block (insn
)
2078 /* Scan backwards to the previous BARRIER. Then see if we can find a
2079 label that starts a basic block. Return the basic block number. */
2081 for (insn
= prev_nonnote_insn (insn
);
2082 insn
&& GET_CODE (insn
) != BARRIER
;
2083 insn
= prev_nonnote_insn (insn
))
2086 /* The start of the function is basic block zero. */
2090 /* See if any of the upcoming CODE_LABELs start a basic block. If we reach
2091 anything other than a CODE_LABEL or note, we can't find this code. */
2092 for (insn
= next_nonnote_insn (insn
);
2093 insn
&& GET_CODE (insn
) == CODE_LABEL
;
2094 insn
= next_nonnote_insn (insn
))
2096 for (i
= 0; i
< n_basic_blocks
; i
++)
2097 if (insn
== basic_block_head
[i
])
2104 /* Called when INSN is being moved from a location near the target of a jump.
2105 We leave a marker of the form (use (INSN)) immediately in front
2106 of WHERE for mark_target_live_regs. These markers will be deleted when
2109 We used to try to update the live status of registers if WHERE is at
2110 the start of a basic block, but that can't work since we may remove a
2111 BARRIER in relax_delay_slots. */
2114 update_block (insn
, where
)
2120 /* Ignore if this was in a delay slot and it came from the target of
2122 if (INSN_FROM_TARGET_P (insn
))
2125 emit_insn_before (gen_rtx (USE
, VOIDmode
, insn
), where
);
2127 /* INSN might be making a value live in a block where it didn't use to
2128 be. So recompute liveness information for this block. */
2130 b
= find_basic_block (insn
);
2135 /* Similar to REDIRECT_JUMP except that we update the BB_TICKS entry for
2136 the basic block containing the jump. */
2139 reorg_redirect_jump (jump
, nlabel
)
2143 int b
= find_basic_block (jump
);
2148 return redirect_jump (jump
, nlabel
);
2151 /* Called when INSN is being moved forward into a delay slot of DELAYED_INSN.
2152 We check every instruction between INSN and DELAYED_INSN for REG_DEAD notes
2153 that reference values used in INSN. If we find one, then we move the
2154 REG_DEAD note to INSN.
2156 This is needed to handle the case where an later insn (after INSN) has a
2157 REG_DEAD note for a register used by INSN, and this later insn subsequently
2158 gets moved before a CODE_LABEL because it is a redundant insn. In this
2159 case, mark_target_live_regs may be confused into thinking the register
2160 is dead because it sees a REG_DEAD note immediately before a CODE_LABEL. */
2163 update_reg_dead_notes (insn
, delayed_insn
)
2164 rtx insn
, delayed_insn
;
2168 for (p
= next_nonnote_insn (insn
); p
!= delayed_insn
;
2169 p
= next_nonnote_insn (p
))
2170 for (link
= REG_NOTES (p
); link
; link
= next
)
2172 next
= XEXP (link
, 1);
2174 if (REG_NOTE_KIND (link
) != REG_DEAD
2175 || GET_CODE (XEXP (link
, 0)) != REG
)
2178 if (reg_referenced_p (XEXP (link
, 0), PATTERN (insn
)))
2180 /* Move the REG_DEAD note from P to INSN. */
2181 remove_note (p
, link
);
2182 XEXP (link
, 1) = REG_NOTES (insn
);
2183 REG_NOTES (insn
) = link
;
2188 /* Marks registers possibly live at the current place being scanned by
2189 mark_target_live_regs. Used only by next two function. */
2191 static HARD_REG_SET current_live_regs
;
2193 /* Marks registers for which we have seen a REG_DEAD note but no assignment.
2194 Also only used by the next two functions. */
2196 static HARD_REG_SET pending_dead_regs
;
2198 /* Utility function called from mark_target_live_regs via note_stores.
2199 It deadens any CLOBBERed registers and livens any SET registers. */
2202 update_live_status (dest
, x
)
2206 int first_regno
, last_regno
;
2209 if (GET_CODE (dest
) != REG
2210 && (GET_CODE (dest
) != SUBREG
|| GET_CODE (SUBREG_REG (dest
)) != REG
))
2213 if (GET_CODE (dest
) == SUBREG
)
2214 first_regno
= REGNO (SUBREG_REG (dest
)) + SUBREG_WORD (dest
);
2216 first_regno
= REGNO (dest
);
2218 last_regno
= first_regno
+ HARD_REGNO_NREGS (first_regno
, GET_MODE (dest
));
2220 if (GET_CODE (x
) == CLOBBER
)
2221 for (i
= first_regno
; i
< last_regno
; i
++)
2222 CLEAR_HARD_REG_BIT (current_live_regs
, i
);
2224 for (i
= first_regno
; i
< last_regno
; i
++)
2226 SET_HARD_REG_BIT (current_live_regs
, i
);
2227 CLEAR_HARD_REG_BIT (pending_dead_regs
, i
);
2231 /* Similar to next_insn, but ignores insns in the delay slots of
2232 an annulled branch. */
2235 next_insn_no_annul (insn
)
2240 /* If INSN is an annulled branch, skip any insns from the target
2242 if (INSN_ANNULLED_BRANCH_P (insn
)
2243 && NEXT_INSN (PREV_INSN (insn
)) != insn
)
2244 while (INSN_FROM_TARGET_P (NEXT_INSN (insn
)))
2245 insn
= NEXT_INSN (insn
);
2247 insn
= NEXT_INSN (insn
);
2248 if (insn
&& GET_CODE (insn
) == INSN
2249 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2250 insn
= XVECEXP (PATTERN (insn
), 0, 0);
2256 /* Set the resources that are live at TARGET.
2258 If TARGET is zero, we refer to the end of the current function and can
2259 return our precomputed value.
2261 Otherwise, we try to find out what is live by consulting the basic block
2262 information. This is tricky, because we must consider the actions of
2263 reload and jump optimization, which occur after the basic block information
2266 Accordingly, we proceed as follows::
2268 We find the previous BARRIER and look at all immediately following labels
2269 (with no intervening active insns) to see if any of them start a basic
2270 block. If we hit the start of the function first, we use block 0.
2272 Once we have found a basic block and a corresponding first insns, we can
2273 accurately compute the live status from basic_block_live_regs and
2274 reg_renumber. (By starting at a label following a BARRIER, we are immune
2275 to actions taken by reload and jump.) Then we scan all insns between
2276 that point and our target. For each CLOBBER (or for call-clobbered regs
2277 when we pass a CALL_INSN), mark the appropriate registers are dead. For
2278 a SET, mark them as live.
2280 We have to be careful when using REG_DEAD notes because they are not
2281 updated by such things as find_equiv_reg. So keep track of registers
2282 marked as dead that haven't been assigned to, and mark them dead at the
2283 next CODE_LABEL since reload and jump won't propagate values across labels.
2285 If we cannot find the start of a basic block (should be a very rare
2286 case, if it can happen at all), mark everything as potentially live.
2288 Next, scan forward from TARGET looking for things set or clobbered
2289 before they are used. These are not live.
2291 Because we can be called many times on the same target, save our results
2292 in a hash table indexed by INSN_UID. */
2295 mark_target_live_regs (target
, res
)
2297 struct resources
*res
;
2301 struct target_info
*tinfo
;
2305 HARD_REG_SET scratch
;
2306 struct resources set
, needed
;
2309 /* Handle end of function. */
2312 *res
= end_of_function_needs
;
2316 /* We have to assume memory is needed, but the CC isn't. */
2321 /* See if we have computed this value already. */
2322 for (tinfo
= target_hash_table
[INSN_UID (target
) % TARGET_HASH_PRIME
];
2323 tinfo
; tinfo
= tinfo
->next
)
2324 if (tinfo
->uid
== INSN_UID (target
))
2327 /* Start by getting the basic block number. If we have saved information,
2328 we can get it from there unless the insn at the start of the basic block
2329 has been deleted. */
2330 if (tinfo
&& tinfo
->block
!= -1
2331 && ! INSN_DELETED_P (basic_block_head
[tinfo
->block
]))
2335 b
= find_basic_block (target
);
2339 /* If the information is up-to-date, use it. Otherwise, we will
2341 if (b
== tinfo
->block
&& b
!= -1 && tinfo
->bb_tick
== bb_ticks
[b
])
2343 COPY_HARD_REG_SET (res
->regs
, tinfo
->live_regs
);
2349 /* Allocate a place to put our results and chain it into the
2351 tinfo
= (struct target_info
*) oballoc (sizeof (struct target_info
));
2352 tinfo
->uid
= INSN_UID (target
);
2354 tinfo
->next
= target_hash_table
[INSN_UID (target
) % TARGET_HASH_PRIME
];
2355 target_hash_table
[INSN_UID (target
) % TARGET_HASH_PRIME
] = tinfo
;
2358 CLEAR_HARD_REG_SET (pending_dead_regs
);
2360 /* If we found a basic block, get the live registers from it and update
2361 them with anything set or killed between its start and the insn before
2362 TARGET. Otherwise, we must assume everything is live. */
2365 regset regs_live
= basic_block_live_at_start
[b
];
2367 REGSET_ELT_TYPE bit
;
2369 rtx start_insn
, stop_insn
;
2371 /* Compute hard regs live at start of block -- this is the real hard regs
2372 marked live, plus live pseudo regs that have been renumbered to
2376 current_live_regs
= *regs_live
;
2378 COPY_HARD_REG_SET (current_live_regs
, regs_live
);
2381 for (offset
= 0, i
= 0; offset
< regset_size
; offset
++)
2383 if (regs_live
[offset
] == 0)
2384 i
+= REGSET_ELT_BITS
;
2386 for (bit
= 1; bit
&& i
< max_regno
; bit
<<= 1, i
++)
2387 if ((regs_live
[offset
] & bit
)
2388 && (regno
= reg_renumber
[i
]) >= 0)
2390 j
< regno
+ HARD_REGNO_NREGS (regno
,
2391 PSEUDO_REGNO_MODE (i
));
2393 SET_HARD_REG_BIT (current_live_regs
, j
);
2396 /* Get starting and ending insn, handling the case where each might
2398 start_insn
= (b
== 0 ? get_insns () : basic_block_head
[b
]);
2401 if (GET_CODE (start_insn
) == INSN
2402 && GET_CODE (PATTERN (start_insn
)) == SEQUENCE
)
2403 start_insn
= XVECEXP (PATTERN (start_insn
), 0, 0);
2405 if (GET_CODE (stop_insn
) == INSN
2406 && GET_CODE (PATTERN (stop_insn
)) == SEQUENCE
)
2407 stop_insn
= next_insn (PREV_INSN (stop_insn
));
2409 for (insn
= start_insn
; insn
!= stop_insn
;
2410 insn
= next_insn_no_annul (insn
))
2413 rtx real_insn
= insn
;
2415 /* If this insn is from the target of a branch, it isn't going to
2416 be used in the sequel. If it is used in both cases, this
2417 test will not be true. */
2418 if (INSN_FROM_TARGET_P (insn
))
2421 /* If this insn is a USE made by update_block, we care about the
2423 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
2424 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn
), 0))) == 'i')
2425 real_insn
= XEXP (PATTERN (insn
), 0);
2427 if (GET_CODE (real_insn
) == CALL_INSN
)
2429 /* CALL clobbers all call-used regs that aren't fixed except
2430 sp, ap, and fp. Do this before setting the result of the
2432 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2433 if (call_used_regs
[i
]
2434 && i
!= STACK_POINTER_REGNUM
&& i
!= FRAME_POINTER_REGNUM
2435 && i
!= ARG_POINTER_REGNUM
2436 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2437 && ! (i
== ARG_POINTER_REGNUM
&& fixed_regs
[i
])
2439 #ifdef PIC_OFFSET_TABLE_REGNUM
2440 && ! (i
== PIC_OFFSET_TABLE_REGNUM
&& flag_pic
)
2443 CLEAR_HARD_REG_BIT (current_live_regs
, i
);
2445 /* A CALL_INSN sets any global register live, since it may
2446 have been modified by the call. */
2447 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2449 SET_HARD_REG_BIT (current_live_regs
, i
);
2452 /* Mark anything killed in an insn to be deadened at the next
2453 label. Ignore USE insns; the only REG_DEAD notes will be for
2454 parameters. But they might be early. A CALL_INSN will usually
2455 clobber registers used for parameters. It isn't worth bothering
2456 with the unlikely case when it won't. */
2457 if ((GET_CODE (real_insn
) == INSN
2458 && GET_CODE (PATTERN (real_insn
)) != USE
)
2459 || GET_CODE (real_insn
) == JUMP_INSN
2460 || GET_CODE (real_insn
) == CALL_INSN
)
2462 for (link
= REG_NOTES (real_insn
); link
; link
= XEXP (link
, 1))
2463 if (REG_NOTE_KIND (link
) == REG_DEAD
2464 && GET_CODE (XEXP (link
, 0)) == REG
2465 && REGNO (XEXP (link
, 0)) < FIRST_PSEUDO_REGISTER
)
2467 int first_regno
= REGNO (XEXP (link
, 0));
2470 + HARD_REGNO_NREGS (first_regno
,
2471 GET_MODE (XEXP (link
, 0))));
2473 for (i
= first_regno
; i
< last_regno
; i
++)
2474 SET_HARD_REG_BIT (pending_dead_regs
, i
);
2477 note_stores (PATTERN (real_insn
), update_live_status
);
2479 /* If any registers were unused after this insn, kill them.
2480 These notes will always be accurate. */
2481 for (link
= REG_NOTES (real_insn
); link
; link
= XEXP (link
, 1))
2482 if (REG_NOTE_KIND (link
) == REG_UNUSED
2483 && GET_CODE (XEXP (link
, 0)) == REG
2484 && REGNO (XEXP (link
, 0)) < FIRST_PSEUDO_REGISTER
)
2486 int first_regno
= REGNO (XEXP (link
, 0));
2489 + HARD_REGNO_NREGS (first_regno
,
2490 GET_MODE (XEXP (link
, 0))));
2492 for (i
= first_regno
; i
< last_regno
; i
++)
2493 CLEAR_HARD_REG_BIT (current_live_regs
, i
);
2497 else if (GET_CODE (real_insn
) == CODE_LABEL
)
2499 /* A label clobbers the pending dead registers since neither
2500 reload nor jump will propagate a value across a label. */
2501 AND_COMPL_HARD_REG_SET (current_live_regs
, pending_dead_regs
);
2502 CLEAR_HARD_REG_SET (pending_dead_regs
);
2505 /* The beginning of the epilogue corresponds to the end of the
2506 RTL chain when there are no epilogue insns. Certain resources
2507 are implicitly required at that point. */
2508 else if (GET_CODE (real_insn
) == NOTE
2509 && NOTE_LINE_NUMBER (real_insn
) == NOTE_INSN_EPILOGUE_BEG
)
2510 IOR_HARD_REG_SET (current_live_regs
, start_of_epilogue_needs
.regs
);
2513 COPY_HARD_REG_SET (res
->regs
, current_live_regs
);
2515 tinfo
->bb_tick
= bb_ticks
[b
];
2518 /* We didn't find the start of a basic block. Assume everything
2519 in use. This should happen only extremely rarely. */
2520 SET_HARD_REG_SET (res
->regs
);
2522 /* Now step forward from TARGET looking for registers that are set before
2523 they are used. These are dead. If we pass a label, any pending dead
2524 registers that weren't yet used can be made dead. Stop when we pass a
2525 conditional JUMP_INSN; follow the first few unconditional branches. */
2527 CLEAR_RESOURCE (&set
);
2528 CLEAR_RESOURCE (&needed
);
2530 for (insn
= target
; insn
; insn
= next
)
2532 rtx this_jump_insn
= insn
;
2534 next
= NEXT_INSN (insn
);
2535 switch (GET_CODE (insn
))
2538 AND_COMPL_HARD_REG_SET (pending_dead_regs
, needed
.regs
);
2539 AND_COMPL_HARD_REG_SET (res
->regs
, pending_dead_regs
);
2540 CLEAR_HARD_REG_SET (pending_dead_regs
);
2548 if (GET_CODE (PATTERN (insn
)) == USE
)
2550 /* If INSN is a USE made by update_block, we care about the
2551 underlying insn. Any registers set by the underlying insn
2552 are live since the insn is being done somewhere else. */
2553 if (GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn
), 0))) == 'i')
2554 mark_set_resources (XEXP (PATTERN (insn
), 0), res
, 0, 1);
2556 /* All other USE insns are to be ignored. */
2559 else if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
2561 else if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2563 /* An unconditional jump can be used to fill the delay slot
2564 of a call, so search for a JUMP_INSN in any position. */
2565 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
2567 this_jump_insn
= XVECEXP (PATTERN (insn
), 0, i
);
2568 if (GET_CODE (this_jump_insn
) == JUMP_INSN
)
2574 if (GET_CODE (this_jump_insn
) == JUMP_INSN
)
2576 if (jump_count
++ < 10
2577 && (simplejump_p (this_jump_insn
)
2578 || GET_CODE (PATTERN (this_jump_insn
)) == RETURN
))
2580 next
= next_active_insn (JUMP_LABEL (this_jump_insn
));
2584 jump_target
= JUMP_LABEL (this_jump_insn
);
2591 mark_referenced_resources (insn
, &needed
, 1);
2592 mark_set_resources (insn
, &set
, 0, 1);
2594 COPY_HARD_REG_SET (scratch
, set
.regs
);
2595 AND_COMPL_HARD_REG_SET (scratch
, needed
.regs
);
2596 AND_COMPL_HARD_REG_SET (res
->regs
, scratch
);
2599 /* If we hit an unconditional branch, we have another way of finding out
2600 what is live: we can see what is live at the branch target and include
2601 anything used but not set before the branch. The only things that are
2602 live are those that are live using the above test and the test below.
2604 Don't try this if we expired our jump count above, since that would
2605 mean there may be an infinite loop in the function being compiled. */
2607 if (jump_insn
&& jump_count
< 10)
2609 struct resources new_resources
;
2610 rtx stop_insn
= next_active_insn (jump_insn
);
2612 mark_target_live_regs (next_active_insn (jump_target
), &new_resources
);
2613 CLEAR_RESOURCE (&set
);
2614 CLEAR_RESOURCE (&needed
);
2616 /* Include JUMP_INSN in the needed registers. */
2617 for (insn
= target
; insn
!= stop_insn
; insn
= next_active_insn (insn
))
2619 mark_referenced_resources (insn
, &needed
, 1);
2621 COPY_HARD_REG_SET (scratch
, needed
.regs
);
2622 AND_COMPL_HARD_REG_SET (scratch
, set
.regs
);
2623 IOR_HARD_REG_SET (new_resources
.regs
, scratch
);
2625 mark_set_resources (insn
, &set
, 0, 1);
2628 AND_HARD_REG_SET (res
->regs
, new_resources
.regs
);
2631 COPY_HARD_REG_SET (tinfo
->live_regs
, res
->regs
);
2634 /* Scan a function looking for insns that need a delay slot and find insns to
2635 put into the delay slot.
2637 NON_JUMPS_P is non-zero if we are to only try to fill non-jump insns (such
2638 as calls). We do these first since we don't want jump insns (that are
2639 easier to fill) to get the only insns that could be used for non-jump insns.
2640 When it is zero, only try to fill JUMP_INSNs.
2642 When slots are filled in this manner, the insns (including the
2643 delay_insn) are put together in a SEQUENCE rtx. In this fashion,
2644 it is possible to tell whether a delay slot has really been filled
2645 or not. `final' knows how to deal with this, by communicating
2646 through FINAL_SEQUENCE. */
2649 fill_simple_delay_slots (first
, non_jumps_p
)
2653 register rtx insn
, pat
, trial
, next_trial
;
2655 int num_unfilled_slots
= unfilled_slots_next
- unfilled_slots_base
;
2656 struct resources needed
, set
;
2657 register int slots_to_fill
, slots_filled
;
2660 for (i
= 0; i
< num_unfilled_slots
; i
++)
2663 /* Get the next insn to fill. If it has already had any slots assigned,
2664 we can't do anything with it. Maybe we'll improve this later. */
2666 insn
= unfilled_slots_base
[i
];
2668 || INSN_DELETED_P (insn
)
2669 || (GET_CODE (insn
) == INSN
2670 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
2671 || (GET_CODE (insn
) == JUMP_INSN
&& non_jumps_p
)
2672 || (GET_CODE (insn
) != JUMP_INSN
&& ! non_jumps_p
))
2675 if (GET_CODE (insn
) == JUMP_INSN
)
2676 flags
= get_jump_flags (insn
, JUMP_LABEL (insn
));
2678 flags
= get_jump_flags (insn
, NULL_RTX
);
2679 slots_to_fill
= num_delay_slots (insn
);
2680 if (slots_to_fill
== 0)
2683 /* This insn needs, or can use, some delay slots. SLOTS_TO_FILL
2684 says how many. After initialization, first try optimizing
2687 nop add %o7,.-L1,%o7
2691 If this case applies, the delay slot of the call is filled with
2692 the unconditional jump. This is done first to avoid having the
2693 delay slot of the call filled in the backward scan. Also, since
2694 the unconditional jump is likely to also have a delay slot, that
2695 insn must exist when it is subsequently scanned.
2697 This is tried on each insn with delay slots as some machines
2698 have insns which perform calls, but are not represented as
2704 if ((trial
= next_active_insn (insn
))
2705 && GET_CODE (trial
) == JUMP_INSN
2706 && simplejump_p (trial
)
2707 && eligible_for_delay (insn
, slots_filled
, trial
, flags
)
2708 && no_labels_between_p (insn
, trial
))
2711 delay_list
= add_to_delay_list (trial
, delay_list
);
2712 /* Remove the unconditional jump from consideration for delay slot
2713 filling and unthread it. */
2714 if (unfilled_slots_base
[i
+ 1] == trial
)
2715 unfilled_slots_base
[i
+ 1] = 0;
2717 rtx next
= NEXT_INSN (trial
);
2718 rtx prev
= PREV_INSN (trial
);
2720 NEXT_INSN (prev
) = next
;
2722 PREV_INSN (next
) = prev
;
2726 /* Now, scan backwards from the insn to search for a potential
2727 delay-slot candidate. Stop searching when a label or jump is hit.
2729 For each candidate, if it is to go into the delay slot (moved
2730 forward in execution sequence), it must not need or set any resources
2731 that were set by later insns and must not set any resources that
2732 are needed for those insns.
2734 The delay slot insn itself sets resources unless it is a call
2735 (in which case the called routine, not the insn itself, is doing
2738 if (slots_filled
< slots_to_fill
)
2740 CLEAR_RESOURCE (&needed
);
2741 CLEAR_RESOURCE (&set
);
2742 mark_set_resources (insn
, &set
, 0, 0);
2743 mark_referenced_resources (insn
, &needed
, 0);
2745 for (trial
= prev_nonnote_insn (insn
); ! stop_search_p (trial
, 1);
2748 next_trial
= prev_nonnote_insn (trial
);
2750 /* This must be an INSN or CALL_INSN. */
2751 pat
= PATTERN (trial
);
2753 /* USE and CLOBBER at this level was just for flow; ignore it. */
2754 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
2757 /* Check for resource conflict first, to avoid unnecessary
2759 if (! insn_references_resource_p (trial
, &set
, 1)
2760 && ! insn_sets_resource_p (trial
, &set
, 1)
2761 && ! insn_sets_resource_p (trial
, &needed
, 1)
2763 /* Can't separate set of cc0 from its use. */
2764 && ! (reg_mentioned_p (cc0_rtx
, pat
)
2765 && ! sets_cc0_p (cc0_rtx
, pat
))
2769 trial
= try_split (pat
, trial
, 1);
2770 next_trial
= prev_nonnote_insn (trial
);
2771 if (eligible_for_delay (insn
, slots_filled
, trial
, flags
))
2773 /* In this case, we are searching backward, so if we
2774 find insns to put on the delay list, we want
2775 to put them at the head, rather than the
2776 tail, of the list. */
2778 update_reg_dead_notes (trial
, insn
);
2779 delay_list
= gen_rtx (INSN_LIST
, VOIDmode
,
2781 update_block (trial
, trial
);
2782 delete_insn (trial
);
2783 if (slots_to_fill
== ++slots_filled
)
2789 mark_set_resources (trial
, &set
, 0, 1);
2790 mark_referenced_resources (trial
, &needed
, 1);
2794 /* If all needed slots haven't been filled, we come here. */
2796 /* Try to optimize case of jumping around a single insn. */
2797 #if defined(ANNUL_IFFALSE_SLOTS) || defined(ANNUL_IFTRUE_SLOTS)
2798 if (slots_filled
!= slots_to_fill
2800 && GET_CODE (insn
) == JUMP_INSN
&& condjump_p (insn
))
2802 delay_list
= optimize_skip (insn
);
2808 /* Try to get insns from beyond the insn needing the delay slot.
2809 These insns can neither set or reference resources set in insns being
2810 skipped, cannot set resources in the insn being skipped, and, if this
2811 is a CALL_INSN (or a CALL_INSN is passed), cannot trap (because the
2812 call might not return).
2814 If this is a conditional jump, see if it merges back to us early
2815 enough for us to pick up insns from the merge point. Don't do
2816 this if there is another branch to our label unless we pass all of
2819 Another similar merge is if we jump to the same place that a
2820 later unconditional jump branches to. In that case, we don't
2821 care about the number of uses of our label. */
2823 if (slots_filled
!= slots_to_fill
2824 && (GET_CODE (insn
) != JUMP_INSN
2825 || (condjump_p (insn
) && ! simplejump_p (insn
)
2826 && JUMP_LABEL (insn
) != 0)))
2829 int maybe_never
= 0;
2830 int passed_label
= 0;
2832 struct resources needed_at_jump
;
2834 CLEAR_RESOURCE (&needed
);
2835 CLEAR_RESOURCE (&set
);
2837 if (GET_CODE (insn
) == CALL_INSN
)
2839 mark_set_resources (insn
, &set
, 0, 1);
2840 mark_referenced_resources (insn
, &needed
, 1);
2845 mark_set_resources (insn
, &set
, 0, 1);
2846 mark_referenced_resources (insn
, &needed
, 1);
2847 if (GET_CODE (insn
) == JUMP_INSN
)
2849 /* Get our target and show how many more uses we want to
2850 see before we hit the label. */
2851 target
= JUMP_LABEL (insn
);
2852 target_uses
= LABEL_NUSES (target
) - 1;
2857 for (trial
= next_nonnote_insn (insn
); trial
; trial
= next_trial
)
2859 rtx pat
, trial_delay
;
2861 next_trial
= next_nonnote_insn (trial
);
2863 if (GET_CODE (trial
) == CODE_LABEL
)
2867 /* If this is our target, see if we have seen all its uses.
2868 If so, indicate we have passed our target and ignore it.
2869 All other labels cause us to stop our search. */
2870 if (trial
== target
&& target_uses
== 0)
2878 else if (GET_CODE (trial
) == BARRIER
)
2881 /* We must have an INSN, JUMP_INSN, or CALL_INSN. */
2882 pat
= PATTERN (trial
);
2884 /* Stand-alone USE and CLOBBER are just for flow. */
2885 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
2888 /* If this already has filled delay slots, get the insn needing
2890 if (GET_CODE (pat
) == SEQUENCE
)
2891 trial_delay
= XVECEXP (pat
, 0, 0);
2893 trial_delay
= trial
;
2895 /* If this is a jump insn to our target, indicate that we have
2896 seen another jump to it. If we aren't handling a conditional
2897 jump, stop our search. Otherwise, compute the needs at its
2898 target and add them to NEEDED. */
2899 if (GET_CODE (trial_delay
) == JUMP_INSN
)
2903 else if (JUMP_LABEL (trial_delay
) == target
)
2907 mark_target_live_regs
2908 (next_active_insn (JUMP_LABEL (trial_delay
)),
2910 needed
.memory
|= needed_at_jump
.memory
;
2911 IOR_HARD_REG_SET (needed
.regs
, needed_at_jump
.regs
);
2915 /* See if we have a resource problem before we try to
2918 && GET_CODE (pat
) != SEQUENCE
2919 && ! insn_references_resource_p (trial
, &set
, 1)
2920 && ! insn_sets_resource_p (trial
, &set
, 1)
2921 && ! insn_sets_resource_p (trial
, &needed
, 1)
2923 && ! (reg_mentioned_p (cc0_rtx
, pat
) && ! sets_cc0_p (pat
))
2925 && ! (maybe_never
&& may_trap_p (pat
))
2926 && (trial
= try_split (pat
, trial
, 0))
2927 && eligible_for_delay (insn
, slots_filled
, trial
, flags
))
2929 next_trial
= next_nonnote_insn (trial
);
2930 delay_list
= add_to_delay_list (trial
, delay_list
);
2933 if (reg_mentioned_p (cc0_rtx
, pat
))
2934 link_cc0_insns (trial
);
2938 update_block (trial
, trial
);
2939 delete_insn (trial
);
2940 if (slots_to_fill
== ++slots_filled
)
2945 mark_set_resources (trial
, &set
, 0, 1);
2946 mark_referenced_resources (trial
, &needed
, 1);
2948 /* Ensure we don't put insns between the setting of cc and the
2949 comparison by moving a setting of cc into an earlier delay
2950 slot since these insns could clobber the condition code. */
2953 /* If this is a call or jump, we might not get here. */
2954 if (GET_CODE (trial
) == CALL_INSN
2955 || GET_CODE (trial
) == JUMP_INSN
)
2959 /* If there are slots left to fill and our search was stopped by an
2960 unconditional branch, try the insn at the branch target. We can
2961 redirect the branch if it works. */
2962 if (slots_to_fill
!= slots_filled
2964 && GET_CODE (trial
) == JUMP_INSN
2965 && simplejump_p (trial
)
2966 && (target
== 0 || JUMP_LABEL (trial
) == target
)
2967 && (next_trial
= next_active_insn (JUMP_LABEL (trial
))) != 0
2968 && ! (GET_CODE (next_trial
) == INSN
2969 && GET_CODE (PATTERN (next_trial
)) == SEQUENCE
)
2970 && ! insn_references_resource_p (next_trial
, &set
, 1)
2971 && ! insn_sets_resource_p (next_trial
, &set
, 1)
2972 && ! insn_sets_resource_p (next_trial
, &needed
, 1)
2974 && ! reg_mentioned_p (cc0_rtx
, PATTERN (next_trial
))
2976 && ! (maybe_never
&& may_trap_p (PATTERN (next_trial
)))
2977 && (next_trial
= try_split (PATTERN (next_trial
), next_trial
, 0))
2978 && eligible_for_delay (insn
, slots_filled
, next_trial
, flags
))
2980 rtx new_label
= next_active_insn (next_trial
);
2983 new_label
= get_label_before (new_label
);
2986 = add_to_delay_list (copy_rtx (next_trial
), delay_list
);
2988 reorg_redirect_jump (trial
, new_label
);
2990 /* If we merged because we both jumped to the same place,
2991 redirect the original insn also. */
2993 reorg_redirect_jump (insn
, new_label
);
2998 unfilled_slots_base
[i
]
2999 = emit_delay_sequence (insn
, delay_list
,
3000 slots_filled
, slots_to_fill
);
3002 if (slots_to_fill
== slots_filled
)
3003 unfilled_slots_base
[i
] = 0;
3005 note_delay_statistics (slots_filled
, 0);
3008 #ifdef DELAY_SLOTS_FOR_EPILOGUE
3009 /* See if the epilogue needs any delay slots. Try to fill them if so.
3010 The only thing we can do is scan backwards from the end of the
3011 function. If we did this in a previous pass, it is incorrect to do it
3013 if (current_function_epilogue_delay_list
)
3016 slots_to_fill
= DELAY_SLOTS_FOR_EPILOGUE
;
3017 if (slots_to_fill
== 0)
3021 CLEAR_RESOURCE (&needed
);
3022 CLEAR_RESOURCE (&set
);
3024 for (trial
= get_last_insn (); ! stop_search_p (trial
, 1);
3025 trial
= PREV_INSN (trial
))
3027 if (GET_CODE (trial
) == NOTE
)
3029 pat
= PATTERN (trial
);
3030 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
3033 if (! insn_references_resource_p (trial
, &set
, 1)
3034 && ! insn_sets_resource_p (trial
, &needed
, 1)
3036 /* Don't want to mess with cc0 here. */
3037 && ! reg_mentioned_p (cc0_rtx
, pat
)
3041 trial
= try_split (pat
, trial
, 1);
3042 if (ELIGIBLE_FOR_EPILOGUE_DELAY (trial
, slots_filled
))
3044 /* Here as well we are searching backward, so put the
3045 insns we find on the head of the list. */
3047 current_function_epilogue_delay_list
3048 = gen_rtx (INSN_LIST
, VOIDmode
, trial
,
3049 current_function_epilogue_delay_list
);
3050 mark_referenced_resources (trial
, &end_of_function_needs
, 1);
3051 update_block (trial
, trial
);
3052 delete_insn (trial
);
3054 /* Clear deleted bit so final.c will output the insn. */
3055 INSN_DELETED_P (trial
) = 0;
3057 if (slots_to_fill
== ++slots_filled
)
3063 mark_set_resources (trial
, &set
, 0, 1);
3064 mark_referenced_resources (trial
, &needed
, 1);
3067 note_delay_statistics (slots_filled
, 0);
3071 /* Try to find insns to place in delay slots.
3073 INSN is the jump needing SLOTS_TO_FILL delay slots. It tests CONDITION
3074 or is an unconditional branch if CONDITION is const_true_rtx.
3075 *PSLOTS_FILLED is updated with the number of slots that we have filled.
3077 THREAD is a flow-of-control, either the insns to be executed if the
3078 branch is true or if the branch is false, THREAD_IF_TRUE says which.
3080 OPPOSITE_THREAD is the thread in the opposite direction. It is used
3081 to see if any potential delay slot insns set things needed there.
3083 LIKELY is non-zero if it is extremely likely that the branch will be
3084 taken and THREAD_IF_TRUE is set. This is used for the branch at the
3085 end of a loop back up to the top.
3087 OWN_THREAD and OWN_OPPOSITE_THREAD are true if we are the only user of the
3088 thread. I.e., it is the fallthrough code of our jump or the target of the
3089 jump when we are the only jump going there.
3091 If OWN_THREAD is false, it must be the "true" thread of a jump. In that
3092 case, we can only take insns from the head of the thread for our delay
3093 slot. We then adjust the jump to point after the insns we have taken. */
3096 fill_slots_from_thread (insn
, condition
, thread
, opposite_thread
, likely
,
3097 thread_if_true
, own_thread
, own_opposite_thread
,
3098 slots_to_fill
, pslots_filled
)
3101 rtx thread
, opposite_thread
;
3104 int own_thread
, own_opposite_thread
;
3105 int slots_to_fill
, *pslots_filled
;
3109 struct resources opposite_needed
, set
, needed
;
3115 /* Validate our arguments. */
3116 if ((condition
== const_true_rtx
&& ! thread_if_true
)
3117 || (! own_thread
&& ! thread_if_true
))
3120 flags
= get_jump_flags (insn
, JUMP_LABEL (insn
));
3122 /* If our thread is the end of subroutine, we can't get any delay
3127 /* If this is an unconditional branch, nothing is needed at the
3128 opposite thread. Otherwise, compute what is needed there. */
3129 if (condition
== const_true_rtx
)
3130 CLEAR_RESOURCE (&opposite_needed
);
3132 mark_target_live_regs (opposite_thread
, &opposite_needed
);
3134 /* If the insn at THREAD can be split, do it here to avoid having to
3135 update THREAD and NEW_THREAD if it is done in the loop below. Also
3136 initialize NEW_THREAD. */
3138 new_thread
= thread
= try_split (PATTERN (thread
), thread
, 0);
3140 /* Scan insns at THREAD. We are looking for an insn that can be removed
3141 from THREAD (it neither sets nor references resources that were set
3142 ahead of it and it doesn't set anything needs by the insns ahead of
3143 it) and that either can be placed in an annulling insn or aren't
3144 needed at OPPOSITE_THREAD. */
3146 CLEAR_RESOURCE (&needed
);
3147 CLEAR_RESOURCE (&set
);
3149 /* If we do not own this thread, we must stop as soon as we find
3150 something that we can't put in a delay slot, since all we can do
3151 is branch into THREAD at a later point. Therefore, labels stop
3152 the search if this is not the `true' thread. */
3154 for (trial
= thread
;
3155 ! stop_search_p (trial
, ! thread_if_true
) && (! lose
|| own_thread
);
3156 trial
= next_nonnote_insn (trial
))
3160 /* If we have passed a label, we no longer own this thread. */
3161 if (GET_CODE (trial
) == CODE_LABEL
)
3167 pat
= PATTERN (trial
);
3168 if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
3171 /* If TRIAL conflicts with the insns ahead of it, we lose. Also,
3172 don't separate or copy insns that set and use CC0. */
3173 if (! insn_references_resource_p (trial
, &set
, 1)
3174 && ! insn_sets_resource_p (trial
, &set
, 1)
3175 && ! insn_sets_resource_p (trial
, &needed
, 1)
3177 && ! (reg_mentioned_p (cc0_rtx
, pat
)
3178 && (! own_thread
|| ! sets_cc0_p (pat
)))
3182 /* If TRIAL is redundant with some insn before INSN, we don't
3183 actually need to add it to the delay list; we can merely pretend
3185 if (redundant_insn_p (trial
, insn
, delay_list
))
3189 update_block (trial
, thread
);
3190 delete_insn (trial
);
3193 new_thread
= next_active_insn (trial
);
3198 /* There are two ways we can win: If TRIAL doesn't set anything
3199 needed at the opposite thread and can't trap, or if it can
3200 go into an annulled delay slot. */
3201 if (condition
== const_true_rtx
3202 || (! insn_sets_resource_p (trial
, &opposite_needed
, 1)
3203 && ! may_trap_p (pat
)))
3206 trial
= try_split (pat
, trial
, 0);
3207 if (new_thread
== old_trial
)
3209 pat
= PATTERN (trial
);
3210 if (eligible_for_delay (insn
, *pslots_filled
, trial
, flags
))
3214 #ifdef ANNUL_IFTRUE_SLOTS
3217 #ifdef ANNUL_IFFALSE_SLOTS
3223 trial
= try_split (pat
, trial
, 0);
3224 if (new_thread
== old_trial
)
3226 pat
= PATTERN (trial
);
3228 ? eligible_for_annul_false (insn
, *pslots_filled
, trial
, flags
)
3229 : eligible_for_annul_true (insn
, *pslots_filled
, trial
, flags
)))
3237 if (reg_mentioned_p (cc0_rtx
, pat
))
3238 link_cc0_insns (trial
);
3241 /* If we own this thread, delete the insn. If this is the
3242 destination of a branch, show that a basic block status
3243 may have been updated. In any case, mark the new
3244 starting point of this thread. */
3247 update_block (trial
, thread
);
3248 delete_insn (trial
);
3251 new_thread
= next_active_insn (trial
);
3253 temp
= own_thread
? trial
: copy_rtx (trial
);
3255 INSN_FROM_TARGET_P (temp
) = 1;
3257 delay_list
= add_to_delay_list (temp
, delay_list
);
3259 if (slots_to_fill
== ++(*pslots_filled
))
3261 /* Even though we have filled all the slots, we
3262 may be branching to a location that has a
3263 redundant insn. Skip any if so. */
3264 while (new_thread
&& ! own_thread
3265 && ! insn_sets_resource_p (new_thread
, &set
, 1)
3266 && ! insn_sets_resource_p (new_thread
, &needed
, 1)
3267 && ! insn_references_resource_p (new_thread
,
3269 && redundant_insn_p (new_thread
, insn
,
3271 new_thread
= next_active_insn (new_thread
);
3280 /* This insn can't go into a delay slot. */
3282 mark_set_resources (trial
, &set
, 0, 1);
3283 mark_referenced_resources (trial
, &needed
, 1);
3285 /* Ensure we don't put insns between the setting of cc and the comparison
3286 by moving a setting of cc into an earlier delay slot since these insns
3287 could clobber the condition code. */
3290 /* If this insn is a register-register copy and the next insn has
3291 a use of our destination, change it to use our source. That way,
3292 it will become a candidate for our delay slot the next time
3293 through this loop. This case occurs commonly in loops that
3296 We could check for more complex cases than those tested below,
3297 but it doesn't seem worth it. It might also be a good idea to try
3298 to swap the two insns. That might do better.
3300 We can't do this if the next insn modifies our destination, because
3301 that would make the replacement into the insn invalid. We also can't
3302 do this if it modifies our source, because it might be an earlyclobber
3303 operand. This latter test also prevents updating the contents of
3306 if (GET_CODE (trial
) == INSN
&& GET_CODE (pat
) == SET
3307 && GET_CODE (SET_SRC (pat
)) == REG
3308 && GET_CODE (SET_DEST (pat
)) == REG
)
3310 rtx next
= next_nonnote_insn (trial
);
3312 if (next
&& GET_CODE (next
) == INSN
3313 && GET_CODE (PATTERN (next
)) != USE
3314 && ! reg_set_p (SET_DEST (pat
), next
)
3315 && ! reg_set_p (SET_SRC (pat
), next
)
3316 && reg_referenced_p (SET_DEST (pat
), PATTERN (next
)))
3317 validate_replace_rtx (SET_DEST (pat
), SET_SRC (pat
), next
);
3321 /* If we stopped on a branch insn that has delay slots, see if we can
3322 steal some of the insns in those slots. */
3323 if (trial
&& GET_CODE (trial
) == INSN
3324 && GET_CODE (PATTERN (trial
)) == SEQUENCE
3325 && GET_CODE (XVECEXP (PATTERN (trial
), 0, 0)) == JUMP_INSN
)
3327 /* If this is the `true' thread, we will want to follow the jump,
3328 so we can only do this if we have taken everything up to here. */
3329 if (thread_if_true
&& trial
== new_thread
)
3331 = steal_delay_list_from_target (insn
, condition
, PATTERN (trial
),
3332 delay_list
, &set
, &needed
,
3333 &opposite_needed
, slots_to_fill
,
3334 pslots_filled
, &must_annul
,
3336 else if (! thread_if_true
)
3338 = steal_delay_list_from_fallthrough (insn
, condition
,
3340 delay_list
, &set
, &needed
,
3341 &opposite_needed
, slots_to_fill
,
3342 pslots_filled
, &must_annul
);
3345 /* If we haven't found anything for this delay slot and it is very
3346 likely that the branch will be taken, see if the insn at our target
3347 increments or decrements a register with an increment that does not
3348 depend on the destination register. If so, try to place the opposite
3349 arithmetic insn after the jump insn and put the arithmetic insn in the
3350 delay slot. If we can't do this, return. */
3351 if (delay_list
== 0 && likely
&& new_thread
&& GET_CODE (new_thread
) == INSN
)
3353 rtx pat
= PATTERN (new_thread
);
3358 pat
= PATTERN (trial
);
3360 if (GET_CODE (trial
) != INSN
|| GET_CODE (pat
) != SET
3361 || ! eligible_for_delay (insn
, 0, trial
, flags
))
3364 dest
= SET_DEST (pat
), src
= SET_SRC (pat
);
3365 if ((GET_CODE (src
) == PLUS
|| GET_CODE (src
) == MINUS
)
3366 && rtx_equal_p (XEXP (src
, 0), dest
)
3367 && ! reg_overlap_mentioned_p (dest
, XEXP (src
, 1)))
3369 rtx other
= XEXP (src
, 1);
3373 /* If this is a constant adjustment, use the same code with
3374 the negated constant. Otherwise, reverse the sense of the
3376 if (GET_CODE (other
) == CONST_INT
)
3377 new_arith
= gen_rtx (GET_CODE (src
), GET_MODE (src
), dest
,
3378 negate_rtx (GET_MODE (src
), other
));
3380 new_arith
= gen_rtx (GET_CODE (src
) == PLUS
? MINUS
: PLUS
,
3381 GET_MODE (src
), dest
, other
);
3383 ninsn
= emit_insn_after (gen_rtx (SET
, VOIDmode
, dest
, new_arith
),
3386 if (recog_memoized (ninsn
) < 0
3387 || (insn_extract (ninsn
),
3388 ! constrain_operands (INSN_CODE (ninsn
), 1)))
3390 delete_insn (ninsn
);
3396 update_block (trial
, thread
);
3397 delete_insn (trial
);
3400 new_thread
= next_active_insn (trial
);
3402 ninsn
= own_thread
? trial
: copy_rtx (trial
);
3404 INSN_FROM_TARGET_P (ninsn
) = 1;
3406 delay_list
= add_to_delay_list (ninsn
, NULL_RTX
);
3411 if (delay_list
&& must_annul
)
3412 INSN_ANNULLED_BRANCH_P (insn
) = 1;
3414 /* If we are to branch into the middle of this thread, find an appropriate
3415 label or make a new one if none, and redirect INSN to it. If we hit the
3416 end of the function, use the end-of-function label. */
3417 if (new_thread
!= thread
)
3421 if (! thread_if_true
)
3424 if (new_thread
&& GET_CODE (new_thread
) == JUMP_INSN
3425 && (simplejump_p (new_thread
)
3426 || GET_CODE (PATTERN (new_thread
)) == RETURN
))
3427 new_thread
= follow_jumps (JUMP_LABEL (new_thread
));
3429 if (new_thread
== 0)
3430 label
= find_end_label ();
3431 else if (GET_CODE (new_thread
) == CODE_LABEL
)
3434 label
= get_label_before (new_thread
);
3436 reorg_redirect_jump (insn
, label
);
3442 /* Make another attempt to find insns to place in delay slots.
3444 We previously looked for insns located in front of the delay insn
3445 and, for non-jump delay insns, located behind the delay insn.
3447 Here only try to schedule jump insns and try to move insns from either
3448 the target or the following insns into the delay slot. If annulling is
3449 supported, we will be likely to do this. Otherwise, we can do this only
3453 fill_eager_delay_slots (first
)
3458 int num_unfilled_slots
= unfilled_slots_next
- unfilled_slots_base
;
3460 for (i
= 0; i
< num_unfilled_slots
; i
++)
3463 rtx target_label
, insn_at_target
, fallthrough_insn
;
3466 int own_fallthrough
;
3467 int prediction
, slots_to_fill
, slots_filled
;
3469 insn
= unfilled_slots_base
[i
];
3471 || INSN_DELETED_P (insn
)
3472 || GET_CODE (insn
) != JUMP_INSN
3473 || ! condjump_p (insn
))
3476 slots_to_fill
= num_delay_slots (insn
);
3477 if (slots_to_fill
== 0)
3481 target_label
= JUMP_LABEL (insn
);
3482 condition
= get_branch_condition (insn
, target_label
);
3487 /* Get the next active fallthough and target insns and see if we own
3488 them. Then see whether the branch is likely true. We don't need
3489 to do a lot of this for unconditional branches. */
3491 insn_at_target
= next_active_insn (target_label
);
3492 own_target
= own_thread_p (target_label
, target_label
, 0);
3494 if (condition
== const_true_rtx
)
3496 own_fallthrough
= 0;
3497 fallthrough_insn
= 0;
3502 fallthrough_insn
= next_active_insn (insn
);
3503 own_fallthrough
= own_thread_p (NEXT_INSN (insn
), NULL_RTX
, 1);
3504 prediction
= mostly_true_jump (insn
, condition
);
3507 /* If this insn is expected to branch, first try to get insns from our
3508 target, then our fallthrough insns. If it is not, expected to branch,
3509 try the other order. */
3514 = fill_slots_from_thread (insn
, condition
, insn_at_target
,
3515 fallthrough_insn
, prediction
== 2, 1,
3516 own_target
, own_fallthrough
,
3517 slots_to_fill
, &slots_filled
);
3519 if (delay_list
== 0 && own_fallthrough
)
3521 /* Even though we didn't find anything for delay slots,
3522 we might have found a redundant insn which we deleted
3523 from the thread that was filled. So we have to recompute
3524 the next insn at the target. */
3525 target_label
= JUMP_LABEL (insn
);
3526 insn_at_target
= next_active_insn (target_label
);
3529 = fill_slots_from_thread (insn
, condition
, fallthrough_insn
,
3530 insn_at_target
, 0, 0,
3531 own_fallthrough
, own_target
,
3532 slots_to_fill
, &slots_filled
);
3537 if (own_fallthrough
)
3539 = fill_slots_from_thread (insn
, condition
, fallthrough_insn
,
3540 insn_at_target
, 0, 0,
3541 own_fallthrough
, own_target
,
3542 slots_to_fill
, &slots_filled
);
3544 if (delay_list
== 0)
3546 = fill_slots_from_thread (insn
, condition
, insn_at_target
,
3547 next_active_insn (insn
), 0, 1,
3548 own_target
, own_fallthrough
,
3549 slots_to_fill
, &slots_filled
);
3553 unfilled_slots_base
[i
]
3554 = emit_delay_sequence (insn
, delay_list
,
3555 slots_filled
, slots_to_fill
);
3557 if (slots_to_fill
== slots_filled
)
3558 unfilled_slots_base
[i
] = 0;
3560 note_delay_statistics (slots_filled
, 1);
3564 /* Once we have tried two ways to fill a delay slot, make a pass over the
3565 code to try to improve the results and to do such things as more jump
3569 relax_delay_slots (first
)
3572 register rtx insn
, next
, pat
;
3573 register rtx trial
, delay_insn
, target_label
;
3575 /* Look at every JUMP_INSN and see if we can improve it. */
3576 for (insn
= first
; insn
; insn
= next
)
3580 next
= next_active_insn (insn
);
3582 /* If this is a jump insn, see if it now jumps to a jump, jumps to
3583 the next insn, or jumps to a label that is not the last of a
3584 group of consecutive labels. */
3585 if (GET_CODE (insn
) == JUMP_INSN
3586 && condjump_p (insn
)
3587 && (target_label
= JUMP_LABEL (insn
)) != 0)
3589 target_label
= follow_jumps (target_label
);
3590 target_label
= prev_label (next_active_insn (target_label
));
3592 if (target_label
== 0)
3593 target_label
= find_end_label ();
3595 if (next_active_insn (target_label
) == next
)
3601 if (target_label
!= JUMP_LABEL (insn
))
3602 reorg_redirect_jump (insn
, target_label
);
3604 /* See if this jump branches around a unconditional jump.
3605 If so, invert this jump and point it to the target of the
3607 if (next
&& GET_CODE (next
) == JUMP_INSN
3608 && (simplejump_p (next
) || GET_CODE (PATTERN (next
)) == RETURN
)
3609 && next_active_insn (target_label
) == next_active_insn (next
)
3610 && no_labels_between_p (insn
, next
))
3612 rtx label
= JUMP_LABEL (next
);
3614 /* Be careful how we do this to avoid deleting code or
3615 labels that are momentarily dead. See similar optimization
3618 We also need to ensure we properly handle the case when
3619 invert_jump fails. */
3621 ++LABEL_NUSES (target_label
);
3623 ++LABEL_NUSES (label
);
3625 if (invert_jump (insn
, label
))
3632 --LABEL_NUSES (label
);
3634 if (--LABEL_NUSES (target_label
) == 0)
3635 delete_insn (target_label
);
3641 /* If this is an unconditional jump and the previous insn is a
3642 conditional jump, try reversing the condition of the previous
3643 insn and swapping our targets. The next pass might be able to
3646 Don't do this if we expect the conditional branch to be true, because
3647 we would then be making the more common case longer. */
3649 if (GET_CODE (insn
) == JUMP_INSN
3650 && (simplejump_p (insn
) || GET_CODE (PATTERN (insn
)) == RETURN
)
3651 && (other
= prev_active_insn (insn
)) != 0
3652 && condjump_p (other
)
3653 && no_labels_between_p (other
, insn
)
3654 && 0 < mostly_true_jump (other
,
3655 get_branch_condition (other
,
3656 JUMP_LABEL (other
))))
3658 rtx other_target
= JUMP_LABEL (other
);
3659 target_label
= JUMP_LABEL (insn
);
3661 /* Increment the count of OTHER_TARGET, so it doesn't get deleted
3662 as we move the label. */
3664 ++LABEL_NUSES (other_target
);
3666 if (invert_jump (other
, target_label
))
3667 reorg_redirect_jump (insn
, other_target
);
3670 --LABEL_NUSES (other_target
);
3673 /* Now look only at cases where we have filled a delay slot. */
3674 if (GET_CODE (insn
) != INSN
3675 || GET_CODE (PATTERN (insn
)) != SEQUENCE
)
3678 pat
= PATTERN (insn
);
3679 delay_insn
= XVECEXP (pat
, 0, 0);
3681 /* See if the first insn in the delay slot is redundant with some
3682 previous insn. Remove it from the delay slot if so; then set up
3683 to reprocess this insn. */
3684 if (redundant_insn_p (XVECEXP (pat
, 0, 1), delay_insn
, 0))
3686 delete_from_delay_slot (XVECEXP (pat
, 0, 1));
3687 next
= prev_active_insn (next
);
3691 /* Now look only at the cases where we have a filled JUMP_INSN. */
3692 if (GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) != JUMP_INSN
3693 || ! condjump_p (XVECEXP (PATTERN (insn
), 0, 0)))
3696 target_label
= JUMP_LABEL (delay_insn
);
3700 /* If this jump goes to another unconditional jump, thread it, but
3701 don't convert a jump into a RETURN here. */
3702 trial
= follow_jumps (target_label
);
3703 trial
= prev_label (next_active_insn (trial
));
3704 if (trial
== 0 && target_label
!= 0)
3705 trial
= find_end_label ();
3707 if (trial
!= target_label
3708 && redirect_with_delay_slots_safe_p (delay_insn
, trial
, insn
))
3710 reorg_redirect_jump (delay_insn
, trial
);
3711 target_label
= trial
;
3714 /* If the first insn at TARGET_LABEL is redundant with a previous
3715 insn, redirect the jump to the following insn process again. */
3716 trial
= next_active_insn (target_label
);
3717 if (trial
&& GET_CODE (PATTERN (trial
)) != SEQUENCE
3718 && redundant_insn_p (trial
, insn
, 0))
3720 trial
= next_active_insn (trial
);
3722 target_label
= find_end_label ();
3724 target_label
= get_label_before (trial
);
3725 reorg_redirect_jump (delay_insn
, target_label
);
3730 /* Similarly, if it is an unconditional jump with one insn in its
3731 delay list and that insn is redundant, thread the jump. */
3732 if (trial
&& GET_CODE (PATTERN (trial
)) == SEQUENCE
3733 && XVECLEN (PATTERN (trial
), 0) == 2
3734 && GET_CODE (XVECEXP (PATTERN (trial
), 0, 0)) == JUMP_INSN
3735 && (simplejump_p (XVECEXP (PATTERN (trial
), 0, 0))
3736 || GET_CODE (PATTERN (XVECEXP (PATTERN (trial
), 0, 0))) == RETURN
)
3737 && redundant_insn_p (XVECEXP (PATTERN (trial
), 0, 1), insn
, 0))
3739 target_label
= JUMP_LABEL (XVECEXP (PATTERN (trial
), 0, 0));
3740 if (target_label
== 0)
3741 target_label
= find_end_label ();
3743 if (redirect_with_delay_slots_safe_p (delay_insn
, target_label
,
3746 reorg_redirect_jump (delay_insn
, target_label
);
3753 if (! INSN_ANNULLED_BRANCH_P (delay_insn
)
3754 && prev_active_insn (target_label
) == insn
3756 /* If the last insn in the delay slot sets CC0 for some insn,
3757 various code assumes that it is in a delay slot. We could
3758 put it back where it belonged and delete the register notes,
3759 but it doesn't seem worthwhile in this uncommon case. */
3760 && ! find_reg_note (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1),
3761 REG_CC_USER
, NULL_RTX
)
3767 /* All this insn does is execute its delay list and jump to the
3768 following insn. So delete the jump and just execute the delay
3771 We do this by deleting the INSN containing the SEQUENCE, then
3772 re-emitting the insns separately, and then deleting the jump.
3773 This allows the count of the jump target to be properly
3776 /* Clear the from target bit, since these insns are no longer
3778 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
3779 INSN_FROM_TARGET_P (XVECEXP (pat
, 0, i
)) = 0;
3781 trial
= PREV_INSN (insn
);
3783 emit_insn_after (pat
, trial
);
3784 delete_scheduled_jump (delay_insn
);
3788 /* See if this is an unconditional jump around a single insn which is
3789 identical to the one in its delay slot. In this case, we can just
3790 delete the branch and the insn in its delay slot. */
3791 if (next
&& GET_CODE (next
) == INSN
3792 && prev_label (next_active_insn (next
)) == target_label
3793 && simplejump_p (insn
)
3794 && XVECLEN (pat
, 0) == 2
3795 && rtx_equal_p (PATTERN (next
), PATTERN (XVECEXP (pat
, 0, 1))))
3801 /* See if this jump (with its delay slots) branches around another
3802 jump (without delay slots). If so, invert this jump and point
3803 it to the target of the second jump. We cannot do this for
3804 annulled jumps, though. Again, don't convert a jump to a RETURN
3806 if (! INSN_ANNULLED_BRANCH_P (delay_insn
)
3807 && next
&& GET_CODE (next
) == JUMP_INSN
3808 && (simplejump_p (next
) || GET_CODE (PATTERN (next
)) == RETURN
)
3809 && next_active_insn (target_label
) == next_active_insn (next
)
3810 && no_labels_between_p (insn
, next
))
3812 rtx label
= JUMP_LABEL (next
);
3813 rtx old_label
= JUMP_LABEL (delay_insn
);
3816 label
= find_end_label ();
3818 if (redirect_with_delay_slots_safe_p (delay_insn
, label
, insn
))
3820 /* Be careful how we do this to avoid deleting code or labels
3821 that are momentarily dead. See similar optimization in
3824 ++LABEL_NUSES (old_label
);
3826 if (invert_jump (delay_insn
, label
))
3832 if (old_label
&& --LABEL_NUSES (old_label
) == 0)
3833 delete_insn (old_label
);
3838 /* If we own the thread opposite the way this insn branches, see if we
3839 can merge its delay slots with following insns. */
3840 if (INSN_FROM_TARGET_P (XVECEXP (pat
, 0, 1))
3841 && own_thread_p (NEXT_INSN (insn
), 0, 1))
3842 try_merge_delay_insns (insn
, next
);
3843 else if (! INSN_FROM_TARGET_P (XVECEXP (pat
, 0, 1))
3844 && own_thread_p (target_label
, target_label
, 0))
3845 try_merge_delay_insns (insn
, next_active_insn (target_label
));
3847 /* If we get here, we haven't deleted INSN. But we may have deleted
3848 NEXT, so recompute it. */
3849 next
= next_active_insn (insn
);
3855 /* Look for filled jumps to the end of function label. We can try to convert
3856 them into RETURN insns if the insns in the delay slot are valid for the
3860 make_return_insns (first
)
3863 rtx insn
, jump_insn
, pat
;
3864 rtx real_return_label
= end_of_function_label
;
3867 /* See if there is a RETURN insn in the function other than the one we
3868 made for END_OF_FUNCTION_LABEL. If so, set up anything we can't change
3869 into a RETURN to jump to it. */
3870 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3871 if (GET_CODE (insn
) == JUMP_INSN
&& GET_CODE (PATTERN (insn
)) == RETURN
)
3873 real_return_label
= get_label_before (insn
);
3877 /* Show an extra usage of REAL_RETURN_LABEL so it won't go away if it
3878 was equal to END_OF_FUNCTION_LABEL. */
3879 LABEL_NUSES (real_return_label
)++;
3881 /* Clear the list of insns to fill so we can use it. */
3882 obstack_free (&unfilled_slots_obstack
, unfilled_firstobj
);
3884 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3888 /* Only look at filled JUMP_INSNs that go to the end of function
3890 if (GET_CODE (insn
) != INSN
3891 || GET_CODE (PATTERN (insn
)) != SEQUENCE
3892 || GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) != JUMP_INSN
3893 || JUMP_LABEL (XVECEXP (PATTERN (insn
), 0, 0)) != end_of_function_label
)
3896 pat
= PATTERN (insn
);
3897 jump_insn
= XVECEXP (pat
, 0, 0);
3899 /* If we can't make the jump into a RETURN, redirect it to the best
3900 RETURN and go on to the next insn. */
3901 if (! reorg_redirect_jump (jump_insn
, NULL_RTX
))
3903 reorg_redirect_jump (jump_insn
, real_return_label
);
3907 /* See if this RETURN can accept the insns current in its delay slot.
3908 It can if it has more or an equal number of slots and the contents
3909 of each is valid. */
3911 flags
= get_jump_flags (jump_insn
, JUMP_LABEL (jump_insn
));
3912 slots
= num_delay_slots (jump_insn
);
3913 if (slots
>= XVECLEN (pat
, 0) - 1)
3915 for (i
= 1; i
< XVECLEN (pat
, 0); i
++)
3917 #ifdef ANNUL_IFFALSE_SLOTS
3918 (INSN_ANNULLED_BRANCH_P (jump_insn
)
3919 && INSN_FROM_TARGET_P (XVECEXP (pat
, 0, i
)))
3920 ? eligible_for_annul_false (jump_insn
, i
- 1,
3921 XVECEXP (pat
, 0, i
), flags
) :
3923 #ifdef ANNUL_IFTRUE_SLOTS
3924 (INSN_ANNULLED_BRANCH_P (jump_insn
)
3925 && ! INSN_FROM_TARGET_P (XVECEXP (pat
, 0, i
)))
3926 ? eligible_for_annul_true (jump_insn
, i
- 1,
3927 XVECEXP (pat
, 0, i
), flags
) :
3929 eligible_for_delay (jump_insn
, i
-1, XVECEXP (pat
, 0, i
), flags
)))
3935 if (i
== XVECLEN (pat
, 0))
3938 /* We have to do something with this insn. If it is an unconditional
3939 RETURN, delete the SEQUENCE and output the individual insns,
3940 followed by the RETURN. Then set things up so we try to find
3941 insns for its delay slots, if it needs some. */
3942 if (GET_CODE (PATTERN (jump_insn
)) == RETURN
)
3944 rtx prev
= PREV_INSN (insn
);
3947 for (i
= 1; i
< XVECLEN (pat
, 0); i
++)
3948 prev
= emit_insn_after (PATTERN (XVECEXP (pat
, 0, i
)), prev
);
3950 insn
= emit_jump_insn_after (PATTERN (jump_insn
), prev
);
3951 emit_barrier_after (insn
);
3954 obstack_ptr_grow (&unfilled_slots_obstack
, insn
);
3957 /* It is probably more efficient to keep this with its current
3958 delay slot as a branch to a RETURN. */
3959 reorg_redirect_jump (jump_insn
, real_return_label
);
3962 /* Now delete REAL_RETURN_LABEL if we never used it. Then try to fill any
3963 new delay slots we have created. */
3964 if (--LABEL_NUSES (real_return_label
) == 0)
3965 delete_insn (real_return_label
);
3967 fill_simple_delay_slots (first
, 1);
3968 fill_simple_delay_slots (first
, 0);
3972 /* Try to find insns to place in delay slots. */
3975 dbr_schedule (first
, file
)
3979 rtx insn
, next
, epilogue_insn
= 0;
3982 int old_flag_no_peephole
= flag_no_peephole
;
3984 /* Execute `final' once in prescan mode to delete any insns that won't be
3985 used. Don't let final try to do any peephole optimization--it will
3986 ruin dataflow information for this pass. */
3988 flag_no_peephole
= 1;
3989 final (first
, 0, NO_DEBUG
, 1, 1);
3990 flag_no_peephole
= old_flag_no_peephole
;
3993 /* If the current function has no insns other than the prologue and
3994 epilogue, then do not try to fill any delay slots. */
3995 if (n_basic_blocks
== 0)
3998 /* Find the highest INSN_UID and allocate and initialize our map from
3999 INSN_UID's to position in code. */
4000 for (max_uid
= 0, insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4002 if (INSN_UID (insn
) > max_uid
)
4003 max_uid
= INSN_UID (insn
);
4004 if (GET_CODE (insn
) == NOTE
4005 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_EPILOGUE_BEG
)
4006 epilogue_insn
= insn
;
4009 uid_to_ruid
= (int *) alloca ((max_uid
+ 1) * sizeof (int *));
4010 for (i
= 0, insn
= first
; insn
; i
++, insn
= NEXT_INSN (insn
))
4011 uid_to_ruid
[INSN_UID (insn
)] = i
;
4013 /* Initialize the list of insns that need filling. */
4014 if (unfilled_firstobj
== 0)
4016 gcc_obstack_init (&unfilled_slots_obstack
);
4017 unfilled_firstobj
= (rtx
*) obstack_alloc (&unfilled_slots_obstack
, 0);
4020 for (insn
= next_active_insn (first
); insn
; insn
= next_active_insn (insn
))
4024 INSN_ANNULLED_BRANCH_P (insn
) = 0;
4025 INSN_FROM_TARGET_P (insn
) = 0;
4027 /* Skip vector tables. We can't get attributes for them. */
4028 if (GET_CODE (insn
) == JUMP_INSN
4029 && (GET_CODE (PATTERN (insn
)) == ADDR_VEC
4030 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
))
4033 if (num_delay_slots (insn
) > 0)
4034 obstack_ptr_grow (&unfilled_slots_obstack
, insn
);
4036 /* Ensure all jumps go to the last of a set of consecutive labels. */
4037 if (GET_CODE (insn
) == JUMP_INSN
&& condjump_p (insn
)
4038 && JUMP_LABEL (insn
) != 0
4039 && ((target
= prev_label (next_active_insn (JUMP_LABEL (insn
))))
4040 != JUMP_LABEL (insn
)))
4041 redirect_jump (insn
, target
);
4044 /* Indicate what resources are required to be valid at the end of the current
4045 function. The condition code never is and memory always is. If the
4046 frame pointer is needed, it is and so is the stack pointer unless
4047 EXIT_IGNORE_STACK is non-zero. If the frame pointer is not needed, the
4048 stack pointer is. Registers used to return the function value are
4049 needed. Registers holding global variables are needed. */
4051 end_of_function_needs
.cc
= 0;
4052 end_of_function_needs
.memory
= 1;
4053 CLEAR_HARD_REG_SET (end_of_function_needs
.regs
);
4055 if (frame_pointer_needed
)
4057 SET_HARD_REG_BIT (end_of_function_needs
.regs
, FRAME_POINTER_REGNUM
);
4058 #ifdef EXIT_IGNORE_STACK
4059 if (! EXIT_IGNORE_STACK
)
4061 SET_HARD_REG_BIT (end_of_function_needs
.regs
, STACK_POINTER_REGNUM
);
4064 SET_HARD_REG_BIT (end_of_function_needs
.regs
, STACK_POINTER_REGNUM
);
4066 if (current_function_return_rtx
!= 0
4067 && GET_CODE (current_function_return_rtx
) == REG
)
4068 mark_referenced_resources (current_function_return_rtx
,
4069 &end_of_function_needs
, 1);
4071 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4073 SET_HARD_REG_BIT (end_of_function_needs
.regs
, i
);
4075 /* The registers required to be live at the end of the function are
4076 represented in the flow information as being dead just prior to
4077 reaching the end of the function. For example, the return of a value
4078 might be represented by a USE of the return register immediately
4079 followed by an unconditional jump to the return label where the
4080 return label is the end of the RTL chain. The end of the RTL chain
4081 is then taken to mean that the return register is live.
4083 This sequence is no longer maintained when epilogue instructions are
4084 added to the RTL chain. To reconstruct the original meaning, the
4085 start of the epilogue (NOTE_INSN_EPILOGUE_BEG) is regarded as the
4086 point where these registers become live (start_of_epilogue_needs).
4087 If epilogue instructions are present, the registers set by those
4088 instructions won't have been processed by flow. Thus, those
4089 registers are additionally required at the end of the RTL chain
4090 (end_of_function_needs). */
4092 start_of_epilogue_needs
= end_of_function_needs
;
4094 while (epilogue_insn
= next_nonnote_insn (epilogue_insn
))
4095 mark_set_resources (epilogue_insn
, &end_of_function_needs
, 0, 1);
4097 /* Show we haven't computed an end-of-function label yet. */
4098 end_of_function_label
= 0;
4100 /* Allocate and initialize the tables used by mark_target_live_regs. */
4102 = (struct target_info
**) alloca ((TARGET_HASH_PRIME
4103 * sizeof (struct target_info
*)));
4104 bzero (target_hash_table
, TARGET_HASH_PRIME
* sizeof (struct target_info
*));
4106 bb_ticks
= (int *) alloca (n_basic_blocks
* sizeof (int));
4107 bzero (bb_ticks
, n_basic_blocks
* sizeof (int));
4109 /* Initialize the statistics for this function. */
4110 bzero (num_insns_needing_delays
, sizeof num_insns_needing_delays
);
4111 bzero (num_filled_delays
, sizeof num_filled_delays
);
4113 /* Now do the delay slot filling. Try everything twice in case earlier
4114 changes make more slots fillable. */
4116 for (reorg_pass_number
= 0;
4117 reorg_pass_number
< MAX_REORG_PASSES
;
4118 reorg_pass_number
++)
4120 fill_simple_delay_slots (first
, 1);
4121 fill_simple_delay_slots (first
, 0);
4122 fill_eager_delay_slots (first
);
4123 relax_delay_slots (first
);
4126 /* Delete any USE insns made by update_block; subsequent passes don't need
4127 them or know how to deal with them. */
4128 for (insn
= first
; insn
; insn
= next
)
4130 next
= NEXT_INSN (insn
);
4132 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
4133 && GET_RTX_CLASS (GET_CODE (XEXP (PATTERN (insn
), 0))) == 'i')
4134 next
= delete_insn (insn
);
4137 /* If we made an end of function label, indicate that it is now
4138 safe to delete it by undoing our prior adjustment to LABEL_NUSES.
4139 If it is now unused, delete it. */
4140 if (end_of_function_label
&& --LABEL_NUSES (end_of_function_label
) == 0)
4141 delete_insn (end_of_function_label
);
4144 if (HAVE_return
&& end_of_function_label
!= 0)
4145 make_return_insns (first
);
4148 obstack_free (&unfilled_slots_obstack
, unfilled_firstobj
);
4150 /* It is not clear why the line below is needed, but it does seem to be. */
4151 unfilled_firstobj
= (rtx
*) obstack_alloc (&unfilled_slots_obstack
, 0);
4153 /* Reposition the prologue and epilogue notes in case we moved the
4154 prologue/epilogue insns. */
4155 reposition_prologue_and_epilogue_notes (first
);
4159 register int i
, j
, need_comma
;
4161 for (reorg_pass_number
= 0;
4162 reorg_pass_number
< MAX_REORG_PASSES
;
4163 reorg_pass_number
++)
4165 fprintf (file
, ";; Reorg pass #%d:\n", reorg_pass_number
+ 1);
4166 for (i
= 0; i
< NUM_REORG_FUNCTIONS
; i
++)
4169 fprintf (file
, ";; Reorg function #%d\n", i
);
4171 fprintf (file
, ";; %d insns needing delay slots\n;; ",
4172 num_insns_needing_delays
[i
][reorg_pass_number
]);
4174 for (j
= 0; j
< MAX_DELAY_HISTOGRAM
; j
++)
4175 if (num_filled_delays
[i
][j
][reorg_pass_number
])
4178 fprintf (file
, ", ");
4180 fprintf (file
, "%d got %d delays",
4181 num_filled_delays
[i
][j
][reorg_pass_number
], j
);
4183 fprintf (file
, "\n");
4188 #endif /* DELAY_SLOTS */