1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx
*reg_last_reload_reg
;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload
;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload
;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx
*reg_equiv_constant
;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx
*reg_equiv_memory_loc
;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx
*reg_equiv_address
;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width
;
117 /* Element N is the insn that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx
*reg_equiv_init
;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber
;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid
;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead
;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs
;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global
;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET
*pseudo_previous_regs
;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET
*pseudo_forbidden_regs
;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs
;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg
;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs
[FIRST_PSEUDO_REGISTER
];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels
;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok
;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok
;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos
;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid
;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed
;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress
= 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
260 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack
;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj
;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj
;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels
;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain
*reload_insn_chain
;
285 /* List of all insns needing reloads. */
286 static struct insn_chain
*insns_need_reload
;
288 /* This structure is used to record information about register eliminations.
289 Each array entry describes one possible way of eliminating a register
290 in favor of another. If there is more than one way of eliminating a
291 particular register, the most preferred should be specified first. */
293 static struct elim_table
295 int from
; /* Register number to be eliminated. */
296 int to
; /* Register number used as replacement. */
297 int initial_offset
; /* Initial difference between values. */
298 int can_eliminate
; /* Non-zero if this elimination can be done. */
299 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
300 insns made by reload. */
301 int offset
; /* Current offset between the two regs. */
302 int max_offset
; /* Maximum offset between the two regs. */
303 int previous_offset
; /* Offset at end of previous insn. */
304 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
305 rtx from_rtx
; /* REG rtx for the register to be eliminated.
306 We cannot simply compare the number since
307 we might then spuriously replace a hard
308 register corresponding to a pseudo
309 assigned to the reg to be eliminated. */
310 rtx to_rtx
; /* REG rtx for the replacement. */
313 /* If a set of eliminable registers was specified, define the table from it.
314 Otherwise, default to the normal case of the frame pointer being
315 replaced by the stack pointer. */
317 #ifdef ELIMINABLE_REGS
320 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
323 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
325 /* Record the number of pending eliminations that have an offset not equal
326 to their initial offset. If non-zero, we use a new copy of each
327 replacement result in any insns encountered. */
328 int num_not_at_initial_offset
;
330 /* Count the number of registers that we may be able to eliminate. */
331 static int num_eliminable
;
333 /* For each label, we record the offset of each elimination. If we reach
334 a label by more than one path and an offset differs, we cannot do the
335 elimination. This information is indexed by the number of the label.
336 The first table is an array of flags that records whether we have yet
337 encountered a label and the second table is an array of arrays, one
338 entry in the latter array for each elimination. */
340 static char *offsets_known_at
;
341 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
343 /* Number of labels in the current function. */
345 static int num_labels
;
347 struct hard_reg_n_uses
353 static void maybe_fix_stack_asms
PROTO((void));
354 static void calculate_needs_all_insns
PROTO((int));
355 static void calculate_needs
PROTO((struct insn_chain
*));
356 static void find_reload_regs
PROTO((struct insn_chain
*chain
,
358 static void find_tworeg_group
PROTO((struct insn_chain
*, int,
360 static void find_group
PROTO((struct insn_chain
*, int,
362 static int possible_group_p
PROTO((struct insn_chain
*, int));
363 static void count_possible_groups
PROTO((struct insn_chain
*, int));
364 static int modes_equiv_for_class_p
PROTO((enum machine_mode
,
367 static void delete_caller_save_insns
PROTO((void));
369 static void spill_failure
PROTO((rtx
));
370 static void new_spill_reg
PROTO((struct insn_chain
*, int, int,
372 static void maybe_mark_pseudo_spilled
PROTO((int));
373 static void delete_dead_insn
PROTO((rtx
));
374 static void alter_reg
PROTO((int, int));
375 static void set_label_offsets
PROTO((rtx
, rtx
, int));
376 static int eliminate_regs_in_insn
PROTO((rtx
, int));
377 static void update_eliminable_offsets
PROTO((void));
378 static void mark_not_eliminable
PROTO((rtx
, rtx
));
379 static void set_initial_elim_offsets
PROTO((void));
380 static void verify_initial_elim_offsets
PROTO((void));
381 static void init_elim_table
PROTO((void));
382 static void update_eliminables
PROTO((HARD_REG_SET
*));
383 static void spill_hard_reg
PROTO((int, FILE *, int));
384 static int finish_spills
PROTO((int, FILE *));
385 static void ior_hard_reg_set
PROTO((HARD_REG_SET
*, HARD_REG_SET
*));
386 static void scan_paradoxical_subregs
PROTO((rtx
));
387 static int hard_reg_use_compare
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
388 static void count_pseudo
PROTO((struct hard_reg_n_uses
*, int));
389 static void order_regs_for_reload
PROTO((struct insn_chain
*));
390 static void reload_as_needed
PROTO((int));
391 static void forget_old_reloads_1
PROTO((rtx
, rtx
));
392 static int reload_reg_class_lower
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
393 static void mark_reload_reg_in_use
PROTO((int, int, enum reload_type
,
395 static void clear_reload_reg_in_use
PROTO((int, int, enum reload_type
,
397 static int reload_reg_free_p
PROTO((int, int, enum reload_type
));
398 static int reload_reg_free_before_p
PROTO((int, int, enum reload_type
, int));
399 static int reload_reg_free_for_value_p
PROTO((int, int, enum reload_type
, rtx
, rtx
, int));
400 static int reload_reg_reaches_end_p
PROTO((int, int, enum reload_type
));
401 static int allocate_reload_reg
PROTO((struct insn_chain
*, int, int,
403 static void choose_reload_regs
PROTO((struct insn_chain
*));
404 static void merge_assigned_reloads
PROTO((rtx
));
405 static void emit_reload_insns
PROTO((struct insn_chain
*));
406 static void delete_output_reload
PROTO((rtx
, int, int));
407 static void delete_address_reloads
PROTO((rtx
, rtx
));
408 static void delete_address_reloads_1
PROTO((rtx
, rtx
, rtx
));
409 static rtx inc_for_reload
PROTO((rtx
, rtx
, rtx
, int));
410 static int constraint_accepts_reg_p
PROTO((char *, rtx
));
411 static void reload_cse_regs_1
PROTO((rtx
));
412 static void reload_cse_invalidate_regno
PROTO((int, enum machine_mode
, int));
413 static int reload_cse_mem_conflict_p
PROTO((rtx
, rtx
));
414 static void reload_cse_invalidate_mem
PROTO((rtx
));
415 static void reload_cse_invalidate_rtx
PROTO((rtx
, rtx
));
416 static int reload_cse_regno_equal_p
PROTO((int, rtx
, enum machine_mode
));
417 static int reload_cse_noop_set_p
PROTO((rtx
, rtx
));
418 static int reload_cse_simplify_set
PROTO((rtx
, rtx
));
419 static int reload_cse_simplify_operands
PROTO((rtx
));
420 static void reload_cse_check_clobber
PROTO((rtx
, rtx
));
421 static void reload_cse_record_set
PROTO((rtx
, rtx
));
422 static void reload_combine
PROTO((void));
423 static void reload_combine_note_use
PROTO((rtx
*, rtx
));
424 static void reload_combine_note_store
PROTO((rtx
, rtx
));
425 static void reload_cse_move2add
PROTO((rtx
));
426 static void move2add_note_store
PROTO((rtx
, rtx
));
428 /* Initialize the reload pass once per compilation. */
435 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
436 Set spill_indirect_levels to the number of levels such addressing is
437 permitted, zero if it is not permitted at all. */
440 = gen_rtx_MEM (Pmode
,
442 gen_rtx_REG (Pmode
, LAST_VIRTUAL_REGISTER
+ 1),
444 spill_indirect_levels
= 0;
446 while (memory_address_p (QImode
, tem
))
448 spill_indirect_levels
++;
449 tem
= gen_rtx_MEM (Pmode
, tem
);
452 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
454 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
455 indirect_symref_ok
= memory_address_p (QImode
, tem
);
457 /* See if reg+reg is a valid (and offsettable) address. */
459 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
461 tem
= gen_rtx_PLUS (Pmode
,
462 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
463 gen_rtx_REG (Pmode
, i
));
464 /* This way, we make sure that reg+reg is an offsettable address. */
465 tem
= plus_constant (tem
, 4);
467 if (memory_address_p (QImode
, tem
))
469 double_reg_address_ok
= 1;
474 /* Initialize obstack for our rtl allocation. */
475 gcc_obstack_init (&reload_obstack
);
476 reload_startobj
= (char *) obstack_alloc (&reload_obstack
, 0);
479 /* List of insn chains that are currently unused. */
480 static struct insn_chain
*unused_insn_chains
= 0;
482 /* Allocate an empty insn_chain structure. */
486 struct insn_chain
*c
;
488 if (unused_insn_chains
== 0)
490 c
= obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
491 c
->live_before
= OBSTACK_ALLOC_REG_SET (&reload_obstack
);
492 c
->live_after
= OBSTACK_ALLOC_REG_SET (&reload_obstack
);
496 c
= unused_insn_chains
;
497 unused_insn_chains
= c
->next
;
499 c
->is_caller_save_insn
= 0;
500 c
->need_operand_change
= 0;
506 /* Small utility function to set all regs in hard reg set TO which are
507 allocated to pseudos in regset FROM. */
509 compute_use_by_pseudos (to
, from
)
514 EXECUTE_IF_SET_IN_REG_SET
515 (from
, FIRST_PSEUDO_REGISTER
, regno
,
517 int r
= reg_renumber
[regno
];
521 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
523 SET_HARD_REG_BIT (*to
, r
+ nregs
);
527 /* Global variables used by reload and its subroutines. */
529 /* Set during calculate_needs if an insn needs register elimination. */
530 static int something_needs_elimination
;
531 /* Set during calculate_needs if an insn needs an operand changed. */
532 int something_needs_operands_changed
;
534 /* Nonzero means we couldn't get enough spill regs. */
537 /* Main entry point for the reload pass.
539 FIRST is the first insn of the function being compiled.
541 GLOBAL nonzero means we were called from global_alloc
542 and should attempt to reallocate any pseudoregs that we
543 displace from hard regs we will use for reloads.
544 If GLOBAL is zero, we do not have enough information to do that,
545 so any pseudo reg that is spilled must go to the stack.
547 DUMPFILE is the global-reg debugging dump file stream, or 0.
548 If it is nonzero, messages are written to it to describe
549 which registers are seized as reload regs, which pseudo regs
550 are spilled from them, and where the pseudo regs are reallocated to.
552 Return value is nonzero if reload failed
553 and we must not do any more for this function. */
556 reload (first
, global
, dumpfile
)
563 register struct elim_table
*ep
;
565 /* The two pointers used to track the true location of the memory used
566 for label offsets. */
567 char *real_known_ptr
= NULL_PTR
;
568 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
570 /* Make sure even insns with volatile mem refs are recognizable. */
575 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
577 /* Make sure that the last insn in the chain
578 is not something that needs reloading. */
579 emit_note (NULL_PTR
, NOTE_INSN_DELETED
);
581 /* Enable find_equiv_reg to distinguish insns made by reload. */
582 reload_first_uid
= get_max_uid ();
584 #ifdef SECONDARY_MEMORY_NEEDED
585 /* Initialize the secondary memory table. */
586 clear_secondary_mem ();
589 /* We don't have a stack slot for any spill reg yet. */
590 bzero ((char *) spill_stack_slot
, sizeof spill_stack_slot
);
591 bzero ((char *) spill_stack_slot_width
, sizeof spill_stack_slot_width
);
593 /* Initialize the save area information for caller-save, in case some
597 /* Compute which hard registers are now in use
598 as homes for pseudo registers.
599 This is done here rather than (eg) in global_alloc
600 because this point is reached even if not optimizing. */
601 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
604 /* A function that receives a nonlocal goto must save all call-saved
606 if (current_function_has_nonlocal_label
)
607 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
609 if (! call_used_regs
[i
] && ! fixed_regs
[i
])
610 regs_ever_live
[i
] = 1;
613 /* Find all the pseudo registers that didn't get hard regs
614 but do have known equivalent constants or memory slots.
615 These include parameters (known equivalent to parameter slots)
616 and cse'd or loop-moved constant memory addresses.
618 Record constant equivalents in reg_equiv_constant
619 so they will be substituted by find_reloads.
620 Record memory equivalents in reg_mem_equiv so they can
621 be substituted eventually by altering the REG-rtx's. */
623 reg_equiv_constant
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
624 bzero ((char *) reg_equiv_constant
, max_regno
* sizeof (rtx
));
625 reg_equiv_memory_loc
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
626 bzero ((char *) reg_equiv_memory_loc
, max_regno
* sizeof (rtx
));
627 reg_equiv_mem
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
628 bzero ((char *) reg_equiv_mem
, max_regno
* sizeof (rtx
));
629 reg_equiv_init
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
630 bzero ((char *) reg_equiv_init
, max_regno
* sizeof (rtx
));
631 reg_equiv_address
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
632 bzero ((char *) reg_equiv_address
, max_regno
* sizeof (rtx
));
633 reg_max_ref_width
= (int *) xmalloc (max_regno
* sizeof (int));
634 bzero ((char *) reg_max_ref_width
, max_regno
* sizeof (int));
635 reg_old_renumber
= (short *) xmalloc (max_regno
* sizeof (short));
636 bcopy (reg_renumber
, reg_old_renumber
, max_regno
* sizeof (short));
637 pseudo_forbidden_regs
638 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
640 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
642 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
643 bzero ((char *) pseudo_previous_regs
, max_regno
* sizeof (HARD_REG_SET
));
645 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
646 Also find all paradoxical subregs and find largest such for each pseudo.
647 On machines with small register classes, record hard registers that
648 are used for user variables. These can never be used for spills.
649 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
650 caller-saved registers must be marked live. */
652 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
654 rtx set
= single_set (insn
);
656 if (GET_CODE (insn
) == NOTE
&& CONST_CALL_P (insn
)
657 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
658 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
659 if (! call_used_regs
[i
])
660 regs_ever_live
[i
] = 1;
662 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
664 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
666 #ifdef LEGITIMATE_PIC_OPERAND_P
667 && (! CONSTANT_P (XEXP (note
, 0)) || ! flag_pic
668 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
672 rtx x
= XEXP (note
, 0);
673 i
= REGNO (SET_DEST (set
));
674 if (i
> LAST_VIRTUAL_REGISTER
)
676 if (GET_CODE (x
) == MEM
)
678 /* If the operand is a PLUS, the MEM may be shared,
679 so make sure we have an unshared copy here. */
680 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
683 reg_equiv_memory_loc
[i
] = x
;
685 else if (CONSTANT_P (x
))
687 if (LEGITIMATE_CONSTANT_P (x
))
688 reg_equiv_constant
[i
] = x
;
690 reg_equiv_memory_loc
[i
]
691 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
696 /* If this register is being made equivalent to a MEM
697 and the MEM is not SET_SRC, the equivalencing insn
698 is one with the MEM as a SET_DEST and it occurs later.
699 So don't mark this insn now. */
700 if (GET_CODE (x
) != MEM
701 || rtx_equal_p (SET_SRC (set
), x
))
702 reg_equiv_init
[i
] = insn
;
707 /* If this insn is setting a MEM from a register equivalent to it,
708 this is the equivalencing insn. */
709 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
710 && GET_CODE (SET_SRC (set
)) == REG
711 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
712 && rtx_equal_p (SET_DEST (set
),
713 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
714 reg_equiv_init
[REGNO (SET_SRC (set
))] = insn
;
716 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
717 scan_paradoxical_subregs (PATTERN (insn
));
722 num_labels
= max_label_num () - get_first_label_num ();
724 /* Allocate the tables used to store offset information at labels. */
725 /* We used to use alloca here, but the size of what it would try to
726 allocate would occasionally cause it to exceed the stack limit and
727 cause a core dump. */
728 real_known_ptr
= xmalloc (num_labels
);
730 = (int (*)[NUM_ELIMINABLE_REGS
])
731 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
733 offsets_known_at
= real_known_ptr
- get_first_label_num ();
735 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
737 /* Alter each pseudo-reg rtx to contain its hard reg number.
738 Assign stack slots to the pseudos that lack hard regs or equivalents.
739 Do not touch virtual registers. */
741 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
744 /* If we have some registers we think can be eliminated, scan all insns to
745 see if there is an insn that sets one of these registers to something
746 other than itself plus a constant. If so, the register cannot be
747 eliminated. Doing this scan here eliminates an extra pass through the
748 main reload loop in the most common case where register elimination
750 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
751 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
752 || GET_CODE (insn
) == CALL_INSN
)
753 note_stores (PATTERN (insn
), mark_not_eliminable
);
755 #ifndef REGISTER_CONSTRAINTS
756 /* If all the pseudo regs have hard regs,
757 except for those that are never referenced,
758 we know that no reloads are needed. */
759 /* But that is not true if there are register constraints, since
760 in that case some pseudos might be in the wrong kind of hard reg. */
762 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
763 if (reg_renumber
[i
] == -1 && REG_N_REFS (i
) != 0)
766 if (i
== max_regno
&& num_eliminable
== 0 && ! caller_save_needed
)
768 free (real_known_ptr
);
770 free (reg_equiv_constant
);
771 free (reg_equiv_memory_loc
);
772 free (reg_equiv_mem
);
773 free (reg_equiv_init
);
774 free (reg_equiv_address
);
775 free (reg_max_ref_width
);
776 free (reg_old_renumber
);
777 free (pseudo_previous_regs
);
778 free (pseudo_forbidden_regs
);
783 maybe_fix_stack_asms ();
785 insns_need_reload
= 0;
786 something_needs_elimination
= 0;
788 /* Initialize to -1, which means take the first spill register. */
791 spilled_pseudos
= ALLOCA_REG_SET ();
793 /* Spill any hard regs that we know we can't eliminate. */
794 CLEAR_HARD_REG_SET (used_spill_regs
);
795 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
796 if (! ep
->can_eliminate
)
797 spill_hard_reg (ep
->from
, dumpfile
, 1);
799 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
800 if (frame_pointer_needed
)
801 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, dumpfile
, 1);
803 finish_spills (global
, dumpfile
);
805 /* From now on, we need to emit any moves without making new pseudos. */
806 reload_in_progress
= 1;
808 /* This loop scans the entire function each go-round
809 and repeats until one repetition spills no additional hard regs. */
812 int something_changed
;
814 struct insn_chain
*chain
;
816 HOST_WIDE_INT starting_frame_size
;
818 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
819 here because the stack size may be a part of the offset computation
820 for register elimination, and there might have been new stack slots
821 created in the last iteration of this loop. */
822 assign_stack_local (BLKmode
, 0, 0);
824 starting_frame_size
= get_frame_size ();
826 set_initial_elim_offsets ();
828 /* For each pseudo register that has an equivalent location defined,
829 try to eliminate any eliminable registers (such as the frame pointer)
830 assuming initial offsets for the replacement register, which
833 If the resulting location is directly addressable, substitute
834 the MEM we just got directly for the old REG.
836 If it is not addressable but is a constant or the sum of a hard reg
837 and constant, it is probably not addressable because the constant is
838 out of range, in that case record the address; we will generate
839 hairy code to compute the address in a register each time it is
840 needed. Similarly if it is a hard register, but one that is not
841 valid as an address register.
843 If the location is not addressable, but does not have one of the
844 above forms, assign a stack slot. We have to do this to avoid the
845 potential of producing lots of reloads if, e.g., a location involves
846 a pseudo that didn't get a hard register and has an equivalent memory
847 location that also involves a pseudo that didn't get a hard register.
849 Perhaps at some point we will improve reload_when_needed handling
850 so this problem goes away. But that's very hairy. */
852 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
853 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
855 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
857 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
859 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
860 else if (CONSTANT_P (XEXP (x
, 0))
861 || (GET_CODE (XEXP (x
, 0)) == REG
862 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
863 || (GET_CODE (XEXP (x
, 0)) == PLUS
864 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
865 && (REGNO (XEXP (XEXP (x
, 0), 0))
866 < FIRST_PSEUDO_REGISTER
)
867 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
868 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
871 /* Make a new stack slot. Then indicate that something
872 changed so we go back and recompute offsets for
873 eliminable registers because the allocation of memory
874 below might change some offset. reg_equiv_{mem,address}
875 will be set up for this pseudo on the next pass around
877 reg_equiv_memory_loc
[i
] = 0;
878 reg_equiv_init
[i
] = 0;
883 if (caller_save_needed
)
886 /* If we allocated another stack slot, redo elimination bookkeeping. */
887 if (starting_frame_size
!= get_frame_size ())
890 if (caller_save_needed
)
892 save_call_clobbered_regs ();
893 /* That might have allocated new insn_chain structures. */
894 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
897 calculate_needs_all_insns (global
);
899 CLEAR_REG_SET (spilled_pseudos
);
902 something_changed
= 0;
904 /* If we allocated any new memory locations, make another pass
905 since it might have changed elimination offsets. */
906 if (starting_frame_size
!= get_frame_size ())
907 something_changed
= 1;
910 HARD_REG_SET to_spill
;
911 CLEAR_HARD_REG_SET (to_spill
);
912 update_eliminables (&to_spill
);
913 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
914 if (TEST_HARD_REG_BIT (to_spill
, i
))
916 spill_hard_reg (i
, dumpfile
, 1);
921 CLEAR_HARD_REG_SET (used_spill_regs
);
922 /* Try to satisfy the needs for each insn. */
923 for (chain
= insns_need_reload
; chain
!= 0;
924 chain
= chain
->next_need_reload
)
925 find_reload_regs (chain
, dumpfile
);
930 if (insns_need_reload
!= 0 || did_spill
)
931 something_changed
|= finish_spills (global
, dumpfile
);
933 if (! something_changed
)
936 if (caller_save_needed
)
937 delete_caller_save_insns ();
940 /* If global-alloc was run, notify it of any register eliminations we have
943 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
944 if (ep
->can_eliminate
)
945 mark_elimination (ep
->from
, ep
->to
);
947 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
948 If that insn didn't set the register (i.e., it copied the register to
949 memory), just delete that insn instead of the equivalencing insn plus
950 anything now dead. If we call delete_dead_insn on that insn, we may
951 delete the insn that actually sets the register if the register die
952 there and that is incorrect. */
954 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
955 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0
956 && GET_CODE (reg_equiv_init
[i
]) != NOTE
)
958 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (reg_equiv_init
[i
])))
959 delete_dead_insn (reg_equiv_init
[i
]);
962 PUT_CODE (reg_equiv_init
[i
], NOTE
);
963 NOTE_SOURCE_FILE (reg_equiv_init
[i
]) = 0;
964 NOTE_LINE_NUMBER (reg_equiv_init
[i
]) = NOTE_INSN_DELETED
;
968 /* Use the reload registers where necessary
969 by generating move instructions to move the must-be-register
970 values into or out of the reload registers. */
972 if (insns_need_reload
!= 0 || something_needs_elimination
973 || something_needs_operands_changed
)
975 int old_frame_size
= get_frame_size ();
977 reload_as_needed (global
);
979 if (old_frame_size
!= get_frame_size ())
983 verify_initial_elim_offsets ();
986 /* If we were able to eliminate the frame pointer, show that it is no
987 longer live at the start of any basic block. If it ls live by
988 virtue of being in a pseudo, that pseudo will be marked live
989 and hence the frame pointer will be known to be live via that
992 if (! frame_pointer_needed
)
993 for (i
= 0; i
< n_basic_blocks
; i
++)
994 CLEAR_REGNO_REG_SET (basic_block_live_at_start
[i
],
995 HARD_FRAME_POINTER_REGNUM
);
997 /* Come here (with failure set nonzero) if we can't get enough spill regs
998 and we decide not to abort about it. */
1001 reload_in_progress
= 0;
1003 /* Now eliminate all pseudo regs by modifying them into
1004 their equivalent memory references.
1005 The REG-rtx's for the pseudos are modified in place,
1006 so all insns that used to refer to them now refer to memory.
1008 For a reg that has a reg_equiv_address, all those insns
1009 were changed by reloading so that no insns refer to it any longer;
1010 but the DECL_RTL of a variable decl may refer to it,
1011 and if so this causes the debugging info to mention the variable. */
1013 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1017 int is_readonly
= 0;
1019 if (reg_equiv_memory_loc
[i
])
1021 in_struct
= MEM_IN_STRUCT_P (reg_equiv_memory_loc
[i
]);
1022 is_readonly
= RTX_UNCHANGING_P (reg_equiv_memory_loc
[i
]);
1025 if (reg_equiv_mem
[i
])
1026 addr
= XEXP (reg_equiv_mem
[i
], 0);
1028 if (reg_equiv_address
[i
])
1029 addr
= reg_equiv_address
[i
];
1033 if (reg_renumber
[i
] < 0)
1035 rtx reg
= regno_reg_rtx
[i
];
1036 XEXP (reg
, 0) = addr
;
1037 REG_USERVAR_P (reg
) = 0;
1038 RTX_UNCHANGING_P (reg
) = is_readonly
;
1039 MEM_IN_STRUCT_P (reg
) = in_struct
;
1040 /* We have no alias information about this newly created
1042 MEM_ALIAS_SET (reg
) = 0;
1043 PUT_CODE (reg
, MEM
);
1045 else if (reg_equiv_mem
[i
])
1046 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1050 /* Make a pass over all the insns and delete all USEs which we inserted
1051 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1052 notes. Delete all CLOBBER insns and simplify (subreg (reg)) operands. */
1054 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1055 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1059 if ((GET_CODE (PATTERN (insn
)) == USE
1060 && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1061 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
1063 PUT_CODE (insn
, NOTE
);
1064 NOTE_SOURCE_FILE (insn
) = 0;
1065 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1069 pnote
= ®_NOTES (insn
);
1072 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1073 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
)
1074 *pnote
= XEXP (*pnote
, 1);
1076 pnote
= &XEXP (*pnote
, 1);
1079 /* And simplify (subreg (reg)) if it appears as an operand. */
1080 cleanup_subreg_operands (insn
);
1083 /* If we are doing stack checking, give a warning if this function's
1084 frame size is larger than we expect. */
1085 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1087 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1089 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1090 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1091 size
+= UNITS_PER_WORD
;
1093 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1094 warning ("frame size too large for reliable stack checking");
1097 /* Indicate that we no longer have known memory locations or constants. */
1098 if (reg_equiv_constant
)
1099 free (reg_equiv_constant
);
1100 reg_equiv_constant
= 0;
1101 if (reg_equiv_memory_loc
)
1102 free (reg_equiv_memory_loc
);
1103 reg_equiv_memory_loc
= 0;
1106 free (real_known_ptr
);
1110 free (reg_equiv_mem
);
1111 free (reg_equiv_init
);
1112 free (reg_equiv_address
);
1113 free (reg_max_ref_width
);
1114 free (reg_old_renumber
);
1115 free (pseudo_previous_regs
);
1116 free (pseudo_forbidden_regs
);
1118 FREE_REG_SET (spilled_pseudos
);
1120 CLEAR_HARD_REG_SET (used_spill_regs
);
1121 for (i
= 0; i
< n_spills
; i
++)
1122 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1124 /* Free all the insn_chain structures at once. */
1125 obstack_free (&reload_obstack
, reload_startobj
);
1126 unused_insn_chains
= 0;
1131 /* Yet another special case. Unfortunately, reg-stack forces people to
1132 write incorrect clobbers in asm statements. These clobbers must not
1133 cause the register to appear in bad_spill_regs, otherwise we'll call
1134 fatal_insn later. We clear the corresponding regnos in the live
1135 register sets to avoid this.
1136 The whole thing is rather sick, I'm afraid. */
1138 maybe_fix_stack_asms ()
1141 char *constraints
[MAX_RECOG_OPERANDS
];
1142 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1143 struct insn_chain
*chain
;
1145 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1148 HARD_REG_SET clobbered
, allowed
;
1151 if (GET_RTX_CLASS (GET_CODE (chain
->insn
)) != 'i'
1152 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1154 pat
= PATTERN (chain
->insn
);
1155 if (GET_CODE (pat
) != PARALLEL
)
1158 CLEAR_HARD_REG_SET (clobbered
);
1159 CLEAR_HARD_REG_SET (allowed
);
1161 /* First, make a mask of all stack regs that are clobbered. */
1162 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1164 rtx t
= XVECEXP (pat
, 0, i
);
1165 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1166 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1169 /* Get the operand values and constraints out of the insn. */
1170 decode_asm_operands (pat
, recog_operand
, recog_operand_loc
,
1171 constraints
, operand_mode
);
1173 /* For every operand, see what registers are allowed. */
1174 for (i
= 0; i
< noperands
; i
++)
1176 char *p
= constraints
[i
];
1177 /* For every alternative, we compute the class of registers allowed
1178 for reloading in CLS, and merge its contents into the reg set
1180 int cls
= (int) NO_REGS
;
1186 if (c
== '\0' || c
== ',' || c
== '#')
1188 /* End of one alternative - mark the regs in the current
1189 class, and reset the class. */
1190 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1195 } while (c
!= '\0' && c
!= ',');
1203 case '=': case '+': case '*': case '%': case '?': case '!':
1204 case '0': case '1': case '2': case '3': case '4': case 'm':
1205 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1206 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1207 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1209 #ifdef EXTRA_CONSTRAINT
1210 case 'Q': case 'R': case 'S': case 'T': case 'U':
1215 cls
= (int) reg_class_subunion
[cls
][(int) BASE_REG_CLASS
];
1220 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1224 cls
= (int) reg_class_subunion
[cls
][(int) REG_CLASS_FROM_LETTER (c
)];
1229 /* Those of the registers which are clobbered, but allowed by the
1230 constraints, must be usable as reload registers. So clear them
1231 out of the life information. */
1232 AND_HARD_REG_SET (allowed
, clobbered
);
1233 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1234 if (TEST_HARD_REG_BIT (allowed
, i
))
1236 CLEAR_REGNO_REG_SET (chain
->live_before
, i
);
1237 CLEAR_REGNO_REG_SET (chain
->live_after
, i
);
1245 /* Walk the chain of insns, and determine for each whether it needs reloads
1246 and/or eliminations. Build the corresponding insns_need_reload list, and
1247 set something_needs_elimination as appropriate. */
1249 calculate_needs_all_insns (global
)
1252 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1253 struct insn_chain
**pchain
;
1255 something_needs_elimination
= 0;
1257 for (pchain
= &reload_insn_chain
; *pchain
!= 0; pchain
= &(*pchain
)->next
)
1260 struct insn_chain
*chain
;
1265 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1266 include REG_LABEL), we need to see what effects this has on the
1267 known offsets at labels. */
1269 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1270 || (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1271 && REG_NOTES (insn
) != 0))
1272 set_label_offsets (insn
, insn
, 0);
1274 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1276 rtx old_body
= PATTERN (insn
);
1277 int old_code
= INSN_CODE (insn
);
1278 rtx old_notes
= REG_NOTES (insn
);
1279 int did_elimination
= 0;
1280 int operands_changed
= 0;
1282 /* If needed, eliminate any eliminable registers. */
1284 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1286 /* Analyze the instruction. */
1287 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1288 global
, spill_reg_order
);
1290 /* If a no-op set needs more than one reload, this is likely
1291 to be something that needs input address reloads. We
1292 can't get rid of this cleanly later, and it is of no use
1293 anyway, so discard it now.
1294 We only do this when expensive_optimizations is enabled,
1295 since this complements reload inheritance / output
1296 reload deletion, and it can make debugging harder. */
1297 if (flag_expensive_optimizations
&& n_reloads
> 1)
1299 rtx set
= single_set (insn
);
1301 && SET_SRC (set
) == SET_DEST (set
)
1302 && GET_CODE (SET_SRC (set
)) == REG
1303 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1305 PUT_CODE (insn
, NOTE
);
1306 NOTE_SOURCE_FILE (insn
) = 0;
1307 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1312 update_eliminable_offsets ();
1314 /* Remember for later shortcuts which insns had any reloads or
1315 register eliminations. */
1316 chain
->need_elim
= did_elimination
;
1317 chain
->need_reload
= n_reloads
> 0;
1318 chain
->need_operand_change
= operands_changed
;
1320 /* Discard any register replacements done. */
1321 if (did_elimination
)
1323 obstack_free (&reload_obstack
, reload_firstobj
);
1324 PATTERN (insn
) = old_body
;
1325 INSN_CODE (insn
) = old_code
;
1326 REG_NOTES (insn
) = old_notes
;
1327 something_needs_elimination
= 1;
1330 something_needs_operands_changed
|= operands_changed
;
1334 *pprev_reload
= chain
;
1335 pprev_reload
= &chain
->next_need_reload
;
1337 calculate_needs (chain
);
1344 /* Compute the most additional registers needed by one instruction,
1345 given by CHAIN. Collect information separately for each class of regs.
1347 To compute the number of reload registers of each class needed for an
1348 insn, we must simulate what choose_reload_regs can do. We do this by
1349 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1350 reloads are used in both. The input part uses those reloads,
1351 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1352 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1353 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1355 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1356 which are live for the entire output portion, and the maximum of all the
1357 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1359 The total number of registers needed is the maximum of the
1360 inputs and outputs. */
1363 calculate_needs (chain
)
1364 struct insn_chain
*chain
;
1368 /* Each `struct needs' corresponds to one RELOAD_... type. */
1372 struct needs output
;
1374 struct needs other_addr
;
1375 struct needs op_addr
;
1376 struct needs op_addr_reload
;
1377 struct needs in_addr
[MAX_RECOG_OPERANDS
];
1378 struct needs in_addr_addr
[MAX_RECOG_OPERANDS
];
1379 struct needs out_addr
[MAX_RECOG_OPERANDS
];
1380 struct needs out_addr_addr
[MAX_RECOG_OPERANDS
];
1383 bzero ((char *) chain
->group_size
, sizeof chain
->group_size
);
1384 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1385 chain
->group_mode
[i
] = VOIDmode
;
1386 bzero ((char *) &insn_needs
, sizeof insn_needs
);
1388 /* Count each reload once in every class
1389 containing the reload's own class. */
1391 for (i
= 0; i
< n_reloads
; i
++)
1393 register enum reg_class
*p
;
1394 enum reg_class
class = reload_reg_class
[i
];
1396 enum machine_mode mode
;
1397 struct needs
*this_needs
;
1399 /* Don't count the dummy reloads, for which one of the
1400 regs mentioned in the insn can be used for reloading.
1401 Don't count optional reloads.
1402 Don't count reloads that got combined with others. */
1403 if (reload_reg_rtx
[i
] != 0
1404 || reload_optional
[i
] != 0
1405 || (reload_out
[i
] == 0 && reload_in
[i
] == 0
1406 && ! reload_secondary_p
[i
]))
1409 mode
= reload_inmode
[i
];
1410 if (GET_MODE_SIZE (reload_outmode
[i
]) > GET_MODE_SIZE (mode
))
1411 mode
= reload_outmode
[i
];
1412 size
= CLASS_MAX_NREGS (class, mode
);
1414 /* Decide which time-of-use to count this reload for. */
1415 switch (reload_when_needed
[i
])
1418 this_needs
= &insn_needs
.other
;
1420 case RELOAD_FOR_INPUT
:
1421 this_needs
= &insn_needs
.input
;
1423 case RELOAD_FOR_OUTPUT
:
1424 this_needs
= &insn_needs
.output
;
1426 case RELOAD_FOR_INSN
:
1427 this_needs
= &insn_needs
.insn
;
1429 case RELOAD_FOR_OTHER_ADDRESS
:
1430 this_needs
= &insn_needs
.other_addr
;
1432 case RELOAD_FOR_INPUT_ADDRESS
:
1433 this_needs
= &insn_needs
.in_addr
[reload_opnum
[i
]];
1435 case RELOAD_FOR_INPADDR_ADDRESS
:
1436 this_needs
= &insn_needs
.in_addr_addr
[reload_opnum
[i
]];
1438 case RELOAD_FOR_OUTPUT_ADDRESS
:
1439 this_needs
= &insn_needs
.out_addr
[reload_opnum
[i
]];
1441 case RELOAD_FOR_OUTADDR_ADDRESS
:
1442 this_needs
= &insn_needs
.out_addr_addr
[reload_opnum
[i
]];
1444 case RELOAD_FOR_OPERAND_ADDRESS
:
1445 this_needs
= &insn_needs
.op_addr
;
1447 case RELOAD_FOR_OPADDR_ADDR
:
1448 this_needs
= &insn_needs
.op_addr_reload
;
1454 enum machine_mode other_mode
, allocate_mode
;
1456 /* Count number of groups needed separately from
1457 number of individual regs needed. */
1458 this_needs
->groups
[(int) class]++;
1459 p
= reg_class_superclasses
[(int) class];
1460 while (*p
!= LIM_REG_CLASSES
)
1461 this_needs
->groups
[(int) *p
++]++;
1463 /* Record size and mode of a group of this class. */
1464 /* If more than one size group is needed,
1465 make all groups the largest needed size. */
1466 if (chain
->group_size
[(int) class] < size
)
1468 other_mode
= chain
->group_mode
[(int) class];
1469 allocate_mode
= mode
;
1471 chain
->group_size
[(int) class] = size
;
1472 chain
->group_mode
[(int) class] = mode
;
1477 allocate_mode
= chain
->group_mode
[(int) class];
1480 /* Crash if two dissimilar machine modes both need
1481 groups of consecutive regs of the same class. */
1483 if (other_mode
!= VOIDmode
&& other_mode
!= allocate_mode
1484 && ! modes_equiv_for_class_p (allocate_mode
,
1486 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1491 this_needs
->regs
[(unsigned char)reload_nongroup
[i
]][(int) class] += 1;
1492 p
= reg_class_superclasses
[(int) class];
1493 while (*p
!= LIM_REG_CLASSES
)
1494 this_needs
->regs
[(unsigned char)reload_nongroup
[i
]][(int) *p
++] += 1;
1500 /* All reloads have been counted for this insn;
1501 now merge the various times of use.
1502 This sets insn_needs, etc., to the maximum total number
1503 of registers needed at any point in this insn. */
1505 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1507 int j
, in_max
, out_max
;
1509 /* Compute normal and nongroup needs. */
1510 for (j
= 0; j
<= 1; j
++)
1513 for (in_max
= 0, out_max
= 0, k
= 0; k
< reload_n_operands
; k
++)
1515 in_max
= MAX (in_max
,
1516 (insn_needs
.in_addr
[k
].regs
[j
][i
]
1517 + insn_needs
.in_addr_addr
[k
].regs
[j
][i
]));
1518 out_max
= MAX (out_max
, insn_needs
.out_addr
[k
].regs
[j
][i
]);
1519 out_max
= MAX (out_max
,
1520 insn_needs
.out_addr_addr
[k
].regs
[j
][i
]);
1523 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1524 and operand addresses but not things used to reload
1525 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1526 don't conflict with things needed to reload inputs or
1529 in_max
= MAX (MAX (insn_needs
.op_addr
.regs
[j
][i
],
1530 insn_needs
.op_addr_reload
.regs
[j
][i
]),
1533 out_max
= MAX (out_max
, insn_needs
.insn
.regs
[j
][i
]);
1535 insn_needs
.input
.regs
[j
][i
]
1536 = MAX (insn_needs
.input
.regs
[j
][i
]
1537 + insn_needs
.op_addr
.regs
[j
][i
]
1538 + insn_needs
.insn
.regs
[j
][i
],
1539 in_max
+ insn_needs
.input
.regs
[j
][i
]);
1541 insn_needs
.output
.regs
[j
][i
] += out_max
;
1542 insn_needs
.other
.regs
[j
][i
]
1543 += MAX (MAX (insn_needs
.input
.regs
[j
][i
],
1544 insn_needs
.output
.regs
[j
][i
]),
1545 insn_needs
.other_addr
.regs
[j
][i
]);
1549 /* Now compute group needs. */
1550 for (in_max
= 0, out_max
= 0, j
= 0; j
< reload_n_operands
; j
++)
1552 in_max
= MAX (in_max
, insn_needs
.in_addr
[j
].groups
[i
]);
1553 in_max
= MAX (in_max
, insn_needs
.in_addr_addr
[j
].groups
[i
]);
1554 out_max
= MAX (out_max
, insn_needs
.out_addr
[j
].groups
[i
]);
1555 out_max
= MAX (out_max
, insn_needs
.out_addr_addr
[j
].groups
[i
]);
1558 in_max
= MAX (MAX (insn_needs
.op_addr
.groups
[i
],
1559 insn_needs
.op_addr_reload
.groups
[i
]),
1561 out_max
= MAX (out_max
, insn_needs
.insn
.groups
[i
]);
1563 insn_needs
.input
.groups
[i
]
1564 = MAX (insn_needs
.input
.groups
[i
]
1565 + insn_needs
.op_addr
.groups
[i
]
1566 + insn_needs
.insn
.groups
[i
],
1567 in_max
+ insn_needs
.input
.groups
[i
]);
1569 insn_needs
.output
.groups
[i
] += out_max
;
1570 insn_needs
.other
.groups
[i
]
1571 += MAX (MAX (insn_needs
.input
.groups
[i
],
1572 insn_needs
.output
.groups
[i
]),
1573 insn_needs
.other_addr
.groups
[i
]);
1576 /* Record the needs for later. */
1577 chain
->need
= insn_needs
.other
;
1580 /* Find a group of exactly 2 registers.
1582 First try to fill out the group by spilling a single register which
1583 would allow completion of the group.
1585 Then try to create a new group from a pair of registers, neither of
1586 which are explicitly used.
1588 Then try to create a group from any pair of registers. */
1591 find_tworeg_group (chain
, class, dumpfile
)
1592 struct insn_chain
*chain
;
1597 /* First, look for a register that will complete a group. */
1598 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1602 j
= potential_reload_regs
[i
];
1603 if (j
>= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
)
1604 && ((j
> 0 && (other
= j
- 1, spill_reg_order
[other
] >= 0)
1605 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1606 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1607 && HARD_REGNO_MODE_OK (other
, chain
->group_mode
[class])
1608 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, other
)
1609 /* We don't want one part of another group.
1610 We could get "two groups" that overlap! */
1611 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, other
))
1612 || (j
< FIRST_PSEUDO_REGISTER
- 1
1613 && (other
= j
+ 1, spill_reg_order
[other
] >= 0)
1614 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1615 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1616 && HARD_REGNO_MODE_OK (j
, chain
->group_mode
[class])
1617 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, other
)
1618 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, other
))))
1620 register enum reg_class
*p
;
1622 /* We have found one that will complete a group,
1623 so count off one group as provided. */
1624 chain
->need
.groups
[class]--;
1625 p
= reg_class_superclasses
[class];
1626 while (*p
!= LIM_REG_CLASSES
)
1628 if (chain
->group_size
[(int) *p
] <= chain
->group_size
[class])
1629 chain
->need
.groups
[(int) *p
]--;
1633 /* Indicate both these regs are part of a group. */
1634 SET_HARD_REG_BIT (chain
->counted_for_groups
, j
);
1635 SET_HARD_REG_BIT (chain
->counted_for_groups
, other
);
1639 /* We can't complete a group, so start one. */
1640 if (i
== FIRST_PSEUDO_REGISTER
)
1641 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1644 j
= potential_reload_regs
[i
];
1645 /* Verify that J+1 is a potential reload reg. */
1646 for (k
= 0; k
< FIRST_PSEUDO_REGISTER
; k
++)
1647 if (potential_reload_regs
[k
] == j
+ 1)
1649 if (j
>= 0 && j
+ 1 < FIRST_PSEUDO_REGISTER
1650 && k
< FIRST_PSEUDO_REGISTER
1651 && spill_reg_order
[j
] < 0 && spill_reg_order
[j
+ 1] < 0
1652 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1653 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ 1)
1654 && HARD_REGNO_MODE_OK (j
, chain
->group_mode
[class])
1655 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, j
+ 1)
1656 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ 1))
1660 /* I should be the index in potential_reload_regs
1661 of the new reload reg we have found. */
1663 new_spill_reg (chain
, i
, class, 0, dumpfile
);
1666 /* Find a group of more than 2 registers.
1667 Look for a sufficient sequence of unspilled registers, and spill them all
1671 find_group (chain
, class, dumpfile
)
1672 struct insn_chain
*chain
;
1678 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1680 int j
= potential_reload_regs
[i
];
1683 && j
+ chain
->group_size
[class] <= FIRST_PSEUDO_REGISTER
1684 && HARD_REGNO_MODE_OK (j
, chain
->group_mode
[class]))
1687 /* Check each reg in the sequence. */
1688 for (k
= 0; k
< chain
->group_size
[class]; k
++)
1689 if (! (spill_reg_order
[j
+ k
] < 0
1690 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ k
)
1691 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ k
)))
1693 /* We got a full sequence, so spill them all. */
1694 if (k
== chain
->group_size
[class])
1696 register enum reg_class
*p
;
1697 for (k
= 0; k
< chain
->group_size
[class]; k
++)
1700 SET_HARD_REG_BIT (chain
->counted_for_groups
, j
+ k
);
1701 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
1702 if (potential_reload_regs
[idx
] == j
+ k
)
1704 new_spill_reg (chain
, idx
, class, 0, dumpfile
);
1707 /* We have found one that will complete a group,
1708 so count off one group as provided. */
1709 chain
->need
.groups
[class]--;
1710 p
= reg_class_superclasses
[class];
1711 while (*p
!= LIM_REG_CLASSES
)
1713 if (chain
->group_size
[(int) *p
]
1714 <= chain
->group_size
[class])
1715 chain
->need
.groups
[(int) *p
]--;
1722 /* There are no groups left. */
1723 spill_failure (chain
->insn
);
1727 /* If pseudo REG conflicts with one of our reload registers, mark it as
1730 maybe_mark_pseudo_spilled (reg
)
1734 int r
= reg_renumber
[reg
];
1739 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1740 for (i
= 0; i
< n_spills
; i
++)
1741 if (r
<= spill_regs
[i
] && r
+ nregs
> spill_regs
[i
])
1743 SET_REGNO_REG_SET (spilled_pseudos
, reg
);
1748 /* Find more reload regs to satisfy the remaining need of an insn, which
1750 Do it by ascending class number, since otherwise a reg
1751 might be spilled for a big class and might fail to count
1752 for a smaller class even though it belongs to that class.
1754 Count spilled regs in `spills', and add entries to
1755 `spill_regs' and `spill_reg_order'.
1757 ??? Note there is a problem here.
1758 When there is a need for a group in a high-numbered class,
1759 and also need for non-group regs that come from a lower class,
1760 the non-group regs are chosen first. If there aren't many regs,
1761 they might leave no room for a group.
1763 This was happening on the 386. To fix it, we added the code
1764 that calls possible_group_p, so that the lower class won't
1765 break up the last possible group.
1767 Really fixing the problem would require changes above
1768 in counting the regs already spilled, and in choose_reload_regs.
1769 It might be hard to avoid introducing bugs there. */
1772 find_reload_regs (chain
, dumpfile
)
1773 struct insn_chain
*chain
;
1777 short *group_needs
= chain
->need
.groups
;
1778 short *simple_needs
= chain
->need
.regs
[0];
1779 short *nongroup_needs
= chain
->need
.regs
[1];
1782 fprintf (dumpfile
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1784 /* Compute the order of preference for hard registers to spill.
1785 Store them by decreasing preference in potential_reload_regs. */
1787 order_regs_for_reload (chain
);
1789 /* So far, no hard regs have been spilled. */
1791 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1792 spill_reg_order
[i
] = -1;
1794 CLEAR_HARD_REG_SET (chain
->used_spill_regs
);
1795 CLEAR_HARD_REG_SET (chain
->counted_for_groups
);
1796 CLEAR_HARD_REG_SET (chain
->counted_for_nongroups
);
1798 for (class = 0; class < N_REG_CLASSES
; class++)
1800 /* First get the groups of registers.
1801 If we got single registers first, we might fragment
1803 while (group_needs
[class] > 0)
1805 /* If any single spilled regs happen to form groups,
1806 count them now. Maybe we don't really need
1807 to spill another group. */
1808 count_possible_groups (chain
, class);
1810 if (group_needs
[class] <= 0)
1813 /* Groups of size 2, the only groups used on most machines,
1814 are treated specially. */
1815 if (chain
->group_size
[class] == 2)
1816 find_tworeg_group (chain
, class, dumpfile
);
1818 find_group (chain
, class, dumpfile
);
1823 /* Now similarly satisfy all need for single registers. */
1825 while (simple_needs
[class] > 0 || nongroup_needs
[class] > 0)
1827 /* If we spilled enough regs, but they weren't counted
1828 against the non-group need, see if we can count them now.
1829 If so, we can avoid some actual spilling. */
1830 if (simple_needs
[class] <= 0 && nongroup_needs
[class] > 0)
1831 for (i
= 0; i
< n_spills
; i
++)
1833 int regno
= spill_regs
[i
];
1834 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1835 && !TEST_HARD_REG_BIT (chain
->counted_for_groups
, regno
)
1836 && !TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
)
1837 && nongroup_needs
[class] > 0)
1839 register enum reg_class
*p
;
1841 SET_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
);
1842 nongroup_needs
[class]--;
1843 p
= reg_class_superclasses
[class];
1844 while (*p
!= LIM_REG_CLASSES
)
1845 nongroup_needs
[(int) *p
++]--;
1849 if (simple_needs
[class] <= 0 && nongroup_needs
[class] <= 0)
1852 /* Consider the potential reload regs that aren't
1853 yet in use as reload regs, in order of preference.
1854 Find the most preferred one that's in this class. */
1856 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1858 int regno
= potential_reload_regs
[i
];
1860 && TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1861 /* If this reg will not be available for groups,
1862 pick one that does not foreclose possible groups.
1863 This is a kludge, and not very general,
1864 but it should be sufficient to make the 386 work,
1865 and the problem should not occur on machines with
1867 && (nongroup_needs
[class] == 0
1868 || possible_group_p (chain
, regno
)))
1872 /* If we couldn't get a register, try to get one even if we
1873 might foreclose possible groups. This may cause problems
1874 later, but that's better than aborting now, since it is
1875 possible that we will, in fact, be able to form the needed
1876 group even with this allocation. */
1878 if (i
>= FIRST_PSEUDO_REGISTER
1879 && asm_noperands (chain
->insn
) < 0)
1880 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1881 if (potential_reload_regs
[i
] >= 0
1882 && TEST_HARD_REG_BIT (reg_class_contents
[class],
1883 potential_reload_regs
[i
]))
1886 /* I should be the index in potential_reload_regs
1887 of the new reload reg we have found. */
1889 new_spill_reg (chain
, i
, class, 1, dumpfile
);
1895 /* We know which hard regs to use, now mark the pseudos that live in them
1896 as needing to be kicked out. */
1897 EXECUTE_IF_SET_IN_REG_SET
1898 (chain
->live_before
, FIRST_PSEUDO_REGISTER
, i
,
1900 maybe_mark_pseudo_spilled (i
);
1902 EXECUTE_IF_SET_IN_REG_SET
1903 (chain
->live_after
, FIRST_PSEUDO_REGISTER
, i
,
1905 maybe_mark_pseudo_spilled (i
);
1908 IOR_HARD_REG_SET (used_spill_regs
, chain
->used_spill_regs
);
1912 dump_needs (chain
, dumpfile
)
1913 struct insn_chain
*chain
;
1916 static char *reg_class_names
[] = REG_CLASS_NAMES
;
1918 struct needs
*n
= &chain
->need
;
1920 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1922 if (n
->regs
[i
][0] > 0)
1924 ";; Need %d reg%s of class %s.\n",
1925 n
->regs
[i
][0], n
->regs
[i
][0] == 1 ? "" : "s",
1926 reg_class_names
[i
]);
1927 if (n
->regs
[i
][1] > 0)
1929 ";; Need %d nongroup reg%s of class %s.\n",
1930 n
->regs
[i
][1], n
->regs
[i
][1] == 1 ? "" : "s",
1931 reg_class_names
[i
]);
1932 if (n
->groups
[i
] > 0)
1934 ";; Need %d group%s (%smode) of class %s.\n",
1935 n
->groups
[i
], n
->groups
[i
] == 1 ? "" : "s",
1936 mode_name
[(int) chain
->group_mode
[i
]],
1937 reg_class_names
[i
]);
1941 /* Delete all insns that were inserted by emit_caller_save_insns during
1944 delete_caller_save_insns ()
1946 struct insn_chain
*c
= reload_insn_chain
;
1950 while (c
!= 0 && c
->is_caller_save_insn
)
1952 struct insn_chain
*next
= c
->next
;
1955 if (insn
== basic_block_head
[c
->block
])
1956 basic_block_head
[c
->block
] = NEXT_INSN (insn
);
1957 if (insn
== basic_block_end
[c
->block
])
1958 basic_block_end
[c
->block
] = PREV_INSN (insn
);
1959 if (c
== reload_insn_chain
)
1960 reload_insn_chain
= next
;
1962 if (NEXT_INSN (insn
) != 0)
1963 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1964 if (PREV_INSN (insn
) != 0)
1965 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1968 next
->prev
= c
->prev
;
1970 c
->prev
->next
= next
;
1971 c
->next
= unused_insn_chains
;
1972 unused_insn_chains
= c
;
1980 /* Nonzero if, after spilling reg REGNO for non-groups,
1981 it will still be possible to find a group if we still need one. */
1984 possible_group_p (chain
, regno
)
1985 struct insn_chain
*chain
;
1989 int class = (int) NO_REGS
;
1991 for (i
= 0; i
< (int) N_REG_CLASSES
; i
++)
1992 if (chain
->need
.groups
[i
] > 0)
1998 if (class == (int) NO_REGS
)
2001 /* Consider each pair of consecutive registers. */
2002 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
- 1; i
++)
2004 /* Ignore pairs that include reg REGNO. */
2005 if (i
== regno
|| i
+ 1 == regno
)
2008 /* Ignore pairs that are outside the class that needs the group.
2009 ??? Here we fail to handle the case where two different classes
2010 independently need groups. But this never happens with our
2011 current machine descriptions. */
2012 if (! (TEST_HARD_REG_BIT (reg_class_contents
[class], i
)
2013 && TEST_HARD_REG_BIT (reg_class_contents
[class], i
+ 1)))
2016 /* A pair of consecutive regs we can still spill does the trick. */
2017 if (spill_reg_order
[i
] < 0 && spill_reg_order
[i
+ 1] < 0
2018 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2019 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1))
2022 /* A pair of one already spilled and one we can spill does it
2023 provided the one already spilled is not otherwise reserved. */
2024 if (spill_reg_order
[i
] < 0
2025 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2026 && spill_reg_order
[i
+ 1] >= 0
2027 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, i
+ 1)
2028 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, i
+ 1))
2030 if (spill_reg_order
[i
+ 1] < 0
2031 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1)
2032 && spill_reg_order
[i
] >= 0
2033 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, i
)
2034 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, i
))
2041 /* Count any groups of CLASS that can be formed from the registers recently
2045 count_possible_groups (chain
, class)
2046 struct insn_chain
*chain
;
2052 /* Now find all consecutive groups of spilled registers
2053 and mark each group off against the need for such groups.
2054 But don't count them against ordinary need, yet. */
2056 if (chain
->group_size
[class] == 0)
2059 CLEAR_HARD_REG_SET (new);
2061 /* Make a mask of all the regs that are spill regs in class I. */
2062 for (i
= 0; i
< n_spills
; i
++)
2064 int regno
= spill_regs
[i
];
2066 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
2067 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, regno
)
2068 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
))
2069 SET_HARD_REG_BIT (new, regno
);
2072 /* Find each consecutive group of them. */
2073 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
&& chain
->need
.groups
[class] > 0; i
++)
2074 if (TEST_HARD_REG_BIT (new, i
)
2075 && i
+ chain
->group_size
[class] <= FIRST_PSEUDO_REGISTER
2076 && HARD_REGNO_MODE_OK (i
, chain
->group_mode
[class]))
2078 for (j
= 1; j
< chain
->group_size
[class]; j
++)
2079 if (! TEST_HARD_REG_BIT (new, i
+ j
))
2082 if (j
== chain
->group_size
[class])
2084 /* We found a group. Mark it off against this class's need for
2085 groups, and against each superclass too. */
2086 register enum reg_class
*p
;
2088 chain
->need
.groups
[class]--;
2089 p
= reg_class_superclasses
[class];
2090 while (*p
!= LIM_REG_CLASSES
)
2092 if (chain
->group_size
[(int) *p
] <= chain
->group_size
[class])
2093 chain
->need
.groups
[(int) *p
]--;
2097 /* Don't count these registers again. */
2098 for (j
= 0; j
< chain
->group_size
[class]; j
++)
2099 SET_HARD_REG_BIT (chain
->counted_for_groups
, i
+ j
);
2102 /* Skip to the last reg in this group. When i is incremented above,
2103 it will then point to the first reg of the next possible group. */
2108 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2109 another mode that needs to be reloaded for the same register class CLASS.
2110 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2111 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2113 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2114 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2115 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2116 causes unnecessary failures on machines requiring alignment of register
2117 groups when the two modes are different sizes, because the larger mode has
2118 more strict alignment rules than the smaller mode. */
2121 modes_equiv_for_class_p (allocate_mode
, other_mode
, class)
2122 enum machine_mode allocate_mode
, other_mode
;
2123 enum reg_class
class;
2126 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2128 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
)
2129 && HARD_REGNO_MODE_OK (regno
, allocate_mode
)
2130 && ! HARD_REGNO_MODE_OK (regno
, other_mode
))
2136 /* Handle the failure to find a register to spill.
2137 INSN should be one of the insns which needed this particular spill reg. */
2140 spill_failure (insn
)
2143 if (asm_noperands (PATTERN (insn
)) >= 0)
2144 error_for_asm (insn
, "`asm' needs too many reloads");
2146 fatal_insn ("Unable to find a register to spill.", insn
);
2149 /* Add a new register to the tables of available spill-registers.
2150 CHAIN is the insn for which the register will be used; we decrease the
2152 I is the index of this register in potential_reload_regs.
2153 CLASS is the regclass whose need is being satisfied.
2154 NONGROUP is 0 if this register is part of a group.
2155 DUMPFILE is the same as the one that `reload' got. */
2158 new_spill_reg (chain
, i
, class, nongroup
, dumpfile
)
2159 struct insn_chain
*chain
;
2165 register enum reg_class
*p
;
2166 int regno
= potential_reload_regs
[i
];
2168 if (i
>= FIRST_PSEUDO_REGISTER
)
2170 spill_failure (chain
->insn
);
2175 if (TEST_HARD_REG_BIT (bad_spill_regs
, regno
))
2177 static char *reg_class_names
[] = REG_CLASS_NAMES
;
2179 if (asm_noperands (PATTERN (chain
->insn
)) < 0)
2181 /* The error message is still correct - we know only that it wasn't
2182 an asm statement that caused the problem, but one of the global
2183 registers declared by the users might have screwed us. */
2184 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2185 regno
, reg_names
[regno
], reg_class_names
[class]);
2186 error ("This may be due to a compiler bug or to impossible asm");
2187 error ("statements or clauses.");
2188 fatal_insn ("This is the instruction:", chain
->insn
);
2190 error_for_asm (chain
->insn
, "Invalid `asm' statement:");
2191 error_for_asm (chain
->insn
,
2192 "fixed or forbidden register %d (%s) was spilled for class %s.",
2193 regno
, reg_names
[regno
], reg_class_names
[class]);
2198 /* Make reg REGNO an additional reload reg. */
2200 potential_reload_regs
[i
] = -1;
2201 spill_regs
[n_spills
] = regno
;
2202 spill_reg_order
[regno
] = n_spills
;
2204 fprintf (dumpfile
, "Spilling reg %d.\n", regno
);
2205 SET_HARD_REG_BIT (chain
->used_spill_regs
, regno
);
2207 /* Clear off the needs we just satisfied. */
2209 chain
->need
.regs
[0][class]--;
2210 p
= reg_class_superclasses
[class];
2211 while (*p
!= LIM_REG_CLASSES
)
2212 chain
->need
.regs
[0][(int) *p
++]--;
2214 if (nongroup
&& chain
->need
.regs
[1][class] > 0)
2216 SET_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
);
2217 chain
->need
.regs
[1][class]--;
2218 p
= reg_class_superclasses
[class];
2219 while (*p
!= LIM_REG_CLASSES
)
2220 chain
->need
.regs
[1][(int) *p
++]--;
2226 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2227 data that is dead in INSN. */
2230 delete_dead_insn (insn
)
2233 rtx prev
= prev_real_insn (insn
);
2236 /* If the previous insn sets a register that dies in our insn, delete it
2238 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2239 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
2240 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2241 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2242 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2243 delete_dead_insn (prev
);
2245 PUT_CODE (insn
, NOTE
);
2246 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2247 NOTE_SOURCE_FILE (insn
) = 0;
2250 /* Modify the home of pseudo-reg I.
2251 The new home is present in reg_renumber[I].
2253 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2254 or it may be -1, meaning there is none or it is not relevant.
2255 This is used so that all pseudos spilled from a given hard reg
2256 can share one stack slot. */
2259 alter_reg (i
, from_reg
)
2263 /* When outputting an inline function, this can happen
2264 for a reg that isn't actually used. */
2265 if (regno_reg_rtx
[i
] == 0)
2268 /* If the reg got changed to a MEM at rtl-generation time,
2270 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
2273 /* Modify the reg-rtx to contain the new hard reg
2274 number or else to contain its pseudo reg number. */
2275 REGNO (regno_reg_rtx
[i
])
2276 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
2278 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2279 allocate a stack slot for it. */
2281 if (reg_renumber
[i
] < 0
2282 && REG_N_REFS (i
) > 0
2283 && reg_equiv_constant
[i
] == 0
2284 && reg_equiv_memory_loc
[i
] == 0)
2287 int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2288 int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2291 /* Each pseudo reg has an inherent size which comes from its own mode,
2292 and a total size which provides room for paradoxical subregs
2293 which refer to the pseudo reg in wider modes.
2295 We can use a slot already allocated if it provides both
2296 enough inherent space and enough total space.
2297 Otherwise, we allocate a new slot, making sure that it has no less
2298 inherent space, and no less total space, then the previous slot. */
2301 /* No known place to spill from => no slot to reuse. */
2302 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
2303 inherent_size
== total_size
? 0 : -1);
2304 if (BYTES_BIG_ENDIAN
)
2305 /* Cancel the big-endian correction done in assign_stack_local.
2306 Get the address of the beginning of the slot.
2307 This is so we can do a big-endian correction unconditionally
2309 adjust
= inherent_size
- total_size
;
2311 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2313 /* Reuse a stack slot if possible. */
2314 else if (spill_stack_slot
[from_reg
] != 0
2315 && spill_stack_slot_width
[from_reg
] >= total_size
2316 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2318 x
= spill_stack_slot
[from_reg
];
2319 /* Allocate a bigger slot. */
2322 /* Compute maximum size needed, both for inherent size
2323 and for total size. */
2324 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2326 if (spill_stack_slot
[from_reg
])
2328 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2330 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2331 if (spill_stack_slot_width
[from_reg
] > total_size
)
2332 total_size
= spill_stack_slot_width
[from_reg
];
2334 /* Make a slot with that size. */
2335 x
= assign_stack_local (mode
, total_size
,
2336 inherent_size
== total_size
? 0 : -1);
2338 if (BYTES_BIG_ENDIAN
)
2340 /* Cancel the big-endian correction done in assign_stack_local.
2341 Get the address of the beginning of the slot.
2342 This is so we can do a big-endian correction unconditionally
2344 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2346 stack_slot
= gen_rtx_MEM (mode_for_size (total_size
2349 plus_constant (XEXP (x
, 0), adjust
));
2351 spill_stack_slot
[from_reg
] = stack_slot
;
2352 spill_stack_slot_width
[from_reg
] = total_size
;
2355 /* On a big endian machine, the "address" of the slot
2356 is the address of the low part that fits its inherent mode. */
2357 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2358 adjust
+= (total_size
- inherent_size
);
2360 /* If we have any adjustment to make, or if the stack slot is the
2361 wrong mode, make a new stack slot. */
2362 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
2364 x
= gen_rtx_MEM (GET_MODE (regno_reg_rtx
[i
]),
2365 plus_constant (XEXP (x
, 0), adjust
));
2367 /* If this was shared among registers, must ensure we never
2368 set it readonly since that can cause scheduling
2369 problems. Note we would only have in this adjustment
2370 case in any event, since the code above doesn't set it. */
2373 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2376 /* Save the stack slot for later. */
2377 reg_equiv_memory_loc
[i
] = x
;
2381 /* Mark the slots in regs_ever_live for the hard regs
2382 used by pseudo-reg number REGNO. */
2385 mark_home_live (regno
)
2388 register int i
, lim
;
2389 i
= reg_renumber
[regno
];
2392 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2394 regs_ever_live
[i
++] = 1;
2397 /* This function handles the tracking of elimination offsets around branches.
2399 X is a piece of RTL being scanned.
2401 INSN is the insn that it came from, if any.
2403 INITIAL_P is non-zero if we are to set the offset to be the initial
2404 offset and zero if we are setting the offset of the label to be the
2408 set_label_offsets (x
, insn
, initial_p
)
2413 enum rtx_code code
= GET_CODE (x
);
2416 struct elim_table
*p
;
2421 if (LABEL_REF_NONLOCAL_P (x
))
2426 /* ... fall through ... */
2429 /* If we know nothing about this label, set the desired offsets. Note
2430 that this sets the offset at a label to be the offset before a label
2431 if we don't know anything about the label. This is not correct for
2432 the label after a BARRIER, but is the best guess we can make. If
2433 we guessed wrong, we will suppress an elimination that might have
2434 been possible had we been able to guess correctly. */
2436 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2438 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2439 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2440 = (initial_p
? reg_eliminate
[i
].initial_offset
2441 : reg_eliminate
[i
].offset
);
2442 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2445 /* Otherwise, if this is the definition of a label and it is
2446 preceded by a BARRIER, set our offsets to the known offset of
2450 && (tem
= prev_nonnote_insn (insn
)) != 0
2451 && GET_CODE (tem
) == BARRIER
)
2453 num_not_at_initial_offset
= 0;
2454 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2456 reg_eliminate
[i
].offset
= reg_eliminate
[i
].previous_offset
2457 = offsets_at
[CODE_LABEL_NUMBER (x
)][i
];
2458 if (reg_eliminate
[i
].can_eliminate
2459 && (reg_eliminate
[i
].offset
2460 != reg_eliminate
[i
].initial_offset
))
2461 num_not_at_initial_offset
++;
2466 /* If neither of the above cases is true, compare each offset
2467 with those previously recorded and suppress any eliminations
2468 where the offsets disagree. */
2470 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2471 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2472 != (initial_p
? reg_eliminate
[i
].initial_offset
2473 : reg_eliminate
[i
].offset
))
2474 reg_eliminate
[i
].can_eliminate
= 0;
2479 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2481 /* ... fall through ... */
2485 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2486 and hence must have all eliminations at their initial offsets. */
2487 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2488 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2489 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2494 /* Each of the labels in the address vector must be at their initial
2495 offsets. We want the first field for ADDR_VEC and the second
2496 field for ADDR_DIFF_VEC. */
2498 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2499 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2504 /* We only care about setting PC. If the source is not RETURN,
2505 IF_THEN_ELSE, or a label, disable any eliminations not at
2506 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2507 isn't one of those possibilities. For branches to a label,
2508 call ourselves recursively.
2510 Note that this can disable elimination unnecessarily when we have
2511 a non-local goto since it will look like a non-constant jump to
2512 someplace in the current function. This isn't a significant
2513 problem since such jumps will normally be when all elimination
2514 pairs are back to their initial offsets. */
2516 if (SET_DEST (x
) != pc_rtx
)
2519 switch (GET_CODE (SET_SRC (x
)))
2526 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2530 tem
= XEXP (SET_SRC (x
), 1);
2531 if (GET_CODE (tem
) == LABEL_REF
)
2532 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2533 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2536 tem
= XEXP (SET_SRC (x
), 2);
2537 if (GET_CODE (tem
) == LABEL_REF
)
2538 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2539 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2547 /* If we reach here, all eliminations must be at their initial
2548 offset because we are doing a jump to a variable address. */
2549 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2550 if (p
->offset
!= p
->initial_offset
)
2551 p
->can_eliminate
= 0;
2559 /* Used for communication between the next two function to properly share
2560 the vector for an ASM_OPERANDS. */
2562 static struct rtvec_def
*old_asm_operands_vec
, *new_asm_operands_vec
;
2564 /* Scan X and replace any eliminable registers (such as fp) with a
2565 replacement (such as sp), plus an offset.
2567 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2568 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2569 MEM, we are allowed to replace a sum of a register and the constant zero
2570 with the register, which we cannot do outside a MEM. In addition, we need
2571 to record the fact that a register is referenced outside a MEM.
2573 If INSN is an insn, it is the insn containing X. If we replace a REG
2574 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2575 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2576 the REG is being modified.
2578 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2579 That's used when we eliminate in expressions stored in notes.
2580 This means, do not set ref_outside_mem even if the reference
2583 If we see a modification to a register we know about, take the
2584 appropriate action (see case SET, below).
2586 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2587 replacements done assuming all offsets are at their initial values. If
2588 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2589 encounter, return the actual location so that find_reloads will do
2590 the proper thing. */
2593 eliminate_regs (x
, mem_mode
, insn
)
2595 enum machine_mode mem_mode
;
2598 enum rtx_code code
= GET_CODE (x
);
2599 struct elim_table
*ep
;
2622 /* This is only for the benefit of the debugging backends, which call
2623 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2624 removed after CSE. */
2625 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2626 if (GET_CODE (new) == MEM
)
2627 return XEXP (new, 0);
2633 /* First handle the case where we encounter a bare register that
2634 is eliminable. Replace it with a PLUS. */
2635 if (regno
< FIRST_PSEUDO_REGISTER
)
2637 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2639 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2642 /* Refs inside notes don't count for this purpose. */
2643 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2644 || GET_CODE (insn
) == INSN_LIST
)))
2645 ep
->ref_outside_mem
= 1;
2646 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2653 /* If this is the sum of an eliminable register and a constant, rework
2655 if (GET_CODE (XEXP (x
, 0)) == REG
2656 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2657 && CONSTANT_P (XEXP (x
, 1)))
2659 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2661 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2664 /* Refs inside notes don't count for this purpose. */
2665 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2666 || GET_CODE (insn
) == INSN_LIST
)))
2667 ep
->ref_outside_mem
= 1;
2669 /* The only time we want to replace a PLUS with a REG (this
2670 occurs when the constant operand of the PLUS is the negative
2671 of the offset) is when we are inside a MEM. We won't want
2672 to do so at other times because that would change the
2673 structure of the insn in a way that reload can't handle.
2674 We special-case the commonest situation in
2675 eliminate_regs_in_insn, so just replace a PLUS with a
2676 PLUS here, unless inside a MEM. */
2677 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2678 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2681 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2682 plus_constant (XEXP (x
, 1),
2683 ep
->previous_offset
));
2686 /* If the register is not eliminable, we are done since the other
2687 operand is a constant. */
2691 /* If this is part of an address, we want to bring any constant to the
2692 outermost PLUS. We will do this by doing register replacement in
2693 our operands and seeing if a constant shows up in one of them.
2695 We assume here this is part of an address (or a "load address" insn)
2696 since an eliminable register is not likely to appear in any other
2699 If we have (plus (eliminable) (reg)), we want to produce
2700 (plus (plus (replacement) (reg) (const))). If this was part of a
2701 normal add insn, (plus (replacement) (reg)) will be pushed as a
2702 reload. This is the desired action. */
2705 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2706 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2708 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2710 /* If one side is a PLUS and the other side is a pseudo that
2711 didn't get a hard register but has a reg_equiv_constant,
2712 we must replace the constant here since it may no longer
2713 be in the position of any operand. */
2714 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2715 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2716 && reg_renumber
[REGNO (new1
)] < 0
2717 && reg_equiv_constant
!= 0
2718 && reg_equiv_constant
[REGNO (new1
)] != 0)
2719 new1
= reg_equiv_constant
[REGNO (new1
)];
2720 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2721 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2722 && reg_renumber
[REGNO (new0
)] < 0
2723 && reg_equiv_constant
[REGNO (new0
)] != 0)
2724 new0
= reg_equiv_constant
[REGNO (new0
)];
2726 new = form_sum (new0
, new1
);
2728 /* As above, if we are not inside a MEM we do not want to
2729 turn a PLUS into something else. We might try to do so here
2730 for an addition of 0 if we aren't optimizing. */
2731 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2732 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2740 /* If this is the product of an eliminable register and a
2741 constant, apply the distribute law and move the constant out
2742 so that we have (plus (mult ..) ..). This is needed in order
2743 to keep load-address insns valid. This case is pathological.
2744 We ignore the possibility of overflow here. */
2745 if (GET_CODE (XEXP (x
, 0)) == REG
2746 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2747 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2748 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2750 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2753 /* Refs inside notes don't count for this purpose. */
2754 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2755 || GET_CODE (insn
) == INSN_LIST
)))
2756 ep
->ref_outside_mem
= 1;
2759 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2760 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2763 /* ... fall through ... */
2768 case DIV
: case UDIV
:
2769 case MOD
: case UMOD
:
2770 case AND
: case IOR
: case XOR
:
2771 case ROTATERT
: case ROTATE
:
2772 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2774 case GE
: case GT
: case GEU
: case GTU
:
2775 case LE
: case LT
: case LEU
: case LTU
:
2777 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2779 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2781 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2782 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2787 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2790 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2791 if (new != XEXP (x
, 0))
2792 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2795 /* ... fall through ... */
2798 /* Now do eliminations in the rest of the chain. If this was
2799 an EXPR_LIST, this might result in allocating more memory than is
2800 strictly needed, but it simplifies the code. */
2803 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2804 if (new != XEXP (x
, 1))
2805 return gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2813 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2814 if (ep
->to_rtx
== XEXP (x
, 0))
2816 int size
= GET_MODE_SIZE (mem_mode
);
2818 /* If more bytes than MEM_MODE are pushed, account for them. */
2819 #ifdef PUSH_ROUNDING
2820 if (ep
->to_rtx
== stack_pointer_rtx
)
2821 size
= PUSH_ROUNDING (size
);
2823 if (code
== PRE_DEC
|| code
== POST_DEC
)
2829 /* Fall through to generic unary operation case. */
2830 case STRICT_LOW_PART
:
2832 case SIGN_EXTEND
: case ZERO_EXTEND
:
2833 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2834 case FLOAT
: case FIX
:
2835 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2839 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2840 if (new != XEXP (x
, 0))
2841 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2845 /* Similar to above processing, but preserve SUBREG_WORD.
2846 Convert (subreg (mem)) to (mem) if not paradoxical.
2847 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2848 pseudo didn't get a hard reg, we must replace this with the
2849 eliminated version of the memory location because push_reloads
2850 may do the replacement in certain circumstances. */
2851 if (GET_CODE (SUBREG_REG (x
)) == REG
2852 && (GET_MODE_SIZE (GET_MODE (x
))
2853 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2854 && reg_equiv_memory_loc
!= 0
2855 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2858 new = eliminate_regs (reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))],
2861 /* If we didn't change anything, we must retain the pseudo. */
2862 if (new == reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))])
2863 new = SUBREG_REG (x
);
2866 /* In this case, we must show that the pseudo is used in this
2867 insn so that delete_output_reload will do the right thing. */
2868 if (insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
2869 && GET_CODE (insn
) != INSN_LIST
)
2870 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode
,
2873 = gen_rtx_EXPR_LIST (REG_EQUAL
, new, NULL_RTX
);
2875 /* Ensure NEW isn't shared in case we have to reload it. */
2876 new = copy_rtx (new);
2879 new = SUBREG_REG (x
);
2883 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
2885 if (new != XEXP (x
, 0))
2887 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2888 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2890 if (GET_CODE (new) == MEM
2891 && ((x_size
< new_size
2892 #ifdef WORD_REGISTER_OPERATIONS
2893 /* On these machines, combine can create rtl of the form
2894 (set (subreg:m1 (reg:m2 R) 0) ...)
2895 where m1 < m2, and expects something interesting to
2896 happen to the entire word. Moreover, it will use the
2897 (reg:m2 R) later, expecting all bits to be preserved.
2898 So if the number of words is the same, preserve the
2899 subreg so that push_reloads can see it. */
2900 && ! ((x_size
-1)/UNITS_PER_WORD
== (new_size
-1)/UNITS_PER_WORD
)
2903 || (x_size
== new_size
))
2906 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
2907 enum machine_mode mode
= GET_MODE (x
);
2909 if (BYTES_BIG_ENDIAN
)
2910 offset
+= (MIN (UNITS_PER_WORD
,
2911 GET_MODE_SIZE (GET_MODE (new)))
2912 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
2914 PUT_MODE (new, mode
);
2915 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
2919 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_WORD (x
));
2925 /* If using a register that is the source of an eliminate we still
2926 think can be performed, note it cannot be performed since we don't
2927 know how this register is used. */
2928 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2929 if (ep
->from_rtx
== XEXP (x
, 0))
2930 ep
->can_eliminate
= 0;
2932 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2933 if (new != XEXP (x
, 0))
2934 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2938 /* If clobbering a register that is the replacement register for an
2939 elimination we still think can be performed, note that it cannot
2940 be performed. Otherwise, we need not be concerned about it. */
2941 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2942 if (ep
->to_rtx
== XEXP (x
, 0))
2943 ep
->can_eliminate
= 0;
2945 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2946 if (new != XEXP (x
, 0))
2947 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2953 /* Properly handle sharing input and constraint vectors. */
2954 if (ASM_OPERANDS_INPUT_VEC (x
) != old_asm_operands_vec
)
2956 /* When we come to a new vector not seen before,
2957 scan all its elements; keep the old vector if none
2958 of them changes; otherwise, make a copy. */
2959 old_asm_operands_vec
= ASM_OPERANDS_INPUT_VEC (x
);
2960 temp_vec
= (rtx
*) alloca (XVECLEN (x
, 3) * sizeof (rtx
));
2961 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
2962 temp_vec
[i
] = eliminate_regs (ASM_OPERANDS_INPUT (x
, i
),
2965 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
2966 if (temp_vec
[i
] != ASM_OPERANDS_INPUT (x
, i
))
2969 if (i
== ASM_OPERANDS_INPUT_LENGTH (x
))
2970 new_asm_operands_vec
= old_asm_operands_vec
;
2972 new_asm_operands_vec
2973 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x
), temp_vec
);
2976 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2977 if (new_asm_operands_vec
== old_asm_operands_vec
)
2980 new = gen_rtx_ASM_OPERANDS (VOIDmode
, ASM_OPERANDS_TEMPLATE (x
),
2981 ASM_OPERANDS_OUTPUT_CONSTRAINT (x
),
2982 ASM_OPERANDS_OUTPUT_IDX (x
),
2983 new_asm_operands_vec
,
2984 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x
),
2985 ASM_OPERANDS_SOURCE_FILE (x
),
2986 ASM_OPERANDS_SOURCE_LINE (x
));
2987 new->volatil
= x
->volatil
;
2992 /* Check for setting a register that we know about. */
2993 if (GET_CODE (SET_DEST (x
)) == REG
)
2995 /* See if this is setting the replacement register for an
2998 If DEST is the hard frame pointer, we do nothing because we
2999 assume that all assignments to the frame pointer are for
3000 non-local gotos and are being done at a time when they are valid
3001 and do not disturb anything else. Some machines want to
3002 eliminate a fake argument pointer (or even a fake frame pointer)
3003 with either the real frame or the stack pointer. Assignments to
3004 the hard frame pointer must not prevent this elimination. */
3006 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3008 if (ep
->to_rtx
== SET_DEST (x
)
3009 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3011 /* If it is being incremented, adjust the offset. Otherwise,
3012 this elimination can't be done. */
3013 rtx src
= SET_SRC (x
);
3015 if (GET_CODE (src
) == PLUS
3016 && XEXP (src
, 0) == SET_DEST (x
)
3017 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
3018 ep
->offset
-= INTVAL (XEXP (src
, 1));
3020 ep
->can_eliminate
= 0;
3023 /* Now check to see we are assigning to a register that can be
3024 eliminated. If so, it must be as part of a PARALLEL, since we
3025 will not have been called if this is a single SET. So indicate
3026 that we can no longer eliminate this reg. */
3027 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3029 if (ep
->from_rtx
== SET_DEST (x
) && ep
->can_eliminate
)
3030 ep
->can_eliminate
= 0;
3033 /* Now avoid the loop below in this common case. */
3035 rtx new0
= eliminate_regs (SET_DEST (x
), 0, insn
);
3036 rtx new1
= eliminate_regs (SET_SRC (x
), 0, insn
);
3038 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3039 write a CLOBBER insn. */
3040 if (GET_CODE (SET_DEST (x
)) == REG
&& GET_CODE (new0
) == MEM
3041 && insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
3042 && GET_CODE (insn
) != INSN_LIST
)
3043 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, SET_DEST (x
)), insn
);
3045 if (new0
!= SET_DEST (x
) || new1
!= SET_SRC (x
))
3046 return gen_rtx_SET (VOIDmode
, new0
, new1
);
3052 /* This is only for the benefit of the debugging backends, which call
3053 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3054 removed after CSE. */
3055 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
3056 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
3058 /* Our only special processing is to pass the mode of the MEM to our
3059 recursive call and copy the flags. While we are here, handle this
3060 case more efficiently. */
3061 new = eliminate_regs (XEXP (x
, 0), GET_MODE (x
), insn
);
3062 if (new != XEXP (x
, 0))
3064 new = gen_rtx_MEM (GET_MODE (x
), new);
3065 new->volatil
= x
->volatil
;
3066 new->unchanging
= x
->unchanging
;
3067 new->in_struct
= x
->in_struct
;
3077 /* Process each of our operands recursively. If any have changed, make a
3079 fmt
= GET_RTX_FORMAT (code
);
3080 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3084 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
3085 if (new != XEXP (x
, i
) && ! copied
)
3087 rtx new_x
= rtx_alloc (code
);
3088 bcopy ((char *) x
, (char *) new_x
,
3089 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3090 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
3096 else if (*fmt
== 'E')
3099 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3101 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
3102 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
3104 rtvec new_v
= gen_rtvec_vv (XVECLEN (x
, i
),
3108 rtx new_x
= rtx_alloc (code
);
3109 bcopy ((char *) x
, (char *) new_x
,
3110 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3111 + (sizeof (new_x
->fld
[0])
3112 * GET_RTX_LENGTH (code
))));
3116 XVEC (x
, i
) = new_v
;
3119 XVECEXP (x
, i
, j
) = new;
3127 /* Scan INSN and eliminate all eliminable registers in it.
3129 If REPLACE is nonzero, do the replacement destructively. Also
3130 delete the insn as dead it if it is setting an eliminable register.
3132 If REPLACE is zero, do all our allocations in reload_obstack.
3134 If no eliminations were done and this insn doesn't require any elimination
3135 processing (these are not identical conditions: it might be updating sp,
3136 but not referencing fp; this needs to be seen during reload_as_needed so
3137 that the offset between fp and sp can be taken into consideration), zero
3138 is returned. Otherwise, 1 is returned. */
3141 eliminate_regs_in_insn (insn
, replace
)
3145 rtx old_body
= PATTERN (insn
);
3146 rtx old_set
= single_set (insn
);
3149 struct elim_table
*ep
;
3152 push_obstacks (&reload_obstack
, &reload_obstack
);
3154 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
3155 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3157 /* Check for setting an eliminable register. */
3158 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3159 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3161 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3162 /* If this is setting the frame pointer register to the
3163 hardware frame pointer register and this is an elimination
3164 that will be done (tested above), this insn is really
3165 adjusting the frame pointer downward to compensate for
3166 the adjustment done before a nonlocal goto. */
3167 if (ep
->from
== FRAME_POINTER_REGNUM
3168 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3170 rtx src
= SET_SRC (old_set
);
3172 rtx prev_insn
, prev_set
;
3174 if (src
== ep
->to_rtx
)
3176 else if (GET_CODE (src
) == PLUS
3177 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3178 && XEXP (src
, 1) == ep
->to_rtx
)
3179 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3180 else if (GET_CODE (src
) == PLUS
3181 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3182 && XEXP (src
, 0) == ep
->to_rtx
)
3183 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3184 else if ((prev_insn
= prev_nonnote_insn (insn
)) != 0
3185 && (prev_set
= single_set (prev_insn
)) != 0
3186 && rtx_equal_p (SET_DEST (prev_set
), src
))
3188 src
= SET_SRC (prev_set
);
3189 if (src
== ep
->to_rtx
)
3191 else if (GET_CODE (src
) == PLUS
3192 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3193 && XEXP (src
, 1) == ep
->to_rtx
)
3194 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3195 else if (GET_CODE (src
) == PLUS
3196 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3197 && XEXP (src
, 0) == ep
->to_rtx
)
3198 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3206 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3208 /* First see if this insn remains valid when we
3209 make the change. If not, keep the INSN_CODE
3210 the same and let reload fit it up. */
3211 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3212 validate_change (insn
, &SET_DEST (old_set
),
3214 if (! apply_change_group ())
3216 SET_SRC (old_set
) = src
;
3217 SET_DEST (old_set
) = ep
->to_rtx
;
3227 /* In this case this insn isn't serving a useful purpose. We
3228 will delete it in reload_as_needed once we know that this
3229 elimination is, in fact, being done.
3231 If REPLACE isn't set, we can't delete this insn, but needn't
3232 process it since it won't be used unless something changes. */
3234 delete_dead_insn (insn
);
3239 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3240 in the insn is the negative of the offset in FROM. Substitute
3241 (set (reg) (reg to)) for the insn and change its code.
3243 We have to do this here, rather than in eliminate_regs, so that we can
3244 change the insn code. */
3246 if (GET_CODE (SET_SRC (old_set
)) == PLUS
3247 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
3248 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
)
3249 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3251 if (ep
->from_rtx
== XEXP (SET_SRC (old_set
), 0)
3252 && ep
->can_eliminate
)
3254 /* We must stop at the first elimination that will be used.
3255 If this one would replace the PLUS with a REG, do it
3256 now. Otherwise, quit the loop and let eliminate_regs
3257 do its normal replacement. */
3258 if (ep
->offset
== - INTVAL (XEXP (SET_SRC (old_set
), 1)))
3260 /* We assume here that we don't need a PARALLEL of
3261 any CLOBBERs for this assignment. There's not
3262 much we can do if we do need it. */
3263 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3266 INSN_CODE (insn
) = -1;
3275 old_asm_operands_vec
= 0;
3277 /* Replace the body of this insn with a substituted form. If we changed
3278 something, return non-zero.
3280 If we are replacing a body that was a (set X (plus Y Z)), try to
3281 re-recognize the insn. We do this in case we had a simple addition
3282 but now can do this as a load-address. This saves an insn in this
3285 new_body
= eliminate_regs (old_body
, 0, replace
? insn
: NULL_RTX
);
3286 if (new_body
!= old_body
)
3288 /* If we aren't replacing things permanently and we changed something,
3289 make another copy to ensure that all the RTL is new. Otherwise
3290 things can go wrong if find_reload swaps commutative operands
3291 and one is inside RTL that has been copied while the other is not. */
3293 /* Don't copy an asm_operands because (1) there's no need and (2)
3294 copy_rtx can't do it properly when there are multiple outputs. */
3295 if (! replace
&& asm_noperands (old_body
) < 0)
3296 new_body
= copy_rtx (new_body
);
3298 /* If we had a move insn but now we don't, rerecognize it. This will
3299 cause spurious re-recognition if the old move had a PARALLEL since
3300 the new one still will, but we can't call single_set without
3301 having put NEW_BODY into the insn and the re-recognition won't
3302 hurt in this rare case. */
3304 && ((GET_CODE (SET_SRC (old_set
)) == REG
3305 && (GET_CODE (new_body
) != SET
3306 || GET_CODE (SET_SRC (new_body
)) != REG
))
3307 /* If this was a load from or store to memory, compare
3308 the MEM in recog_operand to the one in the insn. If they
3309 are not equal, then rerecognize the insn. */
3311 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3312 && SET_SRC (old_set
) != recog_operand
[1])
3313 || (GET_CODE (SET_DEST (old_set
)) == MEM
3314 && SET_DEST (old_set
) != recog_operand
[0])))
3315 /* If this was an add insn before, rerecognize. */
3316 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3318 if (! validate_change (insn
, &PATTERN (insn
), new_body
, 0))
3319 /* If recognition fails, store the new body anyway.
3320 It's normal to have recognition failures here
3321 due to bizarre memory addresses; reloading will fix them. */
3322 PATTERN (insn
) = new_body
;
3325 PATTERN (insn
) = new_body
;
3330 /* Loop through all elimination pairs. See if any have changed.
3332 We also detect a cases where register elimination cannot be done,
3333 namely, if a register would be both changed and referenced outside a MEM
3334 in the resulting insn since such an insn is often undefined and, even if
3335 not, we cannot know what meaning will be given to it. Note that it is
3336 valid to have a register used in an address in an insn that changes it
3337 (presumably with a pre- or post-increment or decrement).
3339 If anything changes, return nonzero. */
3341 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3343 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3344 ep
->can_eliminate
= 0;
3346 ep
->ref_outside_mem
= 0;
3348 if (ep
->previous_offset
!= ep
->offset
)
3353 /* If we changed something, perform elimination in REG_NOTES. This is
3354 needed even when REPLACE is zero because a REG_DEAD note might refer
3355 to a register that we eliminate and could cause a different number
3356 of spill registers to be needed in the final reload pass than in
3358 if (val
&& REG_NOTES (insn
) != 0)
3359 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3367 /* Loop through all elimination pairs.
3368 Recalculate the number not at initial offset.
3370 Compute the maximum offset (minimum offset if the stack does not
3371 grow downward) for each elimination pair. */
3374 update_eliminable_offsets ()
3376 struct elim_table
*ep
;
3378 num_not_at_initial_offset
= 0;
3379 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3381 ep
->previous_offset
= ep
->offset
;
3382 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3383 num_not_at_initial_offset
++;
3385 #ifdef STACK_GROWS_DOWNWARD
3386 ep
->max_offset
= MAX (ep
->max_offset
, ep
->offset
);
3388 ep
->max_offset
= MIN (ep
->max_offset
, ep
->offset
);
3393 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3394 replacement we currently believe is valid, mark it as not eliminable if X
3395 modifies DEST in any way other than by adding a constant integer to it.
3397 If DEST is the frame pointer, we do nothing because we assume that
3398 all assignments to the hard frame pointer are nonlocal gotos and are being
3399 done at a time when they are valid and do not disturb anything else.
3400 Some machines want to eliminate a fake argument pointer with either the
3401 frame or stack pointer. Assignments to the hard frame pointer must not
3402 prevent this elimination.
3404 Called via note_stores from reload before starting its passes to scan
3405 the insns of the function. */
3408 mark_not_eliminable (dest
, x
)
3412 register unsigned int i
;
3414 /* A SUBREG of a hard register here is just changing its mode. We should
3415 not see a SUBREG of an eliminable hard register, but check just in
3417 if (GET_CODE (dest
) == SUBREG
)
3418 dest
= SUBREG_REG (dest
);
3420 if (dest
== hard_frame_pointer_rtx
)
3423 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3424 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3425 && (GET_CODE (x
) != SET
3426 || GET_CODE (SET_SRC (x
)) != PLUS
3427 || XEXP (SET_SRC (x
), 0) != dest
3428 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3430 reg_eliminate
[i
].can_eliminate_previous
3431 = reg_eliminate
[i
].can_eliminate
= 0;
3436 /* Verify that the initial elimination offsets did not change since the
3437 last call to set_initial_elim_offsets. This is used to catch cases
3438 where something illegal happened during reload_as_needed that could
3439 cause incorrect code to be generated if we did not check for it. */
3441 verify_initial_elim_offsets ()
3445 #ifdef ELIMINABLE_REGS
3446 struct elim_table
*ep
;
3448 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3450 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3451 if (t
!= ep
->initial_offset
)
3455 INITIAL_FRAME_POINTER_OFFSET (t
);
3456 if (t
!= reg_eliminate
[0].initial_offset
)
3461 /* Reset all offsets on eliminable registers to their initial values. */
3463 set_initial_elim_offsets ()
3467 #ifdef ELIMINABLE_REGS
3468 struct elim_table
*ep
;
3470 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3472 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3473 ep
->previous_offset
= ep
->offset
3474 = ep
->max_offset
= ep
->initial_offset
;
3477 #ifdef INITIAL_FRAME_POINTER_OFFSET
3478 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate
[0].initial_offset
);
3480 if (!FRAME_POINTER_REQUIRED
)
3482 reg_eliminate
[0].initial_offset
= 0;
3484 reg_eliminate
[0].previous_offset
= reg_eliminate
[0].max_offset
3485 = reg_eliminate
[0].offset
= reg_eliminate
[0].initial_offset
;
3488 num_not_at_initial_offset
= 0;
3490 bzero ((char *) &offsets_known_at
[get_first_label_num ()], num_labels
);
3492 /* Set a known offset for each forced label to be at the initial offset
3493 of each elimination. We do this because we assume that all
3494 computed jumps occur from a location where each elimination is
3495 at its initial offset. */
3497 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3499 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3502 /* See if anything that happened changes which eliminations are valid.
3503 For example, on the Sparc, whether or not the frame pointer can
3504 be eliminated can depend on what registers have been used. We need
3505 not check some conditions again (such as flag_omit_frame_pointer)
3506 since they can't have changed. */
3509 update_eliminables (pset
)
3512 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3513 int previous_frame_pointer_needed
= frame_pointer_needed
;
3515 struct elim_table
*ep
;
3517 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3518 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3519 #ifdef ELIMINABLE_REGS
3520 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3523 ep
->can_eliminate
= 0;
3525 /* Look for the case where we have discovered that we can't replace
3526 register A with register B and that means that we will now be
3527 trying to replace register A with register C. This means we can
3528 no longer replace register C with register B and we need to disable
3529 such an elimination, if it exists. This occurs often with A == ap,
3530 B == sp, and C == fp. */
3532 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3534 struct elim_table
*op
;
3535 register int new_to
= -1;
3537 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3539 /* Find the current elimination for ep->from, if there is a
3541 for (op
= reg_eliminate
;
3542 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3543 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3549 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3551 for (op
= reg_eliminate
;
3552 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3553 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3554 op
->can_eliminate
= 0;
3558 /* See if any registers that we thought we could eliminate the previous
3559 time are no longer eliminable. If so, something has changed and we
3560 must spill the register. Also, recompute the number of eliminable
3561 registers and see if the frame pointer is needed; it is if there is
3562 no elimination of the frame pointer that we can perform. */
3564 frame_pointer_needed
= 1;
3565 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3567 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3568 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3569 frame_pointer_needed
= 0;
3571 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3573 ep
->can_eliminate_previous
= 0;
3574 SET_HARD_REG_BIT (*pset
, ep
->from
);
3579 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3580 /* If we didn't need a frame pointer last time, but we do now, spill
3581 the hard frame pointer. */
3582 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3583 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3587 /* Initialize the table of registers to eliminate. */
3591 struct elim_table
*ep
;
3593 /* Does this function require a frame pointer? */
3595 frame_pointer_needed
= (! flag_omit_frame_pointer
3596 #ifdef EXIT_IGNORE_STACK
3597 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3598 and restore sp for alloca. So we can't eliminate
3599 the frame pointer in that case. At some point,
3600 we should improve this by emitting the
3601 sp-adjusting insns for this case. */
3602 || (current_function_calls_alloca
3603 && EXIT_IGNORE_STACK
)
3605 || FRAME_POINTER_REQUIRED
);
3609 #ifdef ELIMINABLE_REGS
3610 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3612 ep
->can_eliminate
= ep
->can_eliminate_previous
3613 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3614 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3617 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3618 = ! frame_pointer_needed
;
3621 /* Count the number of eliminable registers and build the FROM and TO
3622 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3623 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3624 We depend on this. */
3625 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3627 num_eliminable
+= ep
->can_eliminate
;
3628 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3629 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3633 /* Kick all pseudos out of hard register REGNO.
3634 If DUMPFILE is nonzero, log actions taken on that file.
3636 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3637 because we found we can't eliminate some register. In the case, no pseudos
3638 are allowed to be in the register, even if they are only in a block that
3639 doesn't require spill registers, unlike the case when we are spilling this
3640 hard reg to produce another spill register.
3642 Return nonzero if any pseudos needed to be kicked out. */
3645 spill_hard_reg (regno
, dumpfile
, cant_eliminate
)
3654 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3655 regs_ever_live
[regno
] = 1;
3658 /* Spill every pseudo reg that was allocated to this reg
3659 or to something that overlaps this reg. */
3661 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3662 if (reg_renumber
[i
] >= 0
3663 && reg_renumber
[i
] <= regno
3665 + HARD_REGNO_NREGS (reg_renumber
[i
],
3666 PSEUDO_REGNO_MODE (i
))
3668 SET_REGNO_REG_SET (spilled_pseudos
, i
);
3671 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3672 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3674 ior_hard_reg_set (set1
, set2
)
3675 HARD_REG_SET
*set1
, *set2
;
3677 IOR_HARD_REG_SET (*set1
, *set2
);
3680 /* After find_reload_regs has been run for all insn that need reloads,
3681 and/or spill_hard_regs was called, this function is used to actually
3682 spill pseudo registers and try to reallocate them. It also sets up the
3683 spill_regs array for use by choose_reload_regs. */
3686 finish_spills (global
, dumpfile
)
3690 struct insn_chain
*chain
;
3691 int something_changed
= 0;
3694 /* Build the spill_regs array for the function. */
3695 /* If there are some registers still to eliminate and one of the spill regs
3696 wasn't ever used before, additional stack space may have to be
3697 allocated to store this register. Thus, we may have changed the offset
3698 between the stack and frame pointers, so mark that something has changed.
3700 One might think that we need only set VAL to 1 if this is a call-used
3701 register. However, the set of registers that must be saved by the
3702 prologue is not identical to the call-used set. For example, the
3703 register used by the call insn for the return PC is a call-used register,
3704 but must be saved by the prologue. */
3707 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3708 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3710 spill_reg_order
[i
] = n_spills
;
3711 spill_regs
[n_spills
++] = i
;
3712 if (num_eliminable
&& ! regs_ever_live
[i
])
3713 something_changed
= 1;
3714 regs_ever_live
[i
] = 1;
3717 spill_reg_order
[i
] = -1;
3719 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3720 if (REGNO_REG_SET_P (spilled_pseudos
, i
))
3722 /* Record the current hard register the pseudo is allocated to in
3723 pseudo_previous_regs so we avoid reallocating it to the same
3724 hard reg in a later pass. */
3725 if (reg_renumber
[i
] < 0)
3727 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3728 /* Mark it as no longer having a hard register home. */
3729 reg_renumber
[i
] = -1;
3730 /* We will need to scan everything again. */
3731 something_changed
= 1;
3734 /* Retry global register allocation if possible. */
3737 bzero ((char *) pseudo_forbidden_regs
, max_regno
* sizeof (HARD_REG_SET
));
3738 /* For every insn that needs reloads, set the registers used as spill
3739 regs in pseudo_forbidden_regs for every pseudo live across the
3741 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3743 EXECUTE_IF_SET_IN_REG_SET
3744 (chain
->live_before
, FIRST_PSEUDO_REGISTER
, i
,
3746 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3747 &chain
->used_spill_regs
);
3749 EXECUTE_IF_SET_IN_REG_SET
3750 (chain
->live_after
, FIRST_PSEUDO_REGISTER
, i
,
3752 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3753 &chain
->used_spill_regs
);
3757 /* Retry allocating the spilled pseudos. For each reg, merge the
3758 various reg sets that indicate which hard regs can't be used,
3759 and call retry_global_alloc.
3760 We change spill_pseudos here to only contain pseudos that did not
3761 get a new hard register. */
3762 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3763 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3765 HARD_REG_SET forbidden
;
3766 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3767 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3768 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3769 retry_global_alloc (i
, forbidden
);
3770 if (reg_renumber
[i
] >= 0)
3771 CLEAR_REGNO_REG_SET (spilled_pseudos
, i
);
3775 /* Fix up the register information in the insn chain.
3776 This involves deleting those of the spilled pseudos which did not get
3777 a new hard register home from the live_{before,after} sets. */
3778 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3780 HARD_REG_SET used_by_pseudos
;
3781 HARD_REG_SET used_by_pseudos2
;
3783 AND_COMPL_REG_SET (chain
->live_before
, spilled_pseudos
);
3784 AND_COMPL_REG_SET (chain
->live_after
, spilled_pseudos
);
3786 /* Mark any unallocated hard regs as available for spills. That
3787 makes inheritance work somewhat better. */
3788 if (chain
->need_reload
)
3790 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, chain
->live_before
);
3791 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, chain
->live_after
);
3792 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3794 /* Save the old value for the sanity test below. */
3795 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3797 compute_use_by_pseudos (&used_by_pseudos
, chain
->live_before
);
3798 compute_use_by_pseudos (&used_by_pseudos
, chain
->live_after
);
3799 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3800 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3802 /* Make sure we only enlarge the set. */
3803 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3809 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3810 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3812 int regno
= reg_renumber
[i
];
3813 if (reg_old_renumber
[i
] == regno
)
3816 alter_reg (i
, reg_old_renumber
[i
]);
3817 reg_old_renumber
[i
] = regno
;
3821 fprintf (dumpfile
, " Register %d now on stack.\n\n", i
);
3823 fprintf (dumpfile
, " Register %d now in %d.\n\n",
3824 i
, reg_renumber
[i
]);
3828 return something_changed
;
3831 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3832 Also mark any hard registers used to store user variables as
3833 forbidden from being used for spill registers. */
3836 scan_paradoxical_subregs (x
)
3841 register enum rtx_code code
= GET_CODE (x
);
3847 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
3848 && REG_USERVAR_P (x
))
3849 SET_HARD_REG_BIT (bad_spill_regs_global
, REGNO (x
));
3865 if (GET_CODE (SUBREG_REG (x
)) == REG
3866 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3867 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3868 = GET_MODE_SIZE (GET_MODE (x
));
3875 fmt
= GET_RTX_FORMAT (code
);
3876 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3879 scan_paradoxical_subregs (XEXP (x
, i
));
3880 else if (fmt
[i
] == 'E')
3883 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
3884 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3890 hard_reg_use_compare (p1p
, p2p
)
3891 const GENERIC_PTR p1p
;
3892 const GENERIC_PTR p2p
;
3894 struct hard_reg_n_uses
*p1
= (struct hard_reg_n_uses
*)p1p
;
3895 struct hard_reg_n_uses
*p2
= (struct hard_reg_n_uses
*)p2p
;
3896 int bad1
= TEST_HARD_REG_BIT (bad_spill_regs
, p1
->regno
);
3897 int bad2
= TEST_HARD_REG_BIT (bad_spill_regs
, p2
->regno
);
3899 return p1
->regno
- p2
->regno
;
3904 if (p1
->uses
> p2
->uses
)
3906 if (p1
->uses
< p2
->uses
)
3908 /* If regs are equally good, sort by regno,
3909 so that the results of qsort leave nothing to chance. */
3910 return p1
->regno
- p2
->regno
;
3913 /* Used for communication between order_regs_for_reload and count_pseudo.
3914 Used to avoid counting one pseudo twice. */
3915 static regset pseudos_counted
;
3917 /* Update the costs in N_USES, considering that pseudo REG is live. */
3919 count_pseudo (n_uses
, reg
)
3920 struct hard_reg_n_uses
*n_uses
;
3923 int r
= reg_renumber
[reg
];
3926 if (REGNO_REG_SET_P (pseudos_counted
, reg
))
3928 SET_REGNO_REG_SET (pseudos_counted
, reg
);
3933 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
3935 n_uses
[r
++].uses
+= REG_N_REFS (reg
);
3937 /* Choose the order to consider regs for use as reload registers
3938 based on how much trouble would be caused by spilling one.
3939 Store them in order of decreasing preference in potential_reload_regs. */
3942 order_regs_for_reload (chain
)
3943 struct insn_chain
*chain
;
3947 struct hard_reg_n_uses hard_reg_n_uses
[FIRST_PSEUDO_REGISTER
];
3949 pseudos_counted
= ALLOCA_REG_SET ();
3951 COPY_HARD_REG_SET (bad_spill_regs
, bad_spill_regs_global
);
3953 /* Count number of uses of each hard reg by pseudo regs allocated to it
3954 and then order them by decreasing use. */
3956 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3960 hard_reg_n_uses
[i
].regno
= i
;
3961 hard_reg_n_uses
[i
].uses
= 0;
3963 /* Test the various reasons why we can't use a register for
3964 spilling in this insn. */
3966 || REGNO_REG_SET_P (chain
->live_before
, i
)
3967 || REGNO_REG_SET_P (chain
->live_after
, i
))
3969 SET_HARD_REG_BIT (bad_spill_regs
, i
);
3973 /* Now find out which pseudos are allocated to it, and update
3975 CLEAR_REG_SET (pseudos_counted
);
3977 EXECUTE_IF_SET_IN_REG_SET
3978 (chain
->live_before
, FIRST_PSEUDO_REGISTER
, j
,
3980 count_pseudo (hard_reg_n_uses
, j
);
3982 EXECUTE_IF_SET_IN_REG_SET
3983 (chain
->live_after
, FIRST_PSEUDO_REGISTER
, j
,
3985 count_pseudo (hard_reg_n_uses
, j
);
3989 FREE_REG_SET (pseudos_counted
);
3991 /* Prefer registers not so far used, for use in temporary loading.
3992 Among them, if REG_ALLOC_ORDER is defined, use that order.
3993 Otherwise, prefer registers not preserved by calls. */
3995 #ifdef REG_ALLOC_ORDER
3996 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3998 int regno
= reg_alloc_order
[i
];
4000 if (hard_reg_n_uses
[regno
].uses
== 0
4001 && ! TEST_HARD_REG_BIT (bad_spill_regs
, regno
))
4002 potential_reload_regs
[o
++] = regno
;
4005 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4007 if (hard_reg_n_uses
[i
].uses
== 0 && call_used_regs
[i
]
4008 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
))
4009 potential_reload_regs
[o
++] = i
;
4011 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4013 if (hard_reg_n_uses
[i
].uses
== 0 && ! call_used_regs
[i
]
4014 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
))
4015 potential_reload_regs
[o
++] = i
;
4019 qsort (hard_reg_n_uses
, FIRST_PSEUDO_REGISTER
,
4020 sizeof hard_reg_n_uses
[0], hard_reg_use_compare
);
4022 /* Now add the regs that are already used,
4023 preferring those used less often. The fixed and otherwise forbidden
4024 registers will be at the end of this list. */
4026 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4027 if (hard_reg_n_uses
[i
].uses
!= 0
4028 && ! TEST_HARD_REG_BIT (bad_spill_regs
, hard_reg_n_uses
[i
].regno
))
4029 potential_reload_regs
[o
++] = hard_reg_n_uses
[i
].regno
;
4030 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4031 if (TEST_HARD_REG_BIT (bad_spill_regs
, hard_reg_n_uses
[i
].regno
))
4032 potential_reload_regs
[o
++] = hard_reg_n_uses
[i
].regno
;
4035 /* Reload pseudo-registers into hard regs around each insn as needed.
4036 Additional register load insns are output before the insn that needs it
4037 and perhaps store insns after insns that modify the reloaded pseudo reg.
4039 reg_last_reload_reg and reg_reloaded_contents keep track of
4040 which registers are already available in reload registers.
4041 We update these for the reloads that we perform,
4042 as the insns are scanned. */
4045 reload_as_needed (live_known
)
4048 struct insn_chain
*chain
;
4052 bzero ((char *) spill_reg_rtx
, sizeof spill_reg_rtx
);
4053 bzero ((char *) spill_reg_store
, sizeof spill_reg_store
);
4054 reg_last_reload_reg
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
4055 bzero ((char *) reg_last_reload_reg
, max_regno
* sizeof (rtx
));
4056 reg_has_output_reload
= (char *) alloca (max_regno
);
4057 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4059 /* Reset all offsets on eliminable registers to their initial values. */
4060 #ifdef ELIMINABLE_REGS
4061 for (i
= 0; i
< (int) NUM_ELIMINABLE_REGS
; i
++)
4063 INITIAL_ELIMINATION_OFFSET (reg_eliminate
[i
].from
, reg_eliminate
[i
].to
,
4064 reg_eliminate
[i
].initial_offset
);
4065 reg_eliminate
[i
].previous_offset
4066 = reg_eliminate
[i
].offset
= reg_eliminate
[i
].initial_offset
;
4069 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate
[0].initial_offset
);
4070 reg_eliminate
[0].previous_offset
4071 = reg_eliminate
[0].offset
= reg_eliminate
[0].initial_offset
;
4074 num_not_at_initial_offset
= 0;
4076 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4079 rtx insn
= chain
->insn
;
4080 rtx old_next
= NEXT_INSN (insn
);
4082 /* If we pass a label, copy the offsets from the label information
4083 into the current offsets of each elimination. */
4084 if (GET_CODE (insn
) == CODE_LABEL
)
4086 num_not_at_initial_offset
= 0;
4087 for (i
= 0; i
< (int) NUM_ELIMINABLE_REGS
; i
++)
4089 reg_eliminate
[i
].offset
= reg_eliminate
[i
].previous_offset
4090 = offsets_at
[CODE_LABEL_NUMBER (insn
)][i
];
4091 if (reg_eliminate
[i
].can_eliminate
4092 && (reg_eliminate
[i
].offset
4093 != reg_eliminate
[i
].initial_offset
))
4094 num_not_at_initial_offset
++;
4098 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
4100 rtx oldpat
= PATTERN (insn
);
4102 /* If this is a USE and CLOBBER of a MEM, ensure that any
4103 references to eliminable registers have been removed. */
4105 if ((GET_CODE (PATTERN (insn
)) == USE
4106 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4107 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
4108 XEXP (XEXP (PATTERN (insn
), 0), 0)
4109 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4110 GET_MODE (XEXP (PATTERN (insn
), 0)),
4113 /* If we need to do register elimination processing, do so.
4114 This might delete the insn, in which case we are done. */
4115 if (num_eliminable
&& chain
->need_elim
)
4117 eliminate_regs_in_insn (insn
, 1);
4118 if (GET_CODE (insn
) == NOTE
)
4120 update_eliminable_offsets ();
4125 /* If need_elim is nonzero but need_reload is zero, one might think
4126 that we could simply set n_reloads to 0. However, find_reloads
4127 could have done some manipulation of the insn (such as swapping
4128 commutative operands), and these manipulations are lost during
4129 the first pass for every insn that needs register elimination.
4130 So the actions of find_reloads must be redone here. */
4132 if (! chain
->need_elim
&& ! chain
->need_reload
4133 && ! chain
->need_operand_change
)
4135 /* First find the pseudo regs that must be reloaded for this insn.
4136 This info is returned in the tables reload_... (see reload.h).
4137 Also modify the body of INSN by substituting RELOAD
4138 rtx's for those pseudo regs. */
4141 bzero (reg_has_output_reload
, max_regno
);
4142 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4144 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4148 if (num_eliminable
&& chain
->need_elim
)
4149 update_eliminable_offsets ();
4153 rtx next
= NEXT_INSN (insn
);
4156 prev
= PREV_INSN (insn
);
4158 /* Now compute which reload regs to reload them into. Perhaps
4159 reusing reload regs from previous insns, or else output
4160 load insns to reload them. Maybe output store insns too.
4161 Record the choices of reload reg in reload_reg_rtx. */
4162 choose_reload_regs (chain
);
4164 /* Merge any reloads that we didn't combine for fear of
4165 increasing the number of spill registers needed but now
4166 discover can be safely merged. */
4167 if (SMALL_REGISTER_CLASSES
)
4168 merge_assigned_reloads (insn
);
4170 /* Generate the insns to reload operands into or out of
4171 their reload regs. */
4172 emit_reload_insns (chain
);
4174 /* Substitute the chosen reload regs from reload_reg_rtx
4175 into the insn's body (or perhaps into the bodies of other
4176 load and store insn that we just made for reloading
4177 and that we moved the structure into). */
4180 /* If this was an ASM, make sure that all the reload insns
4181 we have generated are valid. If not, give an error
4184 if (asm_noperands (PATTERN (insn
)) >= 0)
4185 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4186 if (p
!= insn
&& GET_RTX_CLASS (GET_CODE (p
)) == 'i'
4187 && (recog_memoized (p
) < 0
4188 || (insn_extract (p
),
4189 ! constrain_operands (INSN_CODE (p
), 1))))
4191 error_for_asm (insn
,
4192 "`asm' operand requires impossible reload");
4194 NOTE_SOURCE_FILE (p
) = 0;
4195 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
4198 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4199 is no longer validly lying around to save a future reload.
4200 Note that this does not detect pseudos that were reloaded
4201 for this insn in order to be stored in
4202 (obeying register constraints). That is correct; such reload
4203 registers ARE still valid. */
4204 note_stores (oldpat
, forget_old_reloads_1
);
4206 /* There may have been CLOBBER insns placed after INSN. So scan
4207 between INSN and NEXT and use them to forget old reloads. */
4208 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4209 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
4210 note_stores (PATTERN (x
), forget_old_reloads_1
);
4213 /* Likewise for regs altered by auto-increment in this insn.
4214 REG_INC notes have been changed by reloading:
4215 find_reloads_address_1 records substitutions for them,
4216 which have been performed by subst_reloads above. */
4217 for (i
= n_reloads
- 1; i
>= 0; i
--)
4219 rtx in_reg
= reload_in_reg
[i
];
4222 enum rtx_code code
= GET_CODE (in_reg
);
4223 /* PRE_INC / PRE_DEC will have the reload register ending up
4224 with the same value as the stack slot, but that doesn't
4225 hold true for POST_INC / POST_DEC. Either we have to
4226 convert the memory access to a true POST_INC / POST_DEC,
4227 or we can't use the reload register for inheritance. */
4228 if ((code
== POST_INC
|| code
== POST_DEC
)
4229 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4230 REGNO (reload_reg_rtx
[i
]))
4231 /* Make sure it is the inc/dec pseudo, and not
4232 some other (e.g. output operand) pseudo. */
4233 && (reg_reloaded_contents
[REGNO (reload_reg_rtx
[i
])]
4234 == REGNO (XEXP (in_reg
, 0))))
4237 rtx reload_reg
= reload_reg_rtx
[i
];
4238 enum machine_mode mode
= GET_MODE (reload_reg
);
4242 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4244 /* We really want to ignore REG_INC notes here, so
4245 use PATTERN (p) as argument to reg_set_p . */
4246 if (reg_set_p (reload_reg
, PATTERN (p
)))
4248 n
= count_occurrences (PATTERN (p
), reload_reg
);
4252 n
= validate_replace_rtx (reload_reg
,
4253 gen_rtx (code
, mode
,
4258 REG_NOTES (p
) = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4261 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
);
4265 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4266 /* Likewise for regs altered by auto-increment in this insn.
4267 But note that the reg-notes are not changed by reloading:
4268 they still contain the pseudo-regs, not the spill regs. */
4269 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4270 if (REG_NOTE_KIND (x
) == REG_INC
)
4272 /* See if this pseudo reg was reloaded in this insn.
4273 If so, its last-reload info is still valid
4274 because it is based on this insn's reload. */
4275 for (i
= 0; i
< n_reloads
; i
++)
4276 if (reload_out
[i
] == XEXP (x
, 0))
4280 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
);
4285 /* A reload reg's contents are unknown after a label. */
4286 if (GET_CODE (insn
) == CODE_LABEL
)
4287 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4289 /* Don't assume a reload reg is still good after a call insn
4290 if it is a call-used reg. */
4291 else if (GET_CODE (insn
) == CALL_INSN
)
4292 AND_COMPL_HARD_REG_SET(reg_reloaded_valid
, call_used_reg_set
);
4294 /* In case registers overlap, allow certain insns to invalidate
4295 particular hard registers. */
4297 #ifdef INSN_CLOBBERS_REGNO_P
4298 for (i
= 0 ; i
< FIRST_PSEUDO_REGISTER
; i
++)
4299 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
4300 && INSN_CLOBBERS_REGNO_P (insn
, i
))
4301 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
);
4310 /* Discard all record of any value reloaded from X,
4311 or reloaded in X from someplace else;
4312 unless X is an output reload reg of the current insn.
4314 X may be a hard reg (the reload reg)
4315 or it may be a pseudo reg that was reloaded from. */
4318 forget_old_reloads_1 (x
, ignored
)
4320 rtx ignored ATTRIBUTE_UNUSED
;
4326 /* note_stores does give us subregs of hard regs. */
4327 while (GET_CODE (x
) == SUBREG
)
4329 offset
+= SUBREG_WORD (x
);
4333 if (GET_CODE (x
) != REG
)
4336 regno
= REGNO (x
) + offset
;
4338 if (regno
>= FIRST_PSEUDO_REGISTER
)
4343 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4344 /* Storing into a spilled-reg invalidates its contents.
4345 This can happen if a block-local pseudo is allocated to that reg
4346 and it wasn't spilled because this block's total need is 0.
4347 Then some insn might have an optional reload and use this reg. */
4348 for (i
= 0; i
< nr
; i
++)
4349 /* But don't do this if the reg actually serves as an output
4350 reload reg in the current instruction. */
4352 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4353 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4356 /* Since value of X has changed,
4357 forget any value previously copied from it. */
4360 /* But don't forget a copy if this is the output reload
4361 that establishes the copy's validity. */
4362 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4363 reg_last_reload_reg
[regno
+ nr
] = 0;
4366 /* For each reload, the mode of the reload register. */
4367 static enum machine_mode reload_mode
[MAX_RELOADS
];
4369 /* For each reload, the largest number of registers it will require. */
4370 static int reload_nregs
[MAX_RELOADS
];
4372 /* Comparison function for qsort to decide which of two reloads
4373 should be handled first. *P1 and *P2 are the reload numbers. */
4376 reload_reg_class_lower (r1p
, r2p
)
4377 const GENERIC_PTR r1p
;
4378 const GENERIC_PTR r2p
;
4380 register int r1
= *(short *)r1p
, r2
= *(short *)r2p
;
4383 /* Consider required reloads before optional ones. */
4384 t
= reload_optional
[r1
] - reload_optional
[r2
];
4388 /* Count all solitary classes before non-solitary ones. */
4389 t
= ((reg_class_size
[(int) reload_reg_class
[r2
]] == 1)
4390 - (reg_class_size
[(int) reload_reg_class
[r1
]] == 1));
4394 /* Aside from solitaires, consider all multi-reg groups first. */
4395 t
= reload_nregs
[r2
] - reload_nregs
[r1
];
4399 /* Consider reloads in order of increasing reg-class number. */
4400 t
= (int) reload_reg_class
[r1
] - (int) reload_reg_class
[r2
];
4404 /* If reloads are equally urgent, sort by reload number,
4405 so that the results of qsort leave nothing to chance. */
4409 /* The following HARD_REG_SETs indicate when each hard register is
4410 used for a reload of various parts of the current insn. */
4412 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4413 static HARD_REG_SET reload_reg_used
;
4414 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4415 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4416 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4417 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4418 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4419 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4420 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4421 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4422 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4423 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4424 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4425 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4426 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4427 static HARD_REG_SET reload_reg_used_in_op_addr
;
4428 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4429 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4430 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4431 static HARD_REG_SET reload_reg_used_in_insn
;
4432 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4433 static HARD_REG_SET reload_reg_used_in_other_addr
;
4435 /* If reg is in use as a reload reg for any sort of reload. */
4436 static HARD_REG_SET reload_reg_used_at_all
;
4438 /* If reg is use as an inherited reload. We just mark the first register
4440 static HARD_REG_SET reload_reg_used_for_inherit
;
4442 /* Records which hard regs are allocated to a pseudo during any point of the
4444 static HARD_REG_SET reg_used_by_pseudo
;
4446 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4447 TYPE. MODE is used to indicate how many consecutive regs are
4451 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4454 enum reload_type type
;
4455 enum machine_mode mode
;
4457 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4460 for (i
= regno
; i
< nregs
+ regno
; i
++)
4465 SET_HARD_REG_BIT (reload_reg_used
, i
);
4468 case RELOAD_FOR_INPUT_ADDRESS
:
4469 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4472 case RELOAD_FOR_INPADDR_ADDRESS
:
4473 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4476 case RELOAD_FOR_OUTPUT_ADDRESS
:
4477 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4480 case RELOAD_FOR_OUTADDR_ADDRESS
:
4481 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4484 case RELOAD_FOR_OPERAND_ADDRESS
:
4485 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4488 case RELOAD_FOR_OPADDR_ADDR
:
4489 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4492 case RELOAD_FOR_OTHER_ADDRESS
:
4493 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4496 case RELOAD_FOR_INPUT
:
4497 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4500 case RELOAD_FOR_OUTPUT
:
4501 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4504 case RELOAD_FOR_INSN
:
4505 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4509 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4513 /* Similarly, but show REGNO is no longer in use for a reload. */
4516 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4519 enum reload_type type
;
4520 enum machine_mode mode
;
4522 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4523 int start_regno
, end_regno
;
4525 /* A complication is that for some reload types, inheritance might
4526 allow multiple reloads of the same types to share a reload register.
4527 We set check_opnum if we have to check only reloads with the same
4528 operand number, and check_any if we have to check all reloads. */
4529 int check_opnum
= 0;
4531 HARD_REG_SET
*used_in_set
;
4536 used_in_set
= &reload_reg_used
;
4539 case RELOAD_FOR_INPUT_ADDRESS
:
4540 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4543 case RELOAD_FOR_INPADDR_ADDRESS
:
4545 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4548 case RELOAD_FOR_OUTPUT_ADDRESS
:
4549 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4552 case RELOAD_FOR_OUTADDR_ADDRESS
:
4554 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4557 case RELOAD_FOR_OPERAND_ADDRESS
:
4558 used_in_set
= &reload_reg_used_in_op_addr
;
4561 case RELOAD_FOR_OPADDR_ADDR
:
4563 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4566 case RELOAD_FOR_OTHER_ADDRESS
:
4567 used_in_set
= &reload_reg_used_in_other_addr
;
4571 case RELOAD_FOR_INPUT
:
4572 used_in_set
= &reload_reg_used_in_input
[opnum
];
4575 case RELOAD_FOR_OUTPUT
:
4576 used_in_set
= &reload_reg_used_in_output
[opnum
];
4579 case RELOAD_FOR_INSN
:
4580 used_in_set
= &reload_reg_used_in_insn
;
4585 /* We resolve conflicts with remaining reloads of the same type by
4586 excluding the intervals of of reload registers by them from the
4587 interval of freed reload registers. Since we only keep track of
4588 one set of interval bounds, we might have to exclude somewhat
4589 more then what would be necessary if we used a HARD_REG_SET here.
4590 But this should only happen very infrequently, so there should
4591 be no reason to worry about it. */
4593 start_regno
= regno
;
4594 end_regno
= regno
+ nregs
;
4595 if (check_opnum
|| check_any
)
4597 for (i
= n_reloads
- 1; i
>= 0; i
--)
4599 if (reload_when_needed
[i
] == type
4600 && (check_any
|| reload_opnum
[i
] == opnum
)
4601 && reload_reg_rtx
[i
])
4603 int conflict_start
= true_regnum (reload_reg_rtx
[i
]);
4606 + HARD_REGNO_NREGS (conflict_start
, reload_mode
[i
]));
4608 /* If there is an overlap with the first to-be-freed register,
4609 adjust the interval start. */
4610 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4611 start_regno
= conflict_end
;
4612 /* Otherwise, if there is a conflict with one of the other
4613 to-be-freed registers, adjust the interval end. */
4614 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4615 end_regno
= conflict_start
;
4619 for (i
= start_regno
; i
< end_regno
; i
++)
4620 CLEAR_HARD_REG_BIT (*used_in_set
, i
);
4623 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4624 specified by OPNUM and TYPE. */
4627 reload_reg_free_p (regno
, opnum
, type
)
4630 enum reload_type type
;
4634 /* In use for a RELOAD_OTHER means it's not available for anything. */
4635 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4641 /* In use for anything means we can't use it for RELOAD_OTHER. */
4642 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4643 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4644 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4647 for (i
= 0; i
< reload_n_operands
; i
++)
4648 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4649 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4650 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4651 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4652 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4653 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4658 case RELOAD_FOR_INPUT
:
4659 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4660 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4663 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4666 /* If it is used for some other input, can't use it. */
4667 for (i
= 0; i
< reload_n_operands
; i
++)
4668 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4671 /* If it is used in a later operand's address, can't use it. */
4672 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4673 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4674 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4679 case RELOAD_FOR_INPUT_ADDRESS
:
4680 /* Can't use a register if it is used for an input address for this
4681 operand or used as an input in an earlier one. */
4682 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4683 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4686 for (i
= 0; i
< opnum
; i
++)
4687 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4692 case RELOAD_FOR_INPADDR_ADDRESS
:
4693 /* Can't use a register if it is used for an input address
4694 for this operand or used as an input in an earlier
4696 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4699 for (i
= 0; i
< opnum
; i
++)
4700 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4705 case RELOAD_FOR_OUTPUT_ADDRESS
:
4706 /* Can't use a register if it is used for an output address for this
4707 operand or used as an output in this or a later operand. */
4708 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4711 for (i
= opnum
; i
< reload_n_operands
; i
++)
4712 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4717 case RELOAD_FOR_OUTADDR_ADDRESS
:
4718 /* Can't use a register if it is used for an output address
4719 for this operand or used as an output in this or a
4721 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4724 for (i
= opnum
; i
< reload_n_operands
; i
++)
4725 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4730 case RELOAD_FOR_OPERAND_ADDRESS
:
4731 for (i
= 0; i
< reload_n_operands
; i
++)
4732 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4735 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4736 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4738 case RELOAD_FOR_OPADDR_ADDR
:
4739 for (i
= 0; i
< reload_n_operands
; i
++)
4740 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4743 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4745 case RELOAD_FOR_OUTPUT
:
4746 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4747 outputs, or an operand address for this or an earlier output. */
4748 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4751 for (i
= 0; i
< reload_n_operands
; i
++)
4752 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4755 for (i
= 0; i
<= opnum
; i
++)
4756 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4757 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4762 case RELOAD_FOR_INSN
:
4763 for (i
= 0; i
< reload_n_operands
; i
++)
4764 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4765 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4768 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4769 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4771 case RELOAD_FOR_OTHER_ADDRESS
:
4772 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4777 /* Return 1 if the value in reload reg REGNO, as used by a reload
4778 needed for the part of the insn specified by OPNUM and TYPE,
4779 is not in use for a reload in any prior part of the insn.
4781 We can assume that the reload reg was already tested for availability
4782 at the time it is needed, and we should not check this again,
4783 in case the reg has already been marked in use.
4785 However, if EQUIV is set, we are checking the availability of a register
4786 holding an equivalence to the value to be loaded into the reload register,
4787 not the availability of the reload register itself.
4789 This is still less stringent than what reload_reg_free_p checks; for
4790 example, compare the checks for RELOAD_OTHER. */
4793 reload_reg_free_before_p (regno
, opnum
, type
, equiv
)
4796 enum reload_type type
;
4801 /* The code to handle EQUIV below is wrong.
4803 If we wnat to know if a value in a particular reload register is available
4804 at a particular point in time during reloading, we must check *all*
4805 prior reloads to see if they clobber the value.
4807 Note this is significantly different from determining when a register is
4808 free for usage in a reload!
4810 This change is temporary. It will go away. */
4816 case RELOAD_FOR_OTHER_ADDRESS
:
4817 /* These always come first. */
4818 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
))
4823 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4825 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4827 /* If this use is for part of the insn,
4828 check the reg is not in use for any prior part. It is tempting
4829 to try to do this by falling through from objecs that occur
4830 later in the insn to ones that occur earlier, but that will not
4831 correctly take into account the fact that here we MUST ignore
4832 things that would prevent the register from being allocated in
4833 the first place, since we know that it was allocated. */
4835 case RELOAD_FOR_OUTPUT_ADDRESS
:
4837 && TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4839 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */
4840 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4842 /* ... fall through ... */
4843 case RELOAD_FOR_OUTADDR_ADDRESS
:
4845 && (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
)
4846 || TEST_HARD_REG_BIT (reload_reg_used
, regno
)))
4848 /* Earlier reloads are for earlier outputs or their addresses,
4849 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4850 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4852 for (i
= 0; i
< opnum
; i
++)
4853 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4854 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4857 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4860 for (i
= 0; i
< reload_n_operands
; i
++)
4861 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4862 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4863 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4864 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4867 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4868 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4869 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4870 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4872 case RELOAD_FOR_OUTPUT
:
4873 case RELOAD_FOR_INSN
:
4874 /* There is no reason to call this function for output reloads, thus
4875 anything we'd put here wouldn't be tested. So just abort. */
4878 case RELOAD_FOR_OPERAND_ADDRESS
:
4879 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4882 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
4883 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4886 /* ... fall through ... */
4888 case RELOAD_FOR_OPADDR_ADDR
:
4891 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
4892 || TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4894 for (i
= 0; i
< reload_n_operands
; i
++)
4895 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4898 /* These can't conflict with inputs, or each other, so all we have to
4899 test is input addresses and the addresses of OTHER items. */
4901 for (i
= 0; i
< reload_n_operands
; i
++)
4902 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4903 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4906 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4908 case RELOAD_FOR_INPUT
:
4909 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4912 /* The only things earlier are the address for this and
4913 earlier inputs, other inputs (which we know we don't conflict
4914 with), and addresses of RELOAD_OTHER objects.
4915 We can ignore the conflict with addresses of this operand, since
4916 when we inherit this operand, its address reloads are discarded. */
4918 for (i
= 0; i
< opnum
; i
++)
4919 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4920 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4923 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4925 case RELOAD_FOR_INPUT_ADDRESS
:
4926 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */
4927 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4929 /* ... fall through ... */
4930 case RELOAD_FOR_INPADDR_ADDRESS
:
4931 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4934 /* Similarly, all we have to check is for use in earlier inputs'
4936 for (i
= 0; i
< opnum
; i
++)
4937 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4938 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4941 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4946 /* Return 1 if the value in reload reg REGNO, as used by a reload
4947 needed for the part of the insn specified by OPNUM and TYPE,
4948 is still available in REGNO at the end of the insn.
4950 We can assume that the reload reg was already tested for availability
4951 at the time it is needed, and we should not check this again,
4952 in case the reg has already been marked in use. */
4955 reload_reg_reaches_end_p (regno
, opnum
, type
)
4958 enum reload_type type
;
4965 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4966 its value must reach the end. */
4969 /* If this use is for part of the insn,
4970 its value reaches if no subsequent part uses the same register.
4971 Just like the above function, don't try to do this with lots
4974 case RELOAD_FOR_OTHER_ADDRESS
:
4975 /* Here we check for everything else, since these don't conflict
4976 with anything else and everything comes later. */
4978 for (i
= 0; i
< reload_n_operands
; i
++)
4979 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4980 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4981 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4982 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4983 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4984 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4987 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4988 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4989 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4991 case RELOAD_FOR_INPUT_ADDRESS
:
4992 case RELOAD_FOR_INPADDR_ADDRESS
:
4993 /* Similar, except that we check only for this and subsequent inputs
4994 and the address of only subsequent inputs and we do not need
4995 to check for RELOAD_OTHER objects since they are known not to
4998 for (i
= opnum
; i
< reload_n_operands
; i
++)
4999 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5002 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5003 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5004 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5007 for (i
= 0; i
< reload_n_operands
; i
++)
5008 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5009 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5010 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5013 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5016 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5017 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
5019 case RELOAD_FOR_INPUT
:
5020 /* Similar to input address, except we start at the next operand for
5021 both input and input address and we do not check for
5022 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5025 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5026 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5027 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5028 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5031 /* ... fall through ... */
5033 case RELOAD_FOR_OPERAND_ADDRESS
:
5034 /* Check outputs and their addresses. */
5036 for (i
= 0; i
< reload_n_operands
; i
++)
5037 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5038 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5039 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5044 case RELOAD_FOR_OPADDR_ADDR
:
5045 for (i
= 0; i
< reload_n_operands
; i
++)
5046 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5047 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5048 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5051 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5052 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
5054 case RELOAD_FOR_INSN
:
5055 /* These conflict with other outputs with RELOAD_OTHER. So
5056 we need only check for output addresses. */
5060 /* ... fall through ... */
5062 case RELOAD_FOR_OUTPUT
:
5063 case RELOAD_FOR_OUTPUT_ADDRESS
:
5064 case RELOAD_FOR_OUTADDR_ADDRESS
:
5065 /* We already know these can't conflict with a later output. So the
5066 only thing to check are later output addresses. */
5067 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5068 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5069 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5078 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5081 This function uses the same algorithm as reload_reg_free_p above. */
5084 reloads_conflict (r1
, r2
)
5087 enum reload_type r1_type
= reload_when_needed
[r1
];
5088 enum reload_type r2_type
= reload_when_needed
[r2
];
5089 int r1_opnum
= reload_opnum
[r1
];
5090 int r2_opnum
= reload_opnum
[r2
];
5092 /* RELOAD_OTHER conflicts with everything. */
5093 if (r2_type
== RELOAD_OTHER
)
5096 /* Otherwise, check conflicts differently for each type. */
5100 case RELOAD_FOR_INPUT
:
5101 return (r2_type
== RELOAD_FOR_INSN
5102 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5103 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5104 || r2_type
== RELOAD_FOR_INPUT
5105 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5106 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5107 && r2_opnum
> r1_opnum
));
5109 case RELOAD_FOR_INPUT_ADDRESS
:
5110 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5111 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5113 case RELOAD_FOR_INPADDR_ADDRESS
:
5114 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5115 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5117 case RELOAD_FOR_OUTPUT_ADDRESS
:
5118 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5119 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5121 case RELOAD_FOR_OUTADDR_ADDRESS
:
5122 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5123 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5125 case RELOAD_FOR_OPERAND_ADDRESS
:
5126 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5127 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5129 case RELOAD_FOR_OPADDR_ADDR
:
5130 return (r2_type
== RELOAD_FOR_INPUT
5131 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5133 case RELOAD_FOR_OUTPUT
:
5134 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5135 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5136 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5137 && r2_opnum
>= r1_opnum
));
5139 case RELOAD_FOR_INSN
:
5140 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5141 || r2_type
== RELOAD_FOR_INSN
5142 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5144 case RELOAD_FOR_OTHER_ADDRESS
:
5145 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5155 /* Vector of reload-numbers showing the order in which the reloads should
5157 short reload_order
[MAX_RELOADS
];
5159 /* Indexed by reload number, 1 if incoming value
5160 inherited from previous insns. */
5161 char reload_inherited
[MAX_RELOADS
];
5163 /* For an inherited reload, this is the insn the reload was inherited from,
5164 if we know it. Otherwise, this is 0. */
5165 rtx reload_inheritance_insn
[MAX_RELOADS
];
5167 /* If non-zero, this is a place to get the value of the reload,
5168 rather than using reload_in. */
5169 rtx reload_override_in
[MAX_RELOADS
];
5171 /* For each reload, the hard register number of the register used,
5172 or -1 if we did not need a register for this reload. */
5173 int reload_spill_index
[MAX_RELOADS
];
5175 /* Return 1 if the value in reload reg REGNO, as used by a reload
5176 needed for the part of the insn specified by OPNUM and TYPE,
5177 may be used to load VALUE into it.
5179 Other read-only reloads with the same value do not conflict
5180 unless OUT is non-zero and these other reloads have to live while
5181 output reloads live.
5183 RELOADNUM is the number of the reload we want to load this value for;
5184 a reload does not conflict with itself.
5186 The caller has to make sure that there is no conflict with the return
5189 reload_reg_free_for_value_p (regno
, opnum
, type
, value
, out
, reloadnum
)
5192 enum reload_type type
;
5199 /* We use some pseudo 'time' value to check if the lifetimes of the
5200 new register use would overlap with the one of a previous reload
5201 that is not read-only or uses a different value.
5202 The 'time' used doesn't have to be linear in any shape or form, just
5204 Some reload types use different 'buckets' for each operand.
5205 So there are MAX_RECOG_OPERANDS different time values for each
5207 We compute TIME1 as the time when the register for the prospective
5208 new reload ceases to be live, and TIME2 for each existing
5209 reload as the time when that the reload register of that reload
5211 Where there is little to be gained by exact lifetime calculations,
5212 we just make conservative assumptions, i.e. a longer lifetime;
5213 this is done in the 'default:' cases. */
5216 case RELOAD_FOR_OTHER_ADDRESS
:
5219 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5220 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5221 respectively, to the time values for these, we get distinct time
5222 values. To get distinct time values for each operand, we have to
5223 multiply opnum by at least three. We round that up to four because
5224 multiply by four is often cheaper. */
5225 case RELOAD_FOR_INPADDR_ADDRESS
:
5226 time1
= opnum
* 4 + 1;
5228 case RELOAD_FOR_INPUT_ADDRESS
:
5229 time1
= opnum
* 4 + 2;
5231 case RELOAD_FOR_OPADDR_ADDR
:
5232 /* opnum * 4 + 3 < opnum * 4 + 4
5233 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5234 time1
= MAX_RECOG_OPERANDS
* 4;
5236 case RELOAD_FOR_INPUT
:
5237 /* All RELOAD_FOR_INPUT reloads remain live till just before the
5238 instruction is executed. */
5239 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5241 case RELOAD_FOR_OPERAND_ADDRESS
:
5242 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5244 time1
= MAX_RECOG_OPERANDS
* 4 + 2;
5246 case RELOAD_FOR_OUTPUT_ADDRESS
:
5247 time1
= MAX_RECOG_OPERANDS
* 4 + 3 + opnum
;
5250 time1
= MAX_RECOG_OPERANDS
* 5 + 3;
5253 for (i
= 0; i
< n_reloads
; i
++)
5255 rtx reg
= reload_reg_rtx
[i
];
5256 if (reg
&& GET_CODE (reg
) == REG
5257 && ((unsigned) regno
- true_regnum (reg
)
5258 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned)1)
5262 && reload_when_needed
[i
] != RELOAD_FOR_INPUT
5263 && reload_when_needed
[i
] != RELOAD_FOR_INPUT_ADDRESS
5264 && reload_when_needed
[i
] != RELOAD_FOR_INPADDR_ADDRESS
)
5266 if (! reload_in
[i
] || ! rtx_equal_p (reload_in
[i
], value
)
5270 switch (reload_when_needed
[i
])
5272 case RELOAD_FOR_OTHER_ADDRESS
:
5275 case RELOAD_FOR_INPADDR_ADDRESS
:
5276 /* find_reloads makes sure that a
5277 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5278 by at most one - the first -
5279 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5280 address reload is inherited, the address address reload
5281 goes away, so we can ignore this conflict. */
5282 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1)
5284 time2
= reload_opnum
[i
] * 4 + 1;
5286 case RELOAD_FOR_INPUT_ADDRESS
:
5287 time2
= reload_opnum
[i
] * 4 + 2;
5289 case RELOAD_FOR_INPUT
:
5290 time2
= reload_opnum
[i
] * 4 + 3;
5292 case RELOAD_FOR_OPADDR_ADDR
:
5293 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1)
5295 time2
= MAX_RECOG_OPERANDS
* 4;
5297 case RELOAD_FOR_OPERAND_ADDRESS
:
5298 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5300 case RELOAD_FOR_OUTPUT
:
5301 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5302 instruction is executed. */
5303 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5305 case RELOAD_FOR_OUTADDR_ADDRESS
:
5306 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1)
5309 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the
5310 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */
5311 case RELOAD_FOR_OUTPUT_ADDRESS
:
5312 time2
= MAX_RECOG_OPERANDS
* 4 + 3 + reload_opnum
[i
];
5315 if (! reload_in
[i
] || rtx_equal_p (reload_in
[i
], value
))
5317 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5331 /* Find a spill register to use as a reload register for reload R.
5332 LAST_RELOAD is non-zero if this is the last reload for the insn being
5335 Set reload_reg_rtx[R] to the register allocated.
5337 If NOERROR is nonzero, we return 1 if successful,
5338 or 0 if we couldn't find a spill reg and we didn't change anything. */
5341 allocate_reload_reg (chain
, r
, last_reload
, noerror
)
5342 struct insn_chain
*chain
;
5347 rtx insn
= chain
->insn
;
5348 int i
, pass
, count
, regno
;
5351 /* If we put this reload ahead, thinking it is a group,
5352 then insist on finding a group. Otherwise we can grab a
5353 reg that some other reload needs.
5354 (That can happen when we have a 68000 DATA_OR_FP_REG
5355 which is a group of data regs or one fp reg.)
5356 We need not be so restrictive if there are no more reloads
5359 ??? Really it would be nicer to have smarter handling
5360 for that kind of reg class, where a problem like this is normal.
5361 Perhaps those classes should be avoided for reloading
5362 by use of more alternatives. */
5364 int force_group
= reload_nregs
[r
] > 1 && ! last_reload
;
5366 /* If we want a single register and haven't yet found one,
5367 take any reg in the right class and not in use.
5368 If we want a consecutive group, here is where we look for it.
5370 We use two passes so we can first look for reload regs to
5371 reuse, which are already in use for other reloads in this insn,
5372 and only then use additional registers.
5373 I think that maximizing reuse is needed to make sure we don't
5374 run out of reload regs. Suppose we have three reloads, and
5375 reloads A and B can share regs. These need two regs.
5376 Suppose A and B are given different regs.
5377 That leaves none for C. */
5378 for (pass
= 0; pass
< 2; pass
++)
5380 /* I is the index in spill_regs.
5381 We advance it round-robin between insns to use all spill regs
5382 equally, so that inherited reloads have a chance
5383 of leapfrogging each other. Don't do this, however, when we have
5384 group needs and failure would be fatal; if we only have a relatively
5385 small number of spill registers, and more than one of them has
5386 group needs, then by starting in the middle, we may end up
5387 allocating the first one in such a way that we are not left with
5388 sufficient groups to handle the rest. */
5390 if (noerror
|| ! force_group
)
5395 for (count
= 0; count
< n_spills
; count
++)
5397 int class = (int) reload_reg_class
[r
];
5403 regnum
= spill_regs
[i
];
5405 if ((reload_reg_free_p (regnum
, reload_opnum
[r
],
5406 reload_when_needed
[r
])
5408 /* We check reload_reg_used to make sure we
5409 don't clobber the return register. */
5410 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5411 && reload_reg_free_for_value_p (regnum
,
5413 reload_when_needed
[r
],
5416 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5417 && HARD_REGNO_MODE_OK (regnum
, reload_mode
[r
])
5418 /* Look first for regs to share, then for unshared. But
5419 don't share regs used for inherited reloads; they are
5420 the ones we want to preserve. */
5422 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5424 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5427 int nr
= HARD_REGNO_NREGS (regnum
, reload_mode
[r
]);
5428 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5429 (on 68000) got us two FP regs. If NR is 1,
5430 we would reject both of them. */
5432 nr
= CLASS_MAX_NREGS (reload_reg_class
[r
], reload_mode
[r
]);
5433 /* If we need only one reg, we have already won. */
5436 /* But reject a single reg if we demand a group. */
5441 /* Otherwise check that as many consecutive regs as we need
5443 Also, don't use for a group registers that are
5444 needed for nongroups. */
5445 if (! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, regnum
))
5448 regno
= regnum
+ nr
- 1;
5449 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5450 && spill_reg_order
[regno
] >= 0
5451 && reload_reg_free_p (regno
, reload_opnum
[r
],
5452 reload_when_needed
[r
])
5453 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
,
5463 /* If we found something on pass 1, omit pass 2. */
5464 if (count
< n_spills
)
5468 /* We should have found a spill register by now. */
5469 if (count
== n_spills
)
5476 /* I is the index in SPILL_REG_RTX of the reload register we are to
5477 allocate. Get an rtx for it and find its register number. */
5479 new = spill_reg_rtx
[i
];
5481 if (new == 0 || GET_MODE (new) != reload_mode
[r
])
5482 spill_reg_rtx
[i
] = new
5483 = gen_rtx_REG (reload_mode
[r
], spill_regs
[i
]);
5485 regno
= true_regnum (new);
5487 /* Detect when the reload reg can't hold the reload mode.
5488 This used to be one `if', but Sequent compiler can't handle that. */
5489 if (HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
5491 enum machine_mode test_mode
= VOIDmode
;
5493 test_mode
= GET_MODE (reload_in
[r
]);
5494 /* If reload_in[r] has VOIDmode, it means we will load it
5495 in whatever mode the reload reg has: to wit, reload_mode[r].
5496 We have already tested that for validity. */
5497 /* Aside from that, we need to test that the expressions
5498 to reload from or into have modes which are valid for this
5499 reload register. Otherwise the reload insns would be invalid. */
5500 if (! (reload_in
[r
] != 0 && test_mode
!= VOIDmode
5501 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5502 if (! (reload_out
[r
] != 0
5503 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (reload_out
[r
]))))
5505 /* The reg is OK. */
5508 /* Mark as in use for this insn the reload regs we use
5510 mark_reload_reg_in_use (spill_regs
[i
], reload_opnum
[r
],
5511 reload_when_needed
[r
], reload_mode
[r
]);
5513 reload_reg_rtx
[r
] = new;
5514 reload_spill_index
[r
] = spill_regs
[i
];
5519 /* The reg is not OK. */
5524 if (asm_noperands (PATTERN (insn
)) < 0)
5525 /* It's the compiler's fault. */
5526 fatal_insn ("Could not find a spill register", insn
);
5528 /* It's the user's fault; the operand's mode and constraint
5529 don't match. Disable this reload so we don't crash in final. */
5530 error_for_asm (insn
,
5531 "`asm' operand constraint incompatible with operand size");
5534 reload_reg_rtx
[r
] = 0;
5535 reload_optional
[r
] = 1;
5536 reload_secondary_p
[r
] = 1;
5541 /* Assign hard reg targets for the pseudo-registers we must reload
5542 into hard regs for this insn.
5543 Also output the instructions to copy them in and out of the hard regs.
5545 For machines with register classes, we are responsible for
5546 finding a reload reg in the proper class. */
5549 choose_reload_regs (chain
)
5550 struct insn_chain
*chain
;
5552 rtx insn
= chain
->insn
;
5554 int max_group_size
= 1;
5555 enum reg_class group_class
= NO_REGS
;
5559 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5560 char save_reload_inherited
[MAX_RELOADS
];
5561 rtx save_reload_inheritance_insn
[MAX_RELOADS
];
5562 rtx save_reload_override_in
[MAX_RELOADS
];
5563 int save_reload_spill_index
[MAX_RELOADS
];
5564 HARD_REG_SET save_reload_reg_used
;
5565 HARD_REG_SET save_reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5566 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5567 HARD_REG_SET save_reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5568 HARD_REG_SET save_reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5569 HARD_REG_SET save_reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5570 HARD_REG_SET save_reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5571 HARD_REG_SET save_reload_reg_used_in_op_addr
;
5572 HARD_REG_SET save_reload_reg_used_in_op_addr_reload
;
5573 HARD_REG_SET save_reload_reg_used_in_insn
;
5574 HARD_REG_SET save_reload_reg_used_in_other_addr
;
5575 HARD_REG_SET save_reload_reg_used_at_all
;
5577 bzero (reload_inherited
, MAX_RELOADS
);
5578 bzero ((char *) reload_inheritance_insn
, MAX_RELOADS
* sizeof (rtx
));
5579 bzero ((char *) reload_override_in
, MAX_RELOADS
* sizeof (rtx
));
5581 CLEAR_HARD_REG_SET (reload_reg_used
);
5582 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5583 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5584 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5585 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5586 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5588 CLEAR_HARD_REG_SET (reg_used_by_pseudo
);
5589 compute_use_by_pseudos (®_used_by_pseudo
, chain
->live_before
);
5590 compute_use_by_pseudos (®_used_by_pseudo
, chain
->live_after
);
5592 for (i
= 0; i
< reload_n_operands
; i
++)
5594 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5595 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5596 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5597 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5598 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5599 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5602 IOR_COMPL_HARD_REG_SET (reload_reg_used
, chain
->used_spill_regs
);
5604 #if 0 /* Not needed, now that we can always retry without inheritance. */
5605 /* See if we have more mandatory reloads than spill regs.
5606 If so, then we cannot risk optimizations that could prevent
5607 reloads from sharing one spill register.
5609 Since we will try finding a better register than reload_reg_rtx
5610 unless it is equal to reload_in or reload_out, count such reloads. */
5614 for (j
= 0; j
< n_reloads
; j
++)
5615 if (! reload_optional
[j
]
5616 && (reload_in
[j
] != 0 || reload_out
[j
] != 0 || reload_secondary_p
[j
])
5617 && (reload_reg_rtx
[j
] == 0
5618 || (! rtx_equal_p (reload_reg_rtx
[j
], reload_in
[j
])
5619 && ! rtx_equal_p (reload_reg_rtx
[j
], reload_out
[j
]))))
5626 /* In order to be certain of getting the registers we need,
5627 we must sort the reloads into order of increasing register class.
5628 Then our grabbing of reload registers will parallel the process
5629 that provided the reload registers.
5631 Also note whether any of the reloads wants a consecutive group of regs.
5632 If so, record the maximum size of the group desired and what
5633 register class contains all the groups needed by this insn. */
5635 for (j
= 0; j
< n_reloads
; j
++)
5637 reload_order
[j
] = j
;
5638 reload_spill_index
[j
] = -1;
5641 = (reload_inmode
[j
] == VOIDmode
5642 || (GET_MODE_SIZE (reload_outmode
[j
])
5643 > GET_MODE_SIZE (reload_inmode
[j
])))
5644 ? reload_outmode
[j
] : reload_inmode
[j
];
5646 reload_nregs
[j
] = CLASS_MAX_NREGS (reload_reg_class
[j
], reload_mode
[j
]);
5648 if (reload_nregs
[j
] > 1)
5650 max_group_size
= MAX (reload_nregs
[j
], max_group_size
);
5651 group_class
= reg_class_superunion
[(int)reload_reg_class
[j
]][(int)group_class
];
5654 /* If we have already decided to use a certain register,
5655 don't use it in another way. */
5656 if (reload_reg_rtx
[j
])
5657 mark_reload_reg_in_use (REGNO (reload_reg_rtx
[j
]), reload_opnum
[j
],
5658 reload_when_needed
[j
], reload_mode
[j
]);
5662 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5664 bcopy ((char *) reload_reg_rtx
, (char *) save_reload_reg_rtx
,
5665 sizeof reload_reg_rtx
);
5666 bcopy (reload_inherited
, save_reload_inherited
, sizeof reload_inherited
);
5667 bcopy ((char *) reload_inheritance_insn
,
5668 (char *) save_reload_inheritance_insn
,
5669 sizeof reload_inheritance_insn
);
5670 bcopy ((char *) reload_override_in
, (char *) save_reload_override_in
,
5671 sizeof reload_override_in
);
5672 bcopy ((char *) reload_spill_index
, (char *) save_reload_spill_index
,
5673 sizeof reload_spill_index
);
5674 COPY_HARD_REG_SET (save_reload_reg_used
, reload_reg_used
);
5675 COPY_HARD_REG_SET (save_reload_reg_used_at_all
, reload_reg_used_at_all
);
5676 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr
,
5677 reload_reg_used_in_op_addr
);
5679 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload
,
5680 reload_reg_used_in_op_addr_reload
);
5682 COPY_HARD_REG_SET (save_reload_reg_used_in_insn
,
5683 reload_reg_used_in_insn
);
5684 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr
,
5685 reload_reg_used_in_other_addr
);
5687 for (i
= 0; i
< reload_n_operands
; i
++)
5689 COPY_HARD_REG_SET (save_reload_reg_used_in_output
[i
],
5690 reload_reg_used_in_output
[i
]);
5691 COPY_HARD_REG_SET (save_reload_reg_used_in_input
[i
],
5692 reload_reg_used_in_input
[i
]);
5693 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr
[i
],
5694 reload_reg_used_in_input_addr
[i
]);
5695 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr
[i
],
5696 reload_reg_used_in_inpaddr_addr
[i
]);
5697 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr
[i
],
5698 reload_reg_used_in_output_addr
[i
]);
5699 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr
[i
],
5700 reload_reg_used_in_outaddr_addr
[i
]);
5703 /* If -O, try first with inheritance, then turning it off.
5704 If not -O, don't do inheritance.
5705 Using inheritance when not optimizing leads to paradoxes
5706 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5707 because one side of the comparison might be inherited. */
5709 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5711 /* Process the reloads in order of preference just found.
5712 Beyond this point, subregs can be found in reload_reg_rtx.
5714 This used to look for an existing reloaded home for all
5715 of the reloads, and only then perform any new reloads.
5716 But that could lose if the reloads were done out of reg-class order
5717 because a later reload with a looser constraint might have an old
5718 home in a register needed by an earlier reload with a tighter constraint.
5720 To solve this, we make two passes over the reloads, in the order
5721 described above. In the first pass we try to inherit a reload
5722 from a previous insn. If there is a later reload that needs a
5723 class that is a proper subset of the class being processed, we must
5724 also allocate a spill register during the first pass.
5726 Then make a second pass over the reloads to allocate any reloads
5727 that haven't been given registers yet. */
5729 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5731 for (j
= 0; j
< n_reloads
; j
++)
5733 register int r
= reload_order
[j
];
5735 /* Ignore reloads that got marked inoperative. */
5736 if (reload_out
[r
] == 0 && reload_in
[r
] == 0
5737 && ! reload_secondary_p
[r
])
5740 /* If find_reloads chose to use reload_in or reload_out as a reload
5741 register, we don't need to chose one. Otherwise, try even if it
5742 found one since we might save an insn if we find the value lying
5744 Try also when reload_in is a pseudo without a hard reg. */
5745 if (reload_in
[r
] != 0 && reload_reg_rtx
[r
] != 0
5746 && (rtx_equal_p (reload_in
[r
], reload_reg_rtx
[r
])
5747 || (rtx_equal_p (reload_out
[r
], reload_reg_rtx
[r
])
5748 && GET_CODE (reload_in
[r
]) != MEM
5749 && true_regnum (reload_in
[r
]) < FIRST_PSEUDO_REGISTER
)))
5752 #if 0 /* No longer needed for correct operation.
5753 It might give better code, or might not; worth an experiment? */
5754 /* If this is an optional reload, we can't inherit from earlier insns
5755 until we are sure that any non-optional reloads have been allocated.
5756 The following code takes advantage of the fact that optional reloads
5757 are at the end of reload_order. */
5758 if (reload_optional
[r
] != 0)
5759 for (i
= 0; i
< j
; i
++)
5760 if ((reload_out
[reload_order
[i
]] != 0
5761 || reload_in
[reload_order
[i
]] != 0
5762 || reload_secondary_p
[reload_order
[i
]])
5763 && ! reload_optional
[reload_order
[i
]]
5764 && reload_reg_rtx
[reload_order
[i
]] == 0)
5765 allocate_reload_reg (chain
, reload_order
[i
], 0, inheritance
);
5768 /* First see if this pseudo is already available as reloaded
5769 for a previous insn. We cannot try to inherit for reloads
5770 that are smaller than the maximum number of registers needed
5771 for groups unless the register we would allocate cannot be used
5774 We could check here to see if this is a secondary reload for
5775 an object that is already in a register of the desired class.
5776 This would avoid the need for the secondary reload register.
5777 But this is complex because we can't easily determine what
5778 objects might want to be loaded via this reload. So let a
5779 register be allocated here. In `emit_reload_insns' we suppress
5780 one of the loads in the case described above. */
5785 register int regno
= -1;
5786 enum machine_mode mode
;
5788 if (reload_in
[r
] == 0)
5790 else if (GET_CODE (reload_in
[r
]) == REG
)
5792 regno
= REGNO (reload_in
[r
]);
5793 mode
= GET_MODE (reload_in
[r
]);
5795 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
5797 regno
= REGNO (reload_in_reg
[r
]);
5798 mode
= GET_MODE (reload_in_reg
[r
]);
5800 else if (GET_CODE (reload_in_reg
[r
]) == SUBREG
5801 && GET_CODE (SUBREG_REG (reload_in_reg
[r
])) == REG
)
5803 word
= SUBREG_WORD (reload_in_reg
[r
]);
5804 regno
= REGNO (SUBREG_REG (reload_in_reg
[r
]));
5805 if (regno
< FIRST_PSEUDO_REGISTER
)
5807 mode
= GET_MODE (reload_in_reg
[r
]);
5810 else if ((GET_CODE (reload_in_reg
[r
]) == PRE_INC
5811 || GET_CODE (reload_in_reg
[r
]) == PRE_DEC
5812 || GET_CODE (reload_in_reg
[r
]) == POST_INC
5813 || GET_CODE (reload_in_reg
[r
]) == POST_DEC
)
5814 && GET_CODE (XEXP (reload_in_reg
[r
], 0)) == REG
)
5816 regno
= REGNO (XEXP (reload_in_reg
[r
], 0));
5817 mode
= GET_MODE (XEXP (reload_in_reg
[r
], 0));
5818 reload_out
[r
] = reload_in
[r
];
5822 /* This won't work, since REGNO can be a pseudo reg number.
5823 Also, it takes much more hair to keep track of all the things
5824 that can invalidate an inherited reload of part of a pseudoreg. */
5825 else if (GET_CODE (reload_in
[r
]) == SUBREG
5826 && GET_CODE (SUBREG_REG (reload_in
[r
])) == REG
)
5827 regno
= REGNO (SUBREG_REG (reload_in
[r
])) + SUBREG_WORD (reload_in
[r
]);
5830 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5832 enum reg_class
class = reload_reg_class
[r
], last_class
;
5833 rtx last_reg
= reg_last_reload_reg
[regno
];
5835 i
= REGNO (last_reg
) + word
;
5836 last_class
= REGNO_REG_CLASS (i
);
5837 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
5838 >= GET_MODE_SIZE (mode
) + word
* UNITS_PER_WORD
)
5839 && reg_reloaded_contents
[i
] == regno
5840 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5841 && HARD_REGNO_MODE_OK (i
, reload_mode
[r
])
5842 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5843 /* Even if we can't use this register as a reload
5844 register, we might use it for reload_override_in,
5845 if copying it to the desired class is cheap
5847 || ((REGISTER_MOVE_COST (last_class
, class)
5848 < MEMORY_MOVE_COST (mode
, class, 1))
5849 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5850 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5854 #ifdef SECONDARY_MEMORY_NEEDED
5855 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5860 && (reload_nregs
[r
] == max_group_size
5861 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5863 && ((reload_reg_free_p (i
, reload_opnum
[r
],
5864 reload_when_needed
[r
])
5865 && reload_reg_free_before_p (i
, reload_opnum
[r
],
5866 reload_when_needed
[r
],
5868 || reload_reg_free_for_value_p (i
, reload_opnum
[r
],
5869 reload_when_needed
[r
],
5873 /* If a group is needed, verify that all the subsequent
5874 registers still have their values intact. */
5876 = HARD_REGNO_NREGS (i
, reload_mode
[r
]);
5879 for (k
= 1; k
< nr
; k
++)
5880 if (reg_reloaded_contents
[i
+ k
] != regno
5881 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5888 last_reg
= (GET_MODE (last_reg
) == mode
5889 ? last_reg
: gen_rtx_REG (mode
, i
));
5891 /* We found a register that contains the
5892 value we need. If this register is the
5893 same as an `earlyclobber' operand of the
5894 current insn, just mark it as a place to
5895 reload from since we can't use it as the
5896 reload register itself. */
5898 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5899 if (reg_overlap_mentioned_for_reload_p
5900 (reg_last_reload_reg
[regno
],
5901 reload_earlyclobbers
[i1
]))
5904 if (i1
!= n_earlyclobbers
5905 /* Don't use it if we'd clobber a pseudo reg. */
5906 || (! TEST_HARD_REG_BIT (reg_used_by_pseudo
, i
)
5908 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5909 /* Don't really use the inherited spill reg
5910 if we need it wider than we've got it. */
5911 || (GET_MODE_SIZE (reload_mode
[r
])
5912 > GET_MODE_SIZE (mode
))
5913 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
5916 /* If find_reloads chose reload_out as reload
5917 register, stay with it - that leaves the
5918 inherited register for subsequent reloads. */
5919 || (reload_out
[r
] && reload_reg_rtx
[r
]
5920 && rtx_equal_p (reload_out
[r
],
5921 reload_reg_rtx
[r
])))
5923 reload_override_in
[r
] = last_reg
;
5924 reload_inheritance_insn
[r
]
5925 = reg_reloaded_insn
[i
];
5930 /* We can use this as a reload reg. */
5931 /* Mark the register as in use for this part of
5933 mark_reload_reg_in_use (i
,
5935 reload_when_needed
[r
],
5937 reload_reg_rtx
[r
] = last_reg
;
5938 reload_inherited
[r
] = 1;
5939 reload_inheritance_insn
[r
]
5940 = reg_reloaded_insn
[i
];
5941 reload_spill_index
[r
] = i
;
5942 for (k
= 0; k
< nr
; k
++)
5943 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5951 /* Here's another way to see if the value is already lying around. */
5953 && reload_in
[r
] != 0
5954 && ! reload_inherited
[r
]
5955 && reload_out
[r
] == 0
5956 && (CONSTANT_P (reload_in
[r
])
5957 || GET_CODE (reload_in
[r
]) == PLUS
5958 || GET_CODE (reload_in
[r
]) == REG
5959 || GET_CODE (reload_in
[r
]) == MEM
)
5960 && (reload_nregs
[r
] == max_group_size
5961 || ! reg_classes_intersect_p (reload_reg_class
[r
], group_class
)))
5964 = find_equiv_reg (reload_in
[r
], insn
, reload_reg_class
[r
],
5965 -1, NULL_PTR
, 0, reload_mode
[r
]);
5970 if (GET_CODE (equiv
) == REG
)
5971 regno
= REGNO (equiv
);
5972 else if (GET_CODE (equiv
) == SUBREG
)
5974 /* This must be a SUBREG of a hard register.
5975 Make a new REG since this might be used in an
5976 address and not all machines support SUBREGs
5978 regno
= REGNO (SUBREG_REG (equiv
)) + SUBREG_WORD (equiv
);
5979 equiv
= gen_rtx_REG (reload_mode
[r
], regno
);
5985 /* If we found a spill reg, reject it unless it is free
5986 and of the desired class. */
5988 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
)
5989 && ! reload_reg_free_for_value_p (regno
, reload_opnum
[r
],
5990 reload_when_needed
[r
],
5993 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
5997 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
6000 /* We found a register that contains the value we need.
6001 If this register is the same as an `earlyclobber' operand
6002 of the current insn, just mark it as a place to reload from
6003 since we can't use it as the reload register itself. */
6006 for (i
= 0; i
< n_earlyclobbers
; i
++)
6007 if (reg_overlap_mentioned_for_reload_p (equiv
,
6008 reload_earlyclobbers
[i
]))
6010 reload_override_in
[r
] = equiv
;
6015 /* If the equiv register we have found is explicitly clobbered
6016 in the current insn, it depends on the reload type if we
6017 can use it, use it for reload_override_in, or not at all.
6018 In particular, we then can't use EQUIV for a
6019 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6021 if (equiv
!= 0 && regno_clobbered_p (regno
, insn
))
6023 switch (reload_when_needed
[r
])
6025 case RELOAD_FOR_OTHER_ADDRESS
:
6026 case RELOAD_FOR_INPADDR_ADDRESS
:
6027 case RELOAD_FOR_INPUT_ADDRESS
:
6028 case RELOAD_FOR_OPADDR_ADDR
:
6031 case RELOAD_FOR_INPUT
:
6032 case RELOAD_FOR_OPERAND_ADDRESS
:
6033 reload_override_in
[r
] = equiv
;
6041 /* If we found an equivalent reg, say no code need be generated
6042 to load it, and use it as our reload reg. */
6043 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
6045 int nr
= HARD_REGNO_NREGS (regno
, reload_mode
[r
]);
6047 reload_reg_rtx
[r
] = equiv
;
6048 reload_inherited
[r
] = 1;
6050 /* If reg_reloaded_valid is not set for this register,
6051 there might be a stale spill_reg_store lying around.
6052 We must clear it, since otherwise emit_reload_insns
6053 might delete the store. */
6054 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6055 spill_reg_store
[regno
] = NULL_RTX
;
6056 /* If any of the hard registers in EQUIV are spill
6057 registers, mark them as in use for this insn. */
6058 for (k
= 0; k
< nr
; k
++)
6060 i
= spill_reg_order
[regno
+ k
];
6063 mark_reload_reg_in_use (regno
, reload_opnum
[r
],
6064 reload_when_needed
[r
],
6066 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6073 /* If we found a register to use already, or if this is an optional
6074 reload, we are done. */
6075 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
] != 0)
6078 #if 0 /* No longer needed for correct operation. Might or might not
6079 give better code on the average. Want to experiment? */
6081 /* See if there is a later reload that has a class different from our
6082 class that intersects our class or that requires less register
6083 than our reload. If so, we must allocate a register to this
6084 reload now, since that reload might inherit a previous reload
6085 and take the only available register in our class. Don't do this
6086 for optional reloads since they will force all previous reloads
6087 to be allocated. Also don't do this for reloads that have been
6090 for (i
= j
+ 1; i
< n_reloads
; i
++)
6092 int s
= reload_order
[i
];
6094 if ((reload_in
[s
] == 0 && reload_out
[s
] == 0
6095 && ! reload_secondary_p
[s
])
6096 || reload_optional
[s
])
6099 if ((reload_reg_class
[s
] != reload_reg_class
[r
]
6100 && reg_classes_intersect_p (reload_reg_class
[r
],
6101 reload_reg_class
[s
]))
6102 || reload_nregs
[s
] < reload_nregs
[r
])
6109 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1, inheritance
);
6113 /* Now allocate reload registers for anything non-optional that
6114 didn't get one yet. */
6115 for (j
= 0; j
< n_reloads
; j
++)
6117 register int r
= reload_order
[j
];
6119 /* Ignore reloads that got marked inoperative. */
6120 if (reload_out
[r
] == 0 && reload_in
[r
] == 0 && ! reload_secondary_p
[r
])
6123 /* Skip reloads that already have a register allocated or are
6125 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
])
6128 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1, inheritance
))
6132 /* If that loop got all the way, we have won. */
6136 /* Loop around and try without any inheritance. */
6137 /* First undo everything done by the failed attempt
6138 to allocate with inheritance. */
6139 bcopy ((char *) save_reload_reg_rtx
, (char *) reload_reg_rtx
,
6140 sizeof reload_reg_rtx
);
6141 bcopy ((char *) save_reload_inherited
, (char *) reload_inherited
,
6142 sizeof reload_inherited
);
6143 bcopy ((char *) save_reload_inheritance_insn
,
6144 (char *) reload_inheritance_insn
,
6145 sizeof reload_inheritance_insn
);
6146 bcopy ((char *) save_reload_override_in
, (char *) reload_override_in
,
6147 sizeof reload_override_in
);
6148 bcopy ((char *) save_reload_spill_index
, (char *) reload_spill_index
,
6149 sizeof reload_spill_index
);
6150 COPY_HARD_REG_SET (reload_reg_used
, save_reload_reg_used
);
6151 COPY_HARD_REG_SET (reload_reg_used_at_all
, save_reload_reg_used_at_all
);
6152 COPY_HARD_REG_SET (reload_reg_used_in_op_addr
,
6153 save_reload_reg_used_in_op_addr
);
6154 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload
,
6155 save_reload_reg_used_in_op_addr_reload
);
6156 COPY_HARD_REG_SET (reload_reg_used_in_insn
,
6157 save_reload_reg_used_in_insn
);
6158 COPY_HARD_REG_SET (reload_reg_used_in_other_addr
,
6159 save_reload_reg_used_in_other_addr
);
6161 for (i
= 0; i
< reload_n_operands
; i
++)
6163 COPY_HARD_REG_SET (reload_reg_used_in_input
[i
],
6164 save_reload_reg_used_in_input
[i
]);
6165 COPY_HARD_REG_SET (reload_reg_used_in_output
[i
],
6166 save_reload_reg_used_in_output
[i
]);
6167 COPY_HARD_REG_SET (reload_reg_used_in_input_addr
[i
],
6168 save_reload_reg_used_in_input_addr
[i
]);
6169 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
],
6170 save_reload_reg_used_in_inpaddr_addr
[i
]);
6171 COPY_HARD_REG_SET (reload_reg_used_in_output_addr
[i
],
6172 save_reload_reg_used_in_output_addr
[i
]);
6173 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
],
6174 save_reload_reg_used_in_outaddr_addr
[i
]);
6178 /* If we thought we could inherit a reload, because it seemed that
6179 nothing else wanted the same reload register earlier in the insn,
6180 verify that assumption, now that all reloads have been assigned.
6181 Likewise for reloads where reload_override_in has been set. */
6183 /* If doing expensive optimizations, do one preliminary pass that doesn't
6184 cancel any inheritance, but removes reloads that have been needed only
6185 for reloads that we know can be inherited. */
6186 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6188 for (j
= 0; j
< n_reloads
; j
++)
6190 register int r
= reload_order
[j
];
6192 if (reload_inherited
[r
] && reload_reg_rtx
[r
])
6193 check_reg
= reload_reg_rtx
[r
];
6194 else if (reload_override_in
[r
]
6195 && (GET_CODE (reload_override_in
[r
]) == REG
6196 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6197 check_reg
= reload_override_in
[r
];
6200 if (! (reload_reg_free_before_p (true_regnum (check_reg
),
6201 reload_opnum
[r
], reload_when_needed
[r
],
6202 ! reload_inherited
[r
])
6203 || reload_reg_free_for_value_p (true_regnum (check_reg
),
6205 reload_when_needed
[r
],
6211 reload_inherited
[r
] = 0;
6212 reload_override_in
[r
] = 0;
6214 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6215 reload_override_in, then we do not need its related
6216 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6217 likewise for other reload types.
6218 We handle this by removing a reload when its only replacement
6219 is mentioned in reload_in of the reload we are going to inherit.
6220 A special case are auto_inc expressions; even if the input is
6221 inherited, we still need the address for the output. We can
6222 recognize them because they have RELOAD_OUT set but not
6224 If we suceeded removing some reload and we are doing a preliminary
6225 pass just to remove such reloads, make another pass, since the
6226 removal of one reload might allow us to inherit another one. */
6227 else if ((! reload_out
[r
] || reload_out_reg
[r
])
6228 && remove_address_replacements (reload_in
[r
]) && pass
)
6233 /* Now that reload_override_in is known valid,
6234 actually override reload_in. */
6235 for (j
= 0; j
< n_reloads
; j
++)
6236 if (reload_override_in
[j
])
6237 reload_in
[j
] = reload_override_in
[j
];
6239 /* If this reload won't be done because it has been cancelled or is
6240 optional and not inherited, clear reload_reg_rtx so other
6241 routines (such as subst_reloads) don't get confused. */
6242 for (j
= 0; j
< n_reloads
; j
++)
6243 if (reload_reg_rtx
[j
] != 0
6244 && ((reload_optional
[j
] && ! reload_inherited
[j
])
6245 || (reload_in
[j
] == 0 && reload_out
[j
] == 0
6246 && ! reload_secondary_p
[j
])))
6248 int regno
= true_regnum (reload_reg_rtx
[j
]);
6250 if (spill_reg_order
[regno
] >= 0)
6251 clear_reload_reg_in_use (regno
, reload_opnum
[j
],
6252 reload_when_needed
[j
], reload_mode
[j
]);
6253 reload_reg_rtx
[j
] = 0;
6256 /* Record which pseudos and which spill regs have output reloads. */
6257 for (j
= 0; j
< n_reloads
; j
++)
6259 register int r
= reload_order
[j
];
6261 i
= reload_spill_index
[r
];
6263 /* I is nonneg if this reload uses a register.
6264 If reload_reg_rtx[r] is 0, this is an optional reload
6265 that we opted to ignore. */
6266 if (reload_out_reg
[r
] != 0 && GET_CODE (reload_out_reg
[r
]) == REG
6267 && reload_reg_rtx
[r
] != 0)
6269 register int nregno
= REGNO (reload_out_reg
[r
]);
6272 if (nregno
< FIRST_PSEUDO_REGISTER
)
6273 nr
= HARD_REGNO_NREGS (nregno
, reload_mode
[r
]);
6276 reg_has_output_reload
[nregno
+ nr
] = 1;
6280 nr
= HARD_REGNO_NREGS (i
, reload_mode
[r
]);
6282 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6285 if (reload_when_needed
[r
] != RELOAD_OTHER
6286 && reload_when_needed
[r
] != RELOAD_FOR_OUTPUT
6287 && reload_when_needed
[r
] != RELOAD_FOR_INSN
)
6293 /* Deallocate the reload register for reload R. This is called from
6294 remove_address_replacements. */
6296 deallocate_reload_reg (r
)
6301 if (! reload_reg_rtx
[r
])
6303 regno
= true_regnum (reload_reg_rtx
[r
]);
6304 reload_reg_rtx
[r
] = 0;
6305 if (spill_reg_order
[regno
] >= 0)
6306 clear_reload_reg_in_use (regno
, reload_opnum
[r
], reload_when_needed
[r
],
6308 reload_spill_index
[r
] = -1;
6311 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6312 reloads of the same item for fear that we might not have enough reload
6313 registers. However, normally they will get the same reload register
6314 and hence actually need not be loaded twice.
6316 Here we check for the most common case of this phenomenon: when we have
6317 a number of reloads for the same object, each of which were allocated
6318 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6319 reload, and is not modified in the insn itself. If we find such,
6320 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6321 This will not increase the number of spill registers needed and will
6322 prevent redundant code. */
6325 merge_assigned_reloads (insn
)
6330 /* Scan all the reloads looking for ones that only load values and
6331 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6332 assigned and not modified by INSN. */
6334 for (i
= 0; i
< n_reloads
; i
++)
6336 int conflicting_input
= 0;
6337 int max_input_address_opnum
= -1;
6338 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6340 if (reload_in
[i
] == 0 || reload_when_needed
[i
] == RELOAD_OTHER
6341 || reload_out
[i
] != 0 || reload_reg_rtx
[i
] == 0
6342 || reg_set_p (reload_reg_rtx
[i
], insn
))
6345 /* Look at all other reloads. Ensure that the only use of this
6346 reload_reg_rtx is in a reload that just loads the same value
6347 as we do. Note that any secondary reloads must be of the identical
6348 class since the values, modes, and result registers are the
6349 same, so we need not do anything with any secondary reloads. */
6351 for (j
= 0; j
< n_reloads
; j
++)
6353 if (i
== j
|| reload_reg_rtx
[j
] == 0
6354 || ! reg_overlap_mentioned_p (reload_reg_rtx
[j
],
6358 if (reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6359 && reload_opnum
[j
] > max_input_address_opnum
)
6360 max_input_address_opnum
= reload_opnum
[j
];
6362 /* If the reload regs aren't exactly the same (e.g, different modes)
6363 or if the values are different, we can't merge this reload.
6364 But if it is an input reload, we might still merge
6365 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6367 if (! rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6368 || reload_out
[j
] != 0 || reload_in
[j
] == 0
6369 || ! rtx_equal_p (reload_in
[i
], reload_in
[j
]))
6371 if (reload_when_needed
[j
] != RELOAD_FOR_INPUT
6372 || ((reload_when_needed
[i
] != RELOAD_FOR_INPUT_ADDRESS
6373 || reload_opnum
[i
] > reload_opnum
[j
])
6374 && reload_when_needed
[i
] != RELOAD_FOR_OTHER_ADDRESS
))
6376 conflicting_input
= 1;
6377 if (min_conflicting_input_opnum
> reload_opnum
[j
])
6378 min_conflicting_input_opnum
= reload_opnum
[j
];
6382 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6383 we, in fact, found any matching reloads. */
6386 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6388 for (j
= 0; j
< n_reloads
; j
++)
6389 if (i
!= j
&& reload_reg_rtx
[j
] != 0
6390 && rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6391 && (! conflicting_input
6392 || reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6393 || reload_when_needed
[j
] == RELOAD_FOR_OTHER_ADDRESS
))
6395 reload_when_needed
[i
] = RELOAD_OTHER
;
6397 reload_spill_index
[j
] = -1;
6398 transfer_replacements (i
, j
);
6401 /* If this is now RELOAD_OTHER, look for any reloads that load
6402 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6403 if they were for inputs, RELOAD_OTHER for outputs. Note that
6404 this test is equivalent to looking for reloads for this operand
6407 if (reload_when_needed
[i
] == RELOAD_OTHER
)
6408 for (j
= 0; j
< n_reloads
; j
++)
6409 if (reload_in
[j
] != 0
6410 && reload_when_needed
[i
] != RELOAD_OTHER
6411 && reg_overlap_mentioned_for_reload_p (reload_in
[j
],
6413 reload_when_needed
[j
]
6414 = ((reload_when_needed
[i
] == RELOAD_FOR_INPUT_ADDRESS
6415 || reload_when_needed
[i
] == RELOAD_FOR_INPADDR_ADDRESS
)
6416 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6422 /* Output insns to reload values in and out of the chosen reload regs. */
6425 emit_reload_insns (chain
)
6426 struct insn_chain
*chain
;
6428 rtx insn
= chain
->insn
;
6431 rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6432 rtx other_input_address_reload_insns
= 0;
6433 rtx other_input_reload_insns
= 0;
6434 rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6435 rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6436 rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6437 rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6438 rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6439 rtx operand_reload_insns
= 0;
6440 rtx other_operand_reload_insns
= 0;
6441 rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6442 rtx following_insn
= NEXT_INSN (insn
);
6443 rtx before_insn
= PREV_INSN (insn
);
6445 /* Values to be put in spill_reg_store are put here first. */
6446 rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6447 HARD_REG_SET reg_reloaded_died
;
6449 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6451 for (j
= 0; j
< reload_n_operands
; j
++)
6452 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6453 = inpaddr_address_reload_insns
[j
]
6454 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6455 = outaddr_address_reload_insns
[j
]
6456 = other_output_reload_insns
[j
] = 0;
6458 /* Now output the instructions to copy the data into and out of the
6459 reload registers. Do these in the order that the reloads were reported,
6460 since reloads of base and index registers precede reloads of operands
6461 and the operands may need the base and index registers reloaded. */
6463 for (j
= 0; j
< n_reloads
; j
++)
6466 rtx oldequiv_reg
= 0;
6467 rtx this_reload_insn
= 0;
6468 int expect_occurrences
= 1;
6470 if (reload_reg_rtx
[j
]
6471 && REGNO (reload_reg_rtx
[j
]) < FIRST_PSEUDO_REGISTER
)
6472 new_spill_reg_store
[REGNO (reload_reg_rtx
[j
])] = 0;
6474 old
= (reload_in
[j
] && GET_CODE (reload_in
[j
]) == MEM
6475 ? reload_in_reg
[j
] : reload_in
[j
]);
6478 /* AUTO_INC reloads need to be handled even if inherited. We got an
6479 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6480 && (! reload_inherited
[j
] || (reload_out
[j
] && ! reload_out_reg
[j
]))
6481 && ! rtx_equal_p (reload_reg_rtx
[j
], old
)
6482 && reload_reg_rtx
[j
] != 0)
6484 register rtx reloadreg
= reload_reg_rtx
[j
];
6486 enum machine_mode mode
;
6489 /* Determine the mode to reload in.
6490 This is very tricky because we have three to choose from.
6491 There is the mode the insn operand wants (reload_inmode[J]).
6492 There is the mode of the reload register RELOADREG.
6493 There is the intrinsic mode of the operand, which we could find
6494 by stripping some SUBREGs.
6495 It turns out that RELOADREG's mode is irrelevant:
6496 we can change that arbitrarily.
6498 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6499 then the reload reg may not support QImode moves, so use SImode.
6500 If foo is in memory due to spilling a pseudo reg, this is safe,
6501 because the QImode value is in the least significant part of a
6502 slot big enough for a SImode. If foo is some other sort of
6503 memory reference, then it is impossible to reload this case,
6504 so previous passes had better make sure this never happens.
6506 Then consider a one-word union which has SImode and one of its
6507 members is a float, being fetched as (SUBREG:SF union:SI).
6508 We must fetch that as SFmode because we could be loading into
6509 a float-only register. In this case OLD's mode is correct.
6511 Consider an immediate integer: it has VOIDmode. Here we need
6512 to get a mode from something else.
6514 In some cases, there is a fourth mode, the operand's
6515 containing mode. If the insn specifies a containing mode for
6516 this operand, it overrides all others.
6518 I am not sure whether the algorithm here is always right,
6519 but it does the right things in those cases. */
6521 mode
= GET_MODE (old
);
6522 if (mode
== VOIDmode
)
6523 mode
= reload_inmode
[j
];
6525 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6526 /* If we need a secondary register for this operation, see if
6527 the value is already in a register in that class. Don't
6528 do this if the secondary register will be used as a scratch
6531 if (reload_secondary_in_reload
[j
] >= 0
6532 && reload_secondary_in_icode
[j
] == CODE_FOR_nothing
6535 = find_equiv_reg (old
, insn
,
6536 reload_reg_class
[reload_secondary_in_reload
[j
]],
6537 -1, NULL_PTR
, 0, mode
);
6540 /* If reloading from memory, see if there is a register
6541 that already holds the same value. If so, reload from there.
6542 We can pass 0 as the reload_reg_p argument because
6543 any other reload has either already been emitted,
6544 in which case find_equiv_reg will see the reload-insn,
6545 or has yet to be emitted, in which case it doesn't matter
6546 because we will use this equiv reg right away. */
6548 if (oldequiv
== 0 && optimize
6549 && (GET_CODE (old
) == MEM
6550 || (GET_CODE (old
) == REG
6551 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6552 && reg_renumber
[REGNO (old
)] < 0)))
6553 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
,
6554 -1, NULL_PTR
, 0, mode
);
6558 int regno
= true_regnum (oldequiv
);
6560 /* If OLDEQUIV is a spill register, don't use it for this
6561 if any other reload needs it at an earlier stage of this insn
6562 or at this stage. */
6563 if (spill_reg_order
[regno
] >= 0
6564 && (! reload_reg_free_p (regno
, reload_opnum
[j
],
6565 reload_when_needed
[j
])
6566 || ! reload_reg_free_before_p (regno
, reload_opnum
[j
],
6567 reload_when_needed
[j
], 1)))
6570 /* If OLDEQUIV is not a spill register,
6571 don't use it if any other reload wants it. */
6572 if (spill_reg_order
[regno
] < 0)
6575 for (k
= 0; k
< n_reloads
; k
++)
6576 if (reload_reg_rtx
[k
] != 0 && k
!= j
6577 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx
[k
],
6585 /* If it is no cheaper to copy from OLDEQUIV into the
6586 reload register than it would be to move from memory,
6587 don't use it. Likewise, if we need a secondary register
6591 && ((REGNO_REG_CLASS (regno
) != reload_reg_class
[j
]
6592 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno
),
6593 reload_reg_class
[j
])
6594 >= MEMORY_MOVE_COST (mode
, reload_reg_class
[j
], 1)))
6595 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6596 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
6600 #ifdef SECONDARY_MEMORY_NEEDED
6601 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6602 reload_reg_class
[j
],
6609 /* delete_output_reload is only invoked properly if old contains
6610 the original pseudo register. Since this is replaced with a
6611 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6612 find the pseudo in RELOAD_IN_REG. */
6614 && reload_override_in
[j
]
6615 && GET_CODE (reload_in_reg
[j
]) == REG
)
6618 old
= reload_in_reg
[j
];
6622 else if (GET_CODE (oldequiv
) == REG
)
6623 oldequiv_reg
= oldequiv
;
6624 else if (GET_CODE (oldequiv
) == SUBREG
)
6625 oldequiv_reg
= SUBREG_REG (oldequiv
);
6627 /* If we are reloading from a register that was recently stored in
6628 with an output-reload, see if we can prove there was
6629 actually no need to store the old value in it. */
6631 if (optimize
&& GET_CODE (oldequiv
) == REG
6632 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6633 && spill_reg_store
[REGNO (oldequiv
)]
6634 && GET_CODE (old
) == REG
6635 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6636 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6637 reload_out_reg
[j
])))
6638 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6640 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6641 then load RELOADREG from OLDEQUIV. Note that we cannot use
6642 gen_lowpart_common since it can do the wrong thing when
6643 RELOADREG has a multi-word mode. Note that RELOADREG
6644 must always be a REG here. */
6646 if (GET_MODE (reloadreg
) != mode
)
6647 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6648 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6649 oldequiv
= SUBREG_REG (oldequiv
);
6650 if (GET_MODE (oldequiv
) != VOIDmode
6651 && mode
!= GET_MODE (oldequiv
))
6652 oldequiv
= gen_rtx_SUBREG (mode
, oldequiv
, 0);
6654 /* Switch to the right place to emit the reload insns. */
6655 switch (reload_when_needed
[j
])
6658 where
= &other_input_reload_insns
;
6660 case RELOAD_FOR_INPUT
:
6661 where
= &input_reload_insns
[reload_opnum
[j
]];
6663 case RELOAD_FOR_INPUT_ADDRESS
:
6664 where
= &input_address_reload_insns
[reload_opnum
[j
]];
6666 case RELOAD_FOR_INPADDR_ADDRESS
:
6667 where
= &inpaddr_address_reload_insns
[reload_opnum
[j
]];
6669 case RELOAD_FOR_OUTPUT_ADDRESS
:
6670 where
= &output_address_reload_insns
[reload_opnum
[j
]];
6672 case RELOAD_FOR_OUTADDR_ADDRESS
:
6673 where
= &outaddr_address_reload_insns
[reload_opnum
[j
]];
6675 case RELOAD_FOR_OPERAND_ADDRESS
:
6676 where
= &operand_reload_insns
;
6678 case RELOAD_FOR_OPADDR_ADDR
:
6679 where
= &other_operand_reload_insns
;
6681 case RELOAD_FOR_OTHER_ADDRESS
:
6682 where
= &other_input_address_reload_insns
;
6688 push_to_sequence (*where
);
6691 /* Auto-increment addresses must be reloaded in a special way. */
6692 if (reload_out
[j
] && ! reload_out_reg
[j
])
6694 /* We are not going to bother supporting the case where a
6695 incremented register can't be copied directly from
6696 OLDEQUIV since this seems highly unlikely. */
6697 if (reload_secondary_in_reload
[j
] >= 0)
6700 if (reload_inherited
[j
])
6701 oldequiv
= reloadreg
;
6703 old
= XEXP (reload_in_reg
[j
], 0);
6705 if (optimize
&& GET_CODE (oldequiv
) == REG
6706 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6707 && spill_reg_store
[REGNO (oldequiv
)]
6708 && GET_CODE (old
) == REG
6709 && (dead_or_set_p (insn
,
6710 spill_reg_stored_to
[REGNO (oldequiv
)])
6711 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6713 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6715 /* Prevent normal processing of this reload. */
6717 /* Output a special code sequence for this case. */
6718 new_spill_reg_store
[REGNO (reloadreg
)]
6719 = inc_for_reload (reloadreg
, oldequiv
, reload_out
[j
],
6723 /* If we are reloading a pseudo-register that was set by the previous
6724 insn, see if we can get rid of that pseudo-register entirely
6725 by redirecting the previous insn into our reload register. */
6727 else if (optimize
&& GET_CODE (old
) == REG
6728 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6729 && dead_or_set_p (insn
, old
)
6730 /* This is unsafe if some other reload
6731 uses the same reg first. */
6732 && reload_reg_free_before_p (REGNO (reloadreg
),
6734 reload_when_needed
[j
], 0))
6736 rtx temp
= PREV_INSN (insn
);
6737 while (temp
&& GET_CODE (temp
) == NOTE
)
6738 temp
= PREV_INSN (temp
);
6740 && GET_CODE (temp
) == INSN
6741 && GET_CODE (PATTERN (temp
)) == SET
6742 && SET_DEST (PATTERN (temp
)) == old
6743 /* Make sure we can access insn_operand_constraint. */
6744 && asm_noperands (PATTERN (temp
)) < 0
6745 /* This is unsafe if prev insn rejects our reload reg. */
6746 && constraint_accepts_reg_p (insn_operand_constraint
[recog_memoized (temp
)][0],
6748 /* This is unsafe if operand occurs more than once in current
6749 insn. Perhaps some occurrences aren't reloaded. */
6750 && count_occurrences (PATTERN (insn
), old
) == 1
6751 /* Don't risk splitting a matching pair of operands. */
6752 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
6754 /* Store into the reload register instead of the pseudo. */
6755 SET_DEST (PATTERN (temp
)) = reloadreg
;
6756 /* If these are the only uses of the pseudo reg,
6757 pretend for GDB it lives in the reload reg we used. */
6758 if (REG_N_DEATHS (REGNO (old
)) == 1
6759 && REG_N_SETS (REGNO (old
)) == 1)
6761 reg_renumber
[REGNO (old
)] = REGNO (reload_reg_rtx
[j
]);
6762 alter_reg (REGNO (old
), -1);
6768 /* We can't do that, so output an insn to load RELOADREG. */
6772 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6773 rtx second_reload_reg
= 0;
6774 enum insn_code icode
;
6776 /* If we have a secondary reload, pick up the secondary register
6777 and icode, if any. If OLDEQUIV and OLD are different or
6778 if this is an in-out reload, recompute whether or not we
6779 still need a secondary register and what the icode should
6780 be. If we still need a secondary register and the class or
6781 icode is different, go back to reloading from OLD if using
6782 OLDEQUIV means that we got the wrong type of register. We
6783 cannot have different class or icode due to an in-out reload
6784 because we don't make such reloads when both the input and
6785 output need secondary reload registers. */
6787 if (reload_secondary_in_reload
[j
] >= 0)
6789 int secondary_reload
= reload_secondary_in_reload
[j
];
6790 rtx real_oldequiv
= oldequiv
;
6793 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6794 and similarly for OLD.
6795 See comments in get_secondary_reload in reload.c. */
6796 /* If it is a pseudo that cannot be replaced with its
6797 equivalent MEM, we must fall back to reload_in, which
6798 will have all the necessary substitutions registered. */
6800 if (GET_CODE (oldequiv
) == REG
6801 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6802 && reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0)
6804 if (reg_equiv_address
[REGNO (oldequiv
)]
6805 || num_not_at_initial_offset
)
6806 real_oldequiv
= reload_in
[j
];
6808 real_oldequiv
= reg_equiv_mem
[REGNO (oldequiv
)];
6811 if (GET_CODE (old
) == REG
6812 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6813 && reg_equiv_memory_loc
[REGNO (old
)] != 0)
6815 if (reg_equiv_address
[REGNO (old
)]
6816 || num_not_at_initial_offset
)
6817 real_old
= reload_in
[j
];
6819 real_old
= reg_equiv_mem
[REGNO (old
)];
6822 second_reload_reg
= reload_reg_rtx
[secondary_reload
];
6823 icode
= reload_secondary_in_icode
[j
];
6825 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6826 || (reload_in
[j
] != 0 && reload_out
[j
] != 0))
6828 enum reg_class new_class
6829 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
6830 mode
, real_oldequiv
);
6832 if (new_class
== NO_REGS
)
6833 second_reload_reg
= 0;
6836 enum insn_code new_icode
;
6837 enum machine_mode new_mode
;
6839 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6840 REGNO (second_reload_reg
)))
6841 oldequiv
= old
, real_oldequiv
= real_old
;
6844 new_icode
= reload_in_optab
[(int) mode
];
6845 if (new_icode
!= CODE_FOR_nothing
6846 && ((insn_operand_predicate
[(int) new_icode
][0]
6847 && ! ((*insn_operand_predicate
[(int) new_icode
][0])
6849 || (insn_operand_predicate
[(int) new_icode
][1]
6850 && ! ((*insn_operand_predicate
[(int) new_icode
][1])
6851 (real_oldequiv
, mode
)))))
6852 new_icode
= CODE_FOR_nothing
;
6854 if (new_icode
== CODE_FOR_nothing
)
6857 new_mode
= insn_operand_mode
[(int) new_icode
][2];
6859 if (GET_MODE (second_reload_reg
) != new_mode
)
6861 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6863 oldequiv
= old
, real_oldequiv
= real_old
;
6866 = gen_rtx_REG (new_mode
,
6867 REGNO (second_reload_reg
));
6873 /* If we still need a secondary reload register, check
6874 to see if it is being used as a scratch or intermediate
6875 register and generate code appropriately. If we need
6876 a scratch register, use REAL_OLDEQUIV since the form of
6877 the insn may depend on the actual address if it is
6880 if (second_reload_reg
)
6882 if (icode
!= CODE_FOR_nothing
)
6884 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6885 second_reload_reg
));
6890 /* See if we need a scratch register to load the
6891 intermediate register (a tertiary reload). */
6892 enum insn_code tertiary_icode
6893 = reload_secondary_in_icode
[secondary_reload
];
6895 if (tertiary_icode
!= CODE_FOR_nothing
)
6897 rtx third_reload_reg
6898 = reload_reg_rtx
[reload_secondary_in_reload
[secondary_reload
]];
6900 emit_insn ((GEN_FCN (tertiary_icode
)
6901 (second_reload_reg
, real_oldequiv
,
6902 third_reload_reg
)));
6905 gen_reload (second_reload_reg
, real_oldequiv
,
6907 reload_when_needed
[j
]);
6909 oldequiv
= second_reload_reg
;
6915 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6917 rtx real_oldequiv
= oldequiv
;
6919 if ((GET_CODE (oldequiv
) == REG
6920 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6921 && reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0)
6922 || (GET_CODE (oldequiv
) == SUBREG
6923 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
6924 && (REGNO (SUBREG_REG (oldequiv
))
6925 >= FIRST_PSEUDO_REGISTER
)
6926 && (reg_equiv_memory_loc
6927 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6928 real_oldequiv
= reload_in
[j
];
6929 gen_reload (reloadreg
, real_oldequiv
, reload_opnum
[j
],
6930 reload_when_needed
[j
]);
6935 this_reload_insn
= get_last_insn ();
6936 /* End this sequence. */
6937 *where
= get_insns ();
6940 /* Update reload_override_in so that delete_address_reloads_1
6941 can see the actual register usage. */
6943 reload_override_in
[j
] = oldequiv
;
6946 /* When inheriting a wider reload, we have a MEM in reload_in[j],
6947 e.g. inheriting a SImode output reload for
6948 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6949 if (optimize
&& reload_inherited
[j
] && reload_in
[j
]
6950 && GET_CODE (reload_in
[j
]) == MEM
6951 && GET_CODE (reload_in_reg
[j
]) == MEM
6952 && reload_spill_index
[j
] >= 0
6953 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6956 = count_occurrences (PATTERN (insn
), reload_in
[j
]) == 1 ? 0 : -1;
6958 = regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6961 /* If we are reloading a register that was recently stored in with an
6962 output-reload, see if we can prove there was
6963 actually no need to store the old value in it. */
6966 && (reload_inherited
[j
] || reload_override_in
[j
])
6967 && reload_reg_rtx
[j
]
6968 && GET_CODE (reload_reg_rtx
[j
]) == REG
6969 && spill_reg_store
[REGNO (reload_reg_rtx
[j
])] != 0
6971 /* There doesn't seem to be any reason to restrict this to pseudos
6972 and doing so loses in the case where we are copying from a
6973 register of the wrong class. */
6974 && REGNO (spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])])
6975 >= FIRST_PSEUDO_REGISTER
6977 /* The insn might have already some references to stackslots
6978 replaced by MEMs, while reload_out_reg still names the
6980 && (dead_or_set_p (insn
,
6981 spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])])
6982 || rtx_equal_p (spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])],
6983 reload_out_reg
[j
])))
6984 delete_output_reload (insn
, j
, REGNO (reload_reg_rtx
[j
]));
6986 /* Input-reloading is done. Now do output-reloading,
6987 storing the value from the reload-register after the main insn
6988 if reload_out[j] is nonzero.
6990 ??? At some point we need to support handling output reloads of
6991 JUMP_INSNs or insns that set cc0. */
6993 /* If this is an output reload that stores something that is
6994 not loaded in this same reload, see if we can eliminate a previous
6997 rtx pseudo
= reload_out_reg
[j
];
7000 && GET_CODE (pseudo
) == REG
7001 && ! rtx_equal_p (reload_in_reg
[j
], pseudo
)
7002 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7003 && reg_last_reload_reg
[REGNO (pseudo
)])
7005 int pseudo_no
= REGNO (pseudo
);
7006 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7008 /* We don't need to test full validity of last_regno for
7009 inherit here; we only want to know if the store actually
7010 matches the pseudo. */
7011 if (reg_reloaded_contents
[last_regno
] == pseudo_no
7012 && spill_reg_store
[last_regno
]
7013 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7014 delete_output_reload (insn
, j
, last_regno
);
7018 old
= reload_out_reg
[j
];
7020 && reload_reg_rtx
[j
] != old
7021 && reload_reg_rtx
[j
] != 0)
7023 register rtx reloadreg
= reload_reg_rtx
[j
];
7024 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7025 register rtx second_reloadreg
= 0;
7028 enum machine_mode mode
;
7031 /* An output operand that dies right away does need a reload,
7032 but need not be copied from it. Show the new location in the
7034 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
7035 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7037 XEXP (note
, 0) = reload_reg_rtx
[j
];
7040 /* Likewise for a SUBREG of an operand that dies. */
7041 else if (GET_CODE (old
) == SUBREG
7042 && GET_CODE (SUBREG_REG (old
)) == REG
7043 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7046 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
7050 else if (GET_CODE (old
) == SCRATCH
)
7051 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7052 but we don't want to make an output reload. */
7056 /* Strip off of OLD any size-increasing SUBREGs such as
7057 (SUBREG:SI foo:QI 0). */
7059 while (GET_CODE (old
) == SUBREG
&& SUBREG_WORD (old
) == 0
7060 && (GET_MODE_SIZE (GET_MODE (old
))
7061 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old
)))))
7062 old
= SUBREG_REG (old
);
7065 /* If is a JUMP_INSN, we can't support output reloads yet. */
7066 if (GET_CODE (insn
) == JUMP_INSN
)
7069 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7072 push_to_sequence (output_reload_insns
[reload_opnum
[j
]]);
7074 old
= reload_out
[j
];
7076 /* Determine the mode to reload in.
7077 See comments above (for input reloading). */
7079 mode
= GET_MODE (old
);
7080 if (mode
== VOIDmode
)
7082 /* VOIDmode should never happen for an output. */
7083 if (asm_noperands (PATTERN (insn
)) < 0)
7084 /* It's the compiler's fault. */
7085 fatal_insn ("VOIDmode on an output", insn
);
7086 error_for_asm (insn
, "output operand is constant in `asm'");
7087 /* Prevent crash--use something we know is valid. */
7089 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7092 if (GET_MODE (reloadreg
) != mode
)
7093 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7095 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7097 /* If we need two reload regs, set RELOADREG to the intermediate
7098 one, since it will be stored into OLD. We might need a secondary
7099 register only for an input reload, so check again here. */
7101 if (reload_secondary_out_reload
[j
] >= 0)
7105 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
7106 && reg_equiv_mem
[REGNO (old
)] != 0)
7107 real_old
= reg_equiv_mem
[REGNO (old
)];
7109 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class
[j
],
7113 second_reloadreg
= reloadreg
;
7114 reloadreg
= reload_reg_rtx
[reload_secondary_out_reload
[j
]];
7116 /* See if RELOADREG is to be used as a scratch register
7117 or as an intermediate register. */
7118 if (reload_secondary_out_icode
[j
] != CODE_FOR_nothing
)
7120 emit_insn ((GEN_FCN (reload_secondary_out_icode
[j
])
7121 (real_old
, second_reloadreg
, reloadreg
)));
7126 /* See if we need both a scratch and intermediate reload
7129 int secondary_reload
= reload_secondary_out_reload
[j
];
7130 enum insn_code tertiary_icode
7131 = reload_secondary_out_icode
[secondary_reload
];
7133 if (GET_MODE (reloadreg
) != mode
)
7134 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7136 if (tertiary_icode
!= CODE_FOR_nothing
)
7139 = reload_reg_rtx
[reload_secondary_out_reload
[secondary_reload
]];
7142 /* Copy primary reload reg to secondary reload reg.
7143 (Note that these have been swapped above, then
7144 secondary reload reg to OLD using our insn. */
7146 /* If REAL_OLD is a paradoxical SUBREG, remove it
7147 and try to put the opposite SUBREG on
7149 if (GET_CODE (real_old
) == SUBREG
7150 && (GET_MODE_SIZE (GET_MODE (real_old
))
7151 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7152 && 0 != (tem
= gen_lowpart_common
7153 (GET_MODE (SUBREG_REG (real_old
)),
7155 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7157 gen_reload (reloadreg
, second_reloadreg
,
7158 reload_opnum
[j
], reload_when_needed
[j
]);
7159 emit_insn ((GEN_FCN (tertiary_icode
)
7160 (real_old
, reloadreg
, third_reloadreg
)));
7165 /* Copy between the reload regs here and then to
7168 gen_reload (reloadreg
, second_reloadreg
,
7169 reload_opnum
[j
], reload_when_needed
[j
]);
7175 /* Output the last reload insn. */
7180 /* Don't output the last reload if OLD is not the dest of
7181 INSN and is in the src and is clobbered by INSN. */
7182 if (! flag_expensive_optimizations
7183 || GET_CODE (old
) != REG
7184 || !(set
= single_set (insn
))
7185 || rtx_equal_p (old
, SET_DEST (set
))
7186 || !reg_mentioned_p (old
, SET_SRC (set
))
7187 || !regno_clobbered_p (REGNO (old
), insn
))
7188 gen_reload (old
, reloadreg
, reload_opnum
[j
],
7189 reload_when_needed
[j
]);
7192 /* Look at all insns we emitted, just to be safe. */
7193 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7194 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
7196 rtx pat
= PATTERN (p
);
7198 /* If this output reload doesn't come from a spill reg,
7199 clear any memory of reloaded copies of the pseudo reg.
7200 If this output reload comes from a spill reg,
7201 reg_has_output_reload will make this do nothing. */
7202 note_stores (pat
, forget_old_reloads_1
);
7204 if (reg_mentioned_p (reload_reg_rtx
[j
], pat
))
7206 rtx set
= single_set (insn
);
7207 if (reload_spill_index
[j
] < 0
7209 && SET_SRC (set
) == reload_reg_rtx
[j
])
7211 int src
= REGNO (SET_SRC (set
));
7213 reload_spill_index
[j
] = src
;
7214 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7215 if (find_regno_note (insn
, REG_DEAD
, src
))
7216 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7218 if (REGNO (reload_reg_rtx
[j
]) < FIRST_PSEUDO_REGISTER
)
7220 int s
= reload_secondary_out_reload
[j
];
7221 set
= single_set (p
);
7222 /* If this reload copies only to the secondary reload
7223 register, the secondary reload does the actual
7225 if (s
>= 0 && set
== NULL_RTX
)
7226 ; /* We can't tell what function the secondary reload
7227 has and where the actual store to the pseudo is
7228 made; leave new_spill_reg_store alone. */
7230 && SET_SRC (set
) == reload_reg_rtx
[j
]
7231 && SET_DEST (set
) == reload_reg_rtx
[s
])
7233 /* Usually the next instruction will be the
7234 secondary reload insn; if we can confirm
7235 that it is, setting new_spill_reg_store to
7236 that insn will allow an extra optimization. */
7237 rtx s_reg
= reload_reg_rtx
[s
];
7238 rtx next
= NEXT_INSN (p
);
7239 reload_out
[s
] = reload_out
[j
];
7240 reload_out_reg
[s
] = reload_out_reg
[j
];
7241 set
= single_set (next
);
7242 if (set
&& SET_SRC (set
) == s_reg
7243 && ! new_spill_reg_store
[REGNO (s_reg
)])
7245 SET_HARD_REG_BIT (reg_is_output_reload
,
7247 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7251 new_spill_reg_store
[REGNO (reload_reg_rtx
[j
])] = p
;
7256 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7258 emit_insns (other_output_reload_insns
[reload_opnum
[j
]]);
7259 other_output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7262 output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7268 /* Now write all the insns we made for reloads in the order expected by
7269 the allocation functions. Prior to the insn being reloaded, we write
7270 the following reloads:
7272 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7274 RELOAD_OTHER reloads.
7276 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7277 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7278 RELOAD_FOR_INPUT reload for the operand.
7280 RELOAD_FOR_OPADDR_ADDRS reloads.
7282 RELOAD_FOR_OPERAND_ADDRESS reloads.
7284 After the insn being reloaded, we write the following:
7286 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7287 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7288 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7289 reloads for the operand. The RELOAD_OTHER output reloads are
7290 output in descending order by reload number. */
7292 emit_insns_before (other_input_address_reload_insns
, insn
);
7293 emit_insns_before (other_input_reload_insns
, insn
);
7295 for (j
= 0; j
< reload_n_operands
; j
++)
7297 emit_insns_before (inpaddr_address_reload_insns
[j
], insn
);
7298 emit_insns_before (input_address_reload_insns
[j
], insn
);
7299 emit_insns_before (input_reload_insns
[j
], insn
);
7302 emit_insns_before (other_operand_reload_insns
, insn
);
7303 emit_insns_before (operand_reload_insns
, insn
);
7305 for (j
= 0; j
< reload_n_operands
; j
++)
7307 emit_insns_before (outaddr_address_reload_insns
[j
], following_insn
);
7308 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
7309 emit_insns_before (output_reload_insns
[j
], following_insn
);
7310 emit_insns_before (other_output_reload_insns
[j
], following_insn
);
7313 /* Keep basic block info up to date. */
7316 if (basic_block_head
[chain
->block
] == insn
)
7317 basic_block_head
[chain
->block
] = NEXT_INSN (before_insn
);
7318 if (basic_block_end
[chain
->block
] == insn
)
7319 basic_block_end
[chain
->block
] = PREV_INSN (following_insn
);
7322 /* For all the spill regs newly reloaded in this instruction,
7323 record what they were reloaded from, so subsequent instructions
7324 can inherit the reloads.
7326 Update spill_reg_store for the reloads of this insn.
7327 Copy the elements that were updated in the loop above. */
7329 for (j
= 0; j
< n_reloads
; j
++)
7331 register int r
= reload_order
[j
];
7332 register int i
= reload_spill_index
[r
];
7334 /* I is nonneg if this reload used a register.
7335 If reload_reg_rtx[r] is 0, this is an optional reload
7336 that we opted to ignore. */
7338 if (i
>= 0 && reload_reg_rtx
[r
] != 0)
7341 = HARD_REGNO_NREGS (i
, GET_MODE (reload_reg_rtx
[r
]));
7343 int part_reaches_end
= 0;
7344 int all_reaches_end
= 1;
7346 /* For a multi register reload, we need to check if all or part
7347 of the value lives to the end. */
7348 for (k
= 0; k
< nr
; k
++)
7350 if (reload_reg_reaches_end_p (i
+ k
, reload_opnum
[r
],
7351 reload_when_needed
[r
]))
7352 part_reaches_end
= 1;
7354 all_reaches_end
= 0;
7357 /* Ignore reloads that don't reach the end of the insn in
7359 if (all_reaches_end
)
7361 /* First, clear out memory of what used to be in this spill reg.
7362 If consecutive registers are used, clear them all. */
7364 for (k
= 0; k
< nr
; k
++)
7365 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7367 /* Maybe the spill reg contains a copy of reload_out. */
7368 if (reload_out
[r
] != 0
7369 && (GET_CODE (reload_out
[r
]) == REG
7371 || ! reload_out_reg
[r
]
7373 || GET_CODE (reload_out_reg
[r
]) == REG
))
7375 rtx out
= (GET_CODE (reload_out
[r
]) == REG
7379 /* AUTO_INC */ : XEXP (reload_in_reg
[r
], 0));
7380 register int nregno
= REGNO (out
);
7381 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7382 : HARD_REGNO_NREGS (nregno
,
7383 GET_MODE (reload_reg_rtx
[r
])));
7385 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7386 spill_reg_stored_to
[i
] = out
;
7387 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7389 /* If NREGNO is a hard register, it may occupy more than
7390 one register. If it does, say what is in the
7391 rest of the registers assuming that both registers
7392 agree on how many words the object takes. If not,
7393 invalidate the subsequent registers. */
7395 if (nregno
< FIRST_PSEUDO_REGISTER
)
7396 for (k
= 1; k
< nnr
; k
++)
7397 reg_last_reload_reg
[nregno
+ k
]
7399 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7400 REGNO (reload_reg_rtx
[r
]) + k
)
7403 /* Now do the inverse operation. */
7404 for (k
= 0; k
< nr
; k
++)
7406 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7407 reg_reloaded_contents
[i
+ k
]
7408 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7411 reg_reloaded_insn
[i
+ k
] = insn
;
7412 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7416 /* Maybe the spill reg contains a copy of reload_in. Only do
7417 something if there will not be an output reload for
7418 the register being reloaded. */
7419 else if (reload_out_reg
[r
] == 0
7420 && reload_in
[r
] != 0
7421 && ((GET_CODE (reload_in
[r
]) == REG
7422 && REGNO (reload_in
[r
]) >= FIRST_PSEUDO_REGISTER
7423 && ! reg_has_output_reload
[REGNO (reload_in
[r
])])
7424 || (GET_CODE (reload_in_reg
[r
]) == REG
7425 && ! reg_has_output_reload
[REGNO (reload_in_reg
[r
])]))
7426 && ! reg_set_p (reload_reg_rtx
[r
], PATTERN (insn
)))
7428 register int nregno
;
7431 if (GET_CODE (reload_in
[r
]) == REG
7432 && REGNO (reload_in
[r
]) >= FIRST_PSEUDO_REGISTER
)
7433 nregno
= REGNO (reload_in
[r
]);
7434 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
7435 nregno
= REGNO (reload_in_reg
[r
]);
7437 nregno
= REGNO (XEXP (reload_in_reg
[r
], 0));
7439 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7440 : HARD_REGNO_NREGS (nregno
,
7441 GET_MODE (reload_reg_rtx
[r
])));
7443 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7445 if (nregno
< FIRST_PSEUDO_REGISTER
)
7446 for (k
= 1; k
< nnr
; k
++)
7447 reg_last_reload_reg
[nregno
+ k
]
7449 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7450 REGNO (reload_reg_rtx
[r
]) + k
)
7453 /* Unless we inherited this reload, show we haven't
7454 recently done a store.
7455 Previous stores of inherited auto_inc expressions
7456 also have to be discarded. */
7457 if (! reload_inherited
[r
]
7458 || (reload_out
[r
] && ! reload_out_reg
[r
]))
7459 spill_reg_store
[i
] = 0;
7461 for (k
= 0; k
< nr
; k
++)
7463 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7464 reg_reloaded_contents
[i
+ k
]
7465 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7468 reg_reloaded_insn
[i
+ k
] = insn
;
7469 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7474 /* However, if part of the reload reaches the end, then we must
7475 invalidate the old info for the part that survives to the end. */
7476 else if (part_reaches_end
)
7478 for (k
= 0; k
< nr
; k
++)
7479 if (reload_reg_reaches_end_p (i
+ k
,
7481 reload_when_needed
[r
]))
7482 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7486 /* The following if-statement was #if 0'd in 1.34 (or before...).
7487 It's reenabled in 1.35 because supposedly nothing else
7488 deals with this problem. */
7490 /* If a register gets output-reloaded from a non-spill register,
7491 that invalidates any previous reloaded copy of it.
7492 But forget_old_reloads_1 won't get to see it, because
7493 it thinks only about the original insn. So invalidate it here. */
7494 if (i
< 0 && reload_out
[r
] != 0
7495 && (GET_CODE (reload_out
[r
]) == REG
7496 || (GET_CODE (reload_out
[r
]) == MEM
7497 && GET_CODE (reload_out_reg
[r
]) == REG
)))
7499 rtx out
= (GET_CODE (reload_out
[r
]) == REG
7500 ? reload_out
[r
] : reload_out_reg
[r
]);
7501 register int nregno
= REGNO (out
);
7502 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7504 rtx src_reg
, store_insn
;
7506 reg_last_reload_reg
[nregno
] = 0;
7508 /* If we can find a hard register that is stored, record
7509 the storing insn so that we may delete this insn with
7510 delete_output_reload. */
7511 src_reg
= reload_reg_rtx
[r
];
7513 /* If this is an optional reload, try to find the source reg
7514 from an input reload. */
7517 rtx set
= single_set (insn
);
7518 if (SET_DEST (set
) == reload_out
[r
])
7522 src_reg
= SET_SRC (set
);
7524 for (k
= 0; k
< n_reloads
; k
++)
7526 if (reload_in
[k
] == src_reg
)
7528 src_reg
= reload_reg_rtx
[k
];
7535 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7536 if (src_reg
&& GET_CODE (src_reg
) == REG
7537 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7539 int src_regno
= REGNO (src_reg
);
7540 int nr
= HARD_REGNO_NREGS (src_regno
, reload_mode
[r
]);
7541 /* The place where to find a death note varies with
7542 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7543 necessarily checked exactly in the code that moves
7544 notes, so just check both locations. */
7545 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7547 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7550 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7551 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7552 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7553 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7554 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7555 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7557 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7559 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7561 reg_last_reload_reg
[nregno
] = src_reg
;
7566 int num_regs
= HARD_REGNO_NREGS (nregno
,GET_MODE (reload_out
[r
]));
7568 while (num_regs
-- > 0)
7569 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7573 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7576 /* Emit code to perform a reload from IN (which may be a reload register) to
7577 OUT (which may also be a reload register). IN or OUT is from operand
7578 OPNUM with reload type TYPE.
7580 Returns first insn emitted. */
7583 gen_reload (out
, in
, opnum
, type
)
7587 enum reload_type type
;
7589 rtx last
= get_last_insn ();
7592 /* If IN is a paradoxical SUBREG, remove it and try to put the
7593 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7594 if (GET_CODE (in
) == SUBREG
7595 && (GET_MODE_SIZE (GET_MODE (in
))
7596 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7597 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7598 in
= SUBREG_REG (in
), out
= tem
;
7599 else if (GET_CODE (out
) == SUBREG
7600 && (GET_MODE_SIZE (GET_MODE (out
))
7601 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7602 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7603 out
= SUBREG_REG (out
), in
= tem
;
7605 /* How to do this reload can get quite tricky. Normally, we are being
7606 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7607 register that didn't get a hard register. In that case we can just
7608 call emit_move_insn.
7610 We can also be asked to reload a PLUS that adds a register or a MEM to
7611 another register, constant or MEM. This can occur during frame pointer
7612 elimination and while reloading addresses. This case is handled by
7613 trying to emit a single insn to perform the add. If it is not valid,
7614 we use a two insn sequence.
7616 Finally, we could be called to handle an 'o' constraint by putting
7617 an address into a register. In that case, we first try to do this
7618 with a named pattern of "reload_load_address". If no such pattern
7619 exists, we just emit a SET insn and hope for the best (it will normally
7620 be valid on machines that use 'o').
7622 This entire process is made complex because reload will never
7623 process the insns we generate here and so we must ensure that
7624 they will fit their constraints and also by the fact that parts of
7625 IN might be being reloaded separately and replaced with spill registers.
7626 Because of this, we are, in some sense, just guessing the right approach
7627 here. The one listed above seems to work.
7629 ??? At some point, this whole thing needs to be rethought. */
7631 if (GET_CODE (in
) == PLUS
7632 && (GET_CODE (XEXP (in
, 0)) == REG
7633 || GET_CODE (XEXP (in
, 0)) == SUBREG
7634 || GET_CODE (XEXP (in
, 0)) == MEM
)
7635 && (GET_CODE (XEXP (in
, 1)) == REG
7636 || GET_CODE (XEXP (in
, 1)) == SUBREG
7637 || CONSTANT_P (XEXP (in
, 1))
7638 || GET_CODE (XEXP (in
, 1)) == MEM
))
7640 /* We need to compute the sum of a register or a MEM and another
7641 register, constant, or MEM, and put it into the reload
7642 register. The best possible way of doing this is if the machine
7643 has a three-operand ADD insn that accepts the required operands.
7645 The simplest approach is to try to generate such an insn and see if it
7646 is recognized and matches its constraints. If so, it can be used.
7648 It might be better not to actually emit the insn unless it is valid,
7649 but we need to pass the insn as an operand to `recog' and
7650 `insn_extract' and it is simpler to emit and then delete the insn if
7651 not valid than to dummy things up. */
7653 rtx op0
, op1
, tem
, insn
;
7656 op0
= find_replacement (&XEXP (in
, 0));
7657 op1
= find_replacement (&XEXP (in
, 1));
7659 /* Since constraint checking is strict, commutativity won't be
7660 checked, so we need to do that here to avoid spurious failure
7661 if the add instruction is two-address and the second operand
7662 of the add is the same as the reload reg, which is frequently
7663 the case. If the insn would be A = B + A, rearrange it so
7664 it will be A = A + B as constrain_operands expects. */
7666 if (GET_CODE (XEXP (in
, 1)) == REG
7667 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7668 tem
= op0
, op0
= op1
, op1
= tem
;
7670 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7671 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7673 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7674 code
= recog_memoized (insn
);
7678 insn_extract (insn
);
7679 /* We want constrain operands to treat this insn strictly in
7680 its validity determination, i.e., the way it would after reload
7682 if (constrain_operands (code
, 1))
7686 delete_insns_since (last
);
7688 /* If that failed, we must use a conservative two-insn sequence.
7689 use move to copy constant, MEM, or pseudo register to the reload
7690 register since "move" will be able to handle an arbitrary operand,
7691 unlike add which can't, in general. Then add the registers.
7693 If there is another way to do this for a specific machine, a
7694 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7697 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7698 || (GET_CODE (op1
) == REG
7699 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
))
7700 tem
= op0
, op0
= op1
, op1
= tem
;
7702 gen_reload (out
, op0
, opnum
, type
);
7704 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7705 This fixes a problem on the 32K where the stack pointer cannot
7706 be used as an operand of an add insn. */
7708 if (rtx_equal_p (op0
, op1
))
7711 insn
= emit_insn (gen_add2_insn (out
, op1
));
7713 /* If that failed, copy the address register to the reload register.
7714 Then add the constant to the reload register. */
7716 code
= recog_memoized (insn
);
7720 insn_extract (insn
);
7721 /* We want constrain operands to treat this insn strictly in
7722 its validity determination, i.e., the way it would after reload
7724 if (constrain_operands (code
, 1))
7726 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7728 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7733 delete_insns_since (last
);
7735 gen_reload (out
, op1
, opnum
, type
);
7736 insn
= emit_insn (gen_add2_insn (out
, op0
));
7737 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7740 #ifdef SECONDARY_MEMORY_NEEDED
7741 /* If we need a memory location to do the move, do it that way. */
7742 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
7743 && GET_CODE (out
) == REG
&& REGNO (out
) < FIRST_PSEUDO_REGISTER
7744 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
7745 REGNO_REG_CLASS (REGNO (out
)),
7748 /* Get the memory to use and rewrite both registers to its mode. */
7749 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7751 if (GET_MODE (loc
) != GET_MODE (out
))
7752 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7754 if (GET_MODE (loc
) != GET_MODE (in
))
7755 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7757 gen_reload (loc
, in
, opnum
, type
);
7758 gen_reload (out
, loc
, opnum
, type
);
7762 /* If IN is a simple operand, use gen_move_insn. */
7763 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7764 emit_insn (gen_move_insn (out
, in
));
7766 #ifdef HAVE_reload_load_address
7767 else if (HAVE_reload_load_address
)
7768 emit_insn (gen_reload_load_address (out
, in
));
7771 /* Otherwise, just write (set OUT IN) and hope for the best. */
7773 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7775 /* Return the first insn emitted.
7776 We can not just return get_last_insn, because there may have
7777 been multiple instructions emitted. Also note that gen_move_insn may
7778 emit more than one insn itself, so we can not assume that there is one
7779 insn emitted per emit_insn_before call. */
7781 return last
? NEXT_INSN (last
) : get_insns ();
7784 /* Delete a previously made output-reload
7785 whose result we now believe is not needed.
7786 First we double-check.
7788 INSN is the insn now being processed.
7789 LAST_RELOAD_REG is the hard register number for which we want to delete
7790 the last output reload.
7791 J is the reload-number that originally used REG. The caller has made
7792 certain that reload J doesn't use REG any longer for input. */
7795 delete_output_reload (insn
, j
, last_reload_reg
)
7798 int last_reload_reg
;
7800 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7801 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7804 int n_inherited
= 0;
7808 /* Get the raw pseudo-register referred to. */
7810 while (GET_CODE (reg
) == SUBREG
)
7811 reg
= SUBREG_REG (reg
);
7812 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7814 /* This is unsafe if the operand occurs more often in the current
7815 insn than it is inherited. */
7816 for (k
= n_reloads
- 1; k
>= 0; k
--)
7818 rtx reg2
= reload_in
[k
];
7821 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
7822 reg2
= reload_in_reg
[k
];
7824 if (reload_out
[k
] && ! reload_out_reg
[k
])
7825 reg2
= XEXP (reload_in_reg
[k
], 0);
7827 while (GET_CODE (reg2
) == SUBREG
)
7828 reg2
= SUBREG_REG (reg2
);
7829 if (rtx_equal_p (reg2
, reg
))
7830 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7833 reg2
= reload_out_reg
[k
];
7836 while (GET_CODE (reg2
) == SUBREG
)
7837 reg2
= XEXP (reg2
, 0);
7838 if (rtx_equal_p (reg2
, reg
))
7844 n_occurrences
= count_occurrences (PATTERN (insn
), reg
);
7846 n_occurrences
+= count_occurrences (PATTERN (insn
), substed
);
7847 if (n_occurrences
> n_inherited
)
7850 /* If the pseudo-reg we are reloading is no longer referenced
7851 anywhere between the store into it and here,
7852 and no jumps or labels intervene, then the value can get
7853 here through the reload reg alone.
7854 Otherwise, give up--return. */
7855 for (i1
= NEXT_INSN (output_reload_insn
);
7856 i1
!= insn
; i1
= NEXT_INSN (i1
))
7858 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7860 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7861 && reg_mentioned_p (reg
, PATTERN (i1
)))
7863 /* If this is USE in front of INSN, we only have to check that
7864 there are no more references than accounted for by inheritance. */
7865 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
7867 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7868 i1
= NEXT_INSN (i1
);
7870 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7876 /* The caller has already checked that REG dies or is set in INSN.
7877 It has also checked that we are optimizing, and thus some inaccurancies
7878 in the debugging information are acceptable.
7879 So we could just delete output_reload_insn.
7880 But in some cases we can improve the debugging information without
7881 sacrificing optimization - maybe even improving the code:
7882 See if the pseudo reg has been completely replaced
7883 with reload regs. If so, delete the store insn
7884 and forget we had a stack slot for the pseudo. */
7885 if (reload_out
[j
] != reload_in
[j
]
7886 && REG_N_DEATHS (REGNO (reg
)) == 1
7887 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7888 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7892 /* We know that it was used only between here
7893 and the beginning of the current basic block.
7894 (We also know that the last use before INSN was
7895 the output reload we are thinking of deleting, but never mind that.)
7896 Search that range; see if any ref remains. */
7897 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7899 rtx set
= single_set (i2
);
7901 /* Uses which just store in the pseudo don't count,
7902 since if they are the only uses, they are dead. */
7903 if (set
!= 0 && SET_DEST (set
) == reg
)
7905 if (GET_CODE (i2
) == CODE_LABEL
7906 || GET_CODE (i2
) == JUMP_INSN
)
7908 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
7909 && reg_mentioned_p (reg
, PATTERN (i2
)))
7911 /* Some other ref remains; just delete the output reload we
7913 delete_address_reloads (output_reload_insn
, insn
);
7914 PUT_CODE (output_reload_insn
, NOTE
);
7915 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7916 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7921 /* Delete the now-dead stores into this pseudo. */
7922 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7924 rtx set
= single_set (i2
);
7926 if (set
!= 0 && SET_DEST (set
) == reg
)
7928 delete_address_reloads (i2
, insn
);
7929 /* This might be a basic block head,
7930 thus don't use delete_insn. */
7931 PUT_CODE (i2
, NOTE
);
7932 NOTE_SOURCE_FILE (i2
) = 0;
7933 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
7935 if (GET_CODE (i2
) == CODE_LABEL
7936 || GET_CODE (i2
) == JUMP_INSN
)
7940 /* For the debugging info,
7941 say the pseudo lives in this reload reg. */
7942 reg_renumber
[REGNO (reg
)] = REGNO (reload_reg_rtx
[j
]);
7943 alter_reg (REGNO (reg
), -1);
7945 delete_address_reloads (output_reload_insn
, insn
);
7946 PUT_CODE (output_reload_insn
, NOTE
);
7947 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7948 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7952 /* We are going to delete DEAD_INSN. Recursively delete loads of
7953 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7954 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7956 delete_address_reloads (dead_insn
, current_insn
)
7957 rtx dead_insn
, current_insn
;
7959 rtx set
= single_set (dead_insn
);
7960 rtx set2
, dst
, prev
, next
;
7963 rtx dst
= SET_DEST (set
);
7964 if (GET_CODE (dst
) == MEM
)
7965 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7967 /* If we deleted the store from a reloaded post_{in,de}c expression,
7968 we can delete the matching adds. */
7969 prev
= PREV_INSN (dead_insn
);
7970 next
= NEXT_INSN (dead_insn
);
7971 if (! prev
|| ! next
)
7973 set
= single_set (next
);
7974 set2
= single_set (prev
);
7976 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7977 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7978 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7980 dst
= SET_DEST (set
);
7981 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7982 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7983 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7984 || (INTVAL (XEXP (SET_SRC (set
), 1))
7985 != - INTVAL (XEXP (SET_SRC (set2
), 1))))
7991 /* Subfunction of delete_address_reloads: process registers found in X. */
7993 delete_address_reloads_1 (dead_insn
, x
, current_insn
)
7994 rtx dead_insn
, x
, current_insn
;
7996 rtx prev
, set
, dst
, i2
;
7998 enum rtx_code code
= GET_CODE (x
);
8002 char *fmt
= GET_RTX_FORMAT (code
);
8003 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8006 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8007 else if (fmt
[i
] == 'E')
8009 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
8010 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8017 if (spill_reg_order
[REGNO (x
)] < 0)
8020 /* Scan backwards for the insn that sets x. This might be a way back due
8022 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8024 code
= GET_CODE (prev
);
8025 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8027 if (GET_RTX_CLASS (code
) != 'i')
8029 if (reg_set_p (x
, PATTERN (prev
)))
8031 if (reg_referenced_p (x
, PATTERN (prev
)))
8034 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8036 /* Check that PREV only sets the reload register. */
8037 set
= single_set (prev
);
8040 dst
= SET_DEST (set
);
8041 if (GET_CODE (dst
) != REG
8042 || ! rtx_equal_p (dst
, x
))
8044 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8046 /* Check if DST was used in a later insn -
8047 it might have been inherited. */
8048 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8050 if (GET_CODE (i2
) == CODE_LABEL
)
8052 if (GET_RTX_CLASS (GET_CODE (i2
)) != 'i')
8054 if (reg_referenced_p (dst
, PATTERN (i2
)))
8056 /* If there is a reference to the register in the current insn,
8057 it might be loaded in a non-inherited reload. If no other
8058 reload uses it, that means the register is set before
8060 if (i2
== current_insn
)
8062 for (j
= n_reloads
- 1; j
>= 0; j
--)
8063 if ((reload_reg_rtx
[j
] == dst
&& reload_inherited
[j
])
8064 || reload_override_in
[j
] == dst
)
8066 for (j
= n_reloads
- 1; j
>= 0; j
--)
8067 if (reload_in
[j
] && reload_reg_rtx
[j
] == dst
)
8074 if (GET_CODE (i2
) == JUMP_INSN
)
8076 if (reg_set_p (dst
, PATTERN (i2
)))
8078 /* If DST is still live at CURRENT_INSN, check if it is used for
8080 if (i2
== current_insn
)
8082 for (j
= n_reloads
- 1; j
>= 0; j
--)
8083 if ((reload_reg_rtx
[j
] == dst
&& reload_inherited
[j
])
8084 || reload_override_in
[j
] == dst
)
8086 /* ??? We can't finish the loop here, because dst might be
8087 allocated to a pseudo in this block if no reload in this
8088 block needs any of the clsses containing DST - see
8089 spill_hard_reg. There is no easy way to tell this, so we
8090 have to scan till the end of the basic block. */
8094 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8095 reg_reloaded_contents
[REGNO (dst
)] = -1;
8096 /* Can't use delete_insn here because PREV might be a basic block head. */
8097 PUT_CODE (prev
, NOTE
);
8098 NOTE_LINE_NUMBER (prev
) = NOTE_INSN_DELETED
;
8099 NOTE_SOURCE_FILE (prev
) = 0;
8102 /* Output reload-insns to reload VALUE into RELOADREG.
8103 VALUE is an autoincrement or autodecrement RTX whose operand
8104 is a register or memory location;
8105 so reloading involves incrementing that location.
8106 IN is either identical to VALUE, or some cheaper place to reload from.
8108 INC_AMOUNT is the number to increment or decrement by (always positive).
8109 This cannot be deduced from VALUE.
8111 Return the instruction that stores into RELOADREG. */
8114 inc_for_reload (reloadreg
, in
, value
, inc_amount
)
8119 /* REG or MEM to be copied and incremented. */
8120 rtx incloc
= XEXP (value
, 0);
8121 /* Nonzero if increment after copying. */
8122 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
8128 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
8130 /* No hard register is equivalent to this register after
8131 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8132 we could inc/dec that register as well (maybe even using it for
8133 the source), but I'm not sure it's worth worrying about. */
8134 if (GET_CODE (incloc
) == REG
)
8135 reg_last_reload_reg
[REGNO (incloc
)] = 0;
8137 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
8138 inc_amount
= - inc_amount
;
8140 inc
= GEN_INT (inc_amount
);
8142 /* If this is post-increment, first copy the location to the reload reg. */
8143 if (post
&& real_in
!= reloadreg
)
8144 emit_insn (gen_move_insn (reloadreg
, real_in
));
8148 /* See if we can directly increment INCLOC. Use a method similar to
8149 that in gen_reload. */
8151 last
= get_last_insn ();
8152 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
8153 gen_rtx_PLUS (GET_MODE (incloc
),
8156 code
= recog_memoized (add_insn
);
8159 insn_extract (add_insn
);
8160 if (constrain_operands (code
, 1))
8162 /* If this is a pre-increment and we have incremented the value
8163 where it lives, copy the incremented value to RELOADREG to
8164 be used as an address. */
8167 emit_insn (gen_move_insn (reloadreg
, incloc
));
8172 delete_insns_since (last
);
8175 /* If couldn't do the increment directly, must increment in RELOADREG.
8176 The way we do this depends on whether this is pre- or post-increment.
8177 For pre-increment, copy INCLOC to the reload register, increment it
8178 there, then save back. */
8182 if (in
!= reloadreg
)
8183 emit_insn (gen_move_insn (reloadreg
, real_in
));
8184 emit_insn (gen_add2_insn (reloadreg
, inc
));
8185 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8190 Because this might be a jump insn or a compare, and because RELOADREG
8191 may not be available after the insn in an input reload, we must do
8192 the incrementation before the insn being reloaded for.
8194 We have already copied IN to RELOADREG. Increment the copy in
8195 RELOADREG, save that back, then decrement RELOADREG so it has
8196 the original value. */
8198 emit_insn (gen_add2_insn (reloadreg
, inc
));
8199 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8200 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
8206 /* Return 1 if we are certain that the constraint-string STRING allows
8207 the hard register REG. Return 0 if we can't be sure of this. */
8210 constraint_accepts_reg_p (string
, reg
)
8215 int regno
= true_regnum (reg
);
8218 /* Initialize for first alternative. */
8220 /* Check that each alternative contains `g' or `r'. */
8222 switch (c
= *string
++)
8225 /* If an alternative lacks `g' or `r', we lose. */
8228 /* If an alternative lacks `g' or `r', we lose. */
8231 /* Initialize for next alternative. */
8236 /* Any general reg wins for this alternative. */
8237 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
8241 /* Any reg in specified class wins for this alternative. */
8243 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
8245 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
8251 /* Return the number of places FIND appears within X, but don't count
8252 an occurrence if some SET_DEST is FIND. */
8255 count_occurrences (x
, find
)
8256 register rtx x
, find
;
8259 register enum rtx_code code
;
8260 register char *format_ptr
;
8268 code
= GET_CODE (x
);
8283 if (GET_CODE (find
) == MEM
&& rtx_equal_p (x
, find
))
8287 if (SET_DEST (x
) == find
)
8288 return count_occurrences (SET_SRC (x
), find
);
8295 format_ptr
= GET_RTX_FORMAT (code
);
8298 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8300 switch (*format_ptr
++)
8303 count
+= count_occurrences (XEXP (x
, i
), find
);
8307 if (XVEC (x
, i
) != NULL
)
8309 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8310 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
);
8318 /* This array holds values which are equivalent to a hard register
8319 during reload_cse_regs. Each array element is an EXPR_LIST of
8320 values. Each time a hard register is set, we set the corresponding
8321 array element to the value. Each time a hard register is copied
8322 into memory, we add the memory location to the corresponding array
8323 element. We don't store values or memory addresses with side
8324 effects in this array.
8326 If the value is a CONST_INT, then the mode of the containing
8327 EXPR_LIST is the mode in which that CONST_INT was referenced.
8329 We sometimes clobber a specific entry in a list. In that case, we
8330 just set XEXP (list-entry, 0) to 0. */
8332 static rtx
*reg_values
;
8334 /* This is a preallocated REG rtx which we use as a temporary in
8335 reload_cse_invalidate_regno, so that we don't need to allocate a
8336 new one each time through a loop in that function. */
8338 static rtx invalidate_regno_rtx
;
8340 /* Invalidate any entries in reg_values which depend on REGNO,
8341 including those for REGNO itself. This is called if REGNO is
8342 changing. If CLOBBER is true, then always forget anything we
8343 currently know about REGNO. MODE is the mode of the assignment to
8344 REGNO, which is used to determine how many hard registers are being
8345 changed. If MODE is VOIDmode, then only REGNO is being changed;
8346 this is used when invalidating call clobbered registers across a
8350 reload_cse_invalidate_regno (regno
, mode
, clobber
)
8352 enum machine_mode mode
;
8358 /* Our callers don't always go through true_regnum; we may see a
8359 pseudo-register here from a CLOBBER or the like. We probably
8360 won't ever see a pseudo-register that has a real register number,
8361 for we check anyhow for safety. */
8362 if (regno
>= FIRST_PSEUDO_REGISTER
)
8363 regno
= reg_renumber
[regno
];
8367 if (mode
== VOIDmode
)
8368 endregno
= regno
+ 1;
8370 endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
8373 for (i
= regno
; i
< endregno
; i
++)
8376 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8380 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8382 if (XEXP (x
, 0) != 0
8383 && refers_to_regno_p (regno
, endregno
, XEXP (x
, 0), NULL_PTR
))
8385 /* If this is the only entry on the list, clear
8386 reg_values[i]. Otherwise, just clear this entry on
8388 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8398 /* We must look at earlier registers, in case REGNO is part of a
8399 multi word value but is not the first register. If an earlier
8400 register has a value in a mode which overlaps REGNO, then we must
8401 invalidate that earlier register. Note that we do not need to
8402 check REGNO or later registers (we must not check REGNO itself,
8403 because we would incorrectly conclude that there was a conflict). */
8405 for (i
= 0; i
< regno
; i
++)
8409 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8411 if (XEXP (x
, 0) != 0)
8413 PUT_MODE (invalidate_regno_rtx
, GET_MODE (x
));
8414 REGNO (invalidate_regno_rtx
) = i
;
8415 if (refers_to_regno_p (regno
, endregno
, invalidate_regno_rtx
,
8418 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8426 /* The memory at address MEM_BASE is being changed.
8427 Return whether this change will invalidate VAL. */
8430 reload_cse_mem_conflict_p (mem_base
, val
)
8438 code
= GET_CODE (val
);
8441 /* Get rid of a few simple cases quickly. */
8454 if (GET_MODE (mem_base
) == BLKmode
8455 || GET_MODE (val
) == BLKmode
)
8457 if (anti_dependence (val
, mem_base
))
8459 /* The address may contain nested MEMs. */
8466 fmt
= GET_RTX_FORMAT (code
);
8468 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8472 if (reload_cse_mem_conflict_p (mem_base
, XEXP (val
, i
)))
8475 else if (fmt
[i
] == 'E')
8479 for (j
= 0; j
< XVECLEN (val
, i
); j
++)
8480 if (reload_cse_mem_conflict_p (mem_base
, XVECEXP (val
, i
, j
)))
8488 /* Invalidate any entries in reg_values which are changed because of a
8489 store to MEM_RTX. If this is called because of a non-const call
8490 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8493 reload_cse_invalidate_mem (mem_rtx
)
8498 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8502 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8504 if (XEXP (x
, 0) != 0
8505 && reload_cse_mem_conflict_p (mem_rtx
, XEXP (x
, 0)))
8507 /* If this is the only entry on the list, clear
8508 reg_values[i]. Otherwise, just clear this entry on
8510 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8521 /* Invalidate DEST, which is being assigned to or clobbered. The
8522 second parameter exists so that this function can be passed to
8523 note_stores; it is ignored. */
8526 reload_cse_invalidate_rtx (dest
, ignore
)
8528 rtx ignore ATTRIBUTE_UNUSED
;
8530 while (GET_CODE (dest
) == STRICT_LOW_PART
8531 || GET_CODE (dest
) == SIGN_EXTRACT
8532 || GET_CODE (dest
) == ZERO_EXTRACT
8533 || GET_CODE (dest
) == SUBREG
)
8534 dest
= XEXP (dest
, 0);
8536 if (GET_CODE (dest
) == REG
)
8537 reload_cse_invalidate_regno (REGNO (dest
), GET_MODE (dest
), 1);
8538 else if (GET_CODE (dest
) == MEM
)
8539 reload_cse_invalidate_mem (dest
);
8542 /* Do a very simple CSE pass over the hard registers.
8544 This function detects no-op moves where we happened to assign two
8545 different pseudo-registers to the same hard register, and then
8546 copied one to the other. Reload will generate a useless
8547 instruction copying a register to itself.
8549 This function also detects cases where we load a value from memory
8550 into two different registers, and (if memory is more expensive than
8551 registers) changes it to simply copy the first register into the
8554 Another optimization is performed that scans the operands of each
8555 instruction to see whether the value is already available in a
8556 hard register. It then replaces the operand with the hard register
8557 if possible, much like an optional reload would. */
8560 reload_cse_regs_1 (first
)
8568 init_alias_analysis ();
8570 reg_values
= (rtx
*) alloca (FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8571 bzero ((char *)reg_values
, FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8573 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8574 free them when we are done. */
8575 push_obstacks (&reload_obstack
, &reload_obstack
);
8576 firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
8578 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8579 memory for a non-const call instruction. */
8580 callmem
= gen_rtx_MEM (BLKmode
, const0_rtx
);
8582 /* This is used in reload_cse_invalidate_regno to avoid consing a
8583 new REG in a loop in that function. */
8584 invalidate_regno_rtx
= gen_rtx_REG (VOIDmode
, 0);
8586 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8590 if (GET_CODE (insn
) == CODE_LABEL
)
8592 /* Forget all the register values at a code label. We don't
8593 try to do anything clever around jumps. */
8594 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8600 #ifdef NON_SAVING_SETJMP
8601 if (NON_SAVING_SETJMP
&& GET_CODE (insn
) == NOTE
8602 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
8604 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8611 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8614 /* If this is a call instruction, forget anything stored in a
8615 call clobbered register, or, if this is not a const call, in
8617 if (GET_CODE (insn
) == CALL_INSN
)
8619 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8620 if (call_used_regs
[i
])
8621 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8623 if (! CONST_CALL_P (insn
))
8624 reload_cse_invalidate_mem (callmem
);
8627 body
= PATTERN (insn
);
8628 if (GET_CODE (body
) == SET
)
8631 if (reload_cse_noop_set_p (body
, insn
))
8633 /* If this sets the return value of the function, we must keep
8634 a USE around, in case this is in a different basic block
8635 than the final USE. Otherwise, we could loose important
8636 register lifeness information on SMALL_REGISTER_CLASSES
8637 machines, where return registers might be used as spills:
8638 subsequent passes assume that spill registers are dead at
8639 the end of a basic block. */
8640 if (REG_FUNCTION_VALUE_P (SET_DEST (body
)))
8643 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, SET_DEST (body
));
8644 INSN_CODE (insn
) = -1;
8645 REG_NOTES (insn
) = NULL_RTX
;
8646 push_obstacks (&reload_obstack
, &reload_obstack
);
8650 PUT_CODE (insn
, NOTE
);
8651 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8652 NOTE_SOURCE_FILE (insn
) = 0;
8655 /* We're done with this insn. */
8659 /* It's not a no-op, but we can try to simplify it. */
8660 count
+= reload_cse_simplify_set (body
, insn
);
8663 apply_change_group ();
8665 reload_cse_simplify_operands (insn
);
8667 reload_cse_record_set (body
, body
);
8669 else if (GET_CODE (body
) == PARALLEL
)
8672 rtx value
= NULL_RTX
;
8674 /* If every action in a PARALLEL is a noop, we can delete
8675 the entire PARALLEL. */
8676 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8678 rtx part
= XVECEXP (body
, 0, i
);
8679 if (GET_CODE (part
) == SET
)
8681 if (! reload_cse_noop_set_p (part
, insn
))
8683 if (REG_FUNCTION_VALUE_P (SET_DEST (part
)))
8687 value
= SET_DEST (part
);
8690 else if (GET_CODE (part
) != CLOBBER
)
8698 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, value
);
8699 INSN_CODE (insn
) = -1;
8700 REG_NOTES (insn
) = NULL_RTX
;
8701 push_obstacks (&reload_obstack
, &reload_obstack
);
8705 PUT_CODE (insn
, NOTE
);
8706 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8707 NOTE_SOURCE_FILE (insn
) = 0;
8710 /* We're done with this insn. */
8714 /* It's not a no-op, but we can try to simplify it. */
8715 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8716 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
8717 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
8720 apply_change_group ();
8722 reload_cse_simplify_operands (insn
);
8724 /* Look through the PARALLEL and record the values being
8725 set, if possible. Also handle any CLOBBERs. */
8726 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8728 rtx x
= XVECEXP (body
, 0, i
);
8730 if (GET_CODE (x
) == SET
)
8731 reload_cse_record_set (x
, body
);
8733 note_stores (x
, reload_cse_invalidate_rtx
);
8737 note_stores (body
, reload_cse_invalidate_rtx
);
8740 /* Clobber any registers which appear in REG_INC notes. We
8741 could keep track of the changes to their values, but it is
8742 unlikely to help. */
8746 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
8747 if (REG_NOTE_KIND (x
) == REG_INC
)
8748 reload_cse_invalidate_rtx (XEXP (x
, 0), NULL_RTX
);
8752 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8753 after we have processed the insn. */
8754 if (GET_CODE (insn
) == CALL_INSN
)
8758 for (x
= CALL_INSN_FUNCTION_USAGE (insn
); x
; x
= XEXP (x
, 1))
8759 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
8760 reload_cse_invalidate_rtx (XEXP (XEXP (x
, 0), 0), NULL_RTX
);
8764 /* Free all the temporary structures we created, and go back to the
8765 regular obstacks. */
8766 obstack_free (&reload_obstack
, firstobj
);
8770 /* Call cse / combine like post-reload optimization phases.
8771 FIRST is the first instruction. */
8773 reload_cse_regs (first
)
8776 reload_cse_regs_1 (first
);
8778 reload_cse_move2add (first
);
8779 if (flag_expensive_optimizations
)
8780 reload_cse_regs_1 (first
);
8783 /* Return whether the values known for REGNO are equal to VAL. MODE
8784 is the mode of the object that VAL is being copied to; this matters
8785 if VAL is a CONST_INT. */
8788 reload_cse_regno_equal_p (regno
, val
, mode
)
8791 enum machine_mode mode
;
8798 for (x
= reg_values
[regno
]; x
; x
= XEXP (x
, 1))
8799 if (XEXP (x
, 0) != 0
8800 && rtx_equal_p (XEXP (x
, 0), val
)
8801 && (! flag_float_store
|| GET_CODE (XEXP (x
, 0)) != MEM
8802 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
8803 && (GET_CODE (val
) != CONST_INT
8804 || mode
== GET_MODE (x
)
8805 || (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8806 /* On a big endian machine if the value spans more than
8807 one register then this register holds the high part of
8808 it and we can't use it.
8810 ??? We should also compare with the high part of the
8812 && !(WORDS_BIG_ENDIAN
8813 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
8814 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
8815 GET_MODE_BITSIZE (GET_MODE (x
))))))
8821 /* See whether a single set is a noop. SET is the set instruction we
8822 are should check, and INSN is the instruction from which it came. */
8825 reload_cse_noop_set_p (set
, insn
)
8830 enum machine_mode dest_mode
;
8834 src
= SET_SRC (set
);
8835 dest
= SET_DEST (set
);
8836 dest_mode
= GET_MODE (dest
);
8838 if (side_effects_p (src
))
8841 dreg
= true_regnum (dest
);
8842 sreg
= true_regnum (src
);
8844 /* Check for setting a register to itself. In this case, we don't
8845 have to worry about REG_DEAD notes. */
8846 if (dreg
>= 0 && dreg
== sreg
)
8852 /* Check for setting a register to itself. */
8856 /* Check for setting a register to a value which we already know
8857 is in the register. */
8858 else if (reload_cse_regno_equal_p (dreg
, src
, dest_mode
))
8861 /* Check for setting a register DREG to another register SREG
8862 where SREG is equal to a value which is already in DREG. */
8867 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
8871 if (XEXP (x
, 0) == 0)
8874 if (dest_mode
== GET_MODE (x
))
8876 else if (GET_MODE_BITSIZE (dest_mode
)
8877 < GET_MODE_BITSIZE (GET_MODE (x
)))
8878 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
8883 && reload_cse_regno_equal_p (dreg
, tmp
, dest_mode
))
8891 else if (GET_CODE (dest
) == MEM
)
8893 /* Check for storing a register to memory when we know that the
8894 register is equivalent to the memory location. */
8896 && reload_cse_regno_equal_p (sreg
, dest
, dest_mode
)
8897 && ! side_effects_p (dest
))
8904 /* Try to simplify a single SET instruction. SET is the set pattern.
8905 INSN is the instruction it came from.
8906 This function only handles one case: if we set a register to a value
8907 which is not a register, we try to find that value in some other register
8908 and change the set into a register copy. */
8911 reload_cse_simplify_set (set
, insn
)
8917 enum machine_mode dest_mode
;
8918 enum reg_class dclass
;
8921 dreg
= true_regnum (SET_DEST (set
));
8925 src
= SET_SRC (set
);
8926 if (side_effects_p (src
) || true_regnum (src
) >= 0)
8929 dclass
= REGNO_REG_CLASS (dreg
);
8931 /* If memory loads are cheaper than register copies, don't change them. */
8932 if (GET_CODE (src
) == MEM
8933 && MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1) < 2)
8936 /* If the constant is cheaper than a register, don't change it. */
8937 if (CONSTANT_P (src
)
8938 && rtx_cost (src
, SET
) < 2)
8941 dest_mode
= GET_MODE (SET_DEST (set
));
8942 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8945 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i
), dclass
) == 2
8946 && reload_cse_regno_equal_p (i
, src
, dest_mode
))
8950 /* Pop back to the real obstacks while changing the insn. */
8953 validated
= validate_change (insn
, &SET_SRC (set
),
8954 gen_rtx_REG (dest_mode
, i
), 1);
8956 /* Go back to the obstack we are using for temporary
8958 push_obstacks (&reload_obstack
, &reload_obstack
);
8967 /* Try to replace operands in INSN with equivalent values that are already
8968 in registers. This can be viewed as optional reloading.
8970 For each non-register operand in the insn, see if any hard regs are
8971 known to be equivalent to that operand. Record the alternatives which
8972 can accept these hard registers. Among all alternatives, select the
8973 ones which are better or equal to the one currently matching, where
8974 "better" is in terms of '?' and '!' constraints. Among the remaining
8975 alternatives, select the one which replaces most operands with
8979 reload_cse_simplify_operands (insn
)
8982 #ifdef REGISTER_CONSTRAINTS
8983 int insn_code_number
, n_operands
, n_alternatives
;
8986 char *constraints
[MAX_RECOG_OPERANDS
];
8988 /* Vector recording how bad an alternative is. */
8989 int *alternative_reject
;
8990 /* Vector recording how many registers can be introduced by choosing
8991 this alternative. */
8992 int *alternative_nregs
;
8993 /* Array of vectors recording, for each operand and each alternative,
8994 which hard register to substitute, or -1 if the operand should be
8996 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
8997 /* Array of alternatives, sorted in order of decreasing desirability. */
8998 int *alternative_order
;
8999 rtx reg
= gen_rtx_REG (VOIDmode
, -1);
9001 /* Find out some information about this insn. */
9002 insn_code_number
= recog_memoized (insn
);
9003 /* We don't modify asm instructions. */
9004 if (insn_code_number
< 0)
9007 n_operands
= insn_n_operands
[insn_code_number
];
9008 n_alternatives
= insn_n_alternatives
[insn_code_number
];
9010 if (n_alternatives
== 0 || n_operands
== 0)
9012 insn_extract (insn
);
9014 /* Figure out which alternative currently matches. */
9015 if (! constrain_operands (insn_code_number
, 1))
9016 fatal_insn_not_found (insn
);
9018 alternative_reject
= (int *) alloca (n_alternatives
* sizeof (int));
9019 alternative_nregs
= (int *) alloca (n_alternatives
* sizeof (int));
9020 alternative_order
= (int *) alloca (n_alternatives
* sizeof (int));
9021 bzero ((char *)alternative_reject
, n_alternatives
* sizeof (int));
9022 bzero ((char *)alternative_nregs
, n_alternatives
* sizeof (int));
9024 for (i
= 0; i
< n_operands
; i
++)
9026 enum machine_mode mode
;
9030 op_alt_regno
[i
] = (int *) alloca (n_alternatives
* sizeof (int));
9031 for (j
= 0; j
< n_alternatives
; j
++)
9032 op_alt_regno
[i
][j
] = -1;
9034 p
= constraints
[i
] = insn_operand_constraint
[insn_code_number
][i
];
9035 mode
= insn_operand_mode
[insn_code_number
][i
];
9037 /* Add the reject values for each alternative given by the constraints
9038 for this operand. */
9046 alternative_reject
[j
] += 3;
9048 alternative_reject
[j
] += 300;
9051 /* We won't change operands which are already registers. We
9052 also don't want to modify output operands. */
9053 regno
= true_regnum (recog_operand
[i
]);
9055 || constraints
[i
][0] == '='
9056 || constraints
[i
][0] == '+')
9059 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
9061 int class = (int) NO_REGS
;
9063 if (! reload_cse_regno_equal_p (regno
, recog_operand
[i
], mode
))
9066 REGNO (reg
) = regno
;
9067 PUT_MODE (reg
, mode
);
9069 /* We found a register equal to this operand. Now look for all
9070 alternatives that can accept this register and have not been
9071 assigned a register they can use yet. */
9080 case '=': case '+': case '?':
9081 case '#': case '&': case '!':
9083 case '0': case '1': case '2': case '3': case '4':
9084 case 'm': case '<': case '>': case 'V': case 'o':
9085 case 'E': case 'F': case 'G': case 'H':
9086 case 's': case 'i': case 'n':
9087 case 'I': case 'J': case 'K': case 'L':
9088 case 'M': case 'N': case 'O': case 'P':
9089 #ifdef EXTRA_CONSTRAINT
9090 case 'Q': case 'R': case 'S': case 'T': case 'U':
9093 /* These don't say anything we care about. */
9097 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
9102 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
9105 case ',': case '\0':
9106 /* See if REGNO fits this alternative, and set it up as the
9107 replacement register if we don't have one for this
9108 alternative yet and the operand being replaced is not
9109 a cheap CONST_INT. */
9110 if (op_alt_regno
[i
][j
] == -1
9111 && reg_fits_class_p (reg
, class, 0, mode
)
9112 && (GET_CODE (recog_operand
[i
]) != CONST_INT
9113 || rtx_cost (recog_operand
[i
], SET
) > rtx_cost (reg
, SET
)))
9115 alternative_nregs
[j
]++;
9116 op_alt_regno
[i
][j
] = regno
;
9128 /* Record all alternatives which are better or equal to the currently
9129 matching one in the alternative_order array. */
9130 for (i
= j
= 0; i
< n_alternatives
; i
++)
9131 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
9132 alternative_order
[j
++] = i
;
9135 /* Sort it. Given a small number of alternatives, a dumb algorithm
9136 won't hurt too much. */
9137 for (i
= 0; i
< n_alternatives
- 1; i
++)
9140 int best_reject
= alternative_reject
[alternative_order
[i
]];
9141 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
9144 for (j
= i
+ 1; j
< n_alternatives
; j
++)
9146 int this_reject
= alternative_reject
[alternative_order
[j
]];
9147 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
9149 if (this_reject
< best_reject
9150 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
9153 best_reject
= this_reject
;
9154 best_nregs
= this_nregs
;
9158 tmp
= alternative_order
[best
];
9159 alternative_order
[best
] = alternative_order
[i
];
9160 alternative_order
[i
] = tmp
;
9163 /* Substitute the operands as determined by op_alt_regno for the best
9165 j
= alternative_order
[0];
9167 /* Pop back to the real obstacks while changing the insn. */
9170 for (i
= 0; i
< n_operands
; i
++)
9172 enum machine_mode mode
= insn_operand_mode
[insn_code_number
][i
];
9173 if (op_alt_regno
[i
][j
] == -1)
9176 validate_change (insn
, recog_operand_loc
[i
],
9177 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
9180 for (i
= insn_n_dups
[insn_code_number
] - 1; i
>= 0; i
--)
9182 int op
= recog_dup_num
[i
];
9183 enum machine_mode mode
= insn_operand_mode
[insn_code_number
][op
];
9185 if (op_alt_regno
[op
][j
] == -1)
9188 validate_change (insn
, recog_dup_loc
[i
],
9189 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
9192 /* Go back to the obstack we are using for temporary
9194 push_obstacks (&reload_obstack
, &reload_obstack
);
9196 return apply_change_group ();
9202 /* These two variables are used to pass information from
9203 reload_cse_record_set to reload_cse_check_clobber. */
9205 static int reload_cse_check_clobbered
;
9206 static rtx reload_cse_check_src
;
9208 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9209 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9210 second argument, which is passed by note_stores, is ignored. */
9213 reload_cse_check_clobber (dest
, ignore
)
9215 rtx ignore ATTRIBUTE_UNUSED
;
9217 if (reg_overlap_mentioned_p (dest
, reload_cse_check_src
))
9218 reload_cse_check_clobbered
= 1;
9221 /* Record the result of a SET instruction. SET is the set pattern.
9222 BODY is the pattern of the insn that it came from. */
9225 reload_cse_record_set (set
, body
)
9231 enum machine_mode dest_mode
;
9233 dest
= SET_DEST (set
);
9234 src
= SET_SRC (set
);
9235 dreg
= true_regnum (dest
);
9236 sreg
= true_regnum (src
);
9237 dest_mode
= GET_MODE (dest
);
9239 /* Some machines don't define AUTO_INC_DEC, but they still use push
9240 instructions. We need to catch that case here in order to
9241 invalidate the stack pointer correctly. Note that invalidating
9242 the stack pointer is different from invalidating DEST. */
9244 while (GET_CODE (x
) == SUBREG
9245 || GET_CODE (x
) == ZERO_EXTRACT
9246 || GET_CODE (x
) == SIGN_EXTRACT
9247 || GET_CODE (x
) == STRICT_LOW_PART
)
9249 if (push_operand (x
, GET_MODE (x
)))
9251 reload_cse_invalidate_rtx (stack_pointer_rtx
, NULL_RTX
);
9252 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9256 /* We can only handle an assignment to a register, or a store of a
9257 register to a memory location. For other cases, we just clobber
9258 the destination. We also have to just clobber if there are side
9259 effects in SRC or DEST. */
9260 if ((dreg
< 0 && GET_CODE (dest
) != MEM
)
9261 || side_effects_p (src
)
9262 || side_effects_p (dest
))
9264 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9269 /* We don't try to handle values involving CC, because it's a pain
9270 to keep track of when they have to be invalidated. */
9271 if (reg_mentioned_p (cc0_rtx
, src
)
9272 || reg_mentioned_p (cc0_rtx
, dest
))
9274 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9279 /* If BODY is a PARALLEL, then we need to see whether the source of
9280 SET is clobbered by some other instruction in the PARALLEL. */
9281 if (GET_CODE (body
) == PARALLEL
)
9285 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
9289 x
= XVECEXP (body
, 0, i
);
9293 reload_cse_check_clobbered
= 0;
9294 reload_cse_check_src
= src
;
9295 note_stores (x
, reload_cse_check_clobber
);
9296 if (reload_cse_check_clobbered
)
9298 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9308 /* This is an assignment to a register. Update the value we
9309 have stored for the register. */
9314 /* This is a copy from one register to another. Any values
9315 which were valid for SREG are now valid for DREG. If the
9316 mode changes, we use gen_lowpart_common to extract only
9317 the part of the value that is copied. */
9318 reg_values
[dreg
] = 0;
9319 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
9323 if (XEXP (x
, 0) == 0)
9325 if (dest_mode
== GET_MODE (XEXP (x
, 0)))
9327 else if (GET_MODE_BITSIZE (dest_mode
)
9328 > GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
9331 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
9333 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, tmp
,
9338 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, src
, NULL_RTX
);
9340 /* We've changed DREG, so invalidate any values held by other
9341 registers that depend upon it. */
9342 reload_cse_invalidate_regno (dreg
, dest_mode
, 0);
9344 /* If this assignment changes more than one hard register,
9345 forget anything we know about the others. */
9346 for (i
= 1; i
< HARD_REGNO_NREGS (dreg
, dest_mode
); i
++)
9347 reg_values
[dreg
+ i
] = 0;
9349 else if (GET_CODE (dest
) == MEM
)
9351 /* Invalidate conflicting memory locations. */
9352 reload_cse_invalidate_mem (dest
);
9354 /* If we're storing a register to memory, add DEST to the list
9356 if (sreg
>= 0 && ! side_effects_p (dest
))
9357 reg_values
[sreg
] = gen_rtx_EXPR_LIST (dest_mode
, dest
,
9362 /* We should have bailed out earlier. */
9367 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9369 This code might also be useful when reload gave up on reg+reg addresssing
9370 because of clashes between the return register and INDEX_REG_CLASS. */
9372 /* The maximum number of uses of a register we can keep track of to
9373 replace them with reg+reg addressing. */
9374 #define RELOAD_COMBINE_MAX_USES 6
9376 /* INSN is the insn where a register has ben used, and USEP points to the
9377 location of the register within the rtl. */
9378 struct reg_use
{ rtx insn
, *usep
; };
9380 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9381 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9382 indicates where it becomes live again.
9383 Otherwise, USE_INDEX is the index of the last encountered use of the
9384 register (which is first among these we have seen since we scan backwards),
9385 OFFSET contains the constant offset that is added to the register in
9386 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9387 last, of these uses. */
9390 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
9395 } reg_state
[FIRST_PSEUDO_REGISTER
];
9397 /* Reverse linear uid. This is increased in reload_combine while scanning
9398 the instructions from last to first. It is used to set last_label_ruid
9399 and the store_ruid / use_ruid fields in reg_state. */
9400 static int reload_combine_ruid
;
9406 int first_index_reg
= 1, last_index_reg
= 0;
9408 int last_label_ruid
;
9410 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9411 reload has already used it where appropriate, so there is no use in
9412 trying to generate it now. */
9413 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
9416 /* To avoid wasting too much time later searching for an index register,
9417 determine the minimum and maximum index register numbers. */
9418 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9420 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
))
9422 if (! last_index_reg
)
9424 first_index_reg
= i
;
9427 /* If no index register is available, we can quit now. */
9428 if (first_index_reg
> last_index_reg
)
9431 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9432 last_label_ruid
= reload_combine_ruid
= 0;
9433 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9436 reg_state
[i
].use_index
= -1;
9439 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9440 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9444 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
9448 /* We cannot do our optimization across labels. Invalidating all the use
9449 information we have would be costly, so we just note where the label
9450 is and then later disable any optimization that would cross it. */
9451 if (GET_CODE (insn
) == CODE_LABEL
)
9452 last_label_ruid
= reload_combine_ruid
;
9453 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
9455 reload_combine_ruid
++;
9457 /* Look for (set (REGX) (CONST_INT))
9458 (set (REGX) (PLUS (REGX) (REGY)))
9460 ... (MEM (REGX)) ...
9462 (set (REGZ) (CONST_INT))
9464 ... (MEM (PLUS (REGZ) (REGY)))... .
9466 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9467 and that we know all uses of REGX before it dies. */
9468 set
= single_set (insn
);
9470 && GET_CODE (SET_DEST (set
)) == REG
9471 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
9472 GET_MODE (SET_DEST (set
)))
9474 && GET_CODE (SET_SRC (set
)) == PLUS
9475 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
9476 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
9477 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
9479 rtx reg
= SET_DEST (set
);
9480 rtx plus
= SET_SRC (set
);
9481 rtx base
= XEXP (plus
, 1);
9482 rtx prev
= prev_nonnote_insn (insn
);
9483 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
9484 int regno
= REGNO (reg
);
9486 rtx reg_sum
= NULL_RTX
;
9488 /* Now, we need an index register.
9489 We'll set index_reg to this index register, const_reg to the
9490 register that is to be loaded with the constant
9491 (denoted as REGZ in the substitution illustration above),
9492 and reg_sum to the register-register that we want to use to
9493 substitute uses of REG (typically in MEMs) with.
9494 First check REG and BASE for being index registers;
9495 we can use them even if they are not dead. */
9496 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
9497 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
9505 /* Otherwise, look for a free index register. Since we have
9506 checked above that neiter REG nor BASE are index registers,
9507 if we find anything at all, it will be different from these
9509 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
9511 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
9512 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
9513 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
9514 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
9516 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
9517 const_reg
= index_reg
;
9518 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
9524 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
9525 && rtx_equal_p (SET_DEST (prev_set
), reg
)
9526 && reg_state
[regno
].use_index
>= 0
9531 /* Change destination register and - if necessary - the
9532 constant value in PREV, the constant loading instruction. */
9533 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
9534 if (reg_state
[regno
].offset
!= const0_rtx
)
9535 validate_change (prev
,
9536 &SET_SRC (prev_set
),
9537 GEN_INT (INTVAL (SET_SRC (prev_set
))
9538 + INTVAL (reg_state
[regno
].offset
)),
9540 /* Now for every use of REG that we have recorded, replace REG
9542 for (i
= reg_state
[regno
].use_index
;
9543 i
< RELOAD_COMBINE_MAX_USES
; i
++)
9544 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
9545 reg_state
[regno
].reg_use
[i
].usep
,
9548 if (apply_change_group ())
9552 /* Delete the reg-reg addition. */
9553 PUT_CODE (insn
, NOTE
);
9554 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9555 NOTE_SOURCE_FILE (insn
) = 0;
9557 if (reg_state
[regno
].offset
!= const0_rtx
)
9559 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9561 for (np
= ®_NOTES (prev
); *np
; )
9563 if (REG_NOTE_KIND (*np
) == REG_EQUAL
9564 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
9565 *np
= XEXP (*np
, 1);
9567 np
= &XEXP (*np
, 1);
9570 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
9571 reg_state
[REGNO (const_reg
)].store_ruid
= reload_combine_ruid
;
9576 note_stores (PATTERN (insn
), reload_combine_note_store
);
9577 if (GET_CODE (insn
) == CALL_INSN
)
9581 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9583 if (call_used_regs
[i
])
9585 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9586 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9589 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
9590 link
= XEXP (link
, 1))
9592 rtx use
= XEXP (link
, 0);
9593 int regno
= REGNO (XEXP (use
, 0));
9594 if (GET_CODE (use
) == CLOBBER
)
9596 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
9597 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
9600 reg_state
[regno
].use_index
= -1;
9603 if (GET_CODE (insn
) == JUMP_INSN
)
9605 /* Non-spill registers might be used at the call destination in
9606 some unknown fashion, so we have to mark the unknown use. */
9607 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9610 reg_state
[i
].use_index
= -1;
9613 reload_combine_note_use (&PATTERN (insn
), insn
);
9614 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9616 if (REG_NOTE_KIND (note
) == REG_INC
9617 && GET_CODE (XEXP (note
, 0)) == REG
)
9618 reg_state
[REGNO (XEXP (note
, 0))].use_index
= -1;
9623 /* Check if DST is a register or a subreg of a register; if it is,
9624 update reg_state[regno].store_ruid and reg_state[regno].use_index
9625 accordingly. Called via note_stores from reload_combine.
9626 The second argument, SET, is ignored. */
9628 reload_combine_note_store (dst
, set
)
9629 rtx dst
, set ATTRIBUTE_UNUSED
;
9633 unsigned size
= GET_MODE_SIZE (GET_MODE (dst
));
9635 if (GET_CODE (dst
) == SUBREG
)
9637 regno
= SUBREG_WORD (dst
);
9638 dst
= SUBREG_REG (dst
);
9640 if (GET_CODE (dst
) != REG
)
9642 regno
+= REGNO (dst
);
9643 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9644 careful with registers / register parts that are not full words. */
9645 if (size
< (unsigned) UNITS_PER_WORD
)
9646 reg_state
[regno
].use_index
= -1;
9649 for (i
= size
/ UNITS_PER_WORD
- 1 + regno
; i
>= regno
; i
--)
9651 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9652 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9657 /* XP points to a piece of rtl that has to be checked for any uses of
9659 *XP is the pattern of INSN, or a part of it.
9660 Called from reload_combine, and recursively by itself. */
9662 reload_combine_note_use (xp
, insn
)
9666 enum rtx_code code
= x
->code
;
9669 rtx offset
= const0_rtx
; /* For the REG case below. */
9674 if (GET_CODE (SET_DEST (x
)) == REG
)
9676 reload_combine_note_use (&SET_SRC (x
), insn
);
9682 if (GET_CODE (SET_DEST (x
)) == REG
)
9687 /* We are interested in (plus (reg) (const_int)) . */
9688 if (GET_CODE (XEXP (x
, 0)) != REG
|| GET_CODE (XEXP (x
, 1)) != CONST_INT
)
9690 offset
= XEXP (x
, 1);
9695 int regno
= REGNO (x
);
9698 /* Some spurious USEs of pseudo registers might remain.
9699 Just ignore them. */
9700 if (regno
>= FIRST_PSEUDO_REGISTER
)
9703 /* If this register is already used in some unknown fashion, we
9705 If we decrement the index from zero to -1, we can't store more
9706 uses, so this register becomes used in an unknown fashion. */
9707 use_index
= --reg_state
[regno
].use_index
;
9711 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
9713 /* We have found another use for a register that is already
9714 used later. Check if the offsets match; if not, mark the
9715 register as used in an unknown fashion. */
9716 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
9718 reg_state
[regno
].use_index
= -1;
9724 /* This is the first use of this register we have seen since we
9725 marked it as dead. */
9726 reg_state
[regno
].offset
= offset
;
9727 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
9729 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
9730 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
9738 /* Recursively process the components of X. */
9739 fmt
= GET_RTX_FORMAT (code
);
9740 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9743 reload_combine_note_use (&XEXP (x
, i
), insn
);
9744 else if (fmt
[i
] == 'E')
9746 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9747 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
9752 /* See if we can reduce the cost of a constant by replacing a move with
9754 /* We cannot do our optimization across labels. Invalidating all the
9755 information about register contents we have would be costly, so we
9756 use last_label_luid (local variable of reload_cse_move2add) to note
9757 where the label is and then later disable any optimization that would
9759 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9760 reg_set_luid[n] is larger than last_label_luid[n] . */
9761 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
9762 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9763 reg_mode[n] to be valid.
9764 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9765 has been set to reg_offset[n] in mode reg_mode[n] .
9766 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9767 register n has been set to the sum of reg_offset[n] and register
9768 reg_base_reg[n], calculated in mode reg_mode[n] . */
9769 static rtx reg_offset
[FIRST_PSEUDO_REGISTER
];
9770 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
9771 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
9772 /* move2add_luid is linearily increased while scanning the instructions
9773 from first to last. It is used to set reg_set_luid in
9774 reload_cse_move2add and move2add_note_store. */
9775 static int move2add_luid
;
9778 reload_cse_move2add (first
)
9783 int last_label_luid
;
9785 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
9786 reg_set_luid
[i
] = 0;
9788 last_label_luid
= 0;
9790 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
9794 if (GET_CODE (insn
) == CODE_LABEL
)
9795 last_label_luid
= move2add_luid
;
9796 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
9798 pat
= PATTERN (insn
);
9799 /* For simplicity, we only perform this optimization on
9800 straightforward SETs. */
9801 if (GET_CODE (pat
) == SET
9802 && GET_CODE (SET_DEST (pat
)) == REG
)
9804 rtx reg
= SET_DEST (pat
);
9805 int regno
= REGNO (reg
);
9806 rtx src
= SET_SRC (pat
);
9808 /* Check if we have valid information on the contents of this
9809 register in the mode of REG. */
9810 /* ??? We don't know how zero / sign extension is handled, hence
9811 we can't go from a narrower to a wider mode. */
9812 if (reg_set_luid
[regno
] > last_label_luid
9813 && (GET_MODE_SIZE (GET_MODE (reg
))
9814 <= GET_MODE_SIZE (reg_mode
[regno
]))
9815 && GET_CODE (reg_offset
[regno
]) == CONST_INT
)
9817 /* Try to transform (set (REGX) (CONST_INT A))
9819 (set (REGX) (CONST_INT B))
9821 (set (REGX) (CONST_INT A))
9823 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9825 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
9828 rtx new_src
= GEN_INT (INTVAL (src
)
9829 - INTVAL (reg_offset
[regno
]));
9830 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9831 use (set (reg) (reg)) instead.
9832 We don't delete this insn, nor do we convert it into a
9833 note, to avoid losing register notes or the return
9834 value flag. jump2 already knowns how to get rid of
9836 if (new_src
== const0_rtx
)
9837 success
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
9838 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
9839 && have_add2_insn (GET_MODE (reg
)))
9840 success
= validate_change (insn
, &PATTERN (insn
),
9841 gen_add2_insn (reg
, new_src
), 0);
9842 reg_set_luid
[regno
] = move2add_luid
;
9843 reg_mode
[regno
] = GET_MODE (reg
);
9844 reg_offset
[regno
] = src
;
9848 /* Try to transform (set (REGX) (REGY))
9849 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9852 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9855 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9857 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9858 else if (GET_CODE (src
) == REG
9859 && reg_base_reg
[regno
] == REGNO (src
)
9860 && reg_set_luid
[regno
] > reg_set_luid
[REGNO (src
)])
9862 rtx next
= next_nonnote_insn (insn
);
9865 set
= single_set (next
);
9868 && SET_DEST (set
) == reg
9869 && GET_CODE (SET_SRC (set
)) == PLUS
9870 && XEXP (SET_SRC (set
), 0) == reg
9871 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
9873 rtx src3
= XEXP (SET_SRC (set
), 1);
9874 rtx new_src
= GEN_INT (INTVAL (src3
)
9875 - INTVAL (reg_offset
[regno
]));
9878 if (new_src
== const0_rtx
)
9879 /* See above why we create (set (reg) (reg)) here. */
9881 = validate_change (next
, &SET_SRC (set
), reg
, 0);
9882 else if ((rtx_cost (new_src
, PLUS
)
9883 < 2 + rtx_cost (src3
, SET
))
9884 && have_add2_insn (GET_MODE (reg
)))
9886 = validate_change (next
, &PATTERN (next
),
9887 gen_add2_insn (reg
, new_src
), 0);
9890 /* INSN might be the first insn in a basic block
9891 if the preceding insn is a conditional jump
9892 or a possible-throwing call. */
9893 PUT_CODE (insn
, NOTE
);
9894 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9895 NOTE_SOURCE_FILE (insn
) = 0;
9898 reg_set_luid
[regno
] = move2add_luid
;
9899 reg_mode
[regno
] = GET_MODE (reg
);
9900 reg_offset
[regno
] = src3
;
9907 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9909 if (REG_NOTE_KIND (note
) == REG_INC
9910 && GET_CODE (XEXP (note
, 0)) == REG
)
9912 /* Indicate that this register has been recently written to,
9913 but the exact contents are not available. */
9914 int regno
= REGNO (XEXP (note
, 0));
9915 if (regno
< FIRST_PSEUDO_REGISTER
)
9917 reg_set_luid
[regno
] = move2add_luid
;
9918 reg_offset
[regno
] = note
;
9922 note_stores (PATTERN (insn
), move2add_note_store
);
9923 /* If this is a CALL_INSN, all call used registers are stored with
9925 if (GET_CODE (insn
) == CALL_INSN
)
9927 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
9929 if (call_used_regs
[i
])
9931 reg_set_luid
[i
] = move2add_luid
;
9932 reg_offset
[i
] = insn
; /* Invalidate contents. */
9939 /* SET is a SET or CLOBBER that sets DST.
9940 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9941 Called from reload_cse_move2add via note_stores. */
9943 move2add_note_store (dst
, set
)
9949 enum machine_mode mode
= GET_MODE (dst
);
9950 if (GET_CODE (dst
) == SUBREG
)
9952 regno
= SUBREG_WORD (dst
);
9953 dst
= SUBREG_REG (dst
);
9955 if (GET_CODE (dst
) != REG
)
9958 regno
+= REGNO (dst
);
9960 if (HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
)
9962 rtx src
= SET_SRC (set
);
9964 reg_mode
[regno
] = mode
;
9965 switch (GET_CODE (src
))
9969 rtx src0
= XEXP (src
, 0);
9970 if (GET_CODE (src0
) == REG
)
9972 if (REGNO (src0
) != regno
9973 || reg_offset
[regno
] != const0_rtx
)
9975 reg_base_reg
[regno
] = REGNO (src0
);
9976 reg_set_luid
[regno
] = move2add_luid
;
9978 reg_offset
[regno
] = XEXP (src
, 1);
9981 reg_set_luid
[regno
] = move2add_luid
;
9982 reg_offset
[regno
] = set
; /* Invalidate contents. */
9987 reg_base_reg
[regno
] = REGNO (SET_SRC (set
));
9988 reg_offset
[regno
] = const0_rtx
;
9989 reg_set_luid
[regno
] = move2add_luid
;
9993 reg_base_reg
[regno
] = -1;
9994 reg_offset
[regno
] = SET_SRC (set
);
9995 reg_set_luid
[regno
] = move2add_luid
;
10001 for (i
= regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1; i
>= regno
; i
--)
10003 /* Indicate that this register has been recently written to,
10004 but the exact contents are not available. */
10005 reg_set_luid
[i
] = move2add_luid
;
10006 reg_offset
[i
] = dst
;