1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(m, x, y) 2
87 #define LOCAL_REGNO(REGNO) 0
90 /* During reload_as_needed, element N contains a REG rtx for the hard reg
91 into which reg N has been reloaded (perhaps for a previous insn). */
92 static rtx
*reg_last_reload_reg
;
94 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
95 for an output reload that stores into reg N. */
96 static char *reg_has_output_reload
;
98 /* Indicates which hard regs are reload-registers for an output reload
99 in the current insn. */
100 static HARD_REG_SET reg_is_output_reload
;
102 /* Element N is the constant value to which pseudo reg N is equivalent,
103 or zero if pseudo reg N is not equivalent to a constant.
104 find_reloads looks at this in order to replace pseudo reg N
105 with the constant it stands for. */
106 rtx
*reg_equiv_constant
;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx
*reg_equiv_memory_loc
;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx
*reg_equiv_address
;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width
;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
128 static rtx
*reg_equiv_init
;
130 /* Vector to remember old contents of reg_renumber before spilling. */
131 static short *reg_old_renumber
;
133 /* During reload_as_needed, element N contains the last pseudo regno reloaded
134 into hard register N. If that pseudo reg occupied more than one register,
135 reg_reloaded_contents points to that pseudo for each spill register in
136 use; all of these must remain set for an inheritance to occur. */
137 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
139 /* During reload_as_needed, element N contains the insn for which
140 hard register N was last used. Its contents are significant only
141 when reg_reloaded_valid is set for this register. */
142 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
144 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
145 static HARD_REG_SET reg_reloaded_valid
;
146 /* Indicate if the register was dead at the end of the reload.
147 This is only valid if reg_reloaded_contents is set and valid. */
148 static HARD_REG_SET reg_reloaded_dead
;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs
;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global
;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET
*pseudo_previous_regs
;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET
*pseudo_forbidden_regs
;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs
;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg
;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels
;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok
;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok
;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos
;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted
;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid
;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed
;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress
= 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
266 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack
;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj
;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj
;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj
;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain
*reload_insn_chain
;
290 extern tree current_function_decl
;
292 extern union tree_node
*current_function_decl
;
295 /* List of all insns needing reloads. */
296 static struct insn_chain
*insns_need_reload
;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from
; /* Register number to be eliminated. */
306 int to
; /* Register number used as replacement. */
307 int initial_offset
; /* Initial difference between values. */
308 int can_eliminate
; /* Nonzero if this elimination can be done. */
309 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset
; /* Current offset between the two regs. */
312 int previous_offset
; /* Offset at end of previous insn. */
313 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx
; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx
; /* REG rtx for the replacement. */
322 static struct elim_table
*reg_eliminate
= 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static const struct elim_table_1
330 } reg_eliminate_1
[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If nonzero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset
;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable
;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants
;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at
;
363 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
365 /* Number of labels in the current function. */
367 static int num_labels
;
369 static void replace_pseudos_in_call_usage
PARAMS ((rtx
*,
372 static void maybe_fix_stack_asms
PARAMS ((void));
373 static void copy_reloads
PARAMS ((struct insn_chain
*));
374 static void calculate_needs_all_insns
PARAMS ((int));
375 static int find_reg
PARAMS ((struct insn_chain
*, int));
376 static void find_reload_regs
PARAMS ((struct insn_chain
*));
377 static void select_reload_regs
PARAMS ((void));
378 static void delete_caller_save_insns
PARAMS ((void));
380 static void spill_failure
PARAMS ((rtx
, enum reg_class
));
381 static void count_spilled_pseudo
PARAMS ((int, int, int));
382 static void delete_dead_insn
PARAMS ((rtx
));
383 static void alter_reg
PARAMS ((int, int));
384 static void set_label_offsets
PARAMS ((rtx
, rtx
, int));
385 static void check_eliminable_occurrences
PARAMS ((rtx
));
386 static void elimination_effects
PARAMS ((rtx
, enum machine_mode
));
387 static int eliminate_regs_in_insn
PARAMS ((rtx
, int));
388 static void update_eliminable_offsets
PARAMS ((void));
389 static void mark_not_eliminable
PARAMS ((rtx
, rtx
, void *));
390 static void set_initial_elim_offsets
PARAMS ((void));
391 static void verify_initial_elim_offsets
PARAMS ((void));
392 static void set_initial_label_offsets
PARAMS ((void));
393 static void set_offsets_for_label
PARAMS ((rtx
));
394 static void init_elim_table
PARAMS ((void));
395 static void update_eliminables
PARAMS ((HARD_REG_SET
*));
396 static void spill_hard_reg
PARAMS ((unsigned int, int));
397 static int finish_spills
PARAMS ((int));
398 static void ior_hard_reg_set
PARAMS ((HARD_REG_SET
*, HARD_REG_SET
*));
399 static void scan_paradoxical_subregs
PARAMS ((rtx
));
400 static void count_pseudo
PARAMS ((int));
401 static void order_regs_for_reload
PARAMS ((struct insn_chain
*));
402 static void reload_as_needed
PARAMS ((int));
403 static void forget_old_reloads_1
PARAMS ((rtx
, rtx
, void *));
404 static int reload_reg_class_lower
PARAMS ((const PTR
, const PTR
));
405 static void mark_reload_reg_in_use
PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use
PARAMS ((unsigned int, int,
411 static int reload_reg_free_p
PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p
PARAMS ((int, int, int,
415 rtx
, rtx
, int, int));
416 static int free_for_value_p
PARAMS ((int, enum machine_mode
, int,
417 enum reload_type
, rtx
, rtx
,
419 static int reload_reg_reaches_end_p
PARAMS ((unsigned int, int,
421 static int allocate_reload_reg
PARAMS ((struct insn_chain
*, int,
423 static int conflicts_with_override
PARAMS ((rtx
));
424 static void failed_reload
PARAMS ((rtx
, int));
425 static int set_reload_reg
PARAMS ((int, int));
426 static void choose_reload_regs_init
PARAMS ((struct insn_chain
*, rtx
*));
427 static void choose_reload_regs
PARAMS ((struct insn_chain
*));
428 static void merge_assigned_reloads
PARAMS ((rtx
));
429 static void emit_input_reload_insns
PARAMS ((struct insn_chain
*,
430 struct reload
*, rtx
, int));
431 static void emit_output_reload_insns
PARAMS ((struct insn_chain
*,
432 struct reload
*, int));
433 static void do_input_reload
PARAMS ((struct insn_chain
*,
434 struct reload
*, int));
435 static void do_output_reload
PARAMS ((struct insn_chain
*,
436 struct reload
*, int));
437 static void emit_reload_insns
PARAMS ((struct insn_chain
*));
438 static void delete_output_reload
PARAMS ((rtx
, int, int));
439 static void delete_address_reloads
PARAMS ((rtx
, rtx
));
440 static void delete_address_reloads_1
PARAMS ((rtx
, rtx
, rtx
));
441 static rtx inc_for_reload
PARAMS ((rtx
, rtx
, rtx
, int));
442 static void reload_cse_regs_1
PARAMS ((rtx
));
443 static int reload_cse_noop_set_p
PARAMS ((rtx
));
444 static int reload_cse_simplify_set
PARAMS ((rtx
, rtx
));
445 static int reload_cse_simplify_operands
PARAMS ((rtx
, rtx
));
446 static void reload_combine
PARAMS ((void));
447 static void reload_combine_note_use
PARAMS ((rtx
*, rtx
));
448 static void reload_combine_note_store
PARAMS ((rtx
, rtx
, void *));
449 static void reload_cse_move2add
PARAMS ((rtx
));
450 static void move2add_note_store
PARAMS ((rtx
, rtx
, void *));
452 static void add_auto_inc_notes
PARAMS ((rtx
, rtx
));
454 static void copy_eh_notes
PARAMS ((rtx
, rtx
));
455 static HOST_WIDE_INT sext_for_mode
PARAMS ((enum machine_mode
,
457 static void failed_reload
PARAMS ((rtx
, int));
458 static int set_reload_reg
PARAMS ((int, int));
459 static void reload_cse_simplify
PARAMS ((rtx
, rtx
));
460 void fixup_abnormal_edges
PARAMS ((void));
461 extern void dump_needs
PARAMS ((struct insn_chain
*));
463 /* Initialize the reload pass once per compilation. */
470 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
471 Set spill_indirect_levels to the number of levels such addressing is
472 permitted, zero if it is not permitted at all. */
475 = gen_rtx_MEM (Pmode
,
478 LAST_VIRTUAL_REGISTER
+ 1),
480 spill_indirect_levels
= 0;
482 while (memory_address_p (QImode
, tem
))
484 spill_indirect_levels
++;
485 tem
= gen_rtx_MEM (Pmode
, tem
);
488 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
490 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
491 indirect_symref_ok
= memory_address_p (QImode
, tem
);
493 /* See if reg+reg is a valid (and offsettable) address. */
495 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
497 tem
= gen_rtx_PLUS (Pmode
,
498 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
499 gen_rtx_REG (Pmode
, i
));
501 /* This way, we make sure that reg+reg is an offsettable address. */
502 tem
= plus_constant (tem
, 4);
504 if (memory_address_p (QImode
, tem
))
506 double_reg_address_ok
= 1;
511 /* Initialize obstack for our rtl allocation. */
512 gcc_obstack_init (&reload_obstack
);
513 reload_startobj
= (char *) obstack_alloc (&reload_obstack
, 0);
515 INIT_REG_SET (&spilled_pseudos
);
516 INIT_REG_SET (&pseudos_counted
);
519 /* List of insn chains that are currently unused. */
520 static struct insn_chain
*unused_insn_chains
= 0;
522 /* Allocate an empty insn_chain structure. */
526 struct insn_chain
*c
;
528 if (unused_insn_chains
== 0)
530 c
= (struct insn_chain
*)
531 obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
532 INIT_REG_SET (&c
->live_throughout
);
533 INIT_REG_SET (&c
->dead_or_set
);
537 c
= unused_insn_chains
;
538 unused_insn_chains
= c
->next
;
540 c
->is_caller_save_insn
= 0;
541 c
->need_operand_change
= 0;
547 /* Small utility function to set all regs in hard reg set TO which are
548 allocated to pseudos in regset FROM. */
551 compute_use_by_pseudos (to
, from
)
557 EXECUTE_IF_SET_IN_REG_SET
558 (from
, FIRST_PSEUDO_REGISTER
, regno
,
560 int r
= reg_renumber
[regno
];
565 /* reload_combine uses the information from
566 BASIC_BLOCK->global_live_at_start, which might still
567 contain registers that have not actually been allocated
568 since they have an equivalence. */
569 if (! reload_completed
)
574 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
576 SET_HARD_REG_BIT (*to
, r
+ nregs
);
581 /* Replace all pseudos found in LOC with their corresponding
585 replace_pseudos_in_call_usage (loc
, mem_mode
, usage
)
587 enum machine_mode mem_mode
;
601 unsigned int regno
= REGNO (x
);
603 if (regno
< FIRST_PSEUDO_REGISTER
)
606 x
= eliminate_regs (x
, mem_mode
, usage
);
610 replace_pseudos_in_call_usage (loc
, mem_mode
, usage
);
614 if (reg_equiv_constant
[regno
])
615 *loc
= reg_equiv_constant
[regno
];
616 else if (reg_equiv_mem
[regno
])
617 *loc
= reg_equiv_mem
[regno
];
618 else if (reg_equiv_address
[regno
])
619 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
620 else if (GET_CODE (regno_reg_rtx
[regno
]) != REG
621 || REGNO (regno_reg_rtx
[regno
]) != regno
)
622 *loc
= regno_reg_rtx
[regno
];
628 else if (code
== MEM
)
630 replace_pseudos_in_call_usage (& XEXP (x
, 0), GET_MODE (x
), usage
);
634 /* Process each of our operands recursively. */
635 fmt
= GET_RTX_FORMAT (code
);
636 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
638 replace_pseudos_in_call_usage (&XEXP (x
, i
), mem_mode
, usage
);
639 else if (*fmt
== 'E')
640 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
641 replace_pseudos_in_call_usage (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
645 /* Global variables used by reload and its subroutines. */
647 /* Set during calculate_needs if an insn needs register elimination. */
648 static int something_needs_elimination
;
649 /* Set during calculate_needs if an insn needs an operand changed. */
650 int something_needs_operands_changed
;
652 /* Nonzero means we couldn't get enough spill regs. */
655 /* Main entry point for the reload pass.
657 FIRST is the first insn of the function being compiled.
659 GLOBAL nonzero means we were called from global_alloc
660 and should attempt to reallocate any pseudoregs that we
661 displace from hard regs we will use for reloads.
662 If GLOBAL is zero, we do not have enough information to do that,
663 so any pseudo reg that is spilled must go to the stack.
665 Return value is nonzero if reload failed
666 and we must not do any more for this function. */
669 reload (first
, global
)
675 struct elim_table
*ep
;
678 /* The two pointers used to track the true location of the memory used
679 for label offsets. */
680 char *real_known_ptr
= NULL
;
681 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
683 /* Make sure even insns with volatile mem refs are recognizable. */
688 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
690 /* Make sure that the last insn in the chain
691 is not something that needs reloading. */
692 emit_note (NULL
, NOTE_INSN_DELETED
);
694 /* Enable find_equiv_reg to distinguish insns made by reload. */
695 reload_first_uid
= get_max_uid ();
697 #ifdef SECONDARY_MEMORY_NEEDED
698 /* Initialize the secondary memory table. */
699 clear_secondary_mem ();
702 /* We don't have a stack slot for any spill reg yet. */
703 memset ((char *) spill_stack_slot
, 0, sizeof spill_stack_slot
);
704 memset ((char *) spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
706 /* Initialize the save area information for caller-save, in case some
710 /* Compute which hard registers are now in use
711 as homes for pseudo registers.
712 This is done here rather than (eg) in global_alloc
713 because this point is reached even if not optimizing. */
714 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
717 /* A function that receives a nonlocal goto must save all call-saved
719 if (current_function_has_nonlocal_label
)
720 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
721 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
722 regs_ever_live
[i
] = 1;
724 /* Find all the pseudo registers that didn't get hard regs
725 but do have known equivalent constants or memory slots.
726 These include parameters (known equivalent to parameter slots)
727 and cse'd or loop-moved constant memory addresses.
729 Record constant equivalents in reg_equiv_constant
730 so they will be substituted by find_reloads.
731 Record memory equivalents in reg_mem_equiv so they can
732 be substituted eventually by altering the REG-rtx's. */
734 reg_equiv_constant
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
735 reg_equiv_mem
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
736 reg_equiv_init
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
737 reg_equiv_address
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
738 reg_max_ref_width
= (unsigned int *) xcalloc (max_regno
, sizeof (int));
739 reg_old_renumber
= (short *) xcalloc (max_regno
, sizeof (short));
740 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
741 pseudo_forbidden_regs
742 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
744 = (HARD_REG_SET
*) xcalloc (max_regno
, sizeof (HARD_REG_SET
));
746 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
748 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
749 Also find all paradoxical subregs and find largest such for each pseudo.
750 On machines with small register classes, record hard registers that
751 are used for user variables. These can never be used for spills.
752 Also look for a "constant" REG_SETJMP. This means that all
753 caller-saved registers must be marked live. */
755 num_eliminable_invariants
= 0;
756 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
758 rtx set
= single_set (insn
);
760 /* We may introduce USEs that we want to remove at the end, so
761 we'll mark them with QImode. Make sure there are no
762 previously-marked insns left by say regmove. */
763 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
764 && GET_MODE (insn
) != VOIDmode
)
765 PUT_MODE (insn
, VOIDmode
);
767 if (GET_CODE (insn
) == CALL_INSN
768 && find_reg_note (insn
, REG_SETJMP
, NULL
))
769 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
770 if (! call_used_regs
[i
])
771 regs_ever_live
[i
] = 1;
773 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
775 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
777 #ifdef LEGITIMATE_PIC_OPERAND_P
778 && (! function_invariant_p (XEXP (note
, 0))
780 /* A function invariant is often CONSTANT_P but may
781 include a register. We promise to only pass
782 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
783 || (CONSTANT_P (XEXP (note
, 0))
784 && LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0))))
788 rtx x
= XEXP (note
, 0);
789 i
= REGNO (SET_DEST (set
));
790 if (i
> LAST_VIRTUAL_REGISTER
)
792 /* It can happen that a REG_EQUIV note contains a MEM
793 that is not a legitimate memory operand. As later
794 stages of reload assume that all addresses found
795 in the reg_equiv_* arrays were originally legitimate,
796 we ignore such REG_EQUIV notes. */
797 if (memory_operand (x
, VOIDmode
))
799 /* Always unshare the equivalence, so we can
800 substitute into this insn without touching the
802 reg_equiv_memory_loc
[i
] = copy_rtx (x
);
804 else if (function_invariant_p (x
))
806 if (GET_CODE (x
) == PLUS
)
808 /* This is PLUS of frame pointer and a constant,
809 and might be shared. Unshare it. */
810 reg_equiv_constant
[i
] = copy_rtx (x
);
811 num_eliminable_invariants
++;
813 else if (x
== frame_pointer_rtx
814 || x
== arg_pointer_rtx
)
816 reg_equiv_constant
[i
] = x
;
817 num_eliminable_invariants
++;
819 else if (LEGITIMATE_CONSTANT_P (x
))
820 reg_equiv_constant
[i
] = x
;
823 reg_equiv_memory_loc
[i
]
824 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
825 if (!reg_equiv_memory_loc
[i
])
832 /* If this register is being made equivalent to a MEM
833 and the MEM is not SET_SRC, the equivalencing insn
834 is one with the MEM as a SET_DEST and it occurs later.
835 So don't mark this insn now. */
836 if (GET_CODE (x
) != MEM
837 || rtx_equal_p (SET_SRC (set
), x
))
839 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[i
]);
844 /* If this insn is setting a MEM from a register equivalent to it,
845 this is the equivalencing insn. */
846 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
847 && GET_CODE (SET_SRC (set
)) == REG
848 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
849 && rtx_equal_p (SET_DEST (set
),
850 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
851 reg_equiv_init
[REGNO (SET_SRC (set
))]
852 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
853 reg_equiv_init
[REGNO (SET_SRC (set
))]);
856 scan_paradoxical_subregs (PATTERN (insn
));
861 num_labels
= max_label_num () - get_first_label_num ();
863 /* Allocate the tables used to store offset information at labels. */
864 /* We used to use alloca here, but the size of what it would try to
865 allocate would occasionally cause it to exceed the stack limit and
866 cause a core dump. */
867 real_known_ptr
= xmalloc (num_labels
);
869 = (int (*)[NUM_ELIMINABLE_REGS
])
870 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
872 offsets_known_at
= real_known_ptr
- get_first_label_num ();
874 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
876 /* Alter each pseudo-reg rtx to contain its hard reg number.
877 Assign stack slots to the pseudos that lack hard regs or equivalents.
878 Do not touch virtual registers. */
880 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
883 /* If we have some registers we think can be eliminated, scan all insns to
884 see if there is an insn that sets one of these registers to something
885 other than itself plus a constant. If so, the register cannot be
886 eliminated. Doing this scan here eliminates an extra pass through the
887 main reload loop in the most common case where register elimination
889 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
890 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
891 || GET_CODE (insn
) == CALL_INSN
)
892 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
894 maybe_fix_stack_asms ();
896 insns_need_reload
= 0;
897 something_needs_elimination
= 0;
899 /* Initialize to -1, which means take the first spill register. */
902 /* Spill any hard regs that we know we can't eliminate. */
903 CLEAR_HARD_REG_SET (used_spill_regs
);
904 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
905 if (! ep
->can_eliminate
)
906 spill_hard_reg (ep
->from
, 1);
908 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
909 if (frame_pointer_needed
)
910 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
912 finish_spills (global
);
914 /* From now on, we may need to generate moves differently. We may also
915 allow modifications of insns which cause them to not be recognized.
916 Any such modifications will be cleaned up during reload itself. */
917 reload_in_progress
= 1;
919 /* This loop scans the entire function each go-round
920 and repeats until one repetition spills no additional hard regs. */
923 int something_changed
;
926 HOST_WIDE_INT starting_frame_size
;
928 /* Round size of stack frame to stack_alignment_needed. This must be done
929 here because the stack size may be a part of the offset computation
930 for register elimination, and there might have been new stack slots
931 created in the last iteration of this loop. */
932 if (cfun
->stack_alignment_needed
)
933 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
935 starting_frame_size
= get_frame_size ();
937 set_initial_elim_offsets ();
938 set_initial_label_offsets ();
940 /* For each pseudo register that has an equivalent location defined,
941 try to eliminate any eliminable registers (such as the frame pointer)
942 assuming initial offsets for the replacement register, which
945 If the resulting location is directly addressable, substitute
946 the MEM we just got directly for the old REG.
948 If it is not addressable but is a constant or the sum of a hard reg
949 and constant, it is probably not addressable because the constant is
950 out of range, in that case record the address; we will generate
951 hairy code to compute the address in a register each time it is
952 needed. Similarly if it is a hard register, but one that is not
953 valid as an address register.
955 If the location is not addressable, but does not have one of the
956 above forms, assign a stack slot. We have to do this to avoid the
957 potential of producing lots of reloads if, e.g., a location involves
958 a pseudo that didn't get a hard register and has an equivalent memory
959 location that also involves a pseudo that didn't get a hard register.
961 Perhaps at some point we will improve reload_when_needed handling
962 so this problem goes away. But that's very hairy. */
964 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
965 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
967 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
969 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
971 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
972 else if (CONSTANT_P (XEXP (x
, 0))
973 || (GET_CODE (XEXP (x
, 0)) == REG
974 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
975 || (GET_CODE (XEXP (x
, 0)) == PLUS
976 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
977 && (REGNO (XEXP (XEXP (x
, 0), 0))
978 < FIRST_PSEUDO_REGISTER
)
979 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
980 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
983 /* Make a new stack slot. Then indicate that something
984 changed so we go back and recompute offsets for
985 eliminable registers because the allocation of memory
986 below might change some offset. reg_equiv_{mem,address}
987 will be set up for this pseudo on the next pass around
989 reg_equiv_memory_loc
[i
] = 0;
990 reg_equiv_init
[i
] = 0;
995 if (caller_save_needed
)
998 /* If we allocated another stack slot, redo elimination bookkeeping. */
999 if (starting_frame_size
!= get_frame_size ())
1002 if (caller_save_needed
)
1004 save_call_clobbered_regs ();
1005 /* That might have allocated new insn_chain structures. */
1006 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1009 calculate_needs_all_insns (global
);
1011 CLEAR_REG_SET (&spilled_pseudos
);
1014 something_changed
= 0;
1016 /* If we allocated any new memory locations, make another pass
1017 since it might have changed elimination offsets. */
1018 if (starting_frame_size
!= get_frame_size ())
1019 something_changed
= 1;
1022 HARD_REG_SET to_spill
;
1023 CLEAR_HARD_REG_SET (to_spill
);
1024 update_eliminables (&to_spill
);
1025 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1026 if (TEST_HARD_REG_BIT (to_spill
, i
))
1028 spill_hard_reg (i
, 1);
1031 /* Regardless of the state of spills, if we previously had
1032 a register that we thought we could eliminate, but now can
1033 not eliminate, we must run another pass.
1035 Consider pseudos which have an entry in reg_equiv_* which
1036 reference an eliminable register. We must make another pass
1037 to update reg_equiv_* so that we do not substitute in the
1038 old value from when we thought the elimination could be
1040 something_changed
= 1;
1044 select_reload_regs ();
1048 if (insns_need_reload
!= 0 || did_spill
)
1049 something_changed
|= finish_spills (global
);
1051 if (! something_changed
)
1054 if (caller_save_needed
)
1055 delete_caller_save_insns ();
1057 obstack_free (&reload_obstack
, reload_firstobj
);
1060 /* If global-alloc was run, notify it of any register eliminations we have
1063 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1064 if (ep
->can_eliminate
)
1065 mark_elimination (ep
->from
, ep
->to
);
1067 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1068 If that insn didn't set the register (i.e., it copied the register to
1069 memory), just delete that insn instead of the equivalencing insn plus
1070 anything now dead. If we call delete_dead_insn on that insn, we may
1071 delete the insn that actually sets the register if the register dies
1072 there and that is incorrect. */
1074 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1076 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1079 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1081 rtx equiv_insn
= XEXP (list
, 0);
1083 /* If we already deleted the insn or if it may trap, we can't
1084 delete it. The latter case shouldn't happen, but can
1085 if an insn has a variable address, gets a REG_EH_REGION
1086 note added to it, and then gets converted into an load
1087 from a constant address. */
1088 if (GET_CODE (equiv_insn
) == NOTE
1089 || can_throw_internal (equiv_insn
))
1091 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1092 delete_dead_insn (equiv_insn
);
1095 PUT_CODE (equiv_insn
, NOTE
);
1096 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1097 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1103 /* Use the reload registers where necessary
1104 by generating move instructions to move the must-be-register
1105 values into or out of the reload registers. */
1107 if (insns_need_reload
!= 0 || something_needs_elimination
1108 || something_needs_operands_changed
)
1110 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1112 reload_as_needed (global
);
1114 if (old_frame_size
!= get_frame_size ())
1118 verify_initial_elim_offsets ();
1121 /* If we were able to eliminate the frame pointer, show that it is no
1122 longer live at the start of any basic block. If it ls live by
1123 virtue of being in a pseudo, that pseudo will be marked live
1124 and hence the frame pointer will be known to be live via that
1127 if (! frame_pointer_needed
)
1129 CLEAR_REGNO_REG_SET (bb
->global_live_at_start
,
1130 HARD_FRAME_POINTER_REGNUM
);
1132 /* Come here (with failure set nonzero) if we can't get enough spill regs
1133 and we decide not to abort about it. */
1136 CLEAR_REG_SET (&spilled_pseudos
);
1137 reload_in_progress
= 0;
1139 /* Now eliminate all pseudo regs by modifying them into
1140 their equivalent memory references.
1141 The REG-rtx's for the pseudos are modified in place,
1142 so all insns that used to refer to them now refer to memory.
1144 For a reg that has a reg_equiv_address, all those insns
1145 were changed by reloading so that no insns refer to it any longer;
1146 but the DECL_RTL of a variable decl may refer to it,
1147 and if so this causes the debugging info to mention the variable. */
1149 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1153 if (reg_equiv_mem
[i
])
1154 addr
= XEXP (reg_equiv_mem
[i
], 0);
1156 if (reg_equiv_address
[i
])
1157 addr
= reg_equiv_address
[i
];
1161 if (reg_renumber
[i
] < 0)
1163 rtx reg
= regno_reg_rtx
[i
];
1165 REG_USERVAR_P (reg
) = 0;
1166 PUT_CODE (reg
, MEM
);
1167 XEXP (reg
, 0) = addr
;
1168 if (reg_equiv_memory_loc
[i
])
1169 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc
[i
]);
1172 RTX_UNCHANGING_P (reg
) = MEM_IN_STRUCT_P (reg
)
1173 = MEM_SCALAR_P (reg
) = 0;
1174 MEM_ATTRS (reg
) = 0;
1177 else if (reg_equiv_mem
[i
])
1178 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1182 /* We must set reload_completed now since the cleanup_subreg_operands call
1183 below will re-recognize each insn and reload may have generated insns
1184 which are only valid during and after reload. */
1185 reload_completed
= 1;
1187 /* Make a pass over all the insns and delete all USEs which we inserted
1188 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1189 notes. Delete all CLOBBER insns, except those that refer to the return
1190 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1191 from misarranging variable-array code, and simplify (subreg (reg))
1192 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1193 are no longer useful or accurate. Strip and regenerate REG_INC notes
1194 that may have been moved around. */
1196 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1201 if (GET_CODE (insn
) == CALL_INSN
)
1202 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn
),
1204 CALL_INSN_FUNCTION_USAGE (insn
));
1206 if ((GET_CODE (PATTERN (insn
)) == USE
1207 /* We mark with QImode USEs introduced by reload itself. */
1208 && (GET_MODE (insn
) == QImode
1209 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1210 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1211 && (GET_CODE (XEXP (PATTERN (insn
), 0)) != MEM
1212 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1213 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1214 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1215 != stack_pointer_rtx
))
1216 && (GET_CODE (XEXP (PATTERN (insn
), 0)) != REG
1217 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1223 pnote
= ®_NOTES (insn
);
1226 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1227 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1228 || REG_NOTE_KIND (*pnote
) == REG_INC
1229 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1230 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1231 *pnote
= XEXP (*pnote
, 1);
1233 pnote
= &XEXP (*pnote
, 1);
1237 add_auto_inc_notes (insn
, PATTERN (insn
));
1240 /* And simplify (subreg (reg)) if it appears as an operand. */
1241 cleanup_subreg_operands (insn
);
1244 /* If we are doing stack checking, give a warning if this function's
1245 frame size is larger than we expect. */
1246 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1248 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1249 static int verbose_warned
= 0;
1251 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1252 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1253 size
+= UNITS_PER_WORD
;
1255 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1257 warning ("frame size too large for reliable stack checking");
1258 if (! verbose_warned
)
1260 warning ("try reducing the number of local variables");
1266 /* Indicate that we no longer have known memory locations or constants. */
1267 if (reg_equiv_constant
)
1268 free (reg_equiv_constant
);
1269 reg_equiv_constant
= 0;
1270 if (reg_equiv_memory_loc
)
1271 free (reg_equiv_memory_loc
);
1272 reg_equiv_memory_loc
= 0;
1275 free (real_known_ptr
);
1279 free (reg_equiv_mem
);
1280 free (reg_equiv_init
);
1281 free (reg_equiv_address
);
1282 free (reg_max_ref_width
);
1283 free (reg_old_renumber
);
1284 free (pseudo_previous_regs
);
1285 free (pseudo_forbidden_regs
);
1287 CLEAR_HARD_REG_SET (used_spill_regs
);
1288 for (i
= 0; i
< n_spills
; i
++)
1289 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1291 /* Free all the insn_chain structures at once. */
1292 obstack_free (&reload_obstack
, reload_startobj
);
1293 unused_insn_chains
= 0;
1294 fixup_abnormal_edges ();
1296 /* Replacing pseudos with their memory equivalents might have
1297 created shared rtx. Subsequent passes would get confused
1298 by this, so unshare everything here. */
1299 unshare_all_rtl_again (first
);
1304 /* Yet another special case. Unfortunately, reg-stack forces people to
1305 write incorrect clobbers in asm statements. These clobbers must not
1306 cause the register to appear in bad_spill_regs, otherwise we'll call
1307 fatal_insn later. We clear the corresponding regnos in the live
1308 register sets to avoid this.
1309 The whole thing is rather sick, I'm afraid. */
1312 maybe_fix_stack_asms ()
1315 const char *constraints
[MAX_RECOG_OPERANDS
];
1316 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1317 struct insn_chain
*chain
;
1319 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1322 HARD_REG_SET clobbered
, allowed
;
1325 if (! INSN_P (chain
->insn
)
1326 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1328 pat
= PATTERN (chain
->insn
);
1329 if (GET_CODE (pat
) != PARALLEL
)
1332 CLEAR_HARD_REG_SET (clobbered
);
1333 CLEAR_HARD_REG_SET (allowed
);
1335 /* First, make a mask of all stack regs that are clobbered. */
1336 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1338 rtx t
= XVECEXP (pat
, 0, i
);
1339 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1340 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1343 /* Get the operand values and constraints out of the insn. */
1344 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1345 constraints
, operand_mode
);
1347 /* For every operand, see what registers are allowed. */
1348 for (i
= 0; i
< noperands
; i
++)
1350 const char *p
= constraints
[i
];
1351 /* For every alternative, we compute the class of registers allowed
1352 for reloading in CLS, and merge its contents into the reg set
1354 int cls
= (int) NO_REGS
;
1360 if (c
== '\0' || c
== ',' || c
== '#')
1362 /* End of one alternative - mark the regs in the current
1363 class, and reset the class. */
1364 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1370 } while (c
!= '\0' && c
!= ',');
1378 case '=': case '+': case '*': case '%': case '?': case '!':
1379 case '0': case '1': case '2': case '3': case '4': case 'm':
1380 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1381 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1382 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1387 cls
= (int) reg_class_subunion
[cls
]
1388 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1393 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1397 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1398 cls
= (int) reg_class_subunion
[cls
]
1399 [(int) MODE_BASE_REG_CLASS (VOIDmode
)];
1401 cls
= (int) reg_class_subunion
[cls
]
1402 [(int) REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1404 p
+= CONSTRAINT_LEN (c
, p
);
1407 /* Those of the registers which are clobbered, but allowed by the
1408 constraints, must be usable as reload registers. So clear them
1409 out of the life information. */
1410 AND_HARD_REG_SET (allowed
, clobbered
);
1411 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1412 if (TEST_HARD_REG_BIT (allowed
, i
))
1414 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1415 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1422 /* Copy the global variables n_reloads and rld into the corresponding elts
1425 copy_reloads (chain
)
1426 struct insn_chain
*chain
;
1428 chain
->n_reloads
= n_reloads
;
1430 = (struct reload
*) obstack_alloc (&reload_obstack
,
1431 n_reloads
* sizeof (struct reload
));
1432 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1433 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1436 /* Walk the chain of insns, and determine for each whether it needs reloads
1437 and/or eliminations. Build the corresponding insns_need_reload list, and
1438 set something_needs_elimination as appropriate. */
1440 calculate_needs_all_insns (global
)
1443 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1444 struct insn_chain
*chain
, *next
= 0;
1446 something_needs_elimination
= 0;
1448 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1449 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1451 rtx insn
= chain
->insn
;
1455 /* Clear out the shortcuts. */
1456 chain
->n_reloads
= 0;
1457 chain
->need_elim
= 0;
1458 chain
->need_reload
= 0;
1459 chain
->need_operand_change
= 0;
1461 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1462 include REG_LABEL), we need to see what effects this has on the
1463 known offsets at labels. */
1465 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1466 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1467 set_label_offsets (insn
, insn
, 0);
1471 rtx old_body
= PATTERN (insn
);
1472 int old_code
= INSN_CODE (insn
);
1473 rtx old_notes
= REG_NOTES (insn
);
1474 int did_elimination
= 0;
1475 int operands_changed
= 0;
1476 rtx set
= single_set (insn
);
1478 /* Skip insns that only set an equivalence. */
1479 if (set
&& GET_CODE (SET_DEST (set
)) == REG
1480 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1481 && reg_equiv_constant
[REGNO (SET_DEST (set
))])
1484 /* If needed, eliminate any eliminable registers. */
1485 if (num_eliminable
|| num_eliminable_invariants
)
1486 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1488 /* Analyze the instruction. */
1489 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1490 global
, spill_reg_order
);
1492 /* If a no-op set needs more than one reload, this is likely
1493 to be something that needs input address reloads. We
1494 can't get rid of this cleanly later, and it is of no use
1495 anyway, so discard it now.
1496 We only do this when expensive_optimizations is enabled,
1497 since this complements reload inheritance / output
1498 reload deletion, and it can make debugging harder. */
1499 if (flag_expensive_optimizations
&& n_reloads
> 1)
1501 rtx set
= single_set (insn
);
1503 && SET_SRC (set
) == SET_DEST (set
)
1504 && GET_CODE (SET_SRC (set
)) == REG
1505 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1508 /* Delete it from the reload chain. */
1510 chain
->prev
->next
= next
;
1512 reload_insn_chain
= next
;
1514 next
->prev
= chain
->prev
;
1515 chain
->next
= unused_insn_chains
;
1516 unused_insn_chains
= chain
;
1521 update_eliminable_offsets ();
1523 /* Remember for later shortcuts which insns had any reloads or
1524 register eliminations. */
1525 chain
->need_elim
= did_elimination
;
1526 chain
->need_reload
= n_reloads
> 0;
1527 chain
->need_operand_change
= operands_changed
;
1529 /* Discard any register replacements done. */
1530 if (did_elimination
)
1532 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1533 PATTERN (insn
) = old_body
;
1534 INSN_CODE (insn
) = old_code
;
1535 REG_NOTES (insn
) = old_notes
;
1536 something_needs_elimination
= 1;
1539 something_needs_operands_changed
|= operands_changed
;
1543 copy_reloads (chain
);
1544 *pprev_reload
= chain
;
1545 pprev_reload
= &chain
->next_need_reload
;
1552 /* Comparison function for qsort to decide which of two reloads
1553 should be handled first. *P1 and *P2 are the reload numbers. */
1556 reload_reg_class_lower (r1p
, r2p
)
1560 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1563 /* Consider required reloads before optional ones. */
1564 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1568 /* Count all solitary classes before non-solitary ones. */
1569 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1570 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1574 /* Aside from solitaires, consider all multi-reg groups first. */
1575 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1579 /* Consider reloads in order of increasing reg-class number. */
1580 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1584 /* If reloads are equally urgent, sort by reload number,
1585 so that the results of qsort leave nothing to chance. */
1589 /* The cost of spilling each hard reg. */
1590 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1592 /* When spilling multiple hard registers, we use SPILL_COST for the first
1593 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1594 only the first hard reg for a multi-reg pseudo. */
1595 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1597 /* Update the spill cost arrays, considering that pseudo REG is live. */
1603 int freq
= REG_FREQ (reg
);
1604 int r
= reg_renumber
[reg
];
1607 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1608 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1611 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1616 spill_add_cost
[r
] += freq
;
1618 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1620 spill_cost
[r
+ nregs
] += freq
;
1623 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1624 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1627 order_regs_for_reload (chain
)
1628 struct insn_chain
*chain
;
1631 HARD_REG_SET used_by_pseudos
;
1632 HARD_REG_SET used_by_pseudos2
;
1634 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1636 memset (spill_cost
, 0, sizeof spill_cost
);
1637 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1639 /* Count number of uses of each hard reg by pseudo regs allocated to it
1640 and then order them by decreasing use. First exclude hard registers
1641 that are live in or across this insn. */
1643 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1644 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1645 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1646 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1648 /* Now find out which pseudos are allocated to it, and update
1650 CLEAR_REG_SET (&pseudos_counted
);
1652 EXECUTE_IF_SET_IN_REG_SET
1653 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
1657 EXECUTE_IF_SET_IN_REG_SET
1658 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
1662 CLEAR_REG_SET (&pseudos_counted
);
1665 /* Vector of reload-numbers showing the order in which the reloads should
1667 static short reload_order
[MAX_RELOADS
];
1669 /* This is used to keep track of the spill regs used in one insn. */
1670 static HARD_REG_SET used_spill_regs_local
;
1672 /* We decided to spill hard register SPILLED, which has a size of
1673 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1674 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1675 update SPILL_COST/SPILL_ADD_COST. */
1678 count_spilled_pseudo (spilled
, spilled_nregs
, reg
)
1679 int spilled
, spilled_nregs
, reg
;
1681 int r
= reg_renumber
[reg
];
1682 int nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1684 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1685 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1688 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1690 spill_add_cost
[r
] -= REG_FREQ (reg
);
1692 spill_cost
[r
+ nregs
] -= REG_FREQ (reg
);
1695 /* Find reload register to use for reload number ORDER. */
1698 find_reg (chain
, order
)
1699 struct insn_chain
*chain
;
1702 int rnum
= reload_order
[order
];
1703 struct reload
*rl
= rld
+ rnum
;
1704 int best_cost
= INT_MAX
;
1708 HARD_REG_SET not_usable
;
1709 HARD_REG_SET used_by_other_reload
;
1711 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1712 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1713 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1715 CLEAR_HARD_REG_SET (used_by_other_reload
);
1716 for (k
= 0; k
< order
; k
++)
1718 int other
= reload_order
[k
];
1720 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1721 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1722 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1725 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1727 unsigned int regno
= i
;
1729 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1730 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1731 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1733 int this_cost
= spill_cost
[regno
];
1735 unsigned int this_nregs
= HARD_REGNO_NREGS (regno
, rl
->mode
);
1737 for (j
= 1; j
< this_nregs
; j
++)
1739 this_cost
+= spill_add_cost
[regno
+ j
];
1740 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1741 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1746 if (rl
->in
&& GET_CODE (rl
->in
) == REG
&& REGNO (rl
->in
) == regno
)
1748 if (rl
->out
&& GET_CODE (rl
->out
) == REG
&& REGNO (rl
->out
) == regno
)
1750 if (this_cost
< best_cost
1751 /* Among registers with equal cost, prefer caller-saved ones, or
1752 use REG_ALLOC_ORDER if it is defined. */
1753 || (this_cost
== best_cost
1754 #ifdef REG_ALLOC_ORDER
1755 && (inv_reg_alloc_order
[regno
]
1756 < inv_reg_alloc_order
[best_reg
])
1758 && call_used_regs
[regno
]
1759 && ! call_used_regs
[best_reg
]
1764 best_cost
= this_cost
;
1772 fprintf (rtl_dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1774 rl
->nregs
= HARD_REGNO_NREGS (best_reg
, rl
->mode
);
1775 rl
->regno
= best_reg
;
1777 EXECUTE_IF_SET_IN_REG_SET
1778 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
,
1780 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1783 EXECUTE_IF_SET_IN_REG_SET
1784 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
,
1786 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1789 for (i
= 0; i
< rl
->nregs
; i
++)
1791 if (spill_cost
[best_reg
+ i
] != 0
1792 || spill_add_cost
[best_reg
+ i
] != 0)
1794 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1799 /* Find more reload regs to satisfy the remaining need of an insn, which
1801 Do it by ascending class number, since otherwise a reg
1802 might be spilled for a big class and might fail to count
1803 for a smaller class even though it belongs to that class. */
1806 find_reload_regs (chain
)
1807 struct insn_chain
*chain
;
1811 /* In order to be certain of getting the registers we need,
1812 we must sort the reloads into order of increasing register class.
1813 Then our grabbing of reload registers will parallel the process
1814 that provided the reload registers. */
1815 for (i
= 0; i
< chain
->n_reloads
; i
++)
1817 /* Show whether this reload already has a hard reg. */
1818 if (chain
->rld
[i
].reg_rtx
)
1820 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1821 chain
->rld
[i
].regno
= regno
;
1823 = HARD_REGNO_NREGS (regno
, GET_MODE (chain
->rld
[i
].reg_rtx
));
1826 chain
->rld
[i
].regno
= -1;
1827 reload_order
[i
] = i
;
1830 n_reloads
= chain
->n_reloads
;
1831 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1833 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1836 fprintf (rtl_dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1838 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1840 /* Compute the order of preference for hard registers to spill. */
1842 order_regs_for_reload (chain
);
1844 for (i
= 0; i
< n_reloads
; i
++)
1846 int r
= reload_order
[i
];
1848 /* Ignore reloads that got marked inoperative. */
1849 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1850 && ! rld
[r
].optional
1851 && rld
[r
].regno
== -1)
1852 if (! find_reg (chain
, i
))
1854 spill_failure (chain
->insn
, rld
[r
].class);
1860 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1861 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1863 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1867 select_reload_regs ()
1869 struct insn_chain
*chain
;
1871 /* Try to satisfy the needs for each insn. */
1872 for (chain
= insns_need_reload
; chain
!= 0;
1873 chain
= chain
->next_need_reload
)
1874 find_reload_regs (chain
);
1877 /* Delete all insns that were inserted by emit_caller_save_insns during
1880 delete_caller_save_insns ()
1882 struct insn_chain
*c
= reload_insn_chain
;
1886 while (c
!= 0 && c
->is_caller_save_insn
)
1888 struct insn_chain
*next
= c
->next
;
1891 if (c
== reload_insn_chain
)
1892 reload_insn_chain
= next
;
1896 next
->prev
= c
->prev
;
1898 c
->prev
->next
= next
;
1899 c
->next
= unused_insn_chains
;
1900 unused_insn_chains
= c
;
1908 /* Handle the failure to find a register to spill.
1909 INSN should be one of the insns which needed this particular spill reg. */
1912 spill_failure (insn
, class)
1914 enum reg_class
class;
1916 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1917 if (asm_noperands (PATTERN (insn
)) >= 0)
1918 error_for_asm (insn
, "can't find a register in class `%s' while reloading `asm'",
1919 reg_class_names
[class]);
1922 error ("unable to find a register to spill in class `%s'",
1923 reg_class_names
[class]);
1924 fatal_insn ("this is the insn:", insn
);
1928 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1929 data that is dead in INSN. */
1932 delete_dead_insn (insn
)
1935 rtx prev
= prev_real_insn (insn
);
1938 /* If the previous insn sets a register that dies in our insn, delete it
1940 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
1941 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
1942 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
1943 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
1944 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
1945 delete_dead_insn (prev
);
1947 PUT_CODE (insn
, NOTE
);
1948 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1949 NOTE_SOURCE_FILE (insn
) = 0;
1952 /* Modify the home of pseudo-reg I.
1953 The new home is present in reg_renumber[I].
1955 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1956 or it may be -1, meaning there is none or it is not relevant.
1957 This is used so that all pseudos spilled from a given hard reg
1958 can share one stack slot. */
1961 alter_reg (i
, from_reg
)
1965 /* When outputting an inline function, this can happen
1966 for a reg that isn't actually used. */
1967 if (regno_reg_rtx
[i
] == 0)
1970 /* If the reg got changed to a MEM at rtl-generation time,
1972 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
1975 /* Modify the reg-rtx to contain the new hard reg
1976 number or else to contain its pseudo reg number. */
1977 REGNO (regno_reg_rtx
[i
])
1978 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
1980 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1981 allocate a stack slot for it. */
1983 if (reg_renumber
[i
] < 0
1984 && REG_N_REFS (i
) > 0
1985 && reg_equiv_constant
[i
] == 0
1986 && reg_equiv_memory_loc
[i
] == 0)
1989 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
1990 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
1993 /* Each pseudo reg has an inherent size which comes from its own mode,
1994 and a total size which provides room for paradoxical subregs
1995 which refer to the pseudo reg in wider modes.
1997 We can use a slot already allocated if it provides both
1998 enough inherent space and enough total space.
1999 Otherwise, we allocate a new slot, making sure that it has no less
2000 inherent space, and no less total space, then the previous slot. */
2003 /* No known place to spill from => no slot to reuse. */
2004 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
2005 inherent_size
== total_size
? 0 : -1);
2006 if (BYTES_BIG_ENDIAN
)
2007 /* Cancel the big-endian correction done in assign_stack_local.
2008 Get the address of the beginning of the slot.
2009 This is so we can do a big-endian correction unconditionally
2011 adjust
= inherent_size
- total_size
;
2013 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2015 /* Nothing can alias this slot except this pseudo. */
2016 set_mem_alias_set (x
, new_alias_set ());
2019 /* Reuse a stack slot if possible. */
2020 else if (spill_stack_slot
[from_reg
] != 0
2021 && spill_stack_slot_width
[from_reg
] >= total_size
2022 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2024 x
= spill_stack_slot
[from_reg
];
2026 /* Allocate a bigger slot. */
2029 /* Compute maximum size needed, both for inherent size
2030 and for total size. */
2031 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2034 if (spill_stack_slot
[from_reg
])
2036 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2038 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2039 if (spill_stack_slot_width
[from_reg
] > total_size
)
2040 total_size
= spill_stack_slot_width
[from_reg
];
2043 /* Make a slot with that size. */
2044 x
= assign_stack_local (mode
, total_size
,
2045 inherent_size
== total_size
? 0 : -1);
2048 /* All pseudos mapped to this slot can alias each other. */
2049 if (spill_stack_slot
[from_reg
])
2050 set_mem_alias_set (x
, MEM_ALIAS_SET (spill_stack_slot
[from_reg
]));
2052 set_mem_alias_set (x
, new_alias_set ());
2054 if (BYTES_BIG_ENDIAN
)
2056 /* Cancel the big-endian correction done in assign_stack_local.
2057 Get the address of the beginning of the slot.
2058 This is so we can do a big-endian correction unconditionally
2060 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2063 = adjust_address_nv (x
, mode_for_size (total_size
2069 spill_stack_slot
[from_reg
] = stack_slot
;
2070 spill_stack_slot_width
[from_reg
] = total_size
;
2073 /* On a big endian machine, the "address" of the slot
2074 is the address of the low part that fits its inherent mode. */
2075 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2076 adjust
+= (total_size
- inherent_size
);
2078 /* If we have any adjustment to make, or if the stack slot is the
2079 wrong mode, make a new stack slot. */
2080 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2082 /* If we have a decl for the original register, set it for the
2083 memory. If this is a shared MEM, make a copy. */
2084 if (REG_EXPR (regno_reg_rtx
[i
])
2085 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx
[i
]))) == 'd')
2087 rtx decl
= DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx
[i
]));
2089 /* We can do this only for the DECLs home pseudo, not for
2090 any copies of it, since otherwise when the stack slot
2091 is reused, nonoverlapping_memrefs_p might think they
2093 if (decl
&& GET_CODE (decl
) == REG
&& REGNO (decl
) == (unsigned) i
)
2095 if (from_reg
!= -1 && spill_stack_slot
[from_reg
] == x
)
2098 set_mem_attrs_from_reg (x
, regno_reg_rtx
[i
]);
2102 /* Save the stack slot for later. */
2103 reg_equiv_memory_loc
[i
] = x
;
2107 /* Mark the slots in regs_ever_live for the hard regs
2108 used by pseudo-reg number REGNO. */
2111 mark_home_live (regno
)
2116 i
= reg_renumber
[regno
];
2119 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2121 regs_ever_live
[i
++] = 1;
2124 /* This function handles the tracking of elimination offsets around branches.
2126 X is a piece of RTL being scanned.
2128 INSN is the insn that it came from, if any.
2130 INITIAL_P is nonzero if we are to set the offset to be the initial
2131 offset and zero if we are setting the offset of the label to be the
2135 set_label_offsets (x
, insn
, initial_p
)
2140 enum rtx_code code
= GET_CODE (x
);
2143 struct elim_table
*p
;
2148 if (LABEL_REF_NONLOCAL_P (x
))
2153 /* ... fall through ... */
2156 /* If we know nothing about this label, set the desired offsets. Note
2157 that this sets the offset at a label to be the offset before a label
2158 if we don't know anything about the label. This is not correct for
2159 the label after a BARRIER, but is the best guess we can make. If
2160 we guessed wrong, we will suppress an elimination that might have
2161 been possible had we been able to guess correctly. */
2163 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2165 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2166 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2167 = (initial_p
? reg_eliminate
[i
].initial_offset
2168 : reg_eliminate
[i
].offset
);
2169 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2172 /* Otherwise, if this is the definition of a label and it is
2173 preceded by a BARRIER, set our offsets to the known offset of
2177 && (tem
= prev_nonnote_insn (insn
)) != 0
2178 && GET_CODE (tem
) == BARRIER
)
2179 set_offsets_for_label (insn
);
2181 /* If neither of the above cases is true, compare each offset
2182 with those previously recorded and suppress any eliminations
2183 where the offsets disagree. */
2185 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2186 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2187 != (initial_p
? reg_eliminate
[i
].initial_offset
2188 : reg_eliminate
[i
].offset
))
2189 reg_eliminate
[i
].can_eliminate
= 0;
2194 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2196 /* ... fall through ... */
2200 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2201 and hence must have all eliminations at their initial offsets. */
2202 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2203 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2204 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2210 /* Each of the labels in the parallel or address vector must be
2211 at their initial offsets. We want the first field for PARALLEL
2212 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2214 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2215 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2220 /* We only care about setting PC. If the source is not RETURN,
2221 IF_THEN_ELSE, or a label, disable any eliminations not at
2222 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2223 isn't one of those possibilities. For branches to a label,
2224 call ourselves recursively.
2226 Note that this can disable elimination unnecessarily when we have
2227 a non-local goto since it will look like a non-constant jump to
2228 someplace in the current function. This isn't a significant
2229 problem since such jumps will normally be when all elimination
2230 pairs are back to their initial offsets. */
2232 if (SET_DEST (x
) != pc_rtx
)
2235 switch (GET_CODE (SET_SRC (x
)))
2242 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2246 tem
= XEXP (SET_SRC (x
), 1);
2247 if (GET_CODE (tem
) == LABEL_REF
)
2248 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2249 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2252 tem
= XEXP (SET_SRC (x
), 2);
2253 if (GET_CODE (tem
) == LABEL_REF
)
2254 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2255 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2263 /* If we reach here, all eliminations must be at their initial
2264 offset because we are doing a jump to a variable address. */
2265 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2266 if (p
->offset
!= p
->initial_offset
)
2267 p
->can_eliminate
= 0;
2275 /* Scan X and replace any eliminable registers (such as fp) with a
2276 replacement (such as sp), plus an offset.
2278 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2279 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2280 MEM, we are allowed to replace a sum of a register and the constant zero
2281 with the register, which we cannot do outside a MEM. In addition, we need
2282 to record the fact that a register is referenced outside a MEM.
2284 If INSN is an insn, it is the insn containing X. If we replace a REG
2285 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2286 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2287 the REG is being modified.
2289 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2290 That's used when we eliminate in expressions stored in notes.
2291 This means, do not set ref_outside_mem even if the reference
2294 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2295 replacements done assuming all offsets are at their initial values. If
2296 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2297 encounter, return the actual location so that find_reloads will do
2298 the proper thing. */
2301 eliminate_regs (x
, mem_mode
, insn
)
2303 enum machine_mode mem_mode
;
2306 enum rtx_code code
= GET_CODE (x
);
2307 struct elim_table
*ep
;
2314 if (! current_function_decl
)
2334 /* This is only for the benefit of the debugging backends, which call
2335 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2336 removed after CSE. */
2337 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2338 if (GET_CODE (new) == MEM
)
2339 return XEXP (new, 0);
2345 /* First handle the case where we encounter a bare register that
2346 is eliminable. Replace it with a PLUS. */
2347 if (regno
< FIRST_PSEUDO_REGISTER
)
2349 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2351 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2352 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2355 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2356 && reg_equiv_constant
&& reg_equiv_constant
[regno
]
2357 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2358 return eliminate_regs (copy_rtx (reg_equiv_constant
[regno
]),
2362 /* You might think handling MINUS in a manner similar to PLUS is a
2363 good idea. It is not. It has been tried multiple times and every
2364 time the change has had to have been reverted.
2366 Other parts of reload know a PLUS is special (gen_reload for example)
2367 and require special code to handle code a reloaded PLUS operand.
2369 Also consider backends where the flags register is clobbered by a
2370 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2371 lea instruction comes to mind). If we try to reload a MINUS, we
2372 may kill the flags register that was holding a useful value.
2374 So, please before trying to handle MINUS, consider reload as a
2375 whole instead of this little section as well as the backend issues. */
2377 /* If this is the sum of an eliminable register and a constant, rework
2379 if (GET_CODE (XEXP (x
, 0)) == REG
2380 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2381 && CONSTANT_P (XEXP (x
, 1)))
2383 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2385 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2387 /* The only time we want to replace a PLUS with a REG (this
2388 occurs when the constant operand of the PLUS is the negative
2389 of the offset) is when we are inside a MEM. We won't want
2390 to do so at other times because that would change the
2391 structure of the insn in a way that reload can't handle.
2392 We special-case the commonest situation in
2393 eliminate_regs_in_insn, so just replace a PLUS with a
2394 PLUS here, unless inside a MEM. */
2395 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2396 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2399 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2400 plus_constant (XEXP (x
, 1),
2401 ep
->previous_offset
));
2404 /* If the register is not eliminable, we are done since the other
2405 operand is a constant. */
2409 /* If this is part of an address, we want to bring any constant to the
2410 outermost PLUS. We will do this by doing register replacement in
2411 our operands and seeing if a constant shows up in one of them.
2413 Note that there is no risk of modifying the structure of the insn,
2414 since we only get called for its operands, thus we are either
2415 modifying the address inside a MEM, or something like an address
2416 operand of a load-address insn. */
2419 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2420 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2422 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2424 /* If one side is a PLUS and the other side is a pseudo that
2425 didn't get a hard register but has a reg_equiv_constant,
2426 we must replace the constant here since it may no longer
2427 be in the position of any operand. */
2428 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2429 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2430 && reg_renumber
[REGNO (new1
)] < 0
2431 && reg_equiv_constant
!= 0
2432 && reg_equiv_constant
[REGNO (new1
)] != 0)
2433 new1
= reg_equiv_constant
[REGNO (new1
)];
2434 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2435 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2436 && reg_renumber
[REGNO (new0
)] < 0
2437 && reg_equiv_constant
[REGNO (new0
)] != 0)
2438 new0
= reg_equiv_constant
[REGNO (new0
)];
2440 new = form_sum (new0
, new1
);
2442 /* As above, if we are not inside a MEM we do not want to
2443 turn a PLUS into something else. We might try to do so here
2444 for an addition of 0 if we aren't optimizing. */
2445 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2446 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2454 /* If this is the product of an eliminable register and a
2455 constant, apply the distribute law and move the constant out
2456 so that we have (plus (mult ..) ..). This is needed in order
2457 to keep load-address insns valid. This case is pathological.
2458 We ignore the possibility of overflow here. */
2459 if (GET_CODE (XEXP (x
, 0)) == REG
2460 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2461 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2462 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2464 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2467 /* Refs inside notes don't count for this purpose. */
2468 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2469 || GET_CODE (insn
) == INSN_LIST
)))
2470 ep
->ref_outside_mem
= 1;
2473 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2474 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2477 /* ... fall through ... */
2481 /* See comments before PLUS about handling MINUS. */
2483 case DIV
: case UDIV
:
2484 case MOD
: case UMOD
:
2485 case AND
: case IOR
: case XOR
:
2486 case ROTATERT
: case ROTATE
:
2487 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2489 case GE
: case GT
: case GEU
: case GTU
:
2490 case LE
: case LT
: case LEU
: case LTU
:
2492 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2494 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2496 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2497 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2502 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2505 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2506 if (new != XEXP (x
, 0))
2508 /* If this is a REG_DEAD note, it is not valid anymore.
2509 Using the eliminated version could result in creating a
2510 REG_DEAD note for the stack or frame pointer. */
2511 if (GET_MODE (x
) == REG_DEAD
)
2513 ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
)
2516 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2520 /* ... fall through ... */
2523 /* Now do eliminations in the rest of the chain. If this was
2524 an EXPR_LIST, this might result in allocating more memory than is
2525 strictly needed, but it simplifies the code. */
2528 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2529 if (new != XEXP (x
, 1))
2531 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2539 case STRICT_LOW_PART
:
2541 case SIGN_EXTEND
: case ZERO_EXTEND
:
2542 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2543 case FLOAT
: case FIX
:
2544 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2548 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2549 if (new != XEXP (x
, 0))
2550 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2554 /* Similar to above processing, but preserve SUBREG_BYTE.
2555 Convert (subreg (mem)) to (mem) if not paradoxical.
2556 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2557 pseudo didn't get a hard reg, we must replace this with the
2558 eliminated version of the memory location because push_reloads
2559 may do the replacement in certain circumstances. */
2560 if (GET_CODE (SUBREG_REG (x
)) == REG
2561 && (GET_MODE_SIZE (GET_MODE (x
))
2562 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2563 && reg_equiv_memory_loc
!= 0
2564 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2566 new = SUBREG_REG (x
);
2569 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
2571 if (new != SUBREG_REG (x
))
2573 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2574 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2576 if (GET_CODE (new) == MEM
2577 && ((x_size
< new_size
2578 #ifdef WORD_REGISTER_OPERATIONS
2579 /* On these machines, combine can create rtl of the form
2580 (set (subreg:m1 (reg:m2 R) 0) ...)
2581 where m1 < m2, and expects something interesting to
2582 happen to the entire word. Moreover, it will use the
2583 (reg:m2 R) later, expecting all bits to be preserved.
2584 So if the number of words is the same, preserve the
2585 subreg so that push_reloads can see it. */
2586 && ! ((x_size
- 1) / UNITS_PER_WORD
2587 == (new_size
-1 ) / UNITS_PER_WORD
)
2590 || x_size
== new_size
)
2592 return adjust_address_nv (new, GET_MODE (x
), SUBREG_BYTE (x
));
2594 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_BYTE (x
));
2600 /* This is only for the benefit of the debugging backends, which call
2601 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2602 removed after CSE. */
2603 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2604 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
2606 /* Our only special processing is to pass the mode of the MEM to our
2607 recursive call and copy the flags. While we are here, handle this
2608 case more efficiently. */
2610 replace_equiv_address_nv (x
,
2611 eliminate_regs (XEXP (x
, 0),
2612 GET_MODE (x
), insn
));
2615 /* Handle insn_list USE that a call to a pure function may generate. */
2616 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2617 if (new != XEXP (x
, 0))
2618 return gen_rtx_USE (GET_MODE (x
), new);
2630 /* Process each of our operands recursively. If any have changed, make a
2632 fmt
= GET_RTX_FORMAT (code
);
2633 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2637 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
2638 if (new != XEXP (x
, i
) && ! copied
)
2640 rtx new_x
= rtx_alloc (code
);
2642 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2643 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
2649 else if (*fmt
== 'E')
2652 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2654 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
2655 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2657 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2661 rtx new_x
= rtx_alloc (code
);
2663 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2664 + (sizeof (new_x
->fld
[0])
2665 * GET_RTX_LENGTH (code
))));
2669 XVEC (x
, i
) = new_v
;
2672 XVECEXP (x
, i
, j
) = new;
2680 /* Scan rtx X for modifications of elimination target registers. Update
2681 the table of eliminables to reflect the changed state. MEM_MODE is
2682 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2685 elimination_effects (x
, mem_mode
)
2687 enum machine_mode mem_mode
;
2690 enum rtx_code code
= GET_CODE (x
);
2691 struct elim_table
*ep
;
2718 /* First handle the case where we encounter a bare register that
2719 is eliminable. Replace it with a PLUS. */
2720 if (regno
< FIRST_PSEUDO_REGISTER
)
2722 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2724 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2727 ep
->ref_outside_mem
= 1;
2732 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2733 && reg_equiv_constant
[regno
]
2734 && ! function_invariant_p (reg_equiv_constant
[regno
]))
2735 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2744 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2745 if (ep
->to_rtx
== XEXP (x
, 0))
2747 int size
= GET_MODE_SIZE (mem_mode
);
2749 /* If more bytes than MEM_MODE are pushed, account for them. */
2750 #ifdef PUSH_ROUNDING
2751 if (ep
->to_rtx
== stack_pointer_rtx
)
2752 size
= PUSH_ROUNDING (size
);
2754 if (code
== PRE_DEC
|| code
== POST_DEC
)
2756 else if (code
== PRE_INC
|| code
== POST_INC
)
2758 else if ((code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2759 && GET_CODE (XEXP (x
, 1)) == PLUS
2760 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2761 && CONSTANT_P (XEXP (XEXP (x
, 1), 1)))
2762 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2765 /* These two aren't unary operators. */
2766 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2769 /* Fall through to generic unary operation case. */
2770 case STRICT_LOW_PART
:
2772 case SIGN_EXTEND
: case ZERO_EXTEND
:
2773 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2774 case FLOAT
: case FIX
:
2775 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2779 elimination_effects (XEXP (x
, 0), mem_mode
);
2783 if (GET_CODE (SUBREG_REG (x
)) == REG
2784 && (GET_MODE_SIZE (GET_MODE (x
))
2785 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2786 && reg_equiv_memory_loc
!= 0
2787 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2790 elimination_effects (SUBREG_REG (x
), mem_mode
);
2794 /* If using a register that is the source of an eliminate we still
2795 think can be performed, note it cannot be performed since we don't
2796 know how this register is used. */
2797 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2798 if (ep
->from_rtx
== XEXP (x
, 0))
2799 ep
->can_eliminate
= 0;
2801 elimination_effects (XEXP (x
, 0), mem_mode
);
2805 /* If clobbering a register that is the replacement register for an
2806 elimination we still think can be performed, note that it cannot
2807 be performed. Otherwise, we need not be concerned about it. */
2808 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2809 if (ep
->to_rtx
== XEXP (x
, 0))
2810 ep
->can_eliminate
= 0;
2812 elimination_effects (XEXP (x
, 0), mem_mode
);
2816 /* Check for setting a register that we know about. */
2817 if (GET_CODE (SET_DEST (x
)) == REG
)
2819 /* See if this is setting the replacement register for an
2822 If DEST is the hard frame pointer, we do nothing because we
2823 assume that all assignments to the frame pointer are for
2824 non-local gotos and are being done at a time when they are valid
2825 and do not disturb anything else. Some machines want to
2826 eliminate a fake argument pointer (or even a fake frame pointer)
2827 with either the real frame or the stack pointer. Assignments to
2828 the hard frame pointer must not prevent this elimination. */
2830 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2832 if (ep
->to_rtx
== SET_DEST (x
)
2833 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2835 /* If it is being incremented, adjust the offset. Otherwise,
2836 this elimination can't be done. */
2837 rtx src
= SET_SRC (x
);
2839 if (GET_CODE (src
) == PLUS
2840 && XEXP (src
, 0) == SET_DEST (x
)
2841 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2842 ep
->offset
-= INTVAL (XEXP (src
, 1));
2844 ep
->can_eliminate
= 0;
2848 elimination_effects (SET_DEST (x
), 0);
2849 elimination_effects (SET_SRC (x
), 0);
2853 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2856 /* Our only special processing is to pass the mode of the MEM to our
2858 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2865 fmt
= GET_RTX_FORMAT (code
);
2866 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2869 elimination_effects (XEXP (x
, i
), mem_mode
);
2870 else if (*fmt
== 'E')
2871 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2872 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2876 /* Descend through rtx X and verify that no references to eliminable registers
2877 remain. If any do remain, mark the involved register as not
2881 check_eliminable_occurrences (x
)
2891 code
= GET_CODE (x
);
2893 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2895 struct elim_table
*ep
;
2897 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2898 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2899 ep
->can_eliminate
= 0;
2903 fmt
= GET_RTX_FORMAT (code
);
2904 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2907 check_eliminable_occurrences (XEXP (x
, i
));
2908 else if (*fmt
== 'E')
2911 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2912 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2917 /* Scan INSN and eliminate all eliminable registers in it.
2919 If REPLACE is nonzero, do the replacement destructively. Also
2920 delete the insn as dead it if it is setting an eliminable register.
2922 If REPLACE is zero, do all our allocations in reload_obstack.
2924 If no eliminations were done and this insn doesn't require any elimination
2925 processing (these are not identical conditions: it might be updating sp,
2926 but not referencing fp; this needs to be seen during reload_as_needed so
2927 that the offset between fp and sp can be taken into consideration), zero
2928 is returned. Otherwise, 1 is returned. */
2931 eliminate_regs_in_insn (insn
, replace
)
2935 int icode
= recog_memoized (insn
);
2936 rtx old_body
= PATTERN (insn
);
2937 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2938 rtx old_set
= single_set (insn
);
2942 rtx substed_operand
[MAX_RECOG_OPERANDS
];
2943 rtx orig_operand
[MAX_RECOG_OPERANDS
];
2944 struct elim_table
*ep
;
2946 if (! insn_is_asm
&& icode
< 0)
2948 if (GET_CODE (PATTERN (insn
)) == USE
2949 || GET_CODE (PATTERN (insn
)) == CLOBBER
2950 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
2951 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
2952 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
)
2957 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
2958 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
2960 /* Check for setting an eliminable register. */
2961 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2962 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
2964 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2965 /* If this is setting the frame pointer register to the
2966 hardware frame pointer register and this is an elimination
2967 that will be done (tested above), this insn is really
2968 adjusting the frame pointer downward to compensate for
2969 the adjustment done before a nonlocal goto. */
2970 if (ep
->from
== FRAME_POINTER_REGNUM
2971 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
2973 rtx base
= SET_SRC (old_set
);
2974 rtx base_insn
= insn
;
2977 while (base
!= ep
->to_rtx
)
2979 rtx prev_insn
, prev_set
;
2981 if (GET_CODE (base
) == PLUS
2982 && GET_CODE (XEXP (base
, 1)) == CONST_INT
)
2984 offset
+= INTVAL (XEXP (base
, 1));
2985 base
= XEXP (base
, 0);
2987 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
2988 && (prev_set
= single_set (prev_insn
)) != 0
2989 && rtx_equal_p (SET_DEST (prev_set
), base
))
2991 base
= SET_SRC (prev_set
);
2992 base_insn
= prev_insn
;
2998 if (base
== ep
->to_rtx
)
3001 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3003 new_body
= old_body
;
3006 new_body
= copy_insn (old_body
);
3007 if (REG_NOTES (insn
))
3008 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3010 PATTERN (insn
) = new_body
;
3011 old_set
= single_set (insn
);
3013 /* First see if this insn remains valid when we
3014 make the change. If not, keep the INSN_CODE
3015 the same and let reload fit it up. */
3016 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3017 validate_change (insn
, &SET_DEST (old_set
),
3019 if (! apply_change_group ())
3021 SET_SRC (old_set
) = src
;
3022 SET_DEST (old_set
) = ep
->to_rtx
;
3031 /* In this case this insn isn't serving a useful purpose. We
3032 will delete it in reload_as_needed once we know that this
3033 elimination is, in fact, being done.
3035 If REPLACE isn't set, we can't delete this insn, but needn't
3036 process it since it won't be used unless something changes. */
3039 delete_dead_insn (insn
);
3047 /* We allow one special case which happens to work on all machines we
3048 currently support: a single set with the source being a PLUS of an
3049 eliminable register and a constant. */
3051 && GET_CODE (SET_DEST (old_set
)) == REG
3052 && GET_CODE (SET_SRC (old_set
)) == PLUS
3053 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
3054 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
3055 && REGNO (XEXP (SET_SRC (old_set
), 0)) < FIRST_PSEUDO_REGISTER
)
3057 rtx reg
= XEXP (SET_SRC (old_set
), 0);
3058 int offset
= INTVAL (XEXP (SET_SRC (old_set
), 1));
3060 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3061 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3063 offset
+= ep
->offset
;
3068 /* We assume here that if we need a PARALLEL with
3069 CLOBBERs for this assignment, we can do with the
3070 MATCH_SCRATCHes that add_clobbers allocates.
3071 There's not much we can do if that doesn't work. */
3072 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3076 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, &num_clobbers
);
3079 rtvec vec
= rtvec_alloc (num_clobbers
+ 1);
3081 vec
->elem
[0] = PATTERN (insn
);
3082 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
3083 add_clobbers (PATTERN (insn
), INSN_CODE (insn
));
3085 if (INSN_CODE (insn
) < 0)
3090 new_body
= old_body
;
3093 new_body
= copy_insn (old_body
);
3094 if (REG_NOTES (insn
))
3095 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3097 PATTERN (insn
) = new_body
;
3098 old_set
= single_set (insn
);
3100 XEXP (SET_SRC (old_set
), 0) = ep
->to_rtx
;
3101 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
3104 /* This can't have an effect on elimination offsets, so skip right
3110 /* Determine the effects of this insn on elimination offsets. */
3111 elimination_effects (old_body
, 0);
3113 /* Eliminate all eliminable registers occurring in operands that
3114 can be handled by reload. */
3115 extract_insn (insn
);
3116 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3118 orig_operand
[i
] = recog_data
.operand
[i
];
3119 substed_operand
[i
] = recog_data
.operand
[i
];
3121 /* For an asm statement, every operand is eliminable. */
3122 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3124 /* Check for setting a register that we know about. */
3125 if (recog_data
.operand_type
[i
] != OP_IN
3126 && GET_CODE (orig_operand
[i
]) == REG
)
3128 /* If we are assigning to a register that can be eliminated, it
3129 must be as part of a PARALLEL, since the code above handles
3130 single SETs. We must indicate that we can no longer
3131 eliminate this reg. */
3132 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3134 if (ep
->from_rtx
== orig_operand
[i
] && ep
->can_eliminate
)
3135 ep
->can_eliminate
= 0;
3138 substed_operand
[i
] = eliminate_regs (recog_data
.operand
[i
], 0,
3139 replace
? insn
: NULL_RTX
);
3140 if (substed_operand
[i
] != orig_operand
[i
])
3142 /* Terminate the search in check_eliminable_occurrences at
3144 *recog_data
.operand_loc
[i
] = 0;
3146 /* If an output operand changed from a REG to a MEM and INSN is an
3147 insn, write a CLOBBER insn. */
3148 if (recog_data
.operand_type
[i
] != OP_IN
3149 && GET_CODE (orig_operand
[i
]) == REG
3150 && GET_CODE (substed_operand
[i
]) == MEM
3152 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3157 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3158 *recog_data
.dup_loc
[i
]
3159 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3161 /* If any eliminable remain, they aren't eliminable anymore. */
3162 check_eliminable_occurrences (old_body
);
3164 /* Substitute the operands; the new values are in the substed_operand
3166 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3167 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3168 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3169 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3171 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3172 re-recognize the insn. We do this in case we had a simple addition
3173 but now can do this as a load-address. This saves an insn in this
3175 If re-recognition fails, the old insn code number will still be used,
3176 and some register operands may have changed into PLUS expressions.
3177 These will be handled by find_reloads by loading them into a register
3182 /* If we aren't replacing things permanently and we changed something,
3183 make another copy to ensure that all the RTL is new. Otherwise
3184 things can go wrong if find_reload swaps commutative operands
3185 and one is inside RTL that has been copied while the other is not. */
3186 new_body
= old_body
;
3189 new_body
= copy_insn (old_body
);
3190 if (REG_NOTES (insn
))
3191 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3193 PATTERN (insn
) = new_body
;
3195 /* If we had a move insn but now we don't, rerecognize it. This will
3196 cause spurious re-recognition if the old move had a PARALLEL since
3197 the new one still will, but we can't call single_set without
3198 having put NEW_BODY into the insn and the re-recognition won't
3199 hurt in this rare case. */
3200 /* ??? Why this huge if statement - why don't we just rerecognize the
3204 && ((GET_CODE (SET_SRC (old_set
)) == REG
3205 && (GET_CODE (new_body
) != SET
3206 || GET_CODE (SET_SRC (new_body
)) != REG
))
3207 /* If this was a load from or store to memory, compare
3208 the MEM in recog_data.operand to the one in the insn.
3209 If they are not equal, then rerecognize the insn. */
3211 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3212 && SET_SRC (old_set
) != recog_data
.operand
[1])
3213 || (GET_CODE (SET_DEST (old_set
)) == MEM
3214 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3215 /* If this was an add insn before, rerecognize. */
3216 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3218 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3220 INSN_CODE (insn
) = icode
;
3224 /* Restore the old body. If there were any changes to it, we made a copy
3225 of it while the changes were still in place, so we'll correctly return
3226 a modified insn below. */
3229 /* Restore the old body. */
3230 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3231 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3232 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3233 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3236 /* Update all elimination pairs to reflect the status after the current
3237 insn. The changes we make were determined by the earlier call to
3238 elimination_effects.
3240 We also detect cases where register elimination cannot be done,
3241 namely, if a register would be both changed and referenced outside a MEM
3242 in the resulting insn since such an insn is often undefined and, even if
3243 not, we cannot know what meaning will be given to it. Note that it is
3244 valid to have a register used in an address in an insn that changes it
3245 (presumably with a pre- or post-increment or decrement).
3247 If anything changes, return nonzero. */
3249 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3251 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3252 ep
->can_eliminate
= 0;
3254 ep
->ref_outside_mem
= 0;
3256 if (ep
->previous_offset
!= ep
->offset
)
3261 /* If we changed something, perform elimination in REG_NOTES. This is
3262 needed even when REPLACE is zero because a REG_DEAD note might refer
3263 to a register that we eliminate and could cause a different number
3264 of spill registers to be needed in the final reload pass than in
3266 if (val
&& REG_NOTES (insn
) != 0)
3267 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3272 /* Loop through all elimination pairs.
3273 Recalculate the number not at initial offset.
3275 Compute the maximum offset (minimum offset if the stack does not
3276 grow downward) for each elimination pair. */
3279 update_eliminable_offsets ()
3281 struct elim_table
*ep
;
3283 num_not_at_initial_offset
= 0;
3284 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3286 ep
->previous_offset
= ep
->offset
;
3287 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3288 num_not_at_initial_offset
++;
3292 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3293 replacement we currently believe is valid, mark it as not eliminable if X
3294 modifies DEST in any way other than by adding a constant integer to it.
3296 If DEST is the frame pointer, we do nothing because we assume that
3297 all assignments to the hard frame pointer are nonlocal gotos and are being
3298 done at a time when they are valid and do not disturb anything else.
3299 Some machines want to eliminate a fake argument pointer with either the
3300 frame or stack pointer. Assignments to the hard frame pointer must not
3301 prevent this elimination.
3303 Called via note_stores from reload before starting its passes to scan
3304 the insns of the function. */
3307 mark_not_eliminable (dest
, x
, data
)
3310 void *data ATTRIBUTE_UNUSED
;
3314 /* A SUBREG of a hard register here is just changing its mode. We should
3315 not see a SUBREG of an eliminable hard register, but check just in
3317 if (GET_CODE (dest
) == SUBREG
)
3318 dest
= SUBREG_REG (dest
);
3320 if (dest
== hard_frame_pointer_rtx
)
3323 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3324 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3325 && (GET_CODE (x
) != SET
3326 || GET_CODE (SET_SRC (x
)) != PLUS
3327 || XEXP (SET_SRC (x
), 0) != dest
3328 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3330 reg_eliminate
[i
].can_eliminate_previous
3331 = reg_eliminate
[i
].can_eliminate
= 0;
3336 /* Verify that the initial elimination offsets did not change since the
3337 last call to set_initial_elim_offsets. This is used to catch cases
3338 where something illegal happened during reload_as_needed that could
3339 cause incorrect code to be generated if we did not check for it. */
3342 verify_initial_elim_offsets ()
3346 #ifdef ELIMINABLE_REGS
3347 struct elim_table
*ep
;
3349 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3351 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3352 if (t
!= ep
->initial_offset
)
3356 INITIAL_FRAME_POINTER_OFFSET (t
);
3357 if (t
!= reg_eliminate
[0].initial_offset
)
3362 /* Reset all offsets on eliminable registers to their initial values. */
3365 set_initial_elim_offsets ()
3367 struct elim_table
*ep
= reg_eliminate
;
3369 #ifdef ELIMINABLE_REGS
3370 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3372 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3373 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3376 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3377 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3380 num_not_at_initial_offset
= 0;
3383 /* Initialize the known label offsets.
3384 Set a known offset for each forced label to be at the initial offset
3385 of each elimination. We do this because we assume that all
3386 computed jumps occur from a location where each elimination is
3387 at its initial offset.
3388 For all other labels, show that we don't know the offsets. */
3391 set_initial_label_offsets ()
3394 memset ((char *) &offsets_known_at
[get_first_label_num ()], 0, num_labels
);
3396 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3398 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3401 /* Set all elimination offsets to the known values for the code label given
3405 set_offsets_for_label (insn
)
3409 int label_nr
= CODE_LABEL_NUMBER (insn
);
3410 struct elim_table
*ep
;
3412 num_not_at_initial_offset
= 0;
3413 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3415 ep
->offset
= ep
->previous_offset
= offsets_at
[label_nr
][i
];
3416 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3417 num_not_at_initial_offset
++;
3421 /* See if anything that happened changes which eliminations are valid.
3422 For example, on the SPARC, whether or not the frame pointer can
3423 be eliminated can depend on what registers have been used. We need
3424 not check some conditions again (such as flag_omit_frame_pointer)
3425 since they can't have changed. */
3428 update_eliminables (pset
)
3431 int previous_frame_pointer_needed
= frame_pointer_needed
;
3432 struct elim_table
*ep
;
3434 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3435 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3436 #ifdef ELIMINABLE_REGS
3437 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3440 ep
->can_eliminate
= 0;
3442 /* Look for the case where we have discovered that we can't replace
3443 register A with register B and that means that we will now be
3444 trying to replace register A with register C. This means we can
3445 no longer replace register C with register B and we need to disable
3446 such an elimination, if it exists. This occurs often with A == ap,
3447 B == sp, and C == fp. */
3449 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3451 struct elim_table
*op
;
3454 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3456 /* Find the current elimination for ep->from, if there is a
3458 for (op
= reg_eliminate
;
3459 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3460 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3466 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3468 for (op
= reg_eliminate
;
3469 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3470 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3471 op
->can_eliminate
= 0;
3475 /* See if any registers that we thought we could eliminate the previous
3476 time are no longer eliminable. If so, something has changed and we
3477 must spill the register. Also, recompute the number of eliminable
3478 registers and see if the frame pointer is needed; it is if there is
3479 no elimination of the frame pointer that we can perform. */
3481 frame_pointer_needed
= 1;
3482 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3484 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3485 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3486 frame_pointer_needed
= 0;
3488 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3490 ep
->can_eliminate_previous
= 0;
3491 SET_HARD_REG_BIT (*pset
, ep
->from
);
3496 /* If we didn't need a frame pointer last time, but we do now, spill
3497 the hard frame pointer. */
3498 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3499 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3502 /* Initialize the table of registers to eliminate. */
3507 struct elim_table
*ep
;
3508 #ifdef ELIMINABLE_REGS
3509 const struct elim_table_1
*ep1
;
3513 reg_eliminate
= (struct elim_table
*)
3514 xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3516 /* Does this function require a frame pointer? */
3518 frame_pointer_needed
= (! flag_omit_frame_pointer
3519 #ifdef EXIT_IGNORE_STACK
3520 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3521 and restore sp for alloca. So we can't eliminate
3522 the frame pointer in that case. At some point,
3523 we should improve this by emitting the
3524 sp-adjusting insns for this case. */
3525 || (current_function_calls_alloca
3526 && EXIT_IGNORE_STACK
)
3528 || FRAME_POINTER_REQUIRED
);
3532 #ifdef ELIMINABLE_REGS
3533 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3534 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3536 ep
->from
= ep1
->from
;
3538 ep
->can_eliminate
= ep
->can_eliminate_previous
3539 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3540 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3543 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3544 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3545 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3546 = ! frame_pointer_needed
;
3549 /* Count the number of eliminable registers and build the FROM and TO
3550 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3551 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3552 We depend on this. */
3553 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3555 num_eliminable
+= ep
->can_eliminate
;
3556 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3557 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3561 /* Kick all pseudos out of hard register REGNO.
3563 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3564 because we found we can't eliminate some register. In the case, no pseudos
3565 are allowed to be in the register, even if they are only in a block that
3566 doesn't require spill registers, unlike the case when we are spilling this
3567 hard reg to produce another spill register.
3569 Return nonzero if any pseudos needed to be kicked out. */
3572 spill_hard_reg (regno
, cant_eliminate
)
3580 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3581 regs_ever_live
[regno
] = 1;
3584 /* Spill every pseudo reg that was allocated to this reg
3585 or to something that overlaps this reg. */
3587 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3588 if (reg_renumber
[i
] >= 0
3589 && (unsigned int) reg_renumber
[i
] <= regno
3590 && ((unsigned int) reg_renumber
[i
]
3591 + HARD_REGNO_NREGS ((unsigned int) reg_renumber
[i
],
3592 PSEUDO_REGNO_MODE (i
))
3594 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3597 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3598 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3601 ior_hard_reg_set (set1
, set2
)
3602 HARD_REG_SET
*set1
, *set2
;
3604 IOR_HARD_REG_SET (*set1
, *set2
);
3607 /* After find_reload_regs has been run for all insn that need reloads,
3608 and/or spill_hard_regs was called, this function is used to actually
3609 spill pseudo registers and try to reallocate them. It also sets up the
3610 spill_regs array for use by choose_reload_regs. */
3613 finish_spills (global
)
3616 struct insn_chain
*chain
;
3617 int something_changed
= 0;
3620 /* Build the spill_regs array for the function. */
3621 /* If there are some registers still to eliminate and one of the spill regs
3622 wasn't ever used before, additional stack space may have to be
3623 allocated to store this register. Thus, we may have changed the offset
3624 between the stack and frame pointers, so mark that something has changed.
3626 One might think that we need only set VAL to 1 if this is a call-used
3627 register. However, the set of registers that must be saved by the
3628 prologue is not identical to the call-used set. For example, the
3629 register used by the call insn for the return PC is a call-used register,
3630 but must be saved by the prologue. */
3633 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3634 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3636 spill_reg_order
[i
] = n_spills
;
3637 spill_regs
[n_spills
++] = i
;
3638 if (num_eliminable
&& ! regs_ever_live
[i
])
3639 something_changed
= 1;
3640 regs_ever_live
[i
] = 1;
3643 spill_reg_order
[i
] = -1;
3645 EXECUTE_IF_SET_IN_REG_SET
3646 (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
,
3648 /* Record the current hard register the pseudo is allocated to in
3649 pseudo_previous_regs so we avoid reallocating it to the same
3650 hard reg in a later pass. */
3651 if (reg_renumber
[i
] < 0)
3654 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3655 /* Mark it as no longer having a hard register home. */
3656 reg_renumber
[i
] = -1;
3657 /* We will need to scan everything again. */
3658 something_changed
= 1;
3661 /* Retry global register allocation if possible. */
3664 memset ((char *) pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3665 /* For every insn that needs reloads, set the registers used as spill
3666 regs in pseudo_forbidden_regs for every pseudo live across the
3668 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3670 EXECUTE_IF_SET_IN_REG_SET
3671 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
3673 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3674 &chain
->used_spill_regs
);
3676 EXECUTE_IF_SET_IN_REG_SET
3677 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
3679 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3680 &chain
->used_spill_regs
);
3684 /* Retry allocating the spilled pseudos. For each reg, merge the
3685 various reg sets that indicate which hard regs can't be used,
3686 and call retry_global_alloc.
3687 We change spill_pseudos here to only contain pseudos that did not
3688 get a new hard register. */
3689 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3690 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3692 HARD_REG_SET forbidden
;
3693 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3694 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3695 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3696 retry_global_alloc (i
, forbidden
);
3697 if (reg_renumber
[i
] >= 0)
3698 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3702 /* Fix up the register information in the insn chain.
3703 This involves deleting those of the spilled pseudos which did not get
3704 a new hard register home from the live_{before,after} sets. */
3705 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3707 HARD_REG_SET used_by_pseudos
;
3708 HARD_REG_SET used_by_pseudos2
;
3710 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3711 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3713 /* Mark any unallocated hard regs as available for spills. That
3714 makes inheritance work somewhat better. */
3715 if (chain
->need_reload
)
3717 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3718 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3719 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3721 /* Save the old value for the sanity test below. */
3722 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3724 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3725 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3726 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3727 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3729 /* Make sure we only enlarge the set. */
3730 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3736 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3737 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3739 int regno
= reg_renumber
[i
];
3740 if (reg_old_renumber
[i
] == regno
)
3743 alter_reg (i
, reg_old_renumber
[i
]);
3744 reg_old_renumber
[i
] = regno
;
3748 fprintf (rtl_dump_file
, " Register %d now on stack.\n\n", i
);
3750 fprintf (rtl_dump_file
, " Register %d now in %d.\n\n",
3751 i
, reg_renumber
[i
]);
3755 return something_changed
;
3758 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3759 Also mark any hard registers used to store user variables as
3760 forbidden from being used for spill registers. */
3763 scan_paradoxical_subregs (x
)
3768 enum rtx_code code
= GET_CODE (x
);
3774 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
3775 && REG_USERVAR_P (x
))
3776 SET_HARD_REG_BIT (bad_spill_regs_global
, REGNO (x
));
3785 case CONST_VECTOR
: /* shouldn't happen, but just in case. */
3793 if (GET_CODE (SUBREG_REG (x
)) == REG
3794 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3795 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3796 = GET_MODE_SIZE (GET_MODE (x
));
3803 fmt
= GET_RTX_FORMAT (code
);
3804 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3807 scan_paradoxical_subregs (XEXP (x
, i
));
3808 else if (fmt
[i
] == 'E')
3811 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3812 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3817 /* Reload pseudo-registers into hard regs around each insn as needed.
3818 Additional register load insns are output before the insn that needs it
3819 and perhaps store insns after insns that modify the reloaded pseudo reg.
3821 reg_last_reload_reg and reg_reloaded_contents keep track of
3822 which registers are already available in reload registers.
3823 We update these for the reloads that we perform,
3824 as the insns are scanned. */
3827 reload_as_needed (live_known
)
3830 struct insn_chain
*chain
;
3831 #if defined (AUTO_INC_DEC)
3836 memset ((char *) spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
3837 memset ((char *) spill_reg_store
, 0, sizeof spill_reg_store
);
3838 reg_last_reload_reg
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
3839 reg_has_output_reload
= (char *) xmalloc (max_regno
);
3840 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3842 set_initial_elim_offsets ();
3844 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3847 rtx insn
= chain
->insn
;
3848 rtx old_next
= NEXT_INSN (insn
);
3850 /* If we pass a label, copy the offsets from the label information
3851 into the current offsets of each elimination. */
3852 if (GET_CODE (insn
) == CODE_LABEL
)
3853 set_offsets_for_label (insn
);
3855 else if (INSN_P (insn
))
3857 rtx oldpat
= copy_rtx (PATTERN (insn
));
3859 /* If this is a USE and CLOBBER of a MEM, ensure that any
3860 references to eliminable registers have been removed. */
3862 if ((GET_CODE (PATTERN (insn
)) == USE
3863 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3864 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
3865 XEXP (XEXP (PATTERN (insn
), 0), 0)
3866 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3867 GET_MODE (XEXP (PATTERN (insn
), 0)),
3870 /* If we need to do register elimination processing, do so.
3871 This might delete the insn, in which case we are done. */
3872 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
3874 eliminate_regs_in_insn (insn
, 1);
3875 if (GET_CODE (insn
) == NOTE
)
3877 update_eliminable_offsets ();
3882 /* If need_elim is nonzero but need_reload is zero, one might think
3883 that we could simply set n_reloads to 0. However, find_reloads
3884 could have done some manipulation of the insn (such as swapping
3885 commutative operands), and these manipulations are lost during
3886 the first pass for every insn that needs register elimination.
3887 So the actions of find_reloads must be redone here. */
3889 if (! chain
->need_elim
&& ! chain
->need_reload
3890 && ! chain
->need_operand_change
)
3892 /* First find the pseudo regs that must be reloaded for this insn.
3893 This info is returned in the tables reload_... (see reload.h).
3894 Also modify the body of INSN by substituting RELOAD
3895 rtx's for those pseudo regs. */
3898 memset (reg_has_output_reload
, 0, max_regno
);
3899 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3901 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3907 rtx next
= NEXT_INSN (insn
);
3910 prev
= PREV_INSN (insn
);
3912 /* Now compute which reload regs to reload them into. Perhaps
3913 reusing reload regs from previous insns, or else output
3914 load insns to reload them. Maybe output store insns too.
3915 Record the choices of reload reg in reload_reg_rtx. */
3916 choose_reload_regs (chain
);
3918 /* Merge any reloads that we didn't combine for fear of
3919 increasing the number of spill registers needed but now
3920 discover can be safely merged. */
3921 if (SMALL_REGISTER_CLASSES
)
3922 merge_assigned_reloads (insn
);
3924 /* Generate the insns to reload operands into or out of
3925 their reload regs. */
3926 emit_reload_insns (chain
);
3928 /* Substitute the chosen reload regs from reload_reg_rtx
3929 into the insn's body (or perhaps into the bodies of other
3930 load and store insn that we just made for reloading
3931 and that we moved the structure into). */
3932 subst_reloads (insn
);
3934 /* If this was an ASM, make sure that all the reload insns
3935 we have generated are valid. If not, give an error
3938 if (asm_noperands (PATTERN (insn
)) >= 0)
3939 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3940 if (p
!= insn
&& INSN_P (p
)
3941 && (recog_memoized (p
) < 0
3942 || (extract_insn (p
), ! constrain_operands (1))))
3944 error_for_asm (insn
,
3945 "`asm' operand requires impossible reload");
3950 if (num_eliminable
&& chain
->need_elim
)
3951 update_eliminable_offsets ();
3953 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3954 is no longer validly lying around to save a future reload.
3955 Note that this does not detect pseudos that were reloaded
3956 for this insn in order to be stored in
3957 (obeying register constraints). That is correct; such reload
3958 registers ARE still valid. */
3959 note_stores (oldpat
, forget_old_reloads_1
, NULL
);
3961 /* There may have been CLOBBER insns placed after INSN. So scan
3962 between INSN and NEXT and use them to forget old reloads. */
3963 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
3964 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
3965 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
3968 /* Likewise for regs altered by auto-increment in this insn.
3969 REG_INC notes have been changed by reloading:
3970 find_reloads_address_1 records substitutions for them,
3971 which have been performed by subst_reloads above. */
3972 for (i
= n_reloads
- 1; i
>= 0; i
--)
3974 rtx in_reg
= rld
[i
].in_reg
;
3977 enum rtx_code code
= GET_CODE (in_reg
);
3978 /* PRE_INC / PRE_DEC will have the reload register ending up
3979 with the same value as the stack slot, but that doesn't
3980 hold true for POST_INC / POST_DEC. Either we have to
3981 convert the memory access to a true POST_INC / POST_DEC,
3982 or we can't use the reload register for inheritance. */
3983 if ((code
== POST_INC
|| code
== POST_DEC
)
3984 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
3985 REGNO (rld
[i
].reg_rtx
))
3986 /* Make sure it is the inc/dec pseudo, and not
3987 some other (e.g. output operand) pseudo. */
3988 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
3989 == REGNO (XEXP (in_reg
, 0))))
3992 rtx reload_reg
= rld
[i
].reg_rtx
;
3993 enum machine_mode mode
= GET_MODE (reload_reg
);
3997 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
3999 /* We really want to ignore REG_INC notes here, so
4000 use PATTERN (p) as argument to reg_set_p . */
4001 if (reg_set_p (reload_reg
, PATTERN (p
)))
4003 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4008 n
= validate_replace_rtx (reload_reg
,
4009 gen_rtx (code
, mode
,
4013 /* We must also verify that the constraints
4014 are met after the replacement. */
4017 n
= constrain_operands (1);
4021 /* If the constraints were not met, then
4022 undo the replacement. */
4025 validate_replace_rtx (gen_rtx (code
, mode
,
4037 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4039 /* Mark this as having an output reload so that the
4040 REG_INC processing code below won't invalidate
4041 the reload for inheritance. */
4042 SET_HARD_REG_BIT (reg_is_output_reload
,
4043 REGNO (reload_reg
));
4044 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4047 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4050 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4051 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4052 REGNO (rld
[i
].reg_rtx
))
4053 /* Make sure it is the inc/dec pseudo, and not
4054 some other (e.g. output operand) pseudo. */
4055 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4056 == REGNO (XEXP (in_reg
, 0))))
4058 SET_HARD_REG_BIT (reg_is_output_reload
,
4059 REGNO (rld
[i
].reg_rtx
));
4060 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4064 /* If a pseudo that got a hard register is auto-incremented,
4065 we must purge records of copying it into pseudos without
4067 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4068 if (REG_NOTE_KIND (x
) == REG_INC
)
4070 /* See if this pseudo reg was reloaded in this insn.
4071 If so, its last-reload info is still valid
4072 because it is based on this insn's reload. */
4073 for (i
= 0; i
< n_reloads
; i
++)
4074 if (rld
[i
].out
== XEXP (x
, 0))
4078 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4082 /* A reload reg's contents are unknown after a label. */
4083 if (GET_CODE (insn
) == CODE_LABEL
)
4084 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4086 /* Don't assume a reload reg is still good after a call insn
4087 if it is a call-used reg. */
4088 else if (GET_CODE (insn
) == CALL_INSN
)
4089 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4093 free (reg_last_reload_reg
);
4094 free (reg_has_output_reload
);
4097 /* Discard all record of any value reloaded from X,
4098 or reloaded in X from someplace else;
4099 unless X is an output reload reg of the current insn.
4101 X may be a hard reg (the reload reg)
4102 or it may be a pseudo reg that was reloaded from. */
4105 forget_old_reloads_1 (x
, ignored
, data
)
4107 rtx ignored ATTRIBUTE_UNUSED
;
4108 void *data ATTRIBUTE_UNUSED
;
4113 /* note_stores does give us subregs of hard regs,
4114 subreg_regno_offset will abort if it is not a hard reg. */
4115 while (GET_CODE (x
) == SUBREG
)
4117 /* We ignore the subreg offset when calculating the regno,
4118 because we are using the entire underlying hard register
4123 if (GET_CODE (x
) != REG
)
4128 if (regno
>= FIRST_PSEUDO_REGISTER
)
4134 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4135 /* Storing into a spilled-reg invalidates its contents.
4136 This can happen if a block-local pseudo is allocated to that reg
4137 and it wasn't spilled because this block's total need is 0.
4138 Then some insn might have an optional reload and use this reg. */
4139 for (i
= 0; i
< nr
; i
++)
4140 /* But don't do this if the reg actually serves as an output
4141 reload reg in the current instruction. */
4143 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4145 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4146 spill_reg_store
[regno
+ i
] = 0;
4150 /* Since value of X has changed,
4151 forget any value previously copied from it. */
4154 /* But don't forget a copy if this is the output reload
4155 that establishes the copy's validity. */
4156 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4157 reg_last_reload_reg
[regno
+ nr
] = 0;
4160 /* The following HARD_REG_SETs indicate when each hard register is
4161 used for a reload of various parts of the current insn. */
4163 /* If reg is unavailable for all reloads. */
4164 static HARD_REG_SET reload_reg_unavailable
;
4165 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4166 static HARD_REG_SET reload_reg_used
;
4167 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4168 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4169 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4170 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4171 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4172 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4173 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4174 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4175 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4176 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4177 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4178 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4179 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4180 static HARD_REG_SET reload_reg_used_in_op_addr
;
4181 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4182 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4183 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4184 static HARD_REG_SET reload_reg_used_in_insn
;
4185 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4186 static HARD_REG_SET reload_reg_used_in_other_addr
;
4188 /* If reg is in use as a reload reg for any sort of reload. */
4189 static HARD_REG_SET reload_reg_used_at_all
;
4191 /* If reg is use as an inherited reload. We just mark the first register
4193 static HARD_REG_SET reload_reg_used_for_inherit
;
4195 /* Records which hard regs are used in any way, either as explicit use or
4196 by being allocated to a pseudo during any point of the current insn. */
4197 static HARD_REG_SET reg_used_in_insn
;
4199 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4200 TYPE. MODE is used to indicate how many consecutive regs are
4204 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4207 enum reload_type type
;
4208 enum machine_mode mode
;
4210 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4213 for (i
= regno
; i
< nregs
+ regno
; i
++)
4218 SET_HARD_REG_BIT (reload_reg_used
, i
);
4221 case RELOAD_FOR_INPUT_ADDRESS
:
4222 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4225 case RELOAD_FOR_INPADDR_ADDRESS
:
4226 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4229 case RELOAD_FOR_OUTPUT_ADDRESS
:
4230 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4233 case RELOAD_FOR_OUTADDR_ADDRESS
:
4234 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4237 case RELOAD_FOR_OPERAND_ADDRESS
:
4238 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4241 case RELOAD_FOR_OPADDR_ADDR
:
4242 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4245 case RELOAD_FOR_OTHER_ADDRESS
:
4246 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4249 case RELOAD_FOR_INPUT
:
4250 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4253 case RELOAD_FOR_OUTPUT
:
4254 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4257 case RELOAD_FOR_INSN
:
4258 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4262 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4266 /* Similarly, but show REGNO is no longer in use for a reload. */
4269 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4272 enum reload_type type
;
4273 enum machine_mode mode
;
4275 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4276 unsigned int start_regno
, end_regno
, r
;
4278 /* A complication is that for some reload types, inheritance might
4279 allow multiple reloads of the same types to share a reload register.
4280 We set check_opnum if we have to check only reloads with the same
4281 operand number, and check_any if we have to check all reloads. */
4282 int check_opnum
= 0;
4284 HARD_REG_SET
*used_in_set
;
4289 used_in_set
= &reload_reg_used
;
4292 case RELOAD_FOR_INPUT_ADDRESS
:
4293 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4296 case RELOAD_FOR_INPADDR_ADDRESS
:
4298 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4301 case RELOAD_FOR_OUTPUT_ADDRESS
:
4302 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4305 case RELOAD_FOR_OUTADDR_ADDRESS
:
4307 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4310 case RELOAD_FOR_OPERAND_ADDRESS
:
4311 used_in_set
= &reload_reg_used_in_op_addr
;
4314 case RELOAD_FOR_OPADDR_ADDR
:
4316 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4319 case RELOAD_FOR_OTHER_ADDRESS
:
4320 used_in_set
= &reload_reg_used_in_other_addr
;
4324 case RELOAD_FOR_INPUT
:
4325 used_in_set
= &reload_reg_used_in_input
[opnum
];
4328 case RELOAD_FOR_OUTPUT
:
4329 used_in_set
= &reload_reg_used_in_output
[opnum
];
4332 case RELOAD_FOR_INSN
:
4333 used_in_set
= &reload_reg_used_in_insn
;
4338 /* We resolve conflicts with remaining reloads of the same type by
4339 excluding the intervals of reload registers by them from the
4340 interval of freed reload registers. Since we only keep track of
4341 one set of interval bounds, we might have to exclude somewhat
4342 more than what would be necessary if we used a HARD_REG_SET here.
4343 But this should only happen very infrequently, so there should
4344 be no reason to worry about it. */
4346 start_regno
= regno
;
4347 end_regno
= regno
+ nregs
;
4348 if (check_opnum
|| check_any
)
4350 for (i
= n_reloads
- 1; i
>= 0; i
--)
4352 if (rld
[i
].when_needed
== type
4353 && (check_any
|| rld
[i
].opnum
== opnum
)
4356 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4357 unsigned int conflict_end
4359 + HARD_REGNO_NREGS (conflict_start
, rld
[i
].mode
));
4361 /* If there is an overlap with the first to-be-freed register,
4362 adjust the interval start. */
4363 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4364 start_regno
= conflict_end
;
4365 /* Otherwise, if there is a conflict with one of the other
4366 to-be-freed registers, adjust the interval end. */
4367 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4368 end_regno
= conflict_start
;
4373 for (r
= start_regno
; r
< end_regno
; r
++)
4374 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4377 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4378 specified by OPNUM and TYPE. */
4381 reload_reg_free_p (regno
, opnum
, type
)
4384 enum reload_type type
;
4388 /* In use for a RELOAD_OTHER means it's not available for anything. */
4389 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4390 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4396 /* In use for anything means we can't use it for RELOAD_OTHER. */
4397 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4398 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4399 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4402 for (i
= 0; i
< reload_n_operands
; i
++)
4403 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4404 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4405 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4406 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4407 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4408 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4413 case RELOAD_FOR_INPUT
:
4414 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4415 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4418 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4421 /* If it is used for some other input, can't use it. */
4422 for (i
= 0; i
< reload_n_operands
; i
++)
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4426 /* If it is used in a later operand's address, can't use it. */
4427 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4428 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4429 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4434 case RELOAD_FOR_INPUT_ADDRESS
:
4435 /* Can't use a register if it is used for an input address for this
4436 operand or used as an input in an earlier one. */
4437 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4438 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4441 for (i
= 0; i
< opnum
; i
++)
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4447 case RELOAD_FOR_INPADDR_ADDRESS
:
4448 /* Can't use a register if it is used for an input address
4449 for this operand or used as an input in an earlier
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4454 for (i
= 0; i
< opnum
; i
++)
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4460 case RELOAD_FOR_OUTPUT_ADDRESS
:
4461 /* Can't use a register if it is used for an output address for this
4462 operand or used as an output in this or a later operand. Note
4463 that multiple output operands are emitted in reverse order, so
4464 the conflicting ones are those with lower indices. */
4465 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4468 for (i
= 0; i
<= opnum
; i
++)
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4474 case RELOAD_FOR_OUTADDR_ADDRESS
:
4475 /* Can't use a register if it is used for an output address
4476 for this operand or used as an output in this or a
4477 later operand. Note that multiple output operands are
4478 emitted in reverse order, so the conflicting ones are
4479 those with lower indices. */
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4483 for (i
= 0; i
<= opnum
; i
++)
4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4489 case RELOAD_FOR_OPERAND_ADDRESS
:
4490 for (i
= 0; i
< reload_n_operands
; i
++)
4491 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4494 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4495 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4497 case RELOAD_FOR_OPADDR_ADDR
:
4498 for (i
= 0; i
< reload_n_operands
; i
++)
4499 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4502 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4504 case RELOAD_FOR_OUTPUT
:
4505 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4506 outputs, or an operand address for this or an earlier output.
4507 Note that multiple output operands are emitted in reverse order,
4508 so the conflicting ones are those with higher indices. */
4509 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4512 for (i
= 0; i
< reload_n_operands
; i
++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4516 for (i
= opnum
; i
< reload_n_operands
; i
++)
4517 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4518 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4523 case RELOAD_FOR_INSN
:
4524 for (i
= 0; i
< reload_n_operands
; i
++)
4525 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4529 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4530 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4532 case RELOAD_FOR_OTHER_ADDRESS
:
4533 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4538 /* Return 1 if the value in reload reg REGNO, as used by a reload
4539 needed for the part of the insn specified by OPNUM and TYPE,
4540 is still available in REGNO at the end of the insn.
4542 We can assume that the reload reg was already tested for availability
4543 at the time it is needed, and we should not check this again,
4544 in case the reg has already been marked in use. */
4547 reload_reg_reaches_end_p (regno
, opnum
, type
)
4550 enum reload_type type
;
4557 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4558 its value must reach the end. */
4561 /* If this use is for part of the insn,
4562 its value reaches if no subsequent part uses the same register.
4563 Just like the above function, don't try to do this with lots
4566 case RELOAD_FOR_OTHER_ADDRESS
:
4567 /* Here we check for everything else, since these don't conflict
4568 with anything else and everything comes later. */
4570 for (i
= 0; i
< reload_n_operands
; i
++)
4571 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4573 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4574 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4575 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4576 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4579 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4580 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4581 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4583 case RELOAD_FOR_INPUT_ADDRESS
:
4584 case RELOAD_FOR_INPADDR_ADDRESS
:
4585 /* Similar, except that we check only for this and subsequent inputs
4586 and the address of only subsequent inputs and we do not need
4587 to check for RELOAD_OTHER objects since they are known not to
4590 for (i
= opnum
; i
< reload_n_operands
; i
++)
4591 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4594 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4595 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4596 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4599 for (i
= 0; i
< reload_n_operands
; i
++)
4600 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4602 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4605 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4608 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4609 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4610 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4612 case RELOAD_FOR_INPUT
:
4613 /* Similar to input address, except we start at the next operand for
4614 both input and input address and we do not check for
4615 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4618 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4619 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4621 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4624 /* ... fall through ... */
4626 case RELOAD_FOR_OPERAND_ADDRESS
:
4627 /* Check outputs and their addresses. */
4629 for (i
= 0; i
< reload_n_operands
; i
++)
4630 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4631 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4632 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4635 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4637 case RELOAD_FOR_OPADDR_ADDR
:
4638 for (i
= 0; i
< reload_n_operands
; i
++)
4639 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4640 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4641 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4644 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4645 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4646 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4648 case RELOAD_FOR_INSN
:
4649 /* These conflict with other outputs with RELOAD_OTHER. So
4650 we need only check for output addresses. */
4652 opnum
= reload_n_operands
;
4654 /* ... fall through ... */
4656 case RELOAD_FOR_OUTPUT
:
4657 case RELOAD_FOR_OUTPUT_ADDRESS
:
4658 case RELOAD_FOR_OUTADDR_ADDRESS
:
4659 /* We already know these can't conflict with a later output. So the
4660 only thing to check are later output addresses.
4661 Note that multiple output operands are emitted in reverse order,
4662 so the conflicting ones are those with lower indices. */
4663 for (i
= 0; i
< opnum
; i
++)
4664 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4665 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4674 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4677 This function uses the same algorithm as reload_reg_free_p above. */
4680 reloads_conflict (r1
, r2
)
4683 enum reload_type r1_type
= rld
[r1
].when_needed
;
4684 enum reload_type r2_type
= rld
[r2
].when_needed
;
4685 int r1_opnum
= rld
[r1
].opnum
;
4686 int r2_opnum
= rld
[r2
].opnum
;
4688 /* RELOAD_OTHER conflicts with everything. */
4689 if (r2_type
== RELOAD_OTHER
)
4692 /* Otherwise, check conflicts differently for each type. */
4696 case RELOAD_FOR_INPUT
:
4697 return (r2_type
== RELOAD_FOR_INSN
4698 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4699 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4700 || r2_type
== RELOAD_FOR_INPUT
4701 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4702 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4703 && r2_opnum
> r1_opnum
));
4705 case RELOAD_FOR_INPUT_ADDRESS
:
4706 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4707 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4709 case RELOAD_FOR_INPADDR_ADDRESS
:
4710 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4711 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4713 case RELOAD_FOR_OUTPUT_ADDRESS
:
4714 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4715 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4717 case RELOAD_FOR_OUTADDR_ADDRESS
:
4718 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4719 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
4721 case RELOAD_FOR_OPERAND_ADDRESS
:
4722 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4723 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4725 case RELOAD_FOR_OPADDR_ADDR
:
4726 return (r2_type
== RELOAD_FOR_INPUT
4727 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4729 case RELOAD_FOR_OUTPUT
:
4730 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4731 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4732 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4733 && r2_opnum
>= r1_opnum
));
4735 case RELOAD_FOR_INSN
:
4736 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4737 || r2_type
== RELOAD_FOR_INSN
4738 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4740 case RELOAD_FOR_OTHER_ADDRESS
:
4741 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4751 /* Indexed by reload number, 1 if incoming value
4752 inherited from previous insns. */
4753 char reload_inherited
[MAX_RELOADS
];
4755 /* For an inherited reload, this is the insn the reload was inherited from,
4756 if we know it. Otherwise, this is 0. */
4757 rtx reload_inheritance_insn
[MAX_RELOADS
];
4759 /* If nonzero, this is a place to get the value of the reload,
4760 rather than using reload_in. */
4761 rtx reload_override_in
[MAX_RELOADS
];
4763 /* For each reload, the hard register number of the register used,
4764 or -1 if we did not need a register for this reload. */
4765 int reload_spill_index
[MAX_RELOADS
];
4767 /* Subroutine of free_for_value_p, used to check a single register.
4768 START_REGNO is the starting regno of the full reload register
4769 (possibly comprising multiple hard registers) that we are considering. */
4772 reload_reg_free_for_value_p (start_regno
, regno
, opnum
, type
, value
, out
,
4773 reloadnum
, ignore_address_reloads
)
4774 int start_regno
, regno
;
4776 enum reload_type type
;
4779 int ignore_address_reloads
;
4782 /* Set if we see an input reload that must not share its reload register
4783 with any new earlyclobber, but might otherwise share the reload
4784 register with an output or input-output reload. */
4785 int check_earlyclobber
= 0;
4789 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4792 if (out
== const0_rtx
)
4798 /* We use some pseudo 'time' value to check if the lifetimes of the
4799 new register use would overlap with the one of a previous reload
4800 that is not read-only or uses a different value.
4801 The 'time' used doesn't have to be linear in any shape or form, just
4803 Some reload types use different 'buckets' for each operand.
4804 So there are MAX_RECOG_OPERANDS different time values for each
4806 We compute TIME1 as the time when the register for the prospective
4807 new reload ceases to be live, and TIME2 for each existing
4808 reload as the time when that the reload register of that reload
4810 Where there is little to be gained by exact lifetime calculations,
4811 we just make conservative assumptions, i.e. a longer lifetime;
4812 this is done in the 'default:' cases. */
4815 case RELOAD_FOR_OTHER_ADDRESS
:
4816 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4817 time1
= copy
? 0 : 1;
4820 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
4822 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4823 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4824 respectively, to the time values for these, we get distinct time
4825 values. To get distinct time values for each operand, we have to
4826 multiply opnum by at least three. We round that up to four because
4827 multiply by four is often cheaper. */
4828 case RELOAD_FOR_INPADDR_ADDRESS
:
4829 time1
= opnum
* 4 + 2;
4831 case RELOAD_FOR_INPUT_ADDRESS
:
4832 time1
= opnum
* 4 + 3;
4834 case RELOAD_FOR_INPUT
:
4835 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4836 executes (inclusive). */
4837 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
4839 case RELOAD_FOR_OPADDR_ADDR
:
4841 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4842 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
4844 case RELOAD_FOR_OPERAND_ADDRESS
:
4845 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4847 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
4849 case RELOAD_FOR_OUTADDR_ADDRESS
:
4850 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
4852 case RELOAD_FOR_OUTPUT_ADDRESS
:
4853 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
4856 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
4859 for (i
= 0; i
< n_reloads
; i
++)
4861 rtx reg
= rld
[i
].reg_rtx
;
4862 if (reg
&& GET_CODE (reg
) == REG
4863 && ((unsigned) regno
- true_regnum (reg
)
4864 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned) 1)
4867 rtx other_input
= rld
[i
].in
;
4869 /* If the other reload loads the same input value, that
4870 will not cause a conflict only if it's loading it into
4871 the same register. */
4872 if (true_regnum (reg
) != start_regno
)
4873 other_input
= NULL_RTX
;
4874 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
4875 || rld
[i
].out
|| out
)
4878 switch (rld
[i
].when_needed
)
4880 case RELOAD_FOR_OTHER_ADDRESS
:
4883 case RELOAD_FOR_INPADDR_ADDRESS
:
4884 /* find_reloads makes sure that a
4885 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4886 by at most one - the first -
4887 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4888 address reload is inherited, the address address reload
4889 goes away, so we can ignore this conflict. */
4890 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
4891 && ignore_address_reloads
4892 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4893 Then the address address is still needed to store
4894 back the new address. */
4895 && ! rld
[reloadnum
].out
)
4897 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4898 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4900 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4901 && ignore_address_reloads
4902 /* Unless we are reloading an auto_inc expression. */
4903 && ! rld
[reloadnum
].out
)
4905 time2
= rld
[i
].opnum
* 4 + 2;
4907 case RELOAD_FOR_INPUT_ADDRESS
:
4908 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4909 && ignore_address_reloads
4910 && ! rld
[reloadnum
].out
)
4912 time2
= rld
[i
].opnum
* 4 + 3;
4914 case RELOAD_FOR_INPUT
:
4915 time2
= rld
[i
].opnum
* 4 + 4;
4916 check_earlyclobber
= 1;
4918 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4919 == MAX_RECOG_OPERAND * 4 */
4920 case RELOAD_FOR_OPADDR_ADDR
:
4921 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
4922 && ignore_address_reloads
4923 && ! rld
[reloadnum
].out
)
4925 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
4927 case RELOAD_FOR_OPERAND_ADDRESS
:
4928 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
4929 check_earlyclobber
= 1;
4931 case RELOAD_FOR_INSN
:
4932 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4934 case RELOAD_FOR_OUTPUT
:
4935 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4936 instruction is executed. */
4937 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4939 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4940 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4942 case RELOAD_FOR_OUTADDR_ADDRESS
:
4943 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
4944 && ignore_address_reloads
4945 && ! rld
[reloadnum
].out
)
4947 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
4949 case RELOAD_FOR_OUTPUT_ADDRESS
:
4950 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
4953 /* If there is no conflict in the input part, handle this
4954 like an output reload. */
4955 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
4957 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4958 /* Earlyclobbered outputs must conflict with inputs. */
4959 if (earlyclobber_operand_p (rld
[i
].out
))
4960 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4965 /* RELOAD_OTHER might be live beyond instruction execution,
4966 but this is not obvious when we set time2 = 1. So check
4967 here if there might be a problem with the new reload
4968 clobbering the register used by the RELOAD_OTHER. */
4976 && (! rld
[i
].in
|| rld
[i
].out
4977 || ! rtx_equal_p (other_input
, value
)))
4978 || (out
&& rld
[reloadnum
].out_reg
4979 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
4985 /* Earlyclobbered outputs must conflict with inputs. */
4986 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
4992 /* Return 1 if the value in reload reg REGNO, as used by a reload
4993 needed for the part of the insn specified by OPNUM and TYPE,
4994 may be used to load VALUE into it.
4996 MODE is the mode in which the register is used, this is needed to
4997 determine how many hard regs to test.
4999 Other read-only reloads with the same value do not conflict
5000 unless OUT is nonzero and these other reloads have to live while
5001 output reloads live.
5002 If OUT is CONST0_RTX, this is a special case: it means that the
5003 test should not be for using register REGNO as reload register, but
5004 for copying from register REGNO into the reload register.
5006 RELOADNUM is the number of the reload we want to load this value for;
5007 a reload does not conflict with itself.
5009 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5010 reloads that load an address for the very reload we are considering.
5012 The caller has to make sure that there is no conflict with the return
5016 free_for_value_p (regno
, mode
, opnum
, type
, value
, out
, reloadnum
,
5017 ignore_address_reloads
)
5019 enum machine_mode mode
;
5021 enum reload_type type
;
5024 int ignore_address_reloads
;
5026 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
5028 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5029 value
, out
, reloadnum
,
5030 ignore_address_reloads
))
5035 /* Determine whether the reload reg X overlaps any rtx'es used for
5036 overriding inheritance. Return nonzero if so. */
5039 conflicts_with_override (x
)
5043 for (i
= 0; i
< n_reloads
; i
++)
5044 if (reload_override_in
[i
]
5045 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5050 /* Give an error message saying we failed to find a reload for INSN,
5051 and clear out reload R. */
5053 failed_reload (insn
, r
)
5057 if (asm_noperands (PATTERN (insn
)) < 0)
5058 /* It's the compiler's fault. */
5059 fatal_insn ("could not find a spill register", insn
);
5061 /* It's the user's fault; the operand's mode and constraint
5062 don't match. Disable this reload so we don't crash in final. */
5063 error_for_asm (insn
,
5064 "`asm' operand constraint incompatible with operand size");
5068 rld
[r
].optional
= 1;
5069 rld
[r
].secondary_p
= 1;
5072 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5073 for reload R. If it's valid, get an rtx for it. Return nonzero if
5076 set_reload_reg (i
, r
)
5080 rtx reg
= spill_reg_rtx
[i
];
5082 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5083 spill_reg_rtx
[i
] = reg
5084 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5086 regno
= true_regnum (reg
);
5088 /* Detect when the reload reg can't hold the reload mode.
5089 This used to be one `if', but Sequent compiler can't handle that. */
5090 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5092 enum machine_mode test_mode
= VOIDmode
;
5094 test_mode
= GET_MODE (rld
[r
].in
);
5095 /* If rld[r].in has VOIDmode, it means we will load it
5096 in whatever mode the reload reg has: to wit, rld[r].mode.
5097 We have already tested that for validity. */
5098 /* Aside from that, we need to test that the expressions
5099 to reload from or into have modes which are valid for this
5100 reload register. Otherwise the reload insns would be invalid. */
5101 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5102 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5103 if (! (rld
[r
].out
!= 0
5104 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5106 /* The reg is OK. */
5109 /* Mark as in use for this insn the reload regs we use
5111 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5112 rld
[r
].when_needed
, rld
[r
].mode
);
5114 rld
[r
].reg_rtx
= reg
;
5115 reload_spill_index
[r
] = spill_regs
[i
];
5122 /* Find a spill register to use as a reload register for reload R.
5123 LAST_RELOAD is nonzero if this is the last reload for the insn being
5126 Set rld[R].reg_rtx to the register allocated.
5128 We return 1 if successful, or 0 if we couldn't find a spill reg and
5129 we didn't change anything. */
5132 allocate_reload_reg (chain
, r
, last_reload
)
5133 struct insn_chain
*chain ATTRIBUTE_UNUSED
;
5139 /* If we put this reload ahead, thinking it is a group,
5140 then insist on finding a group. Otherwise we can grab a
5141 reg that some other reload needs.
5142 (That can happen when we have a 68000 DATA_OR_FP_REG
5143 which is a group of data regs or one fp reg.)
5144 We need not be so restrictive if there are no more reloads
5147 ??? Really it would be nicer to have smarter handling
5148 for that kind of reg class, where a problem like this is normal.
5149 Perhaps those classes should be avoided for reloading
5150 by use of more alternatives. */
5152 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5154 /* If we want a single register and haven't yet found one,
5155 take any reg in the right class and not in use.
5156 If we want a consecutive group, here is where we look for it.
5158 We use two passes so we can first look for reload regs to
5159 reuse, which are already in use for other reloads in this insn,
5160 and only then use additional registers.
5161 I think that maximizing reuse is needed to make sure we don't
5162 run out of reload regs. Suppose we have three reloads, and
5163 reloads A and B can share regs. These need two regs.
5164 Suppose A and B are given different regs.
5165 That leaves none for C. */
5166 for (pass
= 0; pass
< 2; pass
++)
5168 /* I is the index in spill_regs.
5169 We advance it round-robin between insns to use all spill regs
5170 equally, so that inherited reloads have a chance
5171 of leapfrogging each other. */
5175 for (count
= 0; count
< n_spills
; count
++)
5177 int class = (int) rld
[r
].class;
5183 regnum
= spill_regs
[i
];
5185 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5188 /* We check reload_reg_used to make sure we
5189 don't clobber the return register. */
5190 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5191 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5192 rld
[r
].when_needed
, rld
[r
].in
,
5194 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5195 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5196 /* Look first for regs to share, then for unshared. But
5197 don't share regs used for inherited reloads; they are
5198 the ones we want to preserve. */
5200 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5202 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5205 int nr
= HARD_REGNO_NREGS (regnum
, rld
[r
].mode
);
5206 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5207 (on 68000) got us two FP regs. If NR is 1,
5208 we would reject both of them. */
5211 /* If we need only one reg, we have already won. */
5214 /* But reject a single reg if we demand a group. */
5219 /* Otherwise check that as many consecutive regs as we need
5220 are available here. */
5223 int regno
= regnum
+ nr
- 1;
5224 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5225 && spill_reg_order
[regno
] >= 0
5226 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5227 rld
[r
].when_needed
)))
5236 /* If we found something on pass 1, omit pass 2. */
5237 if (count
< n_spills
)
5241 /* We should have found a spill register by now. */
5242 if (count
>= n_spills
)
5245 /* I is the index in SPILL_REG_RTX of the reload register we are to
5246 allocate. Get an rtx for it and find its register number. */
5248 return set_reload_reg (i
, r
);
5251 /* Initialize all the tables needed to allocate reload registers.
5252 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5253 is the array we use to restore the reg_rtx field for every reload. */
5256 choose_reload_regs_init (chain
, save_reload_reg_rtx
)
5257 struct insn_chain
*chain
;
5258 rtx
*save_reload_reg_rtx
;
5262 for (i
= 0; i
< n_reloads
; i
++)
5263 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5265 memset (reload_inherited
, 0, MAX_RELOADS
);
5266 memset ((char *) reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5267 memset ((char *) reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5269 CLEAR_HARD_REG_SET (reload_reg_used
);
5270 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5271 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5272 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5273 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5274 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5276 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5279 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5280 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5281 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5282 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5283 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5284 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5287 for (i
= 0; i
< reload_n_operands
; i
++)
5289 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5290 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5291 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5292 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5293 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5294 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5297 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5299 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5301 for (i
= 0; i
< n_reloads
; i
++)
5302 /* If we have already decided to use a certain register,
5303 don't use it in another way. */
5305 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5306 rld
[i
].when_needed
, rld
[i
].mode
);
5309 /* Assign hard reg targets for the pseudo-registers we must reload
5310 into hard regs for this insn.
5311 Also output the instructions to copy them in and out of the hard regs.
5313 For machines with register classes, we are responsible for
5314 finding a reload reg in the proper class. */
5317 choose_reload_regs (chain
)
5318 struct insn_chain
*chain
;
5320 rtx insn
= chain
->insn
;
5322 unsigned int max_group_size
= 1;
5323 enum reg_class group_class
= NO_REGS
;
5324 int pass
, win
, inheritance
;
5326 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5328 /* In order to be certain of getting the registers we need,
5329 we must sort the reloads into order of increasing register class.
5330 Then our grabbing of reload registers will parallel the process
5331 that provided the reload registers.
5333 Also note whether any of the reloads wants a consecutive group of regs.
5334 If so, record the maximum size of the group desired and what
5335 register class contains all the groups needed by this insn. */
5337 for (j
= 0; j
< n_reloads
; j
++)
5339 reload_order
[j
] = j
;
5340 reload_spill_index
[j
] = -1;
5342 if (rld
[j
].nregs
> 1)
5344 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5346 = reg_class_superunion
[(int) rld
[j
].class][(int) group_class
];
5349 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5353 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5355 /* If -O, try first with inheritance, then turning it off.
5356 If not -O, don't do inheritance.
5357 Using inheritance when not optimizing leads to paradoxes
5358 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5359 because one side of the comparison might be inherited. */
5361 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5363 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5365 /* Process the reloads in order of preference just found.
5366 Beyond this point, subregs can be found in reload_reg_rtx.
5368 This used to look for an existing reloaded home for all of the
5369 reloads, and only then perform any new reloads. But that could lose
5370 if the reloads were done out of reg-class order because a later
5371 reload with a looser constraint might have an old home in a register
5372 needed by an earlier reload with a tighter constraint.
5374 To solve this, we make two passes over the reloads, in the order
5375 described above. In the first pass we try to inherit a reload
5376 from a previous insn. If there is a later reload that needs a
5377 class that is a proper subset of the class being processed, we must
5378 also allocate a spill register during the first pass.
5380 Then make a second pass over the reloads to allocate any reloads
5381 that haven't been given registers yet. */
5383 for (j
= 0; j
< n_reloads
; j
++)
5385 int r
= reload_order
[j
];
5386 rtx search_equiv
= NULL_RTX
;
5388 /* Ignore reloads that got marked inoperative. */
5389 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5390 && ! rld
[r
].secondary_p
)
5393 /* If find_reloads chose to use reload_in or reload_out as a reload
5394 register, we don't need to chose one. Otherwise, try even if it
5395 found one since we might save an insn if we find the value lying
5397 Try also when reload_in is a pseudo without a hard reg. */
5398 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5399 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5400 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5401 && GET_CODE (rld
[r
].in
) != MEM
5402 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5405 #if 0 /* No longer needed for correct operation.
5406 It might give better code, or might not; worth an experiment? */
5407 /* If this is an optional reload, we can't inherit from earlier insns
5408 until we are sure that any non-optional reloads have been allocated.
5409 The following code takes advantage of the fact that optional reloads
5410 are at the end of reload_order. */
5411 if (rld
[r
].optional
!= 0)
5412 for (i
= 0; i
< j
; i
++)
5413 if ((rld
[reload_order
[i
]].out
!= 0
5414 || rld
[reload_order
[i
]].in
!= 0
5415 || rld
[reload_order
[i
]].secondary_p
)
5416 && ! rld
[reload_order
[i
]].optional
5417 && rld
[reload_order
[i
]].reg_rtx
== 0)
5418 allocate_reload_reg (chain
, reload_order
[i
], 0);
5421 /* First see if this pseudo is already available as reloaded
5422 for a previous insn. We cannot try to inherit for reloads
5423 that are smaller than the maximum number of registers needed
5424 for groups unless the register we would allocate cannot be used
5427 We could check here to see if this is a secondary reload for
5428 an object that is already in a register of the desired class.
5429 This would avoid the need for the secondary reload register.
5430 But this is complex because we can't easily determine what
5431 objects might want to be loaded via this reload. So let a
5432 register be allocated here. In `emit_reload_insns' we suppress
5433 one of the loads in the case described above. */
5439 enum machine_mode mode
= VOIDmode
;
5443 else if (GET_CODE (rld
[r
].in
) == REG
)
5445 regno
= REGNO (rld
[r
].in
);
5446 mode
= GET_MODE (rld
[r
].in
);
5448 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
5450 regno
= REGNO (rld
[r
].in_reg
);
5451 mode
= GET_MODE (rld
[r
].in_reg
);
5453 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5454 && GET_CODE (SUBREG_REG (rld
[r
].in_reg
)) == REG
)
5456 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
5457 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5458 if (regno
< FIRST_PSEUDO_REGISTER
)
5459 regno
= subreg_regno (rld
[r
].in_reg
);
5460 mode
= GET_MODE (rld
[r
].in_reg
);
5463 else if ((GET_CODE (rld
[r
].in_reg
) == PRE_INC
5464 || GET_CODE (rld
[r
].in_reg
) == PRE_DEC
5465 || GET_CODE (rld
[r
].in_reg
) == POST_INC
5466 || GET_CODE (rld
[r
].in_reg
) == POST_DEC
)
5467 && GET_CODE (XEXP (rld
[r
].in_reg
, 0)) == REG
)
5469 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5470 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5471 rld
[r
].out
= rld
[r
].in
;
5475 /* This won't work, since REGNO can be a pseudo reg number.
5476 Also, it takes much more hair to keep track of all the things
5477 that can invalidate an inherited reload of part of a pseudoreg. */
5478 else if (GET_CODE (rld
[r
].in
) == SUBREG
5479 && GET_CODE (SUBREG_REG (rld
[r
].in
)) == REG
)
5480 regno
= subreg_regno (rld
[r
].in
);
5483 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5485 enum reg_class
class = rld
[r
].class, last_class
;
5486 rtx last_reg
= reg_last_reload_reg
[regno
];
5487 enum machine_mode need_mode
;
5489 i
= REGNO (last_reg
);
5490 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
5491 last_class
= REGNO_REG_CLASS (i
);
5497 = smallest_mode_for_size (GET_MODE_SIZE (mode
) + byte
,
5498 GET_MODE_CLASS (mode
));
5501 #ifdef CANNOT_CHANGE_MODE_CLASS
5502 (!REG_CANNOT_CHANGE_MODE_P (i
, GET_MODE (last_reg
),
5506 (GET_MODE_SIZE (GET_MODE (last_reg
))
5507 >= GET_MODE_SIZE (need_mode
))
5508 #ifdef CANNOT_CHANGE_MODE_CLASS
5511 && reg_reloaded_contents
[i
] == regno
5512 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5513 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5514 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5515 /* Even if we can't use this register as a reload
5516 register, we might use it for reload_override_in,
5517 if copying it to the desired class is cheap
5519 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5520 < MEMORY_MOVE_COST (mode
, class, 1))
5521 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5522 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5526 #ifdef SECONDARY_MEMORY_NEEDED
5527 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5532 && (rld
[r
].nregs
== max_group_size
5533 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5535 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5536 rld
[r
].when_needed
, rld
[r
].in
,
5539 /* If a group is needed, verify that all the subsequent
5540 registers still have their values intact. */
5541 int nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5544 for (k
= 1; k
< nr
; k
++)
5545 if (reg_reloaded_contents
[i
+ k
] != regno
5546 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5554 last_reg
= (GET_MODE (last_reg
) == mode
5555 ? last_reg
: gen_rtx_REG (mode
, i
));
5558 for (k
= 0; k
< nr
; k
++)
5559 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5562 /* We found a register that contains the
5563 value we need. If this register is the
5564 same as an `earlyclobber' operand of the
5565 current insn, just mark it as a place to
5566 reload from since we can't use it as the
5567 reload register itself. */
5569 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5570 if (reg_overlap_mentioned_for_reload_p
5571 (reg_last_reload_reg
[regno
],
5572 reload_earlyclobbers
[i1
]))
5575 if (i1
!= n_earlyclobbers
5576 || ! (free_for_value_p (i
, rld
[r
].mode
,
5578 rld
[r
].when_needed
, rld
[r
].in
,
5580 /* Don't use it if we'd clobber a pseudo reg. */
5581 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5583 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5584 /* Don't clobber the frame pointer. */
5585 || (i
== HARD_FRAME_POINTER_REGNUM
5586 && frame_pointer_needed
5588 /* Don't really use the inherited spill reg
5589 if we need it wider than we've got it. */
5590 || (GET_MODE_SIZE (rld
[r
].mode
)
5591 > GET_MODE_SIZE (mode
))
5594 /* If find_reloads chose reload_out as reload
5595 register, stay with it - that leaves the
5596 inherited register for subsequent reloads. */
5597 || (rld
[r
].out
&& rld
[r
].reg_rtx
5598 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5600 if (! rld
[r
].optional
)
5602 reload_override_in
[r
] = last_reg
;
5603 reload_inheritance_insn
[r
]
5604 = reg_reloaded_insn
[i
];
5610 /* We can use this as a reload reg. */
5611 /* Mark the register as in use for this part of
5613 mark_reload_reg_in_use (i
,
5617 rld
[r
].reg_rtx
= last_reg
;
5618 reload_inherited
[r
] = 1;
5619 reload_inheritance_insn
[r
]
5620 = reg_reloaded_insn
[i
];
5621 reload_spill_index
[r
] = i
;
5622 for (k
= 0; k
< nr
; k
++)
5623 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5631 /* Here's another way to see if the value is already lying around. */
5634 && ! reload_inherited
[r
]
5636 && (CONSTANT_P (rld
[r
].in
)
5637 || GET_CODE (rld
[r
].in
) == PLUS
5638 || GET_CODE (rld
[r
].in
) == REG
5639 || GET_CODE (rld
[r
].in
) == MEM
)
5640 && (rld
[r
].nregs
== max_group_size
5641 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5642 search_equiv
= rld
[r
].in
;
5643 /* If this is an output reload from a simple move insn, look
5644 if an equivalence for the input is available. */
5645 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5647 rtx set
= single_set (insn
);
5650 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5651 && CONSTANT_P (SET_SRC (set
)))
5652 search_equiv
= SET_SRC (set
);
5658 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5659 -1, NULL
, 0, rld
[r
].mode
);
5664 if (GET_CODE (equiv
) == REG
)
5665 regno
= REGNO (equiv
);
5666 else if (GET_CODE (equiv
) == SUBREG
)
5668 /* This must be a SUBREG of a hard register.
5669 Make a new REG since this might be used in an
5670 address and not all machines support SUBREGs
5672 regno
= subreg_regno (equiv
);
5673 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5679 /* If we found a spill reg, reject it unless it is free
5680 and of the desired class. */
5682 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
)
5683 && ! free_for_value_p (regno
, rld
[r
].mode
,
5684 rld
[r
].opnum
, rld
[r
].when_needed
,
5685 rld
[r
].in
, rld
[r
].out
, r
, 1))
5686 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5690 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5693 /* We found a register that contains the value we need.
5694 If this register is the same as an `earlyclobber' operand
5695 of the current insn, just mark it as a place to reload from
5696 since we can't use it as the reload register itself. */
5699 for (i
= 0; i
< n_earlyclobbers
; i
++)
5700 if (reg_overlap_mentioned_for_reload_p (equiv
,
5701 reload_earlyclobbers
[i
]))
5703 if (! rld
[r
].optional
)
5704 reload_override_in
[r
] = equiv
;
5709 /* If the equiv register we have found is explicitly clobbered
5710 in the current insn, it depends on the reload type if we
5711 can use it, use it for reload_override_in, or not at all.
5712 In particular, we then can't use EQUIV for a
5713 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5717 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 0))
5718 switch (rld
[r
].when_needed
)
5720 case RELOAD_FOR_OTHER_ADDRESS
:
5721 case RELOAD_FOR_INPADDR_ADDRESS
:
5722 case RELOAD_FOR_INPUT_ADDRESS
:
5723 case RELOAD_FOR_OPADDR_ADDR
:
5726 case RELOAD_FOR_INPUT
:
5727 case RELOAD_FOR_OPERAND_ADDRESS
:
5728 if (! rld
[r
].optional
)
5729 reload_override_in
[r
] = equiv
;
5735 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
5736 switch (rld
[r
].when_needed
)
5738 case RELOAD_FOR_OTHER_ADDRESS
:
5739 case RELOAD_FOR_INPADDR_ADDRESS
:
5740 case RELOAD_FOR_INPUT_ADDRESS
:
5741 case RELOAD_FOR_OPADDR_ADDR
:
5742 case RELOAD_FOR_OPERAND_ADDRESS
:
5743 case RELOAD_FOR_INPUT
:
5746 if (! rld
[r
].optional
)
5747 reload_override_in
[r
] = equiv
;
5755 /* If we found an equivalent reg, say no code need be generated
5756 to load it, and use it as our reload reg. */
5758 && (regno
!= HARD_FRAME_POINTER_REGNUM
5759 || !frame_pointer_needed
))
5761 int nr
= HARD_REGNO_NREGS (regno
, rld
[r
].mode
);
5763 rld
[r
].reg_rtx
= equiv
;
5764 reload_inherited
[r
] = 1;
5766 /* If reg_reloaded_valid is not set for this register,
5767 there might be a stale spill_reg_store lying around.
5768 We must clear it, since otherwise emit_reload_insns
5769 might delete the store. */
5770 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5771 spill_reg_store
[regno
] = NULL_RTX
;
5772 /* If any of the hard registers in EQUIV are spill
5773 registers, mark them as in use for this insn. */
5774 for (k
= 0; k
< nr
; k
++)
5776 i
= spill_reg_order
[regno
+ k
];
5779 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
5782 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5789 /* If we found a register to use already, or if this is an optional
5790 reload, we are done. */
5791 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
5795 /* No longer needed for correct operation. Might or might
5796 not give better code on the average. Want to experiment? */
5798 /* See if there is a later reload that has a class different from our
5799 class that intersects our class or that requires less register
5800 than our reload. If so, we must allocate a register to this
5801 reload now, since that reload might inherit a previous reload
5802 and take the only available register in our class. Don't do this
5803 for optional reloads since they will force all previous reloads
5804 to be allocated. Also don't do this for reloads that have been
5807 for (i
= j
+ 1; i
< n_reloads
; i
++)
5809 int s
= reload_order
[i
];
5811 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
5812 && ! rld
[s
].secondary_p
)
5816 if ((rld
[s
].class != rld
[r
].class
5817 && reg_classes_intersect_p (rld
[r
].class,
5819 || rld
[s
].nregs
< rld
[r
].nregs
)
5826 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
5830 /* Now allocate reload registers for anything non-optional that
5831 didn't get one yet. */
5832 for (j
= 0; j
< n_reloads
; j
++)
5834 int r
= reload_order
[j
];
5836 /* Ignore reloads that got marked inoperative. */
5837 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
5840 /* Skip reloads that already have a register allocated or are
5842 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
5845 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
5849 /* If that loop got all the way, we have won. */
5856 /* Loop around and try without any inheritance. */
5861 /* First undo everything done by the failed attempt
5862 to allocate with inheritance. */
5863 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5865 /* Some sanity tests to verify that the reloads found in the first
5866 pass are identical to the ones we have now. */
5867 if (chain
->n_reloads
!= n_reloads
)
5870 for (i
= 0; i
< n_reloads
; i
++)
5872 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
5874 if (chain
->rld
[i
].when_needed
!= rld
[i
].when_needed
)
5876 for (j
= 0; j
< n_spills
; j
++)
5877 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
5878 if (! set_reload_reg (j
, i
))
5879 failed_reload (chain
->insn
, i
);
5883 /* If we thought we could inherit a reload, because it seemed that
5884 nothing else wanted the same reload register earlier in the insn,
5885 verify that assumption, now that all reloads have been assigned.
5886 Likewise for reloads where reload_override_in has been set. */
5888 /* If doing expensive optimizations, do one preliminary pass that doesn't
5889 cancel any inheritance, but removes reloads that have been needed only
5890 for reloads that we know can be inherited. */
5891 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
5893 for (j
= 0; j
< n_reloads
; j
++)
5895 int r
= reload_order
[j
];
5897 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
5898 check_reg
= rld
[r
].reg_rtx
;
5899 else if (reload_override_in
[r
]
5900 && (GET_CODE (reload_override_in
[r
]) == REG
5901 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5902 check_reg
= reload_override_in
[r
];
5905 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
5906 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
5907 (reload_inherited
[r
]
5908 ? rld
[r
].out
: const0_rtx
),
5913 reload_inherited
[r
] = 0;
5914 reload_override_in
[r
] = 0;
5916 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5917 reload_override_in, then we do not need its related
5918 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5919 likewise for other reload types.
5920 We handle this by removing a reload when its only replacement
5921 is mentioned in reload_in of the reload we are going to inherit.
5922 A special case are auto_inc expressions; even if the input is
5923 inherited, we still need the address for the output. We can
5924 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5925 If we succeeded removing some reload and we are doing a preliminary
5926 pass just to remove such reloads, make another pass, since the
5927 removal of one reload might allow us to inherit another one. */
5929 && rld
[r
].out
!= rld
[r
].in
5930 && remove_address_replacements (rld
[r
].in
) && pass
)
5935 /* Now that reload_override_in is known valid,
5936 actually override reload_in. */
5937 for (j
= 0; j
< n_reloads
; j
++)
5938 if (reload_override_in
[j
])
5939 rld
[j
].in
= reload_override_in
[j
];
5941 /* If this reload won't be done because it has been canceled or is
5942 optional and not inherited, clear reload_reg_rtx so other
5943 routines (such as subst_reloads) don't get confused. */
5944 for (j
= 0; j
< n_reloads
; j
++)
5945 if (rld
[j
].reg_rtx
!= 0
5946 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
5947 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
5948 && ! rld
[j
].secondary_p
)))
5950 int regno
= true_regnum (rld
[j
].reg_rtx
);
5952 if (spill_reg_order
[regno
] >= 0)
5953 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
5954 rld
[j
].when_needed
, rld
[j
].mode
);
5956 reload_spill_index
[j
] = -1;
5959 /* Record which pseudos and which spill regs have output reloads. */
5960 for (j
= 0; j
< n_reloads
; j
++)
5962 int r
= reload_order
[j
];
5964 i
= reload_spill_index
[r
];
5966 /* I is nonneg if this reload uses a register.
5967 If rld[r].reg_rtx is 0, this is an optional reload
5968 that we opted to ignore. */
5969 if (rld
[r
].out_reg
!= 0 && GET_CODE (rld
[r
].out_reg
) == REG
5970 && rld
[r
].reg_rtx
!= 0)
5972 int nregno
= REGNO (rld
[r
].out_reg
);
5975 if (nregno
< FIRST_PSEUDO_REGISTER
)
5976 nr
= HARD_REGNO_NREGS (nregno
, rld
[r
].mode
);
5979 reg_has_output_reload
[nregno
+ nr
] = 1;
5983 nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5985 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
5988 if (rld
[r
].when_needed
!= RELOAD_OTHER
5989 && rld
[r
].when_needed
!= RELOAD_FOR_OUTPUT
5990 && rld
[r
].when_needed
!= RELOAD_FOR_INSN
)
5996 /* Deallocate the reload register for reload R. This is called from
5997 remove_address_replacements. */
6000 deallocate_reload_reg (r
)
6005 if (! rld
[r
].reg_rtx
)
6007 regno
= true_regnum (rld
[r
].reg_rtx
);
6009 if (spill_reg_order
[regno
] >= 0)
6010 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
6012 reload_spill_index
[r
] = -1;
6015 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6016 reloads of the same item for fear that we might not have enough reload
6017 registers. However, normally they will get the same reload register
6018 and hence actually need not be loaded twice.
6020 Here we check for the most common case of this phenomenon: when we have
6021 a number of reloads for the same object, each of which were allocated
6022 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6023 reload, and is not modified in the insn itself. If we find such,
6024 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6025 This will not increase the number of spill registers needed and will
6026 prevent redundant code. */
6029 merge_assigned_reloads (insn
)
6034 /* Scan all the reloads looking for ones that only load values and
6035 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6036 assigned and not modified by INSN. */
6038 for (i
= 0; i
< n_reloads
; i
++)
6040 int conflicting_input
= 0;
6041 int max_input_address_opnum
= -1;
6042 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6044 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6045 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6046 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6049 /* Look at all other reloads. Ensure that the only use of this
6050 reload_reg_rtx is in a reload that just loads the same value
6051 as we do. Note that any secondary reloads must be of the identical
6052 class since the values, modes, and result registers are the
6053 same, so we need not do anything with any secondary reloads. */
6055 for (j
= 0; j
< n_reloads
; j
++)
6057 if (i
== j
|| rld
[j
].reg_rtx
== 0
6058 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6062 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6063 && rld
[j
].opnum
> max_input_address_opnum
)
6064 max_input_address_opnum
= rld
[j
].opnum
;
6066 /* If the reload regs aren't exactly the same (e.g, different modes)
6067 or if the values are different, we can't merge this reload.
6068 But if it is an input reload, we might still merge
6069 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6071 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6072 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6073 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6075 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6076 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6077 || rld
[i
].opnum
> rld
[j
].opnum
)
6078 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6080 conflicting_input
= 1;
6081 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6082 min_conflicting_input_opnum
= rld
[j
].opnum
;
6086 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6087 we, in fact, found any matching reloads. */
6090 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6092 for (j
= 0; j
< n_reloads
; j
++)
6093 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6094 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6095 && (! conflicting_input
6096 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6097 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6099 rld
[i
].when_needed
= RELOAD_OTHER
;
6101 reload_spill_index
[j
] = -1;
6102 transfer_replacements (i
, j
);
6105 /* If this is now RELOAD_OTHER, look for any reloads that load
6106 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6107 if they were for inputs, RELOAD_OTHER for outputs. Note that
6108 this test is equivalent to looking for reloads for this operand
6110 /* We must take special care when there are two or more reloads to
6111 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6112 same value or a part of it; we must not change its type if there
6113 is a conflicting input. */
6115 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6116 for (j
= 0; j
< n_reloads
; j
++)
6118 && rld
[j
].when_needed
!= RELOAD_OTHER
6119 && rld
[j
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
6120 && (! conflicting_input
6121 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6122 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6123 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6129 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6130 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6131 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6133 /* Check to see if we accidentally converted two reloads
6134 that use the same reload register to the same type.
6135 If so, the resulting code won't work, so abort. */
6137 for (k
= 0; k
< j
; k
++)
6138 if (rld
[k
].in
!= 0 && rld
[k
].reg_rtx
!= 0
6139 && rld
[k
].when_needed
== rld
[j
].when_needed
6140 && rtx_equal_p (rld
[k
].reg_rtx
, rld
[j
].reg_rtx
))
6147 /* These arrays are filled by emit_reload_insns and its subroutines. */
6148 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6149 static rtx other_input_address_reload_insns
= 0;
6150 static rtx other_input_reload_insns
= 0;
6151 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6152 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6153 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6154 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6155 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6156 static rtx operand_reload_insns
= 0;
6157 static rtx other_operand_reload_insns
= 0;
6158 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6160 /* Values to be put in spill_reg_store are put here first. */
6161 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6162 static HARD_REG_SET reg_reloaded_died
;
6164 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6165 has the number J. OLD contains the value to be used as input. */
6168 emit_input_reload_insns (chain
, rl
, old
, j
)
6169 struct insn_chain
*chain
;
6174 rtx insn
= chain
->insn
;
6175 rtx reloadreg
= rl
->reg_rtx
;
6176 rtx oldequiv_reg
= 0;
6179 enum machine_mode mode
;
6182 /* Determine the mode to reload in.
6183 This is very tricky because we have three to choose from.
6184 There is the mode the insn operand wants (rl->inmode).
6185 There is the mode of the reload register RELOADREG.
6186 There is the intrinsic mode of the operand, which we could find
6187 by stripping some SUBREGs.
6188 It turns out that RELOADREG's mode is irrelevant:
6189 we can change that arbitrarily.
6191 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6192 then the reload reg may not support QImode moves, so use SImode.
6193 If foo is in memory due to spilling a pseudo reg, this is safe,
6194 because the QImode value is in the least significant part of a
6195 slot big enough for a SImode. If foo is some other sort of
6196 memory reference, then it is impossible to reload this case,
6197 so previous passes had better make sure this never happens.
6199 Then consider a one-word union which has SImode and one of its
6200 members is a float, being fetched as (SUBREG:SF union:SI).
6201 We must fetch that as SFmode because we could be loading into
6202 a float-only register. In this case OLD's mode is correct.
6204 Consider an immediate integer: it has VOIDmode. Here we need
6205 to get a mode from something else.
6207 In some cases, there is a fourth mode, the operand's
6208 containing mode. If the insn specifies a containing mode for
6209 this operand, it overrides all others.
6211 I am not sure whether the algorithm here is always right,
6212 but it does the right things in those cases. */
6214 mode
= GET_MODE (old
);
6215 if (mode
== VOIDmode
)
6218 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6219 /* If we need a secondary register for this operation, see if
6220 the value is already in a register in that class. Don't
6221 do this if the secondary register will be used as a scratch
6224 if (rl
->secondary_in_reload
>= 0
6225 && rl
->secondary_in_icode
== CODE_FOR_nothing
6228 = find_equiv_reg (old
, insn
,
6229 rld
[rl
->secondary_in_reload
].class,
6233 /* If reloading from memory, see if there is a register
6234 that already holds the same value. If so, reload from there.
6235 We can pass 0 as the reload_reg_p argument because
6236 any other reload has either already been emitted,
6237 in which case find_equiv_reg will see the reload-insn,
6238 or has yet to be emitted, in which case it doesn't matter
6239 because we will use this equiv reg right away. */
6241 if (oldequiv
== 0 && optimize
6242 && (GET_CODE (old
) == MEM
6243 || (GET_CODE (old
) == REG
6244 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6245 && reg_renumber
[REGNO (old
)] < 0)))
6246 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
, -1, NULL
, 0, mode
);
6250 unsigned int regno
= true_regnum (oldequiv
);
6252 /* Don't use OLDEQUIV if any other reload changes it at an
6253 earlier stage of this insn or at this stage. */
6254 if (! free_for_value_p (regno
, rl
->mode
, rl
->opnum
, rl
->when_needed
,
6255 rl
->in
, const0_rtx
, j
, 0))
6258 /* If it is no cheaper to copy from OLDEQUIV into the
6259 reload register than it would be to move from memory,
6260 don't use it. Likewise, if we need a secondary register
6264 && (((enum reg_class
) REGNO_REG_CLASS (regno
) != rl
->class
6265 && (REGISTER_MOVE_COST (mode
, REGNO_REG_CLASS (regno
),
6267 >= MEMORY_MOVE_COST (mode
, rl
->class, 1)))
6268 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6269 || (SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6273 #ifdef SECONDARY_MEMORY_NEEDED
6274 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6282 /* delete_output_reload is only invoked properly if old contains
6283 the original pseudo register. Since this is replaced with a
6284 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6285 find the pseudo in RELOAD_IN_REG. */
6287 && reload_override_in
[j
]
6288 && GET_CODE (rl
->in_reg
) == REG
)
6295 else if (GET_CODE (oldequiv
) == REG
)
6296 oldequiv_reg
= oldequiv
;
6297 else if (GET_CODE (oldequiv
) == SUBREG
)
6298 oldequiv_reg
= SUBREG_REG (oldequiv
);
6300 /* If we are reloading from a register that was recently stored in
6301 with an output-reload, see if we can prove there was
6302 actually no need to store the old value in it. */
6304 if (optimize
&& GET_CODE (oldequiv
) == REG
6305 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6306 && spill_reg_store
[REGNO (oldequiv
)]
6307 && GET_CODE (old
) == REG
6308 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6309 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6311 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6313 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6314 then load RELOADREG from OLDEQUIV. Note that we cannot use
6315 gen_lowpart_common since it can do the wrong thing when
6316 RELOADREG has a multi-word mode. Note that RELOADREG
6317 must always be a REG here. */
6319 if (GET_MODE (reloadreg
) != mode
)
6320 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6321 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6322 oldequiv
= SUBREG_REG (oldequiv
);
6323 if (GET_MODE (oldequiv
) != VOIDmode
6324 && mode
!= GET_MODE (oldequiv
))
6325 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6327 /* Switch to the right place to emit the reload insns. */
6328 switch (rl
->when_needed
)
6331 where
= &other_input_reload_insns
;
6333 case RELOAD_FOR_INPUT
:
6334 where
= &input_reload_insns
[rl
->opnum
];
6336 case RELOAD_FOR_INPUT_ADDRESS
:
6337 where
= &input_address_reload_insns
[rl
->opnum
];
6339 case RELOAD_FOR_INPADDR_ADDRESS
:
6340 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6342 case RELOAD_FOR_OUTPUT_ADDRESS
:
6343 where
= &output_address_reload_insns
[rl
->opnum
];
6345 case RELOAD_FOR_OUTADDR_ADDRESS
:
6346 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6348 case RELOAD_FOR_OPERAND_ADDRESS
:
6349 where
= &operand_reload_insns
;
6351 case RELOAD_FOR_OPADDR_ADDR
:
6352 where
= &other_operand_reload_insns
;
6354 case RELOAD_FOR_OTHER_ADDRESS
:
6355 where
= &other_input_address_reload_insns
;
6361 push_to_sequence (*where
);
6363 /* Auto-increment addresses must be reloaded in a special way. */
6364 if (rl
->out
&& ! rl
->out_reg
)
6366 /* We are not going to bother supporting the case where a
6367 incremented register can't be copied directly from
6368 OLDEQUIV since this seems highly unlikely. */
6369 if (rl
->secondary_in_reload
>= 0)
6372 if (reload_inherited
[j
])
6373 oldequiv
= reloadreg
;
6375 old
= XEXP (rl
->in_reg
, 0);
6377 if (optimize
&& GET_CODE (oldequiv
) == REG
6378 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6379 && spill_reg_store
[REGNO (oldequiv
)]
6380 && GET_CODE (old
) == REG
6381 && (dead_or_set_p (insn
,
6382 spill_reg_stored_to
[REGNO (oldequiv
)])
6383 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6385 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6387 /* Prevent normal processing of this reload. */
6389 /* Output a special code sequence for this case. */
6390 new_spill_reg_store
[REGNO (reloadreg
)]
6391 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6395 /* If we are reloading a pseudo-register that was set by the previous
6396 insn, see if we can get rid of that pseudo-register entirely
6397 by redirecting the previous insn into our reload register. */
6399 else if (optimize
&& GET_CODE (old
) == REG
6400 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6401 && dead_or_set_p (insn
, old
)
6402 /* This is unsafe if some other reload
6403 uses the same reg first. */
6404 && ! conflicts_with_override (reloadreg
)
6405 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6406 rl
->when_needed
, old
, rl
->out
, j
, 0))
6408 rtx temp
= PREV_INSN (insn
);
6409 while (temp
&& GET_CODE (temp
) == NOTE
)
6410 temp
= PREV_INSN (temp
);
6412 && GET_CODE (temp
) == INSN
6413 && GET_CODE (PATTERN (temp
)) == SET
6414 && SET_DEST (PATTERN (temp
)) == old
6415 /* Make sure we can access insn_operand_constraint. */
6416 && asm_noperands (PATTERN (temp
)) < 0
6417 /* This is unsafe if operand occurs more than once in current
6418 insn. Perhaps some occurrences aren't reloaded. */
6419 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
6421 rtx old
= SET_DEST (PATTERN (temp
));
6422 /* Store into the reload register instead of the pseudo. */
6423 SET_DEST (PATTERN (temp
)) = reloadreg
;
6425 /* Verify that resulting insn is valid. */
6426 extract_insn (temp
);
6427 if (constrain_operands (1))
6429 /* If the previous insn is an output reload, the source is
6430 a reload register, and its spill_reg_store entry will
6431 contain the previous destination. This is now
6433 if (GET_CODE (SET_SRC (PATTERN (temp
))) == REG
6434 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6436 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6437 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6440 /* If these are the only uses of the pseudo reg,
6441 pretend for GDB it lives in the reload reg we used. */
6442 if (REG_N_DEATHS (REGNO (old
)) == 1
6443 && REG_N_SETS (REGNO (old
)) == 1)
6445 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6446 alter_reg (REGNO (old
), -1);
6452 SET_DEST (PATTERN (temp
)) = old
;
6457 /* We can't do that, so output an insn to load RELOADREG. */
6459 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6460 /* If we have a secondary reload, pick up the secondary register
6461 and icode, if any. If OLDEQUIV and OLD are different or
6462 if this is an in-out reload, recompute whether or not we
6463 still need a secondary register and what the icode should
6464 be. If we still need a secondary register and the class or
6465 icode is different, go back to reloading from OLD if using
6466 OLDEQUIV means that we got the wrong type of register. We
6467 cannot have different class or icode due to an in-out reload
6468 because we don't make such reloads when both the input and
6469 output need secondary reload registers. */
6471 if (! special
&& rl
->secondary_in_reload
>= 0)
6473 rtx second_reload_reg
= 0;
6474 int secondary_reload
= rl
->secondary_in_reload
;
6475 rtx real_oldequiv
= oldequiv
;
6478 enum insn_code icode
;
6480 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6481 and similarly for OLD.
6482 See comments in get_secondary_reload in reload.c. */
6483 /* If it is a pseudo that cannot be replaced with its
6484 equivalent MEM, we must fall back to reload_in, which
6485 will have all the necessary substitutions registered.
6486 Likewise for a pseudo that can't be replaced with its
6487 equivalent constant.
6489 Take extra care for subregs of such pseudos. Note that
6490 we cannot use reg_equiv_mem in this case because it is
6491 not in the right mode. */
6494 if (GET_CODE (tmp
) == SUBREG
)
6495 tmp
= SUBREG_REG (tmp
);
6496 if (GET_CODE (tmp
) == REG
6497 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6498 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6499 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6501 if (! reg_equiv_mem
[REGNO (tmp
)]
6502 || num_not_at_initial_offset
6503 || GET_CODE (oldequiv
) == SUBREG
)
6504 real_oldequiv
= rl
->in
;
6506 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6510 if (GET_CODE (tmp
) == SUBREG
)
6511 tmp
= SUBREG_REG (tmp
);
6512 if (GET_CODE (tmp
) == REG
6513 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6514 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6515 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6517 if (! reg_equiv_mem
[REGNO (tmp
)]
6518 || num_not_at_initial_offset
6519 || GET_CODE (old
) == SUBREG
)
6522 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6525 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6526 icode
= rl
->secondary_in_icode
;
6528 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6529 || (rl
->in
!= 0 && rl
->out
!= 0))
6531 enum reg_class new_class
6532 = SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6533 mode
, real_oldequiv
);
6535 if (new_class
== NO_REGS
)
6536 second_reload_reg
= 0;
6539 enum insn_code new_icode
;
6540 enum machine_mode new_mode
;
6542 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6543 REGNO (second_reload_reg
)))
6544 oldequiv
= old
, real_oldequiv
= real_old
;
6547 new_icode
= reload_in_optab
[(int) mode
];
6548 if (new_icode
!= CODE_FOR_nothing
6549 && ((insn_data
[(int) new_icode
].operand
[0].predicate
6550 && ! ((*insn_data
[(int) new_icode
].operand
[0].predicate
)
6552 || (insn_data
[(int) new_icode
].operand
[1].predicate
6553 && ! ((*insn_data
[(int) new_icode
].operand
[1].predicate
)
6554 (real_oldequiv
, mode
)))))
6555 new_icode
= CODE_FOR_nothing
;
6557 if (new_icode
== CODE_FOR_nothing
)
6560 new_mode
= insn_data
[(int) new_icode
].operand
[2].mode
;
6562 if (GET_MODE (second_reload_reg
) != new_mode
)
6564 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6566 oldequiv
= old
, real_oldequiv
= real_old
;
6569 = gen_rtx_REG (new_mode
,
6570 REGNO (second_reload_reg
));
6576 /* If we still need a secondary reload register, check
6577 to see if it is being used as a scratch or intermediate
6578 register and generate code appropriately. If we need
6579 a scratch register, use REAL_OLDEQUIV since the form of
6580 the insn may depend on the actual address if it is
6583 if (second_reload_reg
)
6585 if (icode
!= CODE_FOR_nothing
)
6587 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6588 second_reload_reg
));
6593 /* See if we need a scratch register to load the
6594 intermediate register (a tertiary reload). */
6595 enum insn_code tertiary_icode
6596 = rld
[secondary_reload
].secondary_in_icode
;
6598 if (tertiary_icode
!= CODE_FOR_nothing
)
6600 rtx third_reload_reg
6601 = rld
[rld
[secondary_reload
].secondary_in_reload
].reg_rtx
;
6603 emit_insn ((GEN_FCN (tertiary_icode
)
6604 (second_reload_reg
, real_oldequiv
,
6605 third_reload_reg
)));
6608 gen_reload (second_reload_reg
, real_oldequiv
,
6612 oldequiv
= second_reload_reg
;
6618 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6620 rtx real_oldequiv
= oldequiv
;
6622 if ((GET_CODE (oldequiv
) == REG
6623 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6624 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6625 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6626 || (GET_CODE (oldequiv
) == SUBREG
6627 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
6628 && (REGNO (SUBREG_REG (oldequiv
))
6629 >= FIRST_PSEUDO_REGISTER
)
6630 && ((reg_equiv_memory_loc
6631 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6632 || (reg_equiv_constant
6633 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6634 || (CONSTANT_P (oldequiv
)
6635 && (PREFERRED_RELOAD_CLASS (oldequiv
,
6636 REGNO_REG_CLASS (REGNO (reloadreg
)))
6638 real_oldequiv
= rl
->in
;
6639 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6643 if (flag_non_call_exceptions
)
6644 copy_eh_notes (insn
, get_insns ());
6646 /* End this sequence. */
6647 *where
= get_insns ();
6650 /* Update reload_override_in so that delete_address_reloads_1
6651 can see the actual register usage. */
6653 reload_override_in
[j
] = oldequiv
;
6656 /* Generate insns to for the output reload RL, which is for the insn described
6657 by CHAIN and has the number J. */
6659 emit_output_reload_insns (chain
, rl
, j
)
6660 struct insn_chain
*chain
;
6664 rtx reloadreg
= rl
->reg_rtx
;
6665 rtx insn
= chain
->insn
;
6668 enum machine_mode mode
= GET_MODE (old
);
6671 if (rl
->when_needed
== RELOAD_OTHER
)
6674 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6676 /* Determine the mode to reload in.
6677 See comments above (for input reloading). */
6679 if (mode
== VOIDmode
)
6681 /* VOIDmode should never happen for an output. */
6682 if (asm_noperands (PATTERN (insn
)) < 0)
6683 /* It's the compiler's fault. */
6684 fatal_insn ("VOIDmode on an output", insn
);
6685 error_for_asm (insn
, "output operand is constant in `asm'");
6686 /* Prevent crash--use something we know is valid. */
6688 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6691 if (GET_MODE (reloadreg
) != mode
)
6692 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6694 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6696 /* If we need two reload regs, set RELOADREG to the intermediate
6697 one, since it will be stored into OLD. We might need a secondary
6698 register only for an input reload, so check again here. */
6700 if (rl
->secondary_out_reload
>= 0)
6704 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
6705 && reg_equiv_mem
[REGNO (old
)] != 0)
6706 real_old
= reg_equiv_mem
[REGNO (old
)];
6708 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl
->class,
6712 rtx second_reloadreg
= reloadreg
;
6713 reloadreg
= rld
[rl
->secondary_out_reload
].reg_rtx
;
6715 /* See if RELOADREG is to be used as a scratch register
6716 or as an intermediate register. */
6717 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
6719 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
6720 (real_old
, second_reloadreg
, reloadreg
)));
6725 /* See if we need both a scratch and intermediate reload
6728 int secondary_reload
= rl
->secondary_out_reload
;
6729 enum insn_code tertiary_icode
6730 = rld
[secondary_reload
].secondary_out_icode
;
6732 if (GET_MODE (reloadreg
) != mode
)
6733 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6735 if (tertiary_icode
!= CODE_FOR_nothing
)
6738 = rld
[rld
[secondary_reload
].secondary_out_reload
].reg_rtx
;
6741 /* Copy primary reload reg to secondary reload reg.
6742 (Note that these have been swapped above, then
6743 secondary reload reg to OLD using our insn.) */
6745 /* If REAL_OLD is a paradoxical SUBREG, remove it
6746 and try to put the opposite SUBREG on
6748 if (GET_CODE (real_old
) == SUBREG
6749 && (GET_MODE_SIZE (GET_MODE (real_old
))
6750 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
6751 && 0 != (tem
= gen_lowpart_common
6752 (GET_MODE (SUBREG_REG (real_old
)),
6754 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
6756 gen_reload (reloadreg
, second_reloadreg
,
6757 rl
->opnum
, rl
->when_needed
);
6758 emit_insn ((GEN_FCN (tertiary_icode
)
6759 (real_old
, reloadreg
, third_reloadreg
)));
6764 /* Copy between the reload regs here and then to
6767 gen_reload (reloadreg
, second_reloadreg
,
6768 rl
->opnum
, rl
->when_needed
);
6774 /* Output the last reload insn. */
6779 /* Don't output the last reload if OLD is not the dest of
6780 INSN and is in the src and is clobbered by INSN. */
6781 if (! flag_expensive_optimizations
6782 || GET_CODE (old
) != REG
6783 || !(set
= single_set (insn
))
6784 || rtx_equal_p (old
, SET_DEST (set
))
6785 || !reg_mentioned_p (old
, SET_SRC (set
))
6786 || !regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0))
6787 gen_reload (old
, reloadreg
, rl
->opnum
,
6791 /* Look at all insns we emitted, just to be safe. */
6792 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6795 rtx pat
= PATTERN (p
);
6797 /* If this output reload doesn't come from a spill reg,
6798 clear any memory of reloaded copies of the pseudo reg.
6799 If this output reload comes from a spill reg,
6800 reg_has_output_reload will make this do nothing. */
6801 note_stores (pat
, forget_old_reloads_1
, NULL
);
6803 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
6805 rtx set
= single_set (insn
);
6806 if (reload_spill_index
[j
] < 0
6808 && SET_SRC (set
) == rl
->reg_rtx
)
6810 int src
= REGNO (SET_SRC (set
));
6812 reload_spill_index
[j
] = src
;
6813 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
6814 if (find_regno_note (insn
, REG_DEAD
, src
))
6815 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
6817 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6819 int s
= rl
->secondary_out_reload
;
6820 set
= single_set (p
);
6821 /* If this reload copies only to the secondary reload
6822 register, the secondary reload does the actual
6824 if (s
>= 0 && set
== NULL_RTX
)
6825 /* We can't tell what function the secondary reload
6826 has and where the actual store to the pseudo is
6827 made; leave new_spill_reg_store alone. */
6830 && SET_SRC (set
) == rl
->reg_rtx
6831 && SET_DEST (set
) == rld
[s
].reg_rtx
)
6833 /* Usually the next instruction will be the
6834 secondary reload insn; if we can confirm
6835 that it is, setting new_spill_reg_store to
6836 that insn will allow an extra optimization. */
6837 rtx s_reg
= rld
[s
].reg_rtx
;
6838 rtx next
= NEXT_INSN (p
);
6839 rld
[s
].out
= rl
->out
;
6840 rld
[s
].out_reg
= rl
->out_reg
;
6841 set
= single_set (next
);
6842 if (set
&& SET_SRC (set
) == s_reg
6843 && ! new_spill_reg_store
[REGNO (s_reg
)])
6845 SET_HARD_REG_BIT (reg_is_output_reload
,
6847 new_spill_reg_store
[REGNO (s_reg
)] = next
;
6851 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
6856 if (rl
->when_needed
== RELOAD_OTHER
)
6858 emit_insn (other_output_reload_insns
[rl
->opnum
]);
6859 other_output_reload_insns
[rl
->opnum
] = get_insns ();
6862 output_reload_insns
[rl
->opnum
] = get_insns ();
6864 if (flag_non_call_exceptions
)
6865 copy_eh_notes (insn
, get_insns ());
6870 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6871 and has the number J. */
6873 do_input_reload (chain
, rl
, j
)
6874 struct insn_chain
*chain
;
6878 rtx insn
= chain
->insn
;
6879 rtx old
= (rl
->in
&& GET_CODE (rl
->in
) == MEM
6880 ? rl
->in_reg
: rl
->in
);
6883 /* AUTO_INC reloads need to be handled even if inherited. We got an
6884 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6885 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
6886 && ! rtx_equal_p (rl
->reg_rtx
, old
)
6887 && rl
->reg_rtx
!= 0)
6888 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
6890 /* When inheriting a wider reload, we have a MEM in rl->in,
6891 e.g. inheriting a SImode output reload for
6892 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6893 if (optimize
&& reload_inherited
[j
] && rl
->in
6894 && GET_CODE (rl
->in
) == MEM
6895 && GET_CODE (rl
->in_reg
) == MEM
6896 && reload_spill_index
[j
] >= 0
6897 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6898 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6900 /* If we are reloading a register that was recently stored in with an
6901 output-reload, see if we can prove there was
6902 actually no need to store the old value in it. */
6905 && (reload_inherited
[j
] || reload_override_in
[j
])
6907 && GET_CODE (rl
->reg_rtx
) == REG
6908 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
6910 /* There doesn't seem to be any reason to restrict this to pseudos
6911 and doing so loses in the case where we are copying from a
6912 register of the wrong class. */
6913 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6914 >= FIRST_PSEUDO_REGISTER
)
6916 /* The insn might have already some references to stackslots
6917 replaced by MEMs, while reload_out_reg still names the
6919 && (dead_or_set_p (insn
,
6920 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6921 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
6923 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
6926 /* Do output reloading for reload RL, which is for the insn described by
6927 CHAIN and has the number J.
6928 ??? At some point we need to support handling output reloads of
6929 JUMP_INSNs or insns that set cc0. */
6931 do_output_reload (chain
, rl
, j
)
6932 struct insn_chain
*chain
;
6937 rtx insn
= chain
->insn
;
6938 /* If this is an output reload that stores something that is
6939 not loaded in this same reload, see if we can eliminate a previous
6941 rtx pseudo
= rl
->out_reg
;
6945 && GET_CODE (pseudo
) == REG
6946 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
6947 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
6948 && reg_last_reload_reg
[REGNO (pseudo
)])
6950 int pseudo_no
= REGNO (pseudo
);
6951 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
6953 /* We don't need to test full validity of last_regno for
6954 inherit here; we only want to know if the store actually
6955 matches the pseudo. */
6956 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
6957 && reg_reloaded_contents
[last_regno
] == pseudo_no
6958 && spill_reg_store
[last_regno
]
6959 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
6960 delete_output_reload (insn
, j
, last_regno
);
6965 || rl
->reg_rtx
== old
6966 || rl
->reg_rtx
== 0)
6969 /* An output operand that dies right away does need a reload,
6970 but need not be copied from it. Show the new location in the
6972 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
6973 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
6975 XEXP (note
, 0) = rl
->reg_rtx
;
6978 /* Likewise for a SUBREG of an operand that dies. */
6979 else if (GET_CODE (old
) == SUBREG
6980 && GET_CODE (SUBREG_REG (old
)) == REG
6981 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
6984 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
6988 else if (GET_CODE (old
) == SCRATCH
)
6989 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6990 but we don't want to make an output reload. */
6993 /* If is a JUMP_INSN, we can't support output reloads yet. */
6994 if (GET_CODE (insn
) == JUMP_INSN
)
6997 emit_output_reload_insns (chain
, rld
+ j
, j
);
7000 /* Output insns to reload values in and out of the chosen reload regs. */
7003 emit_reload_insns (chain
)
7004 struct insn_chain
*chain
;
7006 rtx insn
= chain
->insn
;
7010 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7012 for (j
= 0; j
< reload_n_operands
; j
++)
7013 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7014 = inpaddr_address_reload_insns
[j
]
7015 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7016 = outaddr_address_reload_insns
[j
]
7017 = other_output_reload_insns
[j
] = 0;
7018 other_input_address_reload_insns
= 0;
7019 other_input_reload_insns
= 0;
7020 operand_reload_insns
= 0;
7021 other_operand_reload_insns
= 0;
7023 /* Dump reloads into the dump file. */
7026 fprintf (rtl_dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
7027 debug_reload_to_stream (rtl_dump_file
);
7030 /* Now output the instructions to copy the data into and out of the
7031 reload registers. Do these in the order that the reloads were reported,
7032 since reloads of base and index registers precede reloads of operands
7033 and the operands may need the base and index registers reloaded. */
7035 for (j
= 0; j
< n_reloads
; j
++)
7038 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
7039 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
7041 do_input_reload (chain
, rld
+ j
, j
);
7042 do_output_reload (chain
, rld
+ j
, j
);
7045 /* Now write all the insns we made for reloads in the order expected by
7046 the allocation functions. Prior to the insn being reloaded, we write
7047 the following reloads:
7049 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7051 RELOAD_OTHER reloads.
7053 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7054 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7055 RELOAD_FOR_INPUT reload for the operand.
7057 RELOAD_FOR_OPADDR_ADDRS reloads.
7059 RELOAD_FOR_OPERAND_ADDRESS reloads.
7061 After the insn being reloaded, we write the following:
7063 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7064 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7065 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7066 reloads for the operand. The RELOAD_OTHER output reloads are
7067 output in descending order by reload number. */
7069 emit_insn_before (other_input_address_reload_insns
, insn
);
7070 emit_insn_before (other_input_reload_insns
, insn
);
7072 for (j
= 0; j
< reload_n_operands
; j
++)
7074 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
7075 emit_insn_before (input_address_reload_insns
[j
], insn
);
7076 emit_insn_before (input_reload_insns
[j
], insn
);
7079 emit_insn_before (other_operand_reload_insns
, insn
);
7080 emit_insn_before (operand_reload_insns
, insn
);
7082 for (j
= 0; j
< reload_n_operands
; j
++)
7084 rtx x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
7085 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
7086 x
= emit_insn_after (output_reload_insns
[j
], x
);
7087 emit_insn_after (other_output_reload_insns
[j
], x
);
7090 /* For all the spill regs newly reloaded in this instruction,
7091 record what they were reloaded from, so subsequent instructions
7092 can inherit the reloads.
7094 Update spill_reg_store for the reloads of this insn.
7095 Copy the elements that were updated in the loop above. */
7097 for (j
= 0; j
< n_reloads
; j
++)
7099 int r
= reload_order
[j
];
7100 int i
= reload_spill_index
[r
];
7102 /* If this is a non-inherited input reload from a pseudo, we must
7103 clear any memory of a previous store to the same pseudo. Only do
7104 something if there will not be an output reload for the pseudo
7106 if (rld
[r
].in_reg
!= 0
7107 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7109 rtx reg
= rld
[r
].in_reg
;
7111 if (GET_CODE (reg
) == SUBREG
)
7112 reg
= SUBREG_REG (reg
);
7114 if (GET_CODE (reg
) == REG
7115 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7116 && ! reg_has_output_reload
[REGNO (reg
)])
7118 int nregno
= REGNO (reg
);
7120 if (reg_last_reload_reg
[nregno
])
7122 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7124 if (reg_reloaded_contents
[last_regno
] == nregno
)
7125 spill_reg_store
[last_regno
] = 0;
7130 /* I is nonneg if this reload used a register.
7131 If rld[r].reg_rtx is 0, this is an optional reload
7132 that we opted to ignore. */
7134 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7136 int nr
= HARD_REGNO_NREGS (i
, GET_MODE (rld
[r
].reg_rtx
));
7138 int part_reaches_end
= 0;
7139 int all_reaches_end
= 1;
7141 /* For a multi register reload, we need to check if all or part
7142 of the value lives to the end. */
7143 for (k
= 0; k
< nr
; k
++)
7145 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7146 rld
[r
].when_needed
))
7147 part_reaches_end
= 1;
7149 all_reaches_end
= 0;
7152 /* Ignore reloads that don't reach the end of the insn in
7154 if (all_reaches_end
)
7156 /* First, clear out memory of what used to be in this spill reg.
7157 If consecutive registers are used, clear them all. */
7159 for (k
= 0; k
< nr
; k
++)
7160 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7162 /* Maybe the spill reg contains a copy of reload_out. */
7164 && (GET_CODE (rld
[r
].out
) == REG
7168 || GET_CODE (rld
[r
].out_reg
) == REG
))
7170 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7174 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7175 int nregno
= REGNO (out
);
7176 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7177 : HARD_REGNO_NREGS (nregno
,
7178 GET_MODE (rld
[r
].reg_rtx
)));
7180 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7181 spill_reg_stored_to
[i
] = out
;
7182 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7184 /* If NREGNO is a hard register, it may occupy more than
7185 one register. If it does, say what is in the
7186 rest of the registers assuming that both registers
7187 agree on how many words the object takes. If not,
7188 invalidate the subsequent registers. */
7190 if (nregno
< FIRST_PSEUDO_REGISTER
)
7191 for (k
= 1; k
< nnr
; k
++)
7192 reg_last_reload_reg
[nregno
+ k
]
7194 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7197 /* Now do the inverse operation. */
7198 for (k
= 0; k
< nr
; k
++)
7200 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7201 reg_reloaded_contents
[i
+ k
]
7202 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7205 reg_reloaded_insn
[i
+ k
] = insn
;
7206 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7210 /* Maybe the spill reg contains a copy of reload_in. Only do
7211 something if there will not be an output reload for
7212 the register being reloaded. */
7213 else if (rld
[r
].out_reg
== 0
7215 && ((GET_CODE (rld
[r
].in
) == REG
7216 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
7217 && ! reg_has_output_reload
[REGNO (rld
[r
].in
)])
7218 || (GET_CODE (rld
[r
].in_reg
) == REG
7219 && ! reg_has_output_reload
[REGNO (rld
[r
].in_reg
)]))
7220 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
7225 if (GET_CODE (rld
[r
].in
) == REG
7226 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7227 nregno
= REGNO (rld
[r
].in
);
7228 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
7229 nregno
= REGNO (rld
[r
].in_reg
);
7231 nregno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
7233 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7234 : HARD_REGNO_NREGS (nregno
,
7235 GET_MODE (rld
[r
].reg_rtx
)));
7237 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7239 if (nregno
< FIRST_PSEUDO_REGISTER
)
7240 for (k
= 1; k
< nnr
; k
++)
7241 reg_last_reload_reg
[nregno
+ k
]
7243 ? regno_reg_rtx
[REGNO (rld
[r
].reg_rtx
) + k
]
7246 /* Unless we inherited this reload, show we haven't
7247 recently done a store.
7248 Previous stores of inherited auto_inc expressions
7249 also have to be discarded. */
7250 if (! reload_inherited
[r
]
7251 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7252 spill_reg_store
[i
] = 0;
7254 for (k
= 0; k
< nr
; k
++)
7256 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7257 reg_reloaded_contents
[i
+ k
]
7258 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7261 reg_reloaded_insn
[i
+ k
] = insn
;
7262 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7267 /* However, if part of the reload reaches the end, then we must
7268 invalidate the old info for the part that survives to the end. */
7269 else if (part_reaches_end
)
7271 for (k
= 0; k
< nr
; k
++)
7272 if (reload_reg_reaches_end_p (i
+ k
,
7274 rld
[r
].when_needed
))
7275 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7279 /* The following if-statement was #if 0'd in 1.34 (or before...).
7280 It's reenabled in 1.35 because supposedly nothing else
7281 deals with this problem. */
7283 /* If a register gets output-reloaded from a non-spill register,
7284 that invalidates any previous reloaded copy of it.
7285 But forget_old_reloads_1 won't get to see it, because
7286 it thinks only about the original insn. So invalidate it here. */
7287 if (i
< 0 && rld
[r
].out
!= 0
7288 && (GET_CODE (rld
[r
].out
) == REG
7289 || (GET_CODE (rld
[r
].out
) == MEM
7290 && GET_CODE (rld
[r
].out_reg
) == REG
)))
7292 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7293 ? rld
[r
].out
: rld
[r
].out_reg
);
7294 int nregno
= REGNO (out
);
7295 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7297 rtx src_reg
, store_insn
= NULL_RTX
;
7299 reg_last_reload_reg
[nregno
] = 0;
7301 /* If we can find a hard register that is stored, record
7302 the storing insn so that we may delete this insn with
7303 delete_output_reload. */
7304 src_reg
= rld
[r
].reg_rtx
;
7306 /* If this is an optional reload, try to find the source reg
7307 from an input reload. */
7310 rtx set
= single_set (insn
);
7311 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7315 src_reg
= SET_SRC (set
);
7317 for (k
= 0; k
< n_reloads
; k
++)
7319 if (rld
[k
].in
== src_reg
)
7321 src_reg
= rld
[k
].reg_rtx
;
7328 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7329 if (src_reg
&& GET_CODE (src_reg
) == REG
7330 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7332 int src_regno
= REGNO (src_reg
);
7333 int nr
= HARD_REGNO_NREGS (src_regno
, rld
[r
].mode
);
7334 /* The place where to find a death note varies with
7335 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7336 necessarily checked exactly in the code that moves
7337 notes, so just check both locations. */
7338 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7339 if (! note
&& store_insn
)
7340 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7343 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7344 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7345 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7346 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7347 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7348 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7349 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7351 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7353 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7355 reg_last_reload_reg
[nregno
] = src_reg
;
7360 int num_regs
= HARD_REGNO_NREGS (nregno
, GET_MODE (rld
[r
].out
));
7362 while (num_regs
-- > 0)
7363 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7367 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7370 /* Emit code to perform a reload from IN (which may be a reload register) to
7371 OUT (which may also be a reload register). IN or OUT is from operand
7372 OPNUM with reload type TYPE.
7374 Returns first insn emitted. */
7377 gen_reload (out
, in
, opnum
, type
)
7381 enum reload_type type
;
7383 rtx last
= get_last_insn ();
7386 /* If IN is a paradoxical SUBREG, remove it and try to put the
7387 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7388 if (GET_CODE (in
) == SUBREG
7389 && (GET_MODE_SIZE (GET_MODE (in
))
7390 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7391 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7392 in
= SUBREG_REG (in
), out
= tem
;
7393 else if (GET_CODE (out
) == SUBREG
7394 && (GET_MODE_SIZE (GET_MODE (out
))
7395 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7396 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7397 out
= SUBREG_REG (out
), in
= tem
;
7399 /* How to do this reload can get quite tricky. Normally, we are being
7400 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7401 register that didn't get a hard register. In that case we can just
7402 call emit_move_insn.
7404 We can also be asked to reload a PLUS that adds a register or a MEM to
7405 another register, constant or MEM. This can occur during frame pointer
7406 elimination and while reloading addresses. This case is handled by
7407 trying to emit a single insn to perform the add. If it is not valid,
7408 we use a two insn sequence.
7410 Finally, we could be called to handle an 'o' constraint by putting
7411 an address into a register. In that case, we first try to do this
7412 with a named pattern of "reload_load_address". If no such pattern
7413 exists, we just emit a SET insn and hope for the best (it will normally
7414 be valid on machines that use 'o').
7416 This entire process is made complex because reload will never
7417 process the insns we generate here and so we must ensure that
7418 they will fit their constraints and also by the fact that parts of
7419 IN might be being reloaded separately and replaced with spill registers.
7420 Because of this, we are, in some sense, just guessing the right approach
7421 here. The one listed above seems to work.
7423 ??? At some point, this whole thing needs to be rethought. */
7425 if (GET_CODE (in
) == PLUS
7426 && (GET_CODE (XEXP (in
, 0)) == REG
7427 || GET_CODE (XEXP (in
, 0)) == SUBREG
7428 || GET_CODE (XEXP (in
, 0)) == MEM
)
7429 && (GET_CODE (XEXP (in
, 1)) == REG
7430 || GET_CODE (XEXP (in
, 1)) == SUBREG
7431 || CONSTANT_P (XEXP (in
, 1))
7432 || GET_CODE (XEXP (in
, 1)) == MEM
))
7434 /* We need to compute the sum of a register or a MEM and another
7435 register, constant, or MEM, and put it into the reload
7436 register. The best possible way of doing this is if the machine
7437 has a three-operand ADD insn that accepts the required operands.
7439 The simplest approach is to try to generate such an insn and see if it
7440 is recognized and matches its constraints. If so, it can be used.
7442 It might be better not to actually emit the insn unless it is valid,
7443 but we need to pass the insn as an operand to `recog' and
7444 `extract_insn' and it is simpler to emit and then delete the insn if
7445 not valid than to dummy things up. */
7447 rtx op0
, op1
, tem
, insn
;
7450 op0
= find_replacement (&XEXP (in
, 0));
7451 op1
= find_replacement (&XEXP (in
, 1));
7453 /* Since constraint checking is strict, commutativity won't be
7454 checked, so we need to do that here to avoid spurious failure
7455 if the add instruction is two-address and the second operand
7456 of the add is the same as the reload reg, which is frequently
7457 the case. If the insn would be A = B + A, rearrange it so
7458 it will be A = A + B as constrain_operands expects. */
7460 if (GET_CODE (XEXP (in
, 1)) == REG
7461 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7462 tem
= op0
, op0
= op1
, op1
= tem
;
7464 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7465 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7467 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7468 code
= recog_memoized (insn
);
7472 extract_insn (insn
);
7473 /* We want constrain operands to treat this insn strictly in
7474 its validity determination, i.e., the way it would after reload
7476 if (constrain_operands (1))
7480 delete_insns_since (last
);
7482 /* If that failed, we must use a conservative two-insn sequence.
7484 Use a move to copy one operand into the reload register. Prefer
7485 to reload a constant, MEM or pseudo since the move patterns can
7486 handle an arbitrary operand. If OP1 is not a constant, MEM or
7487 pseudo and OP1 is not a valid operand for an add instruction, then
7490 After reloading one of the operands into the reload register, add
7491 the reload register to the output register.
7493 If there is another way to do this for a specific machine, a
7494 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7497 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7499 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7500 || (GET_CODE (op1
) == REG
7501 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7502 || (code
!= CODE_FOR_nothing
7503 && ! ((*insn_data
[code
].operand
[2].predicate
)
7504 (op1
, insn_data
[code
].operand
[2].mode
))))
7505 tem
= op0
, op0
= op1
, op1
= tem
;
7507 gen_reload (out
, op0
, opnum
, type
);
7509 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7510 This fixes a problem on the 32K where the stack pointer cannot
7511 be used as an operand of an add insn. */
7513 if (rtx_equal_p (op0
, op1
))
7516 insn
= emit_insn (gen_add2_insn (out
, op1
));
7518 /* If that failed, copy the address register to the reload register.
7519 Then add the constant to the reload register. */
7521 code
= recog_memoized (insn
);
7525 extract_insn (insn
);
7526 /* We want constrain operands to treat this insn strictly in
7527 its validity determination, i.e., the way it would after reload
7529 if (constrain_operands (1))
7531 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7533 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7538 delete_insns_since (last
);
7540 gen_reload (out
, op1
, opnum
, type
);
7541 insn
= emit_insn (gen_add2_insn (out
, op0
));
7542 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7545 #ifdef SECONDARY_MEMORY_NEEDED
7546 /* If we need a memory location to do the move, do it that way. */
7547 else if ((GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
7548 && reg_or_subregno (in
) < FIRST_PSEUDO_REGISTER
7549 && (GET_CODE (out
) == REG
|| GET_CODE (out
) == SUBREG
)
7550 && reg_or_subregno (out
) < FIRST_PSEUDO_REGISTER
7551 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in
)),
7552 REGNO_REG_CLASS (reg_or_subregno (out
)),
7555 /* Get the memory to use and rewrite both registers to its mode. */
7556 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7558 if (GET_MODE (loc
) != GET_MODE (out
))
7559 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7561 if (GET_MODE (loc
) != GET_MODE (in
))
7562 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7564 gen_reload (loc
, in
, opnum
, type
);
7565 gen_reload (out
, loc
, opnum
, type
);
7569 /* If IN is a simple operand, use gen_move_insn. */
7570 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7571 emit_insn (gen_move_insn (out
, in
));
7573 #ifdef HAVE_reload_load_address
7574 else if (HAVE_reload_load_address
)
7575 emit_insn (gen_reload_load_address (out
, in
));
7578 /* Otherwise, just write (set OUT IN) and hope for the best. */
7580 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7582 /* Return the first insn emitted.
7583 We can not just return get_last_insn, because there may have
7584 been multiple instructions emitted. Also note that gen_move_insn may
7585 emit more than one insn itself, so we can not assume that there is one
7586 insn emitted per emit_insn_before call. */
7588 return last
? NEXT_INSN (last
) : get_insns ();
7591 /* Delete a previously made output-reload whose result we now believe
7592 is not needed. First we double-check.
7594 INSN is the insn now being processed.
7595 LAST_RELOAD_REG is the hard register number for which we want to delete
7596 the last output reload.
7597 J is the reload-number that originally used REG. The caller has made
7598 certain that reload J doesn't use REG any longer for input. */
7601 delete_output_reload (insn
, j
, last_reload_reg
)
7604 int last_reload_reg
;
7606 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7607 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7610 int n_inherited
= 0;
7614 /* It is possible that this reload has been only used to set another reload
7615 we eliminated earlier and thus deleted this instruction too. */
7616 if (INSN_DELETED_P (output_reload_insn
))
7619 /* Get the raw pseudo-register referred to. */
7621 while (GET_CODE (reg
) == SUBREG
)
7622 reg
= SUBREG_REG (reg
);
7623 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7625 /* This is unsafe if the operand occurs more often in the current
7626 insn than it is inherited. */
7627 for (k
= n_reloads
- 1; k
>= 0; k
--)
7629 rtx reg2
= rld
[k
].in
;
7632 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
7633 reg2
= rld
[k
].in_reg
;
7635 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
7636 reg2
= XEXP (rld
[k
].in_reg
, 0);
7638 while (GET_CODE (reg2
) == SUBREG
)
7639 reg2
= SUBREG_REG (reg2
);
7640 if (rtx_equal_p (reg2
, reg
))
7642 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7645 reg2
= rld
[k
].out_reg
;
7648 while (GET_CODE (reg2
) == SUBREG
)
7649 reg2
= XEXP (reg2
, 0);
7650 if (rtx_equal_p (reg2
, reg
))
7657 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
7659 n_occurrences
+= count_occurrences (PATTERN (insn
),
7660 eliminate_regs (substed
, 0,
7662 if (n_occurrences
> n_inherited
)
7665 /* If the pseudo-reg we are reloading is no longer referenced
7666 anywhere between the store into it and here,
7667 and no jumps or labels intervene, then the value can get
7668 here through the reload reg alone.
7669 Otherwise, give up--return. */
7670 for (i1
= NEXT_INSN (output_reload_insn
);
7671 i1
!= insn
; i1
= NEXT_INSN (i1
))
7673 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7675 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7676 && reg_mentioned_p (reg
, PATTERN (i1
)))
7678 /* If this is USE in front of INSN, we only have to check that
7679 there are no more references than accounted for by inheritance. */
7680 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
7682 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7683 i1
= NEXT_INSN (i1
);
7685 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7691 /* We will be deleting the insn. Remove the spill reg information. */
7692 for (k
= HARD_REGNO_NREGS (last_reload_reg
, GET_MODE (reg
)); k
-- > 0; )
7694 spill_reg_store
[last_reload_reg
+ k
] = 0;
7695 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
7698 /* The caller has already checked that REG dies or is set in INSN.
7699 It has also checked that we are optimizing, and thus some
7700 inaccuracies in the debugging information are acceptable.
7701 So we could just delete output_reload_insn. But in some cases
7702 we can improve the debugging information without sacrificing
7703 optimization - maybe even improving the code: See if the pseudo
7704 reg has been completely replaced with reload regs. If so, delete
7705 the store insn and forget we had a stack slot for the pseudo. */
7706 if (rld
[j
].out
!= rld
[j
].in
7707 && REG_N_DEATHS (REGNO (reg
)) == 1
7708 && REG_N_SETS (REGNO (reg
)) == 1
7709 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7710 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7714 /* We know that it was used only between here and the beginning of
7715 the current basic block. (We also know that the last use before
7716 INSN was the output reload we are thinking of deleting, but never
7717 mind that.) Search that range; see if any ref remains. */
7718 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7720 rtx set
= single_set (i2
);
7722 /* Uses which just store in the pseudo don't count,
7723 since if they are the only uses, they are dead. */
7724 if (set
!= 0 && SET_DEST (set
) == reg
)
7726 if (GET_CODE (i2
) == CODE_LABEL
7727 || GET_CODE (i2
) == JUMP_INSN
)
7729 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
7730 && reg_mentioned_p (reg
, PATTERN (i2
)))
7732 /* Some other ref remains; just delete the output reload we
7734 delete_address_reloads (output_reload_insn
, insn
);
7735 delete_insn (output_reload_insn
);
7740 /* Delete the now-dead stores into this pseudo. Note that this
7741 loop also takes care of deleting output_reload_insn. */
7742 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7744 rtx set
= single_set (i2
);
7746 if (set
!= 0 && SET_DEST (set
) == reg
)
7748 delete_address_reloads (i2
, insn
);
7751 if (GET_CODE (i2
) == CODE_LABEL
7752 || GET_CODE (i2
) == JUMP_INSN
)
7756 /* For the debugging info, say the pseudo lives in this reload reg. */
7757 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
7758 alter_reg (REGNO (reg
), -1);
7762 delete_address_reloads (output_reload_insn
, insn
);
7763 delete_insn (output_reload_insn
);
7767 /* We are going to delete DEAD_INSN. Recursively delete loads of
7768 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7769 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7771 delete_address_reloads (dead_insn
, current_insn
)
7772 rtx dead_insn
, current_insn
;
7774 rtx set
= single_set (dead_insn
);
7775 rtx set2
, dst
, prev
, next
;
7778 rtx dst
= SET_DEST (set
);
7779 if (GET_CODE (dst
) == MEM
)
7780 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7782 /* If we deleted the store from a reloaded post_{in,de}c expression,
7783 we can delete the matching adds. */
7784 prev
= PREV_INSN (dead_insn
);
7785 next
= NEXT_INSN (dead_insn
);
7786 if (! prev
|| ! next
)
7788 set
= single_set (next
);
7789 set2
= single_set (prev
);
7791 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7792 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7793 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7795 dst
= SET_DEST (set
);
7796 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7797 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7798 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7799 || (INTVAL (XEXP (SET_SRC (set
), 1))
7800 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
7802 delete_related_insns (prev
);
7803 delete_related_insns (next
);
7806 /* Subfunction of delete_address_reloads: process registers found in X. */
7808 delete_address_reloads_1 (dead_insn
, x
, current_insn
)
7809 rtx dead_insn
, x
, current_insn
;
7811 rtx prev
, set
, dst
, i2
;
7813 enum rtx_code code
= GET_CODE (x
);
7817 const char *fmt
= GET_RTX_FORMAT (code
);
7818 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7821 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
7822 else if (fmt
[i
] == 'E')
7824 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7825 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
7832 if (spill_reg_order
[REGNO (x
)] < 0)
7835 /* Scan backwards for the insn that sets x. This might be a way back due
7837 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
7839 code
= GET_CODE (prev
);
7840 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
7842 if (GET_RTX_CLASS (code
) != 'i')
7844 if (reg_set_p (x
, PATTERN (prev
)))
7846 if (reg_referenced_p (x
, PATTERN (prev
)))
7849 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
7851 /* Check that PREV only sets the reload register. */
7852 set
= single_set (prev
);
7855 dst
= SET_DEST (set
);
7856 if (GET_CODE (dst
) != REG
7857 || ! rtx_equal_p (dst
, x
))
7859 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
7861 /* Check if DST was used in a later insn -
7862 it might have been inherited. */
7863 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
7865 if (GET_CODE (i2
) == CODE_LABEL
)
7869 if (reg_referenced_p (dst
, PATTERN (i2
)))
7871 /* If there is a reference to the register in the current insn,
7872 it might be loaded in a non-inherited reload. If no other
7873 reload uses it, that means the register is set before
7875 if (i2
== current_insn
)
7877 for (j
= n_reloads
- 1; j
>= 0; j
--)
7878 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7879 || reload_override_in
[j
] == dst
)
7881 for (j
= n_reloads
- 1; j
>= 0; j
--)
7882 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
7889 if (GET_CODE (i2
) == JUMP_INSN
)
7891 /* If DST is still live at CURRENT_INSN, check if it is used for
7892 any reload. Note that even if CURRENT_INSN sets DST, we still
7893 have to check the reloads. */
7894 if (i2
== current_insn
)
7896 for (j
= n_reloads
- 1; j
>= 0; j
--)
7897 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7898 || reload_override_in
[j
] == dst
)
7900 /* ??? We can't finish the loop here, because dst might be
7901 allocated to a pseudo in this block if no reload in this
7902 block needs any of the classes containing DST - see
7903 spill_hard_reg. There is no easy way to tell this, so we
7904 have to scan till the end of the basic block. */
7906 if (reg_set_p (dst
, PATTERN (i2
)))
7910 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
7911 reg_reloaded_contents
[REGNO (dst
)] = -1;
7915 /* Output reload-insns to reload VALUE into RELOADREG.
7916 VALUE is an autoincrement or autodecrement RTX whose operand
7917 is a register or memory location;
7918 so reloading involves incrementing that location.
7919 IN is either identical to VALUE, or some cheaper place to reload from.
7921 INC_AMOUNT is the number to increment or decrement by (always positive).
7922 This cannot be deduced from VALUE.
7924 Return the instruction that stores into RELOADREG. */
7927 inc_for_reload (reloadreg
, in
, value
, inc_amount
)
7932 /* REG or MEM to be copied and incremented. */
7933 rtx incloc
= XEXP (value
, 0);
7934 /* Nonzero if increment after copying. */
7935 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
7941 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
7943 /* No hard register is equivalent to this register after
7944 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7945 we could inc/dec that register as well (maybe even using it for
7946 the source), but I'm not sure it's worth worrying about. */
7947 if (GET_CODE (incloc
) == REG
)
7948 reg_last_reload_reg
[REGNO (incloc
)] = 0;
7950 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
7951 inc_amount
= -inc_amount
;
7953 inc
= GEN_INT (inc_amount
);
7955 /* If this is post-increment, first copy the location to the reload reg. */
7956 if (post
&& real_in
!= reloadreg
)
7957 emit_insn (gen_move_insn (reloadreg
, real_in
));
7961 /* See if we can directly increment INCLOC. Use a method similar to
7962 that in gen_reload. */
7964 last
= get_last_insn ();
7965 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
7966 gen_rtx_PLUS (GET_MODE (incloc
),
7969 code
= recog_memoized (add_insn
);
7972 extract_insn (add_insn
);
7973 if (constrain_operands (1))
7975 /* If this is a pre-increment and we have incremented the value
7976 where it lives, copy the incremented value to RELOADREG to
7977 be used as an address. */
7980 emit_insn (gen_move_insn (reloadreg
, incloc
));
7985 delete_insns_since (last
);
7988 /* If couldn't do the increment directly, must increment in RELOADREG.
7989 The way we do this depends on whether this is pre- or post-increment.
7990 For pre-increment, copy INCLOC to the reload register, increment it
7991 there, then save back. */
7995 if (in
!= reloadreg
)
7996 emit_insn (gen_move_insn (reloadreg
, real_in
));
7997 emit_insn (gen_add2_insn (reloadreg
, inc
));
7998 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8003 Because this might be a jump insn or a compare, and because RELOADREG
8004 may not be available after the insn in an input reload, we must do
8005 the incrementation before the insn being reloaded for.
8007 We have already copied IN to RELOADREG. Increment the copy in
8008 RELOADREG, save that back, then decrement RELOADREG so it has
8009 the original value. */
8011 emit_insn (gen_add2_insn (reloadreg
, inc
));
8012 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8013 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
8020 /* See whether a single set SET is a noop. */
8022 reload_cse_noop_set_p (set
)
8025 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
8028 /* Try to simplify INSN. */
8030 reload_cse_simplify (insn
, testreg
)
8034 rtx body
= PATTERN (insn
);
8036 if (GET_CODE (body
) == SET
)
8040 /* Simplify even if we may think it is a no-op.
8041 We may think a memory load of a value smaller than WORD_SIZE
8042 is redundant because we haven't taken into account possible
8043 implicit extension. reload_cse_simplify_set() will bring
8044 this out, so it's safer to simplify before we delete. */
8045 count
+= reload_cse_simplify_set (body
, insn
);
8047 if (!count
&& reload_cse_noop_set_p (body
))
8049 rtx value
= SET_DEST (body
);
8051 && ! REG_FUNCTION_VALUE_P (value
))
8053 delete_insn_and_edges (insn
);
8058 apply_change_group ();
8060 reload_cse_simplify_operands (insn
, testreg
);
8062 else if (GET_CODE (body
) == PARALLEL
)
8066 rtx value
= NULL_RTX
;
8068 /* If every action in a PARALLEL is a noop, we can delete
8069 the entire PARALLEL. */
8070 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8072 rtx part
= XVECEXP (body
, 0, i
);
8073 if (GET_CODE (part
) == SET
)
8075 if (! reload_cse_noop_set_p (part
))
8077 if (REG_P (SET_DEST (part
))
8078 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
8082 value
= SET_DEST (part
);
8085 else if (GET_CODE (part
) != CLOBBER
)
8091 delete_insn_and_edges (insn
);
8092 /* We're done with this insn. */
8096 /* It's not a no-op, but we can try to simplify it. */
8097 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8098 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
8099 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
8102 apply_change_group ();
8104 reload_cse_simplify_operands (insn
, testreg
);
8108 /* Do a very simple CSE pass over the hard registers.
8110 This function detects no-op moves where we happened to assign two
8111 different pseudo-registers to the same hard register, and then
8112 copied one to the other. Reload will generate a useless
8113 instruction copying a register to itself.
8115 This function also detects cases where we load a value from memory
8116 into two different registers, and (if memory is more expensive than
8117 registers) changes it to simply copy the first register into the
8120 Another optimization is performed that scans the operands of each
8121 instruction to see whether the value is already available in a
8122 hard register. It then replaces the operand with the hard register
8123 if possible, much like an optional reload would. */
8126 reload_cse_regs_1 (first
)
8130 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
8133 init_alias_analysis ();
8135 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8138 reload_cse_simplify (insn
, testreg
);
8140 cselib_process_insn (insn
);
8144 end_alias_analysis ();
8148 /* Call cse / combine like post-reload optimization phases.
8149 FIRST is the first instruction. */
8151 reload_cse_regs (first
)
8154 reload_cse_regs_1 (first
);
8156 reload_cse_move2add (first
);
8157 if (flag_expensive_optimizations
)
8158 reload_cse_regs_1 (first
);
8161 /* Try to simplify a single SET instruction. SET is the set pattern.
8162 INSN is the instruction it came from.
8163 This function only handles one case: if we set a register to a value
8164 which is not a register, we try to find that value in some other register
8165 and change the set into a register copy. */
8168 reload_cse_simplify_set (set
, insn
)
8175 enum reg_class dclass
;
8178 struct elt_loc_list
*l
;
8179 #ifdef LOAD_EXTEND_OP
8180 enum rtx_code extend_op
= NIL
;
8183 dreg
= true_regnum (SET_DEST (set
));
8187 src
= SET_SRC (set
);
8188 if (side_effects_p (src
) || true_regnum (src
) >= 0)
8191 dclass
= REGNO_REG_CLASS (dreg
);
8193 #ifdef LOAD_EXTEND_OP
8194 /* When replacing a memory with a register, we need to honor assumptions
8195 that combine made wrt the contents of sign bits. We'll do this by
8196 generating an extend instruction instead of a reg->reg copy. Thus
8197 the destination must be a register that we can widen. */
8198 if (GET_CODE (src
) == MEM
8199 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
8200 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != NIL
8201 && GET_CODE (SET_DEST (set
)) != REG
)
8205 /* If memory loads are cheaper than register copies, don't change them. */
8206 if (GET_CODE (src
) == MEM
)
8207 old_cost
= MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1);
8208 else if (CONSTANT_P (src
))
8209 old_cost
= rtx_cost (src
, SET
);
8210 else if (GET_CODE (src
) == REG
)
8211 old_cost
= REGISTER_MOVE_COST (GET_MODE (src
),
8212 REGNO_REG_CLASS (REGNO (src
)), dclass
);
8215 old_cost
= rtx_cost (src
, SET
);
8217 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0);
8220 for (l
= val
->locs
; l
; l
= l
->next
)
8222 rtx this_rtx
= l
->loc
;
8225 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
8227 #ifdef LOAD_EXTEND_OP
8228 if (extend_op
!= NIL
)
8230 HOST_WIDE_INT this_val
;
8232 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8233 constants, such as SYMBOL_REF, cannot be extended. */
8234 if (GET_CODE (this_rtx
) != CONST_INT
)
8237 this_val
= INTVAL (this_rtx
);
8241 this_val
&= GET_MODE_MASK (GET_MODE (src
));
8244 /* ??? In theory we're already extended. */
8245 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
8250 this_rtx
= GEN_INT (this_val
);
8253 this_cost
= rtx_cost (this_rtx
, SET
);
8255 else if (GET_CODE (this_rtx
) == REG
)
8257 #ifdef LOAD_EXTEND_OP
8258 if (extend_op
!= NIL
)
8260 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
8261 this_cost
= rtx_cost (this_rtx
, SET
);
8265 this_cost
= REGISTER_MOVE_COST (GET_MODE (this_rtx
),
8266 REGNO_REG_CLASS (REGNO (this_rtx
)),
8272 /* If equal costs, prefer registers over anything else. That
8273 tends to lead to smaller instructions on some machines. */
8274 if (this_cost
< old_cost
8275 || (this_cost
== old_cost
8276 && GET_CODE (this_rtx
) == REG
8277 && GET_CODE (SET_SRC (set
)) != REG
))
8279 #ifdef LOAD_EXTEND_OP
8280 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
8281 && extend_op
!= NIL
)
8283 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
8284 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
8285 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
8289 validate_change (insn
, &SET_SRC (set
), copy_rtx (this_rtx
), 1);
8290 old_cost
= this_cost
, did_change
= 1;
8297 /* Try to replace operands in INSN with equivalent values that are already
8298 in registers. This can be viewed as optional reloading.
8300 For each non-register operand in the insn, see if any hard regs are
8301 known to be equivalent to that operand. Record the alternatives which
8302 can accept these hard registers. Among all alternatives, select the
8303 ones which are better or equal to the one currently matching, where
8304 "better" is in terms of '?' and '!' constraints. Among the remaining
8305 alternatives, select the one which replaces most operands with
8309 reload_cse_simplify_operands (insn
, testreg
)
8315 /* For each operand, all registers that are equivalent to it. */
8316 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
8318 const char *constraints
[MAX_RECOG_OPERANDS
];
8320 /* Vector recording how bad an alternative is. */
8321 int *alternative_reject
;
8322 /* Vector recording how many registers can be introduced by choosing
8323 this alternative. */
8324 int *alternative_nregs
;
8325 /* Array of vectors recording, for each operand and each alternative,
8326 which hard register to substitute, or -1 if the operand should be
8328 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
8329 /* Array of alternatives, sorted in order of decreasing desirability. */
8330 int *alternative_order
;
8332 extract_insn (insn
);
8334 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
8337 /* Figure out which alternative currently matches. */
8338 if (! constrain_operands (1))
8339 fatal_insn_not_found (insn
);
8341 alternative_reject
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8342 alternative_nregs
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8343 alternative_order
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8344 memset ((char *) alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
8345 memset ((char *) alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
8347 /* For each operand, find out which regs are equivalent. */
8348 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8351 struct elt_loc_list
*l
;
8353 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
8355 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8356 right, so avoid the problem here. Likewise if we have a constant
8357 and the insn pattern doesn't tell us the mode we need. */
8358 if (GET_CODE (recog_data
.operand
[i
]) == CODE_LABEL
8359 || (CONSTANT_P (recog_data
.operand
[i
])
8360 && recog_data
.operand_mode
[i
] == VOIDmode
))
8363 v
= cselib_lookup (recog_data
.operand
[i
], recog_data
.operand_mode
[i
], 0);
8367 for (l
= v
->locs
; l
; l
= l
->next
)
8368 if (GET_CODE (l
->loc
) == REG
)
8369 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
8372 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8374 enum machine_mode mode
;
8378 op_alt_regno
[i
] = (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8379 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
8380 op_alt_regno
[i
][j
] = -1;
8382 p
= constraints
[i
] = recog_data
.constraints
[i
];
8383 mode
= recog_data
.operand_mode
[i
];
8385 /* Add the reject values for each alternative given by the constraints
8386 for this operand. */
8394 alternative_reject
[j
] += 3;
8396 alternative_reject
[j
] += 300;
8399 /* We won't change operands which are already registers. We
8400 also don't want to modify output operands. */
8401 regno
= true_regnum (recog_data
.operand
[i
]);
8403 || constraints
[i
][0] == '='
8404 || constraints
[i
][0] == '+')
8407 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
8409 int class = (int) NO_REGS
;
8411 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
8414 REGNO (testreg
) = regno
;
8415 PUT_MODE (testreg
, mode
);
8417 /* We found a register equal to this operand. Now look for all
8418 alternatives that can accept this register and have not been
8419 assigned a register they can use yet. */
8428 case '=': case '+': case '?':
8429 case '#': case '&': case '!':
8431 case '0': case '1': case '2': case '3': case '4':
8432 case '5': case '6': case '7': case '8': case '9':
8433 case 'm': case '<': case '>': case 'V': case 'o':
8434 case 'E': case 'F': case 'G': case 'H':
8435 case 's': case 'i': case 'n':
8436 case 'I': case 'J': case 'K': case 'L':
8437 case 'M': case 'N': case 'O': case 'P':
8439 /* These don't say anything we care about. */
8443 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
8448 = (reg_class_subunion
8450 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
8453 case ',': case '\0':
8454 /* See if REGNO fits this alternative, and set it up as the
8455 replacement register if we don't have one for this
8456 alternative yet and the operand being replaced is not
8457 a cheap CONST_INT. */
8458 if (op_alt_regno
[i
][j
] == -1
8459 && reg_fits_class_p (testreg
, class, 0, mode
)
8460 && (GET_CODE (recog_data
.operand
[i
]) != CONST_INT
8461 || (rtx_cost (recog_data
.operand
[i
], SET
)
8462 > rtx_cost (testreg
, SET
))))
8464 alternative_nregs
[j
]++;
8465 op_alt_regno
[i
][j
] = regno
;
8470 p
+= CONSTRAINT_LEN (c
, p
);
8478 /* Record all alternatives which are better or equal to the currently
8479 matching one in the alternative_order array. */
8480 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
8481 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
8482 alternative_order
[j
++] = i
;
8483 recog_data
.n_alternatives
= j
;
8485 /* Sort it. Given a small number of alternatives, a dumb algorithm
8486 won't hurt too much. */
8487 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
8490 int best_reject
= alternative_reject
[alternative_order
[i
]];
8491 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
8494 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
8496 int this_reject
= alternative_reject
[alternative_order
[j
]];
8497 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
8499 if (this_reject
< best_reject
8500 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
8503 best_reject
= this_reject
;
8504 best_nregs
= this_nregs
;
8508 tmp
= alternative_order
[best
];
8509 alternative_order
[best
] = alternative_order
[i
];
8510 alternative_order
[i
] = tmp
;
8513 /* Substitute the operands as determined by op_alt_regno for the best
8515 j
= alternative_order
[0];
8517 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8519 enum machine_mode mode
= recog_data
.operand_mode
[i
];
8520 if (op_alt_regno
[i
][j
] == -1)
8523 validate_change (insn
, recog_data
.operand_loc
[i
],
8524 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
8527 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
8529 int op
= recog_data
.dup_num
[i
];
8530 enum machine_mode mode
= recog_data
.operand_mode
[op
];
8532 if (op_alt_regno
[op
][j
] == -1)
8535 validate_change (insn
, recog_data
.dup_loc
[i
],
8536 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
8539 return apply_change_group ();
8542 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8544 This code might also be useful when reload gave up on reg+reg addressing
8545 because of clashes between the return register and INDEX_REG_CLASS. */
8547 /* The maximum number of uses of a register we can keep track of to
8548 replace them with reg+reg addressing. */
8549 #define RELOAD_COMBINE_MAX_USES 6
8551 /* INSN is the insn where a register has ben used, and USEP points to the
8552 location of the register within the rtl. */
8553 struct reg_use
{ rtx insn
, *usep
; };
8555 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8556 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8557 indicates where it becomes live again.
8558 Otherwise, USE_INDEX is the index of the last encountered use of the
8559 register (which is first among these we have seen since we scan backwards),
8560 OFFSET contains the constant offset that is added to the register in
8561 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8562 last, of these uses.
8563 STORE_RUID is always meaningful if we only want to use a value in a
8564 register in a different place: it denotes the next insn in the insn
8565 stream (i.e. the last encountered) that sets or clobbers the register. */
8568 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
8573 } reg_state
[FIRST_PSEUDO_REGISTER
];
8575 /* Reverse linear uid. This is increased in reload_combine while scanning
8576 the instructions from last to first. It is used to set last_label_ruid
8577 and the store_ruid / use_ruid fields in reg_state. */
8578 static int reload_combine_ruid
;
8580 #define LABEL_LIVE(LABEL) \
8581 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8587 int first_index_reg
= -1;
8588 int last_index_reg
= 0;
8592 int last_label_ruid
;
8593 int min_labelno
, n_labels
;
8594 HARD_REG_SET ever_live_at_start
, *label_live
;
8596 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
8597 reload has already used it where appropriate, so there is no use in
8598 trying to generate it now. */
8599 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
8602 /* To avoid wasting too much time later searching for an index register,
8603 determine the minimum and maximum index register numbers. */
8604 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8605 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
8607 if (first_index_reg
== -1)
8608 first_index_reg
= r
;
8613 /* If no index register is available, we can quit now. */
8614 if (first_index_reg
== -1)
8617 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8618 information is a bit fuzzy immediately after reload, but it's
8619 still good enough to determine which registers are live at a jump
8621 min_labelno
= get_first_label_num ();
8622 n_labels
= max_label_num () - min_labelno
;
8623 label_live
= (HARD_REG_SET
*) xmalloc (n_labels
* sizeof (HARD_REG_SET
));
8624 CLEAR_HARD_REG_SET (ever_live_at_start
);
8626 FOR_EACH_BB_REVERSE (bb
)
8629 if (GET_CODE (insn
) == CODE_LABEL
)
8633 REG_SET_TO_HARD_REG_SET (live
,
8634 bb
->global_live_at_start
);
8635 compute_use_by_pseudos (&live
,
8636 bb
->global_live_at_start
);
8637 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
8638 IOR_HARD_REG_SET (ever_live_at_start
, live
);
8642 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8643 last_label_ruid
= reload_combine_ruid
= 0;
8644 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8646 reg_state
[r
].store_ruid
= reload_combine_ruid
;
8648 reg_state
[r
].use_index
= -1;
8650 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8653 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
8657 /* We cannot do our optimization across labels. Invalidating all the use
8658 information we have would be costly, so we just note where the label
8659 is and then later disable any optimization that would cross it. */
8660 if (GET_CODE (insn
) == CODE_LABEL
)
8661 last_label_ruid
= reload_combine_ruid
;
8662 else if (GET_CODE (insn
) == BARRIER
)
8663 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8664 if (! fixed_regs
[r
])
8665 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8667 if (! INSN_P (insn
))
8670 reload_combine_ruid
++;
8672 /* Look for (set (REGX) (CONST_INT))
8673 (set (REGX) (PLUS (REGX) (REGY)))
8675 ... (MEM (REGX)) ...
8677 (set (REGZ) (CONST_INT))
8679 ... (MEM (PLUS (REGZ) (REGY)))... .
8681 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8682 and that we know all uses of REGX before it dies. */
8683 set
= single_set (insn
);
8685 && GET_CODE (SET_DEST (set
)) == REG
8686 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
8687 GET_MODE (SET_DEST (set
)))
8689 && GET_CODE (SET_SRC (set
)) == PLUS
8690 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
8691 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
8692 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
8694 rtx reg
= SET_DEST (set
);
8695 rtx plus
= SET_SRC (set
);
8696 rtx base
= XEXP (plus
, 1);
8697 rtx prev
= prev_nonnote_insn (insn
);
8698 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
8699 unsigned int regno
= REGNO (reg
);
8700 rtx const_reg
= NULL_RTX
;
8701 rtx reg_sum
= NULL_RTX
;
8703 /* Now, we need an index register.
8704 We'll set index_reg to this index register, const_reg to the
8705 register that is to be loaded with the constant
8706 (denoted as REGZ in the substitution illustration above),
8707 and reg_sum to the register-register that we want to use to
8708 substitute uses of REG (typically in MEMs) with.
8709 First check REG and BASE for being index registers;
8710 we can use them even if they are not dead. */
8711 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
8712 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
8720 /* Otherwise, look for a free index register. Since we have
8721 checked above that neiter REG nor BASE are index registers,
8722 if we find anything at all, it will be different from these
8724 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
8726 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
8728 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
8729 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
8730 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
8732 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
8734 const_reg
= index_reg
;
8735 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
8741 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8742 (REGY), i.e. BASE, is not clobbered before the last use we'll
8745 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
8746 && rtx_equal_p (SET_DEST (prev_set
), reg
)
8747 && reg_state
[regno
].use_index
>= 0
8748 && (reg_state
[REGNO (base
)].store_ruid
8749 <= reg_state
[regno
].use_ruid
)
8754 /* Change destination register and, if necessary, the
8755 constant value in PREV, the constant loading instruction. */
8756 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
8757 if (reg_state
[regno
].offset
!= const0_rtx
)
8758 validate_change (prev
,
8759 &SET_SRC (prev_set
),
8760 GEN_INT (INTVAL (SET_SRC (prev_set
))
8761 + INTVAL (reg_state
[regno
].offset
)),
8764 /* Now for every use of REG that we have recorded, replace REG
8766 for (i
= reg_state
[regno
].use_index
;
8767 i
< RELOAD_COMBINE_MAX_USES
; i
++)
8768 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
8769 reg_state
[regno
].reg_use
[i
].usep
,
8770 /* Each change must have its own
8772 copy_rtx (reg_sum
), 1);
8774 if (apply_change_group ())
8778 /* Delete the reg-reg addition. */
8781 if (reg_state
[regno
].offset
!= const0_rtx
)
8782 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8784 for (np
= ®_NOTES (prev
); *np
;)
8786 if (REG_NOTE_KIND (*np
) == REG_EQUAL
8787 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
8788 *np
= XEXP (*np
, 1);
8790 np
= &XEXP (*np
, 1);
8793 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
8794 reg_state
[REGNO (const_reg
)].store_ruid
8795 = reload_combine_ruid
;
8801 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
8803 if (GET_CODE (insn
) == CALL_INSN
)
8807 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8808 if (call_used_regs
[r
])
8810 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8811 reg_state
[r
].store_ruid
= reload_combine_ruid
;
8814 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
8815 link
= XEXP (link
, 1))
8817 rtx usage_rtx
= XEXP (XEXP (link
, 0), 0);
8818 if (GET_CODE (usage_rtx
) == REG
)
8821 unsigned int start_reg
= REGNO (usage_rtx
);
8822 unsigned int num_regs
=
8823 HARD_REGNO_NREGS (start_reg
, GET_MODE (usage_rtx
));
8824 unsigned int end_reg
= start_reg
+ num_regs
- 1;
8825 for (i
= start_reg
; i
<= end_reg
; i
++)
8826 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
8828 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8829 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8832 reg_state
[i
].use_index
= -1;
8837 else if (GET_CODE (insn
) == JUMP_INSN
8838 && GET_CODE (PATTERN (insn
)) != RETURN
)
8840 /* Non-spill registers might be used at the call destination in
8841 some unknown fashion, so we have to mark the unknown use. */
8844 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
8845 && JUMP_LABEL (insn
))
8846 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
8848 live
= &ever_live_at_start
;
8850 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
8851 if (TEST_HARD_REG_BIT (*live
, i
))
8852 reg_state
[i
].use_index
= -1;
8855 reload_combine_note_use (&PATTERN (insn
), insn
);
8856 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
8858 if (REG_NOTE_KIND (note
) == REG_INC
8859 && GET_CODE (XEXP (note
, 0)) == REG
)
8861 int regno
= REGNO (XEXP (note
, 0));
8863 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
8864 reg_state
[regno
].use_index
= -1;
8872 /* Check if DST is a register or a subreg of a register; if it is,
8873 update reg_state[regno].store_ruid and reg_state[regno].use_index
8874 accordingly. Called via note_stores from reload_combine. */
8877 reload_combine_note_store (dst
, set
, data
)
8879 void *data ATTRIBUTE_UNUSED
;
8883 enum machine_mode mode
= GET_MODE (dst
);
8885 if (GET_CODE (dst
) == SUBREG
)
8887 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
8888 GET_MODE (SUBREG_REG (dst
)),
8891 dst
= SUBREG_REG (dst
);
8893 if (GET_CODE (dst
) != REG
)
8895 regno
+= REGNO (dst
);
8897 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8898 careful with registers / register parts that are not full words.
8900 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8901 if (GET_CODE (set
) != SET
8902 || GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
8903 || GET_CODE (SET_DEST (set
)) == SIGN_EXTRACT
8904 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
8906 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8908 reg_state
[i
].use_index
= -1;
8909 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8914 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8916 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8917 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8922 /* XP points to a piece of rtl that has to be checked for any uses of
8924 *XP is the pattern of INSN, or a part of it.
8925 Called from reload_combine, and recursively by itself. */
8927 reload_combine_note_use (xp
, insn
)
8931 enum rtx_code code
= x
->code
;
8934 rtx offset
= const0_rtx
; /* For the REG case below. */
8939 if (GET_CODE (SET_DEST (x
)) == REG
)
8941 reload_combine_note_use (&SET_SRC (x
), insn
);
8947 /* If this is the USE of a return value, we can't change it. */
8948 if (GET_CODE (XEXP (x
, 0)) == REG
&& REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
8950 /* Mark the return register as used in an unknown fashion. */
8951 rtx reg
= XEXP (x
, 0);
8952 int regno
= REGNO (reg
);
8953 int nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8955 while (--nregs
>= 0)
8956 reg_state
[regno
+ nregs
].use_index
= -1;
8962 if (GET_CODE (SET_DEST (x
)) == REG
)
8964 /* No spurious CLOBBERs of pseudo registers may remain. */
8965 if (REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
)
8972 /* We are interested in (plus (reg) (const_int)) . */
8973 if (GET_CODE (XEXP (x
, 0)) != REG
8974 || GET_CODE (XEXP (x
, 1)) != CONST_INT
)
8976 offset
= XEXP (x
, 1);
8981 int regno
= REGNO (x
);
8985 /* No spurious USEs of pseudo registers may remain. */
8986 if (regno
>= FIRST_PSEUDO_REGISTER
)
8989 nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
8991 /* We can't substitute into multi-hard-reg uses. */
8994 while (--nregs
>= 0)
8995 reg_state
[regno
+ nregs
].use_index
= -1;
8999 /* If this register is already used in some unknown fashion, we
9001 If we decrement the index from zero to -1, we can't store more
9002 uses, so this register becomes used in an unknown fashion. */
9003 use_index
= --reg_state
[regno
].use_index
;
9007 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
9009 /* We have found another use for a register that is already
9010 used later. Check if the offsets match; if not, mark the
9011 register as used in an unknown fashion. */
9012 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
9014 reg_state
[regno
].use_index
= -1;
9020 /* This is the first use of this register we have seen since we
9021 marked it as dead. */
9022 reg_state
[regno
].offset
= offset
;
9023 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
9025 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
9026 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
9034 /* Recursively process the components of X. */
9035 fmt
= GET_RTX_FORMAT (code
);
9036 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9039 reload_combine_note_use (&XEXP (x
, i
), insn
);
9040 else if (fmt
[i
] == 'E')
9042 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9043 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
9048 /* See if we can reduce the cost of a constant by replacing a move
9049 with an add. We track situations in which a register is set to a
9050 constant or to a register plus a constant. */
9051 /* We cannot do our optimization across labels. Invalidating all the
9052 information about register contents we have would be costly, so we
9053 use move2add_last_label_luid to note where the label is and then
9054 later disable any optimization that would cross it.
9055 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9056 reg_set_luid[n] is greater than last_label_luid[n] . */
9057 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
9059 /* If reg_base_reg[n] is negative, register n has been set to
9060 reg_offset[n] in mode reg_mode[n] .
9061 If reg_base_reg[n] is non-negative, register n has been set to the
9062 sum of reg_offset[n] and the value of register reg_base_reg[n]
9063 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9064 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
9065 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
9066 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
9068 /* move2add_luid is linearly increased while scanning the instructions
9069 from first to last. It is used to set reg_set_luid in
9070 reload_cse_move2add and move2add_note_store. */
9071 static int move2add_luid
;
9073 /* move2add_last_label_luid is set whenever a label is found. Labels
9074 invalidate all previously collected reg_offset data. */
9075 static int move2add_last_label_luid
;
9077 /* Generate a CONST_INT and force it in the range of MODE. */
9079 static HOST_WIDE_INT
9080 sext_for_mode (mode
, value
)
9081 enum machine_mode mode
;
9082 HOST_WIDE_INT value
;
9084 HOST_WIDE_INT cval
= value
& GET_MODE_MASK (mode
);
9085 int width
= GET_MODE_BITSIZE (mode
);
9087 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9089 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
9090 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
9091 cval
|= (HOST_WIDE_INT
) -1 << width
;
9096 /* ??? We don't know how zero / sign extension is handled, hence we
9097 can't go from a narrower to a wider mode. */
9098 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9099 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9100 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9101 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9102 GET_MODE_BITSIZE (INMODE))))
9105 reload_cse_move2add (first
)
9111 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
9112 reg_set_luid
[i
] = 0;
9114 move2add_last_label_luid
= 0;
9116 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
9120 if (GET_CODE (insn
) == CODE_LABEL
)
9122 move2add_last_label_luid
= move2add_luid
;
9123 /* We're going to increment move2add_luid twice after a
9124 label, so that we can use move2add_last_label_luid + 1 as
9125 the luid for constants. */
9129 if (! INSN_P (insn
))
9131 pat
= PATTERN (insn
);
9132 /* For simplicity, we only perform this optimization on
9133 straightforward SETs. */
9134 if (GET_CODE (pat
) == SET
9135 && GET_CODE (SET_DEST (pat
)) == REG
)
9137 rtx reg
= SET_DEST (pat
);
9138 int regno
= REGNO (reg
);
9139 rtx src
= SET_SRC (pat
);
9141 /* Check if we have valid information on the contents of this
9142 register in the mode of REG. */
9143 if (reg_set_luid
[regno
] > move2add_last_label_luid
9144 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
]))
9146 /* Try to transform (set (REGX) (CONST_INT A))
9148 (set (REGX) (CONST_INT B))
9150 (set (REGX) (CONST_INT A))
9152 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9154 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
9157 rtx new_src
= GEN_INT (sext_for_mode (GET_MODE (reg
),
9159 - reg_offset
[regno
]));
9160 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9161 use (set (reg) (reg)) instead.
9162 We don't delete this insn, nor do we convert it into a
9163 note, to avoid losing register notes or the return
9164 value flag. jump2 already knows how to get rid of
9166 if (new_src
== const0_rtx
)
9167 success
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
9168 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
9169 && have_add2_insn (reg
, new_src
))
9170 success
= validate_change (insn
, &PATTERN (insn
),
9171 gen_add2_insn (reg
, new_src
), 0);
9172 reg_set_luid
[regno
] = move2add_luid
;
9173 reg_mode
[regno
] = GET_MODE (reg
);
9174 reg_offset
[regno
] = INTVAL (src
);
9178 /* Try to transform (set (REGX) (REGY))
9179 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9182 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9185 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9187 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9188 else if (GET_CODE (src
) == REG
9189 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
9190 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
9191 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
),
9192 reg_mode
[REGNO (src
)]))
9194 rtx next
= next_nonnote_insn (insn
);
9197 set
= single_set (next
);
9199 && SET_DEST (set
) == reg
9200 && GET_CODE (SET_SRC (set
)) == PLUS
9201 && XEXP (SET_SRC (set
), 0) == reg
9202 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
9204 rtx src3
= XEXP (SET_SRC (set
), 1);
9205 HOST_WIDE_INT added_offset
= INTVAL (src3
);
9206 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
9207 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
9208 rtx new_src
= GEN_INT (sext_for_mode (GET_MODE (reg
),
9214 if (new_src
== const0_rtx
)
9215 /* See above why we create (set (reg) (reg)) here. */
9217 = validate_change (next
, &SET_SRC (set
), reg
, 0);
9218 else if ((rtx_cost (new_src
, PLUS
)
9219 < COSTS_N_INSNS (1) + rtx_cost (src3
, SET
))
9220 && have_add2_insn (reg
, new_src
))
9222 = validate_change (next
, &PATTERN (next
),
9223 gen_add2_insn (reg
, new_src
), 0);
9227 reg_mode
[regno
] = GET_MODE (reg
);
9228 reg_offset
[regno
] = sext_for_mode (GET_MODE (reg
),
9237 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9239 if (REG_NOTE_KIND (note
) == REG_INC
9240 && GET_CODE (XEXP (note
, 0)) == REG
)
9242 /* Reset the information about this register. */
9243 int regno
= REGNO (XEXP (note
, 0));
9244 if (regno
< FIRST_PSEUDO_REGISTER
)
9245 reg_set_luid
[regno
] = 0;
9248 note_stores (PATTERN (insn
), move2add_note_store
, NULL
);
9249 /* If this is a CALL_INSN, all call used registers are stored with
9251 if (GET_CODE (insn
) == CALL_INSN
)
9253 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
9255 if (call_used_regs
[i
])
9256 /* Reset the information about this register. */
9257 reg_set_luid
[i
] = 0;
9263 /* SET is a SET or CLOBBER that sets DST.
9264 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9265 Called from reload_cse_move2add via note_stores. */
9268 move2add_note_store (dst
, set
, data
)
9270 void *data ATTRIBUTE_UNUSED
;
9272 unsigned int regno
= 0;
9274 enum machine_mode mode
= GET_MODE (dst
);
9276 if (GET_CODE (dst
) == SUBREG
)
9278 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
9279 GET_MODE (SUBREG_REG (dst
)),
9282 dst
= SUBREG_REG (dst
);
9285 /* Some targets do argument pushes without adding REG_INC notes. */
9287 if (GET_CODE (dst
) == MEM
)
9289 dst
= XEXP (dst
, 0);
9290 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
9291 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
9292 reg_set_luid
[REGNO (XEXP (dst
, 0))] = 0;
9295 if (GET_CODE (dst
) != REG
)
9298 regno
+= REGNO (dst
);
9300 if (HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
9301 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
9302 && GET_CODE (SET_DEST (set
)) != SIGN_EXTRACT
9303 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
9305 rtx src
= SET_SRC (set
);
9307 HOST_WIDE_INT offset
;
9309 /* This may be different from mode, if SET_DEST (set) is a
9311 enum machine_mode dst_mode
= GET_MODE (dst
);
9313 switch (GET_CODE (src
))
9316 if (GET_CODE (XEXP (src
, 0)) == REG
)
9318 base_reg
= XEXP (src
, 0);
9320 if (GET_CODE (XEXP (src
, 1)) == CONST_INT
)
9321 offset
= INTVAL (XEXP (src
, 1));
9322 else if (GET_CODE (XEXP (src
, 1)) == REG
9323 && (reg_set_luid
[REGNO (XEXP (src
, 1))]
9324 > move2add_last_label_luid
)
9325 && (MODES_OK_FOR_MOVE2ADD
9326 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))])))
9328 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0)
9329 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
9330 /* Maybe the first register is known to be a
9332 else if (reg_set_luid
[REGNO (base_reg
)]
9333 > move2add_last_label_luid
9334 && (MODES_OK_FOR_MOVE2ADD
9335 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))]))
9336 && reg_base_reg
[REGNO (base_reg
)] < 0)
9338 offset
= reg_offset
[REGNO (base_reg
)];
9339 base_reg
= XEXP (src
, 1);
9358 /* Start tracking the register as a constant. */
9359 reg_base_reg
[regno
] = -1;
9360 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
9361 /* We assign the same luid to all registers set to constants. */
9362 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
9363 reg_mode
[regno
] = mode
;
9368 /* Invalidate the contents of the register. */
9369 reg_set_luid
[regno
] = 0;
9373 base_regno
= REGNO (base_reg
);
9374 /* If information about the base register is not valid, set it
9375 up as a new base register, pretending its value is known
9376 starting from the current insn. */
9377 if (reg_set_luid
[base_regno
] <= move2add_last_label_luid
)
9379 reg_base_reg
[base_regno
] = base_regno
;
9380 reg_offset
[base_regno
] = 0;
9381 reg_set_luid
[base_regno
] = move2add_luid
;
9382 reg_mode
[base_regno
] = mode
;
9384 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode
,
9385 reg_mode
[base_regno
]))
9388 reg_mode
[regno
] = mode
;
9390 /* Copy base information from our base register. */
9391 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
9392 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
9394 /* Compute the sum of the offsets or constants. */
9395 reg_offset
[regno
] = sext_for_mode (dst_mode
,
9397 + reg_offset
[base_regno
]);
9401 unsigned int endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
9403 for (i
= regno
; i
< endregno
; i
++)
9404 /* Reset the information about this register. */
9405 reg_set_luid
[i
] = 0;
9411 add_auto_inc_notes (insn
, x
)
9415 enum rtx_code code
= GET_CODE (x
);
9419 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9422 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
9426 /* Scan all the operand sub-expressions. */
9427 fmt
= GET_RTX_FORMAT (code
);
9428 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9431 add_auto_inc_notes (insn
, XEXP (x
, i
));
9432 else if (fmt
[i
] == 'E')
9433 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9434 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
9439 /* Copy EH notes from an insn to its reloads. */
9441 copy_eh_notes (insn
, x
)
9445 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
9448 for (; x
!= 0; x
= NEXT_INSN (x
))
9450 if (may_trap_p (PATTERN (x
)))
9452 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (eh_note
, 0),
9458 /* This is used by reload pass, that does emit some instructions after
9459 abnormal calls moving basic block end, but in fact it wants to emit
9460 them on the edge. Looks for abnormal call edges, find backward the
9461 proper call and fix the damage.
9463 Similar handle instructions throwing exceptions internally. */
9465 fixup_abnormal_edges ()
9467 bool inserted
= false;
9474 /* Look for cases we are interested in - calls or instructions causing
9476 for (e
= bb
->succ
; e
; e
= e
->succ_next
)
9478 if (e
->flags
& EDGE_ABNORMAL_CALL
)
9480 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
9481 == (EDGE_ABNORMAL
| EDGE_EH
))
9484 if (e
&& GET_CODE (bb
->end
) != CALL_INSN
&& !can_throw_internal (bb
->end
))
9486 rtx insn
= bb
->end
, stop
= NEXT_INSN (bb
->end
);
9488 for (e
= bb
->succ
; e
; e
= e
->succ_next
)
9489 if (e
->flags
& EDGE_FALLTHRU
)
9491 /* Get past the new insns generated. Allow notes, as the insns may
9492 be already deleted. */
9493 while ((GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == NOTE
)
9494 && !can_throw_internal (insn
)
9495 && insn
!= bb
->head
)
9496 insn
= PREV_INSN (insn
);
9497 if (GET_CODE (insn
) != CALL_INSN
&& !can_throw_internal (insn
))
9501 insn
= NEXT_INSN (insn
);
9502 while (insn
&& insn
!= stop
)
9504 next
= NEXT_INSN (insn
);
9509 /* Sometimes there's still the return value USE.
9510 If it's placed after a trapping call (i.e. that
9511 call is the last insn anyway), we have no fallthru
9512 edge. Simply delete this use and don't try to insert
9513 on the non-existent edge. */
9514 if (GET_CODE (PATTERN (insn
)) != USE
)
9516 /* We're not deleting it, we're moving it. */
9517 INSN_DELETED_P (insn
) = 0;
9518 PREV_INSN (insn
) = NULL_RTX
;
9519 NEXT_INSN (insn
) = NULL_RTX
;
9521 insert_insn_on_edge (insn
, e
);
9529 commit_edge_insertions ();