1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
35 #include "basic-block.h"
44 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
45 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
48 /* This file contains the reload pass of the compiler, which is
49 run after register allocation has been done. It checks that
50 each insn is valid (operands required to be in registers really
51 are in registers of the proper class) and fixes up invalid ones
52 by copying values temporarily into registers for the insns
55 The results of register allocation are described by the vector
56 reg_renumber; the insns still contain pseudo regs, but reg_renumber
57 can be used to find which hard reg, if any, a pseudo reg is in.
59 The technique we always use is to free up a few hard regs that are
60 called ``reload regs'', and for each place where a pseudo reg
61 must be in a hard reg, copy it temporarily into one of the reload regs.
63 Reload regs are allocated locally for every instruction that needs
64 reloads. When there are pseudos which are allocated to a register that
65 has been chosen as a reload reg, such pseudos must be ``spilled''.
66 This means that they go to other hard regs, or to stack slots if no other
67 available hard regs can be found. Spilling can invalidate more
68 insns, requiring additional need for reloads, so we must keep checking
69 until the process stabilizes.
71 For machines with different classes of registers, we must keep track
72 of the register class needed for each reload, and make sure that
73 we allocate enough reload registers of each class.
75 The file reload.c contains the code that checks one insn for
76 validity and reports the reloads that it needs. This file
77 is in charge of scanning the entire rtl code, accumulating the
78 reload needs, spilling, assigning reload registers to use for
79 fixing up each insn, and generating the new insns to copy values
80 into the reload registers. */
82 #ifndef REGISTER_MOVE_COST
83 #define REGISTER_MOVE_COST(m, x, y) 2
87 #define LOCAL_REGNO(REGNO) 0
90 /* During reload_as_needed, element N contains a REG rtx for the hard reg
91 into which reg N has been reloaded (perhaps for a previous insn). */
92 static rtx
*reg_last_reload_reg
;
94 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
95 for an output reload that stores into reg N. */
96 static char *reg_has_output_reload
;
98 /* Indicates which hard regs are reload-registers for an output reload
99 in the current insn. */
100 static HARD_REG_SET reg_is_output_reload
;
102 /* Element N is the constant value to which pseudo reg N is equivalent,
103 or zero if pseudo reg N is not equivalent to a constant.
104 find_reloads looks at this in order to replace pseudo reg N
105 with the constant it stands for. */
106 rtx
*reg_equiv_constant
;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx
*reg_equiv_memory_loc
;
114 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
115 This is used when the address is not valid as a memory address
116 (because its displacement is too big for the machine.) */
117 rtx
*reg_equiv_address
;
119 /* Element N is the memory slot to which pseudo reg N is equivalent,
120 or zero if pseudo reg N is not equivalent to a memory slot. */
123 /* Widest width in which each pseudo reg is referred to (via subreg). */
124 static unsigned int *reg_max_ref_width
;
126 /* Element N is the list of insns that initialized reg N from its equivalent
127 constant or memory slot. */
128 static rtx
*reg_equiv_init
;
130 /* Vector to remember old contents of reg_renumber before spilling. */
131 static short *reg_old_renumber
;
133 /* During reload_as_needed, element N contains the last pseudo regno reloaded
134 into hard register N. If that pseudo reg occupied more than one register,
135 reg_reloaded_contents points to that pseudo for each spill register in
136 use; all of these must remain set for an inheritance to occur. */
137 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
139 /* During reload_as_needed, element N contains the insn for which
140 hard register N was last used. Its contents are significant only
141 when reg_reloaded_valid is set for this register. */
142 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
144 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
145 static HARD_REG_SET reg_reloaded_valid
;
146 /* Indicate if the register was dead at the end of the reload.
147 This is only valid if reg_reloaded_contents is set and valid. */
148 static HARD_REG_SET reg_reloaded_dead
;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs
;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global
;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET
*pseudo_previous_regs
;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET
*pseudo_forbidden_regs
;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs
;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg
;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels
;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok
;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok
;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos
;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted
;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid
;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed
;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress
= 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
266 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack
;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj
;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj
;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj
;
285 #define obstack_chunk_alloc xmalloc
286 #define obstack_chunk_free free
288 /* List of insn_chain instructions, one for every insn that reload needs to
290 struct insn_chain
*reload_insn_chain
;
293 extern tree current_function_decl
;
295 extern union tree_node
*current_function_decl
;
298 /* List of all insns needing reloads. */
299 static struct insn_chain
*insns_need_reload
;
301 /* This structure is used to record information about register eliminations.
302 Each array entry describes one possible way of eliminating a register
303 in favor of another. If there is more than one way of eliminating a
304 particular register, the most preferred should be specified first. */
308 int from
; /* Register number to be eliminated. */
309 int to
; /* Register number used as replacement. */
310 int initial_offset
; /* Initial difference between values. */
311 int can_eliminate
; /* Non-zero if this elimination can be done. */
312 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
313 insns made by reload. */
314 int offset
; /* Current offset between the two regs. */
315 int previous_offset
; /* Offset at end of previous insn. */
316 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
317 rtx from_rtx
; /* REG rtx for the register to be eliminated.
318 We cannot simply compare the number since
319 we might then spuriously replace a hard
320 register corresponding to a pseudo
321 assigned to the reg to be eliminated. */
322 rtx to_rtx
; /* REG rtx for the replacement. */
325 static struct elim_table
*reg_eliminate
= 0;
327 /* This is an intermediate structure to initialize the table. It has
328 exactly the members provided by ELIMINABLE_REGS. */
329 static struct elim_table_1
333 } reg_eliminate_1
[] =
335 /* If a set of eliminable registers was specified, define the table from it.
336 Otherwise, default to the normal case of the frame pointer being
337 replaced by the stack pointer. */
339 #ifdef ELIMINABLE_REGS
342 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
345 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
347 /* Record the number of pending eliminations that have an offset not equal
348 to their initial offset. If non-zero, we use a new copy of each
349 replacement result in any insns encountered. */
350 int num_not_at_initial_offset
;
352 /* Count the number of registers that we may be able to eliminate. */
353 static int num_eliminable
;
354 /* And the number of registers that are equivalent to a constant that
355 can be eliminated to frame_pointer / arg_pointer + constant. */
356 static int num_eliminable_invariants
;
358 /* For each label, we record the offset of each elimination. If we reach
359 a label by more than one path and an offset differs, we cannot do the
360 elimination. This information is indexed by the number of the label.
361 The first table is an array of flags that records whether we have yet
362 encountered a label and the second table is an array of arrays, one
363 entry in the latter array for each elimination. */
365 static char *offsets_known_at
;
366 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
368 /* Number of labels in the current function. */
370 static int num_labels
;
372 static void replace_pseudos_in_call_usage
PARAMS((rtx
*,
375 static void maybe_fix_stack_asms
PARAMS ((void));
376 static void copy_reloads
PARAMS ((struct insn_chain
*));
377 static void calculate_needs_all_insns
PARAMS ((int));
378 static int find_reg
PARAMS ((struct insn_chain
*, int));
379 static void find_reload_regs
PARAMS ((struct insn_chain
*));
380 static void select_reload_regs
PARAMS ((void));
381 static void delete_caller_save_insns
PARAMS ((void));
383 static void spill_failure
PARAMS ((rtx
, enum reg_class
));
384 static void count_spilled_pseudo
PARAMS ((int, int, int));
385 static void delete_dead_insn
PARAMS ((rtx
));
386 static void alter_reg
PARAMS ((int, int));
387 static void set_label_offsets
PARAMS ((rtx
, rtx
, int));
388 static void check_eliminable_occurrences
PARAMS ((rtx
));
389 static void elimination_effects
PARAMS ((rtx
, enum machine_mode
));
390 static int eliminate_regs_in_insn
PARAMS ((rtx
, int));
391 static void update_eliminable_offsets
PARAMS ((void));
392 static void mark_not_eliminable
PARAMS ((rtx
, rtx
, void *));
393 static void set_initial_elim_offsets
PARAMS ((void));
394 static void verify_initial_elim_offsets
PARAMS ((void));
395 static void set_initial_label_offsets
PARAMS ((void));
396 static void set_offsets_for_label
PARAMS ((rtx
));
397 static void init_elim_table
PARAMS ((void));
398 static void update_eliminables
PARAMS ((HARD_REG_SET
*));
399 static void spill_hard_reg
PARAMS ((unsigned int, int));
400 static int finish_spills
PARAMS ((int));
401 static void ior_hard_reg_set
PARAMS ((HARD_REG_SET
*, HARD_REG_SET
*));
402 static void scan_paradoxical_subregs
PARAMS ((rtx
));
403 static void count_pseudo
PARAMS ((int));
404 static void order_regs_for_reload
PARAMS ((struct insn_chain
*));
405 static void reload_as_needed
PARAMS ((int));
406 static void forget_old_reloads_1
PARAMS ((rtx
, rtx
, void *));
407 static int reload_reg_class_lower
PARAMS ((const PTR
, const PTR
));
408 static void mark_reload_reg_in_use
PARAMS ((unsigned int, int,
411 static void clear_reload_reg_in_use
PARAMS ((unsigned int, int,
414 static int reload_reg_free_p
PARAMS ((unsigned int, int,
416 static int reload_reg_free_for_value_p
PARAMS ((int, int, int,
418 rtx
, rtx
, int, int));
419 static int free_for_value_p
PARAMS ((int, enum machine_mode
, int,
420 enum reload_type
, rtx
, rtx
,
422 static int reload_reg_reaches_end_p
PARAMS ((unsigned int, int,
424 static int allocate_reload_reg
PARAMS ((struct insn_chain
*, int,
426 static int conflicts_with_override
PARAMS ((rtx
));
427 static void failed_reload
PARAMS ((rtx
, int));
428 static int set_reload_reg
PARAMS ((int, int));
429 static void choose_reload_regs_init
PARAMS ((struct insn_chain
*, rtx
*));
430 static void choose_reload_regs
PARAMS ((struct insn_chain
*));
431 static void merge_assigned_reloads
PARAMS ((rtx
));
432 static void emit_input_reload_insns
PARAMS ((struct insn_chain
*,
433 struct reload
*, rtx
, int));
434 static void emit_output_reload_insns
PARAMS ((struct insn_chain
*,
435 struct reload
*, int));
436 static void do_input_reload
PARAMS ((struct insn_chain
*,
437 struct reload
*, int));
438 static void do_output_reload
PARAMS ((struct insn_chain
*,
439 struct reload
*, int));
440 static void emit_reload_insns
PARAMS ((struct insn_chain
*));
441 static void delete_output_reload
PARAMS ((rtx
, int, int));
442 static void delete_address_reloads
PARAMS ((rtx
, rtx
));
443 static void delete_address_reloads_1
PARAMS ((rtx
, rtx
, rtx
));
444 static rtx inc_for_reload
PARAMS ((rtx
, rtx
, rtx
, int));
445 static int constraint_accepts_reg_p
PARAMS ((const char *, rtx
));
446 static void reload_cse_regs_1
PARAMS ((rtx
));
447 static int reload_cse_noop_set_p
PARAMS ((rtx
));
448 static int reload_cse_simplify_set
PARAMS ((rtx
, rtx
));
449 static int reload_cse_simplify_operands
PARAMS ((rtx
));
450 static void reload_combine
PARAMS ((void));
451 static void reload_combine_note_use
PARAMS ((rtx
*, rtx
));
452 static void reload_combine_note_store
PARAMS ((rtx
, rtx
, void *));
453 static void reload_cse_move2add
PARAMS ((rtx
));
454 static void move2add_note_store
PARAMS ((rtx
, rtx
, void *));
456 static void add_auto_inc_notes
PARAMS ((rtx
, rtx
));
458 static void copy_eh_notes
PARAMS ((rtx
, rtx
));
459 static HOST_WIDE_INT sext_for_mode
PARAMS ((enum machine_mode
,
461 static void failed_reload
PARAMS ((rtx
, int));
462 static int set_reload_reg
PARAMS ((int, int));
463 static void reload_cse_delete_noop_set
PARAMS ((rtx
, rtx
));
464 static void reload_cse_simplify
PARAMS ((rtx
));
465 static void fixup_abnormal_edges
PARAMS ((void));
466 extern void dump_needs
PARAMS ((struct insn_chain
*));
468 /* Initialize the reload pass once per compilation. */
475 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
476 Set spill_indirect_levels to the number of levels such addressing is
477 permitted, zero if it is not permitted at all. */
480 = gen_rtx_MEM (Pmode
,
483 LAST_VIRTUAL_REGISTER
+ 1),
485 spill_indirect_levels
= 0;
487 while (memory_address_p (QImode
, tem
))
489 spill_indirect_levels
++;
490 tem
= gen_rtx_MEM (Pmode
, tem
);
493 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
495 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
496 indirect_symref_ok
= memory_address_p (QImode
, tem
);
498 /* See if reg+reg is a valid (and offsettable) address. */
500 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
502 tem
= gen_rtx_PLUS (Pmode
,
503 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
504 gen_rtx_REG (Pmode
, i
));
506 /* This way, we make sure that reg+reg is an offsettable address. */
507 tem
= plus_constant (tem
, 4);
509 if (memory_address_p (QImode
, tem
))
511 double_reg_address_ok
= 1;
516 /* Initialize obstack for our rtl allocation. */
517 gcc_obstack_init (&reload_obstack
);
518 reload_startobj
= (char *) obstack_alloc (&reload_obstack
, 0);
520 INIT_REG_SET (&spilled_pseudos
);
521 INIT_REG_SET (&pseudos_counted
);
524 /* List of insn chains that are currently unused. */
525 static struct insn_chain
*unused_insn_chains
= 0;
527 /* Allocate an empty insn_chain structure. */
531 struct insn_chain
*c
;
533 if (unused_insn_chains
== 0)
535 c
= (struct insn_chain
*)
536 obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
537 INIT_REG_SET (&c
->live_throughout
);
538 INIT_REG_SET (&c
->dead_or_set
);
542 c
= unused_insn_chains
;
543 unused_insn_chains
= c
->next
;
545 c
->is_caller_save_insn
= 0;
546 c
->need_operand_change
= 0;
552 /* Small utility function to set all regs in hard reg set TO which are
553 allocated to pseudos in regset FROM. */
556 compute_use_by_pseudos (to
, from
)
562 EXECUTE_IF_SET_IN_REG_SET
563 (from
, FIRST_PSEUDO_REGISTER
, regno
,
565 int r
= reg_renumber
[regno
];
570 /* reload_combine uses the information from
571 BASIC_BLOCK->global_live_at_start, which might still
572 contain registers that have not actually been allocated
573 since they have an equivalence. */
574 if (! reload_completed
)
579 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
581 SET_HARD_REG_BIT (*to
, r
+ nregs
);
586 /* Replace all pseudos found in LOC with their corresponding
590 replace_pseudos_in_call_usage (loc
, mem_mode
, usage
)
592 enum machine_mode mem_mode
;
606 unsigned int regno
= REGNO (x
);
608 if (regno
< FIRST_PSEUDO_REGISTER
)
611 x
= eliminate_regs (x
, mem_mode
, usage
);
615 replace_pseudos_in_call_usage (loc
, mem_mode
, usage
);
619 if (reg_equiv_constant
[regno
])
620 *loc
= reg_equiv_constant
[regno
];
621 else if (reg_equiv_mem
[regno
])
622 *loc
= reg_equiv_mem
[regno
];
623 else if (reg_equiv_address
[regno
])
624 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address
[regno
]);
625 else if (GET_CODE (regno_reg_rtx
[regno
]) != REG
626 || REGNO (regno_reg_rtx
[regno
]) != regno
)
627 *loc
= regno_reg_rtx
[regno
];
633 else if (code
== MEM
)
635 replace_pseudos_in_call_usage (& XEXP (x
, 0), GET_MODE (x
), usage
);
639 /* Process each of our operands recursively. */
640 fmt
= GET_RTX_FORMAT (code
);
641 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
643 replace_pseudos_in_call_usage (&XEXP (x
, i
), mem_mode
, usage
);
644 else if (*fmt
== 'E')
645 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
646 replace_pseudos_in_call_usage (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
650 /* Global variables used by reload and its subroutines. */
652 /* Set during calculate_needs if an insn needs register elimination. */
653 static int something_needs_elimination
;
654 /* Set during calculate_needs if an insn needs an operand changed. */
655 int something_needs_operands_changed
;
657 /* Nonzero means we couldn't get enough spill regs. */
660 /* Main entry point for the reload pass.
662 FIRST is the first insn of the function being compiled.
664 GLOBAL nonzero means we were called from global_alloc
665 and should attempt to reallocate any pseudoregs that we
666 displace from hard regs we will use for reloads.
667 If GLOBAL is zero, we do not have enough information to do that,
668 so any pseudo reg that is spilled must go to the stack.
670 Return value is nonzero if reload failed
671 and we must not do any more for this function. */
674 reload (first
, global
)
680 register struct elim_table
*ep
;
682 /* The two pointers used to track the true location of the memory used
683 for label offsets. */
684 char *real_known_ptr
= NULL
;
685 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
687 /* Make sure even insns with volatile mem refs are recognizable. */
692 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
694 /* Make sure that the last insn in the chain
695 is not something that needs reloading. */
696 emit_note (NULL
, NOTE_INSN_DELETED
);
698 /* Enable find_equiv_reg to distinguish insns made by reload. */
699 reload_first_uid
= get_max_uid ();
701 #ifdef SECONDARY_MEMORY_NEEDED
702 /* Initialize the secondary memory table. */
703 clear_secondary_mem ();
706 /* We don't have a stack slot for any spill reg yet. */
707 memset ((char *) spill_stack_slot
, 0, sizeof spill_stack_slot
);
708 memset ((char *) spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
710 /* Initialize the save area information for caller-save, in case some
714 /* Compute which hard registers are now in use
715 as homes for pseudo registers.
716 This is done here rather than (eg) in global_alloc
717 because this point is reached even if not optimizing. */
718 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
721 /* A function that receives a nonlocal goto must save all call-saved
723 if (current_function_has_nonlocal_label
)
724 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
725 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
726 regs_ever_live
[i
] = 1;
728 /* Find all the pseudo registers that didn't get hard regs
729 but do have known equivalent constants or memory slots.
730 These include parameters (known equivalent to parameter slots)
731 and cse'd or loop-moved constant memory addresses.
733 Record constant equivalents in reg_equiv_constant
734 so they will be substituted by find_reloads.
735 Record memory equivalents in reg_mem_equiv so they can
736 be substituted eventually by altering the REG-rtx's. */
738 reg_equiv_constant
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
739 reg_equiv_memory_loc
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
740 reg_equiv_mem
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
741 reg_equiv_init
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
742 reg_equiv_address
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
743 reg_max_ref_width
= (unsigned int *) xcalloc (max_regno
, sizeof (int));
744 reg_old_renumber
= (short *) xcalloc (max_regno
, sizeof (short));
745 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
746 pseudo_forbidden_regs
747 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
749 = (HARD_REG_SET
*) xcalloc (max_regno
, sizeof (HARD_REG_SET
));
751 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
753 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
754 Also find all paradoxical subregs and find largest such for each pseudo.
755 On machines with small register classes, record hard registers that
756 are used for user variables. These can never be used for spills.
757 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
758 caller-saved registers must be marked live. */
760 num_eliminable_invariants
= 0;
761 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
763 rtx set
= single_set (insn
);
765 if (GET_CODE (insn
) == NOTE
&& CONST_CALL_P (insn
)
766 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
767 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
768 if (! call_used_regs
[i
])
769 regs_ever_live
[i
] = 1;
771 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
773 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
775 #ifdef LEGITIMATE_PIC_OPERAND_P
776 && (! function_invariant_p (XEXP (note
, 0))
778 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
782 rtx x
= XEXP (note
, 0);
783 i
= REGNO (SET_DEST (set
));
784 if (i
> LAST_VIRTUAL_REGISTER
)
786 if (GET_CODE (x
) == MEM
)
788 /* If the operand is a PLUS, the MEM may be shared,
789 so make sure we have an unshared copy here. */
790 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
793 reg_equiv_memory_loc
[i
] = x
;
795 else if (function_invariant_p (x
))
797 if (GET_CODE (x
) == PLUS
)
799 /* This is PLUS of frame pointer and a constant,
800 and might be shared. Unshare it. */
801 reg_equiv_constant
[i
] = copy_rtx (x
);
802 num_eliminable_invariants
++;
804 else if (x
== frame_pointer_rtx
805 || x
== arg_pointer_rtx
)
807 reg_equiv_constant
[i
] = x
;
808 num_eliminable_invariants
++;
810 else if (LEGITIMATE_CONSTANT_P (x
))
811 reg_equiv_constant
[i
] = x
;
813 reg_equiv_memory_loc
[i
]
814 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
819 /* If this register is being made equivalent to a MEM
820 and the MEM is not SET_SRC, the equivalencing insn
821 is one with the MEM as a SET_DEST and it occurs later.
822 So don't mark this insn now. */
823 if (GET_CODE (x
) != MEM
824 || rtx_equal_p (SET_SRC (set
), x
))
826 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[i
]);
831 /* If this insn is setting a MEM from a register equivalent to it,
832 this is the equivalencing insn. */
833 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
834 && GET_CODE (SET_SRC (set
)) == REG
835 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
836 && rtx_equal_p (SET_DEST (set
),
837 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
838 reg_equiv_init
[REGNO (SET_SRC (set
))]
839 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
840 reg_equiv_init
[REGNO (SET_SRC (set
))]);
843 scan_paradoxical_subregs (PATTERN (insn
));
848 num_labels
= max_label_num () - get_first_label_num ();
850 /* Allocate the tables used to store offset information at labels. */
851 /* We used to use alloca here, but the size of what it would try to
852 allocate would occasionally cause it to exceed the stack limit and
853 cause a core dump. */
854 real_known_ptr
= xmalloc (num_labels
);
856 = (int (*)[NUM_ELIMINABLE_REGS
])
857 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
859 offsets_known_at
= real_known_ptr
- get_first_label_num ();
861 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
863 /* Alter each pseudo-reg rtx to contain its hard reg number.
864 Assign stack slots to the pseudos that lack hard regs or equivalents.
865 Do not touch virtual registers. */
867 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
870 /* If we have some registers we think can be eliminated, scan all insns to
871 see if there is an insn that sets one of these registers to something
872 other than itself plus a constant. If so, the register cannot be
873 eliminated. Doing this scan here eliminates an extra pass through the
874 main reload loop in the most common case where register elimination
876 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
877 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
878 || GET_CODE (insn
) == CALL_INSN
)
879 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
881 maybe_fix_stack_asms ();
883 insns_need_reload
= 0;
884 something_needs_elimination
= 0;
886 /* Initialize to -1, which means take the first spill register. */
889 /* Spill any hard regs that we know we can't eliminate. */
890 CLEAR_HARD_REG_SET (used_spill_regs
);
891 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
892 if (! ep
->can_eliminate
)
893 spill_hard_reg (ep
->from
, 1);
895 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
896 if (frame_pointer_needed
)
897 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
899 finish_spills (global
);
901 /* From now on, we may need to generate moves differently. We may also
902 allow modifications of insns which cause them to not be recognized.
903 Any such modifications will be cleaned up during reload itself. */
904 reload_in_progress
= 1;
906 /* This loop scans the entire function each go-round
907 and repeats until one repetition spills no additional hard regs. */
910 int something_changed
;
913 HOST_WIDE_INT starting_frame_size
;
915 /* Round size of stack frame to stack_alignment_needed. This must be done
916 here because the stack size may be a part of the offset computation
917 for register elimination, and there might have been new stack slots
918 created in the last iteration of this loop. */
919 if (cfun
->stack_alignment_needed
)
920 assign_stack_local (BLKmode
, 0, cfun
->stack_alignment_needed
);
922 starting_frame_size
= get_frame_size ();
924 set_initial_elim_offsets ();
925 set_initial_label_offsets ();
927 /* For each pseudo register that has an equivalent location defined,
928 try to eliminate any eliminable registers (such as the frame pointer)
929 assuming initial offsets for the replacement register, which
932 If the resulting location is directly addressable, substitute
933 the MEM we just got directly for the old REG.
935 If it is not addressable but is a constant or the sum of a hard reg
936 and constant, it is probably not addressable because the constant is
937 out of range, in that case record the address; we will generate
938 hairy code to compute the address in a register each time it is
939 needed. Similarly if it is a hard register, but one that is not
940 valid as an address register.
942 If the location is not addressable, but does not have one of the
943 above forms, assign a stack slot. We have to do this to avoid the
944 potential of producing lots of reloads if, e.g., a location involves
945 a pseudo that didn't get a hard register and has an equivalent memory
946 location that also involves a pseudo that didn't get a hard register.
948 Perhaps at some point we will improve reload_when_needed handling
949 so this problem goes away. But that's very hairy. */
951 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
952 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
954 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
956 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
958 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
959 else if (CONSTANT_P (XEXP (x
, 0))
960 || (GET_CODE (XEXP (x
, 0)) == REG
961 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
962 || (GET_CODE (XEXP (x
, 0)) == PLUS
963 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
964 && (REGNO (XEXP (XEXP (x
, 0), 0))
965 < FIRST_PSEUDO_REGISTER
)
966 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
967 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
970 /* Make a new stack slot. Then indicate that something
971 changed so we go back and recompute offsets for
972 eliminable registers because the allocation of memory
973 below might change some offset. reg_equiv_{mem,address}
974 will be set up for this pseudo on the next pass around
976 reg_equiv_memory_loc
[i
] = 0;
977 reg_equiv_init
[i
] = 0;
982 if (caller_save_needed
)
985 /* If we allocated another stack slot, redo elimination bookkeeping. */
986 if (starting_frame_size
!= get_frame_size ())
989 if (caller_save_needed
)
991 save_call_clobbered_regs ();
992 /* That might have allocated new insn_chain structures. */
993 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
996 calculate_needs_all_insns (global
);
998 CLEAR_REG_SET (&spilled_pseudos
);
1001 something_changed
= 0;
1003 /* If we allocated any new memory locations, make another pass
1004 since it might have changed elimination offsets. */
1005 if (starting_frame_size
!= get_frame_size ())
1006 something_changed
= 1;
1009 HARD_REG_SET to_spill
;
1010 CLEAR_HARD_REG_SET (to_spill
);
1011 update_eliminables (&to_spill
);
1012 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1013 if (TEST_HARD_REG_BIT (to_spill
, i
))
1015 spill_hard_reg (i
, 1);
1018 /* Regardless of the state of spills, if we previously had
1019 a register that we thought we could eliminate, but no can
1020 not eliminate, we must run another pass.
1022 Consider pseudos which have an entry in reg_equiv_* which
1023 reference an eliminable register. We must make another pass
1024 to update reg_equiv_* so that we do not substitute in the
1025 old value from when we thought the elimination could be
1027 something_changed
= 1;
1031 select_reload_regs ();
1035 if (insns_need_reload
!= 0 || did_spill
)
1036 something_changed
|= finish_spills (global
);
1038 if (! something_changed
)
1041 if (caller_save_needed
)
1042 delete_caller_save_insns ();
1044 obstack_free (&reload_obstack
, reload_firstobj
);
1047 /* If global-alloc was run, notify it of any register eliminations we have
1050 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1051 if (ep
->can_eliminate
)
1052 mark_elimination (ep
->from
, ep
->to
);
1054 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1055 If that insn didn't set the register (i.e., it copied the register to
1056 memory), just delete that insn instead of the equivalencing insn plus
1057 anything now dead. If we call delete_dead_insn on that insn, we may
1058 delete the insn that actually sets the register if the register dies
1059 there and that is incorrect. */
1061 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1063 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1066 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1068 rtx equiv_insn
= XEXP (list
, 0);
1069 if (GET_CODE (equiv_insn
) == NOTE
)
1071 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1072 delete_dead_insn (equiv_insn
);
1075 PUT_CODE (equiv_insn
, NOTE
);
1076 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1077 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1083 /* Use the reload registers where necessary
1084 by generating move instructions to move the must-be-register
1085 values into or out of the reload registers. */
1087 if (insns_need_reload
!= 0 || something_needs_elimination
1088 || something_needs_operands_changed
)
1090 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1092 reload_as_needed (global
);
1094 if (old_frame_size
!= get_frame_size ())
1098 verify_initial_elim_offsets ();
1101 /* If we were able to eliminate the frame pointer, show that it is no
1102 longer live at the start of any basic block. If it ls live by
1103 virtue of being in a pseudo, that pseudo will be marked live
1104 and hence the frame pointer will be known to be live via that
1107 if (! frame_pointer_needed
)
1108 for (i
= 0; i
< n_basic_blocks
; i
++)
1109 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i
)->global_live_at_start
,
1110 HARD_FRAME_POINTER_REGNUM
);
1112 /* Come here (with failure set nonzero) if we can't get enough spill regs
1113 and we decide not to abort about it. */
1116 CLEAR_REG_SET (&spilled_pseudos
);
1117 reload_in_progress
= 0;
1119 /* Now eliminate all pseudo regs by modifying them into
1120 their equivalent memory references.
1121 The REG-rtx's for the pseudos are modified in place,
1122 so all insns that used to refer to them now refer to memory.
1124 For a reg that has a reg_equiv_address, all those insns
1125 were changed by reloading so that no insns refer to it any longer;
1126 but the DECL_RTL of a variable decl may refer to it,
1127 and if so this causes the debugging info to mention the variable. */
1129 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1134 int is_readonly
= 0;
1136 if (reg_equiv_memory_loc
[i
])
1138 in_struct
= MEM_IN_STRUCT_P (reg_equiv_memory_loc
[i
]);
1139 is_scalar
= MEM_SCALAR_P (reg_equiv_memory_loc
[i
]);
1140 is_readonly
= RTX_UNCHANGING_P (reg_equiv_memory_loc
[i
]);
1143 if (reg_equiv_mem
[i
])
1144 addr
= XEXP (reg_equiv_mem
[i
], 0);
1146 if (reg_equiv_address
[i
])
1147 addr
= reg_equiv_address
[i
];
1151 if (reg_renumber
[i
] < 0)
1153 rtx reg
= regno_reg_rtx
[i
];
1154 PUT_CODE (reg
, MEM
);
1155 XEXP (reg
, 0) = addr
;
1156 REG_USERVAR_P (reg
) = 0;
1157 RTX_UNCHANGING_P (reg
) = is_readonly
;
1158 MEM_IN_STRUCT_P (reg
) = in_struct
;
1159 MEM_SCALAR_P (reg
) = is_scalar
;
1160 /* We have no alias information about this newly created
1162 set_mem_alias_set (reg
, 0);
1164 else if (reg_equiv_mem
[i
])
1165 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1169 /* We must set reload_completed now since the cleanup_subreg_operands call
1170 below will re-recognize each insn and reload may have generated insns
1171 which are only valid during and after reload. */
1172 reload_completed
= 1;
1174 /* Make a pass over all the insns and delete all USEs which we inserted
1175 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1176 notes. Delete all CLOBBER insns that don't refer to the return value
1177 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1178 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1179 and regenerate REG_INC notes that may have been moved around. */
1181 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1186 if (GET_CODE (insn
) == CALL_INSN
)
1187 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn
),
1189 CALL_INSN_FUNCTION_USAGE (insn
));
1191 if ((GET_CODE (PATTERN (insn
)) == USE
1192 && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1193 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1194 && (GET_CODE (XEXP (PATTERN (insn
), 0)) != REG
1195 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1197 PUT_CODE (insn
, NOTE
);
1198 NOTE_SOURCE_FILE (insn
) = 0;
1199 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1203 pnote
= ®_NOTES (insn
);
1206 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1207 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1208 || REG_NOTE_KIND (*pnote
) == REG_INC
1209 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1210 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1211 *pnote
= XEXP (*pnote
, 1);
1213 pnote
= &XEXP (*pnote
, 1);
1217 add_auto_inc_notes (insn
, PATTERN (insn
));
1220 /* And simplify (subreg (reg)) if it appears as an operand. */
1221 cleanup_subreg_operands (insn
);
1224 /* If we are doing stack checking, give a warning if this function's
1225 frame size is larger than we expect. */
1226 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1228 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1229 static int verbose_warned
= 0;
1231 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1232 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1233 size
+= UNITS_PER_WORD
;
1235 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1237 warning ("frame size too large for reliable stack checking");
1238 if (! verbose_warned
)
1240 warning ("try reducing the number of local variables");
1246 /* Indicate that we no longer have known memory locations or constants. */
1247 if (reg_equiv_constant
)
1248 free (reg_equiv_constant
);
1249 reg_equiv_constant
= 0;
1250 if (reg_equiv_memory_loc
)
1251 free (reg_equiv_memory_loc
);
1252 reg_equiv_memory_loc
= 0;
1255 free (real_known_ptr
);
1259 free (reg_equiv_mem
);
1260 free (reg_equiv_init
);
1261 free (reg_equiv_address
);
1262 free (reg_max_ref_width
);
1263 free (reg_old_renumber
);
1264 free (pseudo_previous_regs
);
1265 free (pseudo_forbidden_regs
);
1267 CLEAR_HARD_REG_SET (used_spill_regs
);
1268 for (i
= 0; i
< n_spills
; i
++)
1269 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1271 /* Free all the insn_chain structures at once. */
1272 obstack_free (&reload_obstack
, reload_startobj
);
1273 unused_insn_chains
= 0;
1274 fixup_abnormal_edges ();
1279 /* Yet another special case. Unfortunately, reg-stack forces people to
1280 write incorrect clobbers in asm statements. These clobbers must not
1281 cause the register to appear in bad_spill_regs, otherwise we'll call
1282 fatal_insn later. We clear the corresponding regnos in the live
1283 register sets to avoid this.
1284 The whole thing is rather sick, I'm afraid. */
1287 maybe_fix_stack_asms ()
1290 const char *constraints
[MAX_RECOG_OPERANDS
];
1291 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1292 struct insn_chain
*chain
;
1294 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1297 HARD_REG_SET clobbered
, allowed
;
1300 if (! INSN_P (chain
->insn
)
1301 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1303 pat
= PATTERN (chain
->insn
);
1304 if (GET_CODE (pat
) != PARALLEL
)
1307 CLEAR_HARD_REG_SET (clobbered
);
1308 CLEAR_HARD_REG_SET (allowed
);
1310 /* First, make a mask of all stack regs that are clobbered. */
1311 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1313 rtx t
= XVECEXP (pat
, 0, i
);
1314 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1315 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1318 /* Get the operand values and constraints out of the insn. */
1319 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1320 constraints
, operand_mode
);
1322 /* For every operand, see what registers are allowed. */
1323 for (i
= 0; i
< noperands
; i
++)
1325 const char *p
= constraints
[i
];
1326 /* For every alternative, we compute the class of registers allowed
1327 for reloading in CLS, and merge its contents into the reg set
1329 int cls
= (int) NO_REGS
;
1335 if (c
== '\0' || c
== ',' || c
== '#')
1337 /* End of one alternative - mark the regs in the current
1338 class, and reset the class. */
1339 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1344 } while (c
!= '\0' && c
!= ',');
1352 case '=': case '+': case '*': case '%': case '?': case '!':
1353 case '0': case '1': case '2': case '3': case '4': case 'm':
1354 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1355 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1356 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1361 cls
= (int) reg_class_subunion
[cls
][(int) BASE_REG_CLASS
];
1366 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1370 cls
= (int) reg_class_subunion
[cls
][(int) REG_CLASS_FROM_LETTER (c
)];
1375 /* Those of the registers which are clobbered, but allowed by the
1376 constraints, must be usable as reload registers. So clear them
1377 out of the life information. */
1378 AND_HARD_REG_SET (allowed
, clobbered
);
1379 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1380 if (TEST_HARD_REG_BIT (allowed
, i
))
1382 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1383 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1390 /* Copy the global variables n_reloads and rld into the corresponding elts
1393 copy_reloads (chain
)
1394 struct insn_chain
*chain
;
1396 chain
->n_reloads
= n_reloads
;
1398 = (struct reload
*) obstack_alloc (&reload_obstack
,
1399 n_reloads
* sizeof (struct reload
));
1400 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1401 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1404 /* Walk the chain of insns, and determine for each whether it needs reloads
1405 and/or eliminations. Build the corresponding insns_need_reload list, and
1406 set something_needs_elimination as appropriate. */
1408 calculate_needs_all_insns (global
)
1411 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1412 struct insn_chain
*chain
, *next
= 0;
1414 something_needs_elimination
= 0;
1416 reload_insn_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1417 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1419 rtx insn
= chain
->insn
;
1423 /* Clear out the shortcuts. */
1424 chain
->n_reloads
= 0;
1425 chain
->need_elim
= 0;
1426 chain
->need_reload
= 0;
1427 chain
->need_operand_change
= 0;
1429 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1430 include REG_LABEL), we need to see what effects this has on the
1431 known offsets at labels. */
1433 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1434 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1435 set_label_offsets (insn
, insn
, 0);
1439 rtx old_body
= PATTERN (insn
);
1440 int old_code
= INSN_CODE (insn
);
1441 rtx old_notes
= REG_NOTES (insn
);
1442 int did_elimination
= 0;
1443 int operands_changed
= 0;
1444 rtx set
= single_set (insn
);
1446 /* Skip insns that only set an equivalence. */
1447 if (set
&& GET_CODE (SET_DEST (set
)) == REG
1448 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1449 && reg_equiv_constant
[REGNO (SET_DEST (set
))])
1452 /* If needed, eliminate any eliminable registers. */
1453 if (num_eliminable
|| num_eliminable_invariants
)
1454 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1456 /* Analyze the instruction. */
1457 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1458 global
, spill_reg_order
);
1460 /* If a no-op set needs more than one reload, this is likely
1461 to be something that needs input address reloads. We
1462 can't get rid of this cleanly later, and it is of no use
1463 anyway, so discard it now.
1464 We only do this when expensive_optimizations is enabled,
1465 since this complements reload inheritance / output
1466 reload deletion, and it can make debugging harder. */
1467 if (flag_expensive_optimizations
&& n_reloads
> 1)
1469 rtx set
= single_set (insn
);
1471 && SET_SRC (set
) == SET_DEST (set
)
1472 && GET_CODE (SET_SRC (set
)) == REG
1473 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1475 PUT_CODE (insn
, NOTE
);
1476 NOTE_SOURCE_FILE (insn
) = 0;
1477 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1478 /* Delete it from the reload chain */
1480 chain
->prev
->next
= next
;
1482 reload_insn_chain
= next
;
1484 next
->prev
= chain
->prev
;
1485 chain
->next
= unused_insn_chains
;
1486 unused_insn_chains
= chain
;
1491 update_eliminable_offsets ();
1493 /* Remember for later shortcuts which insns had any reloads or
1494 register eliminations. */
1495 chain
->need_elim
= did_elimination
;
1496 chain
->need_reload
= n_reloads
> 0;
1497 chain
->need_operand_change
= operands_changed
;
1499 /* Discard any register replacements done. */
1500 if (did_elimination
)
1502 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1503 PATTERN (insn
) = old_body
;
1504 INSN_CODE (insn
) = old_code
;
1505 REG_NOTES (insn
) = old_notes
;
1506 something_needs_elimination
= 1;
1509 something_needs_operands_changed
|= operands_changed
;
1513 copy_reloads (chain
);
1514 *pprev_reload
= chain
;
1515 pprev_reload
= &chain
->next_need_reload
;
1522 /* Comparison function for qsort to decide which of two reloads
1523 should be handled first. *P1 and *P2 are the reload numbers. */
1526 reload_reg_class_lower (r1p
, r2p
)
1530 register int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1533 /* Consider required reloads before optional ones. */
1534 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1538 /* Count all solitary classes before non-solitary ones. */
1539 t
= ((reg_class_size
[(int) rld
[r2
].class] == 1)
1540 - (reg_class_size
[(int) rld
[r1
].class] == 1));
1544 /* Aside from solitaires, consider all multi-reg groups first. */
1545 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1549 /* Consider reloads in order of increasing reg-class number. */
1550 t
= (int) rld
[r1
].class - (int) rld
[r2
].class;
1554 /* If reloads are equally urgent, sort by reload number,
1555 so that the results of qsort leave nothing to chance. */
1559 /* The cost of spilling each hard reg. */
1560 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1562 /* When spilling multiple hard registers, we use SPILL_COST for the first
1563 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1564 only the first hard reg for a multi-reg pseudo. */
1565 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1567 /* Update the spill cost arrays, considering that pseudo REG is live. */
1573 int freq
= REG_FREQ (reg
);
1574 int r
= reg_renumber
[reg
];
1577 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1578 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1581 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1586 spill_add_cost
[r
] += freq
;
1588 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1590 spill_cost
[r
+ nregs
] += freq
;
1593 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1594 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1597 order_regs_for_reload (chain
)
1598 struct insn_chain
*chain
;
1601 HARD_REG_SET used_by_pseudos
;
1602 HARD_REG_SET used_by_pseudos2
;
1604 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1606 memset (spill_cost
, 0, sizeof spill_cost
);
1607 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1609 /* Count number of uses of each hard reg by pseudo regs allocated to it
1610 and then order them by decreasing use. First exclude hard registers
1611 that are live in or across this insn. */
1613 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1614 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1615 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1616 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1618 /* Now find out which pseudos are allocated to it, and update
1620 CLEAR_REG_SET (&pseudos_counted
);
1622 EXECUTE_IF_SET_IN_REG_SET
1623 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
1627 EXECUTE_IF_SET_IN_REG_SET
1628 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
1632 CLEAR_REG_SET (&pseudos_counted
);
1635 /* Vector of reload-numbers showing the order in which the reloads should
1637 static short reload_order
[MAX_RELOADS
];
1639 /* This is used to keep track of the spill regs used in one insn. */
1640 static HARD_REG_SET used_spill_regs_local
;
1642 /* We decided to spill hard register SPILLED, which has a size of
1643 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1644 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1645 update SPILL_COST/SPILL_ADD_COST. */
1648 count_spilled_pseudo (spilled
, spilled_nregs
, reg
)
1649 int spilled
, spilled_nregs
, reg
;
1651 int r
= reg_renumber
[reg
];
1652 int nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1654 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1655 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1658 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1660 spill_add_cost
[r
] -= REG_FREQ (reg
);
1662 spill_cost
[r
+ nregs
] -= REG_FREQ (reg
);
1665 /* Find reload register to use for reload number ORDER. */
1668 find_reg (chain
, order
)
1669 struct insn_chain
*chain
;
1672 int rnum
= reload_order
[order
];
1673 struct reload
*rl
= rld
+ rnum
;
1674 int best_cost
= INT_MAX
;
1678 HARD_REG_SET not_usable
;
1679 HARD_REG_SET used_by_other_reload
;
1681 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1682 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1683 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->class]);
1685 CLEAR_HARD_REG_SET (used_by_other_reload
);
1686 for (k
= 0; k
< order
; k
++)
1688 int other
= reload_order
[k
];
1690 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1691 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1692 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1695 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1697 unsigned int regno
= i
;
1699 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1700 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1701 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1703 int this_cost
= spill_cost
[regno
];
1705 unsigned int this_nregs
= HARD_REGNO_NREGS (regno
, rl
->mode
);
1707 for (j
= 1; j
< this_nregs
; j
++)
1709 this_cost
+= spill_add_cost
[regno
+ j
];
1710 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1711 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1716 if (rl
->in
&& GET_CODE (rl
->in
) == REG
&& REGNO (rl
->in
) == regno
)
1718 if (rl
->out
&& GET_CODE (rl
->out
) == REG
&& REGNO (rl
->out
) == regno
)
1720 if (this_cost
< best_cost
1721 /* Among registers with equal cost, prefer caller-saved ones, or
1722 use REG_ALLOC_ORDER if it is defined. */
1723 || (this_cost
== best_cost
1724 #ifdef REG_ALLOC_ORDER
1725 && (inv_reg_alloc_order
[regno
]
1726 < inv_reg_alloc_order
[best_reg
])
1728 && call_used_regs
[regno
]
1729 && ! call_used_regs
[best_reg
]
1734 best_cost
= this_cost
;
1742 fprintf (rtl_dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1744 rl
->nregs
= HARD_REGNO_NREGS (best_reg
, rl
->mode
);
1745 rl
->regno
= best_reg
;
1747 EXECUTE_IF_SET_IN_REG_SET
1748 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
,
1750 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1753 EXECUTE_IF_SET_IN_REG_SET
1754 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
,
1756 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1759 for (i
= 0; i
< rl
->nregs
; i
++)
1761 if (spill_cost
[best_reg
+ i
] != 0
1762 || spill_add_cost
[best_reg
+ i
] != 0)
1764 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1769 /* Find more reload regs to satisfy the remaining need of an insn, which
1771 Do it by ascending class number, since otherwise a reg
1772 might be spilled for a big class and might fail to count
1773 for a smaller class even though it belongs to that class. */
1776 find_reload_regs (chain
)
1777 struct insn_chain
*chain
;
1781 /* In order to be certain of getting the registers we need,
1782 we must sort the reloads into order of increasing register class.
1783 Then our grabbing of reload registers will parallel the process
1784 that provided the reload registers. */
1785 for (i
= 0; i
< chain
->n_reloads
; i
++)
1787 /* Show whether this reload already has a hard reg. */
1788 if (chain
->rld
[i
].reg_rtx
)
1790 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1791 chain
->rld
[i
].regno
= regno
;
1793 = HARD_REGNO_NREGS (regno
, GET_MODE (chain
->rld
[i
].reg_rtx
));
1796 chain
->rld
[i
].regno
= -1;
1797 reload_order
[i
] = i
;
1800 n_reloads
= chain
->n_reloads
;
1801 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1803 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1806 fprintf (rtl_dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1808 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1810 /* Compute the order of preference for hard registers to spill. */
1812 order_regs_for_reload (chain
);
1814 for (i
= 0; i
< n_reloads
; i
++)
1816 int r
= reload_order
[i
];
1818 /* Ignore reloads that got marked inoperative. */
1819 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1820 && ! rld
[r
].optional
1821 && rld
[r
].regno
== -1)
1822 if (! find_reg (chain
, i
))
1824 spill_failure (chain
->insn
, rld
[r
].class);
1830 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
1831 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
1833 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1837 select_reload_regs ()
1839 struct insn_chain
*chain
;
1841 /* Try to satisfy the needs for each insn. */
1842 for (chain
= insns_need_reload
; chain
!= 0;
1843 chain
= chain
->next_need_reload
)
1844 find_reload_regs (chain
);
1847 /* Delete all insns that were inserted by emit_caller_save_insns during
1850 delete_caller_save_insns ()
1852 struct insn_chain
*c
= reload_insn_chain
;
1856 while (c
!= 0 && c
->is_caller_save_insn
)
1858 struct insn_chain
*next
= c
->next
;
1861 if (insn
== BLOCK_HEAD (c
->block
))
1862 BLOCK_HEAD (c
->block
) = NEXT_INSN (insn
);
1863 if (insn
== BLOCK_END (c
->block
))
1864 BLOCK_END (c
->block
) = PREV_INSN (insn
);
1865 if (c
== reload_insn_chain
)
1866 reload_insn_chain
= next
;
1868 if (NEXT_INSN (insn
) != 0)
1869 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1870 if (PREV_INSN (insn
) != 0)
1871 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1874 next
->prev
= c
->prev
;
1876 c
->prev
->next
= next
;
1877 c
->next
= unused_insn_chains
;
1878 unused_insn_chains
= c
;
1886 /* Handle the failure to find a register to spill.
1887 INSN should be one of the insns which needed this particular spill reg. */
1890 spill_failure (insn
, class)
1892 enum reg_class
class;
1894 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1895 if (asm_noperands (PATTERN (insn
)) >= 0)
1896 error_for_asm (insn
, "Can't find a register in class `%s' while reloading `asm'.",
1897 reg_class_names
[class]);
1900 error ("Unable to find a register to spill in class `%s'.",
1901 reg_class_names
[class]);
1902 fatal_insn ("This is the insn:", insn
);
1906 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1907 data that is dead in INSN. */
1910 delete_dead_insn (insn
)
1913 rtx prev
= prev_real_insn (insn
);
1916 /* If the previous insn sets a register that dies in our insn, delete it
1918 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
1919 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
1920 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
1921 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
1922 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
1923 delete_dead_insn (prev
);
1925 PUT_CODE (insn
, NOTE
);
1926 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1927 NOTE_SOURCE_FILE (insn
) = 0;
1930 /* Modify the home of pseudo-reg I.
1931 The new home is present in reg_renumber[I].
1933 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1934 or it may be -1, meaning there is none or it is not relevant.
1935 This is used so that all pseudos spilled from a given hard reg
1936 can share one stack slot. */
1939 alter_reg (i
, from_reg
)
1943 /* When outputting an inline function, this can happen
1944 for a reg that isn't actually used. */
1945 if (regno_reg_rtx
[i
] == 0)
1948 /* If the reg got changed to a MEM at rtl-generation time,
1950 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
1953 /* Modify the reg-rtx to contain the new hard reg
1954 number or else to contain its pseudo reg number. */
1955 REGNO (regno_reg_rtx
[i
])
1956 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
1958 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1959 allocate a stack slot for it. */
1961 if (reg_renumber
[i
] < 0
1962 && REG_N_REFS (i
) > 0
1963 && reg_equiv_constant
[i
] == 0
1964 && reg_equiv_memory_loc
[i
] == 0)
1967 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
1968 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
1971 /* Each pseudo reg has an inherent size which comes from its own mode,
1972 and a total size which provides room for paradoxical subregs
1973 which refer to the pseudo reg in wider modes.
1975 We can use a slot already allocated if it provides both
1976 enough inherent space and enough total space.
1977 Otherwise, we allocate a new slot, making sure that it has no less
1978 inherent space, and no less total space, then the previous slot. */
1981 /* No known place to spill from => no slot to reuse. */
1982 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
1983 inherent_size
== total_size
? 0 : -1);
1984 if (BYTES_BIG_ENDIAN
)
1985 /* Cancel the big-endian correction done in assign_stack_local.
1986 Get the address of the beginning of the slot.
1987 This is so we can do a big-endian correction unconditionally
1989 adjust
= inherent_size
- total_size
;
1991 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
1993 /* Nothing can alias this slot except this pseudo. */
1994 set_mem_alias_set (x
, new_alias_set ());
1997 /* Reuse a stack slot if possible. */
1998 else if (spill_stack_slot
[from_reg
] != 0
1999 && spill_stack_slot_width
[from_reg
] >= total_size
2000 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2002 x
= spill_stack_slot
[from_reg
];
2004 /* Allocate a bigger slot. */
2007 /* Compute maximum size needed, both for inherent size
2008 and for total size. */
2009 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2012 if (spill_stack_slot
[from_reg
])
2014 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2016 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2017 if (spill_stack_slot_width
[from_reg
] > total_size
)
2018 total_size
= spill_stack_slot_width
[from_reg
];
2021 /* Make a slot with that size. */
2022 x
= assign_stack_local (mode
, total_size
,
2023 inherent_size
== total_size
? 0 : -1);
2026 /* All pseudos mapped to this slot can alias each other. */
2027 if (spill_stack_slot
[from_reg
])
2028 set_mem_alias_set (x
, MEM_ALIAS_SET (spill_stack_slot
[from_reg
]));
2030 set_mem_alias_set (x
, new_alias_set ());
2032 if (BYTES_BIG_ENDIAN
)
2034 /* Cancel the big-endian correction done in assign_stack_local.
2035 Get the address of the beginning of the slot.
2036 This is so we can do a big-endian correction unconditionally
2038 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2040 stack_slot
= gen_rtx_MEM (mode_for_size (total_size
2043 plus_constant (XEXP (x
, 0), adjust
));
2046 spill_stack_slot
[from_reg
] = stack_slot
;
2047 spill_stack_slot_width
[from_reg
] = total_size
;
2050 /* On a big endian machine, the "address" of the slot
2051 is the address of the low part that fits its inherent mode. */
2052 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2053 adjust
+= (total_size
- inherent_size
);
2055 /* If we have any adjustment to make, or if the stack slot is the
2056 wrong mode, make a new stack slot. */
2057 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
2058 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2060 /* Save the stack slot for later. */
2061 reg_equiv_memory_loc
[i
] = x
;
2065 /* Mark the slots in regs_ever_live for the hard regs
2066 used by pseudo-reg number REGNO. */
2069 mark_home_live (regno
)
2072 register int i
, lim
;
2074 i
= reg_renumber
[regno
];
2077 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2079 regs_ever_live
[i
++] = 1;
2082 /* This function handles the tracking of elimination offsets around branches.
2084 X is a piece of RTL being scanned.
2086 INSN is the insn that it came from, if any.
2088 INITIAL_P is non-zero if we are to set the offset to be the initial
2089 offset and zero if we are setting the offset of the label to be the
2093 set_label_offsets (x
, insn
, initial_p
)
2098 enum rtx_code code
= GET_CODE (x
);
2101 struct elim_table
*p
;
2106 if (LABEL_REF_NONLOCAL_P (x
))
2111 /* ... fall through ... */
2114 /* If we know nothing about this label, set the desired offsets. Note
2115 that this sets the offset at a label to be the offset before a label
2116 if we don't know anything about the label. This is not correct for
2117 the label after a BARRIER, but is the best guess we can make. If
2118 we guessed wrong, we will suppress an elimination that might have
2119 been possible had we been able to guess correctly. */
2121 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2123 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2124 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2125 = (initial_p
? reg_eliminate
[i
].initial_offset
2126 : reg_eliminate
[i
].offset
);
2127 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2130 /* Otherwise, if this is the definition of a label and it is
2131 preceded by a BARRIER, set our offsets to the known offset of
2135 && (tem
= prev_nonnote_insn (insn
)) != 0
2136 && GET_CODE (tem
) == BARRIER
)
2137 set_offsets_for_label (insn
);
2139 /* If neither of the above cases is true, compare each offset
2140 with those previously recorded and suppress any eliminations
2141 where the offsets disagree. */
2143 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2144 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2145 != (initial_p
? reg_eliminate
[i
].initial_offset
2146 : reg_eliminate
[i
].offset
))
2147 reg_eliminate
[i
].can_eliminate
= 0;
2152 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2154 /* ... fall through ... */
2158 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2159 and hence must have all eliminations at their initial offsets. */
2160 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2161 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2162 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2168 /* Each of the labels in the parallel or address vector must be
2169 at their initial offsets. We want the first field for PARALLEL
2170 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2172 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2173 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2178 /* We only care about setting PC. If the source is not RETURN,
2179 IF_THEN_ELSE, or a label, disable any eliminations not at
2180 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2181 isn't one of those possibilities. For branches to a label,
2182 call ourselves recursively.
2184 Note that this can disable elimination unnecessarily when we have
2185 a non-local goto since it will look like a non-constant jump to
2186 someplace in the current function. This isn't a significant
2187 problem since such jumps will normally be when all elimination
2188 pairs are back to their initial offsets. */
2190 if (SET_DEST (x
) != pc_rtx
)
2193 switch (GET_CODE (SET_SRC (x
)))
2200 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2204 tem
= XEXP (SET_SRC (x
), 1);
2205 if (GET_CODE (tem
) == LABEL_REF
)
2206 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2207 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2210 tem
= XEXP (SET_SRC (x
), 2);
2211 if (GET_CODE (tem
) == LABEL_REF
)
2212 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2213 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2221 /* If we reach here, all eliminations must be at their initial
2222 offset because we are doing a jump to a variable address. */
2223 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2224 if (p
->offset
!= p
->initial_offset
)
2225 p
->can_eliminate
= 0;
2233 /* Scan X and replace any eliminable registers (such as fp) with a
2234 replacement (such as sp), plus an offset.
2236 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2237 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2238 MEM, we are allowed to replace a sum of a register and the constant zero
2239 with the register, which we cannot do outside a MEM. In addition, we need
2240 to record the fact that a register is referenced outside a MEM.
2242 If INSN is an insn, it is the insn containing X. If we replace a REG
2243 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2244 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2245 the REG is being modified.
2247 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2248 That's used when we eliminate in expressions stored in notes.
2249 This means, do not set ref_outside_mem even if the reference
2252 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2253 replacements done assuming all offsets are at their initial values. If
2254 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2255 encounter, return the actual location so that find_reloads will do
2256 the proper thing. */
2259 eliminate_regs (x
, mem_mode
, insn
)
2261 enum machine_mode mem_mode
;
2264 enum rtx_code code
= GET_CODE (x
);
2265 struct elim_table
*ep
;
2272 if (! current_function_decl
)
2291 /* This is only for the benefit of the debugging backends, which call
2292 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2293 removed after CSE. */
2294 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2295 if (GET_CODE (new) == MEM
)
2296 return XEXP (new, 0);
2302 /* First handle the case where we encounter a bare register that
2303 is eliminable. Replace it with a PLUS. */
2304 if (regno
< FIRST_PSEUDO_REGISTER
)
2306 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2308 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2309 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2312 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2313 && reg_equiv_constant
[regno
]
2314 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2315 return eliminate_regs (copy_rtx (reg_equiv_constant
[regno
]),
2319 /* You might think handling MINUS in a manner similar to PLUS is a
2320 good idea. It is not. It has been tried multiple times and every
2321 time the change has had to have been reverted.
2323 Other parts of reload know a PLUS is special (gen_reload for example)
2324 and require special code to handle code a reloaded PLUS operand.
2326 Also consider backends where the flags register is clobbered by a
2327 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2328 lea instruction comes to mind). If we try to reload a MINUS, we
2329 may kill the flags register that was holding a useful value.
2331 So, please before trying to handle MINUS, consider reload as a
2332 whole instead of this little section as well as the backend issues. */
2334 /* If this is the sum of an eliminable register and a constant, rework
2336 if (GET_CODE (XEXP (x
, 0)) == REG
2337 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2338 && CONSTANT_P (XEXP (x
, 1)))
2340 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2342 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2344 /* The only time we want to replace a PLUS with a REG (this
2345 occurs when the constant operand of the PLUS is the negative
2346 of the offset) is when we are inside a MEM. We won't want
2347 to do so at other times because that would change the
2348 structure of the insn in a way that reload can't handle.
2349 We special-case the commonest situation in
2350 eliminate_regs_in_insn, so just replace a PLUS with a
2351 PLUS here, unless inside a MEM. */
2352 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2353 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2356 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2357 plus_constant (XEXP (x
, 1),
2358 ep
->previous_offset
));
2361 /* If the register is not eliminable, we are done since the other
2362 operand is a constant. */
2366 /* If this is part of an address, we want to bring any constant to the
2367 outermost PLUS. We will do this by doing register replacement in
2368 our operands and seeing if a constant shows up in one of them.
2370 Note that there is no risk of modifying the structure of the insn,
2371 since we only get called for its operands, thus we are either
2372 modifying the address inside a MEM, or something like an address
2373 operand of a load-address insn. */
2376 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2377 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2379 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2381 /* If one side is a PLUS and the other side is a pseudo that
2382 didn't get a hard register but has a reg_equiv_constant,
2383 we must replace the constant here since it may no longer
2384 be in the position of any operand. */
2385 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2386 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2387 && reg_renumber
[REGNO (new1
)] < 0
2388 && reg_equiv_constant
!= 0
2389 && reg_equiv_constant
[REGNO (new1
)] != 0)
2390 new1
= reg_equiv_constant
[REGNO (new1
)];
2391 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2392 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2393 && reg_renumber
[REGNO (new0
)] < 0
2394 && reg_equiv_constant
[REGNO (new0
)] != 0)
2395 new0
= reg_equiv_constant
[REGNO (new0
)];
2397 new = form_sum (new0
, new1
);
2399 /* As above, if we are not inside a MEM we do not want to
2400 turn a PLUS into something else. We might try to do so here
2401 for an addition of 0 if we aren't optimizing. */
2402 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2403 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2411 /* If this is the product of an eliminable register and a
2412 constant, apply the distribute law and move the constant out
2413 so that we have (plus (mult ..) ..). This is needed in order
2414 to keep load-address insns valid. This case is pathological.
2415 We ignore the possibility of overflow here. */
2416 if (GET_CODE (XEXP (x
, 0)) == REG
2417 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2418 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2419 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2421 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2424 /* Refs inside notes don't count for this purpose. */
2425 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2426 || GET_CODE (insn
) == INSN_LIST
)))
2427 ep
->ref_outside_mem
= 1;
2430 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2431 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2434 /* ... fall through ... */
2438 /* See comments before PLUS about handling MINUS. */
2440 case DIV
: case UDIV
:
2441 case MOD
: case UMOD
:
2442 case AND
: case IOR
: case XOR
:
2443 case ROTATERT
: case ROTATE
:
2444 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2446 case GE
: case GT
: case GEU
: case GTU
:
2447 case LE
: case LT
: case LEU
: case LTU
:
2449 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2451 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2453 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2454 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2459 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2462 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2463 if (new != XEXP (x
, 0))
2465 /* If this is a REG_DEAD note, it is not valid anymore.
2466 Using the eliminated version could result in creating a
2467 REG_DEAD note for the stack or frame pointer. */
2468 if (GET_MODE (x
) == REG_DEAD
)
2470 ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
)
2473 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2477 /* ... fall through ... */
2480 /* Now do eliminations in the rest of the chain. If this was
2481 an EXPR_LIST, this might result in allocating more memory than is
2482 strictly needed, but it simplifies the code. */
2485 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2486 if (new != XEXP (x
, 1))
2487 return gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2495 case STRICT_LOW_PART
:
2497 case SIGN_EXTEND
: case ZERO_EXTEND
:
2498 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2499 case FLOAT
: case FIX
:
2500 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2504 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2505 if (new != XEXP (x
, 0))
2506 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2510 /* Similar to above processing, but preserve SUBREG_BYTE.
2511 Convert (subreg (mem)) to (mem) if not paradoxical.
2512 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2513 pseudo didn't get a hard reg, we must replace this with the
2514 eliminated version of the memory location because push_reloads
2515 may do the replacement in certain circumstances. */
2516 if (GET_CODE (SUBREG_REG (x
)) == REG
2517 && (GET_MODE_SIZE (GET_MODE (x
))
2518 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2519 && reg_equiv_memory_loc
!= 0
2520 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2522 new = SUBREG_REG (x
);
2525 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
2527 if (new != SUBREG_REG (x
))
2529 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2530 int new_size
= GET_MODE_SIZE (GET_MODE (new));
2532 if (GET_CODE (new) == MEM
2533 && ((x_size
< new_size
2534 #ifdef WORD_REGISTER_OPERATIONS
2535 /* On these machines, combine can create rtl of the form
2536 (set (subreg:m1 (reg:m2 R) 0) ...)
2537 where m1 < m2, and expects something interesting to
2538 happen to the entire word. Moreover, it will use the
2539 (reg:m2 R) later, expecting all bits to be preserved.
2540 So if the number of words is the same, preserve the
2541 subreg so that push_reloads can see it. */
2542 && ! ((x_size
- 1) / UNITS_PER_WORD
2543 == (new_size
-1 ) / UNITS_PER_WORD
)
2546 || x_size
== new_size
)
2549 int offset
= SUBREG_BYTE (x
);
2550 enum machine_mode mode
= GET_MODE (x
);
2552 PUT_MODE (new, mode
);
2553 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
2557 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_BYTE (x
));
2563 /* This is only for the benefit of the debugging backends, which call
2564 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2565 removed after CSE. */
2566 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2567 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
2569 /* Our only special processing is to pass the mode of the MEM to our
2570 recursive call and copy the flags. While we are here, handle this
2571 case more efficiently. */
2573 replace_equiv_address_nv (x
,
2574 eliminate_regs (XEXP (x
, 0),
2575 GET_MODE (x
), insn
));
2578 /* Handle insn_list USE that a call to a pure function may generate. */
2579 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2580 if (new != XEXP (x
, 0))
2581 return gen_rtx_USE (GET_MODE (x
), new);
2593 /* Process each of our operands recursively. If any have changed, make a
2595 fmt
= GET_RTX_FORMAT (code
);
2596 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2600 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
2601 if (new != XEXP (x
, i
) && ! copied
)
2603 rtx new_x
= rtx_alloc (code
);
2605 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2606 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
2612 else if (*fmt
== 'E')
2615 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2617 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
2618 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
2620 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2624 rtx new_x
= rtx_alloc (code
);
2626 (sizeof (*new_x
) - sizeof (new_x
->fld
)
2627 + (sizeof (new_x
->fld
[0])
2628 * GET_RTX_LENGTH (code
))));
2632 XVEC (x
, i
) = new_v
;
2635 XVECEXP (x
, i
, j
) = new;
2643 /* Scan rtx X for modifications of elimination target registers. Update
2644 the table of eliminables to reflect the changed state. MEM_MODE is
2645 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2648 elimination_effects (x
, mem_mode
)
2650 enum machine_mode mem_mode
;
2653 enum rtx_code code
= GET_CODE (x
);
2654 struct elim_table
*ep
;
2680 /* First handle the case where we encounter a bare register that
2681 is eliminable. Replace it with a PLUS. */
2682 if (regno
< FIRST_PSEUDO_REGISTER
)
2684 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2686 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2689 ep
->ref_outside_mem
= 1;
2694 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2695 && reg_equiv_constant
[regno
]
2696 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2697 elimination_effects (reg_equiv_constant
[regno
], mem_mode
);
2706 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2707 if (ep
->to_rtx
== XEXP (x
, 0))
2709 int size
= GET_MODE_SIZE (mem_mode
);
2711 /* If more bytes than MEM_MODE are pushed, account for them. */
2712 #ifdef PUSH_ROUNDING
2713 if (ep
->to_rtx
== stack_pointer_rtx
)
2714 size
= PUSH_ROUNDING (size
);
2716 if (code
== PRE_DEC
|| code
== POST_DEC
)
2718 else if (code
== PRE_INC
|| code
== POST_INC
)
2720 else if ((code
== PRE_MODIFY
|| code
== POST_MODIFY
)
2721 && GET_CODE (XEXP (x
, 1)) == PLUS
2722 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
2723 && CONSTANT_P (XEXP (XEXP (x
, 1), 1)))
2724 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
2727 /* These two aren't unary operators. */
2728 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
2731 /* Fall through to generic unary operation case. */
2732 case STRICT_LOW_PART
:
2734 case SIGN_EXTEND
: case ZERO_EXTEND
:
2735 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2736 case FLOAT
: case FIX
:
2737 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2741 elimination_effects (XEXP (x
, 0), mem_mode
);
2745 if (GET_CODE (SUBREG_REG (x
)) == REG
2746 && (GET_MODE_SIZE (GET_MODE (x
))
2747 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2748 && reg_equiv_memory_loc
!= 0
2749 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2752 elimination_effects (SUBREG_REG (x
), mem_mode
);
2756 /* If using a register that is the source of an eliminate we still
2757 think can be performed, note it cannot be performed since we don't
2758 know how this register is used. */
2759 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2760 if (ep
->from_rtx
== XEXP (x
, 0))
2761 ep
->can_eliminate
= 0;
2763 elimination_effects (XEXP (x
, 0), mem_mode
);
2767 /* If clobbering a register that is the replacement register for an
2768 elimination we still think can be performed, note that it cannot
2769 be performed. Otherwise, we need not be concerned about it. */
2770 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2771 if (ep
->to_rtx
== XEXP (x
, 0))
2772 ep
->can_eliminate
= 0;
2774 elimination_effects (XEXP (x
, 0), mem_mode
);
2778 /* Check for setting a register that we know about. */
2779 if (GET_CODE (SET_DEST (x
)) == REG
)
2781 /* See if this is setting the replacement register for an
2784 If DEST is the hard frame pointer, we do nothing because we
2785 assume that all assignments to the frame pointer are for
2786 non-local gotos and are being done at a time when they are valid
2787 and do not disturb anything else. Some machines want to
2788 eliminate a fake argument pointer (or even a fake frame pointer)
2789 with either the real frame or the stack pointer. Assignments to
2790 the hard frame pointer must not prevent this elimination. */
2792 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2794 if (ep
->to_rtx
== SET_DEST (x
)
2795 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2797 /* If it is being incremented, adjust the offset. Otherwise,
2798 this elimination can't be done. */
2799 rtx src
= SET_SRC (x
);
2801 if (GET_CODE (src
) == PLUS
2802 && XEXP (src
, 0) == SET_DEST (x
)
2803 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2804 ep
->offset
-= INTVAL (XEXP (src
, 1));
2806 ep
->can_eliminate
= 0;
2810 elimination_effects (SET_DEST (x
), 0);
2811 elimination_effects (SET_SRC (x
), 0);
2815 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
2818 /* Our only special processing is to pass the mode of the MEM to our
2820 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
2827 fmt
= GET_RTX_FORMAT (code
);
2828 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2831 elimination_effects (XEXP (x
, i
), mem_mode
);
2832 else if (*fmt
== 'E')
2833 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2834 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
2838 /* Descend through rtx X and verify that no references to eliminable registers
2839 remain. If any do remain, mark the involved register as not
2843 check_eliminable_occurrences (x
)
2853 code
= GET_CODE (x
);
2855 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
2857 struct elim_table
*ep
;
2859 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2860 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2861 ep
->can_eliminate
= 0;
2865 fmt
= GET_RTX_FORMAT (code
);
2866 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2869 check_eliminable_occurrences (XEXP (x
, i
));
2870 else if (*fmt
== 'E')
2873 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2874 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
2879 /* Scan INSN and eliminate all eliminable registers in it.
2881 If REPLACE is nonzero, do the replacement destructively. Also
2882 delete the insn as dead it if it is setting an eliminable register.
2884 If REPLACE is zero, do all our allocations in reload_obstack.
2886 If no eliminations were done and this insn doesn't require any elimination
2887 processing (these are not identical conditions: it might be updating sp,
2888 but not referencing fp; this needs to be seen during reload_as_needed so
2889 that the offset between fp and sp can be taken into consideration), zero
2890 is returned. Otherwise, 1 is returned. */
2893 eliminate_regs_in_insn (insn
, replace
)
2897 int icode
= recog_memoized (insn
);
2898 rtx old_body
= PATTERN (insn
);
2899 int insn_is_asm
= asm_noperands (old_body
) >= 0;
2900 rtx old_set
= single_set (insn
);
2904 rtx substed_operand
[MAX_RECOG_OPERANDS
];
2905 rtx orig_operand
[MAX_RECOG_OPERANDS
];
2906 struct elim_table
*ep
;
2908 if (! insn_is_asm
&& icode
< 0)
2910 if (GET_CODE (PATTERN (insn
)) == USE
2911 || GET_CODE (PATTERN (insn
)) == CLOBBER
2912 || GET_CODE (PATTERN (insn
)) == ADDR_VEC
2913 || GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
2914 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
)
2919 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
2920 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
2922 /* Check for setting an eliminable register. */
2923 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2924 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
2926 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2927 /* If this is setting the frame pointer register to the
2928 hardware frame pointer register and this is an elimination
2929 that will be done (tested above), this insn is really
2930 adjusting the frame pointer downward to compensate for
2931 the adjustment done before a nonlocal goto. */
2932 if (ep
->from
== FRAME_POINTER_REGNUM
2933 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
2935 rtx src
= SET_SRC (old_set
);
2936 int offset
= 0, ok
= 0;
2937 rtx prev_insn
, prev_set
;
2939 if (src
== ep
->to_rtx
)
2941 else if (GET_CODE (src
) == PLUS
2942 && GET_CODE (XEXP (src
, 0)) == CONST_INT
2943 && XEXP (src
, 1) == ep
->to_rtx
)
2944 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
2945 else if (GET_CODE (src
) == PLUS
2946 && GET_CODE (XEXP (src
, 1)) == CONST_INT
2947 && XEXP (src
, 0) == ep
->to_rtx
)
2948 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
2949 else if ((prev_insn
= prev_nonnote_insn (insn
)) != 0
2950 && (prev_set
= single_set (prev_insn
)) != 0
2951 && rtx_equal_p (SET_DEST (prev_set
), src
))
2953 src
= SET_SRC (prev_set
);
2954 if (src
== ep
->to_rtx
)
2956 else if (GET_CODE (src
) == PLUS
2957 && GET_CODE (XEXP (src
, 0)) == CONST_INT
2958 && XEXP (src
, 1) == ep
->to_rtx
)
2959 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
2960 else if (GET_CODE (src
) == PLUS
2961 && GET_CODE (XEXP (src
, 1)) == CONST_INT
2962 && XEXP (src
, 0) == ep
->to_rtx
)
2963 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
2969 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
2971 new_body
= old_body
;
2974 new_body
= copy_insn (old_body
);
2975 if (REG_NOTES (insn
))
2976 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
2978 PATTERN (insn
) = new_body
;
2979 old_set
= single_set (insn
);
2981 /* First see if this insn remains valid when we
2982 make the change. If not, keep the INSN_CODE
2983 the same and let reload fit it up. */
2984 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
2985 validate_change (insn
, &SET_DEST (old_set
),
2987 if (! apply_change_group ())
2989 SET_SRC (old_set
) = src
;
2990 SET_DEST (old_set
) = ep
->to_rtx
;
2999 /* In this case this insn isn't serving a useful purpose. We
3000 will delete it in reload_as_needed once we know that this
3001 elimination is, in fact, being done.
3003 If REPLACE isn't set, we can't delete this insn, but needn't
3004 process it since it won't be used unless something changes. */
3007 delete_dead_insn (insn
);
3015 /* We allow one special case which happens to work on all machines we
3016 currently support: a single set with the source being a PLUS of an
3017 eliminable register and a constant. */
3019 && GET_CODE (SET_DEST (old_set
)) == REG
3020 && GET_CODE (SET_SRC (old_set
)) == PLUS
3021 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
3022 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
3023 && REGNO (XEXP (SET_SRC (old_set
), 0)) < FIRST_PSEUDO_REGISTER
)
3025 rtx reg
= XEXP (SET_SRC (old_set
), 0);
3026 int offset
= INTVAL (XEXP (SET_SRC (old_set
), 1));
3028 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3029 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3031 offset
+= ep
->offset
;
3036 /* We assume here that if we need a PARALLEL with
3037 CLOBBERs for this assignment, we can do with the
3038 MATCH_SCRATCHes that add_clobbers allocates.
3039 There's not much we can do if that doesn't work. */
3040 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3044 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, &num_clobbers
);
3047 rtvec vec
= rtvec_alloc (num_clobbers
+ 1);
3049 vec
->elem
[0] = PATTERN (insn
);
3050 PATTERN (insn
) = gen_rtx_PARALLEL (VOIDmode
, vec
);
3051 add_clobbers (PATTERN (insn
), INSN_CODE (insn
));
3053 if (INSN_CODE (insn
) < 0)
3058 new_body
= old_body
;
3061 new_body
= copy_insn (old_body
);
3062 if (REG_NOTES (insn
))
3063 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3065 PATTERN (insn
) = new_body
;
3066 old_set
= single_set (insn
);
3068 XEXP (SET_SRC (old_set
), 0) = ep
->to_rtx
;
3069 XEXP (SET_SRC (old_set
), 1) = GEN_INT (offset
);
3072 /* This can't have an effect on elimination offsets, so skip right
3078 /* Determine the effects of this insn on elimination offsets. */
3079 elimination_effects (old_body
, 0);
3081 /* Eliminate all eliminable registers occurring in operands that
3082 can be handled by reload. */
3083 extract_insn (insn
);
3085 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3087 orig_operand
[i
] = recog_data
.operand
[i
];
3088 substed_operand
[i
] = recog_data
.operand
[i
];
3090 /* For an asm statement, every operand is eliminable. */
3091 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3093 /* Check for setting a register that we know about. */
3094 if (recog_data
.operand_type
[i
] != OP_IN
3095 && GET_CODE (orig_operand
[i
]) == REG
)
3097 /* If we are assigning to a register that can be eliminated, it
3098 must be as part of a PARALLEL, since the code above handles
3099 single SETs. We must indicate that we can no longer
3100 eliminate this reg. */
3101 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3103 if (ep
->from_rtx
== orig_operand
[i
] && ep
->can_eliminate
)
3104 ep
->can_eliminate
= 0;
3107 substed_operand
[i
] = eliminate_regs (recog_data
.operand
[i
], 0,
3108 replace
? insn
: NULL_RTX
);
3109 if (substed_operand
[i
] != orig_operand
[i
])
3110 val
= any_changes
= 1;
3111 /* Terminate the search in check_eliminable_occurrences at
3113 *recog_data
.operand_loc
[i
] = 0;
3115 /* If an output operand changed from a REG to a MEM and INSN is an
3116 insn, write a CLOBBER insn. */
3117 if (recog_data
.operand_type
[i
] != OP_IN
3118 && GET_CODE (orig_operand
[i
]) == REG
3119 && GET_CODE (substed_operand
[i
]) == MEM
3121 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, orig_operand
[i
]),
3126 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3127 *recog_data
.dup_loc
[i
]
3128 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3130 /* If any eliminable remain, they aren't eliminable anymore. */
3131 check_eliminable_occurrences (old_body
);
3133 /* Substitute the operands; the new values are in the substed_operand
3135 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3136 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3137 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3138 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3140 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3141 re-recognize the insn. We do this in case we had a simple addition
3142 but now can do this as a load-address. This saves an insn in this
3144 If re-recognition fails, the old insn code number will still be used,
3145 and some register operands may have changed into PLUS expressions.
3146 These will be handled by find_reloads by loading them into a register
3151 /* If we aren't replacing things permanently and we changed something,
3152 make another copy to ensure that all the RTL is new. Otherwise
3153 things can go wrong if find_reload swaps commutative operands
3154 and one is inside RTL that has been copied while the other is not. */
3155 new_body
= old_body
;
3158 new_body
= copy_insn (old_body
);
3159 if (REG_NOTES (insn
))
3160 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3162 PATTERN (insn
) = new_body
;
3164 /* If we had a move insn but now we don't, rerecognize it. This will
3165 cause spurious re-recognition if the old move had a PARALLEL since
3166 the new one still will, but we can't call single_set without
3167 having put NEW_BODY into the insn and the re-recognition won't
3168 hurt in this rare case. */
3169 /* ??? Why this huge if statement - why don't we just rerecognize the
3173 && ((GET_CODE (SET_SRC (old_set
)) == REG
3174 && (GET_CODE (new_body
) != SET
3175 || GET_CODE (SET_SRC (new_body
)) != REG
))
3176 /* If this was a load from or store to memory, compare
3177 the MEM in recog_data.operand to the one in the insn.
3178 If they are not equal, then rerecognize the insn. */
3180 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3181 && SET_SRC (old_set
) != recog_data
.operand
[1])
3182 || (GET_CODE (SET_DEST (old_set
)) == MEM
3183 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3184 /* If this was an add insn before, rerecognize. */
3185 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3187 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3189 INSN_CODE (insn
) = icode
;
3193 /* Restore the old body. If there were any changes to it, we made a copy
3194 of it while the changes were still in place, so we'll correctly return
3195 a modified insn below. */
3198 /* Restore the old body. */
3199 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3200 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3201 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3202 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3205 /* Update all elimination pairs to reflect the status after the current
3206 insn. The changes we make were determined by the earlier call to
3207 elimination_effects.
3209 We also detect a cases where register elimination cannot be done,
3210 namely, if a register would be both changed and referenced outside a MEM
3211 in the resulting insn since such an insn is often undefined and, even if
3212 not, we cannot know what meaning will be given to it. Note that it is
3213 valid to have a register used in an address in an insn that changes it
3214 (presumably with a pre- or post-increment or decrement).
3216 If anything changes, return nonzero. */
3218 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3220 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3221 ep
->can_eliminate
= 0;
3223 ep
->ref_outside_mem
= 0;
3225 if (ep
->previous_offset
!= ep
->offset
)
3230 /* If we changed something, perform elimination in REG_NOTES. This is
3231 needed even when REPLACE is zero because a REG_DEAD note might refer
3232 to a register that we eliminate and could cause a different number
3233 of spill registers to be needed in the final reload pass than in
3235 if (val
&& REG_NOTES (insn
) != 0)
3236 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3241 /* Loop through all elimination pairs.
3242 Recalculate the number not at initial offset.
3244 Compute the maximum offset (minimum offset if the stack does not
3245 grow downward) for each elimination pair. */
3248 update_eliminable_offsets ()
3250 struct elim_table
*ep
;
3252 num_not_at_initial_offset
= 0;
3253 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3255 ep
->previous_offset
= ep
->offset
;
3256 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3257 num_not_at_initial_offset
++;
3261 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3262 replacement we currently believe is valid, mark it as not eliminable if X
3263 modifies DEST in any way other than by adding a constant integer to it.
3265 If DEST is the frame pointer, we do nothing because we assume that
3266 all assignments to the hard frame pointer are nonlocal gotos and are being
3267 done at a time when they are valid and do not disturb anything else.
3268 Some machines want to eliminate a fake argument pointer with either the
3269 frame or stack pointer. Assignments to the hard frame pointer must not
3270 prevent this elimination.
3272 Called via note_stores from reload before starting its passes to scan
3273 the insns of the function. */
3276 mark_not_eliminable (dest
, x
, data
)
3279 void *data ATTRIBUTE_UNUSED
;
3281 register unsigned int i
;
3283 /* A SUBREG of a hard register here is just changing its mode. We should
3284 not see a SUBREG of an eliminable hard register, but check just in
3286 if (GET_CODE (dest
) == SUBREG
)
3287 dest
= SUBREG_REG (dest
);
3289 if (dest
== hard_frame_pointer_rtx
)
3292 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3293 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3294 && (GET_CODE (x
) != SET
3295 || GET_CODE (SET_SRC (x
)) != PLUS
3296 || XEXP (SET_SRC (x
), 0) != dest
3297 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3299 reg_eliminate
[i
].can_eliminate_previous
3300 = reg_eliminate
[i
].can_eliminate
= 0;
3305 /* Verify that the initial elimination offsets did not change since the
3306 last call to set_initial_elim_offsets. This is used to catch cases
3307 where something illegal happened during reload_as_needed that could
3308 cause incorrect code to be generated if we did not check for it. */
3311 verify_initial_elim_offsets ()
3315 #ifdef ELIMINABLE_REGS
3316 struct elim_table
*ep
;
3318 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3320 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3321 if (t
!= ep
->initial_offset
)
3325 INITIAL_FRAME_POINTER_OFFSET (t
);
3326 if (t
!= reg_eliminate
[0].initial_offset
)
3331 /* Reset all offsets on eliminable registers to their initial values. */
3334 set_initial_elim_offsets ()
3336 struct elim_table
*ep
= reg_eliminate
;
3338 #ifdef ELIMINABLE_REGS
3339 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3341 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3342 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3345 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3346 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3349 num_not_at_initial_offset
= 0;
3352 /* Initialize the known label offsets.
3353 Set a known offset for each forced label to be at the initial offset
3354 of each elimination. We do this because we assume that all
3355 computed jumps occur from a location where each elimination is
3356 at its initial offset.
3357 For all other labels, show that we don't know the offsets. */
3360 set_initial_label_offsets ()
3363 memset ((char *) &offsets_known_at
[get_first_label_num ()], 0, num_labels
);
3365 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3367 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3370 /* Set all elimination offsets to the known values for the code label given
3374 set_offsets_for_label (insn
)
3378 int label_nr
= CODE_LABEL_NUMBER (insn
);
3379 struct elim_table
*ep
;
3381 num_not_at_initial_offset
= 0;
3382 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3384 ep
->offset
= ep
->previous_offset
= offsets_at
[label_nr
][i
];
3385 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3386 num_not_at_initial_offset
++;
3390 /* See if anything that happened changes which eliminations are valid.
3391 For example, on the Sparc, whether or not the frame pointer can
3392 be eliminated can depend on what registers have been used. We need
3393 not check some conditions again (such as flag_omit_frame_pointer)
3394 since they can't have changed. */
3397 update_eliminables (pset
)
3400 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3401 int previous_frame_pointer_needed
= frame_pointer_needed
;
3403 struct elim_table
*ep
;
3405 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3406 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3407 #ifdef ELIMINABLE_REGS
3408 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3411 ep
->can_eliminate
= 0;
3413 /* Look for the case where we have discovered that we can't replace
3414 register A with register B and that means that we will now be
3415 trying to replace register A with register C. This means we can
3416 no longer replace register C with register B and we need to disable
3417 such an elimination, if it exists. This occurs often with A == ap,
3418 B == sp, and C == fp. */
3420 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3422 struct elim_table
*op
;
3423 register int new_to
= -1;
3425 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3427 /* Find the current elimination for ep->from, if there is a
3429 for (op
= reg_eliminate
;
3430 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3431 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3437 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3439 for (op
= reg_eliminate
;
3440 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3441 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3442 op
->can_eliminate
= 0;
3446 /* See if any registers that we thought we could eliminate the previous
3447 time are no longer eliminable. If so, something has changed and we
3448 must spill the register. Also, recompute the number of eliminable
3449 registers and see if the frame pointer is needed; it is if there is
3450 no elimination of the frame pointer that we can perform. */
3452 frame_pointer_needed
= 1;
3453 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3455 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3456 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3457 frame_pointer_needed
= 0;
3459 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3461 ep
->can_eliminate_previous
= 0;
3462 SET_HARD_REG_BIT (*pset
, ep
->from
);
3467 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3468 /* If we didn't need a frame pointer last time, but we do now, spill
3469 the hard frame pointer. */
3470 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3471 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3475 /* Initialize the table of registers to eliminate. */
3480 struct elim_table
*ep
;
3481 #ifdef ELIMINABLE_REGS
3482 struct elim_table_1
*ep1
;
3486 reg_eliminate
= (struct elim_table
*)
3487 xcalloc (sizeof (struct elim_table
), NUM_ELIMINABLE_REGS
);
3489 /* Does this function require a frame pointer? */
3491 frame_pointer_needed
= (! flag_omit_frame_pointer
3492 #ifdef EXIT_IGNORE_STACK
3493 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3494 and restore sp for alloca. So we can't eliminate
3495 the frame pointer in that case. At some point,
3496 we should improve this by emitting the
3497 sp-adjusting insns for this case. */
3498 || (current_function_calls_alloca
3499 && EXIT_IGNORE_STACK
)
3501 || FRAME_POINTER_REQUIRED
);
3505 #ifdef ELIMINABLE_REGS
3506 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3507 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3509 ep
->from
= ep1
->from
;
3511 ep
->can_eliminate
= ep
->can_eliminate_previous
3512 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3513 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3516 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3517 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3518 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3519 = ! frame_pointer_needed
;
3522 /* Count the number of eliminable registers and build the FROM and TO
3523 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3524 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3525 We depend on this. */
3526 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3528 num_eliminable
+= ep
->can_eliminate
;
3529 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3530 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3534 /* Kick all pseudos out of hard register REGNO.
3536 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3537 because we found we can't eliminate some register. In the case, no pseudos
3538 are allowed to be in the register, even if they are only in a block that
3539 doesn't require spill registers, unlike the case when we are spilling this
3540 hard reg to produce another spill register.
3542 Return nonzero if any pseudos needed to be kicked out. */
3545 spill_hard_reg (regno
, cant_eliminate
)
3553 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3554 regs_ever_live
[regno
] = 1;
3557 /* Spill every pseudo reg that was allocated to this reg
3558 or to something that overlaps this reg. */
3560 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3561 if (reg_renumber
[i
] >= 0
3562 && (unsigned int) reg_renumber
[i
] <= regno
3563 && ((unsigned int) reg_renumber
[i
]
3564 + HARD_REGNO_NREGS ((unsigned int) reg_renumber
[i
],
3565 PSEUDO_REGNO_MODE (i
))
3567 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
3570 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3571 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3574 ior_hard_reg_set (set1
, set2
)
3575 HARD_REG_SET
*set1
, *set2
;
3577 IOR_HARD_REG_SET (*set1
, *set2
);
3580 /* After find_reload_regs has been run for all insn that need reloads,
3581 and/or spill_hard_regs was called, this function is used to actually
3582 spill pseudo registers and try to reallocate them. It also sets up the
3583 spill_regs array for use by choose_reload_regs. */
3586 finish_spills (global
)
3589 struct insn_chain
*chain
;
3590 int something_changed
= 0;
3593 /* Build the spill_regs array for the function. */
3594 /* If there are some registers still to eliminate and one of the spill regs
3595 wasn't ever used before, additional stack space may have to be
3596 allocated to store this register. Thus, we may have changed the offset
3597 between the stack and frame pointers, so mark that something has changed.
3599 One might think that we need only set VAL to 1 if this is a call-used
3600 register. However, the set of registers that must be saved by the
3601 prologue is not identical to the call-used set. For example, the
3602 register used by the call insn for the return PC is a call-used register,
3603 but must be saved by the prologue. */
3606 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3607 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3609 spill_reg_order
[i
] = n_spills
;
3610 spill_regs
[n_spills
++] = i
;
3611 if (num_eliminable
&& ! regs_ever_live
[i
])
3612 something_changed
= 1;
3613 regs_ever_live
[i
] = 1;
3616 spill_reg_order
[i
] = -1;
3618 EXECUTE_IF_SET_IN_REG_SET
3619 (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
,
3621 /* Record the current hard register the pseudo is allocated to in
3622 pseudo_previous_regs so we avoid reallocating it to the same
3623 hard reg in a later pass. */
3624 if (reg_renumber
[i
] < 0)
3627 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3628 /* Mark it as no longer having a hard register home. */
3629 reg_renumber
[i
] = -1;
3630 /* We will need to scan everything again. */
3631 something_changed
= 1;
3634 /* Retry global register allocation if possible. */
3637 memset ((char *) pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
3638 /* For every insn that needs reloads, set the registers used as spill
3639 regs in pseudo_forbidden_regs for every pseudo live across the
3641 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3643 EXECUTE_IF_SET_IN_REG_SET
3644 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
,
3646 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3647 &chain
->used_spill_regs
);
3649 EXECUTE_IF_SET_IN_REG_SET
3650 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
,
3652 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3653 &chain
->used_spill_regs
);
3657 /* Retry allocating the spilled pseudos. For each reg, merge the
3658 various reg sets that indicate which hard regs can't be used,
3659 and call retry_global_alloc.
3660 We change spill_pseudos here to only contain pseudos that did not
3661 get a new hard register. */
3662 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3663 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3665 HARD_REG_SET forbidden
;
3666 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3667 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3668 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3669 retry_global_alloc (i
, forbidden
);
3670 if (reg_renumber
[i
] >= 0)
3671 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
3675 /* Fix up the register information in the insn chain.
3676 This involves deleting those of the spilled pseudos which did not get
3677 a new hard register home from the live_{before,after} sets. */
3678 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3680 HARD_REG_SET used_by_pseudos
;
3681 HARD_REG_SET used_by_pseudos2
;
3683 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
3684 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
3686 /* Mark any unallocated hard regs as available for spills. That
3687 makes inheritance work somewhat better. */
3688 if (chain
->need_reload
)
3690 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
3691 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
3692 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3694 /* Save the old value for the sanity test below. */
3695 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3697 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
3698 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
3699 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3700 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3702 /* Make sure we only enlarge the set. */
3703 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3709 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3710 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3712 int regno
= reg_renumber
[i
];
3713 if (reg_old_renumber
[i
] == regno
)
3716 alter_reg (i
, reg_old_renumber
[i
]);
3717 reg_old_renumber
[i
] = regno
;
3721 fprintf (rtl_dump_file
, " Register %d now on stack.\n\n", i
);
3723 fprintf (rtl_dump_file
, " Register %d now in %d.\n\n",
3724 i
, reg_renumber
[i
]);
3728 return something_changed
;
3731 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3732 Also mark any hard registers used to store user variables as
3733 forbidden from being used for spill registers. */
3736 scan_paradoxical_subregs (x
)
3740 register const char *fmt
;
3741 register enum rtx_code code
= GET_CODE (x
);
3747 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
3748 && REG_USERVAR_P (x
))
3749 SET_HARD_REG_BIT (bad_spill_regs_global
, REGNO (x
));
3765 if (GET_CODE (SUBREG_REG (x
)) == REG
3766 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3767 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3768 = GET_MODE_SIZE (GET_MODE (x
));
3775 fmt
= GET_RTX_FORMAT (code
);
3776 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3779 scan_paradoxical_subregs (XEXP (x
, i
));
3780 else if (fmt
[i
] == 'E')
3783 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3784 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3789 /* Reload pseudo-registers into hard regs around each insn as needed.
3790 Additional register load insns are output before the insn that needs it
3791 and perhaps store insns after insns that modify the reloaded pseudo reg.
3793 reg_last_reload_reg and reg_reloaded_contents keep track of
3794 which registers are already available in reload registers.
3795 We update these for the reloads that we perform,
3796 as the insns are scanned. */
3799 reload_as_needed (live_known
)
3802 struct insn_chain
*chain
;
3803 #if defined (AUTO_INC_DEC)
3808 memset ((char *) spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
3809 memset ((char *) spill_reg_store
, 0, sizeof spill_reg_store
);
3810 reg_last_reload_reg
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
3811 reg_has_output_reload
= (char *) xmalloc (max_regno
);
3812 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
3814 set_initial_elim_offsets ();
3816 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3819 rtx insn
= chain
->insn
;
3820 rtx old_next
= NEXT_INSN (insn
);
3822 /* If we pass a label, copy the offsets from the label information
3823 into the current offsets of each elimination. */
3824 if (GET_CODE (insn
) == CODE_LABEL
)
3825 set_offsets_for_label (insn
);
3827 else if (INSN_P (insn
))
3829 rtx oldpat
= PATTERN (insn
);
3831 /* If this is a USE and CLOBBER of a MEM, ensure that any
3832 references to eliminable registers have been removed. */
3834 if ((GET_CODE (PATTERN (insn
)) == USE
3835 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3836 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
3837 XEXP (XEXP (PATTERN (insn
), 0), 0)
3838 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3839 GET_MODE (XEXP (PATTERN (insn
), 0)),
3842 /* If we need to do register elimination processing, do so.
3843 This might delete the insn, in which case we are done. */
3844 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
3846 eliminate_regs_in_insn (insn
, 1);
3847 if (GET_CODE (insn
) == NOTE
)
3849 update_eliminable_offsets ();
3854 /* If need_elim is nonzero but need_reload is zero, one might think
3855 that we could simply set n_reloads to 0. However, find_reloads
3856 could have done some manipulation of the insn (such as swapping
3857 commutative operands), and these manipulations are lost during
3858 the first pass for every insn that needs register elimination.
3859 So the actions of find_reloads must be redone here. */
3861 if (! chain
->need_elim
&& ! chain
->need_reload
3862 && ! chain
->need_operand_change
)
3864 /* First find the pseudo regs that must be reloaded for this insn.
3865 This info is returned in the tables reload_... (see reload.h).
3866 Also modify the body of INSN by substituting RELOAD
3867 rtx's for those pseudo regs. */
3870 memset (reg_has_output_reload
, 0, max_regno
);
3871 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3873 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3879 rtx next
= NEXT_INSN (insn
);
3882 prev
= PREV_INSN (insn
);
3884 /* Now compute which reload regs to reload them into. Perhaps
3885 reusing reload regs from previous insns, or else output
3886 load insns to reload them. Maybe output store insns too.
3887 Record the choices of reload reg in reload_reg_rtx. */
3888 choose_reload_regs (chain
);
3890 /* Merge any reloads that we didn't combine for fear of
3891 increasing the number of spill registers needed but now
3892 discover can be safely merged. */
3893 if (SMALL_REGISTER_CLASSES
)
3894 merge_assigned_reloads (insn
);
3896 /* Generate the insns to reload operands into or out of
3897 their reload regs. */
3898 emit_reload_insns (chain
);
3900 /* Substitute the chosen reload regs from reload_reg_rtx
3901 into the insn's body (or perhaps into the bodies of other
3902 load and store insn that we just made for reloading
3903 and that we moved the structure into). */
3904 subst_reloads (insn
);
3906 /* If this was an ASM, make sure that all the reload insns
3907 we have generated are valid. If not, give an error
3910 if (asm_noperands (PATTERN (insn
)) >= 0)
3911 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3912 if (p
!= insn
&& INSN_P (p
)
3913 && (recog_memoized (p
) < 0
3914 || (extract_insn (p
), ! constrain_operands (1))))
3916 error_for_asm (insn
,
3917 "`asm' operand requires impossible reload");
3919 NOTE_SOURCE_FILE (p
) = 0;
3920 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
3924 if (num_eliminable
&& chain
->need_elim
)
3925 update_eliminable_offsets ();
3927 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3928 is no longer validly lying around to save a future reload.
3929 Note that this does not detect pseudos that were reloaded
3930 for this insn in order to be stored in
3931 (obeying register constraints). That is correct; such reload
3932 registers ARE still valid. */
3933 note_stores (oldpat
, forget_old_reloads_1
, NULL
);
3935 /* There may have been CLOBBER insns placed after INSN. So scan
3936 between INSN and NEXT and use them to forget old reloads. */
3937 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
3938 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
3939 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
3942 /* Likewise for regs altered by auto-increment in this insn.
3943 REG_INC notes have been changed by reloading:
3944 find_reloads_address_1 records substitutions for them,
3945 which have been performed by subst_reloads above. */
3946 for (i
= n_reloads
- 1; i
>= 0; i
--)
3948 rtx in_reg
= rld
[i
].in_reg
;
3951 enum rtx_code code
= GET_CODE (in_reg
);
3952 /* PRE_INC / PRE_DEC will have the reload register ending up
3953 with the same value as the stack slot, but that doesn't
3954 hold true for POST_INC / POST_DEC. Either we have to
3955 convert the memory access to a true POST_INC / POST_DEC,
3956 or we can't use the reload register for inheritance. */
3957 if ((code
== POST_INC
|| code
== POST_DEC
)
3958 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
3959 REGNO (rld
[i
].reg_rtx
))
3960 /* Make sure it is the inc/dec pseudo, and not
3961 some other (e.g. output operand) pseudo. */
3962 && (reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
3963 == REGNO (XEXP (in_reg
, 0))))
3966 rtx reload_reg
= rld
[i
].reg_rtx
;
3967 enum machine_mode mode
= GET_MODE (reload_reg
);
3971 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
3973 /* We really want to ignore REG_INC notes here, so
3974 use PATTERN (p) as argument to reg_set_p . */
3975 if (reg_set_p (reload_reg
, PATTERN (p
)))
3977 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
3982 n
= validate_replace_rtx (reload_reg
,
3983 gen_rtx (code
, mode
,
3987 /* We must also verify that the constraints
3988 are met after the replacement. */
3991 n
= constrain_operands (1);
3995 /* If the constraints were not met, then
3996 undo the replacement. */
3999 validate_replace_rtx (gen_rtx (code
, mode
,
4011 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4013 /* Mark this as having an output reload so that the
4014 REG_INC processing code below won't invalidate
4015 the reload for inheritance. */
4016 SET_HARD_REG_BIT (reg_is_output_reload
,
4017 REGNO (reload_reg
));
4018 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4021 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4024 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4025 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4026 REGNO (rld
[i
].reg_rtx
))
4027 /* Make sure it is the inc/dec pseudo, and not
4028 some other (e.g. output operand) pseudo. */
4029 && (reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4030 == REGNO (XEXP (in_reg
, 0))))
4032 SET_HARD_REG_BIT (reg_is_output_reload
,
4033 REGNO (rld
[i
].reg_rtx
));
4034 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4038 /* If a pseudo that got a hard register is auto-incremented,
4039 we must purge records of copying it into pseudos without
4041 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4042 if (REG_NOTE_KIND (x
) == REG_INC
)
4044 /* See if this pseudo reg was reloaded in this insn.
4045 If so, its last-reload info is still valid
4046 because it is based on this insn's reload. */
4047 for (i
= 0; i
< n_reloads
; i
++)
4048 if (rld
[i
].out
== XEXP (x
, 0))
4052 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4056 /* A reload reg's contents are unknown after a label. */
4057 if (GET_CODE (insn
) == CODE_LABEL
)
4058 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4060 /* Don't assume a reload reg is still good after a call insn
4061 if it is a call-used reg. */
4062 else if (GET_CODE (insn
) == CALL_INSN
)
4063 AND_COMPL_HARD_REG_SET(reg_reloaded_valid
, call_used_reg_set
);
4067 free (reg_last_reload_reg
);
4068 free (reg_has_output_reload
);
4071 /* Discard all record of any value reloaded from X,
4072 or reloaded in X from someplace else;
4073 unless X is an output reload reg of the current insn.
4075 X may be a hard reg (the reload reg)
4076 or it may be a pseudo reg that was reloaded from. */
4079 forget_old_reloads_1 (x
, ignored
, data
)
4081 rtx ignored ATTRIBUTE_UNUSED
;
4082 void *data ATTRIBUTE_UNUSED
;
4088 /* note_stores does give us subregs of hard regs,
4089 subreg_regno_offset will abort if it is not a hard reg. */
4090 while (GET_CODE (x
) == SUBREG
)
4092 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (x
)),
4093 GET_MODE (SUBREG_REG (x
)),
4099 if (GET_CODE (x
) != REG
)
4102 regno
= REGNO (x
) + offset
;
4104 if (regno
>= FIRST_PSEUDO_REGISTER
)
4110 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4111 /* Storing into a spilled-reg invalidates its contents.
4112 This can happen if a block-local pseudo is allocated to that reg
4113 and it wasn't spilled because this block's total need is 0.
4114 Then some insn might have an optional reload and use this reg. */
4115 for (i
= 0; i
< nr
; i
++)
4116 /* But don't do this if the reg actually serves as an output
4117 reload reg in the current instruction. */
4119 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4121 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4122 spill_reg_store
[regno
+ i
] = 0;
4126 /* Since value of X has changed,
4127 forget any value previously copied from it. */
4130 /* But don't forget a copy if this is the output reload
4131 that establishes the copy's validity. */
4132 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4133 reg_last_reload_reg
[regno
+ nr
] = 0;
4136 /* The following HARD_REG_SETs indicate when each hard register is
4137 used for a reload of various parts of the current insn. */
4139 /* If reg is unavailable for all reloads. */
4140 static HARD_REG_SET reload_reg_unavailable
;
4141 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4142 static HARD_REG_SET reload_reg_used
;
4143 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4144 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4145 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4146 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4147 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4148 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4149 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4150 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4151 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4152 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4153 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4154 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4155 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4156 static HARD_REG_SET reload_reg_used_in_op_addr
;
4157 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4158 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4159 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4160 static HARD_REG_SET reload_reg_used_in_insn
;
4161 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4162 static HARD_REG_SET reload_reg_used_in_other_addr
;
4164 /* If reg is in use as a reload reg for any sort of reload. */
4165 static HARD_REG_SET reload_reg_used_at_all
;
4167 /* If reg is use as an inherited reload. We just mark the first register
4169 static HARD_REG_SET reload_reg_used_for_inherit
;
4171 /* Records which hard regs are used in any way, either as explicit use or
4172 by being allocated to a pseudo during any point of the current insn. */
4173 static HARD_REG_SET reg_used_in_insn
;
4175 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4176 TYPE. MODE is used to indicate how many consecutive regs are
4180 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4183 enum reload_type type
;
4184 enum machine_mode mode
;
4186 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4189 for (i
= regno
; i
< nregs
+ regno
; i
++)
4194 SET_HARD_REG_BIT (reload_reg_used
, i
);
4197 case RELOAD_FOR_INPUT_ADDRESS
:
4198 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4201 case RELOAD_FOR_INPADDR_ADDRESS
:
4202 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4205 case RELOAD_FOR_OUTPUT_ADDRESS
:
4206 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4209 case RELOAD_FOR_OUTADDR_ADDRESS
:
4210 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4213 case RELOAD_FOR_OPERAND_ADDRESS
:
4214 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4217 case RELOAD_FOR_OPADDR_ADDR
:
4218 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4221 case RELOAD_FOR_OTHER_ADDRESS
:
4222 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4225 case RELOAD_FOR_INPUT
:
4226 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4229 case RELOAD_FOR_OUTPUT
:
4230 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4233 case RELOAD_FOR_INSN
:
4234 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4238 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4242 /* Similarly, but show REGNO is no longer in use for a reload. */
4245 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4248 enum reload_type type
;
4249 enum machine_mode mode
;
4251 unsigned int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4252 unsigned int start_regno
, end_regno
, r
;
4254 /* A complication is that for some reload types, inheritance might
4255 allow multiple reloads of the same types to share a reload register.
4256 We set check_opnum if we have to check only reloads with the same
4257 operand number, and check_any if we have to check all reloads. */
4258 int check_opnum
= 0;
4260 HARD_REG_SET
*used_in_set
;
4265 used_in_set
= &reload_reg_used
;
4268 case RELOAD_FOR_INPUT_ADDRESS
:
4269 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4272 case RELOAD_FOR_INPADDR_ADDRESS
:
4274 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4277 case RELOAD_FOR_OUTPUT_ADDRESS
:
4278 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4281 case RELOAD_FOR_OUTADDR_ADDRESS
:
4283 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4286 case RELOAD_FOR_OPERAND_ADDRESS
:
4287 used_in_set
= &reload_reg_used_in_op_addr
;
4290 case RELOAD_FOR_OPADDR_ADDR
:
4292 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4295 case RELOAD_FOR_OTHER_ADDRESS
:
4296 used_in_set
= &reload_reg_used_in_other_addr
;
4300 case RELOAD_FOR_INPUT
:
4301 used_in_set
= &reload_reg_used_in_input
[opnum
];
4304 case RELOAD_FOR_OUTPUT
:
4305 used_in_set
= &reload_reg_used_in_output
[opnum
];
4308 case RELOAD_FOR_INSN
:
4309 used_in_set
= &reload_reg_used_in_insn
;
4314 /* We resolve conflicts with remaining reloads of the same type by
4315 excluding the intervals of of reload registers by them from the
4316 interval of freed reload registers. Since we only keep track of
4317 one set of interval bounds, we might have to exclude somewhat
4318 more then what would be necessary if we used a HARD_REG_SET here.
4319 But this should only happen very infrequently, so there should
4320 be no reason to worry about it. */
4322 start_regno
= regno
;
4323 end_regno
= regno
+ nregs
;
4324 if (check_opnum
|| check_any
)
4326 for (i
= n_reloads
- 1; i
>= 0; i
--)
4328 if (rld
[i
].when_needed
== type
4329 && (check_any
|| rld
[i
].opnum
== opnum
)
4332 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
4333 unsigned int conflict_end
4335 + HARD_REGNO_NREGS (conflict_start
, rld
[i
].mode
));
4337 /* If there is an overlap with the first to-be-freed register,
4338 adjust the interval start. */
4339 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4340 start_regno
= conflict_end
;
4341 /* Otherwise, if there is a conflict with one of the other
4342 to-be-freed registers, adjust the interval end. */
4343 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4344 end_regno
= conflict_start
;
4349 for (r
= start_regno
; r
< end_regno
; r
++)
4350 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
4353 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4354 specified by OPNUM and TYPE. */
4357 reload_reg_free_p (regno
, opnum
, type
)
4360 enum reload_type type
;
4364 /* In use for a RELOAD_OTHER means it's not available for anything. */
4365 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
4366 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4372 /* In use for anything means we can't use it for RELOAD_OTHER. */
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4374 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4375 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4378 for (i
= 0; i
< reload_n_operands
; i
++)
4379 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4382 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4383 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4384 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4389 case RELOAD_FOR_INPUT
:
4390 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4391 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4397 /* If it is used for some other input, can't use it. */
4398 for (i
= 0; i
< reload_n_operands
; i
++)
4399 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4402 /* If it is used in a later operand's address, can't use it. */
4403 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4404 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4405 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4410 case RELOAD_FOR_INPUT_ADDRESS
:
4411 /* Can't use a register if it is used for an input address for this
4412 operand or used as an input in an earlier one. */
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4414 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4417 for (i
= 0; i
< opnum
; i
++)
4418 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4423 case RELOAD_FOR_INPADDR_ADDRESS
:
4424 /* Can't use a register if it is used for an input address
4425 for this operand or used as an input in an earlier
4427 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4430 for (i
= 0; i
< opnum
; i
++)
4431 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4436 case RELOAD_FOR_OUTPUT_ADDRESS
:
4437 /* Can't use a register if it is used for an output address for this
4438 operand or used as an output in this or a later operand. */
4439 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4442 for (i
= opnum
; i
< reload_n_operands
; i
++)
4443 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4448 case RELOAD_FOR_OUTADDR_ADDRESS
:
4449 /* Can't use a register if it is used for an output address
4450 for this operand or used as an output in this or a
4452 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4455 for (i
= opnum
; i
< reload_n_operands
; i
++)
4456 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4461 case RELOAD_FOR_OPERAND_ADDRESS
:
4462 for (i
= 0; i
< reload_n_operands
; i
++)
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4466 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4467 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4469 case RELOAD_FOR_OPADDR_ADDR
:
4470 for (i
= 0; i
< reload_n_operands
; i
++)
4471 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4474 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4476 case RELOAD_FOR_OUTPUT
:
4477 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4478 outputs, or an operand address for this or an earlier output. */
4479 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4482 for (i
= 0; i
< reload_n_operands
; i
++)
4483 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4486 for (i
= 0; i
<= opnum
; i
++)
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4488 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4493 case RELOAD_FOR_INSN
:
4494 for (i
= 0; i
< reload_n_operands
; i
++)
4495 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4496 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4499 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4500 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4502 case RELOAD_FOR_OTHER_ADDRESS
:
4503 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4508 /* Return 1 if the value in reload reg REGNO, as used by a reload
4509 needed for the part of the insn specified by OPNUM and TYPE,
4510 is still available in REGNO at the end of the insn.
4512 We can assume that the reload reg was already tested for availability
4513 at the time it is needed, and we should not check this again,
4514 in case the reg has already been marked in use. */
4517 reload_reg_reaches_end_p (regno
, opnum
, type
)
4520 enum reload_type type
;
4527 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4528 its value must reach the end. */
4531 /* If this use is for part of the insn,
4532 its value reaches if no subsequent part uses the same register.
4533 Just like the above function, don't try to do this with lots
4536 case RELOAD_FOR_OTHER_ADDRESS
:
4537 /* Here we check for everything else, since these don't conflict
4538 with anything else and everything comes later. */
4540 for (i
= 0; i
< reload_n_operands
; i
++)
4541 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4542 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4545 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4546 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4549 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4550 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4551 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4553 case RELOAD_FOR_INPUT_ADDRESS
:
4554 case RELOAD_FOR_INPADDR_ADDRESS
:
4555 /* Similar, except that we check only for this and subsequent inputs
4556 and the address of only subsequent inputs and we do not need
4557 to check for RELOAD_OTHER objects since they are known not to
4560 for (i
= opnum
; i
< reload_n_operands
; i
++)
4561 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4564 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4569 for (i
= 0; i
< reload_n_operands
; i
++)
4570 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4572 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4575 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4578 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4579 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4580 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4582 case RELOAD_FOR_INPUT
:
4583 /* Similar to input address, except we start at the next operand for
4584 both input and input address and we do not check for
4585 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4588 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4589 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4590 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4591 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4594 /* ... fall through ... */
4596 case RELOAD_FOR_OPERAND_ADDRESS
:
4597 /* Check outputs and their addresses. */
4599 for (i
= 0; i
< reload_n_operands
; i
++)
4600 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4602 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4605 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4607 case RELOAD_FOR_OPADDR_ADDR
:
4608 for (i
= 0; i
< reload_n_operands
; i
++)
4609 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4611 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4614 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4615 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4616 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4618 case RELOAD_FOR_INSN
:
4619 /* These conflict with other outputs with RELOAD_OTHER. So
4620 we need only check for output addresses. */
4624 /* ... fall through ... */
4626 case RELOAD_FOR_OUTPUT
:
4627 case RELOAD_FOR_OUTPUT_ADDRESS
:
4628 case RELOAD_FOR_OUTADDR_ADDRESS
:
4629 /* We already know these can't conflict with a later output. So the
4630 only thing to check are later output addresses. */
4631 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4632 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4633 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4642 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4645 This function uses the same algorithm as reload_reg_free_p above. */
4648 reloads_conflict (r1
, r2
)
4651 enum reload_type r1_type
= rld
[r1
].when_needed
;
4652 enum reload_type r2_type
= rld
[r2
].when_needed
;
4653 int r1_opnum
= rld
[r1
].opnum
;
4654 int r2_opnum
= rld
[r2
].opnum
;
4656 /* RELOAD_OTHER conflicts with everything. */
4657 if (r2_type
== RELOAD_OTHER
)
4660 /* Otherwise, check conflicts differently for each type. */
4664 case RELOAD_FOR_INPUT
:
4665 return (r2_type
== RELOAD_FOR_INSN
4666 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
4667 || r2_type
== RELOAD_FOR_OPADDR_ADDR
4668 || r2_type
== RELOAD_FOR_INPUT
4669 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
4670 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
4671 && r2_opnum
> r1_opnum
));
4673 case RELOAD_FOR_INPUT_ADDRESS
:
4674 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
4675 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4677 case RELOAD_FOR_INPADDR_ADDRESS
:
4678 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
4679 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
4681 case RELOAD_FOR_OUTPUT_ADDRESS
:
4682 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
4683 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
4685 case RELOAD_FOR_OUTADDR_ADDRESS
:
4686 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
4687 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
4689 case RELOAD_FOR_OPERAND_ADDRESS
:
4690 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
4691 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4693 case RELOAD_FOR_OPADDR_ADDR
:
4694 return (r2_type
== RELOAD_FOR_INPUT
4695 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
4697 case RELOAD_FOR_OUTPUT
:
4698 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
4699 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
4700 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
4701 && r2_opnum
<= r1_opnum
));
4703 case RELOAD_FOR_INSN
:
4704 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
4705 || r2_type
== RELOAD_FOR_INSN
4706 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
4708 case RELOAD_FOR_OTHER_ADDRESS
:
4709 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
4719 /* Indexed by reload number, 1 if incoming value
4720 inherited from previous insns. */
4721 char reload_inherited
[MAX_RELOADS
];
4723 /* For an inherited reload, this is the insn the reload was inherited from,
4724 if we know it. Otherwise, this is 0. */
4725 rtx reload_inheritance_insn
[MAX_RELOADS
];
4727 /* If non-zero, this is a place to get the value of the reload,
4728 rather than using reload_in. */
4729 rtx reload_override_in
[MAX_RELOADS
];
4731 /* For each reload, the hard register number of the register used,
4732 or -1 if we did not need a register for this reload. */
4733 int reload_spill_index
[MAX_RELOADS
];
4735 /* Subroutine of free_for_value_p, used to check a single register.
4736 START_REGNO is the starting regno of the full reload register
4737 (possibly comprising multiple hard registers) that we are considering. */
4740 reload_reg_free_for_value_p (start_regno
, regno
, opnum
, type
, value
, out
,
4741 reloadnum
, ignore_address_reloads
)
4742 int start_regno
, regno
;
4744 enum reload_type type
;
4747 int ignore_address_reloads
;
4750 /* Set if we see an input reload that must not share its reload register
4751 with any new earlyclobber, but might otherwise share the reload
4752 register with an output or input-output reload. */
4753 int check_earlyclobber
= 0;
4757 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
4760 if (out
== const0_rtx
)
4766 /* We use some pseudo 'time' value to check if the lifetimes of the
4767 new register use would overlap with the one of a previous reload
4768 that is not read-only or uses a different value.
4769 The 'time' used doesn't have to be linear in any shape or form, just
4771 Some reload types use different 'buckets' for each operand.
4772 So there are MAX_RECOG_OPERANDS different time values for each
4774 We compute TIME1 as the time when the register for the prospective
4775 new reload ceases to be live, and TIME2 for each existing
4776 reload as the time when that the reload register of that reload
4778 Where there is little to be gained by exact lifetime calculations,
4779 we just make conservative assumptions, i.e. a longer lifetime;
4780 this is done in the 'default:' cases. */
4783 case RELOAD_FOR_OTHER_ADDRESS
:
4784 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4785 time1
= copy
? 0 : 1;
4788 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
4790 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4791 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4792 respectively, to the time values for these, we get distinct time
4793 values. To get distinct time values for each operand, we have to
4794 multiply opnum by at least three. We round that up to four because
4795 multiply by four is often cheaper. */
4796 case RELOAD_FOR_INPADDR_ADDRESS
:
4797 time1
= opnum
* 4 + 2;
4799 case RELOAD_FOR_INPUT_ADDRESS
:
4800 time1
= opnum
* 4 + 3;
4802 case RELOAD_FOR_INPUT
:
4803 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4804 executes (inclusive). */
4805 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
4807 case RELOAD_FOR_OPADDR_ADDR
:
4809 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4810 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
4812 case RELOAD_FOR_OPERAND_ADDRESS
:
4813 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4815 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
4817 case RELOAD_FOR_OUTADDR_ADDRESS
:
4818 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
4820 case RELOAD_FOR_OUTPUT_ADDRESS
:
4821 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
4824 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
4827 for (i
= 0; i
< n_reloads
; i
++)
4829 rtx reg
= rld
[i
].reg_rtx
;
4830 if (reg
&& GET_CODE (reg
) == REG
4831 && ((unsigned) regno
- true_regnum (reg
)
4832 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned)1)
4835 rtx other_input
= rld
[i
].in
;
4837 /* If the other reload loads the same input value, that
4838 will not cause a conflict only if it's loading it into
4839 the same register. */
4840 if (true_regnum (reg
) != start_regno
)
4841 other_input
= NULL_RTX
;
4842 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
4843 || rld
[i
].out
|| out
)
4846 switch (rld
[i
].when_needed
)
4848 case RELOAD_FOR_OTHER_ADDRESS
:
4851 case RELOAD_FOR_INPADDR_ADDRESS
:
4852 /* find_reloads makes sure that a
4853 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4854 by at most one - the first -
4855 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4856 address reload is inherited, the address address reload
4857 goes away, so we can ignore this conflict. */
4858 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
4859 && ignore_address_reloads
4860 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4861 Then the address address is still needed to store
4862 back the new address. */
4863 && ! rld
[reloadnum
].out
)
4865 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4866 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4868 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4869 && ignore_address_reloads
4870 /* Unless we are reloading an auto_inc expression. */
4871 && ! rld
[reloadnum
].out
)
4873 time2
= rld
[i
].opnum
* 4 + 2;
4875 case RELOAD_FOR_INPUT_ADDRESS
:
4876 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
4877 && ignore_address_reloads
4878 && ! rld
[reloadnum
].out
)
4880 time2
= rld
[i
].opnum
* 4 + 3;
4882 case RELOAD_FOR_INPUT
:
4883 time2
= rld
[i
].opnum
* 4 + 4;
4884 check_earlyclobber
= 1;
4886 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4887 == MAX_RECOG_OPERAND * 4 */
4888 case RELOAD_FOR_OPADDR_ADDR
:
4889 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
4890 && ignore_address_reloads
4891 && ! rld
[reloadnum
].out
)
4893 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
4895 case RELOAD_FOR_OPERAND_ADDRESS
:
4896 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
4897 check_earlyclobber
= 1;
4899 case RELOAD_FOR_INSN
:
4900 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4902 case RELOAD_FOR_OUTPUT
:
4903 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4904 instruction is executed. */
4905 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4907 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4908 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4910 case RELOAD_FOR_OUTADDR_ADDRESS
:
4911 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
4912 && ignore_address_reloads
4913 && ! rld
[reloadnum
].out
)
4915 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
4917 case RELOAD_FOR_OUTPUT_ADDRESS
:
4918 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
4921 /* If there is no conflict in the input part, handle this
4922 like an output reload. */
4923 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
4925 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
4926 /* Earlyclobbered outputs must conflict with inputs. */
4927 if (earlyclobber_operand_p (rld
[i
].out
))
4928 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
4933 /* RELOAD_OTHER might be live beyond instruction execution,
4934 but this is not obvious when we set time2 = 1. So check
4935 here if there might be a problem with the new reload
4936 clobbering the register used by the RELOAD_OTHER. */
4944 && (! rld
[i
].in
|| rld
[i
].out
4945 || ! rtx_equal_p (other_input
, value
)))
4946 || (out
&& rld
[reloadnum
].out_reg
4947 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
4953 /* Earlyclobbered outputs must conflict with inputs. */
4954 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
4960 /* Return 1 if the value in reload reg REGNO, as used by a reload
4961 needed for the part of the insn specified by OPNUM and TYPE,
4962 may be used to load VALUE into it.
4964 MODE is the mode in which the register is used, this is needed to
4965 determine how many hard regs to test.
4967 Other read-only reloads with the same value do not conflict
4968 unless OUT is non-zero and these other reloads have to live while
4969 output reloads live.
4970 If OUT is CONST0_RTX, this is a special case: it means that the
4971 test should not be for using register REGNO as reload register, but
4972 for copying from register REGNO into the reload register.
4974 RELOADNUM is the number of the reload we want to load this value for;
4975 a reload does not conflict with itself.
4977 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4978 reloads that load an address for the very reload we are considering.
4980 The caller has to make sure that there is no conflict with the return
4984 free_for_value_p (regno
, mode
, opnum
, type
, value
, out
, reloadnum
,
4985 ignore_address_reloads
)
4987 enum machine_mode mode
;
4989 enum reload_type type
;
4992 int ignore_address_reloads
;
4994 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4996 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
4997 value
, out
, reloadnum
,
4998 ignore_address_reloads
))
5003 /* Determine whether the reload reg X overlaps any rtx'es used for
5004 overriding inheritance. Return nonzero if so. */
5007 conflicts_with_override (x
)
5011 for (i
= 0; i
< n_reloads
; i
++)
5012 if (reload_override_in
[i
]
5013 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
5018 /* Give an error message saying we failed to find a reload for INSN,
5019 and clear out reload R. */
5021 failed_reload (insn
, r
)
5025 if (asm_noperands (PATTERN (insn
)) < 0)
5026 /* It's the compiler's fault. */
5027 fatal_insn ("Could not find a spill register", insn
);
5029 /* It's the user's fault; the operand's mode and constraint
5030 don't match. Disable this reload so we don't crash in final. */
5031 error_for_asm (insn
,
5032 "`asm' operand constraint incompatible with operand size");
5036 rld
[r
].optional
= 1;
5037 rld
[r
].secondary_p
= 1;
5040 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5041 for reload R. If it's valid, get an rtx for it. Return nonzero if
5044 set_reload_reg (i
, r
)
5048 rtx reg
= spill_reg_rtx
[i
];
5050 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
5051 spill_reg_rtx
[i
] = reg
5052 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
5054 regno
= true_regnum (reg
);
5056 /* Detect when the reload reg can't hold the reload mode.
5057 This used to be one `if', but Sequent compiler can't handle that. */
5058 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5060 enum machine_mode test_mode
= VOIDmode
;
5062 test_mode
= GET_MODE (rld
[r
].in
);
5063 /* If rld[r].in has VOIDmode, it means we will load it
5064 in whatever mode the reload reg has: to wit, rld[r].mode.
5065 We have already tested that for validity. */
5066 /* Aside from that, we need to test that the expressions
5067 to reload from or into have modes which are valid for this
5068 reload register. Otherwise the reload insns would be invalid. */
5069 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
5070 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5071 if (! (rld
[r
].out
!= 0
5072 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
5074 /* The reg is OK. */
5077 /* Mark as in use for this insn the reload regs we use
5079 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
5080 rld
[r
].when_needed
, rld
[r
].mode
);
5082 rld
[r
].reg_rtx
= reg
;
5083 reload_spill_index
[r
] = spill_regs
[i
];
5090 /* Find a spill register to use as a reload register for reload R.
5091 LAST_RELOAD is non-zero if this is the last reload for the insn being
5094 Set rld[R].reg_rtx to the register allocated.
5096 We return 1 if successful, or 0 if we couldn't find a spill reg and
5097 we didn't change anything. */
5100 allocate_reload_reg (chain
, r
, last_reload
)
5101 struct insn_chain
*chain ATTRIBUTE_UNUSED
;
5107 /* If we put this reload ahead, thinking it is a group,
5108 then insist on finding a group. Otherwise we can grab a
5109 reg that some other reload needs.
5110 (That can happen when we have a 68000 DATA_OR_FP_REG
5111 which is a group of data regs or one fp reg.)
5112 We need not be so restrictive if there are no more reloads
5115 ??? Really it would be nicer to have smarter handling
5116 for that kind of reg class, where a problem like this is normal.
5117 Perhaps those classes should be avoided for reloading
5118 by use of more alternatives. */
5120 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
5122 /* If we want a single register and haven't yet found one,
5123 take any reg in the right class and not in use.
5124 If we want a consecutive group, here is where we look for it.
5126 We use two passes so we can first look for reload regs to
5127 reuse, which are already in use for other reloads in this insn,
5128 and only then use additional registers.
5129 I think that maximizing reuse is needed to make sure we don't
5130 run out of reload regs. Suppose we have three reloads, and
5131 reloads A and B can share regs. These need two regs.
5132 Suppose A and B are given different regs.
5133 That leaves none for C. */
5134 for (pass
= 0; pass
< 2; pass
++)
5136 /* I is the index in spill_regs.
5137 We advance it round-robin between insns to use all spill regs
5138 equally, so that inherited reloads have a chance
5139 of leapfrogging each other. */
5143 for (count
= 0; count
< n_spills
; count
++)
5145 int class = (int) rld
[r
].class;
5151 regnum
= spill_regs
[i
];
5153 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
5156 /* We check reload_reg_used to make sure we
5157 don't clobber the return register. */
5158 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5159 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
5160 rld
[r
].when_needed
, rld
[r
].in
,
5162 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5163 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
5164 /* Look first for regs to share, then for unshared. But
5165 don't share regs used for inherited reloads; they are
5166 the ones we want to preserve. */
5168 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5170 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5173 int nr
= HARD_REGNO_NREGS (regnum
, rld
[r
].mode
);
5174 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5175 (on 68000) got us two FP regs. If NR is 1,
5176 we would reject both of them. */
5179 /* If we need only one reg, we have already won. */
5182 /* But reject a single reg if we demand a group. */
5187 /* Otherwise check that as many consecutive regs as we need
5188 are available here. */
5191 int regno
= regnum
+ nr
- 1;
5192 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5193 && spill_reg_order
[regno
] >= 0
5194 && reload_reg_free_p (regno
, rld
[r
].opnum
,
5195 rld
[r
].when_needed
)))
5204 /* If we found something on pass 1, omit pass 2. */
5205 if (count
< n_spills
)
5209 /* We should have found a spill register by now. */
5210 if (count
>= n_spills
)
5213 /* I is the index in SPILL_REG_RTX of the reload register we are to
5214 allocate. Get an rtx for it and find its register number. */
5216 return set_reload_reg (i
, r
);
5219 /* Initialize all the tables needed to allocate reload registers.
5220 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5221 is the array we use to restore the reg_rtx field for every reload. */
5224 choose_reload_regs_init (chain
, save_reload_reg_rtx
)
5225 struct insn_chain
*chain
;
5226 rtx
*save_reload_reg_rtx
;
5230 for (i
= 0; i
< n_reloads
; i
++)
5231 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
5233 memset (reload_inherited
, 0, MAX_RELOADS
);
5234 memset ((char *) reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
5235 memset ((char *) reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
5237 CLEAR_HARD_REG_SET (reload_reg_used
);
5238 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5239 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5240 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5241 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5242 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5244 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5247 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
5248 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5249 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
5250 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5251 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
5252 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
5255 for (i
= 0; i
< reload_n_operands
; i
++)
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5258 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5259 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5260 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5261 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5262 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5265 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
5267 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5269 for (i
= 0; i
< n_reloads
; i
++)
5270 /* If we have already decided to use a certain register,
5271 don't use it in another way. */
5273 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
5274 rld
[i
].when_needed
, rld
[i
].mode
);
5277 /* Assign hard reg targets for the pseudo-registers we must reload
5278 into hard regs for this insn.
5279 Also output the instructions to copy them in and out of the hard regs.
5281 For machines with register classes, we are responsible for
5282 finding a reload reg in the proper class. */
5285 choose_reload_regs (chain
)
5286 struct insn_chain
*chain
;
5288 rtx insn
= chain
->insn
;
5290 unsigned int max_group_size
= 1;
5291 enum reg_class group_class
= NO_REGS
;
5292 int pass
, win
, inheritance
;
5294 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5296 /* In order to be certain of getting the registers we need,
5297 we must sort the reloads into order of increasing register class.
5298 Then our grabbing of reload registers will parallel the process
5299 that provided the reload registers.
5301 Also note whether any of the reloads wants a consecutive group of regs.
5302 If so, record the maximum size of the group desired and what
5303 register class contains all the groups needed by this insn. */
5305 for (j
= 0; j
< n_reloads
; j
++)
5307 reload_order
[j
] = j
;
5308 reload_spill_index
[j
] = -1;
5310 if (rld
[j
].nregs
> 1)
5312 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
5314 = reg_class_superunion
[(int) rld
[j
].class][(int)group_class
];
5317 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
5321 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5323 /* If -O, try first with inheritance, then turning it off.
5324 If not -O, don't do inheritance.
5325 Using inheritance when not optimizing leads to paradoxes
5326 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5327 because one side of the comparison might be inherited. */
5329 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5331 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5333 /* Process the reloads in order of preference just found.
5334 Beyond this point, subregs can be found in reload_reg_rtx.
5336 This used to look for an existing reloaded home for all of the
5337 reloads, and only then perform any new reloads. But that could lose
5338 if the reloads were done out of reg-class order because a later
5339 reload with a looser constraint might have an old home in a register
5340 needed by an earlier reload with a tighter constraint.
5342 To solve this, we make two passes over the reloads, in the order
5343 described above. In the first pass we try to inherit a reload
5344 from a previous insn. If there is a later reload that needs a
5345 class that is a proper subset of the class being processed, we must
5346 also allocate a spill register during the first pass.
5348 Then make a second pass over the reloads to allocate any reloads
5349 that haven't been given registers yet. */
5351 for (j
= 0; j
< n_reloads
; j
++)
5353 register int r
= reload_order
[j
];
5354 rtx search_equiv
= NULL_RTX
;
5356 /* Ignore reloads that got marked inoperative. */
5357 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
5358 && ! rld
[r
].secondary_p
)
5361 /* If find_reloads chose to use reload_in or reload_out as a reload
5362 register, we don't need to chose one. Otherwise, try even if it
5363 found one since we might save an insn if we find the value lying
5365 Try also when reload_in is a pseudo without a hard reg. */
5366 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
5367 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
5368 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
5369 && GET_CODE (rld
[r
].in
) != MEM
5370 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
5373 #if 0 /* No longer needed for correct operation.
5374 It might give better code, or might not; worth an experiment? */
5375 /* If this is an optional reload, we can't inherit from earlier insns
5376 until we are sure that any non-optional reloads have been allocated.
5377 The following code takes advantage of the fact that optional reloads
5378 are at the end of reload_order. */
5379 if (rld
[r
].optional
!= 0)
5380 for (i
= 0; i
< j
; i
++)
5381 if ((rld
[reload_order
[i
]].out
!= 0
5382 || rld
[reload_order
[i
]].in
!= 0
5383 || rld
[reload_order
[i
]].secondary_p
)
5384 && ! rld
[reload_order
[i
]].optional
5385 && rld
[reload_order
[i
]].reg_rtx
== 0)
5386 allocate_reload_reg (chain
, reload_order
[i
], 0);
5389 /* First see if this pseudo is already available as reloaded
5390 for a previous insn. We cannot try to inherit for reloads
5391 that are smaller than the maximum number of registers needed
5392 for groups unless the register we would allocate cannot be used
5395 We could check here to see if this is a secondary reload for
5396 an object that is already in a register of the desired class.
5397 This would avoid the need for the secondary reload register.
5398 But this is complex because we can't easily determine what
5399 objects might want to be loaded via this reload. So let a
5400 register be allocated here. In `emit_reload_insns' we suppress
5401 one of the loads in the case described above. */
5406 register int regno
= -1;
5407 enum machine_mode mode
= VOIDmode
;
5411 else if (GET_CODE (rld
[r
].in
) == REG
)
5413 regno
= REGNO (rld
[r
].in
);
5414 mode
= GET_MODE (rld
[r
].in
);
5416 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
5418 regno
= REGNO (rld
[r
].in_reg
);
5419 mode
= GET_MODE (rld
[r
].in_reg
);
5421 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
5422 && GET_CODE (SUBREG_REG (rld
[r
].in_reg
)) == REG
)
5424 byte
= SUBREG_BYTE (rld
[r
].in_reg
);
5425 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
5426 if (regno
< FIRST_PSEUDO_REGISTER
)
5427 regno
= subreg_regno (rld
[r
].in_reg
);
5428 mode
= GET_MODE (rld
[r
].in_reg
);
5431 else if ((GET_CODE (rld
[r
].in_reg
) == PRE_INC
5432 || GET_CODE (rld
[r
].in_reg
) == PRE_DEC
5433 || GET_CODE (rld
[r
].in_reg
) == POST_INC
5434 || GET_CODE (rld
[r
].in_reg
) == POST_DEC
)
5435 && GET_CODE (XEXP (rld
[r
].in_reg
, 0)) == REG
)
5437 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
5438 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
5439 rld
[r
].out
= rld
[r
].in
;
5443 /* This won't work, since REGNO can be a pseudo reg number.
5444 Also, it takes much more hair to keep track of all the things
5445 that can invalidate an inherited reload of part of a pseudoreg. */
5446 else if (GET_CODE (rld
[r
].in
) == SUBREG
5447 && GET_CODE (SUBREG_REG (rld
[r
].in
)) == REG
)
5448 regno
= subreg_regno (rld
[r
].in
);
5451 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5453 enum reg_class
class = rld
[r
].class, last_class
;
5454 rtx last_reg
= reg_last_reload_reg
[regno
];
5455 enum machine_mode need_mode
;
5457 i
= REGNO (last_reg
);
5458 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
5459 last_class
= REGNO_REG_CLASS (i
);
5465 = smallest_mode_for_size (GET_MODE_SIZE (mode
) + byte
,
5466 GET_MODE_CLASS (mode
));
5469 #ifdef CLASS_CANNOT_CHANGE_MODE
5471 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
], i
)
5472 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg
),
5474 : (GET_MODE_SIZE (GET_MODE (last_reg
))
5475 >= GET_MODE_SIZE (need_mode
)))
5477 (GET_MODE_SIZE (GET_MODE (last_reg
))
5478 >= GET_MODE_SIZE (need_mode
))
5480 && reg_reloaded_contents
[i
] == regno
5481 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5482 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
5483 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5484 /* Even if we can't use this register as a reload
5485 register, we might use it for reload_override_in,
5486 if copying it to the desired class is cheap
5488 || ((REGISTER_MOVE_COST (mode
, last_class
, class)
5489 < MEMORY_MOVE_COST (mode
, class, 1))
5490 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5491 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5495 #ifdef SECONDARY_MEMORY_NEEDED
5496 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5501 && (rld
[r
].nregs
== max_group_size
5502 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5504 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
5505 rld
[r
].when_needed
, rld
[r
].in
,
5508 /* If a group is needed, verify that all the subsequent
5509 registers still have their values intact. */
5510 int nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5513 for (k
= 1; k
< nr
; k
++)
5514 if (reg_reloaded_contents
[i
+ k
] != regno
5515 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5523 last_reg
= (GET_MODE (last_reg
) == mode
5524 ? last_reg
: gen_rtx_REG (mode
, i
));
5527 for (k
= 0; k
< nr
; k
++)
5528 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5531 /* We found a register that contains the
5532 value we need. If this register is the
5533 same as an `earlyclobber' operand of the
5534 current insn, just mark it as a place to
5535 reload from since we can't use it as the
5536 reload register itself. */
5538 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5539 if (reg_overlap_mentioned_for_reload_p
5540 (reg_last_reload_reg
[regno
],
5541 reload_earlyclobbers
[i1
]))
5544 if (i1
!= n_earlyclobbers
5545 || ! (free_for_value_p (i
, rld
[r
].mode
,
5547 rld
[r
].when_needed
, rld
[r
].in
,
5549 /* Don't use it if we'd clobber a pseudo reg. */
5550 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5552 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5553 /* Don't clobber the frame pointer. */
5554 || (i
== HARD_FRAME_POINTER_REGNUM
5556 /* Don't really use the inherited spill reg
5557 if we need it wider than we've got it. */
5558 || (GET_MODE_SIZE (rld
[r
].mode
)
5559 > GET_MODE_SIZE (mode
))
5562 /* If find_reloads chose reload_out as reload
5563 register, stay with it - that leaves the
5564 inherited register for subsequent reloads. */
5565 || (rld
[r
].out
&& rld
[r
].reg_rtx
5566 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
5568 if (! rld
[r
].optional
)
5570 reload_override_in
[r
] = last_reg
;
5571 reload_inheritance_insn
[r
]
5572 = reg_reloaded_insn
[i
];
5578 /* We can use this as a reload reg. */
5579 /* Mark the register as in use for this part of
5581 mark_reload_reg_in_use (i
,
5585 rld
[r
].reg_rtx
= last_reg
;
5586 reload_inherited
[r
] = 1;
5587 reload_inheritance_insn
[r
]
5588 = reg_reloaded_insn
[i
];
5589 reload_spill_index
[r
] = i
;
5590 for (k
= 0; k
< nr
; k
++)
5591 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5599 /* Here's another way to see if the value is already lying around. */
5602 && ! reload_inherited
[r
]
5604 && (CONSTANT_P (rld
[r
].in
)
5605 || GET_CODE (rld
[r
].in
) == PLUS
5606 || GET_CODE (rld
[r
].in
) == REG
5607 || GET_CODE (rld
[r
].in
) == MEM
)
5608 && (rld
[r
].nregs
== max_group_size
5609 || ! reg_classes_intersect_p (rld
[r
].class, group_class
)))
5610 search_equiv
= rld
[r
].in
;
5611 /* If this is an output reload from a simple move insn, look
5612 if an equivalence for the input is available. */
5613 else if (inheritance
&& rld
[r
].in
== 0 && rld
[r
].out
!= 0)
5615 rtx set
= single_set (insn
);
5618 && rtx_equal_p (rld
[r
].out
, SET_DEST (set
))
5619 && CONSTANT_P (SET_SRC (set
)))
5620 search_equiv
= SET_SRC (set
);
5626 = find_equiv_reg (search_equiv
, insn
, rld
[r
].class,
5627 -1, NULL
, 0, rld
[r
].mode
);
5632 if (GET_CODE (equiv
) == REG
)
5633 regno
= REGNO (equiv
);
5634 else if (GET_CODE (equiv
) == SUBREG
)
5636 /* This must be a SUBREG of a hard register.
5637 Make a new REG since this might be used in an
5638 address and not all machines support SUBREGs
5640 regno
= subreg_regno (equiv
);
5641 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
5647 /* If we found a spill reg, reject it unless it is free
5648 and of the desired class. */
5650 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
)
5651 && ! free_for_value_p (regno
, rld
[r
].mode
,
5652 rld
[r
].opnum
, rld
[r
].when_needed
,
5653 rld
[r
].in
, rld
[r
].out
, r
, 1))
5654 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].class],
5658 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
5661 /* We found a register that contains the value we need.
5662 If this register is the same as an `earlyclobber' operand
5663 of the current insn, just mark it as a place to reload from
5664 since we can't use it as the reload register itself. */
5667 for (i
= 0; i
< n_earlyclobbers
; i
++)
5668 if (reg_overlap_mentioned_for_reload_p (equiv
,
5669 reload_earlyclobbers
[i
]))
5671 if (! rld
[r
].optional
)
5672 reload_override_in
[r
] = equiv
;
5677 /* If the equiv register we have found is explicitly clobbered
5678 in the current insn, it depends on the reload type if we
5679 can use it, use it for reload_override_in, or not at all.
5680 In particular, we then can't use EQUIV for a
5681 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5685 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 0))
5686 switch (rld
[r
].when_needed
)
5688 case RELOAD_FOR_OTHER_ADDRESS
:
5689 case RELOAD_FOR_INPADDR_ADDRESS
:
5690 case RELOAD_FOR_INPUT_ADDRESS
:
5691 case RELOAD_FOR_OPADDR_ADDR
:
5694 case RELOAD_FOR_INPUT
:
5695 case RELOAD_FOR_OPERAND_ADDRESS
:
5696 if (! rld
[r
].optional
)
5697 reload_override_in
[r
] = equiv
;
5703 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
5704 switch (rld
[r
].when_needed
)
5706 case RELOAD_FOR_OTHER_ADDRESS
:
5707 case RELOAD_FOR_INPADDR_ADDRESS
:
5708 case RELOAD_FOR_INPUT_ADDRESS
:
5709 case RELOAD_FOR_OPADDR_ADDR
:
5710 case RELOAD_FOR_OPERAND_ADDRESS
:
5711 case RELOAD_FOR_INPUT
:
5714 if (! rld
[r
].optional
)
5715 reload_override_in
[r
] = equiv
;
5723 /* If we found an equivalent reg, say no code need be generated
5724 to load it, and use it as our reload reg. */
5725 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
5727 int nr
= HARD_REGNO_NREGS (regno
, rld
[r
].mode
);
5729 rld
[r
].reg_rtx
= equiv
;
5730 reload_inherited
[r
] = 1;
5732 /* If reg_reloaded_valid is not set for this register,
5733 there might be a stale spill_reg_store lying around.
5734 We must clear it, since otherwise emit_reload_insns
5735 might delete the store. */
5736 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
5737 spill_reg_store
[regno
] = NULL_RTX
;
5738 /* If any of the hard registers in EQUIV are spill
5739 registers, mark them as in use for this insn. */
5740 for (k
= 0; k
< nr
; k
++)
5742 i
= spill_reg_order
[regno
+ k
];
5745 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
5748 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
5755 /* If we found a register to use already, or if this is an optional
5756 reload, we are done. */
5757 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
5761 /* No longer needed for correct operation. Might or might
5762 not give better code on the average. Want to experiment? */
5764 /* See if there is a later reload that has a class different from our
5765 class that intersects our class or that requires less register
5766 than our reload. If so, we must allocate a register to this
5767 reload now, since that reload might inherit a previous reload
5768 and take the only available register in our class. Don't do this
5769 for optional reloads since they will force all previous reloads
5770 to be allocated. Also don't do this for reloads that have been
5773 for (i
= j
+ 1; i
< n_reloads
; i
++)
5775 int s
= reload_order
[i
];
5777 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
5778 && ! rld
[s
].secondary_p
)
5782 if ((rld
[s
].class != rld
[r
].class
5783 && reg_classes_intersect_p (rld
[r
].class,
5785 || rld
[s
].nregs
< rld
[r
].nregs
)
5792 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
5796 /* Now allocate reload registers for anything non-optional that
5797 didn't get one yet. */
5798 for (j
= 0; j
< n_reloads
; j
++)
5800 register int r
= reload_order
[j
];
5802 /* Ignore reloads that got marked inoperative. */
5803 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
5806 /* Skip reloads that already have a register allocated or are
5808 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
5811 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
5815 /* If that loop got all the way, we have won. */
5822 /* Loop around and try without any inheritance. */
5827 /* First undo everything done by the failed attempt
5828 to allocate with inheritance. */
5829 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
5831 /* Some sanity tests to verify that the reloads found in the first
5832 pass are identical to the ones we have now. */
5833 if (chain
->n_reloads
!= n_reloads
)
5836 for (i
= 0; i
< n_reloads
; i
++)
5838 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
5840 if (chain
->rld
[i
].when_needed
!= rld
[i
].when_needed
)
5842 for (j
= 0; j
< n_spills
; j
++)
5843 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
5844 if (! set_reload_reg (j
, i
))
5845 failed_reload (chain
->insn
, i
);
5849 /* If we thought we could inherit a reload, because it seemed that
5850 nothing else wanted the same reload register earlier in the insn,
5851 verify that assumption, now that all reloads have been assigned.
5852 Likewise for reloads where reload_override_in has been set. */
5854 /* If doing expensive optimizations, do one preliminary pass that doesn't
5855 cancel any inheritance, but removes reloads that have been needed only
5856 for reloads that we know can be inherited. */
5857 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
5859 for (j
= 0; j
< n_reloads
; j
++)
5861 register int r
= reload_order
[j
];
5863 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
5864 check_reg
= rld
[r
].reg_rtx
;
5865 else if (reload_override_in
[r
]
5866 && (GET_CODE (reload_override_in
[r
]) == REG
5867 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5868 check_reg
= reload_override_in
[r
];
5871 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
5872 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
5873 (reload_inherited
[r
]
5874 ? rld
[r
].out
: const0_rtx
),
5879 reload_inherited
[r
] = 0;
5880 reload_override_in
[r
] = 0;
5882 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5883 reload_override_in, then we do not need its related
5884 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5885 likewise for other reload types.
5886 We handle this by removing a reload when its only replacement
5887 is mentioned in reload_in of the reload we are going to inherit.
5888 A special case are auto_inc expressions; even if the input is
5889 inherited, we still need the address for the output. We can
5890 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5891 If we suceeded removing some reload and we are doing a preliminary
5892 pass just to remove such reloads, make another pass, since the
5893 removal of one reload might allow us to inherit another one. */
5895 && rld
[r
].out
!= rld
[r
].in
5896 && remove_address_replacements (rld
[r
].in
) && pass
)
5901 /* Now that reload_override_in is known valid,
5902 actually override reload_in. */
5903 for (j
= 0; j
< n_reloads
; j
++)
5904 if (reload_override_in
[j
])
5905 rld
[j
].in
= reload_override_in
[j
];
5907 /* If this reload won't be done because it has been cancelled or is
5908 optional and not inherited, clear reload_reg_rtx so other
5909 routines (such as subst_reloads) don't get confused. */
5910 for (j
= 0; j
< n_reloads
; j
++)
5911 if (rld
[j
].reg_rtx
!= 0
5912 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
5913 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
5914 && ! rld
[j
].secondary_p
)))
5916 int regno
= true_regnum (rld
[j
].reg_rtx
);
5918 if (spill_reg_order
[regno
] >= 0)
5919 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
5920 rld
[j
].when_needed
, rld
[j
].mode
);
5922 reload_spill_index
[j
] = -1;
5925 /* Record which pseudos and which spill regs have output reloads. */
5926 for (j
= 0; j
< n_reloads
; j
++)
5928 register int r
= reload_order
[j
];
5930 i
= reload_spill_index
[r
];
5932 /* I is nonneg if this reload uses a register.
5933 If rld[r].reg_rtx is 0, this is an optional reload
5934 that we opted to ignore. */
5935 if (rld
[r
].out_reg
!= 0 && GET_CODE (rld
[r
].out_reg
) == REG
5936 && rld
[r
].reg_rtx
!= 0)
5938 register int nregno
= REGNO (rld
[r
].out_reg
);
5941 if (nregno
< FIRST_PSEUDO_REGISTER
)
5942 nr
= HARD_REGNO_NREGS (nregno
, rld
[r
].mode
);
5945 reg_has_output_reload
[nregno
+ nr
] = 1;
5949 nr
= HARD_REGNO_NREGS (i
, rld
[r
].mode
);
5951 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
5954 if (rld
[r
].when_needed
!= RELOAD_OTHER
5955 && rld
[r
].when_needed
!= RELOAD_FOR_OUTPUT
5956 && rld
[r
].when_needed
!= RELOAD_FOR_INSN
)
5962 /* Deallocate the reload register for reload R. This is called from
5963 remove_address_replacements. */
5966 deallocate_reload_reg (r
)
5971 if (! rld
[r
].reg_rtx
)
5973 regno
= true_regnum (rld
[r
].reg_rtx
);
5975 if (spill_reg_order
[regno
] >= 0)
5976 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
5978 reload_spill_index
[r
] = -1;
5981 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5982 reloads of the same item for fear that we might not have enough reload
5983 registers. However, normally they will get the same reload register
5984 and hence actually need not be loaded twice.
5986 Here we check for the most common case of this phenomenon: when we have
5987 a number of reloads for the same object, each of which were allocated
5988 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5989 reload, and is not modified in the insn itself. If we find such,
5990 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5991 This will not increase the number of spill registers needed and will
5992 prevent redundant code. */
5995 merge_assigned_reloads (insn
)
6000 /* Scan all the reloads looking for ones that only load values and
6001 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6002 assigned and not modified by INSN. */
6004 for (i
= 0; i
< n_reloads
; i
++)
6006 int conflicting_input
= 0;
6007 int max_input_address_opnum
= -1;
6008 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6010 if (rld
[i
].in
== 0 || rld
[i
].when_needed
== RELOAD_OTHER
6011 || rld
[i
].out
!= 0 || rld
[i
].reg_rtx
== 0
6012 || reg_set_p (rld
[i
].reg_rtx
, insn
))
6015 /* Look at all other reloads. Ensure that the only use of this
6016 reload_reg_rtx is in a reload that just loads the same value
6017 as we do. Note that any secondary reloads must be of the identical
6018 class since the values, modes, and result registers are the
6019 same, so we need not do anything with any secondary reloads. */
6021 for (j
= 0; j
< n_reloads
; j
++)
6023 if (i
== j
|| rld
[j
].reg_rtx
== 0
6024 || ! reg_overlap_mentioned_p (rld
[j
].reg_rtx
,
6028 if (rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6029 && rld
[j
].opnum
> max_input_address_opnum
)
6030 max_input_address_opnum
= rld
[j
].opnum
;
6032 /* If the reload regs aren't exactly the same (e.g, different modes)
6033 or if the values are different, we can't merge this reload.
6034 But if it is an input reload, we might still merge
6035 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6037 if (! rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6038 || rld
[j
].out
!= 0 || rld
[j
].in
== 0
6039 || ! rtx_equal_p (rld
[i
].in
, rld
[j
].in
))
6041 if (rld
[j
].when_needed
!= RELOAD_FOR_INPUT
6042 || ((rld
[i
].when_needed
!= RELOAD_FOR_INPUT_ADDRESS
6043 || rld
[i
].opnum
> rld
[j
].opnum
)
6044 && rld
[i
].when_needed
!= RELOAD_FOR_OTHER_ADDRESS
))
6046 conflicting_input
= 1;
6047 if (min_conflicting_input_opnum
> rld
[j
].opnum
)
6048 min_conflicting_input_opnum
= rld
[j
].opnum
;
6052 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6053 we, in fact, found any matching reloads. */
6056 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6058 for (j
= 0; j
< n_reloads
; j
++)
6059 if (i
!= j
&& rld
[j
].reg_rtx
!= 0
6060 && rtx_equal_p (rld
[i
].reg_rtx
, rld
[j
].reg_rtx
)
6061 && (! conflicting_input
6062 || rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6063 || rld
[j
].when_needed
== RELOAD_FOR_OTHER_ADDRESS
))
6065 rld
[i
].when_needed
= RELOAD_OTHER
;
6067 reload_spill_index
[j
] = -1;
6068 transfer_replacements (i
, j
);
6071 /* If this is now RELOAD_OTHER, look for any reloads that load
6072 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6073 if they were for inputs, RELOAD_OTHER for outputs. Note that
6074 this test is equivalent to looking for reloads for this operand
6077 if (rld
[i
].when_needed
== RELOAD_OTHER
)
6078 for (j
= 0; j
< n_reloads
; j
++)
6080 && rld
[j
].when_needed
!= RELOAD_OTHER
6081 && reg_overlap_mentioned_for_reload_p (rld
[j
].in
,
6084 = ((rld
[j
].when_needed
== RELOAD_FOR_INPUT_ADDRESS
6085 || rld
[j
].when_needed
== RELOAD_FOR_INPADDR_ADDRESS
)
6086 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6091 /* These arrays are filled by emit_reload_insns and its subroutines. */
6092 static rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6093 static rtx other_input_address_reload_insns
= 0;
6094 static rtx other_input_reload_insns
= 0;
6095 static rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6096 static rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6097 static rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6098 static rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6099 static rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6100 static rtx operand_reload_insns
= 0;
6101 static rtx other_operand_reload_insns
= 0;
6102 static rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6104 /* Values to be put in spill_reg_store are put here first. */
6105 static rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6106 static HARD_REG_SET reg_reloaded_died
;
6108 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6109 has the number J. OLD contains the value to be used as input. */
6112 emit_input_reload_insns (chain
, rl
, old
, j
)
6113 struct insn_chain
*chain
;
6118 rtx insn
= chain
->insn
;
6119 register rtx reloadreg
= rl
->reg_rtx
;
6120 rtx oldequiv_reg
= 0;
6123 enum machine_mode mode
;
6126 /* Determine the mode to reload in.
6127 This is very tricky because we have three to choose from.
6128 There is the mode the insn operand wants (rl->inmode).
6129 There is the mode of the reload register RELOADREG.
6130 There is the intrinsic mode of the operand, which we could find
6131 by stripping some SUBREGs.
6132 It turns out that RELOADREG's mode is irrelevant:
6133 we can change that arbitrarily.
6135 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6136 then the reload reg may not support QImode moves, so use SImode.
6137 If foo is in memory due to spilling a pseudo reg, this is safe,
6138 because the QImode value is in the least significant part of a
6139 slot big enough for a SImode. If foo is some other sort of
6140 memory reference, then it is impossible to reload this case,
6141 so previous passes had better make sure this never happens.
6143 Then consider a one-word union which has SImode and one of its
6144 members is a float, being fetched as (SUBREG:SF union:SI).
6145 We must fetch that as SFmode because we could be loading into
6146 a float-only register. In this case OLD's mode is correct.
6148 Consider an immediate integer: it has VOIDmode. Here we need
6149 to get a mode from something else.
6151 In some cases, there is a fourth mode, the operand's
6152 containing mode. If the insn specifies a containing mode for
6153 this operand, it overrides all others.
6155 I am not sure whether the algorithm here is always right,
6156 but it does the right things in those cases. */
6158 mode
= GET_MODE (old
);
6159 if (mode
== VOIDmode
)
6162 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6163 /* If we need a secondary register for this operation, see if
6164 the value is already in a register in that class. Don't
6165 do this if the secondary register will be used as a scratch
6168 if (rl
->secondary_in_reload
>= 0
6169 && rl
->secondary_in_icode
== CODE_FOR_nothing
6172 = find_equiv_reg (old
, insn
,
6173 rld
[rl
->secondary_in_reload
].class,
6177 /* If reloading from memory, see if there is a register
6178 that already holds the same value. If so, reload from there.
6179 We can pass 0 as the reload_reg_p argument because
6180 any other reload has either already been emitted,
6181 in which case find_equiv_reg will see the reload-insn,
6182 or has yet to be emitted, in which case it doesn't matter
6183 because we will use this equiv reg right away. */
6185 if (oldequiv
== 0 && optimize
6186 && (GET_CODE (old
) == MEM
6187 || (GET_CODE (old
) == REG
6188 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6189 && reg_renumber
[REGNO (old
)] < 0)))
6190 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
, -1, NULL
, 0, mode
);
6194 unsigned int regno
= true_regnum (oldequiv
);
6196 /* Don't use OLDEQUIV if any other reload changes it at an
6197 earlier stage of this insn or at this stage. */
6198 if (! free_for_value_p (regno
, rl
->mode
, rl
->opnum
, rl
->when_needed
,
6199 rl
->in
, const0_rtx
, j
, 0))
6202 /* If it is no cheaper to copy from OLDEQUIV into the
6203 reload register than it would be to move from memory,
6204 don't use it. Likewise, if we need a secondary register
6208 && ((REGNO_REG_CLASS (regno
) != rl
->class
6209 && (REGISTER_MOVE_COST (mode
, REGNO_REG_CLASS (regno
),
6211 >= MEMORY_MOVE_COST (mode
, rl
->class, 1)))
6212 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6213 || (SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6217 #ifdef SECONDARY_MEMORY_NEEDED
6218 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6226 /* delete_output_reload is only invoked properly if old contains
6227 the original pseudo register. Since this is replaced with a
6228 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6229 find the pseudo in RELOAD_IN_REG. */
6231 && reload_override_in
[j
]
6232 && GET_CODE (rl
->in_reg
) == REG
)
6239 else if (GET_CODE (oldequiv
) == REG
)
6240 oldequiv_reg
= oldequiv
;
6241 else if (GET_CODE (oldequiv
) == SUBREG
)
6242 oldequiv_reg
= SUBREG_REG (oldequiv
);
6244 /* If we are reloading from a register that was recently stored in
6245 with an output-reload, see if we can prove there was
6246 actually no need to store the old value in it. */
6248 if (optimize
&& GET_CODE (oldequiv
) == REG
6249 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6250 && spill_reg_store
[REGNO (oldequiv
)]
6251 && GET_CODE (old
) == REG
6252 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6253 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6255 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6257 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6258 then load RELOADREG from OLDEQUIV. Note that we cannot use
6259 gen_lowpart_common since it can do the wrong thing when
6260 RELOADREG has a multi-word mode. Note that RELOADREG
6261 must always be a REG here. */
6263 if (GET_MODE (reloadreg
) != mode
)
6264 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6265 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6266 oldequiv
= SUBREG_REG (oldequiv
);
6267 if (GET_MODE (oldequiv
) != VOIDmode
6268 && mode
!= GET_MODE (oldequiv
))
6269 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
6271 /* Switch to the right place to emit the reload insns. */
6272 switch (rl
->when_needed
)
6275 where
= &other_input_reload_insns
;
6277 case RELOAD_FOR_INPUT
:
6278 where
= &input_reload_insns
[rl
->opnum
];
6280 case RELOAD_FOR_INPUT_ADDRESS
:
6281 where
= &input_address_reload_insns
[rl
->opnum
];
6283 case RELOAD_FOR_INPADDR_ADDRESS
:
6284 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
6286 case RELOAD_FOR_OUTPUT_ADDRESS
:
6287 where
= &output_address_reload_insns
[rl
->opnum
];
6289 case RELOAD_FOR_OUTADDR_ADDRESS
:
6290 where
= &outaddr_address_reload_insns
[rl
->opnum
];
6292 case RELOAD_FOR_OPERAND_ADDRESS
:
6293 where
= &operand_reload_insns
;
6295 case RELOAD_FOR_OPADDR_ADDR
:
6296 where
= &other_operand_reload_insns
;
6298 case RELOAD_FOR_OTHER_ADDRESS
:
6299 where
= &other_input_address_reload_insns
;
6305 push_to_sequence (*where
);
6307 /* Auto-increment addresses must be reloaded in a special way. */
6308 if (rl
->out
&& ! rl
->out_reg
)
6310 /* We are not going to bother supporting the case where a
6311 incremented register can't be copied directly from
6312 OLDEQUIV since this seems highly unlikely. */
6313 if (rl
->secondary_in_reload
>= 0)
6316 if (reload_inherited
[j
])
6317 oldequiv
= reloadreg
;
6319 old
= XEXP (rl
->in_reg
, 0);
6321 if (optimize
&& GET_CODE (oldequiv
) == REG
6322 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6323 && spill_reg_store
[REGNO (oldequiv
)]
6324 && GET_CODE (old
) == REG
6325 && (dead_or_set_p (insn
,
6326 spill_reg_stored_to
[REGNO (oldequiv
)])
6327 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6329 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6331 /* Prevent normal processing of this reload. */
6333 /* Output a special code sequence for this case. */
6334 new_spill_reg_store
[REGNO (reloadreg
)]
6335 = inc_for_reload (reloadreg
, oldequiv
, rl
->out
,
6339 /* If we are reloading a pseudo-register that was set by the previous
6340 insn, see if we can get rid of that pseudo-register entirely
6341 by redirecting the previous insn into our reload register. */
6343 else if (optimize
&& GET_CODE (old
) == REG
6344 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6345 && dead_or_set_p (insn
, old
)
6346 /* This is unsafe if some other reload
6347 uses the same reg first. */
6348 && ! conflicts_with_override (reloadreg
)
6349 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
6350 rl
->when_needed
, old
, rl
->out
, j
, 0))
6352 rtx temp
= PREV_INSN (insn
);
6353 while (temp
&& GET_CODE (temp
) == NOTE
)
6354 temp
= PREV_INSN (temp
);
6356 && GET_CODE (temp
) == INSN
6357 && GET_CODE (PATTERN (temp
)) == SET
6358 && SET_DEST (PATTERN (temp
)) == old
6359 /* Make sure we can access insn_operand_constraint. */
6360 && asm_noperands (PATTERN (temp
)) < 0
6361 /* This is unsafe if prev insn rejects our reload reg. */
6362 && constraint_accepts_reg_p (insn_data
[recog_memoized (temp
)].operand
[0].constraint
,
6364 /* This is unsafe if operand occurs more than once in current
6365 insn. Perhaps some occurrences aren't reloaded. */
6366 && count_occurrences (PATTERN (insn
), old
, 0) == 1
6367 /* Don't risk splitting a matching pair of operands. */
6368 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
6370 /* Store into the reload register instead of the pseudo. */
6371 SET_DEST (PATTERN (temp
)) = reloadreg
;
6373 /* If the previous insn is an output reload, the source is
6374 a reload register, and its spill_reg_store entry will
6375 contain the previous destination. This is now
6377 if (GET_CODE (SET_SRC (PATTERN (temp
))) == REG
6378 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6380 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6381 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6384 /* If these are the only uses of the pseudo reg,
6385 pretend for GDB it lives in the reload reg we used. */
6386 if (REG_N_DEATHS (REGNO (old
)) == 1
6387 && REG_N_SETS (REGNO (old
)) == 1)
6389 reg_renumber
[REGNO (old
)] = REGNO (rl
->reg_rtx
);
6390 alter_reg (REGNO (old
), -1);
6396 /* We can't do that, so output an insn to load RELOADREG. */
6398 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6399 /* If we have a secondary reload, pick up the secondary register
6400 and icode, if any. If OLDEQUIV and OLD are different or
6401 if this is an in-out reload, recompute whether or not we
6402 still need a secondary register and what the icode should
6403 be. If we still need a secondary register and the class or
6404 icode is different, go back to reloading from OLD if using
6405 OLDEQUIV means that we got the wrong type of register. We
6406 cannot have different class or icode due to an in-out reload
6407 because we don't make such reloads when both the input and
6408 output need secondary reload registers. */
6410 if (! special
&& rl
->secondary_in_reload
>= 0)
6412 rtx second_reload_reg
= 0;
6413 int secondary_reload
= rl
->secondary_in_reload
;
6414 rtx real_oldequiv
= oldequiv
;
6417 enum insn_code icode
;
6419 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6420 and similarly for OLD.
6421 See comments in get_secondary_reload in reload.c. */
6422 /* If it is a pseudo that cannot be replaced with its
6423 equivalent MEM, we must fall back to reload_in, which
6424 will have all the necessary substitutions registered.
6425 Likewise for a pseudo that can't be replaced with its
6426 equivalent constant.
6428 Take extra care for subregs of such pseudos. Note that
6429 we cannot use reg_equiv_mem in this case because it is
6430 not in the right mode. */
6433 if (GET_CODE (tmp
) == SUBREG
)
6434 tmp
= SUBREG_REG (tmp
);
6435 if (GET_CODE (tmp
) == REG
6436 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6437 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6438 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6440 if (! reg_equiv_mem
[REGNO (tmp
)]
6441 || num_not_at_initial_offset
6442 || GET_CODE (oldequiv
) == SUBREG
)
6443 real_oldequiv
= rl
->in
;
6445 real_oldequiv
= reg_equiv_mem
[REGNO (tmp
)];
6449 if (GET_CODE (tmp
) == SUBREG
)
6450 tmp
= SUBREG_REG (tmp
);
6451 if (GET_CODE (tmp
) == REG
6452 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
6453 && (reg_equiv_memory_loc
[REGNO (tmp
)] != 0
6454 || reg_equiv_constant
[REGNO (tmp
)] != 0))
6456 if (! reg_equiv_mem
[REGNO (tmp
)]
6457 || num_not_at_initial_offset
6458 || GET_CODE (old
) == SUBREG
)
6461 real_old
= reg_equiv_mem
[REGNO (tmp
)];
6464 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
6465 icode
= rl
->secondary_in_icode
;
6467 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6468 || (rl
->in
!= 0 && rl
->out
!= 0))
6470 enum reg_class new_class
6471 = SECONDARY_INPUT_RELOAD_CLASS (rl
->class,
6472 mode
, real_oldequiv
);
6474 if (new_class
== NO_REGS
)
6475 second_reload_reg
= 0;
6478 enum insn_code new_icode
;
6479 enum machine_mode new_mode
;
6481 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6482 REGNO (second_reload_reg
)))
6483 oldequiv
= old
, real_oldequiv
= real_old
;
6486 new_icode
= reload_in_optab
[(int) mode
];
6487 if (new_icode
!= CODE_FOR_nothing
6488 && ((insn_data
[(int) new_icode
].operand
[0].predicate
6489 && ! ((*insn_data
[(int) new_icode
].operand
[0].predicate
)
6491 || (insn_data
[(int) new_icode
].operand
[1].predicate
6492 && ! ((*insn_data
[(int) new_icode
].operand
[1].predicate
)
6493 (real_oldequiv
, mode
)))))
6494 new_icode
= CODE_FOR_nothing
;
6496 if (new_icode
== CODE_FOR_nothing
)
6499 new_mode
= insn_data
[(int) new_icode
].operand
[2].mode
;
6501 if (GET_MODE (second_reload_reg
) != new_mode
)
6503 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6505 oldequiv
= old
, real_oldequiv
= real_old
;
6508 = gen_rtx_REG (new_mode
,
6509 REGNO (second_reload_reg
));
6515 /* If we still need a secondary reload register, check
6516 to see if it is being used as a scratch or intermediate
6517 register and generate code appropriately. If we need
6518 a scratch register, use REAL_OLDEQUIV since the form of
6519 the insn may depend on the actual address if it is
6522 if (second_reload_reg
)
6524 if (icode
!= CODE_FOR_nothing
)
6526 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6527 second_reload_reg
));
6532 /* See if we need a scratch register to load the
6533 intermediate register (a tertiary reload). */
6534 enum insn_code tertiary_icode
6535 = rld
[secondary_reload
].secondary_in_icode
;
6537 if (tertiary_icode
!= CODE_FOR_nothing
)
6539 rtx third_reload_reg
6540 = rld
[rld
[secondary_reload
].secondary_in_reload
].reg_rtx
;
6542 emit_insn ((GEN_FCN (tertiary_icode
)
6543 (second_reload_reg
, real_oldequiv
,
6544 third_reload_reg
)));
6547 gen_reload (second_reload_reg
, real_oldequiv
,
6551 oldequiv
= second_reload_reg
;
6557 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6559 rtx real_oldequiv
= oldequiv
;
6561 if ((GET_CODE (oldequiv
) == REG
6562 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6563 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6564 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6565 || (GET_CODE (oldequiv
) == SUBREG
6566 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
6567 && (REGNO (SUBREG_REG (oldequiv
))
6568 >= FIRST_PSEUDO_REGISTER
)
6569 && ((reg_equiv_memory_loc
6570 [REGNO (SUBREG_REG (oldequiv
))] != 0)
6571 || (reg_equiv_constant
6572 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
6573 || (CONSTANT_P (oldequiv
)
6574 && PREFERRED_RELOAD_CLASS (oldequiv
,
6575 REGNO_REG_CLASS (REGNO (reloadreg
))) == NO_REGS
))
6576 real_oldequiv
= rl
->in
;
6577 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
6581 if (flag_non_call_exceptions
)
6582 copy_eh_notes (insn
, get_insns ());
6584 /* End this sequence. */
6585 *where
= get_insns ();
6588 /* Update reload_override_in so that delete_address_reloads_1
6589 can see the actual register usage. */
6591 reload_override_in
[j
] = oldequiv
;
6594 /* Generate insns to for the output reload RL, which is for the insn described
6595 by CHAIN and has the number J. */
6597 emit_output_reload_insns (chain
, rl
, j
)
6598 struct insn_chain
*chain
;
6602 rtx reloadreg
= rl
->reg_rtx
;
6603 rtx insn
= chain
->insn
;
6606 enum machine_mode mode
= GET_MODE (old
);
6609 if (rl
->when_needed
== RELOAD_OTHER
)
6612 push_to_sequence (output_reload_insns
[rl
->opnum
]);
6614 /* Determine the mode to reload in.
6615 See comments above (for input reloading). */
6617 if (mode
== VOIDmode
)
6619 /* VOIDmode should never happen for an output. */
6620 if (asm_noperands (PATTERN (insn
)) < 0)
6621 /* It's the compiler's fault. */
6622 fatal_insn ("VOIDmode on an output", insn
);
6623 error_for_asm (insn
, "output operand is constant in `asm'");
6624 /* Prevent crash--use something we know is valid. */
6626 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6629 if (GET_MODE (reloadreg
) != mode
)
6630 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6632 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6634 /* If we need two reload regs, set RELOADREG to the intermediate
6635 one, since it will be stored into OLD. We might need a secondary
6636 register only for an input reload, so check again here. */
6638 if (rl
->secondary_out_reload
>= 0)
6642 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
6643 && reg_equiv_mem
[REGNO (old
)] != 0)
6644 real_old
= reg_equiv_mem
[REGNO (old
)];
6646 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl
->class,
6650 rtx second_reloadreg
= reloadreg
;
6651 reloadreg
= rld
[rl
->secondary_out_reload
].reg_rtx
;
6653 /* See if RELOADREG is to be used as a scratch register
6654 or as an intermediate register. */
6655 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
6657 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
6658 (real_old
, second_reloadreg
, reloadreg
)));
6663 /* See if we need both a scratch and intermediate reload
6666 int secondary_reload
= rl
->secondary_out_reload
;
6667 enum insn_code tertiary_icode
6668 = rld
[secondary_reload
].secondary_out_icode
;
6670 if (GET_MODE (reloadreg
) != mode
)
6671 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6673 if (tertiary_icode
!= CODE_FOR_nothing
)
6676 = rld
[rld
[secondary_reload
].secondary_out_reload
].reg_rtx
;
6679 /* Copy primary reload reg to secondary reload reg.
6680 (Note that these have been swapped above, then
6681 secondary reload reg to OLD using our insn.) */
6683 /* If REAL_OLD is a paradoxical SUBREG, remove it
6684 and try to put the opposite SUBREG on
6686 if (GET_CODE (real_old
) == SUBREG
6687 && (GET_MODE_SIZE (GET_MODE (real_old
))
6688 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
6689 && 0 != (tem
= gen_lowpart_common
6690 (GET_MODE (SUBREG_REG (real_old
)),
6692 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
6694 gen_reload (reloadreg
, second_reloadreg
,
6695 rl
->opnum
, rl
->when_needed
);
6696 emit_insn ((GEN_FCN (tertiary_icode
)
6697 (real_old
, reloadreg
, third_reloadreg
)));
6702 /* Copy between the reload regs here and then to
6705 gen_reload (reloadreg
, second_reloadreg
,
6706 rl
->opnum
, rl
->when_needed
);
6712 /* Output the last reload insn. */
6717 /* Don't output the last reload if OLD is not the dest of
6718 INSN and is in the src and is clobbered by INSN. */
6719 if (! flag_expensive_optimizations
6720 || GET_CODE (old
) != REG
6721 || !(set
= single_set (insn
))
6722 || rtx_equal_p (old
, SET_DEST (set
))
6723 || !reg_mentioned_p (old
, SET_SRC (set
))
6724 || !regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0))
6725 gen_reload (old
, reloadreg
, rl
->opnum
,
6729 /* Look at all insns we emitted, just to be safe. */
6730 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6733 rtx pat
= PATTERN (p
);
6735 /* If this output reload doesn't come from a spill reg,
6736 clear any memory of reloaded copies of the pseudo reg.
6737 If this output reload comes from a spill reg,
6738 reg_has_output_reload will make this do nothing. */
6739 note_stores (pat
, forget_old_reloads_1
, NULL
);
6741 if (reg_mentioned_p (rl
->reg_rtx
, pat
))
6743 rtx set
= single_set (insn
);
6744 if (reload_spill_index
[j
] < 0
6746 && SET_SRC (set
) == rl
->reg_rtx
)
6748 int src
= REGNO (SET_SRC (set
));
6750 reload_spill_index
[j
] = src
;
6751 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
6752 if (find_regno_note (insn
, REG_DEAD
, src
))
6753 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
6755 if (REGNO (rl
->reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6757 int s
= rl
->secondary_out_reload
;
6758 set
= single_set (p
);
6759 /* If this reload copies only to the secondary reload
6760 register, the secondary reload does the actual
6762 if (s
>= 0 && set
== NULL_RTX
)
6763 /* We can't tell what function the secondary reload
6764 has and where the actual store to the pseudo is
6765 made; leave new_spill_reg_store alone. */
6768 && SET_SRC (set
) == rl
->reg_rtx
6769 && SET_DEST (set
) == rld
[s
].reg_rtx
)
6771 /* Usually the next instruction will be the
6772 secondary reload insn; if we can confirm
6773 that it is, setting new_spill_reg_store to
6774 that insn will allow an extra optimization. */
6775 rtx s_reg
= rld
[s
].reg_rtx
;
6776 rtx next
= NEXT_INSN (p
);
6777 rld
[s
].out
= rl
->out
;
6778 rld
[s
].out_reg
= rl
->out_reg
;
6779 set
= single_set (next
);
6780 if (set
&& SET_SRC (set
) == s_reg
6781 && ! new_spill_reg_store
[REGNO (s_reg
)])
6783 SET_HARD_REG_BIT (reg_is_output_reload
,
6785 new_spill_reg_store
[REGNO (s_reg
)] = next
;
6789 new_spill_reg_store
[REGNO (rl
->reg_rtx
)] = p
;
6794 if (rl
->when_needed
== RELOAD_OTHER
)
6796 emit_insns (other_output_reload_insns
[rl
->opnum
]);
6797 other_output_reload_insns
[rl
->opnum
] = get_insns ();
6800 output_reload_insns
[rl
->opnum
] = get_insns ();
6802 if (flag_non_call_exceptions
)
6803 copy_eh_notes (insn
, get_insns ());
6808 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6809 and has the number J. */
6811 do_input_reload (chain
, rl
, j
)
6812 struct insn_chain
*chain
;
6816 int expect_occurrences
= 1;
6817 rtx insn
= chain
->insn
;
6818 rtx old
= (rl
->in
&& GET_CODE (rl
->in
) == MEM
6819 ? rl
->in_reg
: rl
->in
);
6822 /* AUTO_INC reloads need to be handled even if inherited. We got an
6823 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6824 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
6825 && ! rtx_equal_p (rl
->reg_rtx
, old
)
6826 && rl
->reg_rtx
!= 0)
6827 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
6829 /* When inheriting a wider reload, we have a MEM in rl->in,
6830 e.g. inheriting a SImode output reload for
6831 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6832 if (optimize
&& reload_inherited
[j
] && rl
->in
6833 && GET_CODE (rl
->in
) == MEM
6834 && GET_CODE (rl
->in_reg
) == MEM
6835 && reload_spill_index
[j
] >= 0
6836 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
6839 = count_occurrences (PATTERN (insn
), rl
->in
, 0) == 1 ? 0 : -1;
6840 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
6843 /* If we are reloading a register that was recently stored in with an
6844 output-reload, see if we can prove there was
6845 actually no need to store the old value in it. */
6848 && (reload_inherited
[j
] || reload_override_in
[j
])
6850 && GET_CODE (rl
->reg_rtx
) == REG
6851 && spill_reg_store
[REGNO (rl
->reg_rtx
)] != 0
6853 /* There doesn't seem to be any reason to restrict this to pseudos
6854 and doing so loses in the case where we are copying from a
6855 register of the wrong class. */
6856 && (REGNO (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6857 >= FIRST_PSEUDO_REGISTER
)
6859 /* The insn might have already some references to stackslots
6860 replaced by MEMs, while reload_out_reg still names the
6862 && (dead_or_set_p (insn
,
6863 spill_reg_stored_to
[REGNO (rl
->reg_rtx
)])
6864 || rtx_equal_p (spill_reg_stored_to
[REGNO (rl
->reg_rtx
)],
6866 delete_output_reload (insn
, j
, REGNO (rl
->reg_rtx
));
6869 /* Do output reloading for reload RL, which is for the insn described by
6870 CHAIN and has the number J.
6871 ??? At some point we need to support handling output reloads of
6872 JUMP_INSNs or insns that set cc0. */
6874 do_output_reload (chain
, rl
, j
)
6875 struct insn_chain
*chain
;
6880 rtx insn
= chain
->insn
;
6881 /* If this is an output reload that stores something that is
6882 not loaded in this same reload, see if we can eliminate a previous
6884 rtx pseudo
= rl
->out_reg
;
6887 && GET_CODE (pseudo
) == REG
6888 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
6889 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
6890 && reg_last_reload_reg
[REGNO (pseudo
)])
6892 int pseudo_no
= REGNO (pseudo
);
6893 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
6895 /* We don't need to test full validity of last_regno for
6896 inherit here; we only want to know if the store actually
6897 matches the pseudo. */
6898 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
6899 && reg_reloaded_contents
[last_regno
] == pseudo_no
6900 && spill_reg_store
[last_regno
]
6901 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
6902 delete_output_reload (insn
, j
, last_regno
);
6907 || rl
->reg_rtx
== old
6908 || rl
->reg_rtx
== 0)
6911 /* An output operand that dies right away does need a reload,
6912 but need not be copied from it. Show the new location in the
6914 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
6915 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
6917 XEXP (note
, 0) = rl
->reg_rtx
;
6920 /* Likewise for a SUBREG of an operand that dies. */
6921 else if (GET_CODE (old
) == SUBREG
6922 && GET_CODE (SUBREG_REG (old
)) == REG
6923 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
6926 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
6930 else if (GET_CODE (old
) == SCRATCH
)
6931 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6932 but we don't want to make an output reload. */
6935 /* If is a JUMP_INSN, we can't support output reloads yet. */
6936 if (GET_CODE (insn
) == JUMP_INSN
)
6939 emit_output_reload_insns (chain
, rld
+ j
, j
);
6942 /* Output insns to reload values in and out of the chosen reload regs. */
6945 emit_reload_insns (chain
)
6946 struct insn_chain
*chain
;
6948 rtx insn
= chain
->insn
;
6951 rtx following_insn
= NEXT_INSN (insn
);
6952 rtx before_insn
= PREV_INSN (insn
);
6954 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6956 for (j
= 0; j
< reload_n_operands
; j
++)
6957 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6958 = inpaddr_address_reload_insns
[j
]
6959 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6960 = outaddr_address_reload_insns
[j
]
6961 = other_output_reload_insns
[j
] = 0;
6962 other_input_address_reload_insns
= 0;
6963 other_input_reload_insns
= 0;
6964 operand_reload_insns
= 0;
6965 other_operand_reload_insns
= 0;
6967 /* Dump reloads into the dump file. */
6970 fprintf (rtl_dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
6971 debug_reload_to_stream (rtl_dump_file
);
6974 /* Now output the instructions to copy the data into and out of the
6975 reload registers. Do these in the order that the reloads were reported,
6976 since reloads of base and index registers precede reloads of operands
6977 and the operands may need the base and index registers reloaded. */
6979 for (j
= 0; j
< n_reloads
; j
++)
6982 && REGNO (rld
[j
].reg_rtx
) < FIRST_PSEUDO_REGISTER
)
6983 new_spill_reg_store
[REGNO (rld
[j
].reg_rtx
)] = 0;
6985 do_input_reload (chain
, rld
+ j
, j
);
6986 do_output_reload (chain
, rld
+ j
, j
);
6989 /* Now write all the insns we made for reloads in the order expected by
6990 the allocation functions. Prior to the insn being reloaded, we write
6991 the following reloads:
6993 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6995 RELOAD_OTHER reloads.
6997 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6998 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6999 RELOAD_FOR_INPUT reload for the operand.
7001 RELOAD_FOR_OPADDR_ADDRS reloads.
7003 RELOAD_FOR_OPERAND_ADDRESS reloads.
7005 After the insn being reloaded, we write the following:
7007 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7008 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7009 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7010 reloads for the operand. The RELOAD_OTHER output reloads are
7011 output in descending order by reload number. */
7013 emit_insns_before (other_input_address_reload_insns
, insn
);
7014 emit_insns_before (other_input_reload_insns
, insn
);
7016 for (j
= 0; j
< reload_n_operands
; j
++)
7018 emit_insns_before (inpaddr_address_reload_insns
[j
], insn
);
7019 emit_insns_before (input_address_reload_insns
[j
], insn
);
7020 emit_insns_before (input_reload_insns
[j
], insn
);
7023 emit_insns_before (other_operand_reload_insns
, insn
);
7024 emit_insns_before (operand_reload_insns
, insn
);
7026 for (j
= 0; j
< reload_n_operands
; j
++)
7028 emit_insns_before (outaddr_address_reload_insns
[j
], following_insn
);
7029 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
7030 emit_insns_before (output_reload_insns
[j
], following_insn
);
7031 emit_insns_before (other_output_reload_insns
[j
], following_insn
);
7034 /* Keep basic block info up to date. */
7037 if (BLOCK_HEAD (chain
->block
) == insn
)
7038 BLOCK_HEAD (chain
->block
) = NEXT_INSN (before_insn
);
7039 if (BLOCK_END (chain
->block
) == insn
)
7040 BLOCK_END (chain
->block
) = PREV_INSN (following_insn
);
7043 /* For all the spill regs newly reloaded in this instruction,
7044 record what they were reloaded from, so subsequent instructions
7045 can inherit the reloads.
7047 Update spill_reg_store for the reloads of this insn.
7048 Copy the elements that were updated in the loop above. */
7050 for (j
= 0; j
< n_reloads
; j
++)
7052 register int r
= reload_order
[j
];
7053 register int i
= reload_spill_index
[r
];
7055 /* If this is a non-inherited input reload from a pseudo, we must
7056 clear any memory of a previous store to the same pseudo. Only do
7057 something if there will not be an output reload for the pseudo
7059 if (rld
[r
].in_reg
!= 0
7060 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7062 rtx reg
= rld
[r
].in_reg
;
7064 if (GET_CODE (reg
) == SUBREG
)
7065 reg
= SUBREG_REG (reg
);
7067 if (GET_CODE (reg
) == REG
7068 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7069 && ! reg_has_output_reload
[REGNO (reg
)])
7071 int nregno
= REGNO (reg
);
7073 if (reg_last_reload_reg
[nregno
])
7075 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7077 if (reg_reloaded_contents
[last_regno
] == nregno
)
7078 spill_reg_store
[last_regno
] = 0;
7083 /* I is nonneg if this reload used a register.
7084 If rld[r].reg_rtx is 0, this is an optional reload
7085 that we opted to ignore. */
7087 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
7089 int nr
= HARD_REGNO_NREGS (i
, GET_MODE (rld
[r
].reg_rtx
));
7091 int part_reaches_end
= 0;
7092 int all_reaches_end
= 1;
7094 /* For a multi register reload, we need to check if all or part
7095 of the value lives to the end. */
7096 for (k
= 0; k
< nr
; k
++)
7098 if (reload_reg_reaches_end_p (i
+ k
, rld
[r
].opnum
,
7099 rld
[r
].when_needed
))
7100 part_reaches_end
= 1;
7102 all_reaches_end
= 0;
7105 /* Ignore reloads that don't reach the end of the insn in
7107 if (all_reaches_end
)
7109 /* First, clear out memory of what used to be in this spill reg.
7110 If consecutive registers are used, clear them all. */
7112 for (k
= 0; k
< nr
; k
++)
7113 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7115 /* Maybe the spill reg contains a copy of reload_out. */
7117 && (GET_CODE (rld
[r
].out
) == REG
7121 || GET_CODE (rld
[r
].out_reg
) == REG
))
7123 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7127 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
7128 register int nregno
= REGNO (out
);
7129 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7130 : HARD_REGNO_NREGS (nregno
,
7131 GET_MODE (rld
[r
].reg_rtx
)));
7133 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7134 spill_reg_stored_to
[i
] = out
;
7135 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7137 /* If NREGNO is a hard register, it may occupy more than
7138 one register. If it does, say what is in the
7139 rest of the registers assuming that both registers
7140 agree on how many words the object takes. If not,
7141 invalidate the subsequent registers. */
7143 if (nregno
< FIRST_PSEUDO_REGISTER
)
7144 for (k
= 1; k
< nnr
; k
++)
7145 reg_last_reload_reg
[nregno
+ k
]
7147 ? gen_rtx_REG (reg_raw_mode
[REGNO (rld
[r
].reg_rtx
) + k
],
7148 REGNO (rld
[r
].reg_rtx
) + k
)
7151 /* Now do the inverse operation. */
7152 for (k
= 0; k
< nr
; k
++)
7154 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7155 reg_reloaded_contents
[i
+ k
]
7156 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7159 reg_reloaded_insn
[i
+ k
] = insn
;
7160 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7164 /* Maybe the spill reg contains a copy of reload_in. Only do
7165 something if there will not be an output reload for
7166 the register being reloaded. */
7167 else if (rld
[r
].out_reg
== 0
7169 && ((GET_CODE (rld
[r
].in
) == REG
7170 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
7171 && ! reg_has_output_reload
[REGNO (rld
[r
].in
)])
7172 || (GET_CODE (rld
[r
].in_reg
) == REG
7173 && ! reg_has_output_reload
[REGNO (rld
[r
].in_reg
)]))
7174 && ! reg_set_p (rld
[r
].reg_rtx
, PATTERN (insn
)))
7176 register int nregno
;
7179 if (GET_CODE (rld
[r
].in
) == REG
7180 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
7181 nregno
= REGNO (rld
[r
].in
);
7182 else if (GET_CODE (rld
[r
].in_reg
) == REG
)
7183 nregno
= REGNO (rld
[r
].in_reg
);
7185 nregno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
7187 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7188 : HARD_REGNO_NREGS (nregno
,
7189 GET_MODE (rld
[r
].reg_rtx
)));
7191 reg_last_reload_reg
[nregno
] = rld
[r
].reg_rtx
;
7193 if (nregno
< FIRST_PSEUDO_REGISTER
)
7194 for (k
= 1; k
< nnr
; k
++)
7195 reg_last_reload_reg
[nregno
+ k
]
7197 ? gen_rtx_REG (reg_raw_mode
[REGNO (rld
[r
].reg_rtx
) + k
],
7198 REGNO (rld
[r
].reg_rtx
) + k
)
7201 /* Unless we inherited this reload, show we haven't
7202 recently done a store.
7203 Previous stores of inherited auto_inc expressions
7204 also have to be discarded. */
7205 if (! reload_inherited
[r
]
7206 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
7207 spill_reg_store
[i
] = 0;
7209 for (k
= 0; k
< nr
; k
++)
7211 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7212 reg_reloaded_contents
[i
+ k
]
7213 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7216 reg_reloaded_insn
[i
+ k
] = insn
;
7217 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7222 /* However, if part of the reload reaches the end, then we must
7223 invalidate the old info for the part that survives to the end. */
7224 else if (part_reaches_end
)
7226 for (k
= 0; k
< nr
; k
++)
7227 if (reload_reg_reaches_end_p (i
+ k
,
7229 rld
[r
].when_needed
))
7230 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7234 /* The following if-statement was #if 0'd in 1.34 (or before...).
7235 It's reenabled in 1.35 because supposedly nothing else
7236 deals with this problem. */
7238 /* If a register gets output-reloaded from a non-spill register,
7239 that invalidates any previous reloaded copy of it.
7240 But forget_old_reloads_1 won't get to see it, because
7241 it thinks only about the original insn. So invalidate it here. */
7242 if (i
< 0 && rld
[r
].out
!= 0
7243 && (GET_CODE (rld
[r
].out
) == REG
7244 || (GET_CODE (rld
[r
].out
) == MEM
7245 && GET_CODE (rld
[r
].out_reg
) == REG
)))
7247 rtx out
= (GET_CODE (rld
[r
].out
) == REG
7248 ? rld
[r
].out
: rld
[r
].out_reg
);
7249 register int nregno
= REGNO (out
);
7250 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7252 rtx src_reg
, store_insn
= NULL_RTX
;
7254 reg_last_reload_reg
[nregno
] = 0;
7256 /* If we can find a hard register that is stored, record
7257 the storing insn so that we may delete this insn with
7258 delete_output_reload. */
7259 src_reg
= rld
[r
].reg_rtx
;
7261 /* If this is an optional reload, try to find the source reg
7262 from an input reload. */
7265 rtx set
= single_set (insn
);
7266 if (set
&& SET_DEST (set
) == rld
[r
].out
)
7270 src_reg
= SET_SRC (set
);
7272 for (k
= 0; k
< n_reloads
; k
++)
7274 if (rld
[k
].in
== src_reg
)
7276 src_reg
= rld
[k
].reg_rtx
;
7283 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7284 if (src_reg
&& GET_CODE (src_reg
) == REG
7285 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7287 int src_regno
= REGNO (src_reg
);
7288 int nr
= HARD_REGNO_NREGS (src_regno
, rld
[r
].mode
);
7289 /* The place where to find a death note varies with
7290 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7291 necessarily checked exactly in the code that moves
7292 notes, so just check both locations. */
7293 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7295 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7298 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7299 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7300 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7301 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7302 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7303 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7304 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7306 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7308 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7310 reg_last_reload_reg
[nregno
] = src_reg
;
7315 int num_regs
= HARD_REGNO_NREGS (nregno
, GET_MODE (rld
[r
].out
));
7317 while (num_regs
-- > 0)
7318 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7322 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7325 /* Emit code to perform a reload from IN (which may be a reload register) to
7326 OUT (which may also be a reload register). IN or OUT is from operand
7327 OPNUM with reload type TYPE.
7329 Returns first insn emitted. */
7332 gen_reload (out
, in
, opnum
, type
)
7336 enum reload_type type
;
7338 rtx last
= get_last_insn ();
7341 /* If IN is a paradoxical SUBREG, remove it and try to put the
7342 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7343 if (GET_CODE (in
) == SUBREG
7344 && (GET_MODE_SIZE (GET_MODE (in
))
7345 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7346 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7347 in
= SUBREG_REG (in
), out
= tem
;
7348 else if (GET_CODE (out
) == SUBREG
7349 && (GET_MODE_SIZE (GET_MODE (out
))
7350 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7351 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7352 out
= SUBREG_REG (out
), in
= tem
;
7354 /* How to do this reload can get quite tricky. Normally, we are being
7355 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7356 register that didn't get a hard register. In that case we can just
7357 call emit_move_insn.
7359 We can also be asked to reload a PLUS that adds a register or a MEM to
7360 another register, constant or MEM. This can occur during frame pointer
7361 elimination and while reloading addresses. This case is handled by
7362 trying to emit a single insn to perform the add. If it is not valid,
7363 we use a two insn sequence.
7365 Finally, we could be called to handle an 'o' constraint by putting
7366 an address into a register. In that case, we first try to do this
7367 with a named pattern of "reload_load_address". If no such pattern
7368 exists, we just emit a SET insn and hope for the best (it will normally
7369 be valid on machines that use 'o').
7371 This entire process is made complex because reload will never
7372 process the insns we generate here and so we must ensure that
7373 they will fit their constraints and also by the fact that parts of
7374 IN might be being reloaded separately and replaced with spill registers.
7375 Because of this, we are, in some sense, just guessing the right approach
7376 here. The one listed above seems to work.
7378 ??? At some point, this whole thing needs to be rethought. */
7380 if (GET_CODE (in
) == PLUS
7381 && (GET_CODE (XEXP (in
, 0)) == REG
7382 || GET_CODE (XEXP (in
, 0)) == SUBREG
7383 || GET_CODE (XEXP (in
, 0)) == MEM
)
7384 && (GET_CODE (XEXP (in
, 1)) == REG
7385 || GET_CODE (XEXP (in
, 1)) == SUBREG
7386 || CONSTANT_P (XEXP (in
, 1))
7387 || GET_CODE (XEXP (in
, 1)) == MEM
))
7389 /* We need to compute the sum of a register or a MEM and another
7390 register, constant, or MEM, and put it into the reload
7391 register. The best possible way of doing this is if the machine
7392 has a three-operand ADD insn that accepts the required operands.
7394 The simplest approach is to try to generate such an insn and see if it
7395 is recognized and matches its constraints. If so, it can be used.
7397 It might be better not to actually emit the insn unless it is valid,
7398 but we need to pass the insn as an operand to `recog' and
7399 `extract_insn' and it is simpler to emit and then delete the insn if
7400 not valid than to dummy things up. */
7402 rtx op0
, op1
, tem
, insn
;
7405 op0
= find_replacement (&XEXP (in
, 0));
7406 op1
= find_replacement (&XEXP (in
, 1));
7408 /* Since constraint checking is strict, commutativity won't be
7409 checked, so we need to do that here to avoid spurious failure
7410 if the add instruction is two-address and the second operand
7411 of the add is the same as the reload reg, which is frequently
7412 the case. If the insn would be A = B + A, rearrange it so
7413 it will be A = A + B as constrain_operands expects. */
7415 if (GET_CODE (XEXP (in
, 1)) == REG
7416 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7417 tem
= op0
, op0
= op1
, op1
= tem
;
7419 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7420 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7422 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7423 code
= recog_memoized (insn
);
7427 extract_insn (insn
);
7428 /* We want constrain operands to treat this insn strictly in
7429 its validity determination, i.e., the way it would after reload
7431 if (constrain_operands (1))
7435 delete_insns_since (last
);
7437 /* If that failed, we must use a conservative two-insn sequence.
7439 Use a move to copy one operand into the reload register. Prefer
7440 to reload a constant, MEM or pseudo since the move patterns can
7441 handle an arbitrary operand. If OP1 is not a constant, MEM or
7442 pseudo and OP1 is not a valid operand for an add instruction, then
7445 After reloading one of the operands into the reload register, add
7446 the reload register to the output register.
7448 If there is another way to do this for a specific machine, a
7449 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7452 code
= (int) add_optab
->handlers
[(int) GET_MODE (out
)].insn_code
;
7454 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7455 || (GET_CODE (op1
) == REG
7456 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
7457 || (code
!= CODE_FOR_nothing
7458 && ! ((*insn_data
[code
].operand
[2].predicate
)
7459 (op1
, insn_data
[code
].operand
[2].mode
))))
7460 tem
= op0
, op0
= op1
, op1
= tem
;
7462 gen_reload (out
, op0
, opnum
, type
);
7464 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7465 This fixes a problem on the 32K where the stack pointer cannot
7466 be used as an operand of an add insn. */
7468 if (rtx_equal_p (op0
, op1
))
7471 insn
= emit_insn (gen_add2_insn (out
, op1
));
7473 /* If that failed, copy the address register to the reload register.
7474 Then add the constant to the reload register. */
7476 code
= recog_memoized (insn
);
7480 extract_insn (insn
);
7481 /* We want constrain operands to treat this insn strictly in
7482 its validity determination, i.e., the way it would after reload
7484 if (constrain_operands (1))
7486 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7488 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7493 delete_insns_since (last
);
7495 gen_reload (out
, op1
, opnum
, type
);
7496 insn
= emit_insn (gen_add2_insn (out
, op0
));
7497 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7500 #ifdef SECONDARY_MEMORY_NEEDED
7501 /* If we need a memory location to do the move, do it that way. */
7502 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
7503 && GET_CODE (out
) == REG
&& REGNO (out
) < FIRST_PSEUDO_REGISTER
7504 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
7505 REGNO_REG_CLASS (REGNO (out
)),
7508 /* Get the memory to use and rewrite both registers to its mode. */
7509 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7511 if (GET_MODE (loc
) != GET_MODE (out
))
7512 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7514 if (GET_MODE (loc
) != GET_MODE (in
))
7515 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7517 gen_reload (loc
, in
, opnum
, type
);
7518 gen_reload (out
, loc
, opnum
, type
);
7522 /* If IN is a simple operand, use gen_move_insn. */
7523 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7524 emit_insn (gen_move_insn (out
, in
));
7526 #ifdef HAVE_reload_load_address
7527 else if (HAVE_reload_load_address
)
7528 emit_insn (gen_reload_load_address (out
, in
));
7531 /* Otherwise, just write (set OUT IN) and hope for the best. */
7533 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7535 /* Return the first insn emitted.
7536 We can not just return get_last_insn, because there may have
7537 been multiple instructions emitted. Also note that gen_move_insn may
7538 emit more than one insn itself, so we can not assume that there is one
7539 insn emitted per emit_insn_before call. */
7541 return last
? NEXT_INSN (last
) : get_insns ();
7544 /* Delete a previously made output-reload
7545 whose result we now believe is not needed.
7546 First we double-check.
7548 INSN is the insn now being processed.
7549 LAST_RELOAD_REG is the hard register number for which we want to delete
7550 the last output reload.
7551 J is the reload-number that originally used REG. The caller has made
7552 certain that reload J doesn't use REG any longer for input. */
7555 delete_output_reload (insn
, j
, last_reload_reg
)
7558 int last_reload_reg
;
7560 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7561 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7564 int n_inherited
= 0;
7568 /* Get the raw pseudo-register referred to. */
7570 while (GET_CODE (reg
) == SUBREG
)
7571 reg
= SUBREG_REG (reg
);
7572 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7574 /* This is unsafe if the operand occurs more often in the current
7575 insn than it is inherited. */
7576 for (k
= n_reloads
- 1; k
>= 0; k
--)
7578 rtx reg2
= rld
[k
].in
;
7581 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
7582 reg2
= rld
[k
].in_reg
;
7584 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
7585 reg2
= XEXP (rld
[k
].in_reg
, 0);
7587 while (GET_CODE (reg2
) == SUBREG
)
7588 reg2
= SUBREG_REG (reg2
);
7589 if (rtx_equal_p (reg2
, reg
))
7591 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7594 reg2
= rld
[k
].out_reg
;
7597 while (GET_CODE (reg2
) == SUBREG
)
7598 reg2
= XEXP (reg2
, 0);
7599 if (rtx_equal_p (reg2
, reg
))
7606 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
7608 n_occurrences
+= count_occurrences (PATTERN (insn
),
7609 eliminate_regs (substed
, 0,
7611 if (n_occurrences
> n_inherited
)
7614 /* If the pseudo-reg we are reloading is no longer referenced
7615 anywhere between the store into it and here,
7616 and no jumps or labels intervene, then the value can get
7617 here through the reload reg alone.
7618 Otherwise, give up--return. */
7619 for (i1
= NEXT_INSN (output_reload_insn
);
7620 i1
!= insn
; i1
= NEXT_INSN (i1
))
7622 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7624 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7625 && reg_mentioned_p (reg
, PATTERN (i1
)))
7627 /* If this is USE in front of INSN, we only have to check that
7628 there are no more references than accounted for by inheritance. */
7629 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
7631 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7632 i1
= NEXT_INSN (i1
);
7634 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7640 /* The caller has already checked that REG dies or is set in INSN.
7641 It has also checked that we are optimizing, and thus some inaccurancies
7642 in the debugging information are acceptable.
7643 So we could just delete output_reload_insn.
7644 But in some cases we can improve the debugging information without
7645 sacrificing optimization - maybe even improving the code:
7646 See if the pseudo reg has been completely replaced
7647 with reload regs. If so, delete the store insn
7648 and forget we had a stack slot for the pseudo. */
7649 if (rld
[j
].out
!= rld
[j
].in
7650 && REG_N_DEATHS (REGNO (reg
)) == 1
7651 && REG_N_SETS (REGNO (reg
)) == 1
7652 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7653 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
7657 /* We know that it was used only between here
7658 and the beginning of the current basic block.
7659 (We also know that the last use before INSN was
7660 the output reload we are thinking of deleting, but never mind that.)
7661 Search that range; see if any ref remains. */
7662 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7664 rtx set
= single_set (i2
);
7666 /* Uses which just store in the pseudo don't count,
7667 since if they are the only uses, they are dead. */
7668 if (set
!= 0 && SET_DEST (set
) == reg
)
7670 if (GET_CODE (i2
) == CODE_LABEL
7671 || GET_CODE (i2
) == JUMP_INSN
)
7673 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
7674 && reg_mentioned_p (reg
, PATTERN (i2
)))
7676 /* Some other ref remains; just delete the output reload we
7678 delete_address_reloads (output_reload_insn
, insn
);
7679 PUT_CODE (output_reload_insn
, NOTE
);
7680 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7681 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7686 /* Delete the now-dead stores into this pseudo. */
7687 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
7689 rtx set
= single_set (i2
);
7691 if (set
!= 0 && SET_DEST (set
) == reg
)
7693 delete_address_reloads (i2
, insn
);
7694 /* This might be a basic block head,
7695 thus don't use delete_insn. */
7696 PUT_CODE (i2
, NOTE
);
7697 NOTE_SOURCE_FILE (i2
) = 0;
7698 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
7700 if (GET_CODE (i2
) == CODE_LABEL
7701 || GET_CODE (i2
) == JUMP_INSN
)
7705 /* For the debugging info,
7706 say the pseudo lives in this reload reg. */
7707 reg_renumber
[REGNO (reg
)] = REGNO (rld
[j
].reg_rtx
);
7708 alter_reg (REGNO (reg
), -1);
7710 delete_address_reloads (output_reload_insn
, insn
);
7711 PUT_CODE (output_reload_insn
, NOTE
);
7712 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
7713 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
7717 /* We are going to delete DEAD_INSN. Recursively delete loads of
7718 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7719 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7721 delete_address_reloads (dead_insn
, current_insn
)
7722 rtx dead_insn
, current_insn
;
7724 rtx set
= single_set (dead_insn
);
7725 rtx set2
, dst
, prev
, next
;
7728 rtx dst
= SET_DEST (set
);
7729 if (GET_CODE (dst
) == MEM
)
7730 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
7732 /* If we deleted the store from a reloaded post_{in,de}c expression,
7733 we can delete the matching adds. */
7734 prev
= PREV_INSN (dead_insn
);
7735 next
= NEXT_INSN (dead_insn
);
7736 if (! prev
|| ! next
)
7738 set
= single_set (next
);
7739 set2
= single_set (prev
);
7741 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
7742 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
7743 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
7745 dst
= SET_DEST (set
);
7746 if (! rtx_equal_p (dst
, SET_DEST (set2
))
7747 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
7748 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
7749 || (INTVAL (XEXP (SET_SRC (set
), 1))
7750 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
7756 /* Subfunction of delete_address_reloads: process registers found in X. */
7758 delete_address_reloads_1 (dead_insn
, x
, current_insn
)
7759 rtx dead_insn
, x
, current_insn
;
7761 rtx prev
, set
, dst
, i2
;
7763 enum rtx_code code
= GET_CODE (x
);
7767 const char *fmt
= GET_RTX_FORMAT (code
);
7768 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7771 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
7772 else if (fmt
[i
] == 'E')
7774 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7775 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
7782 if (spill_reg_order
[REGNO (x
)] < 0)
7785 /* Scan backwards for the insn that sets x. This might be a way back due
7787 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
7789 code
= GET_CODE (prev
);
7790 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
7792 if (GET_RTX_CLASS (code
) != 'i')
7794 if (reg_set_p (x
, PATTERN (prev
)))
7796 if (reg_referenced_p (x
, PATTERN (prev
)))
7799 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
7801 /* Check that PREV only sets the reload register. */
7802 set
= single_set (prev
);
7805 dst
= SET_DEST (set
);
7806 if (GET_CODE (dst
) != REG
7807 || ! rtx_equal_p (dst
, x
))
7809 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
7811 /* Check if DST was used in a later insn -
7812 it might have been inherited. */
7813 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
7815 if (GET_CODE (i2
) == CODE_LABEL
)
7819 if (reg_referenced_p (dst
, PATTERN (i2
)))
7821 /* If there is a reference to the register in the current insn,
7822 it might be loaded in a non-inherited reload. If no other
7823 reload uses it, that means the register is set before
7825 if (i2
== current_insn
)
7827 for (j
= n_reloads
- 1; j
>= 0; j
--)
7828 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7829 || reload_override_in
[j
] == dst
)
7831 for (j
= n_reloads
- 1; j
>= 0; j
--)
7832 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
7839 if (GET_CODE (i2
) == JUMP_INSN
)
7841 /* If DST is still live at CURRENT_INSN, check if it is used for
7842 any reload. Note that even if CURRENT_INSN sets DST, we still
7843 have to check the reloads. */
7844 if (i2
== current_insn
)
7846 for (j
= n_reloads
- 1; j
>= 0; j
--)
7847 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
7848 || reload_override_in
[j
] == dst
)
7850 /* ??? We can't finish the loop here, because dst might be
7851 allocated to a pseudo in this block if no reload in this
7852 block needs any of the clsses containing DST - see
7853 spill_hard_reg. There is no easy way to tell this, so we
7854 have to scan till the end of the basic block. */
7856 if (reg_set_p (dst
, PATTERN (i2
)))
7860 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
7861 reg_reloaded_contents
[REGNO (dst
)] = -1;
7862 /* Can't use delete_insn here because PREV might be a basic block head. */
7863 PUT_CODE (prev
, NOTE
);
7864 NOTE_LINE_NUMBER (prev
) = NOTE_INSN_DELETED
;
7865 NOTE_SOURCE_FILE (prev
) = 0;
7868 /* Output reload-insns to reload VALUE into RELOADREG.
7869 VALUE is an autoincrement or autodecrement RTX whose operand
7870 is a register or memory location;
7871 so reloading involves incrementing that location.
7872 IN is either identical to VALUE, or some cheaper place to reload from.
7874 INC_AMOUNT is the number to increment or decrement by (always positive).
7875 This cannot be deduced from VALUE.
7877 Return the instruction that stores into RELOADREG. */
7880 inc_for_reload (reloadreg
, in
, value
, inc_amount
)
7885 /* REG or MEM to be copied and incremented. */
7886 rtx incloc
= XEXP (value
, 0);
7887 /* Nonzero if increment after copying. */
7888 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
7894 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
7896 /* No hard register is equivalent to this register after
7897 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7898 we could inc/dec that register as well (maybe even using it for
7899 the source), but I'm not sure it's worth worrying about. */
7900 if (GET_CODE (incloc
) == REG
)
7901 reg_last_reload_reg
[REGNO (incloc
)] = 0;
7903 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
7904 inc_amount
= -inc_amount
;
7906 inc
= GEN_INT (inc_amount
);
7908 /* If this is post-increment, first copy the location to the reload reg. */
7909 if (post
&& real_in
!= reloadreg
)
7910 emit_insn (gen_move_insn (reloadreg
, real_in
));
7914 /* See if we can directly increment INCLOC. Use a method similar to
7915 that in gen_reload. */
7917 last
= get_last_insn ();
7918 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
7919 gen_rtx_PLUS (GET_MODE (incloc
),
7922 code
= recog_memoized (add_insn
);
7925 extract_insn (add_insn
);
7926 if (constrain_operands (1))
7928 /* If this is a pre-increment and we have incremented the value
7929 where it lives, copy the incremented value to RELOADREG to
7930 be used as an address. */
7933 emit_insn (gen_move_insn (reloadreg
, incloc
));
7938 delete_insns_since (last
);
7941 /* If couldn't do the increment directly, must increment in RELOADREG.
7942 The way we do this depends on whether this is pre- or post-increment.
7943 For pre-increment, copy INCLOC to the reload register, increment it
7944 there, then save back. */
7948 if (in
!= reloadreg
)
7949 emit_insn (gen_move_insn (reloadreg
, real_in
));
7950 emit_insn (gen_add2_insn (reloadreg
, inc
));
7951 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7956 Because this might be a jump insn or a compare, and because RELOADREG
7957 may not be available after the insn in an input reload, we must do
7958 the incrementation before the insn being reloaded for.
7960 We have already copied IN to RELOADREG. Increment the copy in
7961 RELOADREG, save that back, then decrement RELOADREG so it has
7962 the original value. */
7964 emit_insn (gen_add2_insn (reloadreg
, inc
));
7965 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
7966 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
7972 /* Return 1 if we are certain that the constraint-string STRING allows
7973 the hard register REG. Return 0 if we can't be sure of this. */
7976 constraint_accepts_reg_p (string
, reg
)
7981 int regno
= true_regnum (reg
);
7984 /* Initialize for first alternative. */
7986 /* Check that each alternative contains `g' or `r'. */
7988 switch (c
= *string
++)
7991 /* If an alternative lacks `g' or `r', we lose. */
7994 /* If an alternative lacks `g' or `r', we lose. */
7997 /* Initialize for next alternative. */
8002 /* Any general reg wins for this alternative. */
8003 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
8007 /* Any reg in specified class wins for this alternative. */
8009 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
8011 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
8017 /* INSN is a no-op; delete it.
8018 If this sets the return value of the function, we must keep a USE around,
8019 in case this is in a different basic block than the final USE. Otherwise,
8020 we could loose important register lifeness information on
8021 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8022 spills: subsequent passes assume that spill registers are dead at the end
8024 VALUE must be the return value in such a case, NULL otherwise. */
8026 reload_cse_delete_noop_set (insn
, value
)
8031 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, value
);
8032 INSN_CODE (insn
) = -1;
8033 REG_NOTES (insn
) = NULL_RTX
;
8037 PUT_CODE (insn
, NOTE
);
8038 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8039 NOTE_SOURCE_FILE (insn
) = 0;
8043 /* See whether a single set SET is a noop. */
8045 reload_cse_noop_set_p (set
)
8048 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
8051 /* Try to simplify INSN. */
8053 reload_cse_simplify (insn
)
8056 rtx body
= PATTERN (insn
);
8058 if (GET_CODE (body
) == SET
)
8062 /* Simplify even if we may think it is a no-op.
8063 We may think a memory load of a value smaller than WORD_SIZE
8064 is redundant because we haven't taken into account possible
8065 implicit extension. reload_cse_simplify_set() will bring
8066 this out, so it's safer to simplify before we delete. */
8067 count
+= reload_cse_simplify_set (body
, insn
);
8069 if (!count
&& reload_cse_noop_set_p (body
))
8071 rtx value
= SET_DEST (body
);
8072 if (! REG_FUNCTION_VALUE_P (SET_DEST (body
)))
8074 reload_cse_delete_noop_set (insn
, value
);
8079 apply_change_group ();
8081 reload_cse_simplify_operands (insn
);
8083 else if (GET_CODE (body
) == PARALLEL
)
8087 rtx value
= NULL_RTX
;
8089 /* If every action in a PARALLEL is a noop, we can delete
8090 the entire PARALLEL. */
8091 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8093 rtx part
= XVECEXP (body
, 0, i
);
8094 if (GET_CODE (part
) == SET
)
8096 if (! reload_cse_noop_set_p (part
))
8098 if (REG_FUNCTION_VALUE_P (SET_DEST (part
)))
8102 value
= SET_DEST (part
);
8105 else if (GET_CODE (part
) != CLOBBER
)
8111 reload_cse_delete_noop_set (insn
, value
);
8112 /* We're done with this insn. */
8116 /* It's not a no-op, but we can try to simplify it. */
8117 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8118 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
8119 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
8122 apply_change_group ();
8124 reload_cse_simplify_operands (insn
);
8128 /* Do a very simple CSE pass over the hard registers.
8130 This function detects no-op moves where we happened to assign two
8131 different pseudo-registers to the same hard register, and then
8132 copied one to the other. Reload will generate a useless
8133 instruction copying a register to itself.
8135 This function also detects cases where we load a value from memory
8136 into two different registers, and (if memory is more expensive than
8137 registers) changes it to simply copy the first register into the
8140 Another optimization is performed that scans the operands of each
8141 instruction to see whether the value is already available in a
8142 hard register. It then replaces the operand with the hard register
8143 if possible, much like an optional reload would. */
8146 reload_cse_regs_1 (first
)
8152 init_alias_analysis ();
8154 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8157 reload_cse_simplify (insn
);
8159 cselib_process_insn (insn
);
8163 end_alias_analysis ();
8167 /* Call cse / combine like post-reload optimization phases.
8168 FIRST is the first instruction. */
8170 reload_cse_regs (first
)
8173 reload_cse_regs_1 (first
);
8175 reload_cse_move2add (first
);
8176 if (flag_expensive_optimizations
)
8177 reload_cse_regs_1 (first
);
8180 /* Try to simplify a single SET instruction. SET is the set pattern.
8181 INSN is the instruction it came from.
8182 This function only handles one case: if we set a register to a value
8183 which is not a register, we try to find that value in some other register
8184 and change the set into a register copy. */
8187 reload_cse_simplify_set (set
, insn
)
8194 enum reg_class dclass
;
8197 struct elt_loc_list
*l
;
8198 #ifdef LOAD_EXTEND_OP
8199 enum rtx_code extend_op
= NIL
;
8202 dreg
= true_regnum (SET_DEST (set
));
8206 src
= SET_SRC (set
);
8207 if (side_effects_p (src
) || true_regnum (src
) >= 0)
8210 dclass
= REGNO_REG_CLASS (dreg
);
8212 #ifdef LOAD_EXTEND_OP
8213 /* When replacing a memory with a register, we need to honor assumptions
8214 that combine made wrt the contents of sign bits. We'll do this by
8215 generating an extend instruction instead of a reg->reg copy. Thus
8216 the destination must be a register that we can widen. */
8217 if (GET_CODE (src
) == MEM
8218 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
8219 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != NIL
8220 && GET_CODE (SET_DEST (set
)) != REG
)
8224 /* If memory loads are cheaper than register copies, don't change them. */
8225 if (GET_CODE (src
) == MEM
)
8226 old_cost
= MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1);
8227 else if (CONSTANT_P (src
))
8228 old_cost
= rtx_cost (src
, SET
);
8229 else if (GET_CODE (src
) == REG
)
8230 old_cost
= REGISTER_MOVE_COST (GET_MODE (src
),
8231 REGNO_REG_CLASS (REGNO (src
)), dclass
);
8234 old_cost
= rtx_cost (src
, SET
);
8236 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0);
8239 for (l
= val
->locs
; l
; l
= l
->next
)
8241 rtx this_rtx
= l
->loc
;
8244 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
8246 #ifdef LOAD_EXTEND_OP
8247 if (extend_op
!= NIL
)
8249 HOST_WIDE_INT this_val
;
8251 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8252 constants, such as SYMBOL_REF, cannot be extended. */
8253 if (GET_CODE (this_rtx
) != CONST_INT
)
8256 this_val
= INTVAL (this_rtx
);
8260 this_val
&= GET_MODE_MASK (GET_MODE (src
));
8263 /* ??? In theory we're already extended. */
8264 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
8269 this_rtx
= GEN_INT (this_val
);
8272 this_cost
= rtx_cost (this_rtx
, SET
);
8274 else if (GET_CODE (this_rtx
) == REG
)
8276 #ifdef LOAD_EXTEND_OP
8277 if (extend_op
!= NIL
)
8279 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
8280 this_cost
= rtx_cost (this_rtx
, SET
);
8284 this_cost
= REGISTER_MOVE_COST (GET_MODE (this_rtx
),
8285 REGNO_REG_CLASS (REGNO (this_rtx
)),
8291 /* If equal costs, prefer registers over anything else. That
8292 tends to lead to smaller instructions on some machines. */
8293 if (this_cost
< old_cost
8294 || (this_cost
== old_cost
8295 && GET_CODE (this_rtx
) == REG
8296 && GET_CODE (SET_SRC (set
)) != REG
))
8298 #ifdef LOAD_EXTEND_OP
8299 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
8300 && extend_op
!= NIL
)
8302 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
8303 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
8304 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
8308 validate_change (insn
, &SET_SRC (set
), copy_rtx (this_rtx
), 1);
8309 old_cost
= this_cost
, did_change
= 1;
8316 /* Try to replace operands in INSN with equivalent values that are already
8317 in registers. This can be viewed as optional reloading.
8319 For each non-register operand in the insn, see if any hard regs are
8320 known to be equivalent to that operand. Record the alternatives which
8321 can accept these hard registers. Among all alternatives, select the
8322 ones which are better or equal to the one currently matching, where
8323 "better" is in terms of '?' and '!' constraints. Among the remaining
8324 alternatives, select the one which replaces most operands with
8328 reload_cse_simplify_operands (insn
)
8333 /* For each operand, all registers that are equivalent to it. */
8334 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
8336 const char *constraints
[MAX_RECOG_OPERANDS
];
8338 /* Vector recording how bad an alternative is. */
8339 int *alternative_reject
;
8340 /* Vector recording how many registers can be introduced by choosing
8341 this alternative. */
8342 int *alternative_nregs
;
8343 /* Array of vectors recording, for each operand and each alternative,
8344 which hard register to substitute, or -1 if the operand should be
8346 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
8347 /* Array of alternatives, sorted in order of decreasing desirability. */
8348 int *alternative_order
;
8349 rtx reg
= gen_rtx_REG (VOIDmode
, -1);
8351 extract_insn (insn
);
8353 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
8356 /* Figure out which alternative currently matches. */
8357 if (! constrain_operands (1))
8358 fatal_insn_not_found (insn
);
8360 alternative_reject
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8361 alternative_nregs
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8362 alternative_order
= (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8363 memset ((char *)alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
8364 memset ((char *)alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
8366 /* For each operand, find out which regs are equivalent. */
8367 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8370 struct elt_loc_list
*l
;
8372 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
8374 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8375 right, so avoid the problem here. Likewise if we have a constant
8376 and the insn pattern doesn't tell us the mode we need. */
8377 if (GET_CODE (recog_data
.operand
[i
]) == CODE_LABEL
8378 || (CONSTANT_P (recog_data
.operand
[i
])
8379 && recog_data
.operand_mode
[i
] == VOIDmode
))
8382 v
= cselib_lookup (recog_data
.operand
[i
], recog_data
.operand_mode
[i
], 0);
8386 for (l
= v
->locs
; l
; l
= l
->next
)
8387 if (GET_CODE (l
->loc
) == REG
)
8388 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
8391 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8393 enum machine_mode mode
;
8397 op_alt_regno
[i
] = (int *) alloca (recog_data
.n_alternatives
* sizeof (int));
8398 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
8399 op_alt_regno
[i
][j
] = -1;
8401 p
= constraints
[i
] = recog_data
.constraints
[i
];
8402 mode
= recog_data
.operand_mode
[i
];
8404 /* Add the reject values for each alternative given by the constraints
8405 for this operand. */
8413 alternative_reject
[j
] += 3;
8415 alternative_reject
[j
] += 300;
8418 /* We won't change operands which are already registers. We
8419 also don't want to modify output operands. */
8420 regno
= true_regnum (recog_data
.operand
[i
]);
8422 || constraints
[i
][0] == '='
8423 || constraints
[i
][0] == '+')
8426 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
8428 int class = (int) NO_REGS
;
8430 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
8433 REGNO (reg
) = regno
;
8434 PUT_MODE (reg
, mode
);
8436 /* We found a register equal to this operand. Now look for all
8437 alternatives that can accept this register and have not been
8438 assigned a register they can use yet. */
8447 case '=': case '+': case '?':
8448 case '#': case '&': case '!':
8450 case '0': case '1': case '2': case '3': case '4':
8451 case '5': case '6': case '7': case '8': case '9':
8452 case 'm': case '<': case '>': case 'V': case 'o':
8453 case 'E': case 'F': case 'G': case 'H':
8454 case 's': case 'i': case 'n':
8455 case 'I': case 'J': case 'K': case 'L':
8456 case 'M': case 'N': case 'O': case 'P':
8458 /* These don't say anything we care about. */
8462 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
8467 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
8470 case ',': case '\0':
8471 /* See if REGNO fits this alternative, and set it up as the
8472 replacement register if we don't have one for this
8473 alternative yet and the operand being replaced is not
8474 a cheap CONST_INT. */
8475 if (op_alt_regno
[i
][j
] == -1
8476 && reg_fits_class_p (reg
, class, 0, mode
)
8477 && (GET_CODE (recog_data
.operand
[i
]) != CONST_INT
8478 || (rtx_cost (recog_data
.operand
[i
], SET
)
8479 > rtx_cost (reg
, SET
))))
8481 alternative_nregs
[j
]++;
8482 op_alt_regno
[i
][j
] = regno
;
8494 /* Record all alternatives which are better or equal to the currently
8495 matching one in the alternative_order array. */
8496 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
8497 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
8498 alternative_order
[j
++] = i
;
8499 recog_data
.n_alternatives
= j
;
8501 /* Sort it. Given a small number of alternatives, a dumb algorithm
8502 won't hurt too much. */
8503 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
8506 int best_reject
= alternative_reject
[alternative_order
[i
]];
8507 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
8510 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
8512 int this_reject
= alternative_reject
[alternative_order
[j
]];
8513 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
8515 if (this_reject
< best_reject
8516 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
8519 best_reject
= this_reject
;
8520 best_nregs
= this_nregs
;
8524 tmp
= alternative_order
[best
];
8525 alternative_order
[best
] = alternative_order
[i
];
8526 alternative_order
[i
] = tmp
;
8529 /* Substitute the operands as determined by op_alt_regno for the best
8531 j
= alternative_order
[0];
8533 for (i
= 0; i
< recog_data
.n_operands
; i
++)
8535 enum machine_mode mode
= recog_data
.operand_mode
[i
];
8536 if (op_alt_regno
[i
][j
] == -1)
8539 validate_change (insn
, recog_data
.operand_loc
[i
],
8540 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
8543 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
8545 int op
= recog_data
.dup_num
[i
];
8546 enum machine_mode mode
= recog_data
.operand_mode
[op
];
8548 if (op_alt_regno
[op
][j
] == -1)
8551 validate_change (insn
, recog_data
.dup_loc
[i
],
8552 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
8555 return apply_change_group ();
8558 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8560 This code might also be useful when reload gave up on reg+reg addresssing
8561 because of clashes between the return register and INDEX_REG_CLASS. */
8563 /* The maximum number of uses of a register we can keep track of to
8564 replace them with reg+reg addressing. */
8565 #define RELOAD_COMBINE_MAX_USES 6
8567 /* INSN is the insn where a register has ben used, and USEP points to the
8568 location of the register within the rtl. */
8569 struct reg_use
{ rtx insn
, *usep
; };
8571 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8572 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8573 indicates where it becomes live again.
8574 Otherwise, USE_INDEX is the index of the last encountered use of the
8575 register (which is first among these we have seen since we scan backwards),
8576 OFFSET contains the constant offset that is added to the register in
8577 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8578 last, of these uses.
8579 STORE_RUID is always meaningful if we only want to use a value in a
8580 register in a different place: it denotes the next insn in the insn
8581 stream (i.e. the last ecountered) that sets or clobbers the register. */
8584 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
8589 } reg_state
[FIRST_PSEUDO_REGISTER
];
8591 /* Reverse linear uid. This is increased in reload_combine while scanning
8592 the instructions from last to first. It is used to set last_label_ruid
8593 and the store_ruid / use_ruid fields in reg_state. */
8594 static int reload_combine_ruid
;
8596 #define LABEL_LIVE(LABEL) \
8597 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8603 int first_index_reg
= -1;
8604 int last_index_reg
= 0;
8607 int last_label_ruid
;
8608 int min_labelno
, n_labels
;
8609 HARD_REG_SET ever_live_at_start
, *label_live
;
8611 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8612 reload has already used it where appropriate, so there is no use in
8613 trying to generate it now. */
8614 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
8617 /* To avoid wasting too much time later searching for an index register,
8618 determine the minimum and maximum index register numbers. */
8619 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8620 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
8622 if (first_index_reg
== -1)
8623 first_index_reg
= r
;
8628 /* If no index register is available, we can quit now. */
8629 if (first_index_reg
== -1)
8632 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8633 information is a bit fuzzy immediately after reload, but it's
8634 still good enough to determine which registers are live at a jump
8636 min_labelno
= get_first_label_num ();
8637 n_labels
= max_label_num () - min_labelno
;
8638 label_live
= (HARD_REG_SET
*) xmalloc (n_labels
* sizeof (HARD_REG_SET
));
8639 CLEAR_HARD_REG_SET (ever_live_at_start
);
8641 for (i
= n_basic_blocks
- 1; i
>= 0; i
--)
8643 insn
= BLOCK_HEAD (i
);
8644 if (GET_CODE (insn
) == CODE_LABEL
)
8648 REG_SET_TO_HARD_REG_SET (live
,
8649 BASIC_BLOCK (i
)->global_live_at_start
);
8650 compute_use_by_pseudos (&live
,
8651 BASIC_BLOCK (i
)->global_live_at_start
);
8652 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
8653 IOR_HARD_REG_SET (ever_live_at_start
, live
);
8657 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8658 last_label_ruid
= reload_combine_ruid
= 0;
8659 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8661 reg_state
[r
].store_ruid
= reload_combine_ruid
;
8663 reg_state
[r
].use_index
= -1;
8665 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8668 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
8672 /* We cannot do our optimization across labels. Invalidating all the use
8673 information we have would be costly, so we just note where the label
8674 is and then later disable any optimization that would cross it. */
8675 if (GET_CODE (insn
) == CODE_LABEL
)
8676 last_label_ruid
= reload_combine_ruid
;
8677 else if (GET_CODE (insn
) == BARRIER
)
8678 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8679 if (! fixed_regs
[r
])
8680 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8682 if (! INSN_P (insn
))
8685 reload_combine_ruid
++;
8687 /* Look for (set (REGX) (CONST_INT))
8688 (set (REGX) (PLUS (REGX) (REGY)))
8690 ... (MEM (REGX)) ...
8692 (set (REGZ) (CONST_INT))
8694 ... (MEM (PLUS (REGZ) (REGY)))... .
8696 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8697 and that we know all uses of REGX before it dies. */
8698 set
= single_set (insn
);
8700 && GET_CODE (SET_DEST (set
)) == REG
8701 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
8702 GET_MODE (SET_DEST (set
)))
8704 && GET_CODE (SET_SRC (set
)) == PLUS
8705 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
8706 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
8707 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
8709 rtx reg
= SET_DEST (set
);
8710 rtx plus
= SET_SRC (set
);
8711 rtx base
= XEXP (plus
, 1);
8712 rtx prev
= prev_nonnote_insn (insn
);
8713 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
8714 unsigned int regno
= REGNO (reg
);
8715 rtx const_reg
= NULL_RTX
;
8716 rtx reg_sum
= NULL_RTX
;
8718 /* Now, we need an index register.
8719 We'll set index_reg to this index register, const_reg to the
8720 register that is to be loaded with the constant
8721 (denoted as REGZ in the substitution illustration above),
8722 and reg_sum to the register-register that we want to use to
8723 substitute uses of REG (typically in MEMs) with.
8724 First check REG and BASE for being index registers;
8725 we can use them even if they are not dead. */
8726 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
8727 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
8735 /* Otherwise, look for a free index register. Since we have
8736 checked above that neiter REG nor BASE are index registers,
8737 if we find anything at all, it will be different from these
8739 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
8741 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
8743 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
8744 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
8745 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
8747 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
8749 const_reg
= index_reg
;
8750 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
8756 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8757 (REGY), i.e. BASE, is not clobbered before the last use we'll
8760 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
8761 && rtx_equal_p (SET_DEST (prev_set
), reg
)
8762 && reg_state
[regno
].use_index
>= 0
8763 && (reg_state
[REGNO (base
)].store_ruid
8764 <= reg_state
[regno
].use_ruid
)
8769 /* Change destination register and, if necessary, the
8770 constant value in PREV, the constant loading instruction. */
8771 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
8772 if (reg_state
[regno
].offset
!= const0_rtx
)
8773 validate_change (prev
,
8774 &SET_SRC (prev_set
),
8775 GEN_INT (INTVAL (SET_SRC (prev_set
))
8776 + INTVAL (reg_state
[regno
].offset
)),
8779 /* Now for every use of REG that we have recorded, replace REG
8781 for (i
= reg_state
[regno
].use_index
;
8782 i
< RELOAD_COMBINE_MAX_USES
; i
++)
8783 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
8784 reg_state
[regno
].reg_use
[i
].usep
,
8787 if (apply_change_group ())
8791 /* Delete the reg-reg addition. */
8792 PUT_CODE (insn
, NOTE
);
8793 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8794 NOTE_SOURCE_FILE (insn
) = 0;
8796 if (reg_state
[regno
].offset
!= const0_rtx
)
8797 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8799 for (np
= ®_NOTES (prev
); *np
;)
8801 if (REG_NOTE_KIND (*np
) == REG_EQUAL
8802 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
8803 *np
= XEXP (*np
, 1);
8805 np
= &XEXP (*np
, 1);
8808 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
8809 reg_state
[REGNO (const_reg
)].store_ruid
8810 = reload_combine_ruid
;
8816 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
8818 if (GET_CODE (insn
) == CALL_INSN
)
8822 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
8823 if (call_used_regs
[r
])
8825 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
8826 reg_state
[r
].store_ruid
= reload_combine_ruid
;
8829 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
8830 link
= XEXP (link
, 1))
8832 rtx usage_rtx
= XEXP (XEXP (link
, 0), 0);
8833 if (GET_CODE (usage_rtx
) == REG
)
8836 unsigned int start_reg
= REGNO (usage_rtx
);
8837 unsigned int num_regs
=
8838 HARD_REGNO_NREGS (start_reg
, GET_MODE (usage_rtx
));
8839 unsigned int end_reg
= start_reg
+ num_regs
- 1;
8840 for (i
= start_reg
; i
<= end_reg
; i
++)
8841 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
8843 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8844 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8847 reg_state
[i
].use_index
= -1;
8852 else if (GET_CODE (insn
) == JUMP_INSN
8853 && GET_CODE (PATTERN (insn
)) != RETURN
)
8855 /* Non-spill registers might be used at the call destination in
8856 some unknown fashion, so we have to mark the unknown use. */
8859 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
8860 && JUMP_LABEL (insn
))
8861 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
8863 live
= &ever_live_at_start
;
8865 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
8866 if (TEST_HARD_REG_BIT (*live
, i
))
8867 reg_state
[i
].use_index
= -1;
8870 reload_combine_note_use (&PATTERN (insn
), insn
);
8871 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
8873 if (REG_NOTE_KIND (note
) == REG_INC
8874 && GET_CODE (XEXP (note
, 0)) == REG
)
8876 int regno
= REGNO (XEXP (note
, 0));
8878 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
8879 reg_state
[regno
].use_index
= -1;
8887 /* Check if DST is a register or a subreg of a register; if it is,
8888 update reg_state[regno].store_ruid and reg_state[regno].use_index
8889 accordingly. Called via note_stores from reload_combine. */
8892 reload_combine_note_store (dst
, set
, data
)
8894 void *data ATTRIBUTE_UNUSED
;
8898 enum machine_mode mode
= GET_MODE (dst
);
8900 if (GET_CODE (dst
) == SUBREG
)
8902 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
8903 GET_MODE (SUBREG_REG (dst
)),
8906 dst
= SUBREG_REG (dst
);
8908 if (GET_CODE (dst
) != REG
)
8910 regno
+= REGNO (dst
);
8912 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8913 careful with registers / register parts that are not full words.
8915 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8916 if (GET_CODE (set
) != SET
8917 || GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
8918 || GET_CODE (SET_DEST (set
)) == SIGN_EXTRACT
8919 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
8921 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8923 reg_state
[i
].use_index
= -1;
8924 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8929 for (i
= HARD_REGNO_NREGS (regno
, mode
) - 1 + regno
; i
>= regno
; i
--)
8931 reg_state
[i
].store_ruid
= reload_combine_ruid
;
8932 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
8937 /* XP points to a piece of rtl that has to be checked for any uses of
8939 *XP is the pattern of INSN, or a part of it.
8940 Called from reload_combine, and recursively by itself. */
8942 reload_combine_note_use (xp
, insn
)
8946 enum rtx_code code
= x
->code
;
8949 rtx offset
= const0_rtx
; /* For the REG case below. */
8954 if (GET_CODE (SET_DEST (x
)) == REG
)
8956 reload_combine_note_use (&SET_SRC (x
), insn
);
8962 /* If this is the USE of a return value, we can't change it. */
8963 if (GET_CODE (XEXP (x
, 0)) == REG
&& REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
8965 /* Mark the return register as used in an unknown fashion. */
8966 rtx reg
= XEXP (x
, 0);
8967 int regno
= REGNO (reg
);
8968 int nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
8970 while (--nregs
>= 0)
8971 reg_state
[regno
+ nregs
].use_index
= -1;
8977 if (GET_CODE (SET_DEST (x
)) == REG
)
8982 /* We are interested in (plus (reg) (const_int)) . */
8983 if (GET_CODE (XEXP (x
, 0)) != REG
8984 || GET_CODE (XEXP (x
, 1)) != CONST_INT
)
8986 offset
= XEXP (x
, 1);
8991 int regno
= REGNO (x
);
8995 /* Some spurious USEs of pseudo registers might remain.
8996 Just ignore them. */
8997 if (regno
>= FIRST_PSEUDO_REGISTER
)
9000 nregs
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
9002 /* We can't substitute into multi-hard-reg uses. */
9005 while (--nregs
>= 0)
9006 reg_state
[regno
+ nregs
].use_index
= -1;
9010 /* If this register is already used in some unknown fashion, we
9012 If we decrement the index from zero to -1, we can't store more
9013 uses, so this register becomes used in an unknown fashion. */
9014 use_index
= --reg_state
[regno
].use_index
;
9018 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
9020 /* We have found another use for a register that is already
9021 used later. Check if the offsets match; if not, mark the
9022 register as used in an unknown fashion. */
9023 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
9025 reg_state
[regno
].use_index
= -1;
9031 /* This is the first use of this register we have seen since we
9032 marked it as dead. */
9033 reg_state
[regno
].offset
= offset
;
9034 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
9036 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
9037 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
9045 /* Recursively process the components of X. */
9046 fmt
= GET_RTX_FORMAT (code
);
9047 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9050 reload_combine_note_use (&XEXP (x
, i
), insn
);
9051 else if (fmt
[i
] == 'E')
9053 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9054 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
9059 /* See if we can reduce the cost of a constant by replacing a move
9060 with an add. We track situations in which a register is set to a
9061 constant or to a register plus a constant. */
9062 /* We cannot do our optimization across labels. Invalidating all the
9063 information about register contents we have would be costly, so we
9064 use move2add_last_label_luid to note where the label is and then
9065 later disable any optimization that would cross it.
9066 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9067 reg_set_luid[n] is greater than last_label_luid[n] . */
9068 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
9070 /* If reg_base_reg[n] is negative, register n has been set to
9071 reg_offset[n] in mode reg_mode[n] .
9072 If reg_base_reg[n] is non-negative, register n has been set to the
9073 sum of reg_offset[n] and the value of register reg_base_reg[n]
9074 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9075 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
9076 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
9077 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
9079 /* move2add_luid is linearily increased while scanning the instructions
9080 from first to last. It is used to set reg_set_luid in
9081 reload_cse_move2add and move2add_note_store. */
9082 static int move2add_luid
;
9084 /* move2add_last_label_luid is set whenever a label is found. Labels
9085 invalidate all previously collected reg_offset data. */
9086 static int move2add_last_label_luid
;
9088 /* Generate a CONST_INT and force it in the range of MODE. */
9090 static HOST_WIDE_INT
9091 sext_for_mode (mode
, value
)
9092 enum machine_mode mode
;
9093 HOST_WIDE_INT value
;
9095 HOST_WIDE_INT cval
= value
& GET_MODE_MASK (mode
);
9096 int width
= GET_MODE_BITSIZE (mode
);
9098 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9100 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
9101 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
9102 cval
|= (HOST_WIDE_INT
) -1 << width
;
9107 /* ??? We don't know how zero / sign extension is handled, hence we
9108 can't go from a narrower to a wider mode. */
9109 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9110 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9111 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9112 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9113 GET_MODE_BITSIZE (INMODE))))
9116 reload_cse_move2add (first
)
9122 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
9123 reg_set_luid
[i
] = 0;
9125 move2add_last_label_luid
= 0;
9127 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
9131 if (GET_CODE (insn
) == CODE_LABEL
)
9133 move2add_last_label_luid
= move2add_luid
;
9134 /* We're going to increment move2add_luid twice after a
9135 label, so that we can use move2add_last_label_luid + 1 as
9136 the luid for constants. */
9140 if (! INSN_P (insn
))
9142 pat
= PATTERN (insn
);
9143 /* For simplicity, we only perform this optimization on
9144 straightforward SETs. */
9145 if (GET_CODE (pat
) == SET
9146 && GET_CODE (SET_DEST (pat
)) == REG
)
9148 rtx reg
= SET_DEST (pat
);
9149 int regno
= REGNO (reg
);
9150 rtx src
= SET_SRC (pat
);
9152 /* Check if we have valid information on the contents of this
9153 register in the mode of REG. */
9154 if (reg_set_luid
[regno
] > move2add_last_label_luid
9155 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
]))
9157 /* Try to transform (set (REGX) (CONST_INT A))
9159 (set (REGX) (CONST_INT B))
9161 (set (REGX) (CONST_INT A))
9163 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9165 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
9168 rtx new_src
= GEN_INT (sext_for_mode (GET_MODE (reg
),
9170 - reg_offset
[regno
]));
9171 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9172 use (set (reg) (reg)) instead.
9173 We don't delete this insn, nor do we convert it into a
9174 note, to avoid losing register notes or the return
9175 value flag. jump2 already knowns how to get rid of
9177 if (new_src
== const0_rtx
)
9178 success
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
9179 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
9180 && have_add2_insn (reg
, new_src
))
9181 success
= validate_change (insn
, &PATTERN (insn
),
9182 gen_add2_insn (reg
, new_src
), 0);
9183 reg_set_luid
[regno
] = move2add_luid
;
9184 reg_mode
[regno
] = GET_MODE (reg
);
9185 reg_offset
[regno
] = INTVAL (src
);
9189 /* Try to transform (set (REGX) (REGY))
9190 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9193 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9196 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9198 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9199 else if (GET_CODE (src
) == REG
9200 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
9201 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
9202 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
),
9203 reg_mode
[REGNO (src
)]))
9205 rtx next
= next_nonnote_insn (insn
);
9208 set
= single_set (next
);
9210 && SET_DEST (set
) == reg
9211 && GET_CODE (SET_SRC (set
)) == PLUS
9212 && XEXP (SET_SRC (set
), 0) == reg
9213 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
9215 rtx src3
= XEXP (SET_SRC (set
), 1);
9216 HOST_WIDE_INT added_offset
= INTVAL (src3
);
9217 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
9218 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
9219 rtx new_src
= GEN_INT (sext_for_mode (GET_MODE (reg
),
9225 if (new_src
== const0_rtx
)
9226 /* See above why we create (set (reg) (reg)) here. */
9228 = validate_change (next
, &SET_SRC (set
), reg
, 0);
9229 else if ((rtx_cost (new_src
, PLUS
)
9230 < COSTS_N_INSNS (1) + rtx_cost (src3
, SET
))
9231 && have_add2_insn (reg
, new_src
))
9233 = validate_change (next
, &PATTERN (next
),
9234 gen_add2_insn (reg
, new_src
), 0);
9237 /* INSN might be the first insn in a basic block
9238 if the preceding insn is a conditional jump
9239 or a possible-throwing call. */
9240 PUT_CODE (insn
, NOTE
);
9241 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9242 NOTE_SOURCE_FILE (insn
) = 0;
9245 reg_mode
[regno
] = GET_MODE (reg
);
9246 reg_offset
[regno
] = sext_for_mode (GET_MODE (reg
),
9255 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9257 if (REG_NOTE_KIND (note
) == REG_INC
9258 && GET_CODE (XEXP (note
, 0)) == REG
)
9260 /* Reset the information about this register. */
9261 int regno
= REGNO (XEXP (note
, 0));
9262 if (regno
< FIRST_PSEUDO_REGISTER
)
9263 reg_set_luid
[regno
] = 0;
9266 note_stores (PATTERN (insn
), move2add_note_store
, NULL
);
9267 /* If this is a CALL_INSN, all call used registers are stored with
9269 if (GET_CODE (insn
) == CALL_INSN
)
9271 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
9273 if (call_used_regs
[i
])
9274 /* Reset the information about this register. */
9275 reg_set_luid
[i
] = 0;
9281 /* SET is a SET or CLOBBER that sets DST.
9282 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9283 Called from reload_cse_move2add via note_stores. */
9286 move2add_note_store (dst
, set
, data
)
9288 void *data ATTRIBUTE_UNUSED
;
9290 unsigned int regno
= 0;
9292 enum machine_mode mode
= GET_MODE (dst
);
9294 if (GET_CODE (dst
) == SUBREG
)
9296 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
9297 GET_MODE (SUBREG_REG (dst
)),
9300 dst
= SUBREG_REG (dst
);
9303 /* Some targets do argument pushes without adding REG_INC notes. */
9305 if (GET_CODE (dst
) == MEM
)
9307 dst
= XEXP (dst
, 0);
9308 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_DEC
9309 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
9310 reg_set_luid
[REGNO (XEXP (dst
, 0))] = 0;
9313 if (GET_CODE (dst
) != REG
)
9316 regno
+= REGNO (dst
);
9318 if (HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
9319 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
9320 && GET_CODE (SET_DEST (set
)) != SIGN_EXTRACT
9321 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
9323 rtx src
= SET_SRC (set
);
9325 HOST_WIDE_INT offset
;
9327 /* This may be different from mode, if SET_DEST (set) is a
9329 enum machine_mode dst_mode
= GET_MODE (dst
);
9331 switch (GET_CODE (src
))
9334 if (GET_CODE (XEXP (src
, 0)) == REG
)
9336 base_reg
= XEXP (src
, 0);
9338 if (GET_CODE (XEXP (src
, 1)) == CONST_INT
)
9339 offset
= INTVAL (XEXP (src
, 1));
9340 else if (GET_CODE (XEXP (src
, 1)) == REG
9341 && (reg_set_luid
[REGNO (XEXP (src
, 1))]
9342 > move2add_last_label_luid
)
9343 && (MODES_OK_FOR_MOVE2ADD
9344 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))])))
9346 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0)
9347 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
9348 /* Maybe the first register is known to be a
9350 else if (reg_set_luid
[REGNO (base_reg
)]
9351 > move2add_last_label_luid
9352 && (MODES_OK_FOR_MOVE2ADD
9353 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))]))
9354 && reg_base_reg
[REGNO (base_reg
)] < 0)
9356 offset
= reg_offset
[REGNO (base_reg
)];
9357 base_reg
= XEXP (src
, 1);
9376 /* Start tracking the register as a constant. */
9377 reg_base_reg
[regno
] = -1;
9378 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
9379 /* We assign the same luid to all registers set to constants. */
9380 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
9381 reg_mode
[regno
] = mode
;
9386 /* Invalidate the contents of the register. */
9387 reg_set_luid
[regno
] = 0;
9391 base_regno
= REGNO (base_reg
);
9392 /* If information about the base register is not valid, set it
9393 up as a new base register, pretending its value is known
9394 starting from the current insn. */
9395 if (reg_set_luid
[base_regno
] <= move2add_last_label_luid
)
9397 reg_base_reg
[base_regno
] = base_regno
;
9398 reg_offset
[base_regno
] = 0;
9399 reg_set_luid
[base_regno
] = move2add_luid
;
9400 reg_mode
[base_regno
] = mode
;
9402 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode
,
9403 reg_mode
[base_regno
]))
9406 reg_mode
[regno
] = mode
;
9408 /* Copy base information from our base register. */
9409 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
9410 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
9412 /* Compute the sum of the offsets or constants. */
9413 reg_offset
[regno
] = sext_for_mode (dst_mode
,
9415 + reg_offset
[base_regno
]);
9419 unsigned int endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
9421 for (i
= regno
; i
< endregno
; i
++)
9422 /* Reset the information about this register. */
9423 reg_set_luid
[i
] = 0;
9429 add_auto_inc_notes (insn
, x
)
9433 enum rtx_code code
= GET_CODE (x
);
9437 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9440 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
9444 /* Scan all the operand sub-expressions. */
9445 fmt
= GET_RTX_FORMAT (code
);
9446 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9449 add_auto_inc_notes (insn
, XEXP (x
, i
));
9450 else if (fmt
[i
] == 'E')
9451 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9452 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
9457 /* Copy EH notes from an insn to its reloads. */
9459 copy_eh_notes (insn
, x
)
9463 rtx eh_note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
9466 for (; x
!= 0; x
= NEXT_INSN (x
))
9468 if (may_trap_p (PATTERN (x
)))
9470 = gen_rtx_EXPR_LIST (REG_EH_REGION
, XEXP (eh_note
, 0),
9476 /* This is used by reload pass, that does emit some instructions after
9477 abnormal calls moving basic block end, but in fact it wants to emit
9478 them on the edge. Looks for abnormal call edges, find backward the
9479 proper call and fix the damage.
9481 Similar handle instructions throwing exceptions internally. */
9483 fixup_abnormal_edges ()
9486 bool inserted
= false;
9488 for (i
= 0; i
< n_basic_blocks
; i
++)
9490 basic_block bb
= BASIC_BLOCK (i
);
9493 /* Look for cases we are interested in - an calls or instructions causing
9495 for (e
= bb
->succ
; e
; e
= e
->succ_next
)
9497 if (e
->flags
& EDGE_ABNORMAL_CALL
)
9499 if ((e
->flags
& (EDGE_ABNORMAL
| EDGE_EH
))
9500 == (EDGE_ABNORMAL
| EDGE_EH
))
9503 if (e
&& GET_CODE (bb
->end
) != CALL_INSN
&& !can_throw_internal (bb
->end
))
9507 for (e
= bb
->succ
; e
; e
= e
->succ_next
)
9508 if (e
->flags
& EDGE_FALLTHRU
)
9510 /* Get past the new insns generated. Allow notes, as the insns may
9511 be already deleted. */
9512 while ((GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == NOTE
)
9513 && !can_throw_internal (insn
)
9514 && insn
!= bb
->head
)
9515 insn
= PREV_INSN (insn
);
9516 if (GET_CODE (insn
) != CALL_INSN
&& !can_throw_internal (insn
))
9520 insn
= NEXT_INSN (insn
);
9521 while (insn
&& GET_CODE (insn
) == INSN
)
9523 next
= NEXT_INSN (insn
);
9524 insert_insn_on_edge (PATTERN (insn
), e
);
9525 flow_delete_insn (insn
);
9531 commit_edge_insertions ();