1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 All the pseudos that were formerly allocated to the hard regs that
58 are now in use as reload regs must be ``spilled''. This means
59 that they go to other hard regs, or to stack slots if no other
60 available hard regs can be found. Spilling can invalidate more
61 insns, requiring additional need for reloads, so we must keep checking
62 until the process stabilizes.
64 For machines with different classes of registers, we must keep track
65 of the register class needed for each reload, and make sure that
66 we allocate enough reload registers of each class.
68 The file reload.c contains the code that checks one insn for
69 validity and reports the reloads that it needs. This file
70 is in charge of scanning the entire rtl code, accumulating the
71 reload needs, spilling, assigning reload registers to use for
72 fixing up each insn, and generating the new insns to copy values
73 into the reload registers. */
76 #ifndef REGISTER_MOVE_COST
77 #define REGISTER_MOVE_COST(x, y) 2
80 /* During reload_as_needed, element N contains a REG rtx for the hard reg
81 into which reg N has been reloaded (perhaps for a previous insn). */
82 static rtx
*reg_last_reload_reg
;
84 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
85 for an output reload that stores into reg N. */
86 static char *reg_has_output_reload
;
88 /* Indicates which hard regs are reload-registers for an output reload
89 in the current insn. */
90 static HARD_REG_SET reg_is_output_reload
;
92 /* Element N is the constant value to which pseudo reg N is equivalent,
93 or zero if pseudo reg N is not equivalent to a constant.
94 find_reloads looks at this in order to replace pseudo reg N
95 with the constant it stands for. */
96 rtx
*reg_equiv_constant
;
98 /* Element N is a memory location to which pseudo reg N is equivalent,
99 prior to any register elimination (such as frame pointer to stack
100 pointer). Depending on whether or not it is a valid address, this value
101 is transferred to either reg_equiv_address or reg_equiv_mem. */
102 rtx
*reg_equiv_memory_loc
;
104 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
105 This is used when the address is not valid as a memory address
106 (because its displacement is too big for the machine.) */
107 rtx
*reg_equiv_address
;
109 /* Element N is the memory slot to which pseudo reg N is equivalent,
110 or zero if pseudo reg N is not equivalent to a memory slot. */
113 /* Widest width in which each pseudo reg is referred to (via subreg). */
114 static int *reg_max_ref_width
;
116 /* Element N is the insn that initialized reg N from its equivalent
117 constant or memory slot. */
118 static rtx
*reg_equiv_init
;
120 /* During reload_as_needed, element N contains the last pseudo regno reloaded
121 into hard register N. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
126 /* During reload_as_needed, element N contains the insn for which
127 hard register N was last used. Its contents are significant only
128 when reg_reloaded_valid is set for this register. */
129 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
131 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
132 static HARD_REG_SET reg_reloaded_valid
;
133 /* Indicate if the register was dead at the end of the reload.
134 This is only valid if reg_reloaded_contents is set and valid. */
135 static HARD_REG_SET reg_reloaded_dead
;
137 /* Number of spill-regs so far; number of valid elements of spill_regs. */
140 /* In parallel with spill_regs, contains REG rtx's for those regs.
141 Holds the last rtx used for any given reg, or 0 if it has never
142 been used for spilling yet. This rtx is reused, provided it has
144 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
146 /* In parallel with spill_regs, contains nonzero for a spill reg
147 that was stored after the last time it was used.
148 The precise value is the insn generated to do the store. */
149 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
151 /* This is the register that was stored with spill_reg_store. This is a
152 copy of reload_out / reload_out_reg when the value was stored; if
153 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
154 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
156 /* This table is the inverse mapping of spill_regs:
157 indexed by hard reg number,
158 it contains the position of that reg in spill_regs,
159 or -1 for something that is not in spill_regs.
161 ?!? This is no longer accurate. */
162 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
164 /* This reg set indicates registers that may not be used for retrying global
165 allocation. The registers that may not be used include all spill registers
166 and the frame pointer (if we are using one). */
167 HARD_REG_SET forbidden_regs
;
169 /* This reg set indicates registers that are not good for spill registers.
170 They will not be used to complete groups of spill registers. This includes
171 all fixed registers, registers that may be eliminated, and, if
172 SMALL_REGISTER_CLASSES is zero, registers explicitly used in the rtl.
174 (spill_reg_order prevents these registers from being used to start a
176 static HARD_REG_SET bad_spill_regs
;
178 /* Describes order of use of registers for reloading
179 of spilled pseudo-registers. `spills' is the number of
180 elements that are actually valid; new ones are added at the end. */
181 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
183 /* This reg set indicates those registers that have been used a spill
184 registers. This information is used in reorg.c, to help figure out
185 what registers are live at any point. It is assumed that all spill_regs
186 are dead at every CODE_LABEL. */
187 HARD_REG_SET used_spill_regs
;
189 /* Index of last register assigned as a spill register. We allocate in
190 a round-robin fashion. */
191 static int last_spill_reg
;
193 /* Describes order of preference for putting regs into spill_regs.
194 Contains the numbers of all the hard regs, in order most preferred first.
195 This order is different for each function.
196 It is set up by order_regs_for_reload.
197 Empty elements at the end contain -1. */
198 static short potential_reload_regs
[FIRST_PSEUDO_REGISTER
];
200 /* 1 for a hard register that appears explicitly in the rtl
201 (for example, function value registers, special registers
202 used by insns, structure value pointer registers). */
203 static char regs_explicitly_used
[FIRST_PSEUDO_REGISTER
];
205 /* Indicates if a register was counted against the need for
206 groups. 0 means it can count against max_nongroup instead. */
207 static HARD_REG_SET counted_for_groups
;
209 /* Indicates if a register was counted against the need for
210 non-groups. 0 means it can become part of a new group.
211 During choose_reload_regs, 1 here means don't use this reg
212 as part of a group, even if it seems to be otherwise ok. */
213 static HARD_REG_SET counted_for_nongroups
;
215 /* Nonzero if indirect addressing is supported on the machine; this means
216 that spilling (REG n) does not require reloading it into a register in
217 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
218 value indicates the level of indirect addressing supported, e.g., two
219 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
221 static char spill_indirect_levels
;
223 /* Nonzero if indirect addressing is supported when the innermost MEM is
224 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
225 which these are valid is the same as spill_indirect_levels, above. */
226 char indirect_symref_ok
;
228 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
229 char double_reg_address_ok
;
231 /* Record the stack slot for each spilled hard register. */
232 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
234 /* Width allocated so far for that stack slot. */
235 static int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
237 /* Record which pseudos needed to be spilled. */
238 static regset spilled_pseudos
;
240 /* Indexed by register class and basic block number, nonzero if there is
241 any need for a spill register of that class in that basic block.
242 The pointer is 0 if we did stupid allocation and don't know
243 the structure of basic blocks. */
244 char *basic_block_needs
[N_REG_CLASSES
];
246 /* First uid used by insns created by reload in this function.
247 Used in find_equiv_reg. */
248 int reload_first_uid
;
250 /* Flag set by local-alloc or global-alloc if anything is live in
251 a call-clobbered reg across calls. */
252 int caller_save_needed
;
254 /* The register class to use for a base register when reloading an
255 address. This is normally BASE_REG_CLASS, but it may be different
256 when using SMALL_REGISTER_CLASSES and passing parameters in
258 enum reg_class reload_address_base_reg_class
;
260 /* The register class to use for an index register when reloading an
261 address. This is normally INDEX_REG_CLASS, but it may be different
262 when using SMALL_REGISTER_CLASSES and passing parameters in
264 enum reg_class reload_address_index_reg_class
;
266 /* Set to 1 while reload_as_needed is operating.
267 Required by some machines to handle any generated moves differently. */
269 int reload_in_progress
= 0;
271 /* These arrays record the insn_code of insns that may be needed to
272 perform input and output reloads of special objects. They provide a
273 place to pass a scratch register. */
275 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
276 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
278 /* This obstack is used for allocation of rtl during register elimination.
279 The allocated storage can be freed once find_reloads has processed the
282 struct obstack reload_obstack
;
284 /* Points to the beginning of the reload_obstack. All insn_chain structures
285 are allocated first. */
286 char *reload_startobj
;
288 /* The point after all insn_chain structures. Used to quickly deallocate
289 memory used while processing one insn. */
290 char *reload_firstobj
;
292 #define obstack_chunk_alloc xmalloc
293 #define obstack_chunk_free free
295 /* List of labels that must never be deleted. */
296 extern rtx forced_labels
;
298 /* List of insn_chain instructions, one for every insn that reload needs to
300 struct insn_chain
*reload_insn_chain
;
302 /* List of insns needing reloads. */
303 static struct insn_chain
*insns_need_reload
;
305 /* This structure is used to record information about register eliminations.
306 Each array entry describes one possible way of eliminating a register
307 in favor of another. If there is more than one way of eliminating a
308 particular register, the most preferred should be specified first. */
310 static struct elim_table
312 int from
; /* Register number to be eliminated. */
313 int to
; /* Register number used as replacement. */
314 int initial_offset
; /* Initial difference between values. */
315 int can_eliminate
; /* Non-zero if this elimination can be done. */
316 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
317 insns made by reload. */
318 int offset
; /* Current offset between the two regs. */
319 int max_offset
; /* Maximum offset between the two regs. */
320 int previous_offset
; /* Offset at end of previous insn. */
321 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx
; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx
; /* REG rtx for the replacement. */
330 /* If a set of eliminable registers was specified, define the table from it.
331 Otherwise, default to the normal case of the frame pointer being
332 replaced by the stack pointer. */
334 #ifdef ELIMINABLE_REGS
337 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
340 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
342 /* Record the number of pending eliminations that have an offset not equal
343 to their initial offset. If non-zero, we use a new copy of each
344 replacement result in any insns encountered. */
345 int num_not_at_initial_offset
;
347 /* Count the number of registers that we may be able to eliminate. */
348 static int num_eliminable
;
350 /* For each label, we record the offset of each elimination. If we reach
351 a label by more than one path and an offset differs, we cannot do the
352 elimination. This information is indexed by the number of the label.
353 The first table is an array of flags that records whether we have yet
354 encountered a label and the second table is an array of arrays, one
355 entry in the latter array for each elimination. */
357 static char *offsets_known_at
;
358 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
360 /* Number of labels in the current function. */
362 static int num_labels
;
364 struct hard_reg_n_uses
{ int regno
; int uses
; };
366 static void dump_needs
PROTO((FILE *));
367 static void maybe_fix_stack_asms
PROTO((void));
368 static int calculate_needs_all_insns
PROTO((int));
369 static int calculate_needs
PROTO((struct insn_chain
*, rtx
, int));
370 static int find_reload_regs
PROTO((int, FILE *));
371 static int find_tworeg_group
PROTO((int, int, FILE *));
372 static int find_group
PROTO((int, int, FILE *));
373 static int possible_group_p
PROTO((int, int *));
374 static void count_possible_groups
PROTO((int *, enum machine_mode
*,
376 static int modes_equiv_for_class_p
PROTO((enum machine_mode
,
379 static void delete_caller_save_insns
PROTO((void));
380 static void spill_failure
PROTO((rtx
));
381 static int new_spill_reg
PROTO((int, int, int *, int *, int,
383 static void delete_dead_insn
PROTO((rtx
));
384 static void alter_reg
PROTO((int, int));
385 static void set_label_offsets
PROTO((rtx
, rtx
, int));
386 static int eliminate_regs_in_insn
PROTO((rtx
, int));
387 static void update_eliminable_offsets
PROTO((void));
388 static void mark_not_eliminable
PROTO((rtx
, rtx
));
389 static void set_initial_elim_offsets
PROTO((void));
390 static void init_elim_table
PROTO((void));
391 static void update_eliminables
PROTO((HARD_REG_SET
*));
392 static int spill_hard_reg
PROTO((int, int, FILE *, int));
393 static void finish_spills
PROTO((int, FILE *));
394 static void scan_paradoxical_subregs
PROTO((rtx
));
395 static int hard_reg_use_compare
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
396 static void order_regs_for_reload
PROTO((void));
397 static int compare_spill_regs
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
398 static void reload_as_needed
PROTO((int));
399 static void forget_old_reloads_1
PROTO((rtx
, rtx
));
400 static int reload_reg_class_lower
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
401 static void mark_reload_reg_in_use
PROTO((int, int, enum reload_type
,
403 static void clear_reload_reg_in_use
PROTO((int, int, enum reload_type
,
405 static int reload_reg_free_p
PROTO((int, int, enum reload_type
));
406 static int reload_reg_free_before_p
PROTO((int, int, enum reload_type
, int));
407 static int reload_reg_free_for_value_p
PROTO((int, int, enum reload_type
, rtx
, rtx
, int));
408 static int reload_reg_reaches_end_p
PROTO((int, int, enum reload_type
));
409 static int allocate_reload_reg
PROTO((struct insn_chain
*, int, int, int));
410 static void choose_reload_regs
PROTO((struct insn_chain
*, rtx
));
411 static void merge_assigned_reloads
PROTO((rtx
));
412 static void emit_reload_insns
PROTO((struct insn_chain
*));
413 static void delete_output_reload
PROTO((rtx
, int, int));
414 static void delete_address_reloads
PROTO((rtx
, rtx
));
415 static void delete_address_reloads_1
PROTO((rtx
, rtx
, rtx
));
416 static rtx inc_for_reload
PROTO((rtx
, rtx
, rtx
, int));
417 static int constraint_accepts_reg_p
PROTO((char *, rtx
));
418 static void reload_cse_regs_1
PROTO((rtx
));
419 static void reload_cse_invalidate_regno
PROTO((int, enum machine_mode
, int));
420 static int reload_cse_mem_conflict_p
PROTO((rtx
, rtx
));
421 static void reload_cse_invalidate_mem
PROTO((rtx
));
422 static void reload_cse_invalidate_rtx
PROTO((rtx
, rtx
));
423 static int reload_cse_regno_equal_p
PROTO((int, rtx
, enum machine_mode
));
424 static int reload_cse_noop_set_p
PROTO((rtx
, rtx
));
425 static int reload_cse_simplify_set
PROTO((rtx
, rtx
));
426 static int reload_cse_simplify_operands
PROTO((rtx
));
427 static void reload_cse_check_clobber
PROTO((rtx
, rtx
));
428 static void reload_cse_record_set
PROTO((rtx
, rtx
));
429 static void reload_combine
PROTO((void));
430 static void reload_combine_note_use
PROTO((rtx
*, rtx
));
431 static void reload_combine_note_store
PROTO((rtx
, rtx
));
432 static void reload_cse_move2add
PROTO((rtx
));
433 static void move2add_note_store
PROTO((rtx
, rtx
));
435 /* Initialize the reload pass once per compilation. */
442 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
443 Set spill_indirect_levels to the number of levels such addressing is
444 permitted, zero if it is not permitted at all. */
447 = gen_rtx_MEM (Pmode
,
449 gen_rtx_REG (Pmode
, LAST_VIRTUAL_REGISTER
+ 1),
451 spill_indirect_levels
= 0;
453 while (memory_address_p (QImode
, tem
))
455 spill_indirect_levels
++;
456 tem
= gen_rtx_MEM (Pmode
, tem
);
459 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
461 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
462 indirect_symref_ok
= memory_address_p (QImode
, tem
);
464 /* See if reg+reg is a valid (and offsettable) address. */
466 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
468 tem
= gen_rtx_PLUS (Pmode
,
469 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
470 gen_rtx_REG (Pmode
, i
));
471 /* This way, we make sure that reg+reg is an offsettable address. */
472 tem
= plus_constant (tem
, 4);
474 if (memory_address_p (QImode
, tem
))
476 double_reg_address_ok
= 1;
481 /* Initialize obstack for our rtl allocation. */
482 gcc_obstack_init (&reload_obstack
);
483 reload_startobj
= (char *) obstack_alloc (&reload_obstack
, 0);
485 /* Decide which register class should be used when reloading
486 addresses. If we are using SMALL_REGISTER_CLASSES, and any
487 parameters are passed in registers, then we do not want to use
488 those registers when reloading an address. Otherwise, if a
489 function argument needs a reload, we may wind up clobbering
490 another argument to the function which was already computed. If
491 we find a subset class which simply avoids those registers, we
492 use it instead. ??? It would be better to only use the
493 restricted class when we actually are loading function arguments,
494 but that is hard to determine. */
495 reload_address_base_reg_class
= BASE_REG_CLASS
;
496 reload_address_index_reg_class
= INDEX_REG_CLASS
;
497 if (SMALL_REGISTER_CLASSES
)
500 HARD_REG_SET base
, index
;
503 COPY_HARD_REG_SET (base
, reg_class_contents
[BASE_REG_CLASS
]);
504 COPY_HARD_REG_SET (index
, reg_class_contents
[INDEX_REG_CLASS
]);
505 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
507 if (FUNCTION_ARG_REGNO_P (regno
))
509 CLEAR_HARD_REG_BIT (base
, regno
);
510 CLEAR_HARD_REG_BIT (index
, regno
);
514 GO_IF_HARD_REG_EQUAL (base
, reg_class_contents
[BASE_REG_CLASS
],
516 for (p
= reg_class_subclasses
[BASE_REG_CLASS
];
517 *p
!= LIM_REG_CLASSES
;
520 GO_IF_HARD_REG_EQUAL (base
, reg_class_contents
[*p
], usebase
);
523 reload_address_base_reg_class
= *p
;
528 GO_IF_HARD_REG_EQUAL (index
, reg_class_contents
[INDEX_REG_CLASS
],
530 for (p
= reg_class_subclasses
[INDEX_REG_CLASS
];
531 *p
!= LIM_REG_CLASSES
;
534 GO_IF_HARD_REG_EQUAL (index
, reg_class_contents
[*p
], useindex
);
537 reload_address_index_reg_class
= *p
;
544 /* List of insn chains that are currently unused. */
545 static struct insn_chain
*unused_insn_chains
= 0;
547 /* Allocate an empty insn_chain structure. */
551 struct insn_chain
*c
;
553 if (unused_insn_chains
== 0)
555 c
= obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
556 c
->live_before
= OBSTACK_ALLOC_REG_SET (&reload_obstack
);
557 c
->live_after
= OBSTACK_ALLOC_REG_SET (&reload_obstack
);
561 c
= unused_insn_chains
;
562 unused_insn_chains
= c
->next
;
564 c
->is_caller_save_insn
= 0;
570 /* Small utility function to set all regs in hard reg set TO which are
571 allocated to pseudos in regset FROM. */
573 compute_use_by_pseudos (to
, from
)
578 EXECUTE_IF_SET_IN_REG_SET
579 (from
, FIRST_PSEUDO_REGISTER
, regno
,
581 int r
= reg_renumber
[regno
];
585 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
587 SET_HARD_REG_BIT (*to
, r
+ nregs
);
591 /* Global variables used by reload and its subroutines. */
593 /* Set during calculate_needs if an insn needs register elimination. */
594 static int something_needs_elimination
;
595 /* Set during calculate_needs if an insn needs an operand changed. */
596 int something_needs_operands_changed
;
598 /* For each class, number of reload regs needed in that class.
599 This is the maximum over all insns of the needs in that class
600 of the individual insn. */
601 static int max_needs
[N_REG_CLASSES
];
603 /* For each class, size of group of consecutive regs
604 that is needed for the reloads of this class. */
605 static int group_size
[N_REG_CLASSES
];
607 /* For each class, max number of consecutive groups needed.
608 (Each group contains group_size[CLASS] consecutive registers.) */
609 static int max_groups
[N_REG_CLASSES
];
611 /* For each class, max number needed of regs that don't belong
612 to any of the groups. */
613 static int max_nongroups
[N_REG_CLASSES
];
615 /* For each class, the machine mode which requires consecutive
616 groups of regs of that class.
617 If two different modes ever require groups of one class,
618 they must be the same size and equally restrictive for that class,
619 otherwise we can't handle the complexity. */
620 static enum machine_mode group_mode
[N_REG_CLASSES
];
622 /* Record the insn where each maximum need is first found. */
623 static rtx max_needs_insn
[N_REG_CLASSES
];
624 static rtx max_groups_insn
[N_REG_CLASSES
];
625 static rtx max_nongroups_insn
[N_REG_CLASSES
];
627 /* Nonzero means we couldn't get enough spill regs. */
630 /* Main entry point for the reload pass.
632 FIRST is the first insn of the function being compiled.
634 GLOBAL nonzero means we were called from global_alloc
635 and should attempt to reallocate any pseudoregs that we
636 displace from hard regs we will use for reloads.
637 If GLOBAL is zero, we do not have enough information to do that,
638 so any pseudo reg that is spilled must go to the stack.
640 DUMPFILE is the global-reg debugging dump file stream, or 0.
641 If it is nonzero, messages are written to it to describe
642 which registers are seized as reload regs, which pseudo regs
643 are spilled from them, and where the pseudo regs are reallocated to.
645 Return value is nonzero if reload failed
646 and we must not do any more for this function. */
649 reload (first
, global
, dumpfile
)
656 register struct elim_table
*ep
;
658 /* The two pointers used to track the true location of the memory used
659 for label offsets. */
660 char *real_known_ptr
= NULL_PTR
;
661 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
663 int something_changed
;
665 /* Make sure even insns with volatile mem refs are recognizable. */
670 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
672 /* Make sure that the last insn in the chain
673 is not something that needs reloading. */
674 emit_note (NULL_PTR
, NOTE_INSN_DELETED
);
676 /* Enable find_equiv_reg to distinguish insns made by reload. */
677 reload_first_uid
= get_max_uid ();
679 for (i
= 0; i
< N_REG_CLASSES
; i
++)
680 basic_block_needs
[i
] = 0;
682 #ifdef SECONDARY_MEMORY_NEEDED
683 /* Initialize the secondary memory table. */
684 clear_secondary_mem ();
687 /* Remember which hard regs appear explicitly
688 before we merge into `regs_ever_live' the ones in which
689 pseudo regs have been allocated. */
690 bcopy (regs_ever_live
, regs_explicitly_used
, sizeof regs_ever_live
);
692 /* We don't have a stack slot for any spill reg yet. */
693 bzero ((char *) spill_stack_slot
, sizeof spill_stack_slot
);
694 bzero ((char *) spill_stack_slot_width
, sizeof spill_stack_slot_width
);
696 /* Initialize the save area information for caller-save, in case some
700 /* Compute which hard registers are now in use
701 as homes for pseudo registers.
702 This is done here rather than (eg) in global_alloc
703 because this point is reached even if not optimizing. */
704 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
707 /* A function that receives a nonlocal goto must save all call-saved
709 if (current_function_has_nonlocal_label
)
710 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
712 if (! call_used_regs
[i
] && ! fixed_regs
[i
])
713 regs_ever_live
[i
] = 1;
716 /* Find all the pseudo registers that didn't get hard regs
717 but do have known equivalent constants or memory slots.
718 These include parameters (known equivalent to parameter slots)
719 and cse'd or loop-moved constant memory addresses.
721 Record constant equivalents in reg_equiv_constant
722 so they will be substituted by find_reloads.
723 Record memory equivalents in reg_mem_equiv so they can
724 be substituted eventually by altering the REG-rtx's. */
726 reg_equiv_constant
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
727 bzero ((char *) reg_equiv_constant
, max_regno
* sizeof (rtx
));
728 reg_equiv_memory_loc
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
729 bzero ((char *) reg_equiv_memory_loc
, max_regno
* sizeof (rtx
));
730 reg_equiv_mem
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
731 bzero ((char *) reg_equiv_mem
, max_regno
* sizeof (rtx
));
732 reg_equiv_init
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
733 bzero ((char *) reg_equiv_init
, max_regno
* sizeof (rtx
));
734 reg_equiv_address
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
735 bzero ((char *) reg_equiv_address
, max_regno
* sizeof (rtx
));
736 reg_max_ref_width
= (int *) xmalloc (max_regno
* sizeof (int));
737 bzero ((char *) reg_max_ref_width
, max_regno
* sizeof (int));
739 if (SMALL_REGISTER_CLASSES
)
740 CLEAR_HARD_REG_SET (forbidden_regs
);
742 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
743 Also find all paradoxical subregs and find largest such for each pseudo.
744 On machines with small register classes, record hard registers that
745 are used for user variables. These can never be used for spills.
746 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
747 caller-saved registers must be marked live. */
749 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
751 rtx set
= single_set (insn
);
753 if (GET_CODE (insn
) == NOTE
&& CONST_CALL_P (insn
)
754 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
755 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
756 if (! call_used_regs
[i
])
757 regs_ever_live
[i
] = 1;
759 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
761 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
763 #ifdef LEGITIMATE_PIC_OPERAND_P
764 && (! CONSTANT_P (XEXP (note
, 0)) || ! flag_pic
765 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
769 rtx x
= XEXP (note
, 0);
770 i
= REGNO (SET_DEST (set
));
771 if (i
> LAST_VIRTUAL_REGISTER
)
773 if (GET_CODE (x
) == MEM
)
775 /* If the operand is a PLUS, the MEM may be shared,
776 so make sure we have an unshared copy here. */
777 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
780 reg_equiv_memory_loc
[i
] = x
;
782 else if (CONSTANT_P (x
))
784 if (LEGITIMATE_CONSTANT_P (x
))
785 reg_equiv_constant
[i
] = x
;
787 reg_equiv_memory_loc
[i
]
788 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
793 /* If this register is being made equivalent to a MEM
794 and the MEM is not SET_SRC, the equivalencing insn
795 is one with the MEM as a SET_DEST and it occurs later.
796 So don't mark this insn now. */
797 if (GET_CODE (x
) != MEM
798 || rtx_equal_p (SET_SRC (set
), x
))
799 reg_equiv_init
[i
] = insn
;
804 /* If this insn is setting a MEM from a register equivalent to it,
805 this is the equivalencing insn. */
806 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
807 && GET_CODE (SET_SRC (set
)) == REG
808 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
809 && rtx_equal_p (SET_DEST (set
),
810 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
811 reg_equiv_init
[REGNO (SET_SRC (set
))] = insn
;
813 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
814 scan_paradoxical_subregs (PATTERN (insn
));
819 num_labels
= max_label_num () - get_first_label_num ();
821 /* Allocate the tables used to store offset information at labels. */
822 /* We used to use alloca here, but the size of what it would try to
823 allocate would occasionally cause it to exceed the stack limit and
824 cause a core dump. */
825 real_known_ptr
= xmalloc (num_labels
);
827 = (int (*)[NUM_ELIMINABLE_REGS
])
828 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
830 offsets_known_at
= real_known_ptr
- get_first_label_num ();
832 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
834 /* Alter each pseudo-reg rtx to contain its hard reg number.
835 Assign stack slots to the pseudos that lack hard regs or equivalents.
836 Do not touch virtual registers. */
838 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
841 /* If we have some registers we think can be eliminated, scan all insns to
842 see if there is an insn that sets one of these registers to something
843 other than itself plus a constant. If so, the register cannot be
844 eliminated. Doing this scan here eliminates an extra pass through the
845 main reload loop in the most common case where register elimination
847 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
848 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
849 || GET_CODE (insn
) == CALL_INSN
)
850 note_stores (PATTERN (insn
), mark_not_eliminable
);
852 #ifndef REGISTER_CONSTRAINTS
853 /* If all the pseudo regs have hard regs,
854 except for those that are never referenced,
855 we know that no reloads are needed. */
856 /* But that is not true if there are register constraints, since
857 in that case some pseudos might be in the wrong kind of hard reg. */
859 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
860 if (reg_renumber
[i
] == -1 && REG_N_REFS (i
) != 0)
863 if (i
== max_regno
&& num_eliminable
== 0 && ! caller_save_needed
)
865 free (real_known_ptr
);
867 free (reg_equiv_constant
);
868 free (reg_equiv_memory_loc
);
869 free (reg_equiv_mem
);
870 free (reg_equiv_init
);
871 free (reg_equiv_address
);
872 free (reg_max_ref_width
);
877 /* Compute the order of preference for hard registers to spill.
878 Store them by decreasing preference in potential_reload_regs. */
880 order_regs_for_reload ();
882 maybe_fix_stack_asms ();
884 /* So far, no hard regs have been spilled. */
886 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
887 spill_reg_order
[i
] = -1;
889 /* Initialize to -1, which means take the first spill register. */
892 /* On most machines, we can't use any register explicitly used in the
893 rtl as a spill register. But on some, we have to. Those will have
894 taken care to keep the life of hard regs as short as possible. */
896 if (! SMALL_REGISTER_CLASSES
)
897 COPY_HARD_REG_SET (forbidden_regs
, bad_spill_regs
);
899 spilled_pseudos
= ALLOCA_REG_SET ();
901 /* Spill any hard regs that we know we can't eliminate. */
902 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
903 if (! ep
->can_eliminate
)
904 spill_hard_reg (ep
->from
, global
, dumpfile
, 1);
906 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
907 if (frame_pointer_needed
)
908 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, global
, dumpfile
, 1);
911 finish_spills (global
, dumpfile
);
914 for (i
= 0; i
< N_REG_CLASSES
; i
++)
916 basic_block_needs
[i
] = (char *) alloca (n_basic_blocks
);
917 bzero (basic_block_needs
[i
], n_basic_blocks
);
920 /* From now on, we need to emit any moves without making new pseudos. */
921 reload_in_progress
= 1;
923 /* This loop scans the entire function each go-round
924 and repeats until one repetition spills no additional hard regs. */
926 /* This flag is set when a pseudo reg is spilled,
927 to require another pass. Note that getting an additional reload
928 reg does not necessarily imply any pseudo reg was spilled;
929 sometimes we find a reload reg that no pseudo reg was allocated in. */
930 something_changed
= 1;
932 /* This flag is set if there are any insns that require register
934 something_needs_elimination
= 0;
935 something_needs_operands_changed
= 0;
936 while (something_changed
)
938 HOST_WIDE_INT starting_frame_size
;
940 something_changed
= 0;
941 bzero ((char *) max_needs
, sizeof max_needs
);
942 bzero ((char *) max_groups
, sizeof max_groups
);
943 bzero ((char *) max_nongroups
, sizeof max_nongroups
);
944 bzero ((char *) max_needs_insn
, sizeof max_needs_insn
);
945 bzero ((char *) max_groups_insn
, sizeof max_groups_insn
);
946 bzero ((char *) max_nongroups_insn
, sizeof max_nongroups_insn
);
947 bzero ((char *) group_size
, sizeof group_size
);
948 for (i
= 0; i
< N_REG_CLASSES
; i
++)
949 group_mode
[i
] = VOIDmode
;
951 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
952 here because the stack size may be a part of the offset computation
953 for register elimination, and there might have been new stack slots
954 created in the last iteration of this loop. */
955 assign_stack_local (BLKmode
, 0, 0);
957 starting_frame_size
= get_frame_size ();
959 set_initial_elim_offsets ();
961 /* For each pseudo register that has an equivalent location defined,
962 try to eliminate any eliminable registers (such as the frame pointer)
963 assuming initial offsets for the replacement register, which
966 If the resulting location is directly addressable, substitute
967 the MEM we just got directly for the old REG.
969 If it is not addressable but is a constant or the sum of a hard reg
970 and constant, it is probably not addressable because the constant is
971 out of range, in that case record the address; we will generate
972 hairy code to compute the address in a register each time it is
973 needed. Similarly if it is a hard register, but one that is not
974 valid as an address register.
976 If the location is not addressable, but does not have one of the
977 above forms, assign a stack slot. We have to do this to avoid the
978 potential of producing lots of reloads if, e.g., a location involves
979 a pseudo that didn't get a hard register and has an equivalent memory
980 location that also involves a pseudo that didn't get a hard register.
982 Perhaps at some point we will improve reload_when_needed handling
983 so this problem goes away. But that's very hairy. */
985 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
986 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
988 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
990 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
992 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
993 else if (CONSTANT_P (XEXP (x
, 0))
994 || (GET_CODE (XEXP (x
, 0)) == REG
995 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
996 || (GET_CODE (XEXP (x
, 0)) == PLUS
997 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
998 && (REGNO (XEXP (XEXP (x
, 0), 0))
999 < FIRST_PSEUDO_REGISTER
)
1000 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
1001 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
1004 /* Make a new stack slot. Then indicate that something
1005 changed so we go back and recompute offsets for
1006 eliminable registers because the allocation of memory
1007 below might change some offset. reg_equiv_{mem,address}
1008 will be set up for this pseudo on the next pass around
1010 reg_equiv_memory_loc
[i
] = 0;
1011 reg_equiv_init
[i
] = 0;
1013 something_changed
= 1;
1017 /* Insert code to save and restore call-clobbered hard regs
1018 around calls. Tell if what mode to use so that we will process
1019 those insns in reload_as_needed if we have to. */
1021 if (caller_save_needed
)
1022 setup_save_areas ();
1024 if (starting_frame_size
!= get_frame_size ())
1025 something_changed
= 1;
1027 /* If we allocated another pseudo to the stack, redo elimination
1029 if (something_changed
)
1032 if (caller_save_needed
)
1034 save_call_clobbered_regs ();
1035 /* That might have allocated new insn_chain structures. */
1036 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
1039 something_changed
|= calculate_needs_all_insns (global
);
1041 /* If we allocated any new memory locations, make another pass
1042 since it might have changed elimination offsets. */
1043 if (starting_frame_size
!= get_frame_size ())
1044 something_changed
= 1;
1047 dump_needs (dumpfile
);
1050 HARD_REG_SET to_spill
;
1051 CLEAR_HARD_REG_SET (to_spill
);
1052 update_eliminables (&to_spill
);
1053 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1054 if (TEST_HARD_REG_BIT (to_spill
, i
))
1056 spill_hard_reg (i
, global
, dumpfile
, 1);
1057 something_changed
= 1;
1061 finish_spills (global
, dumpfile
);
1063 /* If all needs are met, we win. */
1065 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1066 if (max_needs
[i
] > 0 || max_groups
[i
] > 0 || max_nongroups
[i
] > 0)
1068 if (i
== N_REG_CLASSES
&& ! something_changed
)
1071 /* Not all needs are met; must spill some hard regs. */
1073 /* Put all registers spilled so far back in potential_reload_regs, but
1074 put them at the front, since we've already spilled most of the
1075 pseudos in them (we might have left some pseudos unspilled if they
1076 were in a block that didn't need any spill registers of a conflicting
1077 class. We used to try to mark off the need for those registers,
1078 but doing so properly is very complex and reallocating them is the
1079 simpler approach. First, "pack" potential_reload_regs by pushing
1080 any nonnegative entries towards the end. That will leave room
1081 for the registers we already spilled.
1083 Also, undo the marking of the spill registers from the last time
1084 around in FORBIDDEN_REGS since we will be probably be allocating
1087 ??? It is theoretically possible that we might end up not using one
1088 of our previously-spilled registers in this allocation, even though
1089 they are at the head of the list. It's not clear what to do about
1090 this, but it was no better before, when we marked off the needs met
1091 by the previously-spilled registers. With the current code, globals
1092 can be allocated into these registers, but locals cannot. */
1096 for (i
= j
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1097 if (potential_reload_regs
[i
] != -1)
1098 potential_reload_regs
[j
--] = potential_reload_regs
[i
];
1100 for (i
= 0; i
< n_spills
; i
++)
1102 potential_reload_regs
[i
] = spill_regs
[i
];
1103 spill_reg_order
[spill_regs
[i
]] = -1;
1104 CLEAR_HARD_REG_BIT (forbidden_regs
, spill_regs
[i
]);
1110 something_changed
|= find_reload_regs (global
, dumpfile
);
1114 finish_spills (global
, dumpfile
);
1116 if (something_changed
)
1117 delete_caller_save_insns ();
1120 /* If global-alloc was run, notify it of any register eliminations we have
1123 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1124 if (ep
->can_eliminate
)
1125 mark_elimination (ep
->from
, ep
->to
);
1127 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1128 If that insn didn't set the register (i.e., it copied the register to
1129 memory), just delete that insn instead of the equivalencing insn plus
1130 anything now dead. If we call delete_dead_insn on that insn, we may
1131 delete the insn that actually sets the register if the register die
1132 there and that is incorrect. */
1134 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1135 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0
1136 && GET_CODE (reg_equiv_init
[i
]) != NOTE
)
1138 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (reg_equiv_init
[i
])))
1139 delete_dead_insn (reg_equiv_init
[i
]);
1142 PUT_CODE (reg_equiv_init
[i
], NOTE
);
1143 NOTE_SOURCE_FILE (reg_equiv_init
[i
]) = 0;
1144 NOTE_LINE_NUMBER (reg_equiv_init
[i
]) = NOTE_INSN_DELETED
;
1148 /* Use the reload registers where necessary
1149 by generating move instructions to move the must-be-register
1150 values into or out of the reload registers. */
1152 if (insns_need_reload
!= 0 || something_needs_elimination
)
1153 reload_as_needed (global
);
1155 /* If we were able to eliminate the frame pointer, show that it is no
1156 longer live at the start of any basic block. If it ls live by
1157 virtue of being in a pseudo, that pseudo will be marked live
1158 and hence the frame pointer will be known to be live via that
1161 if (! frame_pointer_needed
)
1162 for (i
= 0; i
< n_basic_blocks
; i
++)
1163 CLEAR_REGNO_REG_SET (basic_block_live_at_start
[i
],
1164 HARD_FRAME_POINTER_REGNUM
);
1166 /* Come here (with failure set nonzero) if we can't get enough spill regs
1167 and we decide not to abort about it. */
1170 reload_in_progress
= 0;
1172 /* Now eliminate all pseudo regs by modifying them into
1173 their equivalent memory references.
1174 The REG-rtx's for the pseudos are modified in place,
1175 so all insns that used to refer to them now refer to memory.
1177 For a reg that has a reg_equiv_address, all those insns
1178 were changed by reloading so that no insns refer to it any longer;
1179 but the DECL_RTL of a variable decl may refer to it,
1180 and if so this causes the debugging info to mention the variable. */
1182 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1186 int is_readonly
= 0;
1188 if (reg_equiv_memory_loc
[i
])
1190 in_struct
= MEM_IN_STRUCT_P (reg_equiv_memory_loc
[i
]);
1191 is_readonly
= RTX_UNCHANGING_P (reg_equiv_memory_loc
[i
]);
1194 if (reg_equiv_mem
[i
])
1195 addr
= XEXP (reg_equiv_mem
[i
], 0);
1197 if (reg_equiv_address
[i
])
1198 addr
= reg_equiv_address
[i
];
1202 if (reg_renumber
[i
] < 0)
1204 rtx reg
= regno_reg_rtx
[i
];
1205 XEXP (reg
, 0) = addr
;
1206 REG_USERVAR_P (reg
) = 0;
1207 RTX_UNCHANGING_P (reg
) = is_readonly
;
1208 MEM_IN_STRUCT_P (reg
) = in_struct
;
1209 /* We have no alias information about this newly created
1211 MEM_ALIAS_SET (reg
) = 0;
1212 PUT_CODE (reg
, MEM
);
1214 else if (reg_equiv_mem
[i
])
1215 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1219 /* Make a pass over all the insns and delete all USEs which we inserted
1220 only to tag a REG_EQUAL note on them. Also remove all REG_DEAD and
1221 REG_UNUSED notes. */
1223 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1224 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1228 if (GET_CODE (PATTERN (insn
)) == USE
1229 && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1231 PUT_CODE (insn
, NOTE
);
1232 NOTE_SOURCE_FILE (insn
) = 0;
1233 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1237 pnote
= ®_NOTES (insn
);
1240 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1241 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
)
1242 *pnote
= XEXP (*pnote
, 1);
1244 pnote
= &XEXP (*pnote
, 1);
1248 /* If we are doing stack checking, give a warning if this function's
1249 frame size is larger than we expect. */
1250 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1252 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1254 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1255 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1256 size
+= UNITS_PER_WORD
;
1258 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1259 warning ("frame size too large for reliable stack checking");
1262 /* Indicate that we no longer have known memory locations or constants. */
1263 if (reg_equiv_constant
)
1264 free (reg_equiv_constant
);
1265 reg_equiv_constant
= 0;
1266 if (reg_equiv_memory_loc
)
1267 free (reg_equiv_memory_loc
);
1268 reg_equiv_memory_loc
= 0;
1271 free (real_known_ptr
);
1275 free (reg_equiv_mem
);
1276 free (reg_equiv_init
);
1277 free (reg_equiv_address
);
1278 free (reg_max_ref_width
);
1280 FREE_REG_SET (spilled_pseudos
);
1282 CLEAR_HARD_REG_SET (used_spill_regs
);
1283 for (i
= 0; i
< n_spills
; i
++)
1284 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1286 /* Free all the insn_chain structures at once. */
1287 obstack_free (&reload_obstack
, reload_startobj
);
1288 unused_insn_chains
= 0;
1293 /* Yet another special case. Unfortunately, reg-stack forces people to
1294 write incorrect clobbers in asm statements. These clobbers must not
1295 cause the register to appear in bad_spill_regs, otherwise we'll call
1296 fatal_insn later. We clear the corresponding regnos in the live
1297 register sets to avoid this.
1298 The whole thing is rather sick, I'm afraid. */
1300 maybe_fix_stack_asms ()
1303 char *constraints
[MAX_RECOG_OPERANDS
];
1304 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1305 struct insn_chain
*chain
;
1307 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1310 HARD_REG_SET clobbered
, allowed
;
1313 if (GET_RTX_CLASS (GET_CODE (chain
->insn
)) != 'i'
1314 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1316 pat
= PATTERN (chain
->insn
);
1317 if (GET_CODE (pat
) != PARALLEL
)
1320 CLEAR_HARD_REG_SET (clobbered
);
1321 CLEAR_HARD_REG_SET (allowed
);
1323 /* First, make a mask of all stack regs that are clobbered. */
1324 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1326 rtx t
= XVECEXP (pat
, 0, i
);
1327 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1328 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1331 /* Get the operand values and constraints out of the insn. */
1332 decode_asm_operands (pat
, recog_operand
, recog_operand_loc
,
1333 constraints
, operand_mode
);
1335 /* For every operand, see what registers are allowed. */
1336 for (i
= 0; i
< noperands
; i
++)
1338 char *p
= constraints
[i
];
1339 /* For every alternative, we compute the class of registers allowed
1340 for reloading in CLS, and merge its contents into the reg set
1342 int cls
= (int) NO_REGS
;
1348 if (c
== '\0' || c
== ',' || c
== '#')
1350 /* End of one alternative - mark the regs in the current
1351 class, and reset the class. */
1352 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1357 } while (c
!= '\0' && c
!= ',');
1365 case '=': case '+': case '*': case '%': case '?': case '!':
1366 case '0': case '1': case '2': case '3': case '4': case 'm':
1367 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1368 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1369 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1371 #ifdef EXTRA_CONSTRAINT
1372 case 'Q': case 'R': case 'S': case 'T': case 'U':
1377 cls
= (int) reg_class_subunion
[cls
][(int) BASE_REG_CLASS
];
1382 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1386 cls
= (int) reg_class_subunion
[cls
][(int) REG_CLASS_FROM_LETTER (c
)];
1391 /* Those of the registers which are clobbered, but allowed by the
1392 constraints, must be usable as reload registers. So clear them
1393 out of the life information. */
1394 AND_HARD_REG_SET (allowed
, clobbered
);
1395 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1396 if (TEST_HARD_REG_BIT (allowed
, i
))
1398 CLEAR_REGNO_REG_SET (chain
->live_before
, i
);
1399 CLEAR_REGNO_REG_SET (chain
->live_after
, i
);
1406 /* Walk the insns of the current function, starting with FIRST, and collect
1407 information about the need to do register elimination and the need to
1410 calculate_needs_all_insns (global
)
1413 int something_changed
= 0;
1415 int after_call_nregs
;
1416 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1417 struct insn_chain
*chain
;
1419 /* Compute the most additional registers needed by any instruction.
1420 Collect information separately for each class of regs. */
1422 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
1424 rtx insn
= chain
->insn
;
1426 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
1427 might include REG_LABEL), we need to see what effects this
1428 has on the known offsets at labels. */
1430 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1431 || (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1432 && REG_NOTES (insn
) != 0))
1433 set_label_offsets (insn
, insn
, 0);
1435 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1437 rtx old_body
= PATTERN (insn
);
1438 int old_code
= INSN_CODE (insn
);
1439 rtx old_notes
= REG_NOTES (insn
);
1440 int did_elimination
= 0;
1441 int operands_changed
= 0;
1443 /* Nonzero means don't use a reload reg that overlaps
1444 the place where a function value can be returned. */
1445 rtx avoid_return_reg
= 0;
1447 /* Set avoid_return_reg if this is an insn
1448 that might use the value of a function call. */
1449 if (SMALL_REGISTER_CLASSES
&& GET_CODE (insn
) == CALL_INSN
)
1451 if (GET_CODE (PATTERN (insn
)) == SET
)
1453 after_call
= SET_DEST (PATTERN (insn
));
1454 after_call_nregs
= HARD_REGNO_NREGS (REGNO (after_call
),
1455 GET_MODE (after_call
));
1457 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1458 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1460 after_call
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
1461 after_call_nregs
= HARD_REGNO_NREGS (REGNO (after_call
),
1462 GET_MODE (after_call
));
1467 else if (SMALL_REGISTER_CLASSES
&& after_call
!= 0
1468 && !(GET_CODE (PATTERN (insn
)) == SET
1469 && SET_DEST (PATTERN (insn
)) == stack_pointer_rtx
)
1470 && GET_CODE (PATTERN (insn
)) != CLOBBER
1471 && GET_CODE (PATTERN (insn
)) != USE
)
1473 if (reg_referenced_p (after_call
, PATTERN (insn
)))
1475 avoid_return_reg
= after_call
;
1476 if (! --after_call_nregs
)
1480 /* If INSN copies the return register in a single chunk,
1481 clear after_call now. */
1482 rtx set
= single_set (insn
);
1483 if (set
&& (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
1484 == GET_MODE_SIZE (GET_MODE (after_call
))))
1492 /* If needed, eliminate any eliminable registers. */
1494 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1496 /* Analyze the instruction. */
1497 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1498 global
, spill_reg_order
);
1500 /* If a no-op set needs more than one reload, this is likely
1501 to be something that needs input address reloads. We
1502 can't get rid of this cleanly later, and it is of no use
1503 anyway, so discard it now.
1504 We only do this when expensive_optimizations is enabled,
1505 since this complements reload inheritance / output
1506 reload deletion, and it can make debugging harder. */
1507 if (flag_expensive_optimizations
&& n_reloads
> 1)
1509 rtx set
= single_set (insn
);
1511 && SET_SRC (set
) == SET_DEST (set
)
1512 && GET_CODE (SET_SRC (set
)) == REG
1513 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1515 PUT_CODE (insn
, NOTE
);
1516 NOTE_SOURCE_FILE (insn
) = 0;
1517 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1522 update_eliminable_offsets ();
1524 /* Remember for later shortcuts which insns had any reloads or
1525 register eliminations. */
1526 chain
->need_elim
= did_elimination
;
1527 chain
->need_reload
= (n_reloads
> 0 | operands_changed
);
1529 /* Discard any register replacements done. */
1530 if (did_elimination
)
1532 obstack_free (&reload_obstack
, reload_firstobj
);
1533 PATTERN (insn
) = old_body
;
1534 INSN_CODE (insn
) = old_code
;
1535 REG_NOTES (insn
) = old_notes
;
1536 something_needs_elimination
= 1;
1539 something_needs_operands_changed
|= operands_changed
;
1543 *pprev_reload
= chain
;
1544 pprev_reload
= &chain
->next_need_reload
;
1545 something_changed
|= calculate_needs (chain
, avoid_return_reg
,
1551 return something_changed
;
1554 /* To compute the number of reload registers of each class
1555 needed for an insn, we must simulate what choose_reload_regs
1556 can do. We do this by splitting an insn into an "input" and
1557 an "output" part. RELOAD_OTHER reloads are used in both.
1558 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
1559 which must be live over the entire input section of reloads,
1560 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1561 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
1564 The registers needed for output are RELOAD_OTHER and
1565 RELOAD_FOR_OUTPUT, which are live for the entire output
1566 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
1567 reloads for each operand.
1569 The total number of registers needed is the maximum of the
1570 inputs and outputs. */
1573 calculate_needs (chain
, avoid_return_reg
, global
)
1574 struct insn_chain
*chain
;
1575 rtx avoid_return_reg
;
1578 rtx insn
= chain
->insn
;
1579 int something_changed
= 0;
1582 /* Each `struct needs' corresponds to one RELOAD_... type. */
1586 struct needs output
;
1588 struct needs other_addr
;
1589 struct needs op_addr
;
1590 struct needs op_addr_reload
;
1591 struct needs in_addr
[MAX_RECOG_OPERANDS
];
1592 struct needs in_addr_addr
[MAX_RECOG_OPERANDS
];
1593 struct needs out_addr
[MAX_RECOG_OPERANDS
];
1594 struct needs out_addr_addr
[MAX_RECOG_OPERANDS
];
1597 bzero ((char *) &insn_needs
, sizeof insn_needs
);
1599 /* Count each reload once in every class
1600 containing the reload's own class. */
1602 for (i
= 0; i
< n_reloads
; i
++)
1604 register enum reg_class
*p
;
1605 enum reg_class
class = reload_reg_class
[i
];
1607 enum machine_mode mode
;
1608 struct needs
*this_needs
;
1610 /* Don't count the dummy reloads, for which one of the
1611 regs mentioned in the insn can be used for reloading.
1612 Don't count optional reloads.
1613 Don't count reloads that got combined with others. */
1614 if (reload_reg_rtx
[i
] != 0
1615 || reload_optional
[i
] != 0
1616 || (reload_out
[i
] == 0 && reload_in
[i
] == 0
1617 && ! reload_secondary_p
[i
]))
1620 /* Show that a reload register of this class is needed
1621 in this basic block. We do not use insn_needs and
1622 insn_groups because they are overly conservative for
1624 if (global
&& ! basic_block_needs
[(int) class][chain
->block
])
1626 basic_block_needs
[(int) class][chain
->block
] = 1;
1627 something_changed
= 1;
1630 mode
= reload_inmode
[i
];
1631 if (GET_MODE_SIZE (reload_outmode
[i
]) > GET_MODE_SIZE (mode
))
1632 mode
= reload_outmode
[i
];
1633 size
= CLASS_MAX_NREGS (class, mode
);
1635 /* Decide which time-of-use to count this reload for. */
1636 switch (reload_when_needed
[i
])
1639 this_needs
= &insn_needs
.other
;
1641 case RELOAD_FOR_INPUT
:
1642 this_needs
= &insn_needs
.input
;
1644 case RELOAD_FOR_OUTPUT
:
1645 this_needs
= &insn_needs
.output
;
1647 case RELOAD_FOR_INSN
:
1648 this_needs
= &insn_needs
.insn
;
1650 case RELOAD_FOR_OTHER_ADDRESS
:
1651 this_needs
= &insn_needs
.other_addr
;
1653 case RELOAD_FOR_INPUT_ADDRESS
:
1654 this_needs
= &insn_needs
.in_addr
[reload_opnum
[i
]];
1656 case RELOAD_FOR_INPADDR_ADDRESS
:
1657 this_needs
= &insn_needs
.in_addr_addr
[reload_opnum
[i
]];
1659 case RELOAD_FOR_OUTPUT_ADDRESS
:
1660 this_needs
= &insn_needs
.out_addr
[reload_opnum
[i
]];
1662 case RELOAD_FOR_OUTADDR_ADDRESS
:
1663 this_needs
= &insn_needs
.out_addr_addr
[reload_opnum
[i
]];
1665 case RELOAD_FOR_OPERAND_ADDRESS
:
1666 this_needs
= &insn_needs
.op_addr
;
1668 case RELOAD_FOR_OPADDR_ADDR
:
1669 this_needs
= &insn_needs
.op_addr_reload
;
1675 enum machine_mode other_mode
, allocate_mode
;
1677 /* Count number of groups needed separately from
1678 number of individual regs needed. */
1679 this_needs
->groups
[(int) class]++;
1680 p
= reg_class_superclasses
[(int) class];
1681 while (*p
!= LIM_REG_CLASSES
)
1682 this_needs
->groups
[(int) *p
++]++;
1684 /* Record size and mode of a group of this class. */
1685 /* If more than one size group is needed,
1686 make all groups the largest needed size. */
1687 if (group_size
[(int) class] < size
)
1689 other_mode
= group_mode
[(int) class];
1690 allocate_mode
= mode
;
1692 group_size
[(int) class] = size
;
1693 group_mode
[(int) class] = mode
;
1698 allocate_mode
= group_mode
[(int) class];
1701 /* Crash if two dissimilar machine modes both need
1702 groups of consecutive regs of the same class. */
1704 if (other_mode
!= VOIDmode
&& other_mode
!= allocate_mode
1705 && ! modes_equiv_for_class_p (allocate_mode
,
1707 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1712 this_needs
->regs
[(unsigned char)reload_nongroup
[i
]][(int) class] += 1;
1713 p
= reg_class_superclasses
[(int) class];
1714 while (*p
!= LIM_REG_CLASSES
)
1715 this_needs
->regs
[(unsigned char)reload_nongroup
[i
]][(int) *p
++] += 1;
1721 /* All reloads have been counted for this insn;
1722 now merge the various times of use.
1723 This sets insn_needs, etc., to the maximum total number
1724 of registers needed at any point in this insn. */
1726 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1728 int j
, in_max
, out_max
;
1730 /* Compute normal and nongroup needs. */
1731 for (j
= 0; j
<= 1; j
++)
1734 for (in_max
= 0, out_max
= 0, k
= 0; k
< reload_n_operands
; k
++)
1736 in_max
= MAX (in_max
,
1737 (insn_needs
.in_addr
[k
].regs
[j
][i
]
1738 + insn_needs
.in_addr_addr
[k
].regs
[j
][i
]));
1739 out_max
= MAX (out_max
, insn_needs
.out_addr
[k
].regs
[j
][i
]);
1740 out_max
= MAX (out_max
,
1741 insn_needs
.out_addr_addr
[k
].regs
[j
][i
]);
1744 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1745 and operand addresses but not things used to reload
1746 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1747 don't conflict with things needed to reload inputs or
1750 in_max
= MAX (MAX (insn_needs
.op_addr
.regs
[j
][i
],
1751 insn_needs
.op_addr_reload
.regs
[j
][i
]),
1754 out_max
= MAX (out_max
, insn_needs
.insn
.regs
[j
][i
]);
1756 insn_needs
.input
.regs
[j
][i
]
1757 = MAX (insn_needs
.input
.regs
[j
][i
]
1758 + insn_needs
.op_addr
.regs
[j
][i
]
1759 + insn_needs
.insn
.regs
[j
][i
],
1760 in_max
+ insn_needs
.input
.regs
[j
][i
]);
1762 insn_needs
.output
.regs
[j
][i
] += out_max
;
1763 insn_needs
.other
.regs
[j
][i
]
1764 += MAX (MAX (insn_needs
.input
.regs
[j
][i
],
1765 insn_needs
.output
.regs
[j
][i
]),
1766 insn_needs
.other_addr
.regs
[j
][i
]);
1770 /* Now compute group needs. */
1771 for (in_max
= 0, out_max
= 0, j
= 0; j
< reload_n_operands
; j
++)
1773 in_max
= MAX (in_max
, insn_needs
.in_addr
[j
].groups
[i
]);
1774 in_max
= MAX (in_max
, insn_needs
.in_addr_addr
[j
].groups
[i
]);
1775 out_max
= MAX (out_max
, insn_needs
.out_addr
[j
].groups
[i
]);
1776 out_max
= MAX (out_max
, insn_needs
.out_addr_addr
[j
].groups
[i
]);
1779 in_max
= MAX (MAX (insn_needs
.op_addr
.groups
[i
],
1780 insn_needs
.op_addr_reload
.groups
[i
]),
1782 out_max
= MAX (out_max
, insn_needs
.insn
.groups
[i
]);
1784 insn_needs
.input
.groups
[i
]
1785 = MAX (insn_needs
.input
.groups
[i
]
1786 + insn_needs
.op_addr
.groups
[i
]
1787 + insn_needs
.insn
.groups
[i
],
1788 in_max
+ insn_needs
.input
.groups
[i
]);
1790 insn_needs
.output
.groups
[i
] += out_max
;
1791 insn_needs
.other
.groups
[i
]
1792 += MAX (MAX (insn_needs
.input
.groups
[i
],
1793 insn_needs
.output
.groups
[i
]),
1794 insn_needs
.other_addr
.groups
[i
]);
1797 /* If this insn stores the value of a function call,
1798 and that value is in a register that has been spilled,
1799 and if the insn needs a reload in a class
1800 that might use that register as the reload register,
1801 then add an extra need in that class.
1802 This makes sure we have a register available that does
1803 not overlap the return value. */
1805 if (SMALL_REGISTER_CLASSES
&& avoid_return_reg
)
1807 int regno
= REGNO (avoid_return_reg
);
1809 = HARD_REGNO_NREGS (regno
, GET_MODE (avoid_return_reg
));
1811 int basic_needs
[N_REG_CLASSES
], basic_groups
[N_REG_CLASSES
];
1813 /* First compute the "basic needs", which counts a
1814 need only in the smallest class in which it
1817 bcopy ((char *) insn_needs
.other
.regs
[0],
1818 (char *) basic_needs
, sizeof basic_needs
);
1819 bcopy ((char *) insn_needs
.other
.groups
,
1820 (char *) basic_groups
, sizeof basic_groups
);
1822 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1826 if (basic_needs
[i
] >= 0)
1827 for (p
= reg_class_superclasses
[i
];
1828 *p
!= LIM_REG_CLASSES
; p
++)
1829 basic_needs
[(int) *p
] -= basic_needs
[i
];
1831 if (basic_groups
[i
] >= 0)
1832 for (p
= reg_class_superclasses
[i
];
1833 *p
!= LIM_REG_CLASSES
; p
++)
1834 basic_groups
[(int) *p
] -= basic_groups
[i
];
1837 /* Now count extra regs if there might be a conflict with
1838 the return value register. */
1840 for (r
= regno
; r
< regno
+ nregs
; r
++)
1841 if (spill_reg_order
[r
] >= 0)
1842 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1843 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], r
))
1845 if (basic_needs
[i
] > 0)
1849 insn_needs
.other
.regs
[0][i
]++;
1850 p
= reg_class_superclasses
[i
];
1851 while (*p
!= LIM_REG_CLASSES
)
1852 insn_needs
.other
.regs
[0][(int) *p
++]++;
1854 if (basic_groups
[i
] > 0)
1858 insn_needs
.other
.groups
[i
]++;
1859 p
= reg_class_superclasses
[i
];
1860 while (*p
!= LIM_REG_CLASSES
)
1861 insn_needs
.other
.groups
[(int) *p
++]++;
1866 /* For each class, collect maximum need of any insn. */
1868 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1870 if (max_needs
[i
] < insn_needs
.other
.regs
[0][i
])
1872 max_needs
[i
] = insn_needs
.other
.regs
[0][i
];
1873 max_needs_insn
[i
] = insn
;
1875 if (max_groups
[i
] < insn_needs
.other
.groups
[i
])
1877 max_groups
[i
] = insn_needs
.other
.groups
[i
];
1878 max_groups_insn
[i
] = insn
;
1880 if (max_nongroups
[i
] < insn_needs
.other
.regs
[1][i
])
1882 max_nongroups
[i
] = insn_needs
.other
.regs
[1][i
];
1883 max_nongroups_insn
[i
] = insn
;
1887 /* Record the needs for later. */
1888 chain
->need
= insn_needs
.other
;
1890 return something_changed
;
1893 /* Find a group of exactly 2 registers.
1895 First try to fill out the group by spilling a single register which
1896 would allow completion of the group.
1898 Then try to create a new group from a pair of registers, neither of
1899 which are explicitly used.
1901 Then try to create a group from any pair of registers. */
1903 find_tworeg_group (global
, class, dumpfile
)
1909 /* First, look for a register that will complete a group. */
1910 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1914 j
= potential_reload_regs
[i
];
1915 if (j
>= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
)
1916 && ((j
> 0 && (other
= j
- 1, spill_reg_order
[other
] >= 0)
1917 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1918 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1919 && HARD_REGNO_MODE_OK (other
, group_mode
[class])
1920 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, other
)
1921 /* We don't want one part of another group.
1922 We could get "two groups" that overlap! */
1923 && ! TEST_HARD_REG_BIT (counted_for_groups
, other
))
1924 || (j
< FIRST_PSEUDO_REGISTER
- 1
1925 && (other
= j
+ 1, spill_reg_order
[other
] >= 0)
1926 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1927 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1928 && HARD_REGNO_MODE_OK (j
, group_mode
[class])
1929 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, other
)
1930 && ! TEST_HARD_REG_BIT (counted_for_groups
, other
))))
1932 register enum reg_class
*p
;
1934 /* We have found one that will complete a group,
1935 so count off one group as provided. */
1936 max_groups
[class]--;
1937 p
= reg_class_superclasses
[class];
1938 while (*p
!= LIM_REG_CLASSES
)
1940 if (group_size
[(int) *p
] <= group_size
[class])
1941 max_groups
[(int) *p
]--;
1945 /* Indicate both these regs are part of a group. */
1946 SET_HARD_REG_BIT (counted_for_groups
, j
);
1947 SET_HARD_REG_BIT (counted_for_groups
, other
);
1951 /* We can't complete a group, so start one. */
1952 /* Look for a pair neither of which is explicitly used. */
1953 if (SMALL_REGISTER_CLASSES
&& i
== FIRST_PSEUDO_REGISTER
)
1954 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1957 j
= potential_reload_regs
[i
];
1958 /* Verify that J+1 is a potential reload reg. */
1959 for (k
= 0; k
< FIRST_PSEUDO_REGISTER
; k
++)
1960 if (potential_reload_regs
[k
] == j
+ 1)
1962 if (j
>= 0 && j
+ 1 < FIRST_PSEUDO_REGISTER
1963 && k
< FIRST_PSEUDO_REGISTER
1964 && spill_reg_order
[j
] < 0 && spill_reg_order
[j
+ 1] < 0
1965 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1966 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ 1)
1967 && HARD_REGNO_MODE_OK (j
, group_mode
[class])
1968 && ! TEST_HARD_REG_BIT (counted_for_nongroups
,
1970 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ 1)
1971 /* Reject J at this stage
1972 if J+1 was explicitly used. */
1973 && ! regs_explicitly_used
[j
+ 1])
1976 /* Now try any group at all
1977 whose registers are not in bad_spill_regs. */
1978 if (i
== FIRST_PSEUDO_REGISTER
)
1979 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1982 j
= potential_reload_regs
[i
];
1983 /* Verify that J+1 is a potential reload reg. */
1984 for (k
= 0; k
< FIRST_PSEUDO_REGISTER
; k
++)
1985 if (potential_reload_regs
[k
] == j
+ 1)
1987 if (j
>= 0 && j
+ 1 < FIRST_PSEUDO_REGISTER
1988 && k
< FIRST_PSEUDO_REGISTER
1989 && spill_reg_order
[j
] < 0 && spill_reg_order
[j
+ 1] < 0
1990 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1991 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ 1)
1992 && HARD_REGNO_MODE_OK (j
, group_mode
[class])
1993 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, j
+ 1)
1994 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ 1))
1998 /* I should be the index in potential_reload_regs
1999 of the new reload reg we have found. */
2001 if (i
< FIRST_PSEUDO_REGISTER
)
2002 return new_spill_reg (i
, class, max_needs
, NULL_PTR
,
2005 /* There are no groups left to spill. */
2006 spill_failure (max_groups_insn
[class]);
2011 /* Find a group of more than 2 registers.
2012 Look for a sufficient sequence of unspilled registers, and spill them all
2015 find_group (global
, class, dumpfile
)
2020 int something_changed
= 0;
2023 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2027 j
= potential_reload_regs
[i
];
2029 && j
+ group_size
[class] <= FIRST_PSEUDO_REGISTER
2030 && HARD_REGNO_MODE_OK (j
, group_mode
[class]))
2032 /* Check each reg in the sequence. */
2033 for (k
= 0; k
< group_size
[class]; k
++)
2034 if (! (spill_reg_order
[j
+ k
] < 0
2035 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ k
)
2036 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ k
)))
2038 /* We got a full sequence, so spill them all. */
2039 if (k
== group_size
[class])
2041 register enum reg_class
*p
;
2042 for (k
= 0; k
< group_size
[class]; k
++)
2045 SET_HARD_REG_BIT (counted_for_groups
, j
+ k
);
2046 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
2047 if (potential_reload_regs
[idx
] == j
+ k
)
2049 something_changed
|= new_spill_reg (idx
, class, max_needs
,
2054 /* We have found one that will complete a group,
2055 so count off one group as provided. */
2056 max_groups
[class]--;
2057 p
= reg_class_superclasses
[class];
2058 while (*p
!= LIM_REG_CLASSES
)
2060 if (group_size
[(int) *p
]
2061 <= group_size
[class])
2062 max_groups
[(int) *p
]--;
2065 return something_changed
;
2069 /* There are no groups left. */
2070 spill_failure (max_groups_insn
[class]);
2075 /* Find more reload regs to satisfy the remaining need.
2076 Do it by ascending class number, since otherwise a reg
2077 might be spilled for a big class and might fail to count
2078 for a smaller class even though it belongs to that class.
2080 Count spilled regs in `spills', and add entries to
2081 `spill_regs' and `spill_reg_order'.
2083 ??? Note there is a problem here.
2084 When there is a need for a group in a high-numbered class,
2085 and also need for non-group regs that come from a lower class,
2086 the non-group regs are chosen first. If there aren't many regs,
2087 they might leave no room for a group.
2089 This was happening on the 386. To fix it, we added the code
2090 that calls possible_group_p, so that the lower class won't
2091 break up the last possible group.
2093 Really fixing the problem would require changes above
2094 in counting the regs already spilled, and in choose_reload_regs.
2095 It might be hard to avoid introducing bugs there. */
2098 find_reload_regs (global
, dumpfile
)
2103 int something_changed
= 0;
2105 CLEAR_HARD_REG_SET (counted_for_groups
);
2106 CLEAR_HARD_REG_SET (counted_for_nongroups
);
2108 for (class = 0; class < N_REG_CLASSES
; class++)
2110 /* First get the groups of registers.
2111 If we got single registers first, we might fragment
2113 while (max_groups
[class] > 0)
2115 /* If any single spilled regs happen to form groups,
2116 count them now. Maybe we don't really need
2117 to spill another group. */
2118 count_possible_groups (group_size
, group_mode
, max_groups
, class);
2120 if (max_groups
[class] <= 0)
2123 /* Groups of size 2 (the only groups used on most machines)
2124 are treated specially. */
2125 if (group_size
[class] == 2)
2126 something_changed
|= find_tworeg_group (global
, class, dumpfile
);
2128 something_changed
|= find_group (global
, class, dumpfile
);
2134 /* Now similarly satisfy all need for single registers. */
2136 while (max_needs
[class] > 0 || max_nongroups
[class] > 0)
2139 /* If we spilled enough regs, but they weren't counted
2140 against the non-group need, see if we can count them now.
2141 If so, we can avoid some actual spilling. */
2142 if (max_needs
[class] <= 0 && max_nongroups
[class] > 0)
2143 for (i
= 0; i
< n_spills
; i
++)
2145 int regno
= spill_regs
[i
];
2146 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
2147 && !TEST_HARD_REG_BIT (counted_for_groups
, regno
)
2148 && !TEST_HARD_REG_BIT (counted_for_nongroups
, regno
)
2149 && max_nongroups
[class] > 0)
2151 register enum reg_class
*p
;
2153 SET_HARD_REG_BIT (counted_for_nongroups
, regno
);
2154 max_nongroups
[class]--;
2155 p
= reg_class_superclasses
[class];
2156 while (*p
!= LIM_REG_CLASSES
)
2157 max_nongroups
[(int) *p
++]--;
2160 if (max_needs
[class] <= 0 && max_nongroups
[class] <= 0)
2163 /* Consider the potential reload regs that aren't
2164 yet in use as reload regs, in order of preference.
2165 Find the most preferred one that's in this class. */
2167 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2169 int regno
= potential_reload_regs
[i
];
2171 && TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
2172 /* If this reg will not be available for groups,
2173 pick one that does not foreclose possible groups.
2174 This is a kludge, and not very general,
2175 but it should be sufficient to make the 386 work,
2176 and the problem should not occur on machines with
2178 && (max_nongroups
[class] == 0
2179 || possible_group_p (regno
, max_groups
)))
2183 /* If we couldn't get a register, try to get one even if we
2184 might foreclose possible groups. This may cause problems
2185 later, but that's better than aborting now, since it is
2186 possible that we will, in fact, be able to form the needed
2187 group even with this allocation. */
2189 if (i
>= FIRST_PSEUDO_REGISTER
2190 && (asm_noperands (max_needs
[class] > 0
2191 ? max_needs_insn
[class]
2192 : max_nongroups_insn
[class])
2194 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2195 if (potential_reload_regs
[i
] >= 0
2196 && TEST_HARD_REG_BIT (reg_class_contents
[class],
2197 potential_reload_regs
[i
]))
2200 /* I should be the index in potential_reload_regs
2201 of the new reload reg we have found. */
2203 if (i
>= FIRST_PSEUDO_REGISTER
)
2205 /* There are no possible registers left to spill. */
2206 spill_failure (max_needs
[class] > 0 ? max_needs_insn
[class]
2207 : max_nongroups_insn
[class]);
2212 something_changed
|= new_spill_reg (i
, class, max_needs
,
2213 max_nongroups
, global
,
2217 return something_changed
;
2221 dump_needs (dumpfile
)
2224 static char *reg_class_names
[] = REG_CLASS_NAMES
;
2227 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2229 if (max_needs
[i
] > 0)
2231 ";; Need %d reg%s of class %s (for insn %d).\n",
2232 max_needs
[i
], max_needs
[i
] == 1 ? "" : "s",
2233 reg_class_names
[i
], INSN_UID (max_needs_insn
[i
]));
2234 if (max_nongroups
[i
] > 0)
2236 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
2237 max_nongroups
[i
], max_nongroups
[i
] == 1 ? "" : "s",
2238 reg_class_names
[i
], INSN_UID (max_nongroups_insn
[i
]));
2239 if (max_groups
[i
] > 0)
2241 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
2242 max_groups
[i
], max_groups
[i
] == 1 ? "" : "s",
2243 mode_name
[(int) group_mode
[i
]],
2244 reg_class_names
[i
], INSN_UID (max_groups_insn
[i
]));
2248 /* Delete all insns that were inserted by emit_caller_save_insns during
2251 delete_caller_save_insns ()
2253 struct insn_chain
*c
= reload_insn_chain
;
2257 while (c
!= 0 && c
->is_caller_save_insn
)
2259 struct insn_chain
*next
= c
->next
;
2262 if (insn
== basic_block_head
[c
->block
])
2263 basic_block_head
[c
->block
] = NEXT_INSN (insn
);
2264 if (insn
== basic_block_end
[c
->block
])
2265 basic_block_end
[c
->block
] = PREV_INSN (insn
);
2266 if (c
== reload_insn_chain
)
2267 reload_insn_chain
= next
;
2269 if (NEXT_INSN (insn
) != 0)
2270 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2271 if (PREV_INSN (insn
) != 0)
2272 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2275 next
->prev
= c
->prev
;
2277 c
->prev
->next
= next
;
2278 c
->next
= unused_insn_chains
;
2279 unused_insn_chains
= c
;
2287 /* Nonzero if, after spilling reg REGNO for non-groups,
2288 it will still be possible to find a group if we still need one. */
2291 possible_group_p (regno
, max_groups
)
2296 int class = (int) NO_REGS
;
2298 for (i
= 0; i
< (int) N_REG_CLASSES
; i
++)
2299 if (max_groups
[i
] > 0)
2305 if (class == (int) NO_REGS
)
2308 /* Consider each pair of consecutive registers. */
2309 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
- 1; i
++)
2311 /* Ignore pairs that include reg REGNO. */
2312 if (i
== regno
|| i
+ 1 == regno
)
2315 /* Ignore pairs that are outside the class that needs the group.
2316 ??? Here we fail to handle the case where two different classes
2317 independently need groups. But this never happens with our
2318 current machine descriptions. */
2319 if (! (TEST_HARD_REG_BIT (reg_class_contents
[class], i
)
2320 && TEST_HARD_REG_BIT (reg_class_contents
[class], i
+ 1)))
2323 /* A pair of consecutive regs we can still spill does the trick. */
2324 if (spill_reg_order
[i
] < 0 && spill_reg_order
[i
+ 1] < 0
2325 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2326 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1))
2329 /* A pair of one already spilled and one we can spill does it
2330 provided the one already spilled is not otherwise reserved. */
2331 if (spill_reg_order
[i
] < 0
2332 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2333 && spill_reg_order
[i
+ 1] >= 0
2334 && ! TEST_HARD_REG_BIT (counted_for_groups
, i
+ 1)
2335 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, i
+ 1))
2337 if (spill_reg_order
[i
+ 1] < 0
2338 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1)
2339 && spill_reg_order
[i
] >= 0
2340 && ! TEST_HARD_REG_BIT (counted_for_groups
, i
)
2341 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, i
))
2348 /* Count any groups of CLASS that can be formed from the registers recently
2352 count_possible_groups (group_size
, group_mode
, max_groups
, class)
2354 enum machine_mode
*group_mode
;
2361 /* Now find all consecutive groups of spilled registers
2362 and mark each group off against the need for such groups.
2363 But don't count them against ordinary need, yet. */
2365 if (group_size
[class] == 0)
2368 CLEAR_HARD_REG_SET (new);
2370 /* Make a mask of all the regs that are spill regs in class I. */
2371 for (i
= 0; i
< n_spills
; i
++)
2372 if (TEST_HARD_REG_BIT (reg_class_contents
[class], spill_regs
[i
])
2373 && ! TEST_HARD_REG_BIT (counted_for_groups
, spill_regs
[i
])
2374 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, spill_regs
[i
]))
2375 SET_HARD_REG_BIT (new, spill_regs
[i
]);
2377 /* Find each consecutive group of them. */
2378 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
&& max_groups
[class] > 0; i
++)
2379 if (TEST_HARD_REG_BIT (new, i
)
2380 && i
+ group_size
[class] <= FIRST_PSEUDO_REGISTER
2381 && HARD_REGNO_MODE_OK (i
, group_mode
[class]))
2383 for (j
= 1; j
< group_size
[class]; j
++)
2384 if (! TEST_HARD_REG_BIT (new, i
+ j
))
2387 if (j
== group_size
[class])
2389 /* We found a group. Mark it off against this class's need for
2390 groups, and against each superclass too. */
2391 register enum reg_class
*p
;
2393 max_groups
[class]--;
2394 p
= reg_class_superclasses
[class];
2395 while (*p
!= LIM_REG_CLASSES
)
2397 if (group_size
[(int) *p
] <= group_size
[class])
2398 max_groups
[(int) *p
]--;
2402 /* Don't count these registers again. */
2403 for (j
= 0; j
< group_size
[class]; j
++)
2404 SET_HARD_REG_BIT (counted_for_groups
, i
+ j
);
2407 /* Skip to the last reg in this group. When i is incremented above,
2408 it will then point to the first reg of the next possible group. */
2413 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2414 another mode that needs to be reloaded for the same register class CLASS.
2415 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2416 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2418 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2419 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2420 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2421 causes unnecessary failures on machines requiring alignment of register
2422 groups when the two modes are different sizes, because the larger mode has
2423 more strict alignment rules than the smaller mode. */
2426 modes_equiv_for_class_p (allocate_mode
, other_mode
, class)
2427 enum machine_mode allocate_mode
, other_mode
;
2428 enum reg_class
class;
2431 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2433 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
)
2434 && HARD_REGNO_MODE_OK (regno
, allocate_mode
)
2435 && ! HARD_REGNO_MODE_OK (regno
, other_mode
))
2441 /* Handle the failure to find a register to spill.
2442 INSN should be one of the insns which needed this particular spill reg. */
2445 spill_failure (insn
)
2448 if (asm_noperands (PATTERN (insn
)) >= 0)
2449 error_for_asm (insn
, "`asm' needs too many reloads");
2451 fatal_insn ("Unable to find a register to spill.", insn
);
2454 /* Add a new register to the tables of available spill-registers
2455 (as well as spilling all pseudos allocated to the register).
2456 I is the index of this register in potential_reload_regs.
2457 CLASS is the regclass whose need is being satisfied.
2458 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2459 so that this register can count off against them.
2460 MAX_NONGROUPS is 0 if this register is part of a group.
2461 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2464 new_spill_reg (i
, class, max_needs
, max_nongroups
, global
, dumpfile
)
2472 register enum reg_class
*p
;
2474 int regno
= potential_reload_regs
[i
];
2476 if (i
>= FIRST_PSEUDO_REGISTER
)
2477 abort (); /* Caller failed to find any register. */
2479 if (fixed_regs
[regno
] || TEST_HARD_REG_BIT (forbidden_regs
, regno
))
2481 static char *reg_class_names
[] = REG_CLASS_NAMES
;
2482 fatal ("fixed or forbidden register %d (%s) was spilled for class %s.\n\
2483 This may be due to a compiler bug or to impossible asm\n\
2484 statements or clauses.", regno
, reg_names
[regno
], reg_class_names
[class]);
2487 /* Make reg REGNO an additional reload reg. */
2489 potential_reload_regs
[i
] = -1;
2490 spill_regs
[n_spills
] = regno
;
2491 spill_reg_order
[regno
] = n_spills
;
2493 fprintf (dumpfile
, "Spilling reg %d.\n", spill_regs
[n_spills
]);
2495 /* Clear off the needs we just satisfied. */
2498 p
= reg_class_superclasses
[class];
2499 while (*p
!= LIM_REG_CLASSES
)
2500 max_needs
[(int) *p
++]--;
2502 if (max_nongroups
&& max_nongroups
[class] > 0)
2504 SET_HARD_REG_BIT (counted_for_nongroups
, regno
);
2505 max_nongroups
[class]--;
2506 p
= reg_class_superclasses
[class];
2507 while (*p
!= LIM_REG_CLASSES
)
2508 max_nongroups
[(int) *p
++]--;
2511 /* Spill every pseudo reg that was allocated to this reg
2512 or to something that overlaps this reg. */
2514 val
= spill_hard_reg (spill_regs
[n_spills
], global
, dumpfile
, 0);
2516 /* If there are some registers still to eliminate and this register
2517 wasn't ever used before, additional stack space may have to be
2518 allocated to store this register. Thus, we may have changed the offset
2519 between the stack and frame pointers, so mark that something has changed.
2520 (If new pseudos were spilled, thus requiring more space, VAL would have
2521 been set non-zero by the call to spill_hard_reg above since additional
2522 reloads may be needed in that case.
2524 One might think that we need only set VAL to 1 if this is a call-used
2525 register. However, the set of registers that must be saved by the
2526 prologue is not identical to the call-used set. For example, the
2527 register used by the call insn for the return PC is a call-used register,
2528 but must be saved by the prologue. */
2529 if (num_eliminable
&& ! regs_ever_live
[spill_regs
[n_spills
]])
2532 regs_ever_live
[spill_regs
[n_spills
]] = 1;
2538 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2539 data that is dead in INSN. */
2542 delete_dead_insn (insn
)
2545 rtx prev
= prev_real_insn (insn
);
2548 /* If the previous insn sets a register that dies in our insn, delete it
2550 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2551 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
2552 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2553 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2554 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2555 delete_dead_insn (prev
);
2557 PUT_CODE (insn
, NOTE
);
2558 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2559 NOTE_SOURCE_FILE (insn
) = 0;
2562 /* Modify the home of pseudo-reg I.
2563 The new home is present in reg_renumber[I].
2565 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2566 or it may be -1, meaning there is none or it is not relevant.
2567 This is used so that all pseudos spilled from a given hard reg
2568 can share one stack slot. */
2571 alter_reg (i
, from_reg
)
2575 /* When outputting an inline function, this can happen
2576 for a reg that isn't actually used. */
2577 if (regno_reg_rtx
[i
] == 0)
2580 /* If the reg got changed to a MEM at rtl-generation time,
2582 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
2585 /* Modify the reg-rtx to contain the new hard reg
2586 number or else to contain its pseudo reg number. */
2587 REGNO (regno_reg_rtx
[i
])
2588 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
2590 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2591 allocate a stack slot for it. */
2593 if (reg_renumber
[i
] < 0
2594 && REG_N_REFS (i
) > 0
2595 && reg_equiv_constant
[i
] == 0
2596 && reg_equiv_memory_loc
[i
] == 0)
2599 int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2600 int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2603 /* Each pseudo reg has an inherent size which comes from its own mode,
2604 and a total size which provides room for paradoxical subregs
2605 which refer to the pseudo reg in wider modes.
2607 We can use a slot already allocated if it provides both
2608 enough inherent space and enough total space.
2609 Otherwise, we allocate a new slot, making sure that it has no less
2610 inherent space, and no less total space, then the previous slot. */
2613 /* No known place to spill from => no slot to reuse. */
2614 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
2615 inherent_size
== total_size
? 0 : -1);
2616 if (BYTES_BIG_ENDIAN
)
2617 /* Cancel the big-endian correction done in assign_stack_local.
2618 Get the address of the beginning of the slot.
2619 This is so we can do a big-endian correction unconditionally
2621 adjust
= inherent_size
- total_size
;
2623 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2625 /* Reuse a stack slot if possible. */
2626 else if (spill_stack_slot
[from_reg
] != 0
2627 && spill_stack_slot_width
[from_reg
] >= total_size
2628 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2630 x
= spill_stack_slot
[from_reg
];
2631 /* Allocate a bigger slot. */
2634 /* Compute maximum size needed, both for inherent size
2635 and for total size. */
2636 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2638 if (spill_stack_slot
[from_reg
])
2640 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2642 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2643 if (spill_stack_slot_width
[from_reg
] > total_size
)
2644 total_size
= spill_stack_slot_width
[from_reg
];
2646 /* Make a slot with that size. */
2647 x
= assign_stack_local (mode
, total_size
,
2648 inherent_size
== total_size
? 0 : -1);
2650 if (BYTES_BIG_ENDIAN
)
2652 /* Cancel the big-endian correction done in assign_stack_local.
2653 Get the address of the beginning of the slot.
2654 This is so we can do a big-endian correction unconditionally
2656 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2658 stack_slot
= gen_rtx_MEM (mode_for_size (total_size
2661 plus_constant (XEXP (x
, 0), adjust
));
2663 spill_stack_slot
[from_reg
] = stack_slot
;
2664 spill_stack_slot_width
[from_reg
] = total_size
;
2667 /* On a big endian machine, the "address" of the slot
2668 is the address of the low part that fits its inherent mode. */
2669 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2670 adjust
+= (total_size
- inherent_size
);
2672 /* If we have any adjustment to make, or if the stack slot is the
2673 wrong mode, make a new stack slot. */
2674 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
2676 x
= gen_rtx_MEM (GET_MODE (regno_reg_rtx
[i
]),
2677 plus_constant (XEXP (x
, 0), adjust
));
2679 /* If this was shared among registers, must ensure we never
2680 set it readonly since that can cause scheduling
2681 problems. Note we would only have in this adjustment
2682 case in any event, since the code above doesn't set it. */
2685 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2688 /* Save the stack slot for later. */
2689 reg_equiv_memory_loc
[i
] = x
;
2693 /* Mark the slots in regs_ever_live for the hard regs
2694 used by pseudo-reg number REGNO. */
2697 mark_home_live (regno
)
2700 register int i
, lim
;
2701 i
= reg_renumber
[regno
];
2704 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2706 regs_ever_live
[i
++] = 1;
2709 /* This function handles the tracking of elimination offsets around branches.
2711 X is a piece of RTL being scanned.
2713 INSN is the insn that it came from, if any.
2715 INITIAL_P is non-zero if we are to set the offset to be the initial
2716 offset and zero if we are setting the offset of the label to be the
2720 set_label_offsets (x
, insn
, initial_p
)
2725 enum rtx_code code
= GET_CODE (x
);
2728 struct elim_table
*p
;
2733 if (LABEL_REF_NONLOCAL_P (x
))
2738 /* ... fall through ... */
2741 /* If we know nothing about this label, set the desired offsets. Note
2742 that this sets the offset at a label to be the offset before a label
2743 if we don't know anything about the label. This is not correct for
2744 the label after a BARRIER, but is the best guess we can make. If
2745 we guessed wrong, we will suppress an elimination that might have
2746 been possible had we been able to guess correctly. */
2748 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2750 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2751 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2752 = (initial_p
? reg_eliminate
[i
].initial_offset
2753 : reg_eliminate
[i
].offset
);
2754 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2757 /* Otherwise, if this is the definition of a label and it is
2758 preceded by a BARRIER, set our offsets to the known offset of
2762 && (tem
= prev_nonnote_insn (insn
)) != 0
2763 && GET_CODE (tem
) == BARRIER
)
2765 num_not_at_initial_offset
= 0;
2766 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2768 reg_eliminate
[i
].offset
= reg_eliminate
[i
].previous_offset
2769 = offsets_at
[CODE_LABEL_NUMBER (x
)][i
];
2770 if (reg_eliminate
[i
].can_eliminate
2771 && (reg_eliminate
[i
].offset
2772 != reg_eliminate
[i
].initial_offset
))
2773 num_not_at_initial_offset
++;
2778 /* If neither of the above cases is true, compare each offset
2779 with those previously recorded and suppress any eliminations
2780 where the offsets disagree. */
2782 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2783 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2784 != (initial_p
? reg_eliminate
[i
].initial_offset
2785 : reg_eliminate
[i
].offset
))
2786 reg_eliminate
[i
].can_eliminate
= 0;
2791 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2793 /* ... fall through ... */
2797 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2798 and hence must have all eliminations at their initial offsets. */
2799 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2800 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2801 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2806 /* Each of the labels in the address vector must be at their initial
2807 offsets. We want the first field for ADDR_VEC and the second
2808 field for ADDR_DIFF_VEC. */
2810 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2811 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2816 /* We only care about setting PC. If the source is not RETURN,
2817 IF_THEN_ELSE, or a label, disable any eliminations not at
2818 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2819 isn't one of those possibilities. For branches to a label,
2820 call ourselves recursively.
2822 Note that this can disable elimination unnecessarily when we have
2823 a non-local goto since it will look like a non-constant jump to
2824 someplace in the current function. This isn't a significant
2825 problem since such jumps will normally be when all elimination
2826 pairs are back to their initial offsets. */
2828 if (SET_DEST (x
) != pc_rtx
)
2831 switch (GET_CODE (SET_SRC (x
)))
2838 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2842 tem
= XEXP (SET_SRC (x
), 1);
2843 if (GET_CODE (tem
) == LABEL_REF
)
2844 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2845 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2848 tem
= XEXP (SET_SRC (x
), 2);
2849 if (GET_CODE (tem
) == LABEL_REF
)
2850 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2851 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2859 /* If we reach here, all eliminations must be at their initial
2860 offset because we are doing a jump to a variable address. */
2861 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2862 if (p
->offset
!= p
->initial_offset
)
2863 p
->can_eliminate
= 0;
2871 /* Used for communication between the next two function to properly share
2872 the vector for an ASM_OPERANDS. */
2874 static struct rtvec_def
*old_asm_operands_vec
, *new_asm_operands_vec
;
2876 /* Scan X and replace any eliminable registers (such as fp) with a
2877 replacement (such as sp), plus an offset.
2879 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2880 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2881 MEM, we are allowed to replace a sum of a register and the constant zero
2882 with the register, which we cannot do outside a MEM. In addition, we need
2883 to record the fact that a register is referenced outside a MEM.
2885 If INSN is an insn, it is the insn containing X. If we replace a REG
2886 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2887 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2888 the REG is being modified.
2890 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2891 That's used when we eliminate in expressions stored in notes.
2892 This means, do not set ref_outside_mem even if the reference
2895 If we see a modification to a register we know about, take the
2896 appropriate action (see case SET, below).
2898 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2899 replacements done assuming all offsets are at their initial values. If
2900 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2901 encounter, return the actual location so that find_reloads will do
2902 the proper thing. */
2905 eliminate_regs (x
, mem_mode
, insn
)
2907 enum machine_mode mem_mode
;
2910 enum rtx_code code
= GET_CODE (x
);
2911 struct elim_table
*ep
;
2934 /* This is only for the benefit of the debugging backends, which call
2935 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2936 removed after CSE. */
2937 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2938 if (GET_CODE (new) == MEM
)
2939 return XEXP (new, 0);
2945 /* First handle the case where we encounter a bare register that
2946 is eliminable. Replace it with a PLUS. */
2947 if (regno
< FIRST_PSEUDO_REGISTER
)
2949 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2951 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2954 /* Refs inside notes don't count for this purpose. */
2955 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2956 || GET_CODE (insn
) == INSN_LIST
)))
2957 ep
->ref_outside_mem
= 1;
2958 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2965 /* If this is the sum of an eliminable register and a constant, rework
2967 if (GET_CODE (XEXP (x
, 0)) == REG
2968 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2969 && CONSTANT_P (XEXP (x
, 1)))
2971 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2973 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2976 /* Refs inside notes don't count for this purpose. */
2977 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2978 || GET_CODE (insn
) == INSN_LIST
)))
2979 ep
->ref_outside_mem
= 1;
2981 /* The only time we want to replace a PLUS with a REG (this
2982 occurs when the constant operand of the PLUS is the negative
2983 of the offset) is when we are inside a MEM. We won't want
2984 to do so at other times because that would change the
2985 structure of the insn in a way that reload can't handle.
2986 We special-case the commonest situation in
2987 eliminate_regs_in_insn, so just replace a PLUS with a
2988 PLUS here, unless inside a MEM. */
2989 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2990 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2993 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2994 plus_constant (XEXP (x
, 1),
2995 ep
->previous_offset
));
2998 /* If the register is not eliminable, we are done since the other
2999 operand is a constant. */
3003 /* If this is part of an address, we want to bring any constant to the
3004 outermost PLUS. We will do this by doing register replacement in
3005 our operands and seeing if a constant shows up in one of them.
3007 We assume here this is part of an address (or a "load address" insn)
3008 since an eliminable register is not likely to appear in any other
3011 If we have (plus (eliminable) (reg)), we want to produce
3012 (plus (plus (replacement) (reg) (const))). If this was part of a
3013 normal add insn, (plus (replacement) (reg)) will be pushed as a
3014 reload. This is the desired action. */
3017 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3018 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
3020 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
3022 /* If one side is a PLUS and the other side is a pseudo that
3023 didn't get a hard register but has a reg_equiv_constant,
3024 we must replace the constant here since it may no longer
3025 be in the position of any operand. */
3026 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
3027 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
3028 && reg_renumber
[REGNO (new1
)] < 0
3029 && reg_equiv_constant
!= 0
3030 && reg_equiv_constant
[REGNO (new1
)] != 0)
3031 new1
= reg_equiv_constant
[REGNO (new1
)];
3032 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
3033 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
3034 && reg_renumber
[REGNO (new0
)] < 0
3035 && reg_equiv_constant
[REGNO (new0
)] != 0)
3036 new0
= reg_equiv_constant
[REGNO (new0
)];
3038 new = form_sum (new0
, new1
);
3040 /* As above, if we are not inside a MEM we do not want to
3041 turn a PLUS into something else. We might try to do so here
3042 for an addition of 0 if we aren't optimizing. */
3043 if (! mem_mode
&& GET_CODE (new) != PLUS
)
3044 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
3052 /* If this is the product of an eliminable register and a
3053 constant, apply the distribute law and move the constant out
3054 so that we have (plus (mult ..) ..). This is needed in order
3055 to keep load-address insns valid. This case is pathological.
3056 We ignore the possibility of overflow here. */
3057 if (GET_CODE (XEXP (x
, 0)) == REG
3058 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
3059 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3060 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3062 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
3065 /* Refs inside notes don't count for this purpose. */
3066 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
3067 || GET_CODE (insn
) == INSN_LIST
)))
3068 ep
->ref_outside_mem
= 1;
3071 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
3072 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
3075 /* ... fall through ... */
3080 case DIV
: case UDIV
:
3081 case MOD
: case UMOD
:
3082 case AND
: case IOR
: case XOR
:
3083 case ROTATERT
: case ROTATE
:
3084 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
3086 case GE
: case GT
: case GEU
: case GTU
:
3087 case LE
: case LT
: case LEU
: case LTU
:
3089 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3091 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
3093 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
3094 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
3099 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
3102 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3103 if (new != XEXP (x
, 0))
3104 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
3107 /* ... fall through ... */
3110 /* Now do eliminations in the rest of the chain. If this was
3111 an EXPR_LIST, this might result in allocating more memory than is
3112 strictly needed, but it simplifies the code. */
3115 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
3116 if (new != XEXP (x
, 1))
3117 return gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
3125 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3126 if (ep
->to_rtx
== XEXP (x
, 0))
3128 int size
= GET_MODE_SIZE (mem_mode
);
3130 /* If more bytes than MEM_MODE are pushed, account for them. */
3131 #ifdef PUSH_ROUNDING
3132 if (ep
->to_rtx
== stack_pointer_rtx
)
3133 size
= PUSH_ROUNDING (size
);
3135 if (code
== PRE_DEC
|| code
== POST_DEC
)
3141 /* Fall through to generic unary operation case. */
3142 case STRICT_LOW_PART
:
3144 case SIGN_EXTEND
: case ZERO_EXTEND
:
3145 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3146 case FLOAT
: case FIX
:
3147 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3151 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3152 if (new != XEXP (x
, 0))
3153 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3157 /* Similar to above processing, but preserve SUBREG_WORD.
3158 Convert (subreg (mem)) to (mem) if not paradoxical.
3159 Also, if we have a non-paradoxical (subreg (pseudo)) and the
3160 pseudo didn't get a hard reg, we must replace this with the
3161 eliminated version of the memory location because push_reloads
3162 may do the replacement in certain circumstances. */
3163 if (GET_CODE (SUBREG_REG (x
)) == REG
3164 && (GET_MODE_SIZE (GET_MODE (x
))
3165 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3166 && reg_equiv_memory_loc
!= 0
3167 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
3170 new = eliminate_regs (reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))],
3173 /* If we didn't change anything, we must retain the pseudo. */
3174 if (new == reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))])
3175 new = SUBREG_REG (x
);
3178 /* In this case, we must show that the pseudo is used in this
3179 insn so that delete_output_reload will do the right thing. */
3180 if (insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
3181 && GET_CODE (insn
) != INSN_LIST
)
3182 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode
,
3185 = gen_rtx_EXPR_LIST (REG_EQUAL
, new, NULL_RTX
);
3187 /* Ensure NEW isn't shared in case we have to reload it. */
3188 new = copy_rtx (new);
3191 new = SUBREG_REG (x
);
3195 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
3197 if (new != XEXP (x
, 0))
3199 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
3200 int new_size
= GET_MODE_SIZE (GET_MODE (new));
3202 if (GET_CODE (new) == MEM
3203 && ((x_size
< new_size
3204 #ifdef WORD_REGISTER_OPERATIONS
3205 /* On these machines, combine can create rtl of the form
3206 (set (subreg:m1 (reg:m2 R) 0) ...)
3207 where m1 < m2, and expects something interesting to
3208 happen to the entire word. Moreover, it will use the
3209 (reg:m2 R) later, expecting all bits to be preserved.
3210 So if the number of words is the same, preserve the
3211 subreg so that push_reloads can see it. */
3212 && ! ((x_size
-1)/UNITS_PER_WORD
== (new_size
-1)/UNITS_PER_WORD
)
3215 || (x_size
== new_size
))
3218 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
3219 enum machine_mode mode
= GET_MODE (x
);
3221 if (BYTES_BIG_ENDIAN
)
3222 offset
+= (MIN (UNITS_PER_WORD
,
3223 GET_MODE_SIZE (GET_MODE (new)))
3224 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
3226 PUT_MODE (new, mode
);
3227 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
3231 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_WORD (x
));
3237 /* If using a register that is the source of an eliminate we still
3238 think can be performed, note it cannot be performed since we don't
3239 know how this register is used. */
3240 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3241 if (ep
->from_rtx
== XEXP (x
, 0))
3242 ep
->can_eliminate
= 0;
3244 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3245 if (new != XEXP (x
, 0))
3246 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3250 /* If clobbering a register that is the replacement register for an
3251 elimination we still think can be performed, note that it cannot
3252 be performed. Otherwise, we need not be concerned about it. */
3253 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3254 if (ep
->to_rtx
== XEXP (x
, 0))
3255 ep
->can_eliminate
= 0;
3257 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3258 if (new != XEXP (x
, 0))
3259 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3265 /* Properly handle sharing input and constraint vectors. */
3266 if (ASM_OPERANDS_INPUT_VEC (x
) != old_asm_operands_vec
)
3268 /* When we come to a new vector not seen before,
3269 scan all its elements; keep the old vector if none
3270 of them changes; otherwise, make a copy. */
3271 old_asm_operands_vec
= ASM_OPERANDS_INPUT_VEC (x
);
3272 temp_vec
= (rtx
*) alloca (XVECLEN (x
, 3) * sizeof (rtx
));
3273 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
3274 temp_vec
[i
] = eliminate_regs (ASM_OPERANDS_INPUT (x
, i
),
3277 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
3278 if (temp_vec
[i
] != ASM_OPERANDS_INPUT (x
, i
))
3281 if (i
== ASM_OPERANDS_INPUT_LENGTH (x
))
3282 new_asm_operands_vec
= old_asm_operands_vec
;
3284 new_asm_operands_vec
3285 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x
), temp_vec
);
3288 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3289 if (new_asm_operands_vec
== old_asm_operands_vec
)
3292 new = gen_rtx_ASM_OPERANDS (VOIDmode
, ASM_OPERANDS_TEMPLATE (x
),
3293 ASM_OPERANDS_OUTPUT_CONSTRAINT (x
),
3294 ASM_OPERANDS_OUTPUT_IDX (x
),
3295 new_asm_operands_vec
,
3296 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x
),
3297 ASM_OPERANDS_SOURCE_FILE (x
),
3298 ASM_OPERANDS_SOURCE_LINE (x
));
3299 new->volatil
= x
->volatil
;
3304 /* Check for setting a register that we know about. */
3305 if (GET_CODE (SET_DEST (x
)) == REG
)
3307 /* See if this is setting the replacement register for an
3310 If DEST is the hard frame pointer, we do nothing because we
3311 assume that all assignments to the frame pointer are for
3312 non-local gotos and are being done at a time when they are valid
3313 and do not disturb anything else. Some machines want to
3314 eliminate a fake argument pointer (or even a fake frame pointer)
3315 with either the real frame or the stack pointer. Assignments to
3316 the hard frame pointer must not prevent this elimination. */
3318 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3320 if (ep
->to_rtx
== SET_DEST (x
)
3321 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3323 /* If it is being incremented, adjust the offset. Otherwise,
3324 this elimination can't be done. */
3325 rtx src
= SET_SRC (x
);
3327 if (GET_CODE (src
) == PLUS
3328 && XEXP (src
, 0) == SET_DEST (x
)
3329 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
3330 ep
->offset
-= INTVAL (XEXP (src
, 1));
3332 ep
->can_eliminate
= 0;
3335 /* Now check to see we are assigning to a register that can be
3336 eliminated. If so, it must be as part of a PARALLEL, since we
3337 will not have been called if this is a single SET. So indicate
3338 that we can no longer eliminate this reg. */
3339 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3341 if (ep
->from_rtx
== SET_DEST (x
) && ep
->can_eliminate
)
3342 ep
->can_eliminate
= 0;
3345 /* Now avoid the loop below in this common case. */
3347 rtx new0
= eliminate_regs (SET_DEST (x
), 0, insn
);
3348 rtx new1
= eliminate_regs (SET_SRC (x
), 0, insn
);
3350 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3351 write a CLOBBER insn. */
3352 if (GET_CODE (SET_DEST (x
)) == REG
&& GET_CODE (new0
) == MEM
3353 && insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
3354 && GET_CODE (insn
) != INSN_LIST
)
3355 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, SET_DEST (x
)), insn
);
3357 if (new0
!= SET_DEST (x
) || new1
!= SET_SRC (x
))
3358 return gen_rtx_SET (VOIDmode
, new0
, new1
);
3364 /* This is only for the benefit of the debugging backends, which call
3365 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3366 removed after CSE. */
3367 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
3368 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
3370 /* Our only special processing is to pass the mode of the MEM to our
3371 recursive call and copy the flags. While we are here, handle this
3372 case more efficiently. */
3373 new = eliminate_regs (XEXP (x
, 0), GET_MODE (x
), insn
);
3374 if (new != XEXP (x
, 0))
3376 new = gen_rtx_MEM (GET_MODE (x
), new);
3377 new->volatil
= x
->volatil
;
3378 new->unchanging
= x
->unchanging
;
3379 new->in_struct
= x
->in_struct
;
3389 /* Process each of our operands recursively. If any have changed, make a
3391 fmt
= GET_RTX_FORMAT (code
);
3392 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3396 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
3397 if (new != XEXP (x
, i
) && ! copied
)
3399 rtx new_x
= rtx_alloc (code
);
3400 bcopy ((char *) x
, (char *) new_x
,
3401 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3402 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
3408 else if (*fmt
== 'E')
3411 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3413 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
3414 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
3416 rtvec new_v
= gen_rtvec_vv (XVECLEN (x
, i
),
3420 rtx new_x
= rtx_alloc (code
);
3421 bcopy ((char *) x
, (char *) new_x
,
3422 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3423 + (sizeof (new_x
->fld
[0])
3424 * GET_RTX_LENGTH (code
))));
3428 XVEC (x
, i
) = new_v
;
3431 XVECEXP (x
, i
, j
) = new;
3439 /* Scan INSN and eliminate all eliminable registers in it.
3441 If REPLACE is nonzero, do the replacement destructively. Also
3442 delete the insn as dead it if it is setting an eliminable register.
3444 If REPLACE is zero, do all our allocations in reload_obstack.
3446 If no eliminations were done and this insn doesn't require any elimination
3447 processing (these are not identical conditions: it might be updating sp,
3448 but not referencing fp; this needs to be seen during reload_as_needed so
3449 that the offset between fp and sp can be taken into consideration), zero
3450 is returned. Otherwise, 1 is returned. */
3453 eliminate_regs_in_insn (insn
, replace
)
3457 rtx old_body
= PATTERN (insn
);
3458 rtx old_set
= single_set (insn
);
3461 struct elim_table
*ep
;
3464 push_obstacks (&reload_obstack
, &reload_obstack
);
3466 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
3467 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3469 /* Check for setting an eliminable register. */
3470 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3471 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3473 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3474 /* If this is setting the frame pointer register to the
3475 hardware frame pointer register and this is an elimination
3476 that will be done (tested above), this insn is really
3477 adjusting the frame pointer downward to compensate for
3478 the adjustment done before a nonlocal goto. */
3479 if (ep
->from
== FRAME_POINTER_REGNUM
3480 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3482 rtx src
= SET_SRC (old_set
);
3484 rtx prev_insn
, prev_set
;
3486 if (src
== ep
->to_rtx
)
3488 else if (GET_CODE (src
) == PLUS
3489 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3490 && XEXP (src
, 1) == ep
->to_rtx
)
3491 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3492 else if (GET_CODE (src
) == PLUS
3493 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3494 && XEXP (src
, 0) == ep
->to_rtx
)
3495 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3496 else if ((prev_insn
= prev_nonnote_insn (insn
)) != 0
3497 && (prev_set
= single_set (prev_insn
)) != 0
3498 && rtx_equal_p (SET_DEST (prev_set
), src
))
3500 src
= SET_SRC (prev_set
);
3501 if (src
== ep
->to_rtx
)
3503 else if (GET_CODE (src
) == PLUS
3504 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3505 && XEXP (src
, 1) == ep
->to_rtx
)
3506 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3507 else if (GET_CODE (src
) == PLUS
3508 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3509 && XEXP (src
, 0) == ep
->to_rtx
)
3510 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3518 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3520 /* First see if this insn remains valid when we
3521 make the change. If not, keep the INSN_CODE
3522 the same and let reload fit it up. */
3523 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3524 validate_change (insn
, &SET_DEST (old_set
),
3526 if (! apply_change_group ())
3528 SET_SRC (old_set
) = src
;
3529 SET_DEST (old_set
) = ep
->to_rtx
;
3539 /* In this case this insn isn't serving a useful purpose. We
3540 will delete it in reload_as_needed once we know that this
3541 elimination is, in fact, being done.
3543 If REPLACE isn't set, we can't delete this insn, but needn't
3544 process it since it won't be used unless something changes. */
3546 delete_dead_insn (insn
);
3551 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3552 in the insn is the negative of the offset in FROM. Substitute
3553 (set (reg) (reg to)) for the insn and change its code.
3555 We have to do this here, rather than in eliminate_regs, so that we can
3556 change the insn code. */
3558 if (GET_CODE (SET_SRC (old_set
)) == PLUS
3559 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
3560 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
)
3561 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3563 if (ep
->from_rtx
== XEXP (SET_SRC (old_set
), 0)
3564 && ep
->can_eliminate
)
3566 /* We must stop at the first elimination that will be used.
3567 If this one would replace the PLUS with a REG, do it
3568 now. Otherwise, quit the loop and let eliminate_regs
3569 do its normal replacement. */
3570 if (ep
->offset
== - INTVAL (XEXP (SET_SRC (old_set
), 1)))
3572 /* We assume here that we don't need a PARALLEL of
3573 any CLOBBERs for this assignment. There's not
3574 much we can do if we do need it. */
3575 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3578 INSN_CODE (insn
) = -1;
3587 old_asm_operands_vec
= 0;
3589 /* Replace the body of this insn with a substituted form. If we changed
3590 something, return non-zero.
3592 If we are replacing a body that was a (set X (plus Y Z)), try to
3593 re-recognize the insn. We do this in case we had a simple addition
3594 but now can do this as a load-address. This saves an insn in this
3597 new_body
= eliminate_regs (old_body
, 0, replace
? insn
: NULL_RTX
);
3598 if (new_body
!= old_body
)
3600 /* If we aren't replacing things permanently and we changed something,
3601 make another copy to ensure that all the RTL is new. Otherwise
3602 things can go wrong if find_reload swaps commutative operands
3603 and one is inside RTL that has been copied while the other is not. */
3605 /* Don't copy an asm_operands because (1) there's no need and (2)
3606 copy_rtx can't do it properly when there are multiple outputs. */
3607 if (! replace
&& asm_noperands (old_body
) < 0)
3608 new_body
= copy_rtx (new_body
);
3610 /* If we had a move insn but now we don't, rerecognize it. This will
3611 cause spurious re-recognition if the old move had a PARALLEL since
3612 the new one still will, but we can't call single_set without
3613 having put NEW_BODY into the insn and the re-recognition won't
3614 hurt in this rare case. */
3616 && ((GET_CODE (SET_SRC (old_set
)) == REG
3617 && (GET_CODE (new_body
) != SET
3618 || GET_CODE (SET_SRC (new_body
)) != REG
))
3619 /* If this was a load from or store to memory, compare
3620 the MEM in recog_operand to the one in the insn. If they
3621 are not equal, then rerecognize the insn. */
3623 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3624 && SET_SRC (old_set
) != recog_operand
[1])
3625 || (GET_CODE (SET_DEST (old_set
)) == MEM
3626 && SET_DEST (old_set
) != recog_operand
[0])))
3627 /* If this was an add insn before, rerecognize. */
3628 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3630 if (! validate_change (insn
, &PATTERN (insn
), new_body
, 0))
3631 /* If recognition fails, store the new body anyway.
3632 It's normal to have recognition failures here
3633 due to bizarre memory addresses; reloading will fix them. */
3634 PATTERN (insn
) = new_body
;
3637 PATTERN (insn
) = new_body
;
3642 /* Loop through all elimination pairs. See if any have changed.
3644 We also detect a cases where register elimination cannot be done,
3645 namely, if a register would be both changed and referenced outside a MEM
3646 in the resulting insn since such an insn is often undefined and, even if
3647 not, we cannot know what meaning will be given to it. Note that it is
3648 valid to have a register used in an address in an insn that changes it
3649 (presumably with a pre- or post-increment or decrement).
3651 If anything changes, return nonzero. */
3653 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3655 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3656 ep
->can_eliminate
= 0;
3658 ep
->ref_outside_mem
= 0;
3660 if (ep
->previous_offset
!= ep
->offset
)
3665 /* If we changed something, perform elimination in REG_NOTES. This is
3666 needed even when REPLACE is zero because a REG_DEAD note might refer
3667 to a register that we eliminate and could cause a different number
3668 of spill registers to be needed in the final reload pass than in
3670 if (val
&& REG_NOTES (insn
) != 0)
3671 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3679 /* Loop through all elimination pairs.
3680 Recalculate the number not at initial offset.
3682 Compute the maximum offset (minimum offset if the stack does not
3683 grow downward) for each elimination pair. */
3686 update_eliminable_offsets ()
3688 struct elim_table
*ep
;
3690 num_not_at_initial_offset
= 0;
3691 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3693 ep
->previous_offset
= ep
->offset
;
3694 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3695 num_not_at_initial_offset
++;
3697 #ifdef STACK_GROWS_DOWNWARD
3698 ep
->max_offset
= MAX (ep
->max_offset
, ep
->offset
);
3700 ep
->max_offset
= MIN (ep
->max_offset
, ep
->offset
);
3705 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3706 replacement we currently believe is valid, mark it as not eliminable if X
3707 modifies DEST in any way other than by adding a constant integer to it.
3709 If DEST is the frame pointer, we do nothing because we assume that
3710 all assignments to the hard frame pointer are nonlocal gotos and are being
3711 done at a time when they are valid and do not disturb anything else.
3712 Some machines want to eliminate a fake argument pointer with either the
3713 frame or stack pointer. Assignments to the hard frame pointer must not
3714 prevent this elimination.
3716 Called via note_stores from reload before starting its passes to scan
3717 the insns of the function. */
3720 mark_not_eliminable (dest
, x
)
3724 register unsigned int i
;
3726 /* A SUBREG of a hard register here is just changing its mode. We should
3727 not see a SUBREG of an eliminable hard register, but check just in
3729 if (GET_CODE (dest
) == SUBREG
)
3730 dest
= SUBREG_REG (dest
);
3732 if (dest
== hard_frame_pointer_rtx
)
3735 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3736 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3737 && (GET_CODE (x
) != SET
3738 || GET_CODE (SET_SRC (x
)) != PLUS
3739 || XEXP (SET_SRC (x
), 0) != dest
3740 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3742 reg_eliminate
[i
].can_eliminate_previous
3743 = reg_eliminate
[i
].can_eliminate
= 0;
3748 /* Reset all offsets on eliminable registers to their initial values. */
3750 set_initial_elim_offsets ()
3754 #ifdef ELIMINABLE_REGS
3755 struct elim_table
*ep
;
3757 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3759 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3760 ep
->previous_offset
= ep
->offset
3761 = ep
->max_offset
= ep
->initial_offset
;
3764 #ifdef INITIAL_FRAME_POINTER_OFFSET
3765 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate
[0].initial_offset
);
3767 if (!FRAME_POINTER_REQUIRED
)
3769 reg_eliminate
[0].initial_offset
= 0;
3771 reg_eliminate
[0].previous_offset
= reg_eliminate
[0].max_offset
3772 = reg_eliminate
[0].offset
= reg_eliminate
[0].initial_offset
;
3775 num_not_at_initial_offset
= 0;
3777 bzero ((char *) &offsets_known_at
[get_first_label_num ()], num_labels
);
3779 /* Set a known offset for each forced label to be at the initial offset
3780 of each elimination. We do this because we assume that all
3781 computed jumps occur from a location where each elimination is
3782 at its initial offset. */
3784 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3786 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3789 /* See if anything that happened changes which eliminations are valid.
3790 For example, on the Sparc, whether or not the frame pointer can
3791 be eliminated can depend on what registers have been used. We need
3792 not check some conditions again (such as flag_omit_frame_pointer)
3793 since they can't have changed. */
3796 update_eliminables (pset
)
3799 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3800 int previous_frame_pointer_needed
= frame_pointer_needed
;
3802 struct elim_table
*ep
;
3804 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3805 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3806 #ifdef ELIMINABLE_REGS
3807 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3810 ep
->can_eliminate
= 0;
3812 /* Look for the case where we have discovered that we can't replace
3813 register A with register B and that means that we will now be
3814 trying to replace register A with register C. This means we can
3815 no longer replace register C with register B and we need to disable
3816 such an elimination, if it exists. This occurs often with A == ap,
3817 B == sp, and C == fp. */
3819 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3821 struct elim_table
*op
;
3822 register int new_to
= -1;
3824 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3826 /* Find the current elimination for ep->from, if there is a
3828 for (op
= reg_eliminate
;
3829 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3830 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3836 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3838 for (op
= reg_eliminate
;
3839 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3840 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3841 op
->can_eliminate
= 0;
3845 /* See if any registers that we thought we could eliminate the previous
3846 time are no longer eliminable. If so, something has changed and we
3847 must spill the register. Also, recompute the number of eliminable
3848 registers and see if the frame pointer is needed; it is if there is
3849 no elimination of the frame pointer that we can perform. */
3851 frame_pointer_needed
= 1;
3852 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3854 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3855 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3856 frame_pointer_needed
= 0;
3858 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3860 ep
->can_eliminate_previous
= 0;
3861 SET_HARD_REG_BIT (*pset
, ep
->from
);
3866 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3867 /* If we didn't need a frame pointer last time, but we do now, spill
3868 the hard frame pointer. */
3869 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3870 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3874 /* Initialize the table of registers to eliminate. */
3878 struct elim_table
*ep
;
3880 /* Does this function require a frame pointer? */
3882 frame_pointer_needed
= (! flag_omit_frame_pointer
3883 #ifdef EXIT_IGNORE_STACK
3884 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3885 and restore sp for alloca. So we can't eliminate
3886 the frame pointer in that case. At some point,
3887 we should improve this by emitting the
3888 sp-adjusting insns for this case. */
3889 || (current_function_calls_alloca
3890 && EXIT_IGNORE_STACK
)
3892 || FRAME_POINTER_REQUIRED
);
3896 #ifdef ELIMINABLE_REGS
3897 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3899 ep
->can_eliminate
= ep
->can_eliminate_previous
3900 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3901 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3904 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3905 = ! frame_pointer_needed
;
3908 /* Count the number of eliminable registers and build the FROM and TO
3909 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3910 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3911 We depend on this. */
3912 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3914 num_eliminable
+= ep
->can_eliminate
;
3915 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3916 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3920 /* Kick all pseudos out of hard register REGNO.
3921 If GLOBAL is nonzero, try to find someplace else to put them.
3922 If DUMPFILE is nonzero, log actions taken on that file.
3924 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3925 because we found we can't eliminate some register. In the case, no pseudos
3926 are allowed to be in the register, even if they are only in a block that
3927 doesn't require spill registers, unlike the case when we are spilling this
3928 hard reg to produce another spill register.
3930 Return nonzero if any pseudos needed to be kicked out. */
3933 spill_hard_reg (regno
, global
, dumpfile
, cant_eliminate
)
3939 enum reg_class
class = REGNO_REG_CLASS (regno
);
3940 int something_changed
= 0;
3943 SET_HARD_REG_BIT (forbidden_regs
, regno
);
3946 regs_ever_live
[regno
] = 1;
3948 /* Spill every pseudo reg that was allocated to this reg
3949 or to something that overlaps this reg. */
3951 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3952 if (reg_renumber
[i
] >= 0
3953 && reg_renumber
[i
] <= regno
3955 + HARD_REGNO_NREGS (reg_renumber
[i
],
3956 PSEUDO_REGNO_MODE (i
))
3959 /* If this register belongs solely to a basic block which needed no
3960 spilling of any class that this register is contained in,
3961 leave it be, unless we are spilling this register because
3962 it was a hard register that can't be eliminated. */
3964 if (! cant_eliminate
3965 && basic_block_needs
[0]
3966 && REG_BASIC_BLOCK (i
) >= 0
3967 && basic_block_needs
[(int) class][REG_BASIC_BLOCK (i
)] == 0)
3971 for (p
= reg_class_superclasses
[(int) class];
3972 *p
!= LIM_REG_CLASSES
; p
++)
3973 if (basic_block_needs
[(int) *p
][REG_BASIC_BLOCK (i
)] > 0)
3976 if (*p
== LIM_REG_CLASSES
)
3980 /* Mark it as no longer having a hard register home. */
3981 reg_renumber
[i
] = -1;
3982 /* We will need to scan everything again. */
3983 something_changed
= 1;
3985 retry_global_alloc (i
, forbidden_regs
);
3987 alter_reg (i
, regno
);
3989 if (reg_renumber
[i
] == -1)
3990 SET_REGNO_REG_SET (spilled_pseudos
, i
);
3994 if (reg_renumber
[i
] == -1)
3995 fprintf (dumpfile
, " Register %d now on stack.\n\n", i
);
3997 fprintf (dumpfile
, " Register %d now in %d.\n\n",
3998 i
, reg_renumber
[i
]);
4002 return something_changed
;
4005 /* Clear the contents of spilled_pseudos from the life information in all
4008 finish_spills (global
, dumpfile
)
4012 struct insn_chain
*chain
;
4014 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4016 AND_COMPL_REG_SET (chain
->live_before
, spilled_pseudos
);
4017 AND_COMPL_REG_SET (chain
->live_after
, spilled_pseudos
);
4021 /* Find all paradoxical subregs within X and update reg_max_ref_width.
4022 Also mark any hard registers used to store user variables as
4023 forbidden from being used for spill registers. */
4026 scan_paradoxical_subregs (x
)
4031 register enum rtx_code code
= GET_CODE (x
);
4036 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
4037 && REG_USERVAR_P (x
))
4038 SET_HARD_REG_BIT (forbidden_regs
, REGNO (x
));
4053 if (GET_CODE (SUBREG_REG (x
)) == REG
4054 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
4055 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4056 = GET_MODE_SIZE (GET_MODE (x
));
4063 fmt
= GET_RTX_FORMAT (code
);
4064 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4067 scan_paradoxical_subregs (XEXP (x
, i
));
4068 else if (fmt
[i
] == 'E')
4071 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
4072 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4078 hard_reg_use_compare (p1p
, p2p
)
4079 const GENERIC_PTR p1p
;
4080 const GENERIC_PTR p2p
;
4082 struct hard_reg_n_uses
*p1
= (struct hard_reg_n_uses
*)p1p
,
4083 *p2
= (struct hard_reg_n_uses
*)p2p
;
4084 int tem
= p1
->uses
- p2
->uses
;
4085 if (tem
!= 0) return tem
;
4086 /* If regs are equally good, sort by regno,
4087 so that the results of qsort leave nothing to chance. */
4088 return p1
->regno
- p2
->regno
;
4091 /* Choose the order to consider regs for use as reload registers
4092 based on how much trouble would be caused by spilling one.
4093 Store them in order of decreasing preference in potential_reload_regs. */
4096 order_regs_for_reload ()
4098 register unsigned int i
;
4102 struct hard_reg_n_uses hard_reg_n_uses
[FIRST_PSEUDO_REGISTER
];
4104 CLEAR_HARD_REG_SET (bad_spill_regs
);
4106 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4107 potential_reload_regs
[i
] = -1;
4109 /* Count number of uses of each hard reg by pseudo regs allocated to it
4110 and then order them by decreasing use. */
4112 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4114 hard_reg_n_uses
[i
].uses
= 0;
4115 hard_reg_n_uses
[i
].regno
= i
;
4118 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4120 int regno
= reg_renumber
[i
];
4123 int lim
= regno
+ HARD_REGNO_NREGS (regno
, PSEUDO_REGNO_MODE (i
));
4125 hard_reg_n_uses
[regno
++].uses
+= REG_N_REFS (i
);
4127 large
+= REG_N_REFS (i
);
4130 /* Now fixed registers (which cannot safely be used for reloading)
4131 get a very high use count so they will be considered least desirable.
4132 Registers used explicitly in the rtl code are almost as bad. */
4134 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4138 hard_reg_n_uses
[i
].uses
+= 2 * large
+ 2;
4139 SET_HARD_REG_BIT (bad_spill_regs
, i
);
4141 else if (regs_explicitly_used
[i
])
4143 hard_reg_n_uses
[i
].uses
+= large
+ 1;
4144 if (! SMALL_REGISTER_CLASSES
)
4145 /* ??? We are doing this here because of the potential
4146 that bad code may be generated if a register explicitly
4147 used in an insn was used as a spill register for that
4148 insn. But not using these are spill registers may lose
4149 on some machine. We'll have to see how this works out. */
4150 SET_HARD_REG_BIT (bad_spill_regs
, i
);
4153 hard_reg_n_uses
[HARD_FRAME_POINTER_REGNUM
].uses
+= 2 * large
+ 2;
4154 SET_HARD_REG_BIT (bad_spill_regs
, HARD_FRAME_POINTER_REGNUM
);
4156 #ifdef ELIMINABLE_REGS
4157 /* If registers other than the frame pointer are eliminable, mark them as
4159 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
4161 hard_reg_n_uses
[reg_eliminate
[i
].from
].uses
+= 2 * large
+ 2;
4162 SET_HARD_REG_BIT (bad_spill_regs
, reg_eliminate
[i
].from
);
4166 /* Prefer registers not so far used, for use in temporary loading.
4167 Among them, if REG_ALLOC_ORDER is defined, use that order.
4168 Otherwise, prefer registers not preserved by calls. */
4170 #ifdef REG_ALLOC_ORDER
4171 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4173 int regno
= reg_alloc_order
[i
];
4175 if (hard_reg_n_uses
[regno
].uses
== 0)
4176 potential_reload_regs
[o
++] = regno
;
4179 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4181 if (hard_reg_n_uses
[i
].uses
== 0 && call_used_regs
[i
])
4182 potential_reload_regs
[o
++] = i
;
4184 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4186 if (hard_reg_n_uses
[i
].uses
== 0 && ! call_used_regs
[i
])
4187 potential_reload_regs
[o
++] = i
;
4191 qsort (hard_reg_n_uses
, FIRST_PSEUDO_REGISTER
,
4192 sizeof hard_reg_n_uses
[0], hard_reg_use_compare
);
4194 /* Now add the regs that are already used,
4195 preferring those used less often. The fixed and otherwise forbidden
4196 registers will be at the end of this list. */
4198 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4199 if (hard_reg_n_uses
[i
].uses
!= 0)
4200 potential_reload_regs
[o
++] = hard_reg_n_uses
[i
].regno
;
4203 /* Used in reload_as_needed to sort the spilled regs. */
4206 compare_spill_regs (r1p
, r2p
)
4207 const GENERIC_PTR r1p
;
4208 const GENERIC_PTR r2p
;
4210 short r1
= *(short *)r1p
, r2
= *(short *)r2p
;
4214 /* Reload pseudo-registers into hard regs around each insn as needed.
4215 Additional register load insns are output before the insn that needs it
4216 and perhaps store insns after insns that modify the reloaded pseudo reg.
4218 reg_last_reload_reg and reg_reloaded_contents keep track of
4219 which registers are already available in reload registers.
4220 We update these for the reloads that we perform,
4221 as the insns are scanned. */
4224 reload_as_needed (live_known
)
4227 struct insn_chain
*chain
;
4231 int after_call_nregs
;
4233 bzero ((char *) spill_reg_rtx
, sizeof spill_reg_rtx
);
4234 bzero ((char *) spill_reg_store
, sizeof spill_reg_store
);
4235 reg_last_reload_reg
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
4236 bzero ((char *) reg_last_reload_reg
, max_regno
* sizeof (rtx
));
4237 reg_has_output_reload
= (char *) alloca (max_regno
);
4238 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4240 /* Reset all offsets on eliminable registers to their initial values. */
4241 #ifdef ELIMINABLE_REGS
4242 for (i
= 0; i
< (int) NUM_ELIMINABLE_REGS
; i
++)
4244 INITIAL_ELIMINATION_OFFSET (reg_eliminate
[i
].from
, reg_eliminate
[i
].to
,
4245 reg_eliminate
[i
].initial_offset
);
4246 reg_eliminate
[i
].previous_offset
4247 = reg_eliminate
[i
].offset
= reg_eliminate
[i
].initial_offset
;
4250 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate
[0].initial_offset
);
4251 reg_eliminate
[0].previous_offset
4252 = reg_eliminate
[0].offset
= reg_eliminate
[0].initial_offset
;
4255 num_not_at_initial_offset
= 0;
4257 /* Order the spilled regs, so that allocate_reload_regs can guarantee to
4258 pack registers with group needs. */
4261 qsort (spill_regs
, n_spills
, sizeof (short), compare_spill_regs
);
4262 for (i
= 0; i
< n_spills
; i
++)
4263 spill_reg_order
[spill_regs
[i
]] = i
;
4266 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4268 rtx insn
= chain
->insn
;
4269 rtx old_next
= NEXT_INSN (insn
);
4272 /* If we pass a label, copy the offsets from the label information
4273 into the current offsets of each elimination. */
4274 if (GET_CODE (insn
) == CODE_LABEL
)
4276 num_not_at_initial_offset
= 0;
4277 for (i
= 0; i
< (int) NUM_ELIMINABLE_REGS
; i
++)
4279 reg_eliminate
[i
].offset
= reg_eliminate
[i
].previous_offset
4280 = offsets_at
[CODE_LABEL_NUMBER (insn
)][i
];
4281 if (reg_eliminate
[i
].can_eliminate
4282 && (reg_eliminate
[i
].offset
4283 != reg_eliminate
[i
].initial_offset
))
4284 num_not_at_initial_offset
++;
4288 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
4290 rtx avoid_return_reg
= 0;
4291 rtx oldpat
= PATTERN (insn
);
4293 /* Set avoid_return_reg if this is an insn
4294 that might use the value of a function call. */
4295 if (SMALL_REGISTER_CLASSES
&& GET_CODE (insn
) == CALL_INSN
)
4297 if (GET_CODE (PATTERN (insn
)) == SET
)
4299 after_call
= SET_DEST (PATTERN (insn
));
4300 after_call_nregs
= HARD_REGNO_NREGS (REGNO (after_call
),
4301 GET_MODE (after_call
));
4303 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
4304 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
4306 after_call
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
4307 after_call_nregs
= HARD_REGNO_NREGS (REGNO (after_call
),
4308 GET_MODE (after_call
));
4313 else if (SMALL_REGISTER_CLASSES
&& after_call
!= 0
4314 && !(GET_CODE (PATTERN (insn
)) == SET
4315 && SET_DEST (PATTERN (insn
)) == stack_pointer_rtx
)
4316 && GET_CODE (PATTERN (insn
)) != CLOBBER
4317 && GET_CODE (PATTERN (insn
)) != USE
)
4319 if (reg_referenced_p (after_call
, PATTERN (insn
)))
4321 avoid_return_reg
= after_call
;
4322 if (! --after_call_nregs
)
4326 /* If INSN copies the return register in a single chunk,
4327 clear after_call now. */
4328 rtx set
= single_set (insn
);
4329 if (set
&& (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
4330 == GET_MODE_SIZE (GET_MODE (after_call
))))
4338 /* If this is a USE and CLOBBER of a MEM, ensure that any
4339 references to eliminable registers have been removed. */
4341 if ((GET_CODE (PATTERN (insn
)) == USE
4342 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4343 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
4344 XEXP (XEXP (PATTERN (insn
), 0), 0)
4345 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4346 GET_MODE (XEXP (PATTERN (insn
), 0)),
4349 /* If we need to do register elimination processing, do so.
4350 This might delete the insn, in which case we are done. */
4351 if (num_eliminable
&& chain
->need_elim
)
4353 eliminate_regs_in_insn (insn
, 1);
4354 if (GET_CODE (insn
) == NOTE
)
4356 update_eliminable_offsets ();
4361 /* If need_elim is nonzero but need_reload is zero, one might think
4362 that we could simply set n_reloads to 0. However, find_reloads
4363 could have done some manipulation of the insn (such as swapping
4364 commutative operands), and these manipulations are lost during
4365 the first pass for every insn that needs register elimination.
4366 So the actions of find_reloads must be redone here. */
4368 if (! chain
->need_elim
&& ! chain
->need_reload
)
4370 /* First find the pseudo regs that must be reloaded for this insn.
4371 This info is returned in the tables reload_... (see reload.h).
4372 Also modify the body of INSN by substituting RELOAD
4373 rtx's for those pseudo regs. */
4376 bzero (reg_has_output_reload
, max_regno
);
4377 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4379 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4383 if (num_eliminable
&& chain
->need_elim
)
4384 update_eliminable_offsets ();
4388 rtx next
= NEXT_INSN (insn
);
4392 prev
= PREV_INSN (insn
);
4394 /* If this block has not had spilling done for a
4395 particular clas and we have any non-optionals that need a
4396 spill reg in that class, abort. */
4398 for (class = 0; class < N_REG_CLASSES
; class++)
4399 if (basic_block_needs
[class] != 0
4400 && basic_block_needs
[class][chain
->block
] == 0)
4401 for (i
= 0; i
< n_reloads
; i
++)
4402 if (class == (int) reload_reg_class
[i
]
4403 && reload_reg_rtx
[i
] == 0
4404 && ! reload_optional
[i
]
4405 && (reload_in
[i
] != 0 || reload_out
[i
] != 0
4406 || reload_secondary_p
[i
] != 0))
4407 fatal_insn ("Non-optional registers need a spill register", insn
);
4409 /* Now compute which reload regs to reload them into. Perhaps
4410 reusing reload regs from previous insns, or else output
4411 load insns to reload them. Maybe output store insns too.
4412 Record the choices of reload reg in reload_reg_rtx. */
4413 choose_reload_regs (chain
, avoid_return_reg
);
4415 /* Merge any reloads that we didn't combine for fear of
4416 increasing the number of spill registers needed but now
4417 discover can be safely merged. */
4418 if (SMALL_REGISTER_CLASSES
)
4419 merge_assigned_reloads (insn
);
4421 /* Generate the insns to reload operands into or out of
4422 their reload regs. */
4423 emit_reload_insns (chain
);
4425 /* Substitute the chosen reload regs from reload_reg_rtx
4426 into the insn's body (or perhaps into the bodies of other
4427 load and store insn that we just made for reloading
4428 and that we moved the structure into). */
4431 /* If this was an ASM, make sure that all the reload insns
4432 we have generated are valid. If not, give an error
4435 if (asm_noperands (PATTERN (insn
)) >= 0)
4436 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4437 if (p
!= insn
&& GET_RTX_CLASS (GET_CODE (p
)) == 'i'
4438 && (recog_memoized (p
) < 0
4439 || (insn_extract (p
),
4440 ! constrain_operands (INSN_CODE (p
), 1))))
4442 error_for_asm (insn
,
4443 "`asm' operand requires impossible reload");
4445 NOTE_SOURCE_FILE (p
) = 0;
4446 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
4449 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4450 is no longer validly lying around to save a future reload.
4451 Note that this does not detect pseudos that were reloaded
4452 for this insn in order to be stored in
4453 (obeying register constraints). That is correct; such reload
4454 registers ARE still valid. */
4455 note_stores (oldpat
, forget_old_reloads_1
);
4457 /* There may have been CLOBBER insns placed after INSN. So scan
4458 between INSN and NEXT and use them to forget old reloads. */
4459 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4460 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
4461 note_stores (PATTERN (x
), forget_old_reloads_1
);
4464 /* Likewise for regs altered by auto-increment in this insn.
4465 REG_INC notes have been changed by reloading:
4466 find_reloads_address_1 records substitutions for them,
4467 which have been performed by subst_reloads above. */
4468 for (i
= n_reloads
- 1; i
>= 0; i
--)
4470 rtx in_reg
= reload_in_reg
[i
];
4473 enum rtx_code code
= GET_CODE (in_reg
);
4474 /* PRE_INC / PRE_DEC will have the reload register ending up
4475 with the same value as the stack slot, but that doesn't
4476 hold true for POST_INC / POST_DEC. Either we have to
4477 convert the memory access to a true POST_INC / POST_DEC,
4478 or we can't use the reload register for inheritance. */
4479 if ((code
== POST_INC
|| code
== POST_DEC
)
4480 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4481 REGNO (reload_reg_rtx
[i
]))
4482 /* Make sure it is the inc/dec pseudo, and not
4483 some other (e.g. output operand) pseudo. */
4484 && (reg_reloaded_contents
[REGNO (reload_reg_rtx
[i
])]
4485 == REGNO (XEXP (in_reg
, 0))))
4488 rtx reload_reg
= reload_reg_rtx
[i
];
4489 enum machine_mode mode
= GET_MODE (reload_reg
);
4493 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4495 /* We really want to ignore REG_INC notes here, so
4496 use PATTERN (p) as argument to reg_set_p . */
4497 if (reg_set_p (reload_reg
, PATTERN (p
)))
4499 n
= count_occurrences (PATTERN (p
), reload_reg
);
4503 n
= validate_replace_rtx (reload_reg
,
4504 gen_rtx (code
, mode
,
4509 REG_NOTES (p
) = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4512 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
);
4516 #if 0 /* ??? Is this code obsolete now? Need to check carefully. */
4517 /* Likewise for regs altered by auto-increment in this insn.
4518 But note that the reg-notes are not changed by reloading:
4519 they still contain the pseudo-regs, not the spill regs. */
4520 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4521 if (REG_NOTE_KIND (x
) == REG_INC
)
4523 /* See if this pseudo reg was reloaded in this insn.
4524 If so, its last-reload info is still valid
4525 because it is based on this insn's reload. */
4526 for (i
= 0; i
< n_reloads
; i
++)
4527 if (reload_out
[i
] == XEXP (x
, 0))
4531 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
);
4536 /* A reload reg's contents are unknown after a label. */
4537 if (GET_CODE (insn
) == CODE_LABEL
)
4538 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4540 /* Don't assume a reload reg is still good after a call insn
4541 if it is a call-used reg. */
4542 else if (GET_CODE (insn
) == CALL_INSN
)
4543 AND_COMPL_HARD_REG_SET(reg_reloaded_valid
, call_used_reg_set
);
4545 /* In case registers overlap, allow certain insns to invalidate
4546 particular hard registers. */
4548 #ifdef INSN_CLOBBERS_REGNO_P
4549 for (i
= 0 ; i
< FIRST_PSEUDO_REGISTER
; i
++)
4550 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
4551 && INSN_CLOBBERS_REGNO_P (insn
, i
))
4552 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
);
4561 /* Discard all record of any value reloaded from X,
4562 or reloaded in X from someplace else;
4563 unless X is an output reload reg of the current insn.
4565 X may be a hard reg (the reload reg)
4566 or it may be a pseudo reg that was reloaded from. */
4569 forget_old_reloads_1 (x
, ignored
)
4571 rtx ignored ATTRIBUTE_UNUSED
;
4577 /* note_stores does give us subregs of hard regs. */
4578 while (GET_CODE (x
) == SUBREG
)
4580 offset
+= SUBREG_WORD (x
);
4584 if (GET_CODE (x
) != REG
)
4587 regno
= REGNO (x
) + offset
;
4589 if (regno
>= FIRST_PSEUDO_REGISTER
)
4594 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4595 /* Storing into a spilled-reg invalidates its contents.
4596 This can happen if a block-local pseudo is allocated to that reg
4597 and it wasn't spilled because this block's total need is 0.
4598 Then some insn might have an optional reload and use this reg. */
4599 for (i
= 0; i
< nr
; i
++)
4600 /* But don't do this if the reg actually serves as an output
4601 reload reg in the current instruction. */
4603 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4604 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4607 /* Since value of X has changed,
4608 forget any value previously copied from it. */
4611 /* But don't forget a copy if this is the output reload
4612 that establishes the copy's validity. */
4613 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4614 reg_last_reload_reg
[regno
+ nr
] = 0;
4617 /* For each reload, the mode of the reload register. */
4618 static enum machine_mode reload_mode
[MAX_RELOADS
];
4620 /* For each reload, the largest number of registers it will require. */
4621 static int reload_nregs
[MAX_RELOADS
];
4623 /* Comparison function for qsort to decide which of two reloads
4624 should be handled first. *P1 and *P2 are the reload numbers. */
4627 reload_reg_class_lower (r1p
, r2p
)
4628 const GENERIC_PTR r1p
;
4629 const GENERIC_PTR r2p
;
4631 register int r1
= *(short *)r1p
, r2
= *(short *)r2p
;
4634 /* Consider required reloads before optional ones. */
4635 t
= reload_optional
[r1
] - reload_optional
[r2
];
4639 /* Count all solitary classes before non-solitary ones. */
4640 t
= ((reg_class_size
[(int) reload_reg_class
[r2
]] == 1)
4641 - (reg_class_size
[(int) reload_reg_class
[r1
]] == 1));
4645 /* Aside from solitaires, consider all multi-reg groups first. */
4646 t
= reload_nregs
[r2
] - reload_nregs
[r1
];
4650 /* Consider reloads in order of increasing reg-class number. */
4651 t
= (int) reload_reg_class
[r1
] - (int) reload_reg_class
[r2
];
4655 /* If reloads are equally urgent, sort by reload number,
4656 so that the results of qsort leave nothing to chance. */
4660 /* The following HARD_REG_SETs indicate when each hard register is
4661 used for a reload of various parts of the current insn. */
4663 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4664 static HARD_REG_SET reload_reg_used
;
4665 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4666 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4667 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4668 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4669 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4670 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4671 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4672 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4673 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4674 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4675 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4676 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4677 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4678 static HARD_REG_SET reload_reg_used_in_op_addr
;
4679 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4680 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4681 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4682 static HARD_REG_SET reload_reg_used_in_insn
;
4683 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4684 static HARD_REG_SET reload_reg_used_in_other_addr
;
4686 /* If reg is in use as a reload reg for any sort of reload. */
4687 static HARD_REG_SET reload_reg_used_at_all
;
4689 /* If reg is use as an inherited reload. We just mark the first register
4691 static HARD_REG_SET reload_reg_used_for_inherit
;
4693 /* Records which hard regs are allocated to a pseudo during any point of the
4695 static HARD_REG_SET reg_used_by_pseudo
;
4697 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4698 TYPE. MODE is used to indicate how many consecutive regs are
4702 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4705 enum reload_type type
;
4706 enum machine_mode mode
;
4708 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4711 for (i
= regno
; i
< nregs
+ regno
; i
++)
4716 SET_HARD_REG_BIT (reload_reg_used
, i
);
4719 case RELOAD_FOR_INPUT_ADDRESS
:
4720 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4723 case RELOAD_FOR_INPADDR_ADDRESS
:
4724 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4727 case RELOAD_FOR_OUTPUT_ADDRESS
:
4728 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4731 case RELOAD_FOR_OUTADDR_ADDRESS
:
4732 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4735 case RELOAD_FOR_OPERAND_ADDRESS
:
4736 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4739 case RELOAD_FOR_OPADDR_ADDR
:
4740 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4743 case RELOAD_FOR_OTHER_ADDRESS
:
4744 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4747 case RELOAD_FOR_INPUT
:
4748 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4751 case RELOAD_FOR_OUTPUT
:
4752 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4755 case RELOAD_FOR_INSN
:
4756 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4760 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4764 /* Similarly, but show REGNO is no longer in use for a reload. */
4767 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4770 enum reload_type type
;
4771 enum machine_mode mode
;
4773 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4774 int start_regno
, end_regno
;
4776 /* A complication is that for some reload types, inheritance might
4777 allow multiple reloads of the same types to share a reload register.
4778 We set check_opnum if we have to check only reloads with the same
4779 operand number, and check_any if we have to check all reloads. */
4780 int check_opnum
= 0;
4782 HARD_REG_SET
*used_in_set
;
4787 used_in_set
= &reload_reg_used
;
4790 case RELOAD_FOR_INPUT_ADDRESS
:
4791 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4794 case RELOAD_FOR_INPADDR_ADDRESS
:
4796 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4799 case RELOAD_FOR_OUTPUT_ADDRESS
:
4800 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4803 case RELOAD_FOR_OUTADDR_ADDRESS
:
4805 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4808 case RELOAD_FOR_OPERAND_ADDRESS
:
4809 used_in_set
= &reload_reg_used_in_op_addr
;
4812 case RELOAD_FOR_OPADDR_ADDR
:
4814 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4817 case RELOAD_FOR_OTHER_ADDRESS
:
4818 used_in_set
= &reload_reg_used_in_other_addr
;
4822 case RELOAD_FOR_INPUT
:
4823 used_in_set
= &reload_reg_used_in_input
[opnum
];
4826 case RELOAD_FOR_OUTPUT
:
4827 used_in_set
= &reload_reg_used_in_output
[opnum
];
4830 case RELOAD_FOR_INSN
:
4831 used_in_set
= &reload_reg_used_in_insn
;
4836 /* We resolve conflicts with remaining reloads of the same type by
4837 excluding the intervals of of reload registers by them from the
4838 interval of freed reload registers. Since we only keep track of
4839 one set of interval bounds, we might have to exclude somewhat
4840 more then what would be necessary if we used a HARD_REG_SET here.
4841 But this should only happen very infrequently, so there should
4842 be no reason to worry about it. */
4844 start_regno
= regno
;
4845 end_regno
= regno
+ nregs
;
4846 if (check_opnum
|| check_any
)
4848 for (i
= n_reloads
- 1; i
>= 0; i
--)
4850 if (reload_when_needed
[i
] == type
4851 && (check_any
|| reload_opnum
[i
] == opnum
)
4852 && reload_reg_rtx
[i
])
4854 int conflict_start
= true_regnum (reload_reg_rtx
[i
]);
4857 + HARD_REGNO_NREGS (conflict_start
, reload_mode
[i
]));
4859 /* If there is an overlap with the first to-be-freed register,
4860 adjust the interval start. */
4861 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4862 start_regno
= conflict_end
;
4863 /* Otherwise, if there is a conflict with one of the other
4864 to-be-freed registers, adjust the interval end. */
4865 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4866 end_regno
= conflict_start
;
4870 for (i
= start_regno
; i
< end_regno
; i
++)
4871 CLEAR_HARD_REG_BIT (*used_in_set
, i
);
4874 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4875 specified by OPNUM and TYPE. */
4878 reload_reg_free_p (regno
, opnum
, type
)
4881 enum reload_type type
;
4885 /* In use for a RELOAD_OTHER means it's not available for anything. */
4886 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4892 /* In use for anything means we can't use it for RELOAD_OTHER. */
4893 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4894 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4895 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4898 for (i
= 0; i
< reload_n_operands
; i
++)
4899 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4900 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4901 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4902 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4903 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4904 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4909 case RELOAD_FOR_INPUT
:
4910 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4911 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4914 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4917 /* If it is used for some other input, can't use it. */
4918 for (i
= 0; i
< reload_n_operands
; i
++)
4919 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4922 /* If it is used in a later operand's address, can't use it. */
4923 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4924 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4925 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4930 case RELOAD_FOR_INPUT_ADDRESS
:
4931 /* Can't use a register if it is used for an input address for this
4932 operand or used as an input in an earlier one. */
4933 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4934 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4937 for (i
= 0; i
< opnum
; i
++)
4938 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4943 case RELOAD_FOR_INPADDR_ADDRESS
:
4944 /* Can't use a register if it is used for an input address
4945 for this operand or used as an input in an earlier
4947 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4950 for (i
= 0; i
< opnum
; i
++)
4951 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4956 case RELOAD_FOR_OUTPUT_ADDRESS
:
4957 /* Can't use a register if it is used for an output address for this
4958 operand or used as an output in this or a later operand. */
4959 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4962 for (i
= opnum
; i
< reload_n_operands
; i
++)
4963 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4968 case RELOAD_FOR_OUTADDR_ADDRESS
:
4969 /* Can't use a register if it is used for an output address
4970 for this operand or used as an output in this or a
4972 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4975 for (i
= opnum
; i
< reload_n_operands
; i
++)
4976 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4981 case RELOAD_FOR_OPERAND_ADDRESS
:
4982 for (i
= 0; i
< reload_n_operands
; i
++)
4983 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4986 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4987 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4989 case RELOAD_FOR_OPADDR_ADDR
:
4990 for (i
= 0; i
< reload_n_operands
; i
++)
4991 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4994 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4996 case RELOAD_FOR_OUTPUT
:
4997 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4998 outputs, or an operand address for this or an earlier output. */
4999 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5002 for (i
= 0; i
< reload_n_operands
; i
++)
5003 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5006 for (i
= 0; i
<= opnum
; i
++)
5007 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5008 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5013 case RELOAD_FOR_INSN
:
5014 for (i
= 0; i
< reload_n_operands
; i
++)
5015 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5016 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5019 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5020 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5022 case RELOAD_FOR_OTHER_ADDRESS
:
5023 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5028 /* Return 1 if the value in reload reg REGNO, as used by a reload
5029 needed for the part of the insn specified by OPNUM and TYPE,
5030 is not in use for a reload in any prior part of the insn.
5032 We can assume that the reload reg was already tested for availability
5033 at the time it is needed, and we should not check this again,
5034 in case the reg has already been marked in use.
5036 However, if EQUIV is set, we are checking the availability of a register
5037 holding an equivalence to the value to be loaded into the reload register,
5038 not the availability of the reload register itself.
5040 This is still less stringent than what reload_reg_free_p checks; for
5041 example, compare the checks for RELOAD_OTHER. */
5044 reload_reg_free_before_p (regno
, opnum
, type
, equiv
)
5047 enum reload_type type
;
5052 /* The code to handle EQUIV below is wrong.
5054 If we wnat to know if a value in a particular reload register is available
5055 at a particular point in time during reloading, we must check *all*
5056 prior reloads to see if they clobber the value.
5058 Note this is significantly different from determining when a register is
5059 free for usage in a reload!
5061 This change is temporary. It will go away. */
5067 case RELOAD_FOR_OTHER_ADDRESS
:
5068 /* These always come first. */
5069 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
))
5074 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used
, regno
))
5076 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5078 /* If this use is for part of the insn,
5079 check the reg is not in use for any prior part. It is tempting
5080 to try to do this by falling through from objecs that occur
5081 later in the insn to ones that occur earlier, but that will not
5082 correctly take into account the fact that here we MUST ignore
5083 things that would prevent the register from being allocated in
5084 the first place, since we know that it was allocated. */
5086 case RELOAD_FOR_OUTPUT_ADDRESS
:
5088 && TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5090 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */
5091 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5093 /* ... fall through ... */
5094 case RELOAD_FOR_OUTADDR_ADDRESS
:
5096 && (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
)
5097 || TEST_HARD_REG_BIT (reload_reg_used
, regno
)))
5099 /* Earlier reloads are for earlier outputs or their addresses,
5100 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
5101 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
5103 for (i
= 0; i
< opnum
; i
++)
5104 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5105 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5108 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5111 for (i
= 0; i
< reload_n_operands
; i
++)
5112 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5113 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5114 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5115 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5118 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5119 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5120 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5121 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5123 case RELOAD_FOR_OUTPUT
:
5124 case RELOAD_FOR_INSN
:
5125 /* There is no reason to call this function for output reloads, thus
5126 anything we'd put here wouldn't be tested. So just abort. */
5129 case RELOAD_FOR_OPERAND_ADDRESS
:
5130 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5133 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */
5134 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5137 /* ... fall through ... */
5139 case RELOAD_FOR_OPADDR_ADDR
:
5142 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5143 || TEST_HARD_REG_BIT (reload_reg_used
, regno
))
5145 for (i
= 0; i
< reload_n_operands
; i
++)
5146 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5149 /* These can't conflict with inputs, or each other, so all we have to
5150 test is input addresses and the addresses of OTHER items. */
5152 for (i
= 0; i
< reload_n_operands
; i
++)
5153 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5154 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5157 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5159 case RELOAD_FOR_INPUT
:
5160 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used
, regno
))
5163 /* The only things earlier are the address for this and
5164 earlier inputs, other inputs (which we know we don't conflict
5165 with), and addresses of RELOAD_OTHER objects.
5166 We can ignore the conflict with addresses of this operand, since
5167 when we inherit this operand, its address reloads are discarded. */
5169 for (i
= 0; i
< opnum
; i
++)
5170 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5171 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5174 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5176 case RELOAD_FOR_INPUT_ADDRESS
:
5177 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */
5178 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5180 /* ... fall through ... */
5181 case RELOAD_FOR_INPADDR_ADDRESS
:
5182 if (equiv
&& TEST_HARD_REG_BIT (reload_reg_used
, regno
))
5185 /* Similarly, all we have to check is for use in earlier inputs'
5187 for (i
= 0; i
< opnum
; i
++)
5188 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5189 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5192 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5197 /* Return 1 if the value in reload reg REGNO, as used by a reload
5198 needed for the part of the insn specified by OPNUM and TYPE,
5199 is still available in REGNO at the end of the insn.
5201 We can assume that the reload reg was already tested for availability
5202 at the time it is needed, and we should not check this again,
5203 in case the reg has already been marked in use. */
5206 reload_reg_reaches_end_p (regno
, opnum
, type
)
5209 enum reload_type type
;
5216 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5217 its value must reach the end. */
5220 /* If this use is for part of the insn,
5221 its value reaches if no subsequent part uses the same register.
5222 Just like the above function, don't try to do this with lots
5225 case RELOAD_FOR_OTHER_ADDRESS
:
5226 /* Here we check for everything else, since these don't conflict
5227 with anything else and everything comes later. */
5229 for (i
= 0; i
< reload_n_operands
; i
++)
5230 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5231 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5232 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5233 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5234 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5235 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5238 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5239 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5240 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5242 case RELOAD_FOR_INPUT_ADDRESS
:
5243 case RELOAD_FOR_INPADDR_ADDRESS
:
5244 /* Similar, except that we check only for this and subsequent inputs
5245 and the address of only subsequent inputs and we do not need
5246 to check for RELOAD_OTHER objects since they are known not to
5249 for (i
= opnum
; i
< reload_n_operands
; i
++)
5250 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5253 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5254 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5255 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5258 for (i
= 0; i
< reload_n_operands
; i
++)
5259 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5260 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5261 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5264 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5267 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5268 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
5270 case RELOAD_FOR_INPUT
:
5271 /* Similar to input address, except we start at the next operand for
5272 both input and input address and we do not check for
5273 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5276 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5277 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5278 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5279 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5282 /* ... fall through ... */
5284 case RELOAD_FOR_OPERAND_ADDRESS
:
5285 /* Check outputs and their addresses. */
5287 for (i
= 0; i
< reload_n_operands
; i
++)
5288 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5289 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5290 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5295 case RELOAD_FOR_OPADDR_ADDR
:
5296 for (i
= 0; i
< reload_n_operands
; i
++)
5297 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5298 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5299 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5302 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5303 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
5305 case RELOAD_FOR_INSN
:
5306 /* These conflict with other outputs with RELOAD_OTHER. So
5307 we need only check for output addresses. */
5311 /* ... fall through ... */
5313 case RELOAD_FOR_OUTPUT
:
5314 case RELOAD_FOR_OUTPUT_ADDRESS
:
5315 case RELOAD_FOR_OUTADDR_ADDRESS
:
5316 /* We already know these can't conflict with a later output. So the
5317 only thing to check are later output addresses. */
5318 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5319 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5320 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5329 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5332 This function uses the same algorithm as reload_reg_free_p above. */
5335 reloads_conflict (r1
, r2
)
5338 enum reload_type r1_type
= reload_when_needed
[r1
];
5339 enum reload_type r2_type
= reload_when_needed
[r2
];
5340 int r1_opnum
= reload_opnum
[r1
];
5341 int r2_opnum
= reload_opnum
[r2
];
5343 /* RELOAD_OTHER conflicts with everything. */
5344 if (r2_type
== RELOAD_OTHER
)
5347 /* Otherwise, check conflicts differently for each type. */
5351 case RELOAD_FOR_INPUT
:
5352 return (r2_type
== RELOAD_FOR_INSN
5353 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5354 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5355 || r2_type
== RELOAD_FOR_INPUT
5356 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5357 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5358 && r2_opnum
> r1_opnum
));
5360 case RELOAD_FOR_INPUT_ADDRESS
:
5361 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5362 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5364 case RELOAD_FOR_INPADDR_ADDRESS
:
5365 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5366 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5368 case RELOAD_FOR_OUTPUT_ADDRESS
:
5369 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5370 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5372 case RELOAD_FOR_OUTADDR_ADDRESS
:
5373 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5374 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5376 case RELOAD_FOR_OPERAND_ADDRESS
:
5377 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5378 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5380 case RELOAD_FOR_OPADDR_ADDR
:
5381 return (r2_type
== RELOAD_FOR_INPUT
5382 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5384 case RELOAD_FOR_OUTPUT
:
5385 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5386 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5387 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5388 && r2_opnum
>= r1_opnum
));
5390 case RELOAD_FOR_INSN
:
5391 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5392 || r2_type
== RELOAD_FOR_INSN
5393 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5395 case RELOAD_FOR_OTHER_ADDRESS
:
5396 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5406 /* Vector of reload-numbers showing the order in which the reloads should
5408 short reload_order
[MAX_RELOADS
];
5410 /* Indexed by reload number, 1 if incoming value
5411 inherited from previous insns. */
5412 char reload_inherited
[MAX_RELOADS
];
5414 /* For an inherited reload, this is the insn the reload was inherited from,
5415 if we know it. Otherwise, this is 0. */
5416 rtx reload_inheritance_insn
[MAX_RELOADS
];
5418 /* If non-zero, this is a place to get the value of the reload,
5419 rather than using reload_in. */
5420 rtx reload_override_in
[MAX_RELOADS
];
5422 /* For each reload, the hard register number of the register used,
5423 or -1 if we did not need a register for this reload. */
5424 int reload_spill_index
[MAX_RELOADS
];
5426 /* Return 1 if the value in reload reg REGNO, as used by a reload
5427 needed for the part of the insn specified by OPNUM and TYPE,
5428 may be used to load VALUE into it.
5430 Other read-only reloads with the same value do not conflict
5431 unless OUT is non-zero and these other reloads have to live while
5432 output reloads live.
5434 RELOADNUM is the number of the reload we want to load this value for;
5435 a reload does not conflict with itself.
5437 The caller has to make sure that there is no conflict with the return
5440 reload_reg_free_for_value_p (regno
, opnum
, type
, value
, out
, reloadnum
)
5443 enum reload_type type
;
5450 /* We use some pseudo 'time' value to check if the lifetimes of the
5451 new register use would overlap with the one of a previous reload
5452 that is not read-only or uses a different value.
5453 The 'time' used doesn't have to be linear in any shape or form, just
5455 Some reload types use different 'buckets' for each operand.
5456 So there are MAX_RECOG_OPERANDS different time values for each
5458 We compute TIME1 as the time when the register for the prospective
5459 new reload ceases to be live, and TIME2 for each existing
5460 reload as the time when that the reload register of that reload
5462 Where there is little to be gained by exact lifetime calculations,
5463 we just make conservative assumptions, i.e. a longer lifetime;
5464 this is done in the 'default:' cases. */
5467 case RELOAD_FOR_OTHER_ADDRESS
:
5470 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5471 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5472 respectively, to the time values for these, we get distinct time
5473 values. To get distinct time values for each operand, we have to
5474 multiply opnum by at least three. We round that up to four because
5475 multiply by four is often cheaper. */
5476 case RELOAD_FOR_INPADDR_ADDRESS
:
5477 time1
= opnum
* 4 + 1;
5479 case RELOAD_FOR_INPUT_ADDRESS
:
5480 time1
= opnum
* 4 + 2;
5482 case RELOAD_FOR_OPADDR_ADDR
:
5483 /* opnum * 4 + 3 < opnum * 4 + 4
5484 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5485 time1
= MAX_RECOG_OPERANDS
* 4;
5487 case RELOAD_FOR_INPUT
:
5488 /* All RELOAD_FOR_INPUT reloads remain live till just before the
5489 instruction is executed. */
5490 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5492 case RELOAD_FOR_OPERAND_ADDRESS
:
5493 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5495 time1
= MAX_RECOG_OPERANDS
* 4 + 2;
5497 case RELOAD_FOR_OUTPUT_ADDRESS
:
5498 time1
= MAX_RECOG_OPERANDS
* 4 + 3 + opnum
;
5501 time1
= MAX_RECOG_OPERANDS
* 5 + 3;
5504 for (i
= 0; i
< n_reloads
; i
++)
5506 rtx reg
= reload_reg_rtx
[i
];
5507 if (reg
&& GET_CODE (reg
) == REG
5508 && ((unsigned) regno
- true_regnum (reg
)
5509 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned)1)
5513 && reload_when_needed
[i
] != RELOAD_FOR_INPUT
5514 && reload_when_needed
[i
] != RELOAD_FOR_INPUT_ADDRESS
5515 && reload_when_needed
[i
] != RELOAD_FOR_INPADDR_ADDRESS
)
5517 if (! reload_in
[i
] || ! rtx_equal_p (reload_in
[i
], value
)
5521 switch (reload_when_needed
[i
])
5523 case RELOAD_FOR_OTHER_ADDRESS
:
5526 case RELOAD_FOR_INPADDR_ADDRESS
:
5527 /* find_reloads makes sure that a
5528 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5529 by at most one - the first -
5530 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5531 address reload is inherited, the address address reload
5532 goes away, so we can ignore this conflict. */
5533 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1)
5535 time2
= reload_opnum
[i
] * 4 + 1;
5537 case RELOAD_FOR_INPUT_ADDRESS
:
5538 time2
= reload_opnum
[i
] * 4 + 2;
5540 case RELOAD_FOR_INPUT
:
5541 time2
= reload_opnum
[i
] * 4 + 3;
5543 case RELOAD_FOR_OPADDR_ADDR
:
5544 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1)
5546 time2
= MAX_RECOG_OPERANDS
* 4;
5548 case RELOAD_FOR_OPERAND_ADDRESS
:
5549 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5551 case RELOAD_FOR_OUTPUT
:
5552 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5553 instruction is executed. */
5554 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5556 case RELOAD_FOR_OUTADDR_ADDRESS
:
5557 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1)
5560 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the
5561 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */
5562 case RELOAD_FOR_OUTPUT_ADDRESS
:
5563 time2
= MAX_RECOG_OPERANDS
* 4 + 3 + reload_opnum
[i
];
5566 if (! reload_in
[i
] || rtx_equal_p (reload_in
[i
], value
))
5568 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5582 /* Find a spill register to use as a reload register for reload R.
5583 LAST_RELOAD is non-zero if this is the last reload for the insn being
5586 Set reload_reg_rtx[R] to the register allocated.
5588 If NOERROR is nonzero, we return 1 if successful,
5589 or 0 if we couldn't find a spill reg and we didn't change anything. */
5592 allocate_reload_reg (chain
, r
, last_reload
, noerror
)
5593 struct insn_chain
*chain
;
5598 rtx insn
= chain
->insn
;
5605 /* If we put this reload ahead, thinking it is a group,
5606 then insist on finding a group. Otherwise we can grab a
5607 reg that some other reload needs.
5608 (That can happen when we have a 68000 DATA_OR_FP_REG
5609 which is a group of data regs or one fp reg.)
5610 We need not be so restrictive if there are no more reloads
5613 ??? Really it would be nicer to have smarter handling
5614 for that kind of reg class, where a problem like this is normal.
5615 Perhaps those classes should be avoided for reloading
5616 by use of more alternatives. */
5618 int force_group
= reload_nregs
[r
] > 1 && ! last_reload
;
5620 /* If we want a single register and haven't yet found one,
5621 take any reg in the right class and not in use.
5622 If we want a consecutive group, here is where we look for it.
5624 We use two passes so we can first look for reload regs to
5625 reuse, which are already in use for other reloads in this insn,
5626 and only then use additional registers.
5627 I think that maximizing reuse is needed to make sure we don't
5628 run out of reload regs. Suppose we have three reloads, and
5629 reloads A and B can share regs. These need two regs.
5630 Suppose A and B are given different regs.
5631 That leaves none for C. */
5632 for (pass
= 0; pass
< 2; pass
++)
5634 /* I is the index in spill_regs.
5635 We advance it round-robin between insns to use all spill regs
5636 equally, so that inherited reloads have a chance
5637 of leapfrogging each other. Don't do this, however, when we have
5638 group needs and failure would be fatal; if we only have a relatively
5639 small number of spill registers, and more than one of them has
5640 group needs, then by starting in the middle, we may end up
5641 allocating the first one in such a way that we are not left with
5642 sufficient groups to handle the rest. */
5644 if (noerror
|| ! force_group
)
5649 for (count
= 0; count
< n_spills
; count
++)
5651 int class = (int) reload_reg_class
[r
];
5653 i
= (i
+ 1) % n_spills
;
5655 if ((reload_reg_free_p (spill_regs
[i
], reload_opnum
[r
],
5656 reload_when_needed
[r
])
5658 /* We check reload_reg_used to make sure we
5659 don't clobber the return register. */
5660 && ! TEST_HARD_REG_BIT (reload_reg_used
, spill_regs
[i
])
5661 && reload_reg_free_for_value_p (spill_regs
[i
],
5663 reload_when_needed
[r
],
5666 && TEST_HARD_REG_BIT (reg_class_contents
[class], spill_regs
[i
])
5667 && HARD_REGNO_MODE_OK (spill_regs
[i
], reload_mode
[r
])
5668 /* Look first for regs to share, then for unshared. But
5669 don't share regs used for inherited reloads; they are
5670 the ones we want to preserve. */
5672 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5674 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5677 int nr
= HARD_REGNO_NREGS (spill_regs
[i
], reload_mode
[r
]);
5678 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5679 (on 68000) got us two FP regs. If NR is 1,
5680 we would reject both of them. */
5682 nr
= CLASS_MAX_NREGS (reload_reg_class
[r
], reload_mode
[r
]);
5683 /* If we need only one reg, we have already won. */
5686 /* But reject a single reg if we demand a group. */
5691 /* Otherwise check that as many consecutive regs as we need
5693 Also, don't use for a group registers that are
5694 needed for nongroups. */
5695 if (! TEST_HARD_REG_BIT (counted_for_nongroups
, spill_regs
[i
]))
5698 regno
= spill_regs
[i
] + nr
- 1;
5699 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5700 && spill_reg_order
[regno
] >= 0
5701 && reload_reg_free_p (regno
, reload_opnum
[r
],
5702 reload_when_needed
[r
])
5703 && ! TEST_HARD_REG_BIT (counted_for_nongroups
,
5713 /* If we found something on pass 1, omit pass 2. */
5714 if (count
< n_spills
)
5718 /* We should have found a spill register by now. */
5719 if (count
== n_spills
)
5726 /* I is the index in SPILL_REG_RTX of the reload register we are to
5727 allocate. Get an rtx for it and find its register number. */
5729 new = spill_reg_rtx
[i
];
5731 if (new == 0 || GET_MODE (new) != reload_mode
[r
])
5732 spill_reg_rtx
[i
] = new
5733 = gen_rtx_REG (reload_mode
[r
], spill_regs
[i
]);
5735 regno
= true_regnum (new);
5737 /* Detect when the reload reg can't hold the reload mode.
5738 This used to be one `if', but Sequent compiler can't handle that. */
5739 if (HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
5741 enum machine_mode test_mode
= VOIDmode
;
5743 test_mode
= GET_MODE (reload_in
[r
]);
5744 /* If reload_in[r] has VOIDmode, it means we will load it
5745 in whatever mode the reload reg has: to wit, reload_mode[r].
5746 We have already tested that for validity. */
5747 /* Aside from that, we need to test that the expressions
5748 to reload from or into have modes which are valid for this
5749 reload register. Otherwise the reload insns would be invalid. */
5750 if (! (reload_in
[r
] != 0 && test_mode
!= VOIDmode
5751 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5752 if (! (reload_out
[r
] != 0
5753 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (reload_out
[r
]))))
5755 /* The reg is OK. */
5758 /* Mark as in use for this insn the reload regs we use
5760 mark_reload_reg_in_use (spill_regs
[i
], reload_opnum
[r
],
5761 reload_when_needed
[r
], reload_mode
[r
]);
5763 reload_reg_rtx
[r
] = new;
5764 reload_spill_index
[r
] = spill_regs
[i
];
5769 /* The reg is not OK. */
5774 if (asm_noperands (PATTERN (insn
)) < 0)
5775 /* It's the compiler's fault. */
5776 fatal_insn ("Could not find a spill register", insn
);
5778 /* It's the user's fault; the operand's mode and constraint
5779 don't match. Disable this reload so we don't crash in final. */
5780 error_for_asm (insn
,
5781 "`asm' operand constraint incompatible with operand size");
5784 reload_reg_rtx
[r
] = 0;
5785 reload_optional
[r
] = 1;
5786 reload_secondary_p
[r
] = 1;
5791 /* Assign hard reg targets for the pseudo-registers we must reload
5792 into hard regs for this insn.
5793 Also output the instructions to copy them in and out of the hard regs.
5795 For machines with register classes, we are responsible for
5796 finding a reload reg in the proper class. */
5799 choose_reload_regs (chain
, avoid_return_reg
)
5800 struct insn_chain
*chain
;
5801 rtx avoid_return_reg
;
5803 rtx insn
= chain
->insn
;
5805 int max_group_size
= 1;
5806 enum reg_class group_class
= NO_REGS
;
5810 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5811 char save_reload_inherited
[MAX_RELOADS
];
5812 rtx save_reload_inheritance_insn
[MAX_RELOADS
];
5813 rtx save_reload_override_in
[MAX_RELOADS
];
5814 int save_reload_spill_index
[MAX_RELOADS
];
5815 HARD_REG_SET save_reload_reg_used
;
5816 HARD_REG_SET save_reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5817 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5818 HARD_REG_SET save_reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5819 HARD_REG_SET save_reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5820 HARD_REG_SET save_reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5821 HARD_REG_SET save_reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5822 HARD_REG_SET save_reload_reg_used_in_op_addr
;
5823 HARD_REG_SET save_reload_reg_used_in_op_addr_reload
;
5824 HARD_REG_SET save_reload_reg_used_in_insn
;
5825 HARD_REG_SET save_reload_reg_used_in_other_addr
;
5826 HARD_REG_SET save_reload_reg_used_at_all
;
5828 bzero (reload_inherited
, MAX_RELOADS
);
5829 bzero ((char *) reload_inheritance_insn
, MAX_RELOADS
* sizeof (rtx
));
5830 bzero ((char *) reload_override_in
, MAX_RELOADS
* sizeof (rtx
));
5832 CLEAR_HARD_REG_SET (reload_reg_used
);
5833 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5834 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5835 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5836 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5837 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5839 CLEAR_HARD_REG_SET (reg_used_by_pseudo
);
5840 compute_use_by_pseudos (®_used_by_pseudo
, chain
->live_before
);
5841 compute_use_by_pseudos (®_used_by_pseudo
, chain
->live_after
);
5843 for (i
= 0; i
< reload_n_operands
; i
++)
5845 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5846 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5847 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5848 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5849 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5850 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5853 /* Don't bother with avoiding the return reg
5854 if we have no mandatory reload that could use it. */
5855 if (SMALL_REGISTER_CLASSES
&& avoid_return_reg
)
5858 int regno
= REGNO (avoid_return_reg
);
5860 = HARD_REGNO_NREGS (regno
, GET_MODE (avoid_return_reg
));
5863 for (r
= regno
; r
< regno
+ nregs
; r
++)
5864 if (spill_reg_order
[r
] >= 0)
5865 for (j
= 0; j
< n_reloads
; j
++)
5866 if (!reload_optional
[j
] && reload_reg_rtx
[j
] == 0
5867 && (reload_in
[j
] != 0 || reload_out
[j
] != 0
5868 || reload_secondary_p
[j
])
5870 TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[j
]], r
))
5873 avoid_return_reg
= 0;
5876 #if 0 /* Not needed, now that we can always retry without inheritance. */
5877 /* See if we have more mandatory reloads than spill regs.
5878 If so, then we cannot risk optimizations that could prevent
5879 reloads from sharing one spill register.
5881 Since we will try finding a better register than reload_reg_rtx
5882 unless it is equal to reload_in or reload_out, count such reloads. */
5885 int tem
= SMALL_REGISTER_CLASSES
? (avoid_return_reg
!= 0): 0;
5886 for (j
= 0; j
< n_reloads
; j
++)
5887 if (! reload_optional
[j
]
5888 && (reload_in
[j
] != 0 || reload_out
[j
] != 0 || reload_secondary_p
[j
])
5889 && (reload_reg_rtx
[j
] == 0
5890 || (! rtx_equal_p (reload_reg_rtx
[j
], reload_in
[j
])
5891 && ! rtx_equal_p (reload_reg_rtx
[j
], reload_out
[j
]))))
5898 /* Don't use the subroutine call return reg for a reload
5899 if we are supposed to avoid it. */
5900 if (SMALL_REGISTER_CLASSES
&& avoid_return_reg
)
5902 int regno
= REGNO (avoid_return_reg
);
5904 = HARD_REGNO_NREGS (regno
, GET_MODE (avoid_return_reg
));
5907 for (r
= regno
; r
< regno
+ nregs
; r
++)
5908 if (spill_reg_order
[r
] >= 0)
5909 SET_HARD_REG_BIT (reload_reg_used
, r
);
5912 /* In order to be certain of getting the registers we need,
5913 we must sort the reloads into order of increasing register class.
5914 Then our grabbing of reload registers will parallel the process
5915 that provided the reload registers.
5917 Also note whether any of the reloads wants a consecutive group of regs.
5918 If so, record the maximum size of the group desired and what
5919 register class contains all the groups needed by this insn. */
5921 for (j
= 0; j
< n_reloads
; j
++)
5923 reload_order
[j
] = j
;
5924 reload_spill_index
[j
] = -1;
5927 = (reload_inmode
[j
] == VOIDmode
5928 || (GET_MODE_SIZE (reload_outmode
[j
])
5929 > GET_MODE_SIZE (reload_inmode
[j
])))
5930 ? reload_outmode
[j
] : reload_inmode
[j
];
5932 reload_nregs
[j
] = CLASS_MAX_NREGS (reload_reg_class
[j
], reload_mode
[j
]);
5934 if (reload_nregs
[j
] > 1)
5936 max_group_size
= MAX (reload_nregs
[j
], max_group_size
);
5937 group_class
= reg_class_superunion
[(int)reload_reg_class
[j
]][(int)group_class
];
5940 /* If we have already decided to use a certain register,
5941 don't use it in another way. */
5942 if (reload_reg_rtx
[j
])
5943 mark_reload_reg_in_use (REGNO (reload_reg_rtx
[j
]), reload_opnum
[j
],
5944 reload_when_needed
[j
], reload_mode
[j
]);
5948 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5950 bcopy ((char *) reload_reg_rtx
, (char *) save_reload_reg_rtx
,
5951 sizeof reload_reg_rtx
);
5952 bcopy (reload_inherited
, save_reload_inherited
, sizeof reload_inherited
);
5953 bcopy ((char *) reload_inheritance_insn
,
5954 (char *) save_reload_inheritance_insn
,
5955 sizeof reload_inheritance_insn
);
5956 bcopy ((char *) reload_override_in
, (char *) save_reload_override_in
,
5957 sizeof reload_override_in
);
5958 bcopy ((char *) reload_spill_index
, (char *) save_reload_spill_index
,
5959 sizeof reload_spill_index
);
5960 COPY_HARD_REG_SET (save_reload_reg_used
, reload_reg_used
);
5961 COPY_HARD_REG_SET (save_reload_reg_used_at_all
, reload_reg_used_at_all
);
5962 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr
,
5963 reload_reg_used_in_op_addr
);
5965 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload
,
5966 reload_reg_used_in_op_addr_reload
);
5968 COPY_HARD_REG_SET (save_reload_reg_used_in_insn
,
5969 reload_reg_used_in_insn
);
5970 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr
,
5971 reload_reg_used_in_other_addr
);
5973 for (i
= 0; i
< reload_n_operands
; i
++)
5975 COPY_HARD_REG_SET (save_reload_reg_used_in_output
[i
],
5976 reload_reg_used_in_output
[i
]);
5977 COPY_HARD_REG_SET (save_reload_reg_used_in_input
[i
],
5978 reload_reg_used_in_input
[i
]);
5979 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr
[i
],
5980 reload_reg_used_in_input_addr
[i
]);
5981 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr
[i
],
5982 reload_reg_used_in_inpaddr_addr
[i
]);
5983 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr
[i
],
5984 reload_reg_used_in_output_addr
[i
]);
5985 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr
[i
],
5986 reload_reg_used_in_outaddr_addr
[i
]);
5989 /* If -O, try first with inheritance, then turning it off.
5990 If not -O, don't do inheritance.
5991 Using inheritance when not optimizing leads to paradoxes
5992 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5993 because one side of the comparison might be inherited. */
5995 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5997 /* Process the reloads in order of preference just found.
5998 Beyond this point, subregs can be found in reload_reg_rtx.
6000 This used to look for an existing reloaded home for all
6001 of the reloads, and only then perform any new reloads.
6002 But that could lose if the reloads were done out of reg-class order
6003 because a later reload with a looser constraint might have an old
6004 home in a register needed by an earlier reload with a tighter constraint.
6006 To solve this, we make two passes over the reloads, in the order
6007 described above. In the first pass we try to inherit a reload
6008 from a previous insn. If there is a later reload that needs a
6009 class that is a proper subset of the class being processed, we must
6010 also allocate a spill register during the first pass.
6012 Then make a second pass over the reloads to allocate any reloads
6013 that haven't been given registers yet. */
6015 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6017 for (j
= 0; j
< n_reloads
; j
++)
6019 register int r
= reload_order
[j
];
6021 /* Ignore reloads that got marked inoperative. */
6022 if (reload_out
[r
] == 0 && reload_in
[r
] == 0
6023 && ! reload_secondary_p
[r
])
6026 /* If find_reloads chose to use reload_in or reload_out as a reload
6027 register, we don't need to chose one. Otherwise, try even if it
6028 found one since we might save an insn if we find the value lying
6030 Try also when reload_in is a pseudo without a hard reg. */
6031 if (reload_in
[r
] != 0 && reload_reg_rtx
[r
] != 0
6032 && (rtx_equal_p (reload_in
[r
], reload_reg_rtx
[r
])
6033 || (rtx_equal_p (reload_out
[r
], reload_reg_rtx
[r
])
6034 && GET_CODE (reload_in
[r
]) != MEM
6035 && true_regnum (reload_in
[r
]) < FIRST_PSEUDO_REGISTER
)))
6038 #if 0 /* No longer needed for correct operation.
6039 It might give better code, or might not; worth an experiment? */
6040 /* If this is an optional reload, we can't inherit from earlier insns
6041 until we are sure that any non-optional reloads have been allocated.
6042 The following code takes advantage of the fact that optional reloads
6043 are at the end of reload_order. */
6044 if (reload_optional
[r
] != 0)
6045 for (i
= 0; i
< j
; i
++)
6046 if ((reload_out
[reload_order
[i
]] != 0
6047 || reload_in
[reload_order
[i
]] != 0
6048 || reload_secondary_p
[reload_order
[i
]])
6049 && ! reload_optional
[reload_order
[i
]]
6050 && reload_reg_rtx
[reload_order
[i
]] == 0)
6051 allocate_reload_reg (chain
, reload_order
[i
], 0, inheritance
);
6054 /* First see if this pseudo is already available as reloaded
6055 for a previous insn. We cannot try to inherit for reloads
6056 that are smaller than the maximum number of registers needed
6057 for groups unless the register we would allocate cannot be used
6060 We could check here to see if this is a secondary reload for
6061 an object that is already in a register of the desired class.
6062 This would avoid the need for the secondary reload register.
6063 But this is complex because we can't easily determine what
6064 objects might want to be loaded via this reload. So let a
6065 register be allocated here. In `emit_reload_insns' we suppress
6066 one of the loads in the case described above. */
6071 register int regno
= -1;
6072 enum machine_mode mode
;
6074 if (reload_in
[r
] == 0)
6076 else if (GET_CODE (reload_in
[r
]) == REG
)
6078 regno
= REGNO (reload_in
[r
]);
6079 mode
= GET_MODE (reload_in
[r
]);
6081 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
6083 regno
= REGNO (reload_in_reg
[r
]);
6084 mode
= GET_MODE (reload_in_reg
[r
]);
6086 else if (GET_CODE (reload_in_reg
[r
]) == SUBREG
6087 && GET_CODE (SUBREG_REG (reload_in_reg
[r
])) == REG
)
6089 word
= SUBREG_WORD (reload_in_reg
[r
]);
6090 regno
= REGNO (SUBREG_REG (reload_in_reg
[r
]));
6091 if (regno
< FIRST_PSEUDO_REGISTER
)
6093 mode
= GET_MODE (reload_in_reg
[r
]);
6096 else if ((GET_CODE (reload_in_reg
[r
]) == PRE_INC
6097 || GET_CODE (reload_in_reg
[r
]) == PRE_DEC
6098 || GET_CODE (reload_in_reg
[r
]) == POST_INC
6099 || GET_CODE (reload_in_reg
[r
]) == POST_DEC
)
6100 && GET_CODE (XEXP (reload_in_reg
[r
], 0)) == REG
)
6102 regno
= REGNO (XEXP (reload_in_reg
[r
], 0));
6103 mode
= GET_MODE (XEXP (reload_in_reg
[r
], 0));
6104 reload_out
[r
] = reload_in
[r
];
6108 /* This won't work, since REGNO can be a pseudo reg number.
6109 Also, it takes much more hair to keep track of all the things
6110 that can invalidate an inherited reload of part of a pseudoreg. */
6111 else if (GET_CODE (reload_in
[r
]) == SUBREG
6112 && GET_CODE (SUBREG_REG (reload_in
[r
])) == REG
)
6113 regno
= REGNO (SUBREG_REG (reload_in
[r
])) + SUBREG_WORD (reload_in
[r
]);
6116 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
6118 enum reg_class
class = reload_reg_class
[r
], last_class
;
6119 rtx last_reg
= reg_last_reload_reg
[regno
];
6121 i
= REGNO (last_reg
) + word
;
6122 last_class
= REGNO_REG_CLASS (i
);
6123 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
6124 >= GET_MODE_SIZE (mode
) + word
* UNITS_PER_WORD
)
6125 && reg_reloaded_contents
[i
] == regno
6126 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6127 && HARD_REGNO_MODE_OK (i
, reload_mode
[r
])
6128 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
6129 /* Even if we can't use this register as a reload
6130 register, we might use it for reload_override_in,
6131 if copying it to the desired class is cheap
6133 || ((REGISTER_MOVE_COST (last_class
, class)
6134 < MEMORY_MOVE_COST (mode
, class, 1))
6135 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6136 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
6140 #ifdef SECONDARY_MEMORY_NEEDED
6141 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
6146 && (reload_nregs
[r
] == max_group_size
6147 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6149 && ((reload_reg_free_p (i
, reload_opnum
[r
],
6150 reload_when_needed
[r
])
6151 && reload_reg_free_before_p (i
, reload_opnum
[r
],
6152 reload_when_needed
[r
],
6154 || reload_reg_free_for_value_p (i
, reload_opnum
[r
],
6155 reload_when_needed
[r
],
6159 /* If a group is needed, verify that all the subsequent
6160 registers still have their values intact. */
6162 = HARD_REGNO_NREGS (i
, reload_mode
[r
]);
6165 for (k
= 1; k
< nr
; k
++)
6166 if (reg_reloaded_contents
[i
+ k
] != regno
6167 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6174 last_reg
= (GET_MODE (last_reg
) == mode
6175 ? last_reg
: gen_rtx_REG (mode
, i
));
6177 /* We found a register that contains the
6178 value we need. If this register is the
6179 same as an `earlyclobber' operand of the
6180 current insn, just mark it as a place to
6181 reload from since we can't use it as the
6182 reload register itself. */
6184 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6185 if (reg_overlap_mentioned_for_reload_p
6186 (reg_last_reload_reg
[regno
],
6187 reload_earlyclobbers
[i1
]))
6190 if (i1
!= n_earlyclobbers
6191 /* Don't use it if we'd clobber a pseudo reg. */
6192 || (! TEST_HARD_REG_BIT (reg_used_by_pseudo
, i
)
6194 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6195 /* Don't really use the inherited spill reg
6196 if we need it wider than we've got it. */
6197 || (GET_MODE_SIZE (reload_mode
[r
])
6198 > GET_MODE_SIZE (mode
))
6199 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
6202 /* If find_reloads chose reload_out as reload
6203 register, stay with it - that leaves the
6204 inherited register for subsequent reloads. */
6205 || (reload_out
[r
] && reload_reg_rtx
[r
]
6206 && rtx_equal_p (reload_out
[r
],
6207 reload_reg_rtx
[r
])))
6209 reload_override_in
[r
] = last_reg
;
6210 reload_inheritance_insn
[r
]
6211 = reg_reloaded_insn
[i
];
6216 /* We can use this as a reload reg. */
6217 /* Mark the register as in use for this part of
6219 mark_reload_reg_in_use (i
,
6221 reload_when_needed
[r
],
6223 reload_reg_rtx
[r
] = last_reg
;
6224 reload_inherited
[r
] = 1;
6225 reload_inheritance_insn
[r
]
6226 = reg_reloaded_insn
[i
];
6227 reload_spill_index
[r
] = i
;
6228 for (k
= 0; k
< nr
; k
++)
6229 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6237 /* Here's another way to see if the value is already lying around. */
6239 && reload_in
[r
] != 0
6240 && ! reload_inherited
[r
]
6241 && reload_out
[r
] == 0
6242 && (CONSTANT_P (reload_in
[r
])
6243 || GET_CODE (reload_in
[r
]) == PLUS
6244 || GET_CODE (reload_in
[r
]) == REG
6245 || GET_CODE (reload_in
[r
]) == MEM
)
6246 && (reload_nregs
[r
] == max_group_size
6247 || ! reg_classes_intersect_p (reload_reg_class
[r
], group_class
)))
6250 = find_equiv_reg (reload_in
[r
], insn
, reload_reg_class
[r
],
6251 -1, NULL_PTR
, 0, reload_mode
[r
]);
6256 if (GET_CODE (equiv
) == REG
)
6257 regno
= REGNO (equiv
);
6258 else if (GET_CODE (equiv
) == SUBREG
)
6260 /* This must be a SUBREG of a hard register.
6261 Make a new REG since this might be used in an
6262 address and not all machines support SUBREGs
6264 regno
= REGNO (SUBREG_REG (equiv
)) + SUBREG_WORD (equiv
);
6265 equiv
= gen_rtx_REG (reload_mode
[r
], regno
);
6271 /* If we found a spill reg, reject it unless it is free
6272 and of the desired class. */
6274 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
)
6275 && ! reload_reg_free_for_value_p (regno
, reload_opnum
[r
],
6276 reload_when_needed
[r
],
6279 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
6283 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
6286 /* We found a register that contains the value we need.
6287 If this register is the same as an `earlyclobber' operand
6288 of the current insn, just mark it as a place to reload from
6289 since we can't use it as the reload register itself. */
6292 for (i
= 0; i
< n_earlyclobbers
; i
++)
6293 if (reg_overlap_mentioned_for_reload_p (equiv
,
6294 reload_earlyclobbers
[i
]))
6296 reload_override_in
[r
] = equiv
;
6301 /* If the equiv register we have found is explicitly clobbered
6302 in the current insn, it depends on the reload type if we
6303 can use it, use it for reload_override_in, or not at all.
6304 In particular, we then can't use EQUIV for a
6305 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6307 if (equiv
!= 0 && regno_clobbered_p (regno
, insn
))
6309 switch (reload_when_needed
[r
])
6311 case RELOAD_FOR_OTHER_ADDRESS
:
6312 case RELOAD_FOR_INPADDR_ADDRESS
:
6313 case RELOAD_FOR_INPUT_ADDRESS
:
6314 case RELOAD_FOR_OPADDR_ADDR
:
6317 case RELOAD_FOR_INPUT
:
6318 case RELOAD_FOR_OPERAND_ADDRESS
:
6319 reload_override_in
[r
] = equiv
;
6327 /* If we found an equivalent reg, say no code need be generated
6328 to load it, and use it as our reload reg. */
6329 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
6331 int nr
= HARD_REGNO_NREGS (regno
, reload_mode
[r
]);
6333 reload_reg_rtx
[r
] = equiv
;
6334 reload_inherited
[r
] = 1;
6336 /* If reg_reloaded_valid is not set for this register,
6337 there might be a stale spill_reg_store lying around.
6338 We must clear it, since otherwise emit_reload_insns
6339 might delete the store. */
6340 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6341 spill_reg_store
[regno
] = NULL_RTX
;
6342 /* If any of the hard registers in EQUIV are spill
6343 registers, mark them as in use for this insn. */
6344 for (k
= 0; k
< nr
; k
++)
6346 i
= spill_reg_order
[regno
+ k
];
6349 mark_reload_reg_in_use (regno
, reload_opnum
[r
],
6350 reload_when_needed
[r
],
6352 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6359 /* If we found a register to use already, or if this is an optional
6360 reload, we are done. */
6361 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
] != 0)
6364 #if 0 /* No longer needed for correct operation. Might or might not
6365 give better code on the average. Want to experiment? */
6367 /* See if there is a later reload that has a class different from our
6368 class that intersects our class or that requires less register
6369 than our reload. If so, we must allocate a register to this
6370 reload now, since that reload might inherit a previous reload
6371 and take the only available register in our class. Don't do this
6372 for optional reloads since they will force all previous reloads
6373 to be allocated. Also don't do this for reloads that have been
6376 for (i
= j
+ 1; i
< n_reloads
; i
++)
6378 int s
= reload_order
[i
];
6380 if ((reload_in
[s
] == 0 && reload_out
[s
] == 0
6381 && ! reload_secondary_p
[s
])
6382 || reload_optional
[s
])
6385 if ((reload_reg_class
[s
] != reload_reg_class
[r
]
6386 && reg_classes_intersect_p (reload_reg_class
[r
],
6387 reload_reg_class
[s
]))
6388 || reload_nregs
[s
] < reload_nregs
[r
])
6395 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1, inheritance
);
6399 /* Now allocate reload registers for anything non-optional that
6400 didn't get one yet. */
6401 for (j
= 0; j
< n_reloads
; j
++)
6403 register int r
= reload_order
[j
];
6405 /* Ignore reloads that got marked inoperative. */
6406 if (reload_out
[r
] == 0 && reload_in
[r
] == 0 && ! reload_secondary_p
[r
])
6409 /* Skip reloads that already have a register allocated or are
6411 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
])
6414 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1, inheritance
))
6418 /* If that loop got all the way, we have won. */
6425 /* Loop around and try without any inheritance. */
6426 /* First undo everything done by the failed attempt
6427 to allocate with inheritance. */
6428 bcopy ((char *) save_reload_reg_rtx
, (char *) reload_reg_rtx
,
6429 sizeof reload_reg_rtx
);
6430 bcopy ((char *) save_reload_inherited
, (char *) reload_inherited
,
6431 sizeof reload_inherited
);
6432 bcopy ((char *) save_reload_inheritance_insn
,
6433 (char *) reload_inheritance_insn
,
6434 sizeof reload_inheritance_insn
);
6435 bcopy ((char *) save_reload_override_in
, (char *) reload_override_in
,
6436 sizeof reload_override_in
);
6437 bcopy ((char *) save_reload_spill_index
, (char *) reload_spill_index
,
6438 sizeof reload_spill_index
);
6439 COPY_HARD_REG_SET (reload_reg_used
, save_reload_reg_used
);
6440 COPY_HARD_REG_SET (reload_reg_used_at_all
, save_reload_reg_used_at_all
);
6441 COPY_HARD_REG_SET (reload_reg_used_in_op_addr
,
6442 save_reload_reg_used_in_op_addr
);
6443 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload
,
6444 save_reload_reg_used_in_op_addr_reload
);
6445 COPY_HARD_REG_SET (reload_reg_used_in_insn
,
6446 save_reload_reg_used_in_insn
);
6447 COPY_HARD_REG_SET (reload_reg_used_in_other_addr
,
6448 save_reload_reg_used_in_other_addr
);
6450 for (i
= 0; i
< reload_n_operands
; i
++)
6452 COPY_HARD_REG_SET (reload_reg_used_in_input
[i
],
6453 save_reload_reg_used_in_input
[i
]);
6454 COPY_HARD_REG_SET (reload_reg_used_in_output
[i
],
6455 save_reload_reg_used_in_output
[i
]);
6456 COPY_HARD_REG_SET (reload_reg_used_in_input_addr
[i
],
6457 save_reload_reg_used_in_input_addr
[i
]);
6458 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
],
6459 save_reload_reg_used_in_inpaddr_addr
[i
]);
6460 COPY_HARD_REG_SET (reload_reg_used_in_output_addr
[i
],
6461 save_reload_reg_used_in_output_addr
[i
]);
6462 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
],
6463 save_reload_reg_used_in_outaddr_addr
[i
]);
6467 /* If we thought we could inherit a reload, because it seemed that
6468 nothing else wanted the same reload register earlier in the insn,
6469 verify that assumption, now that all reloads have been assigned.
6470 Likewise for reloads where reload_override_in has been set. */
6472 /* If doing expensive optimizations, do one preliminary pass that doesn't
6473 cancel any inheritance, but removes reloads that have been needed only
6474 for reloads that we know can be inherited. */
6475 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6477 for (j
= 0; j
< n_reloads
; j
++)
6479 register int r
= reload_order
[j
];
6482 if (reload_inherited
[r
] && reload_reg_rtx
[r
])
6483 check_reg
= reload_reg_rtx
[r
];
6484 else if (reload_override_in
[r
]
6485 && (GET_CODE (reload_override_in
[r
]) == REG
6486 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6487 check_reg
= reload_override_in
[r
];
6490 if (! (reload_reg_free_before_p (true_regnum (check_reg
),
6491 reload_opnum
[r
], reload_when_needed
[r
],
6492 ! reload_inherited
[r
])
6493 || reload_reg_free_for_value_p (true_regnum (check_reg
),
6495 reload_when_needed
[r
],
6501 reload_inherited
[r
] = 0;
6502 reload_override_in
[r
] = 0;
6504 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6505 reload_override_in, then we do not need its related
6506 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6507 likewise for other reload types.
6508 We handle this by removing a reload when its only replacement
6509 is mentioned in reload_in of the reload we are going to inherit.
6510 A special case are auto_inc expressions; even if the input is
6511 inherited, we still need the address for the output. We can
6512 recognize them because they have RELOAD_OUT set but not
6514 If we suceeded removing some reload and we are doing a preliminary
6515 pass just to remove such reloads, make another pass, since the
6516 removal of one reload might allow us to inherit another one. */
6517 else if ((! reload_out
[r
] || reload_out_reg
[r
])
6518 && remove_address_replacements (reload_in
[r
]) && pass
)
6523 /* Now that reload_override_in is known valid,
6524 actually override reload_in. */
6525 for (j
= 0; j
< n_reloads
; j
++)
6526 if (reload_override_in
[j
])
6527 reload_in
[j
] = reload_override_in
[j
];
6529 /* If this reload won't be done because it has been cancelled or is
6530 optional and not inherited, clear reload_reg_rtx so other
6531 routines (such as subst_reloads) don't get confused. */
6532 for (j
= 0; j
< n_reloads
; j
++)
6533 if (reload_reg_rtx
[j
] != 0
6534 && ((reload_optional
[j
] && ! reload_inherited
[j
])
6535 || (reload_in
[j
] == 0 && reload_out
[j
] == 0
6536 && ! reload_secondary_p
[j
])))
6538 int regno
= true_regnum (reload_reg_rtx
[j
]);
6540 if (spill_reg_order
[regno
] >= 0)
6541 clear_reload_reg_in_use (regno
, reload_opnum
[j
],
6542 reload_when_needed
[j
], reload_mode
[j
]);
6543 reload_reg_rtx
[j
] = 0;
6546 /* Record which pseudos and which spill regs have output reloads. */
6547 for (j
= 0; j
< n_reloads
; j
++)
6549 register int r
= reload_order
[j
];
6551 i
= reload_spill_index
[r
];
6553 /* I is nonneg if this reload uses a register.
6554 If reload_reg_rtx[r] is 0, this is an optional reload
6555 that we opted to ignore. */
6556 if (reload_out_reg
[r
] != 0 && GET_CODE (reload_out_reg
[r
]) == REG
6557 && reload_reg_rtx
[r
] != 0)
6559 register int nregno
= REGNO (reload_out_reg
[r
]);
6562 if (nregno
< FIRST_PSEUDO_REGISTER
)
6563 nr
= HARD_REGNO_NREGS (nregno
, reload_mode
[r
]);
6566 reg_has_output_reload
[nregno
+ nr
] = 1;
6570 nr
= HARD_REGNO_NREGS (i
, reload_mode
[r
]);
6572 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6575 if (reload_when_needed
[r
] != RELOAD_OTHER
6576 && reload_when_needed
[r
] != RELOAD_FOR_OUTPUT
6577 && reload_when_needed
[r
] != RELOAD_FOR_INSN
)
6583 /* Deallocate the reload register for reload R. This is called from
6584 remove_address_replacements. */
6586 deallocate_reload_reg (r
)
6591 if (! reload_reg_rtx
[r
])
6593 regno
= true_regnum (reload_reg_rtx
[r
]);
6594 reload_reg_rtx
[r
] = 0;
6595 if (spill_reg_order
[regno
] >= 0)
6596 clear_reload_reg_in_use (regno
, reload_opnum
[r
], reload_when_needed
[r
],
6598 reload_spill_index
[r
] = -1;
6601 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6602 reloads of the same item for fear that we might not have enough reload
6603 registers. However, normally they will get the same reload register
6604 and hence actually need not be loaded twice.
6606 Here we check for the most common case of this phenomenon: when we have
6607 a number of reloads for the same object, each of which were allocated
6608 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6609 reload, and is not modified in the insn itself. If we find such,
6610 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6611 This will not increase the number of spill registers needed and will
6612 prevent redundant code. */
6615 merge_assigned_reloads (insn
)
6620 /* Scan all the reloads looking for ones that only load values and
6621 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6622 assigned and not modified by INSN. */
6624 for (i
= 0; i
< n_reloads
; i
++)
6626 int conflicting_input
= 0;
6627 int max_input_address_opnum
= -1;
6628 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6630 if (reload_in
[i
] == 0 || reload_when_needed
[i
] == RELOAD_OTHER
6631 || reload_out
[i
] != 0 || reload_reg_rtx
[i
] == 0
6632 || reg_set_p (reload_reg_rtx
[i
], insn
))
6635 /* Look at all other reloads. Ensure that the only use of this
6636 reload_reg_rtx is in a reload that just loads the same value
6637 as we do. Note that any secondary reloads must be of the identical
6638 class since the values, modes, and result registers are the
6639 same, so we need not do anything with any secondary reloads. */
6641 for (j
= 0; j
< n_reloads
; j
++)
6643 if (i
== j
|| reload_reg_rtx
[j
] == 0
6644 || ! reg_overlap_mentioned_p (reload_reg_rtx
[j
],
6648 if (reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6649 && reload_opnum
[j
] > max_input_address_opnum
)
6650 max_input_address_opnum
= reload_opnum
[j
];
6652 /* If the reload regs aren't exactly the same (e.g, different modes)
6653 or if the values are different, we can't merge this reload.
6654 But if it is an input reload, we might still merge
6655 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6657 if (! rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6658 || reload_out
[j
] != 0 || reload_in
[j
] == 0
6659 || ! rtx_equal_p (reload_in
[i
], reload_in
[j
]))
6661 if (reload_when_needed
[j
] != RELOAD_FOR_INPUT
6662 || ((reload_when_needed
[i
] != RELOAD_FOR_INPUT_ADDRESS
6663 || reload_opnum
[i
] > reload_opnum
[j
])
6664 && reload_when_needed
[i
] != RELOAD_FOR_OTHER_ADDRESS
))
6666 conflicting_input
= 1;
6667 if (min_conflicting_input_opnum
> reload_opnum
[j
])
6668 min_conflicting_input_opnum
= reload_opnum
[j
];
6672 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6673 we, in fact, found any matching reloads. */
6676 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6678 for (j
= 0; j
< n_reloads
; j
++)
6679 if (i
!= j
&& reload_reg_rtx
[j
] != 0
6680 && rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6681 && (! conflicting_input
6682 || reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6683 || reload_when_needed
[j
] == RELOAD_FOR_OTHER_ADDRESS
))
6685 reload_when_needed
[i
] = RELOAD_OTHER
;
6687 reload_spill_index
[j
] = -1;
6688 transfer_replacements (i
, j
);
6691 /* If this is now RELOAD_OTHER, look for any reloads that load
6692 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6693 if they were for inputs, RELOAD_OTHER for outputs. Note that
6694 this test is equivalent to looking for reloads for this operand
6697 if (reload_when_needed
[i
] == RELOAD_OTHER
)
6698 for (j
= 0; j
< n_reloads
; j
++)
6699 if (reload_in
[j
] != 0
6700 && reload_when_needed
[i
] != RELOAD_OTHER
6701 && reg_overlap_mentioned_for_reload_p (reload_in
[j
],
6703 reload_when_needed
[j
]
6704 = ((reload_when_needed
[i
] == RELOAD_FOR_INPUT_ADDRESS
6705 || reload_when_needed
[i
] == RELOAD_FOR_INPADDR_ADDRESS
)
6706 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6712 /* Output insns to reload values in and out of the chosen reload regs. */
6715 emit_reload_insns (chain
)
6716 struct insn_chain
*chain
;
6718 rtx insn
= chain
->insn
;
6721 rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6722 rtx other_input_address_reload_insns
= 0;
6723 rtx other_input_reload_insns
= 0;
6724 rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6725 rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6726 rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6727 rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6728 rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6729 rtx operand_reload_insns
= 0;
6730 rtx other_operand_reload_insns
= 0;
6731 rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6732 rtx following_insn
= NEXT_INSN (insn
);
6733 rtx before_insn
= PREV_INSN (insn
);
6735 /* Values to be put in spill_reg_store are put here first. */
6736 rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6737 HARD_REG_SET reg_reloaded_died
;
6739 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6741 for (j
= 0; j
< reload_n_operands
; j
++)
6742 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6743 = inpaddr_address_reload_insns
[j
]
6744 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6745 = outaddr_address_reload_insns
[j
]
6746 = other_output_reload_insns
[j
] = 0;
6748 /* Now output the instructions to copy the data into and out of the
6749 reload registers. Do these in the order that the reloads were reported,
6750 since reloads of base and index registers precede reloads of operands
6751 and the operands may need the base and index registers reloaded. */
6753 for (j
= 0; j
< n_reloads
; j
++)
6756 rtx oldequiv_reg
= 0;
6757 rtx this_reload_insn
= 0;
6758 int expect_occurrences
= 1;
6760 if (reload_reg_rtx
[j
]
6761 && REGNO (reload_reg_rtx
[j
]) < FIRST_PSEUDO_REGISTER
)
6762 new_spill_reg_store
[REGNO (reload_reg_rtx
[j
])] = 0;
6764 old
= (reload_in
[j
] && GET_CODE (reload_in
[j
]) == MEM
6765 ? reload_in_reg
[j
] : reload_in
[j
]);
6768 /* AUTO_INC reloads need to be handled even if inherited. We got an
6769 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6770 && (! reload_inherited
[j
] || (reload_out
[j
] && ! reload_out_reg
[j
]))
6771 && ! rtx_equal_p (reload_reg_rtx
[j
], old
)
6772 && reload_reg_rtx
[j
] != 0)
6774 register rtx reloadreg
= reload_reg_rtx
[j
];
6776 enum machine_mode mode
;
6779 /* Determine the mode to reload in.
6780 This is very tricky because we have three to choose from.
6781 There is the mode the insn operand wants (reload_inmode[J]).
6782 There is the mode of the reload register RELOADREG.
6783 There is the intrinsic mode of the operand, which we could find
6784 by stripping some SUBREGs.
6785 It turns out that RELOADREG's mode is irrelevant:
6786 we can change that arbitrarily.
6788 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6789 then the reload reg may not support QImode moves, so use SImode.
6790 If foo is in memory due to spilling a pseudo reg, this is safe,
6791 because the QImode value is in the least significant part of a
6792 slot big enough for a SImode. If foo is some other sort of
6793 memory reference, then it is impossible to reload this case,
6794 so previous passes had better make sure this never happens.
6796 Then consider a one-word union which has SImode and one of its
6797 members is a float, being fetched as (SUBREG:SF union:SI).
6798 We must fetch that as SFmode because we could be loading into
6799 a float-only register. In this case OLD's mode is correct.
6801 Consider an immediate integer: it has VOIDmode. Here we need
6802 to get a mode from something else.
6804 In some cases, there is a fourth mode, the operand's
6805 containing mode. If the insn specifies a containing mode for
6806 this operand, it overrides all others.
6808 I am not sure whether the algorithm here is always right,
6809 but it does the right things in those cases. */
6811 mode
= GET_MODE (old
);
6812 if (mode
== VOIDmode
)
6813 mode
= reload_inmode
[j
];
6815 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6816 /* If we need a secondary register for this operation, see if
6817 the value is already in a register in that class. Don't
6818 do this if the secondary register will be used as a scratch
6821 if (reload_secondary_in_reload
[j
] >= 0
6822 && reload_secondary_in_icode
[j
] == CODE_FOR_nothing
6825 = find_equiv_reg (old
, insn
,
6826 reload_reg_class
[reload_secondary_in_reload
[j
]],
6827 -1, NULL_PTR
, 0, mode
);
6830 /* If reloading from memory, see if there is a register
6831 that already holds the same value. If so, reload from there.
6832 We can pass 0 as the reload_reg_p argument because
6833 any other reload has either already been emitted,
6834 in which case find_equiv_reg will see the reload-insn,
6835 or has yet to be emitted, in which case it doesn't matter
6836 because we will use this equiv reg right away. */
6838 if (oldequiv
== 0 && optimize
6839 && (GET_CODE (old
) == MEM
6840 || (GET_CODE (old
) == REG
6841 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6842 && reg_renumber
[REGNO (old
)] < 0)))
6843 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
,
6844 -1, NULL_PTR
, 0, mode
);
6848 int regno
= true_regnum (oldequiv
);
6850 /* If OLDEQUIV is a spill register, don't use it for this
6851 if any other reload needs it at an earlier stage of this insn
6852 or at this stage. */
6853 if (spill_reg_order
[regno
] >= 0
6854 && (! reload_reg_free_p (regno
, reload_opnum
[j
],
6855 reload_when_needed
[j
])
6856 || ! reload_reg_free_before_p (regno
, reload_opnum
[j
],
6857 reload_when_needed
[j
], 1)))
6860 /* If OLDEQUIV is not a spill register,
6861 don't use it if any other reload wants it. */
6862 if (spill_reg_order
[regno
] < 0)
6865 for (k
= 0; k
< n_reloads
; k
++)
6866 if (reload_reg_rtx
[k
] != 0 && k
!= j
6867 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx
[k
],
6875 /* If it is no cheaper to copy from OLDEQUIV into the
6876 reload register than it would be to move from memory,
6877 don't use it. Likewise, if we need a secondary register
6881 && ((REGNO_REG_CLASS (regno
) != reload_reg_class
[j
]
6882 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno
),
6883 reload_reg_class
[j
])
6884 >= MEMORY_MOVE_COST (mode
, reload_reg_class
[j
], 1)))
6885 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6886 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
6890 #ifdef SECONDARY_MEMORY_NEEDED
6891 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6892 reload_reg_class
[j
],
6899 /* delete_output_reload is only invoked properly if old contains
6900 the original pseudo register. Since this is replaced with a
6901 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6902 find the pseudo in RELOAD_IN_REG. */
6904 && reload_override_in
[j
]
6905 && GET_CODE (reload_in_reg
[j
]) == REG
)
6908 old
= reload_in_reg
[j
];
6912 else if (GET_CODE (oldequiv
) == REG
)
6913 oldequiv_reg
= oldequiv
;
6914 else if (GET_CODE (oldequiv
) == SUBREG
)
6915 oldequiv_reg
= SUBREG_REG (oldequiv
);
6917 /* If we are reloading from a register that was recently stored in
6918 with an output-reload, see if we can prove there was
6919 actually no need to store the old value in it. */
6921 if (optimize
&& GET_CODE (oldequiv
) == REG
6922 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6923 && spill_reg_store
[REGNO (oldequiv
)]
6924 && GET_CODE (old
) == REG
6925 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6926 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6927 reload_out_reg
[j
])))
6928 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6930 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6931 then load RELOADREG from OLDEQUIV. Note that we cannot use
6932 gen_lowpart_common since it can do the wrong thing when
6933 RELOADREG has a multi-word mode. Note that RELOADREG
6934 must always be a REG here. */
6936 if (GET_MODE (reloadreg
) != mode
)
6937 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6938 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6939 oldequiv
= SUBREG_REG (oldequiv
);
6940 if (GET_MODE (oldequiv
) != VOIDmode
6941 && mode
!= GET_MODE (oldequiv
))
6942 oldequiv
= gen_rtx_SUBREG (mode
, oldequiv
, 0);
6944 /* Switch to the right place to emit the reload insns. */
6945 switch (reload_when_needed
[j
])
6948 where
= &other_input_reload_insns
;
6950 case RELOAD_FOR_INPUT
:
6951 where
= &input_reload_insns
[reload_opnum
[j
]];
6953 case RELOAD_FOR_INPUT_ADDRESS
:
6954 where
= &input_address_reload_insns
[reload_opnum
[j
]];
6956 case RELOAD_FOR_INPADDR_ADDRESS
:
6957 where
= &inpaddr_address_reload_insns
[reload_opnum
[j
]];
6959 case RELOAD_FOR_OUTPUT_ADDRESS
:
6960 where
= &output_address_reload_insns
[reload_opnum
[j
]];
6962 case RELOAD_FOR_OUTADDR_ADDRESS
:
6963 where
= &outaddr_address_reload_insns
[reload_opnum
[j
]];
6965 case RELOAD_FOR_OPERAND_ADDRESS
:
6966 where
= &operand_reload_insns
;
6968 case RELOAD_FOR_OPADDR_ADDR
:
6969 where
= &other_operand_reload_insns
;
6971 case RELOAD_FOR_OTHER_ADDRESS
:
6972 where
= &other_input_address_reload_insns
;
6978 push_to_sequence (*where
);
6981 /* Auto-increment addresses must be reloaded in a special way. */
6982 if (reload_out
[j
] && ! reload_out_reg
[j
])
6984 /* We are not going to bother supporting the case where a
6985 incremented register can't be copied directly from
6986 OLDEQUIV since this seems highly unlikely. */
6987 if (reload_secondary_in_reload
[j
] >= 0)
6990 if (reload_inherited
[j
])
6991 oldequiv
= reloadreg
;
6993 old
= XEXP (reload_in_reg
[j
], 0);
6995 if (optimize
&& GET_CODE (oldequiv
) == REG
6996 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6997 && spill_reg_store
[REGNO (oldequiv
)]
6998 && GET_CODE (old
) == REG
6999 && (dead_or_set_p (insn
,
7000 spill_reg_stored_to
[REGNO (oldequiv
)])
7001 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7003 delete_output_reload (insn
, j
, REGNO (oldequiv
));
7005 /* Prevent normal processing of this reload. */
7007 /* Output a special code sequence for this case. */
7008 new_spill_reg_store
[REGNO (reloadreg
)]
7009 = inc_for_reload (reloadreg
, oldequiv
, reload_out
[j
],
7013 /* If we are reloading a pseudo-register that was set by the previous
7014 insn, see if we can get rid of that pseudo-register entirely
7015 by redirecting the previous insn into our reload register. */
7017 else if (optimize
&& GET_CODE (old
) == REG
7018 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7019 && dead_or_set_p (insn
, old
)
7020 /* This is unsafe if some other reload
7021 uses the same reg first. */
7022 && reload_reg_free_before_p (REGNO (reloadreg
),
7024 reload_when_needed
[j
], 0))
7026 rtx temp
= PREV_INSN (insn
);
7027 while (temp
&& GET_CODE (temp
) == NOTE
)
7028 temp
= PREV_INSN (temp
);
7030 && GET_CODE (temp
) == INSN
7031 && GET_CODE (PATTERN (temp
)) == SET
7032 && SET_DEST (PATTERN (temp
)) == old
7033 /* Make sure we can access insn_operand_constraint. */
7034 && asm_noperands (PATTERN (temp
)) < 0
7035 /* This is unsafe if prev insn rejects our reload reg. */
7036 && constraint_accepts_reg_p (insn_operand_constraint
[recog_memoized (temp
)][0],
7038 /* This is unsafe if operand occurs more than once in current
7039 insn. Perhaps some occurrences aren't reloaded. */
7040 && count_occurrences (PATTERN (insn
), old
) == 1
7041 /* Don't risk splitting a matching pair of operands. */
7042 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
7044 /* Store into the reload register instead of the pseudo. */
7045 SET_DEST (PATTERN (temp
)) = reloadreg
;
7046 /* If these are the only uses of the pseudo reg,
7047 pretend for GDB it lives in the reload reg we used. */
7048 if (REG_N_DEATHS (REGNO (old
)) == 1
7049 && REG_N_SETS (REGNO (old
)) == 1)
7051 reg_renumber
[REGNO (old
)] = REGNO (reload_reg_rtx
[j
]);
7052 alter_reg (REGNO (old
), -1);
7058 /* We can't do that, so output an insn to load RELOADREG. */
7062 #ifdef SECONDARY_INPUT_RELOAD_CLASS
7063 rtx second_reload_reg
= 0;
7064 enum insn_code icode
;
7066 /* If we have a secondary reload, pick up the secondary register
7067 and icode, if any. If OLDEQUIV and OLD are different or
7068 if this is an in-out reload, recompute whether or not we
7069 still need a secondary register and what the icode should
7070 be. If we still need a secondary register and the class or
7071 icode is different, go back to reloading from OLD if using
7072 OLDEQUIV means that we got the wrong type of register. We
7073 cannot have different class or icode due to an in-out reload
7074 because we don't make such reloads when both the input and
7075 output need secondary reload registers. */
7077 if (reload_secondary_in_reload
[j
] >= 0)
7079 int secondary_reload
= reload_secondary_in_reload
[j
];
7080 rtx real_oldequiv
= oldequiv
;
7083 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7084 and similarly for OLD.
7085 See comments in get_secondary_reload in reload.c. */
7086 /* If it is a pseudo that cannot be replaced with its
7087 equivalent MEM, we must fall back to reload_in, which
7088 will have all the necessary substitutions registered. */
7090 if (GET_CODE (oldequiv
) == REG
7091 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7092 && reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0)
7094 if (reg_equiv_address
[REGNO (oldequiv
)]
7095 || num_not_at_initial_offset
)
7096 real_oldequiv
= reload_in
[j
];
7098 real_oldequiv
= reg_equiv_mem
[REGNO (oldequiv
)];
7101 if (GET_CODE (old
) == REG
7102 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7103 && reg_equiv_memory_loc
[REGNO (old
)] != 0)
7105 if (reg_equiv_address
[REGNO (old
)]
7106 || num_not_at_initial_offset
)
7107 real_old
= reload_in
[j
];
7109 real_old
= reg_equiv_mem
[REGNO (old
)];
7112 second_reload_reg
= reload_reg_rtx
[secondary_reload
];
7113 icode
= reload_secondary_in_icode
[j
];
7115 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7116 || (reload_in
[j
] != 0 && reload_out
[j
] != 0))
7118 enum reg_class new_class
7119 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
7120 mode
, real_oldequiv
);
7122 if (new_class
== NO_REGS
)
7123 second_reload_reg
= 0;
7126 enum insn_code new_icode
;
7127 enum machine_mode new_mode
;
7129 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
7130 REGNO (second_reload_reg
)))
7131 oldequiv
= old
, real_oldequiv
= real_old
;
7134 new_icode
= reload_in_optab
[(int) mode
];
7135 if (new_icode
!= CODE_FOR_nothing
7136 && ((insn_operand_predicate
[(int) new_icode
][0]
7137 && ! ((*insn_operand_predicate
[(int) new_icode
][0])
7139 || (insn_operand_predicate
[(int) new_icode
][1]
7140 && ! ((*insn_operand_predicate
[(int) new_icode
][1])
7141 (real_oldequiv
, mode
)))))
7142 new_icode
= CODE_FOR_nothing
;
7144 if (new_icode
== CODE_FOR_nothing
)
7147 new_mode
= insn_operand_mode
[(int) new_icode
][2];
7149 if (GET_MODE (second_reload_reg
) != new_mode
)
7151 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
7153 oldequiv
= old
, real_oldequiv
= real_old
;
7156 = gen_rtx_REG (new_mode
,
7157 REGNO (second_reload_reg
));
7163 /* If we still need a secondary reload register, check
7164 to see if it is being used as a scratch or intermediate
7165 register and generate code appropriately. If we need
7166 a scratch register, use REAL_OLDEQUIV since the form of
7167 the insn may depend on the actual address if it is
7170 if (second_reload_reg
)
7172 if (icode
!= CODE_FOR_nothing
)
7174 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7175 second_reload_reg
));
7180 /* See if we need a scratch register to load the
7181 intermediate register (a tertiary reload). */
7182 enum insn_code tertiary_icode
7183 = reload_secondary_in_icode
[secondary_reload
];
7185 if (tertiary_icode
!= CODE_FOR_nothing
)
7187 rtx third_reload_reg
7188 = reload_reg_rtx
[reload_secondary_in_reload
[secondary_reload
]];
7190 emit_insn ((GEN_FCN (tertiary_icode
)
7191 (second_reload_reg
, real_oldequiv
,
7192 third_reload_reg
)));
7195 gen_reload (second_reload_reg
, real_oldequiv
,
7197 reload_when_needed
[j
]);
7199 oldequiv
= second_reload_reg
;
7205 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7207 rtx real_oldequiv
= oldequiv
;
7209 if ((GET_CODE (oldequiv
) == REG
7210 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7211 && reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0)
7212 || (GET_CODE (oldequiv
) == SUBREG
7213 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
7214 && (REGNO (SUBREG_REG (oldequiv
))
7215 >= FIRST_PSEUDO_REGISTER
)
7216 && (reg_equiv_memory_loc
7217 [REGNO (SUBREG_REG (oldequiv
))] != 0)))
7218 real_oldequiv
= reload_in
[j
];
7219 gen_reload (reloadreg
, real_oldequiv
, reload_opnum
[j
],
7220 reload_when_needed
[j
]);
7225 this_reload_insn
= get_last_insn ();
7226 /* End this sequence. */
7227 *where
= get_insns ();
7230 /* Update reload_override_in so that delete_address_reloads_1
7231 can see the actual register usage. */
7233 reload_override_in
[j
] = oldequiv
;
7236 /* When inheriting a wider reload, we have a MEM in reload_in[j],
7237 e.g. inheriting a SImode output reload for
7238 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7239 if (optimize
&& reload_inherited
[j
] && reload_in
[j
]
7240 && GET_CODE (reload_in
[j
]) == MEM
7241 && GET_CODE (reload_in_reg
[j
]) == MEM
7242 && reload_spill_index
[j
] >= 0
7243 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7246 = count_occurrences (PATTERN (insn
), reload_in
[j
]) == 1 ? 0 : -1;
7248 = regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7251 /* If we are reloading a register that was recently stored in with an
7252 output-reload, see if we can prove there was
7253 actually no need to store the old value in it. */
7256 && (reload_inherited
[j
] || reload_override_in
[j
])
7257 && reload_reg_rtx
[j
]
7258 && GET_CODE (reload_reg_rtx
[j
]) == REG
7259 && spill_reg_store
[REGNO (reload_reg_rtx
[j
])] != 0
7261 /* There doesn't seem to be any reason to restrict this to pseudos
7262 and doing so loses in the case where we are copying from a
7263 register of the wrong class. */
7264 && REGNO (spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])])
7265 >= FIRST_PSEUDO_REGISTER
7267 /* The insn might have already some references to stackslots
7268 replaced by MEMs, while reload_out_reg still names the
7270 && (dead_or_set_p (insn
,
7271 spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])])
7272 || rtx_equal_p (spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])],
7273 reload_out_reg
[j
])))
7274 delete_output_reload (insn
, j
, REGNO (reload_reg_rtx
[j
]));
7276 /* Input-reloading is done. Now do output-reloading,
7277 storing the value from the reload-register after the main insn
7278 if reload_out[j] is nonzero.
7280 ??? At some point we need to support handling output reloads of
7281 JUMP_INSNs or insns that set cc0. */
7283 /* If this is an output reload that stores something that is
7284 not loaded in this same reload, see if we can eliminate a previous
7287 rtx pseudo
= reload_out_reg
[j
];
7290 && GET_CODE (pseudo
) == REG
7291 && ! rtx_equal_p (reload_in_reg
[j
], pseudo
)
7292 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7293 && reg_last_reload_reg
[REGNO (pseudo
)])
7295 int pseudo_no
= REGNO (pseudo
);
7296 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7298 /* We don't need to test full validity of last_regno for
7299 inherit here; we only want to know if the store actually
7300 matches the pseudo. */
7301 if (reg_reloaded_contents
[last_regno
] == pseudo_no
7302 && spill_reg_store
[last_regno
]
7303 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7304 delete_output_reload (insn
, j
, last_regno
);
7308 old
= reload_out_reg
[j
];
7310 && reload_reg_rtx
[j
] != old
7311 && reload_reg_rtx
[j
] != 0)
7313 register rtx reloadreg
= reload_reg_rtx
[j
];
7314 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7315 register rtx second_reloadreg
= 0;
7318 enum machine_mode mode
;
7321 /* An output operand that dies right away does need a reload,
7322 but need not be copied from it. Show the new location in the
7324 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
7325 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7327 XEXP (note
, 0) = reload_reg_rtx
[j
];
7330 /* Likewise for a SUBREG of an operand that dies. */
7331 else if (GET_CODE (old
) == SUBREG
7332 && GET_CODE (SUBREG_REG (old
)) == REG
7333 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7336 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
7340 else if (GET_CODE (old
) == SCRATCH
)
7341 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7342 but we don't want to make an output reload. */
7346 /* Strip off of OLD any size-increasing SUBREGs such as
7347 (SUBREG:SI foo:QI 0). */
7349 while (GET_CODE (old
) == SUBREG
&& SUBREG_WORD (old
) == 0
7350 && (GET_MODE_SIZE (GET_MODE (old
))
7351 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old
)))))
7352 old
= SUBREG_REG (old
);
7355 /* If is a JUMP_INSN, we can't support output reloads yet. */
7356 if (GET_CODE (insn
) == JUMP_INSN
)
7359 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7362 push_to_sequence (output_reload_insns
[reload_opnum
[j
]]);
7364 old
= reload_out
[j
];
7366 /* Determine the mode to reload in.
7367 See comments above (for input reloading). */
7369 mode
= GET_MODE (old
);
7370 if (mode
== VOIDmode
)
7372 /* VOIDmode should never happen for an output. */
7373 if (asm_noperands (PATTERN (insn
)) < 0)
7374 /* It's the compiler's fault. */
7375 fatal_insn ("VOIDmode on an output", insn
);
7376 error_for_asm (insn
, "output operand is constant in `asm'");
7377 /* Prevent crash--use something we know is valid. */
7379 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7382 if (GET_MODE (reloadreg
) != mode
)
7383 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7385 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7387 /* If we need two reload regs, set RELOADREG to the intermediate
7388 one, since it will be stored into OLD. We might need a secondary
7389 register only for an input reload, so check again here. */
7391 if (reload_secondary_out_reload
[j
] >= 0)
7395 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
7396 && reg_equiv_mem
[REGNO (old
)] != 0)
7397 real_old
= reg_equiv_mem
[REGNO (old
)];
7399 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class
[j
],
7403 second_reloadreg
= reloadreg
;
7404 reloadreg
= reload_reg_rtx
[reload_secondary_out_reload
[j
]];
7406 /* See if RELOADREG is to be used as a scratch register
7407 or as an intermediate register. */
7408 if (reload_secondary_out_icode
[j
] != CODE_FOR_nothing
)
7410 emit_insn ((GEN_FCN (reload_secondary_out_icode
[j
])
7411 (real_old
, second_reloadreg
, reloadreg
)));
7416 /* See if we need both a scratch and intermediate reload
7419 int secondary_reload
= reload_secondary_out_reload
[j
];
7420 enum insn_code tertiary_icode
7421 = reload_secondary_out_icode
[secondary_reload
];
7423 if (GET_MODE (reloadreg
) != mode
)
7424 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7426 if (tertiary_icode
!= CODE_FOR_nothing
)
7429 = reload_reg_rtx
[reload_secondary_out_reload
[secondary_reload
]];
7432 /* Copy primary reload reg to secondary reload reg.
7433 (Note that these have been swapped above, then
7434 secondary reload reg to OLD using our insn. */
7436 /* If REAL_OLD is a paradoxical SUBREG, remove it
7437 and try to put the opposite SUBREG on
7439 if (GET_CODE (real_old
) == SUBREG
7440 && (GET_MODE_SIZE (GET_MODE (real_old
))
7441 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7442 && 0 != (tem
= gen_lowpart_common
7443 (GET_MODE (SUBREG_REG (real_old
)),
7445 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7447 gen_reload (reloadreg
, second_reloadreg
,
7448 reload_opnum
[j
], reload_when_needed
[j
]);
7449 emit_insn ((GEN_FCN (tertiary_icode
)
7450 (real_old
, reloadreg
, third_reloadreg
)));
7455 /* Copy between the reload regs here and then to
7458 gen_reload (reloadreg
, second_reloadreg
,
7459 reload_opnum
[j
], reload_when_needed
[j
]);
7465 /* Output the last reload insn. */
7470 /* Don't output the last reload if OLD is not the dest of
7471 INSN and is in the src and is clobbered by INSN. */
7472 if (! flag_expensive_optimizations
7473 || GET_CODE (old
) != REG
7474 || !(set
= single_set (insn
))
7475 || rtx_equal_p (old
, SET_DEST (set
))
7476 || !reg_mentioned_p (old
, SET_SRC (set
))
7477 || !regno_clobbered_p (REGNO (old
), insn
))
7478 gen_reload (old
, reloadreg
, reload_opnum
[j
],
7479 reload_when_needed
[j
]);
7482 /* Look at all insns we emitted, just to be safe. */
7483 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7484 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
7486 rtx pat
= PATTERN (p
);
7488 /* If this output reload doesn't come from a spill reg,
7489 clear any memory of reloaded copies of the pseudo reg.
7490 If this output reload comes from a spill reg,
7491 reg_has_output_reload will make this do nothing. */
7492 note_stores (pat
, forget_old_reloads_1
);
7494 if (reg_mentioned_p (reload_reg_rtx
[j
], pat
))
7496 rtx set
= single_set (insn
);
7497 if (reload_spill_index
[j
] < 0
7499 && SET_SRC (set
) == reload_reg_rtx
[j
])
7501 int src
= REGNO (SET_SRC (set
));
7503 reload_spill_index
[j
] = src
;
7504 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7505 if (find_regno_note (insn
, REG_DEAD
, src
))
7506 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7508 if (REGNO (reload_reg_rtx
[j
]) < FIRST_PSEUDO_REGISTER
)
7510 int s
= reload_secondary_out_reload
[j
];
7511 set
= single_set (p
);
7512 /* If this reload copies only to the secondary reload
7513 register, the secondary reload does the actual
7515 if (s
>= 0 && set
== NULL_RTX
)
7516 ; /* We can't tell what function the secondary reload
7517 has and where the actual store to the pseudo is
7518 made; leave new_spill_reg_store alone. */
7520 && SET_SRC (set
) == reload_reg_rtx
[j
]
7521 && SET_DEST (set
) == reload_reg_rtx
[s
])
7523 /* Usually the next instruction will be the
7524 secondary reload insn; if we can confirm
7525 that it is, setting new_spill_reg_store to
7526 that insn will allow an extra optimization. */
7527 rtx s_reg
= reload_reg_rtx
[s
];
7528 rtx next
= NEXT_INSN (p
);
7529 reload_out
[s
] = reload_out
[j
];
7530 reload_out_reg
[s
] = reload_out_reg
[j
];
7531 set
= single_set (next
);
7532 if (set
&& SET_SRC (set
) == s_reg
7533 && ! new_spill_reg_store
[REGNO (s_reg
)])
7535 SET_HARD_REG_BIT (reg_is_output_reload
,
7537 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7541 new_spill_reg_store
[REGNO (reload_reg_rtx
[j
])] = p
;
7546 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7548 emit_insns (other_output_reload_insns
[reload_opnum
[j
]]);
7549 other_output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7552 output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7558 /* Now write all the insns we made for reloads in the order expected by
7559 the allocation functions. Prior to the insn being reloaded, we write
7560 the following reloads:
7562 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7564 RELOAD_OTHER reloads.
7566 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7567 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7568 RELOAD_FOR_INPUT reload for the operand.
7570 RELOAD_FOR_OPADDR_ADDRS reloads.
7572 RELOAD_FOR_OPERAND_ADDRESS reloads.
7574 After the insn being reloaded, we write the following:
7576 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7577 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7578 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7579 reloads for the operand. The RELOAD_OTHER output reloads are
7580 output in descending order by reload number. */
7582 emit_insns_before (other_input_address_reload_insns
, insn
);
7583 emit_insns_before (other_input_reload_insns
, insn
);
7585 for (j
= 0; j
< reload_n_operands
; j
++)
7587 emit_insns_before (inpaddr_address_reload_insns
[j
], insn
);
7588 emit_insns_before (input_address_reload_insns
[j
], insn
);
7589 emit_insns_before (input_reload_insns
[j
], insn
);
7592 emit_insns_before (other_operand_reload_insns
, insn
);
7593 emit_insns_before (operand_reload_insns
, insn
);
7595 for (j
= 0; j
< reload_n_operands
; j
++)
7597 emit_insns_before (outaddr_address_reload_insns
[j
], following_insn
);
7598 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
7599 emit_insns_before (output_reload_insns
[j
], following_insn
);
7600 emit_insns_before (other_output_reload_insns
[j
], following_insn
);
7603 /* Keep basic block info up to date. */
7606 if (basic_block_head
[chain
->block
] == insn
)
7607 basic_block_head
[chain
->block
] = NEXT_INSN (before_insn
);
7608 if (basic_block_end
[chain
->block
] == insn
)
7609 basic_block_end
[chain
->block
] = PREV_INSN (following_insn
);
7612 /* For all the spill regs newly reloaded in this instruction,
7613 record what they were reloaded from, so subsequent instructions
7614 can inherit the reloads.
7616 Update spill_reg_store for the reloads of this insn.
7617 Copy the elements that were updated in the loop above. */
7619 for (j
= 0; j
< n_reloads
; j
++)
7621 register int r
= reload_order
[j
];
7622 register int i
= reload_spill_index
[r
];
7624 /* I is nonneg if this reload used a register.
7625 If reload_reg_rtx[r] is 0, this is an optional reload
7626 that we opted to ignore. */
7628 if (i
>= 0 && reload_reg_rtx
[r
] != 0)
7631 = HARD_REGNO_NREGS (i
, GET_MODE (reload_reg_rtx
[r
]));
7633 int part_reaches_end
= 0;
7634 int all_reaches_end
= 1;
7636 /* For a multi register reload, we need to check if all or part
7637 of the value lives to the end. */
7638 for (k
= 0; k
< nr
; k
++)
7640 if (reload_reg_reaches_end_p (i
+ k
, reload_opnum
[r
],
7641 reload_when_needed
[r
]))
7642 part_reaches_end
= 1;
7644 all_reaches_end
= 0;
7647 /* Ignore reloads that don't reach the end of the insn in
7649 if (all_reaches_end
)
7651 /* First, clear out memory of what used to be in this spill reg.
7652 If consecutive registers are used, clear them all. */
7654 for (k
= 0; k
< nr
; k
++)
7655 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7657 /* Maybe the spill reg contains a copy of reload_out. */
7658 if (reload_out
[r
] != 0
7659 && (GET_CODE (reload_out
[r
]) == REG
7661 || ! reload_out_reg
[r
]
7663 || GET_CODE (reload_out_reg
[r
]) == REG
))
7665 rtx out
= (GET_CODE (reload_out
[r
]) == REG
7669 /* AUTO_INC */ : XEXP (reload_in_reg
[r
], 0));
7670 register int nregno
= REGNO (out
);
7671 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7672 : HARD_REGNO_NREGS (nregno
,
7673 GET_MODE (reload_reg_rtx
[r
])));
7675 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7676 spill_reg_stored_to
[i
] = out
;
7677 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7679 /* If NREGNO is a hard register, it may occupy more than
7680 one register. If it does, say what is in the
7681 rest of the registers assuming that both registers
7682 agree on how many words the object takes. If not,
7683 invalidate the subsequent registers. */
7685 if (nregno
< FIRST_PSEUDO_REGISTER
)
7686 for (k
= 1; k
< nnr
; k
++)
7687 reg_last_reload_reg
[nregno
+ k
]
7689 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7690 REGNO (reload_reg_rtx
[r
]) + k
)
7693 /* Now do the inverse operation. */
7694 for (k
= 0; k
< nr
; k
++)
7696 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7697 reg_reloaded_contents
[i
+ k
]
7698 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7701 reg_reloaded_insn
[i
+ k
] = insn
;
7702 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7706 /* Maybe the spill reg contains a copy of reload_in. Only do
7707 something if there will not be an output reload for
7708 the register being reloaded. */
7709 else if (reload_out_reg
[r
] == 0
7710 && reload_in
[r
] != 0
7711 && ((GET_CODE (reload_in
[r
]) == REG
7712 && REGNO (reload_in
[r
]) >= FIRST_PSEUDO_REGISTER
7713 && ! reg_has_output_reload
[REGNO (reload_in
[r
])])
7714 || (GET_CODE (reload_in_reg
[r
]) == REG
7715 && ! reg_has_output_reload
[REGNO (reload_in_reg
[r
])]))
7716 && ! reg_set_p (reload_reg_rtx
[r
], PATTERN (insn
)))
7718 register int nregno
;
7721 if (GET_CODE (reload_in
[r
]) == REG
7722 && REGNO (reload_in
[r
]) >= FIRST_PSEUDO_REGISTER
)
7723 nregno
= REGNO (reload_in
[r
]);
7724 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
7725 nregno
= REGNO (reload_in_reg
[r
]);
7727 nregno
= REGNO (XEXP (reload_in_reg
[r
], 0));
7729 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7730 : HARD_REGNO_NREGS (nregno
,
7731 GET_MODE (reload_reg_rtx
[r
])));
7733 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7735 if (nregno
< FIRST_PSEUDO_REGISTER
)
7736 for (k
= 1; k
< nnr
; k
++)
7737 reg_last_reload_reg
[nregno
+ k
]
7739 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7740 REGNO (reload_reg_rtx
[r
]) + k
)
7743 /* Unless we inherited this reload, show we haven't
7744 recently done a store.
7745 Previous stores of inherited auto_inc expressions
7746 also have to be discarded. */
7747 if (! reload_inherited
[r
]
7748 || (reload_out
[r
] && ! reload_out_reg
[r
]))
7749 spill_reg_store
[i
] = 0;
7751 for (k
= 0; k
< nr
; k
++)
7753 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7754 reg_reloaded_contents
[i
+ k
]
7755 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7758 reg_reloaded_insn
[i
+ k
] = insn
;
7759 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7764 /* However, if part of the reload reaches the end, then we must
7765 invalidate the old info for the part that survives to the end. */
7766 else if (part_reaches_end
)
7768 for (k
= 0; k
< nr
; k
++)
7769 if (reload_reg_reaches_end_p (i
+ k
,
7771 reload_when_needed
[r
]))
7772 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7776 /* The following if-statement was #if 0'd in 1.34 (or before...).
7777 It's reenabled in 1.35 because supposedly nothing else
7778 deals with this problem. */
7780 /* If a register gets output-reloaded from a non-spill register,
7781 that invalidates any previous reloaded copy of it.
7782 But forget_old_reloads_1 won't get to see it, because
7783 it thinks only about the original insn. So invalidate it here. */
7784 if (i
< 0 && reload_out
[r
] != 0
7785 && (GET_CODE (reload_out
[r
]) == REG
7786 || (GET_CODE (reload_out
[r
]) == MEM
7787 && GET_CODE (reload_out_reg
[r
]) == REG
)))
7789 rtx out
= (GET_CODE (reload_out
[r
]) == REG
7790 ? reload_out
[r
] : reload_out_reg
[r
]);
7791 register int nregno
= REGNO (out
);
7792 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7794 rtx src_reg
, store_insn
;
7796 reg_last_reload_reg
[nregno
] = 0;
7798 /* If we can find a hard register that is stored, record
7799 the storing insn so that we may delete this insn with
7800 delete_output_reload. */
7801 src_reg
= reload_reg_rtx
[r
];
7803 /* If this is an optional reload, try to find the source reg
7804 from an input reload. */
7807 rtx set
= single_set (insn
);
7808 if (SET_DEST (set
) == reload_out
[r
])
7812 src_reg
= SET_SRC (set
);
7814 for (k
= 0; k
< n_reloads
; k
++)
7816 if (reload_in
[k
] == src_reg
)
7818 src_reg
= reload_reg_rtx
[k
];
7825 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7826 if (src_reg
&& GET_CODE (src_reg
) == REG
7827 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7829 int src_regno
= REGNO (src_reg
);
7830 int nr
= HARD_REGNO_NREGS (src_regno
, reload_mode
[r
]);
7831 /* The place where to find a death note varies with
7832 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7833 necessarily checked exactly in the code that moves
7834 notes, so just check both locations. */
7835 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7837 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7840 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7841 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7842 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7843 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7844 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7845 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7847 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7849 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7851 reg_last_reload_reg
[nregno
] = src_reg
;
7856 int num_regs
= HARD_REGNO_NREGS (nregno
,GET_MODE (reload_out
[r
]));
7858 while (num_regs
-- > 0)
7859 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7863 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7866 /* Emit code to perform a reload from IN (which may be a reload register) to
7867 OUT (which may also be a reload register). IN or OUT is from operand
7868 OPNUM with reload type TYPE.
7870 Returns first insn emitted. */
7873 gen_reload (out
, in
, opnum
, type
)
7877 enum reload_type type
;
7879 rtx last
= get_last_insn ();
7882 /* If IN is a paradoxical SUBREG, remove it and try to put the
7883 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7884 if (GET_CODE (in
) == SUBREG
7885 && (GET_MODE_SIZE (GET_MODE (in
))
7886 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7887 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7888 in
= SUBREG_REG (in
), out
= tem
;
7889 else if (GET_CODE (out
) == SUBREG
7890 && (GET_MODE_SIZE (GET_MODE (out
))
7891 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7892 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7893 out
= SUBREG_REG (out
), in
= tem
;
7895 /* How to do this reload can get quite tricky. Normally, we are being
7896 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7897 register that didn't get a hard register. In that case we can just
7898 call emit_move_insn.
7900 We can also be asked to reload a PLUS that adds a register or a MEM to
7901 another register, constant or MEM. This can occur during frame pointer
7902 elimination and while reloading addresses. This case is handled by
7903 trying to emit a single insn to perform the add. If it is not valid,
7904 we use a two insn sequence.
7906 Finally, we could be called to handle an 'o' constraint by putting
7907 an address into a register. In that case, we first try to do this
7908 with a named pattern of "reload_load_address". If no such pattern
7909 exists, we just emit a SET insn and hope for the best (it will normally
7910 be valid on machines that use 'o').
7912 This entire process is made complex because reload will never
7913 process the insns we generate here and so we must ensure that
7914 they will fit their constraints and also by the fact that parts of
7915 IN might be being reloaded separately and replaced with spill registers.
7916 Because of this, we are, in some sense, just guessing the right approach
7917 here. The one listed above seems to work.
7919 ??? At some point, this whole thing needs to be rethought. */
7921 if (GET_CODE (in
) == PLUS
7922 && (GET_CODE (XEXP (in
, 0)) == REG
7923 || GET_CODE (XEXP (in
, 0)) == SUBREG
7924 || GET_CODE (XEXP (in
, 0)) == MEM
)
7925 && (GET_CODE (XEXP (in
, 1)) == REG
7926 || GET_CODE (XEXP (in
, 1)) == SUBREG
7927 || CONSTANT_P (XEXP (in
, 1))
7928 || GET_CODE (XEXP (in
, 1)) == MEM
))
7930 /* We need to compute the sum of a register or a MEM and another
7931 register, constant, or MEM, and put it into the reload
7932 register. The best possible way of doing this is if the machine
7933 has a three-operand ADD insn that accepts the required operands.
7935 The simplest approach is to try to generate such an insn and see if it
7936 is recognized and matches its constraints. If so, it can be used.
7938 It might be better not to actually emit the insn unless it is valid,
7939 but we need to pass the insn as an operand to `recog' and
7940 `insn_extract' and it is simpler to emit and then delete the insn if
7941 not valid than to dummy things up. */
7943 rtx op0
, op1
, tem
, insn
;
7946 op0
= find_replacement (&XEXP (in
, 0));
7947 op1
= find_replacement (&XEXP (in
, 1));
7949 /* Since constraint checking is strict, commutativity won't be
7950 checked, so we need to do that here to avoid spurious failure
7951 if the add instruction is two-address and the second operand
7952 of the add is the same as the reload reg, which is frequently
7953 the case. If the insn would be A = B + A, rearrange it so
7954 it will be A = A + B as constrain_operands expects. */
7956 if (GET_CODE (XEXP (in
, 1)) == REG
7957 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7958 tem
= op0
, op0
= op1
, op1
= tem
;
7960 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7961 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7963 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7964 code
= recog_memoized (insn
);
7968 insn_extract (insn
);
7969 /* We want constrain operands to treat this insn strictly in
7970 its validity determination, i.e., the way it would after reload
7972 if (constrain_operands (code
, 1))
7976 delete_insns_since (last
);
7978 /* If that failed, we must use a conservative two-insn sequence.
7979 use move to copy constant, MEM, or pseudo register to the reload
7980 register since "move" will be able to handle an arbitrary operand,
7981 unlike add which can't, in general. Then add the registers.
7983 If there is another way to do this for a specific machine, a
7984 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7987 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7988 || (GET_CODE (op1
) == REG
7989 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
))
7990 tem
= op0
, op0
= op1
, op1
= tem
;
7992 gen_reload (out
, op0
, opnum
, type
);
7994 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7995 This fixes a problem on the 32K where the stack pointer cannot
7996 be used as an operand of an add insn. */
7998 if (rtx_equal_p (op0
, op1
))
8001 insn
= emit_insn (gen_add2_insn (out
, op1
));
8003 /* If that failed, copy the address register to the reload register.
8004 Then add the constant to the reload register. */
8006 code
= recog_memoized (insn
);
8010 insn_extract (insn
);
8011 /* We want constrain operands to treat this insn strictly in
8012 its validity determination, i.e., the way it would after reload
8014 if (constrain_operands (code
, 1))
8016 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8018 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
8023 delete_insns_since (last
);
8025 gen_reload (out
, op1
, opnum
, type
);
8026 insn
= emit_insn (gen_add2_insn (out
, op0
));
8027 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
8030 #ifdef SECONDARY_MEMORY_NEEDED
8031 /* If we need a memory location to do the move, do it that way. */
8032 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
8033 && GET_CODE (out
) == REG
&& REGNO (out
) < FIRST_PSEUDO_REGISTER
8034 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
8035 REGNO_REG_CLASS (REGNO (out
)),
8038 /* Get the memory to use and rewrite both registers to its mode. */
8039 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8041 if (GET_MODE (loc
) != GET_MODE (out
))
8042 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
8044 if (GET_MODE (loc
) != GET_MODE (in
))
8045 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
8047 gen_reload (loc
, in
, opnum
, type
);
8048 gen_reload (out
, loc
, opnum
, type
);
8052 /* If IN is a simple operand, use gen_move_insn. */
8053 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
8054 emit_insn (gen_move_insn (out
, in
));
8056 #ifdef HAVE_reload_load_address
8057 else if (HAVE_reload_load_address
)
8058 emit_insn (gen_reload_load_address (out
, in
));
8061 /* Otherwise, just write (set OUT IN) and hope for the best. */
8063 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
8065 /* Return the first insn emitted.
8066 We can not just return get_last_insn, because there may have
8067 been multiple instructions emitted. Also note that gen_move_insn may
8068 emit more than one insn itself, so we can not assume that there is one
8069 insn emitted per emit_insn_before call. */
8071 return last
? NEXT_INSN (last
) : get_insns ();
8074 /* Delete a previously made output-reload
8075 whose result we now believe is not needed.
8076 First we double-check.
8078 INSN is the insn now being processed.
8079 LAST_RELOAD_REG is the hard register number for which we want to delete
8080 the last output reload.
8081 J is the reload-number that originally used REG. The caller has made
8082 certain that reload J doesn't use REG any longer for input. */
8085 delete_output_reload (insn
, j
, last_reload_reg
)
8088 int last_reload_reg
;
8090 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
8091 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8094 int n_inherited
= 0;
8098 /* Get the raw pseudo-register referred to. */
8100 while (GET_CODE (reg
) == SUBREG
)
8101 reg
= SUBREG_REG (reg
);
8102 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
8104 /* This is unsafe if the operand occurs more often in the current
8105 insn than it is inherited. */
8106 for (k
= n_reloads
- 1; k
>= 0; k
--)
8108 rtx reg2
= reload_in
[k
];
8111 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
8112 reg2
= reload_in_reg
[k
];
8114 if (reload_out
[k
] && ! reload_out_reg
[k
])
8115 reg2
= XEXP (reload_in_reg
[k
], 0);
8117 while (GET_CODE (reg2
) == SUBREG
)
8118 reg2
= SUBREG_REG (reg2
);
8119 if (rtx_equal_p (reg2
, reg
))
8120 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8123 reg2
= reload_out_reg
[k
];
8126 while (GET_CODE (reg2
) == SUBREG
)
8127 reg2
= XEXP (reg2
, 0);
8128 if (rtx_equal_p (reg2
, reg
))
8134 n_occurrences
= count_occurrences (PATTERN (insn
), reg
);
8136 n_occurrences
+= count_occurrences (PATTERN (insn
), substed
);
8137 if (n_occurrences
> n_inherited
)
8140 /* If the pseudo-reg we are reloading is no longer referenced
8141 anywhere between the store into it and here,
8142 and no jumps or labels intervene, then the value can get
8143 here through the reload reg alone.
8144 Otherwise, give up--return. */
8145 for (i1
= NEXT_INSN (output_reload_insn
);
8146 i1
!= insn
; i1
= NEXT_INSN (i1
))
8148 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
8150 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
8151 && reg_mentioned_p (reg
, PATTERN (i1
)))
8153 /* If this is USE in front of INSN, we only have to check that
8154 there are no more references than accounted for by inheritance. */
8155 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
8157 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8158 i1
= NEXT_INSN (i1
);
8160 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8166 /* The caller has already checked that REG dies or is set in INSN.
8167 It has also checked that we are optimizing, and thus some inaccurancies
8168 in the debugging information are acceptable.
8169 So we could just delete output_reload_insn.
8170 But in some cases we can improve the debugging information without
8171 sacrificing optimization - maybe even improving the code:
8172 See if the pseudo reg has been completely replaced
8173 with reload regs. If so, delete the store insn
8174 and forget we had a stack slot for the pseudo. */
8175 if (reload_out
[j
] != reload_in
[j
]
8176 && REG_N_DEATHS (REGNO (reg
)) == 1
8177 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
8178 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8182 /* We know that it was used only between here
8183 and the beginning of the current basic block.
8184 (We also know that the last use before INSN was
8185 the output reload we are thinking of deleting, but never mind that.)
8186 Search that range; see if any ref remains. */
8187 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8189 rtx set
= single_set (i2
);
8191 /* Uses which just store in the pseudo don't count,
8192 since if they are the only uses, they are dead. */
8193 if (set
!= 0 && SET_DEST (set
) == reg
)
8195 if (GET_CODE (i2
) == CODE_LABEL
8196 || GET_CODE (i2
) == JUMP_INSN
)
8198 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
8199 && reg_mentioned_p (reg
, PATTERN (i2
)))
8201 /* Some other ref remains; just delete the output reload we
8203 delete_address_reloads (output_reload_insn
, insn
);
8204 PUT_CODE (output_reload_insn
, NOTE
);
8205 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
8206 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
8211 /* Delete the now-dead stores into this pseudo. */
8212 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8214 rtx set
= single_set (i2
);
8216 if (set
!= 0 && SET_DEST (set
) == reg
)
8218 delete_address_reloads (i2
, insn
);
8219 /* This might be a basic block head,
8220 thus don't use delete_insn. */
8221 PUT_CODE (i2
, NOTE
);
8222 NOTE_SOURCE_FILE (i2
) = 0;
8223 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
8225 if (GET_CODE (i2
) == CODE_LABEL
8226 || GET_CODE (i2
) == JUMP_INSN
)
8230 /* For the debugging info,
8231 say the pseudo lives in this reload reg. */
8232 reg_renumber
[REGNO (reg
)] = REGNO (reload_reg_rtx
[j
]);
8233 alter_reg (REGNO (reg
), -1);
8235 delete_address_reloads (output_reload_insn
, insn
);
8236 PUT_CODE (output_reload_insn
, NOTE
);
8237 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
8238 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
8242 /* We are going to delete DEAD_INSN. Recursively delete loads of
8243 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8244 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8246 delete_address_reloads (dead_insn
, current_insn
)
8247 rtx dead_insn
, current_insn
;
8249 rtx set
= single_set (dead_insn
);
8250 rtx set2
, dst
, prev
, next
;
8253 rtx dst
= SET_DEST (set
);
8254 if (GET_CODE (dst
) == MEM
)
8255 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8257 /* If we deleted the store from a reloaded post_{in,de}c expression,
8258 we can delete the matching adds. */
8259 prev
= PREV_INSN (dead_insn
);
8260 next
= NEXT_INSN (dead_insn
);
8261 if (! prev
|| ! next
)
8263 set
= single_set (next
);
8264 set2
= single_set (prev
);
8266 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8267 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
8268 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
8270 dst
= SET_DEST (set
);
8271 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8272 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8273 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8274 || (INTVAL (XEXP (SET_SRC (set
), 1))
8275 != - INTVAL (XEXP (SET_SRC (set2
), 1))))
8281 /* Subfunction of delete_address_reloads: process registers found in X. */
8283 delete_address_reloads_1 (dead_insn
, x
, current_insn
)
8284 rtx dead_insn
, x
, current_insn
;
8286 rtx prev
, set
, dst
, i2
;
8288 enum rtx_code code
= GET_CODE (x
);
8292 char *fmt
= GET_RTX_FORMAT (code
);
8293 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8296 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8297 else if (fmt
[i
] == 'E')
8299 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
8300 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8307 if (spill_reg_order
[REGNO (x
)] < 0)
8310 /* Scan backwards for the insn that sets x. This might be a way back due
8312 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8314 code
= GET_CODE (prev
);
8315 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8317 if (GET_RTX_CLASS (code
) != 'i')
8319 if (reg_set_p (x
, PATTERN (prev
)))
8321 if (reg_referenced_p (x
, PATTERN (prev
)))
8324 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8326 /* Check that PREV only sets the reload register. */
8327 set
= single_set (prev
);
8330 dst
= SET_DEST (set
);
8331 if (GET_CODE (dst
) != REG
8332 || ! rtx_equal_p (dst
, x
))
8334 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8336 /* Check if DST was used in a later insn -
8337 it might have been inherited. */
8338 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8340 if (GET_CODE (i2
) == CODE_LABEL
)
8342 if (GET_RTX_CLASS (GET_CODE (i2
)) != 'i')
8344 if (reg_referenced_p (dst
, PATTERN (i2
)))
8346 /* If there is a reference to the register in the current insn,
8347 it might be loaded in a non-inherited reload. If no other
8348 reload uses it, that means the register is set before
8350 if (i2
== current_insn
)
8352 for (j
= n_reloads
- 1; j
>= 0; j
--)
8353 if ((reload_reg_rtx
[j
] == dst
&& reload_inherited
[j
])
8354 || reload_override_in
[j
] == dst
)
8356 for (j
= n_reloads
- 1; j
>= 0; j
--)
8357 if (reload_in
[j
] && reload_reg_rtx
[j
] == dst
)
8364 if (GET_CODE (i2
) == JUMP_INSN
)
8366 if (reg_set_p (dst
, PATTERN (i2
)))
8368 /* If DST is still live at CURRENT_INSN, check if it is used for
8370 if (i2
== current_insn
)
8372 for (j
= n_reloads
- 1; j
>= 0; j
--)
8373 if ((reload_reg_rtx
[j
] == dst
&& reload_inherited
[j
])
8374 || reload_override_in
[j
] == dst
)
8376 /* ??? We can't finish the loop here, because dst might be
8377 allocated to a pseudo in this block if no reload in this
8378 block needs any of the clsses containing DST - see
8379 spill_hard_reg. There is no easy way to tell this, so we
8380 have to scan till the end of the basic block. */
8384 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8385 reg_reloaded_contents
[REGNO (dst
)] = -1;
8386 /* Can't use delete_insn here because PREV might be a basic block head. */
8387 PUT_CODE (prev
, NOTE
);
8388 NOTE_LINE_NUMBER (prev
) = NOTE_INSN_DELETED
;
8389 NOTE_SOURCE_FILE (prev
) = 0;
8392 /* Output reload-insns to reload VALUE into RELOADREG.
8393 VALUE is an autoincrement or autodecrement RTX whose operand
8394 is a register or memory location;
8395 so reloading involves incrementing that location.
8396 IN is either identical to VALUE, or some cheaper place to reload from.
8398 INC_AMOUNT is the number to increment or decrement by (always positive).
8399 This cannot be deduced from VALUE.
8401 Return the instruction that stores into RELOADREG. */
8404 inc_for_reload (reloadreg
, in
, value
, inc_amount
)
8409 /* REG or MEM to be copied and incremented. */
8410 rtx incloc
= XEXP (value
, 0);
8411 /* Nonzero if increment after copying. */
8412 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
8418 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
8420 /* No hard register is equivalent to this register after
8421 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8422 we could inc/dec that register as well (maybe even using it for
8423 the source), but I'm not sure it's worth worrying about. */
8424 if (GET_CODE (incloc
) == REG
)
8425 reg_last_reload_reg
[REGNO (incloc
)] = 0;
8427 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
8428 inc_amount
= - inc_amount
;
8430 inc
= GEN_INT (inc_amount
);
8432 /* If this is post-increment, first copy the location to the reload reg. */
8433 if (post
&& real_in
!= reloadreg
)
8434 emit_insn (gen_move_insn (reloadreg
, real_in
));
8438 /* See if we can directly increment INCLOC. Use a method similar to
8439 that in gen_reload. */
8441 last
= get_last_insn ();
8442 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
8443 gen_rtx_PLUS (GET_MODE (incloc
),
8446 code
= recog_memoized (add_insn
);
8449 insn_extract (add_insn
);
8450 if (constrain_operands (code
, 1))
8452 /* If this is a pre-increment and we have incremented the value
8453 where it lives, copy the incremented value to RELOADREG to
8454 be used as an address. */
8457 emit_insn (gen_move_insn (reloadreg
, incloc
));
8462 delete_insns_since (last
);
8465 /* If couldn't do the increment directly, must increment in RELOADREG.
8466 The way we do this depends on whether this is pre- or post-increment.
8467 For pre-increment, copy INCLOC to the reload register, increment it
8468 there, then save back. */
8472 if (in
!= reloadreg
)
8473 emit_insn (gen_move_insn (reloadreg
, real_in
));
8474 emit_insn (gen_add2_insn (reloadreg
, inc
));
8475 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8480 Because this might be a jump insn or a compare, and because RELOADREG
8481 may not be available after the insn in an input reload, we must do
8482 the incrementation before the insn being reloaded for.
8484 We have already copied IN to RELOADREG. Increment the copy in
8485 RELOADREG, save that back, then decrement RELOADREG so it has
8486 the original value. */
8488 emit_insn (gen_add2_insn (reloadreg
, inc
));
8489 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8490 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
8496 /* Return 1 if we are certain that the constraint-string STRING allows
8497 the hard register REG. Return 0 if we can't be sure of this. */
8500 constraint_accepts_reg_p (string
, reg
)
8505 int regno
= true_regnum (reg
);
8508 /* Initialize for first alternative. */
8510 /* Check that each alternative contains `g' or `r'. */
8512 switch (c
= *string
++)
8515 /* If an alternative lacks `g' or `r', we lose. */
8518 /* If an alternative lacks `g' or `r', we lose. */
8521 /* Initialize for next alternative. */
8526 /* Any general reg wins for this alternative. */
8527 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
8531 /* Any reg in specified class wins for this alternative. */
8533 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
8535 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
8541 /* Return the number of places FIND appears within X, but don't count
8542 an occurrence if some SET_DEST is FIND. */
8545 count_occurrences (x
, find
)
8546 register rtx x
, find
;
8549 register enum rtx_code code
;
8550 register char *format_ptr
;
8558 code
= GET_CODE (x
);
8573 if (GET_CODE (find
) == MEM
&& rtx_equal_p (x
, find
))
8577 if (SET_DEST (x
) == find
)
8578 return count_occurrences (SET_SRC (x
), find
);
8585 format_ptr
= GET_RTX_FORMAT (code
);
8588 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8590 switch (*format_ptr
++)
8593 count
+= count_occurrences (XEXP (x
, i
), find
);
8597 if (XVEC (x
, i
) != NULL
)
8599 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8600 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
);
8608 /* This array holds values which are equivalent to a hard register
8609 during reload_cse_regs. Each array element is an EXPR_LIST of
8610 values. Each time a hard register is set, we set the corresponding
8611 array element to the value. Each time a hard register is copied
8612 into memory, we add the memory location to the corresponding array
8613 element. We don't store values or memory addresses with side
8614 effects in this array.
8616 If the value is a CONST_INT, then the mode of the containing
8617 EXPR_LIST is the mode in which that CONST_INT was referenced.
8619 We sometimes clobber a specific entry in a list. In that case, we
8620 just set XEXP (list-entry, 0) to 0. */
8622 static rtx
*reg_values
;
8624 /* This is a preallocated REG rtx which we use as a temporary in
8625 reload_cse_invalidate_regno, so that we don't need to allocate a
8626 new one each time through a loop in that function. */
8628 static rtx invalidate_regno_rtx
;
8630 /* Invalidate any entries in reg_values which depend on REGNO,
8631 including those for REGNO itself. This is called if REGNO is
8632 changing. If CLOBBER is true, then always forget anything we
8633 currently know about REGNO. MODE is the mode of the assignment to
8634 REGNO, which is used to determine how many hard registers are being
8635 changed. If MODE is VOIDmode, then only REGNO is being changed;
8636 this is used when invalidating call clobbered registers across a
8640 reload_cse_invalidate_regno (regno
, mode
, clobber
)
8642 enum machine_mode mode
;
8648 /* Our callers don't always go through true_regnum; we may see a
8649 pseudo-register here from a CLOBBER or the like. We probably
8650 won't ever see a pseudo-register that has a real register number,
8651 for we check anyhow for safety. */
8652 if (regno
>= FIRST_PSEUDO_REGISTER
)
8653 regno
= reg_renumber
[regno
];
8657 if (mode
== VOIDmode
)
8658 endregno
= regno
+ 1;
8660 endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
8663 for (i
= regno
; i
< endregno
; i
++)
8666 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8670 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8672 if (XEXP (x
, 0) != 0
8673 && refers_to_regno_p (regno
, endregno
, XEXP (x
, 0), NULL_PTR
))
8675 /* If this is the only entry on the list, clear
8676 reg_values[i]. Otherwise, just clear this entry on
8678 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8688 /* We must look at earlier registers, in case REGNO is part of a
8689 multi word value but is not the first register. If an earlier
8690 register has a value in a mode which overlaps REGNO, then we must
8691 invalidate that earlier register. Note that we do not need to
8692 check REGNO or later registers (we must not check REGNO itself,
8693 because we would incorrectly conclude that there was a conflict). */
8695 for (i
= 0; i
< regno
; i
++)
8699 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8701 if (XEXP (x
, 0) != 0)
8703 PUT_MODE (invalidate_regno_rtx
, GET_MODE (x
));
8704 REGNO (invalidate_regno_rtx
) = i
;
8705 if (refers_to_regno_p (regno
, endregno
, invalidate_regno_rtx
,
8708 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8716 /* The memory at address MEM_BASE is being changed.
8717 Return whether this change will invalidate VAL. */
8720 reload_cse_mem_conflict_p (mem_base
, val
)
8728 code
= GET_CODE (val
);
8731 /* Get rid of a few simple cases quickly. */
8744 if (GET_MODE (mem_base
) == BLKmode
8745 || GET_MODE (val
) == BLKmode
)
8747 if (anti_dependence (val
, mem_base
))
8749 /* The address may contain nested MEMs. */
8756 fmt
= GET_RTX_FORMAT (code
);
8758 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8762 if (reload_cse_mem_conflict_p (mem_base
, XEXP (val
, i
)))
8765 else if (fmt
[i
] == 'E')
8769 for (j
= 0; j
< XVECLEN (val
, i
); j
++)
8770 if (reload_cse_mem_conflict_p (mem_base
, XVECEXP (val
, i
, j
)))
8778 /* Invalidate any entries in reg_values which are changed because of a
8779 store to MEM_RTX. If this is called because of a non-const call
8780 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8783 reload_cse_invalidate_mem (mem_rtx
)
8788 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8792 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8794 if (XEXP (x
, 0) != 0
8795 && reload_cse_mem_conflict_p (mem_rtx
, XEXP (x
, 0)))
8797 /* If this is the only entry on the list, clear
8798 reg_values[i]. Otherwise, just clear this entry on
8800 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8811 /* Invalidate DEST, which is being assigned to or clobbered. The
8812 second parameter exists so that this function can be passed to
8813 note_stores; it is ignored. */
8816 reload_cse_invalidate_rtx (dest
, ignore
)
8818 rtx ignore ATTRIBUTE_UNUSED
;
8820 while (GET_CODE (dest
) == STRICT_LOW_PART
8821 || GET_CODE (dest
) == SIGN_EXTRACT
8822 || GET_CODE (dest
) == ZERO_EXTRACT
8823 || GET_CODE (dest
) == SUBREG
)
8824 dest
= XEXP (dest
, 0);
8826 if (GET_CODE (dest
) == REG
)
8827 reload_cse_invalidate_regno (REGNO (dest
), GET_MODE (dest
), 1);
8828 else if (GET_CODE (dest
) == MEM
)
8829 reload_cse_invalidate_mem (dest
);
8832 /* Do a very simple CSE pass over the hard registers.
8834 This function detects no-op moves where we happened to assign two
8835 different pseudo-registers to the same hard register, and then
8836 copied one to the other. Reload will generate a useless
8837 instruction copying a register to itself.
8839 This function also detects cases where we load a value from memory
8840 into two different registers, and (if memory is more expensive than
8841 registers) changes it to simply copy the first register into the
8844 Another optimization is performed that scans the operands of each
8845 instruction to see whether the value is already available in a
8846 hard register. It then replaces the operand with the hard register
8847 if possible, much like an optional reload would. */
8850 reload_cse_regs_1 (first
)
8858 init_alias_analysis ();
8860 reg_values
= (rtx
*) alloca (FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8861 bzero ((char *)reg_values
, FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8863 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8864 free them when we are done. */
8865 push_obstacks (&reload_obstack
, &reload_obstack
);
8866 firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
8868 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8869 memory for a non-const call instruction. */
8870 callmem
= gen_rtx_MEM (BLKmode
, const0_rtx
);
8872 /* This is used in reload_cse_invalidate_regno to avoid consing a
8873 new REG in a loop in that function. */
8874 invalidate_regno_rtx
= gen_rtx_REG (VOIDmode
, 0);
8876 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8880 if (GET_CODE (insn
) == CODE_LABEL
)
8882 /* Forget all the register values at a code label. We don't
8883 try to do anything clever around jumps. */
8884 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8890 #ifdef NON_SAVING_SETJMP
8891 if (NON_SAVING_SETJMP
&& GET_CODE (insn
) == NOTE
8892 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
8894 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8901 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8904 /* If this is a call instruction, forget anything stored in a
8905 call clobbered register, or, if this is not a const call, in
8907 if (GET_CODE (insn
) == CALL_INSN
)
8909 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8910 if (call_used_regs
[i
])
8911 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8913 if (! CONST_CALL_P (insn
))
8914 reload_cse_invalidate_mem (callmem
);
8917 body
= PATTERN (insn
);
8918 if (GET_CODE (body
) == SET
)
8921 if (reload_cse_noop_set_p (body
, insn
))
8923 /* If this sets the return value of the function, we must keep
8924 a USE around, in case this is in a different basic block
8925 than the final USE. Otherwise, we could loose important
8926 register lifeness information on SMALL_REGISTER_CLASSES
8927 machines, where return registers might be used as spills:
8928 subsequent passes assume that spill registers are dead at
8929 the end of a basic block. */
8930 if (REG_FUNCTION_VALUE_P (SET_DEST (body
)))
8933 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, SET_DEST (body
));
8934 INSN_CODE (insn
) = -1;
8935 REG_NOTES (insn
) = NULL_RTX
;
8936 push_obstacks (&reload_obstack
, &reload_obstack
);
8940 PUT_CODE (insn
, NOTE
);
8941 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8942 NOTE_SOURCE_FILE (insn
) = 0;
8945 /* We're done with this insn. */
8949 /* It's not a no-op, but we can try to simplify it. */
8950 count
+= reload_cse_simplify_set (body
, insn
);
8953 apply_change_group ();
8955 reload_cse_simplify_operands (insn
);
8957 reload_cse_record_set (body
, body
);
8959 else if (GET_CODE (body
) == PARALLEL
)
8962 rtx value
= NULL_RTX
;
8964 /* If every action in a PARALLEL is a noop, we can delete
8965 the entire PARALLEL. */
8966 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8968 rtx part
= XVECEXP (body
, 0, i
);
8969 if (GET_CODE (part
) == SET
)
8971 if (! reload_cse_noop_set_p (part
, insn
))
8973 if (REG_FUNCTION_VALUE_P (SET_DEST (part
)))
8977 value
= SET_DEST (part
);
8980 else if (GET_CODE (part
) != CLOBBER
)
8988 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, value
);
8989 INSN_CODE (insn
) = -1;
8990 REG_NOTES (insn
) = NULL_RTX
;
8991 push_obstacks (&reload_obstack
, &reload_obstack
);
8995 PUT_CODE (insn
, NOTE
);
8996 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8997 NOTE_SOURCE_FILE (insn
) = 0;
9000 /* We're done with this insn. */
9004 /* It's not a no-op, but we can try to simplify it. */
9005 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
9006 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
9007 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
9010 apply_change_group ();
9012 reload_cse_simplify_operands (insn
);
9014 /* Look through the PARALLEL and record the values being
9015 set, if possible. Also handle any CLOBBERs. */
9016 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
9018 rtx x
= XVECEXP (body
, 0, i
);
9020 if (GET_CODE (x
) == SET
)
9021 reload_cse_record_set (x
, body
);
9023 note_stores (x
, reload_cse_invalidate_rtx
);
9027 note_stores (body
, reload_cse_invalidate_rtx
);
9030 /* Clobber any registers which appear in REG_INC notes. We
9031 could keep track of the changes to their values, but it is
9032 unlikely to help. */
9036 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
9037 if (REG_NOTE_KIND (x
) == REG_INC
)
9038 reload_cse_invalidate_rtx (XEXP (x
, 0), NULL_RTX
);
9042 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
9043 after we have processed the insn. */
9044 if (GET_CODE (insn
) == CALL_INSN
)
9048 for (x
= CALL_INSN_FUNCTION_USAGE (insn
); x
; x
= XEXP (x
, 1))
9049 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
9050 reload_cse_invalidate_rtx (XEXP (XEXP (x
, 0), 0), NULL_RTX
);
9054 /* Free all the temporary structures we created, and go back to the
9055 regular obstacks. */
9056 obstack_free (&reload_obstack
, firstobj
);
9060 /* Call cse / combine like post-reload optimization phases.
9061 FIRST is the first instruction. */
9063 reload_cse_regs (first
)
9066 reload_cse_regs_1 (first
);
9068 reload_cse_move2add (first
);
9069 if (flag_expensive_optimizations
)
9070 reload_cse_regs_1 (first
);
9073 /* Return whether the values known for REGNO are equal to VAL. MODE
9074 is the mode of the object that VAL is being copied to; this matters
9075 if VAL is a CONST_INT. */
9078 reload_cse_regno_equal_p (regno
, val
, mode
)
9081 enum machine_mode mode
;
9088 for (x
= reg_values
[regno
]; x
; x
= XEXP (x
, 1))
9089 if (XEXP (x
, 0) != 0
9090 && rtx_equal_p (XEXP (x
, 0), val
)
9091 && (! flag_float_store
|| GET_CODE (XEXP (x
, 0)) != MEM
9092 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
9093 && (GET_CODE (val
) != CONST_INT
9094 || mode
== GET_MODE (x
)
9095 || (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
9096 /* On a big endian machine if the value spans more than
9097 one register then this register holds the high part of
9098 it and we can't use it.
9100 ??? We should also compare with the high part of the
9102 && !(WORDS_BIG_ENDIAN
9103 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
9104 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
9105 GET_MODE_BITSIZE (GET_MODE (x
))))))
9111 /* See whether a single set is a noop. SET is the set instruction we
9112 are should check, and INSN is the instruction from which it came. */
9115 reload_cse_noop_set_p (set
, insn
)
9120 enum machine_mode dest_mode
;
9124 src
= SET_SRC (set
);
9125 dest
= SET_DEST (set
);
9126 dest_mode
= GET_MODE (dest
);
9128 if (side_effects_p (src
))
9131 dreg
= true_regnum (dest
);
9132 sreg
= true_regnum (src
);
9134 /* Check for setting a register to itself. In this case, we don't
9135 have to worry about REG_DEAD notes. */
9136 if (dreg
>= 0 && dreg
== sreg
)
9142 /* Check for setting a register to itself. */
9146 /* Check for setting a register to a value which we already know
9147 is in the register. */
9148 else if (reload_cse_regno_equal_p (dreg
, src
, dest_mode
))
9151 /* Check for setting a register DREG to another register SREG
9152 where SREG is equal to a value which is already in DREG. */
9157 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
9161 if (XEXP (x
, 0) == 0)
9164 if (dest_mode
== GET_MODE (x
))
9166 else if (GET_MODE_BITSIZE (dest_mode
)
9167 < GET_MODE_BITSIZE (GET_MODE (x
)))
9168 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
9173 && reload_cse_regno_equal_p (dreg
, tmp
, dest_mode
))
9181 else if (GET_CODE (dest
) == MEM
)
9183 /* Check for storing a register to memory when we know that the
9184 register is equivalent to the memory location. */
9186 && reload_cse_regno_equal_p (sreg
, dest
, dest_mode
)
9187 && ! side_effects_p (dest
))
9194 /* Try to simplify a single SET instruction. SET is the set pattern.
9195 INSN is the instruction it came from.
9196 This function only handles one case: if we set a register to a value
9197 which is not a register, we try to find that value in some other register
9198 and change the set into a register copy. */
9201 reload_cse_simplify_set (set
, insn
)
9207 enum machine_mode dest_mode
;
9208 enum reg_class dclass
;
9211 dreg
= true_regnum (SET_DEST (set
));
9215 src
= SET_SRC (set
);
9216 if (side_effects_p (src
) || true_regnum (src
) >= 0)
9219 dclass
= REGNO_REG_CLASS (dreg
);
9221 /* If memory loads are cheaper than register copies, don't change them. */
9222 if (GET_CODE (src
) == MEM
9223 && MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1) < 2)
9226 /* If the constant is cheaper than a register, don't change it. */
9227 if (CONSTANT_P (src
)
9228 && rtx_cost (src
, SET
) < 2)
9231 dest_mode
= GET_MODE (SET_DEST (set
));
9232 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
9235 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i
), dclass
) == 2
9236 && reload_cse_regno_equal_p (i
, src
, dest_mode
))
9240 /* Pop back to the real obstacks while changing the insn. */
9243 validated
= validate_change (insn
, &SET_SRC (set
),
9244 gen_rtx_REG (dest_mode
, i
), 1);
9246 /* Go back to the obstack we are using for temporary
9248 push_obstacks (&reload_obstack
, &reload_obstack
);
9257 /* Try to replace operands in INSN with equivalent values that are already
9258 in registers. This can be viewed as optional reloading.
9260 For each non-register operand in the insn, see if any hard regs are
9261 known to be equivalent to that operand. Record the alternatives which
9262 can accept these hard registers. Among all alternatives, select the
9263 ones which are better or equal to the one currently matching, where
9264 "better" is in terms of '?' and '!' constraints. Among the remaining
9265 alternatives, select the one which replaces most operands with
9269 reload_cse_simplify_operands (insn
)
9272 #ifdef REGISTER_CONSTRAINTS
9273 int insn_code_number
, n_operands
, n_alternatives
;
9276 char *constraints
[MAX_RECOG_OPERANDS
];
9278 /* Vector recording how bad an alternative is. */
9279 int *alternative_reject
;
9280 /* Vector recording how many registers can be introduced by choosing
9281 this alternative. */
9282 int *alternative_nregs
;
9283 /* Array of vectors recording, for each operand and each alternative,
9284 which hard register to substitute, or -1 if the operand should be
9286 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
9287 /* Array of alternatives, sorted in order of decreasing desirability. */
9288 int *alternative_order
;
9289 rtx reg
= gen_rtx_REG (VOIDmode
, -1);
9291 /* Find out some information about this insn. */
9292 insn_code_number
= recog_memoized (insn
);
9293 /* We don't modify asm instructions. */
9294 if (insn_code_number
< 0)
9297 n_operands
= insn_n_operands
[insn_code_number
];
9298 n_alternatives
= insn_n_alternatives
[insn_code_number
];
9300 if (n_alternatives
== 0 || n_operands
== 0)
9302 insn_extract (insn
);
9304 /* Figure out which alternative currently matches. */
9305 if (! constrain_operands (insn_code_number
, 1))
9306 fatal_insn_not_found (insn
);
9308 alternative_reject
= (int *) alloca (n_alternatives
* sizeof (int));
9309 alternative_nregs
= (int *) alloca (n_alternatives
* sizeof (int));
9310 alternative_order
= (int *) alloca (n_alternatives
* sizeof (int));
9311 bzero ((char *)alternative_reject
, n_alternatives
* sizeof (int));
9312 bzero ((char *)alternative_nregs
, n_alternatives
* sizeof (int));
9314 for (i
= 0; i
< n_operands
; i
++)
9316 enum machine_mode mode
;
9320 op_alt_regno
[i
] = (int *) alloca (n_alternatives
* sizeof (int));
9321 for (j
= 0; j
< n_alternatives
; j
++)
9322 op_alt_regno
[i
][j
] = -1;
9324 p
= constraints
[i
] = insn_operand_constraint
[insn_code_number
][i
];
9325 mode
= insn_operand_mode
[insn_code_number
][i
];
9327 /* Add the reject values for each alternative given by the constraints
9328 for this operand. */
9336 alternative_reject
[j
] += 3;
9338 alternative_reject
[j
] += 300;
9341 /* We won't change operands which are already registers. We
9342 also don't want to modify output operands. */
9343 regno
= true_regnum (recog_operand
[i
]);
9345 || constraints
[i
][0] == '='
9346 || constraints
[i
][0] == '+')
9349 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
9351 int class = (int) NO_REGS
;
9353 if (! reload_cse_regno_equal_p (regno
, recog_operand
[i
], mode
))
9356 REGNO (reg
) = regno
;
9357 PUT_MODE (reg
, mode
);
9359 /* We found a register equal to this operand. Now look for all
9360 alternatives that can accept this register and have not been
9361 assigned a register they can use yet. */
9370 case '=': case '+': case '?':
9371 case '#': case '&': case '!':
9373 case '0': case '1': case '2': case '3': case '4':
9374 case 'm': case '<': case '>': case 'V': case 'o':
9375 case 'E': case 'F': case 'G': case 'H':
9376 case 's': case 'i': case 'n':
9377 case 'I': case 'J': case 'K': case 'L':
9378 case 'M': case 'N': case 'O': case 'P':
9379 #ifdef EXTRA_CONSTRAINT
9380 case 'Q': case 'R': case 'S': case 'T': case 'U':
9383 /* These don't say anything we care about. */
9387 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
9392 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
9395 case ',': case '\0':
9396 /* See if REGNO fits this alternative, and set it up as the
9397 replacement register if we don't have one for this
9398 alternative yet and the operand being replaced is not
9399 a cheap CONST_INT. */
9400 if (op_alt_regno
[i
][j
] == -1
9401 && reg_fits_class_p (reg
, class, 0, mode
)
9402 && (GET_CODE (recog_operand
[i
]) != CONST_INT
9403 || rtx_cost (recog_operand
[i
], SET
) > rtx_cost (reg
, SET
)))
9405 alternative_nregs
[j
]++;
9406 op_alt_regno
[i
][j
] = regno
;
9418 /* Record all alternatives which are better or equal to the currently
9419 matching one in the alternative_order array. */
9420 for (i
= j
= 0; i
< n_alternatives
; i
++)
9421 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
9422 alternative_order
[j
++] = i
;
9425 /* Sort it. Given a small number of alternatives, a dumb algorithm
9426 won't hurt too much. */
9427 for (i
= 0; i
< n_alternatives
- 1; i
++)
9430 int best_reject
= alternative_reject
[alternative_order
[i
]];
9431 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
9434 for (j
= i
+ 1; j
< n_alternatives
; j
++)
9436 int this_reject
= alternative_reject
[alternative_order
[j
]];
9437 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
9439 if (this_reject
< best_reject
9440 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
9443 best_reject
= this_reject
;
9444 best_nregs
= this_nregs
;
9448 tmp
= alternative_order
[best
];
9449 alternative_order
[best
] = alternative_order
[i
];
9450 alternative_order
[i
] = tmp
;
9453 /* Substitute the operands as determined by op_alt_regno for the best
9455 j
= alternative_order
[0];
9457 /* Pop back to the real obstacks while changing the insn. */
9460 for (i
= 0; i
< n_operands
; i
++)
9462 enum machine_mode mode
= insn_operand_mode
[insn_code_number
][i
];
9463 if (op_alt_regno
[i
][j
] == -1)
9466 validate_change (insn
, recog_operand_loc
[i
],
9467 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
9470 for (i
= insn_n_dups
[insn_code_number
] - 1; i
>= 0; i
--)
9472 int op
= recog_dup_num
[i
];
9473 enum machine_mode mode
= insn_operand_mode
[insn_code_number
][op
];
9475 if (op_alt_regno
[op
][j
] == -1)
9478 validate_change (insn
, recog_dup_loc
[i
],
9479 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
9482 /* Go back to the obstack we are using for temporary
9484 push_obstacks (&reload_obstack
, &reload_obstack
);
9486 return apply_change_group ();
9492 /* These two variables are used to pass information from
9493 reload_cse_record_set to reload_cse_check_clobber. */
9495 static int reload_cse_check_clobbered
;
9496 static rtx reload_cse_check_src
;
9498 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9499 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9500 second argument, which is passed by note_stores, is ignored. */
9503 reload_cse_check_clobber (dest
, ignore
)
9505 rtx ignore ATTRIBUTE_UNUSED
;
9507 if (reg_overlap_mentioned_p (dest
, reload_cse_check_src
))
9508 reload_cse_check_clobbered
= 1;
9511 /* Record the result of a SET instruction. SET is the set pattern.
9512 BODY is the pattern of the insn that it came from. */
9515 reload_cse_record_set (set
, body
)
9521 enum machine_mode dest_mode
;
9523 dest
= SET_DEST (set
);
9524 src
= SET_SRC (set
);
9525 dreg
= true_regnum (dest
);
9526 sreg
= true_regnum (src
);
9527 dest_mode
= GET_MODE (dest
);
9529 /* Some machines don't define AUTO_INC_DEC, but they still use push
9530 instructions. We need to catch that case here in order to
9531 invalidate the stack pointer correctly. Note that invalidating
9532 the stack pointer is different from invalidating DEST. */
9534 while (GET_CODE (x
) == SUBREG
9535 || GET_CODE (x
) == ZERO_EXTRACT
9536 || GET_CODE (x
) == SIGN_EXTRACT
9537 || GET_CODE (x
) == STRICT_LOW_PART
)
9539 if (push_operand (x
, GET_MODE (x
)))
9541 reload_cse_invalidate_rtx (stack_pointer_rtx
, NULL_RTX
);
9542 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9546 /* We can only handle an assignment to a register, or a store of a
9547 register to a memory location. For other cases, we just clobber
9548 the destination. We also have to just clobber if there are side
9549 effects in SRC or DEST. */
9550 if ((dreg
< 0 && GET_CODE (dest
) != MEM
)
9551 || side_effects_p (src
)
9552 || side_effects_p (dest
))
9554 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9559 /* We don't try to handle values involving CC, because it's a pain
9560 to keep track of when they have to be invalidated. */
9561 if (reg_mentioned_p (cc0_rtx
, src
)
9562 || reg_mentioned_p (cc0_rtx
, dest
))
9564 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9569 /* If BODY is a PARALLEL, then we need to see whether the source of
9570 SET is clobbered by some other instruction in the PARALLEL. */
9571 if (GET_CODE (body
) == PARALLEL
)
9575 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
9579 x
= XVECEXP (body
, 0, i
);
9583 reload_cse_check_clobbered
= 0;
9584 reload_cse_check_src
= src
;
9585 note_stores (x
, reload_cse_check_clobber
);
9586 if (reload_cse_check_clobbered
)
9588 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9598 /* This is an assignment to a register. Update the value we
9599 have stored for the register. */
9604 /* This is a copy from one register to another. Any values
9605 which were valid for SREG are now valid for DREG. If the
9606 mode changes, we use gen_lowpart_common to extract only
9607 the part of the value that is copied. */
9608 reg_values
[dreg
] = 0;
9609 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
9613 if (XEXP (x
, 0) == 0)
9615 if (dest_mode
== GET_MODE (XEXP (x
, 0)))
9617 else if (GET_MODE_BITSIZE (dest_mode
)
9618 > GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
9621 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
9623 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, tmp
,
9628 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, src
, NULL_RTX
);
9630 /* We've changed DREG, so invalidate any values held by other
9631 registers that depend upon it. */
9632 reload_cse_invalidate_regno (dreg
, dest_mode
, 0);
9634 /* If this assignment changes more than one hard register,
9635 forget anything we know about the others. */
9636 for (i
= 1; i
< HARD_REGNO_NREGS (dreg
, dest_mode
); i
++)
9637 reg_values
[dreg
+ i
] = 0;
9639 else if (GET_CODE (dest
) == MEM
)
9641 /* Invalidate conflicting memory locations. */
9642 reload_cse_invalidate_mem (dest
);
9644 /* If we're storing a register to memory, add DEST to the list
9646 if (sreg
>= 0 && ! side_effects_p (dest
))
9647 reg_values
[sreg
] = gen_rtx_EXPR_LIST (dest_mode
, dest
,
9652 /* We should have bailed out earlier. */
9657 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9659 This code might also be useful when reload gave up on reg+reg addresssing
9660 because of clashes between the return register and INDEX_REG_CLASS. */
9662 /* The maximum number of uses of a register we can keep track of to
9663 replace them with reg+reg addressing. */
9664 #define RELOAD_COMBINE_MAX_USES 6
9666 /* INSN is the insn where a register has ben used, and USEP points to the
9667 location of the register within the rtl. */
9668 struct reg_use
{ rtx insn
, *usep
; };
9670 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9671 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9672 indicates where it becomes live again.
9673 Otherwise, USE_INDEX is the index of the last encountered use of the
9674 register (which is first among these we have seen since we scan backwards),
9675 OFFSET contains the constant offset that is added to the register in
9676 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9677 last, of these uses. */
9680 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
9685 } reg_state
[FIRST_PSEUDO_REGISTER
];
9687 /* Reverse linear uid. This is increased in reload_combine while scanning
9688 the instructions from last to first. It is used to set last_label_ruid
9689 and the store_ruid / use_ruid fields in reg_state. */
9690 static int reload_combine_ruid
;
9696 int first_index_reg
= 1, last_index_reg
= 0;
9698 int last_label_ruid
;
9700 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9701 reload has already used it where appropriate, so there is no use in
9702 trying to generate it now. */
9703 if (double_reg_address_ok
&& reload_address_index_reg_class
!= NO_REGS
)
9706 /* To avoid wasting too much time later searching for an index register,
9707 determine the minimum and maximum index register numbers. */
9708 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9710 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
))
9712 if (! last_index_reg
)
9714 first_index_reg
= i
;
9717 /* If no index register is available, we can quit now. */
9718 if (first_index_reg
> last_index_reg
)
9721 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9722 last_label_ruid
= reload_combine_ruid
= 0;
9723 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9726 reg_state
[i
].use_index
= -1;
9729 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9730 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9734 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
9738 /* We cannot do our optimization across labels. Invalidating all the use
9739 information we have would be costly, so we just note where the label
9740 is and then later disable any optimization that would cross it. */
9741 if (GET_CODE (insn
) == CODE_LABEL
)
9742 last_label_ruid
= reload_combine_ruid
;
9743 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
9745 reload_combine_ruid
++;
9747 /* Look for (set (REGX) (CONST_INT))
9748 (set (REGX) (PLUS (REGX) (REGY)))
9750 ... (MEM (REGX)) ...
9752 (set (REGZ) (CONST_INT))
9754 ... (MEM (PLUS (REGZ) (REGY)))... .
9756 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9757 and that we know all uses of REGX before it dies. */
9758 set
= single_set (insn
);
9760 && GET_CODE (SET_DEST (set
)) == REG
9761 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
9762 GET_MODE (SET_DEST (set
)))
9764 && GET_CODE (SET_SRC (set
)) == PLUS
9765 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
9766 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
9767 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
9769 rtx reg
= SET_DEST (set
);
9770 rtx plus
= SET_SRC (set
);
9771 rtx base
= XEXP (plus
, 1);
9772 rtx prev
= prev_nonnote_insn (insn
);
9773 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
9774 int regno
= REGNO (reg
);
9776 rtx reg_sum
= NULL_RTX
;
9778 /* Now, we need an index register.
9779 We'll set index_reg to this index register, const_reg to the
9780 register that is to be loaded with the constant
9781 (denoted as REGZ in the substitution illustration above),
9782 and reg_sum to the register-register that we want to use to
9783 substitute uses of REG (typically in MEMs) with.
9784 First check REG and BASE for being index registers;
9785 we can use them even if they are not dead. */
9786 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
9787 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
9795 /* Otherwise, look for a free index register. Since we have
9796 checked above that neiter REG nor BASE are index registers,
9797 if we find anything at all, it will be different from these
9799 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
9801 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
9802 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
9803 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
9804 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
9806 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
9807 const_reg
= index_reg
;
9808 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
9814 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
9815 && rtx_equal_p (SET_DEST (prev_set
), reg
)
9816 && reg_state
[regno
].use_index
>= 0
9821 /* Change destination register and - if necessary - the
9822 constant value in PREV, the constant loading instruction. */
9823 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
9824 if (reg_state
[regno
].offset
!= const0_rtx
)
9825 validate_change (prev
,
9826 &SET_SRC (prev_set
),
9827 GEN_INT (INTVAL (SET_SRC (prev_set
))
9828 + INTVAL (reg_state
[regno
].offset
)),
9830 /* Now for every use of REG that we have recorded, replace REG
9832 for (i
= reg_state
[regno
].use_index
;
9833 i
< RELOAD_COMBINE_MAX_USES
; i
++)
9834 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
9835 reg_state
[regno
].reg_use
[i
].usep
,
9838 if (apply_change_group ())
9842 /* Delete the reg-reg addition. */
9843 PUT_CODE (insn
, NOTE
);
9844 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9845 NOTE_SOURCE_FILE (insn
) = 0;
9847 if (reg_state
[regno
].offset
!= const0_rtx
)
9849 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9851 for (np
= ®_NOTES (prev
); *np
; )
9853 if (REG_NOTE_KIND (*np
) == REG_EQUAL
9854 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
9855 *np
= XEXP (*np
, 1);
9857 np
= &XEXP (*np
, 1);
9860 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
9861 reg_state
[REGNO (const_reg
)].store_ruid
= reload_combine_ruid
;
9866 note_stores (PATTERN (insn
), reload_combine_note_store
);
9867 if (GET_CODE (insn
) == CALL_INSN
)
9871 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9873 if (call_used_regs
[i
])
9875 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9876 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9879 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
9880 link
= XEXP (link
, 1))
9882 rtx use
= XEXP (link
, 0);
9883 int regno
= REGNO (XEXP (use
, 0));
9884 if (GET_CODE (use
) == CLOBBER
)
9886 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
9887 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
9890 reg_state
[regno
].use_index
= -1;
9893 if (GET_CODE (insn
) == JUMP_INSN
)
9895 /* Non-spill registers might be used at the call destination in
9896 some unknown fashion, so we have to mark the unknown use. */
9897 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9899 if (! TEST_HARD_REG_BIT (used_spill_regs
, i
))
9900 reg_state
[i
].use_index
= -1;
9903 reload_combine_note_use (&PATTERN (insn
), insn
);
9904 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9906 if (REG_NOTE_KIND (note
) == REG_INC
9907 && GET_CODE (XEXP (note
, 0)) == REG
)
9908 reg_state
[REGNO (XEXP (note
, 0))].use_index
= -1;
9913 /* Check if DST is a register or a subreg of a register; if it is,
9914 update reg_state[regno].store_ruid and reg_state[regno].use_index
9915 accordingly. Called via note_stores from reload_combine.
9916 The second argument, SET, is ignored. */
9918 reload_combine_note_store (dst
, set
)
9919 rtx dst
, set ATTRIBUTE_UNUSED
;
9923 unsigned size
= GET_MODE_SIZE (GET_MODE (dst
));
9925 if (GET_CODE (dst
) == SUBREG
)
9927 regno
= SUBREG_WORD (dst
);
9928 dst
= SUBREG_REG (dst
);
9930 if (GET_CODE (dst
) != REG
)
9932 regno
+= REGNO (dst
);
9933 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9934 careful with registers / register parts that are not full words. */
9935 if (size
< (unsigned) UNITS_PER_WORD
)
9936 reg_state
[regno
].use_index
= -1;
9939 for (i
= size
/ UNITS_PER_WORD
- 1 + regno
; i
>= regno
; i
--)
9941 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9942 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9947 /* XP points to a piece of rtl that has to be checked for any uses of
9949 *XP is the pattern of INSN, or a part of it.
9950 Called from reload_combine, and recursively by itself. */
9952 reload_combine_note_use (xp
, insn
)
9956 enum rtx_code code
= x
->code
;
9959 rtx offset
= const0_rtx
; /* For the REG case below. */
9964 if (GET_CODE (SET_DEST (x
)) == REG
)
9966 reload_combine_note_use (&SET_SRC (x
), insn
);
9972 if (GET_CODE (SET_DEST (x
)) == REG
)
9977 /* We are interested in (plus (reg) (const_int)) . */
9978 if (GET_CODE (XEXP (x
, 0)) != REG
|| GET_CODE (XEXP (x
, 1)) != CONST_INT
)
9980 offset
= XEXP (x
, 1);
9985 int regno
= REGNO (x
);
9988 /* Some spurious USEs of pseudo registers might remain.
9989 Just ignore them. */
9990 if (regno
>= FIRST_PSEUDO_REGISTER
)
9993 /* If this register is already used in some unknown fashion, we
9995 If we decrement the index from zero to -1, we can't store more
9996 uses, so this register becomes used in an unknown fashion. */
9997 use_index
= --reg_state
[regno
].use_index
;
10001 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
10003 /* We have found another use for a register that is already
10004 used later. Check if the offsets match; if not, mark the
10005 register as used in an unknown fashion. */
10006 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
10008 reg_state
[regno
].use_index
= -1;
10014 /* This is the first use of this register we have seen since we
10015 marked it as dead. */
10016 reg_state
[regno
].offset
= offset
;
10017 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
10019 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
10020 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
10028 /* Recursively process the components of X. */
10029 fmt
= GET_RTX_FORMAT (code
);
10030 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10033 reload_combine_note_use (&XEXP (x
, i
), insn
);
10034 else if (fmt
[i
] == 'E')
10036 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10037 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
10042 /* See if we can reduce the cost of a constant by replacing a move with
10044 /* We cannot do our optimization across labels. Invalidating all the
10045 information about register contents we have would be costly, so we
10046 use last_label_luid (local variable of reload_cse_move2add) to note
10047 where the label is and then later disable any optimization that would
10049 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
10050 reg_set_luid[n] is larger than last_label_luid[n] . */
10051 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
10052 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
10053 reg_mode[n] to be valid.
10054 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
10055 has been set to reg_offset[n] in mode reg_mode[n] .
10056 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
10057 register n has been set to the sum of reg_offset[n] and register
10058 reg_base_reg[n], calculated in mode reg_mode[n] . */
10059 static rtx reg_offset
[FIRST_PSEUDO_REGISTER
];
10060 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
10061 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
10062 /* move2add_luid is linearily increased while scanning the instructions
10063 from first to last. It is used to set reg_set_luid in
10064 reload_cse_move2add and move2add_note_store. */
10065 static int move2add_luid
;
10068 reload_cse_move2add (first
)
10073 int last_label_luid
;
10075 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
10076 reg_set_luid
[i
] = 0;
10078 last_label_luid
= 0;
10080 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
10084 if (GET_CODE (insn
) == CODE_LABEL
)
10085 last_label_luid
= move2add_luid
;
10086 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
10088 pat
= PATTERN (insn
);
10089 /* For simplicity, we only perform this optimization on
10090 straightforward SETs. */
10091 if (GET_CODE (pat
) == SET
10092 && GET_CODE (SET_DEST (pat
)) == REG
)
10094 rtx reg
= SET_DEST (pat
);
10095 int regno
= REGNO (reg
);
10096 rtx src
= SET_SRC (pat
);
10098 /* Check if we have valid information on the contents of this
10099 register in the mode of REG. */
10100 /* ??? We don't know how zero / sign extension is handled, hence
10101 we can't go from a narrower to a wider mode. */
10102 if (reg_set_luid
[regno
] > last_label_luid
10103 && (GET_MODE_SIZE (GET_MODE (reg
))
10104 <= GET_MODE_SIZE (reg_mode
[regno
]))
10105 && GET_CODE (reg_offset
[regno
]) == CONST_INT
)
10107 /* Try to transform (set (REGX) (CONST_INT A))
10109 (set (REGX) (CONST_INT B))
10111 (set (REGX) (CONST_INT A))
10113 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10115 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
10118 rtx new_src
= GEN_INT (INTVAL (src
)
10119 - INTVAL (reg_offset
[regno
]));
10120 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
10121 use (set (reg) (reg)) instead.
10122 We don't delete this insn, nor do we convert it into a
10123 note, to avoid losing register notes or the return
10124 value flag. jump2 already knowns how to get rid of
10126 if (new_src
== const0_rtx
)
10127 success
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
10128 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
10129 && have_add2_insn (GET_MODE (reg
)))
10130 success
= validate_change (insn
, &PATTERN (insn
),
10131 gen_add2_insn (reg
, new_src
), 0);
10132 reg_set_luid
[regno
] = move2add_luid
;
10133 reg_mode
[regno
] = GET_MODE (reg
);
10134 reg_offset
[regno
] = src
;
10138 /* Try to transform (set (REGX) (REGY))
10139 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10141 (set (REGX) (REGY))
10142 (set (REGX) (PLUS (REGX) (CONST_INT B)))
10145 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10147 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10148 else if (GET_CODE (src
) == REG
10149 && reg_base_reg
[regno
] == REGNO (src
)
10150 && reg_set_luid
[regno
] > reg_set_luid
[REGNO (src
)])
10152 rtx next
= next_nonnote_insn (insn
);
10155 set
= single_set (next
);
10158 && SET_DEST (set
) == reg
10159 && GET_CODE (SET_SRC (set
)) == PLUS
10160 && XEXP (SET_SRC (set
), 0) == reg
10161 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
10163 rtx src3
= XEXP (SET_SRC (set
), 1);
10164 rtx new_src
= GEN_INT (INTVAL (src3
)
10165 - INTVAL (reg_offset
[regno
]));
10168 if (new_src
== const0_rtx
)
10169 /* See above why we create (set (reg) (reg)) here. */
10171 = validate_change (next
, &SET_SRC (set
), reg
, 0);
10172 else if ((rtx_cost (new_src
, PLUS
)
10173 < 2 + rtx_cost (src3
, SET
))
10174 && have_add2_insn (GET_MODE (reg
)))
10176 = validate_change (next
, &PATTERN (next
),
10177 gen_add2_insn (reg
, new_src
), 0);
10180 /* INSN might be the first insn in a basic block
10181 if the preceding insn is a conditional jump
10182 or a possible-throwing call. */
10183 PUT_CODE (insn
, NOTE
);
10184 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
10185 NOTE_SOURCE_FILE (insn
) = 0;
10188 reg_set_luid
[regno
] = move2add_luid
;
10189 reg_mode
[regno
] = GET_MODE (reg
);
10190 reg_offset
[regno
] = src3
;
10197 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
10199 if (REG_NOTE_KIND (note
) == REG_INC
10200 && GET_CODE (XEXP (note
, 0)) == REG
)
10202 /* Indicate that this register has been recently written to,
10203 but the exact contents are not available. */
10204 int regno
= REGNO (XEXP (note
, 0));
10205 if (regno
< FIRST_PSEUDO_REGISTER
)
10207 reg_set_luid
[regno
] = move2add_luid
;
10208 reg_offset
[regno
] = note
;
10212 note_stores (PATTERN (insn
), move2add_note_store
);
10213 /* If this is a CALL_INSN, all call used registers are stored with
10215 if (GET_CODE (insn
) == CALL_INSN
)
10217 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
10219 if (call_used_regs
[i
])
10221 reg_set_luid
[i
] = move2add_luid
;
10222 reg_offset
[i
] = insn
; /* Invalidate contents. */
10229 /* SET is a SET or CLOBBER that sets DST.
10230 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10231 Called from reload_cse_move2add via note_stores. */
10233 move2add_note_store (dst
, set
)
10239 enum machine_mode mode
= GET_MODE (dst
);
10240 if (GET_CODE (dst
) == SUBREG
)
10242 regno
= SUBREG_WORD (dst
);
10243 dst
= SUBREG_REG (dst
);
10245 if (GET_CODE (dst
) != REG
)
10248 regno
+= REGNO (dst
);
10250 if (HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
)
10252 rtx src
= SET_SRC (set
);
10254 reg_mode
[regno
] = mode
;
10255 switch (GET_CODE (src
))
10259 rtx src0
= XEXP (src
, 0);
10260 if (GET_CODE (src0
) == REG
)
10262 if (REGNO (src0
) != regno
10263 || reg_offset
[regno
] != const0_rtx
)
10265 reg_base_reg
[regno
] = REGNO (src0
);
10266 reg_set_luid
[regno
] = move2add_luid
;
10268 reg_offset
[regno
] = XEXP (src
, 1);
10271 reg_set_luid
[regno
] = move2add_luid
;
10272 reg_offset
[regno
] = set
; /* Invalidate contents. */
10277 reg_base_reg
[regno
] = REGNO (SET_SRC (set
));
10278 reg_offset
[regno
] = const0_rtx
;
10279 reg_set_luid
[regno
] = move2add_luid
;
10283 reg_base_reg
[regno
] = -1;
10284 reg_offset
[regno
] = SET_SRC (set
);
10285 reg_set_luid
[regno
] = move2add_luid
;
10291 for (i
= regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1; i
>= regno
; i
--)
10293 /* Indicate that this register has been recently written to,
10294 but the exact contents are not available. */
10295 reg_set_luid
[i
] = move2add_luid
;
10296 reg_offset
[i
] = dst
;