1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "insn-flags.h"
31 #include "insn-codes.h"
35 #include "basic-block.h"
42 /* This file contains the reload pass of the compiler, which is
43 run after register allocation has been done. It checks that
44 each insn is valid (operands required to be in registers really
45 are in registers of the proper class) and fixes up invalid ones
46 by copying values temporarily into registers for the insns
49 The results of register allocation are described by the vector
50 reg_renumber; the insns still contain pseudo regs, but reg_renumber
51 can be used to find which hard reg, if any, a pseudo reg is in.
53 The technique we always use is to free up a few hard regs that are
54 called ``reload regs'', and for each place where a pseudo reg
55 must be in a hard reg, copy it temporarily into one of the reload regs.
57 Reload regs are allocated locally for every instruction that needs
58 reloads. When there are pseudos which are allocated to a register that
59 has been chosen as a reload reg, such pseudos must be ``spilled''.
60 This means that they go to other hard regs, or to stack slots if no other
61 available hard regs can be found. Spilling can invalidate more
62 insns, requiring additional need for reloads, so we must keep checking
63 until the process stabilizes.
65 For machines with different classes of registers, we must keep track
66 of the register class needed for each reload, and make sure that
67 we allocate enough reload registers of each class.
69 The file reload.c contains the code that checks one insn for
70 validity and reports the reloads that it needs. This file
71 is in charge of scanning the entire rtl code, accumulating the
72 reload needs, spilling, assigning reload registers to use for
73 fixing up each insn, and generating the new insns to copy values
74 into the reload registers. */
77 #ifndef REGISTER_MOVE_COST
78 #define REGISTER_MOVE_COST(x, y) 2
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx
*reg_last_reload_reg
;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload
;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload
;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx
*reg_equiv_constant
;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx
*reg_equiv_memory_loc
;
105 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
106 This is used when the address is not valid as a memory address
107 (because its displacement is too big for the machine.) */
108 rtx
*reg_equiv_address
;
110 /* Element N is the memory slot to which pseudo reg N is equivalent,
111 or zero if pseudo reg N is not equivalent to a memory slot. */
114 /* Widest width in which each pseudo reg is referred to (via subreg). */
115 static int *reg_max_ref_width
;
117 /* Element N is the list of insns that initialized reg N from its equivalent
118 constant or memory slot. */
119 static rtx
*reg_equiv_init
;
121 /* Vector to remember old contents of reg_renumber before spilling. */
122 static short *reg_old_renumber
;
124 /* During reload_as_needed, element N contains the last pseudo regno reloaded
125 into hard register N. If that pseudo reg occupied more than one register,
126 reg_reloaded_contents points to that pseudo for each spill register in
127 use; all of these must remain set for an inheritance to occur. */
128 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
130 /* During reload_as_needed, element N contains the insn for which
131 hard register N was last used. Its contents are significant only
132 when reg_reloaded_valid is set for this register. */
133 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
135 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
136 static HARD_REG_SET reg_reloaded_valid
;
137 /* Indicate if the register was dead at the end of the reload.
138 This is only valid if reg_reloaded_contents is set and valid. */
139 static HARD_REG_SET reg_reloaded_dead
;
141 /* Number of spill-regs so far; number of valid elements of spill_regs. */
144 /* In parallel with spill_regs, contains REG rtx's for those regs.
145 Holds the last rtx used for any given reg, or 0 if it has never
146 been used for spilling yet. This rtx is reused, provided it has
148 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
150 /* In parallel with spill_regs, contains nonzero for a spill reg
151 that was stored after the last time it was used.
152 The precise value is the insn generated to do the store. */
153 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
155 /* This is the register that was stored with spill_reg_store. This is a
156 copy of reload_out / reload_out_reg when the value was stored; if
157 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
158 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
160 /* This table is the inverse mapping of spill_regs:
161 indexed by hard reg number,
162 it contains the position of that reg in spill_regs,
163 or -1 for something that is not in spill_regs.
165 ?!? This is no longer accurate. */
166 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
168 /* This reg set indicates registers that can't be used as spill registers for
169 the currently processed insn. These are the hard registers which are live
170 during the insn, but not allocated to pseudos, as well as fixed
172 static HARD_REG_SET bad_spill_regs
;
174 /* These are the hard registers that can't be used as spill register for any
175 insn. This includes registers used for user variables and registers that
176 we can't eliminate. A register that appears in this set also can't be used
177 to retry register allocation. */
178 static HARD_REG_SET bad_spill_regs_global
;
180 /* Describes order of use of registers for reloading
181 of spilled pseudo-registers. `n_spills' is the number of
182 elements that are actually valid; new ones are added at the end.
184 Both spill_regs and spill_reg_order are used on two occasions:
185 once during find_reload_regs, where they keep track of the spill registers
186 for a single insn, but also during reload_as_needed where they show all
187 the registers ever used by reload. For the latter case, the information
188 is calculated during finish_spills. */
189 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
191 /* This vector of reg sets indicates, for each pseudo, which hard registers
192 may not be used for retrying global allocation because the register was
193 formerly spilled from one of them. If we allowed reallocating a pseudo to
194 a register that it was already allocated to, reload might not
196 static HARD_REG_SET
*pseudo_previous_regs
;
198 /* This vector of reg sets indicates, for each pseudo, which hard
199 registers may not be used for retrying global allocation because they
200 are used as spill registers during one of the insns in which the
202 static HARD_REG_SET
*pseudo_forbidden_regs
;
204 /* All hard regs that have been used as spill registers for any insn are
205 marked in this set. */
206 static HARD_REG_SET used_spill_regs
;
208 /* Index of last register assigned as a spill register. We allocate in
209 a round-robin fashion. */
210 static int last_spill_reg
;
212 /* Describes order of preference for putting regs into spill_regs.
213 Contains the numbers of all the hard regs, in order most preferred first.
214 This order is different for each function.
215 It is set up by order_regs_for_reload.
216 Empty elements at the end contain -1. */
217 static short potential_reload_regs
[FIRST_PSEUDO_REGISTER
];
219 /* Nonzero if indirect addressing is supported on the machine; this means
220 that spilling (REG n) does not require reloading it into a register in
221 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
222 value indicates the level of indirect addressing supported, e.g., two
223 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
225 static char spill_indirect_levels
;
227 /* Nonzero if indirect addressing is supported when the innermost MEM is
228 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
229 which these are valid is the same as spill_indirect_levels, above. */
230 char indirect_symref_ok
;
232 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
233 char double_reg_address_ok
;
235 /* Record the stack slot for each spilled hard register. */
236 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
238 /* Width allocated so far for that stack slot. */
239 static int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
241 /* Record which pseudos needed to be spilled. */
242 static regset spilled_pseudos
;
244 /* First uid used by insns created by reload in this function.
245 Used in find_equiv_reg. */
246 int reload_first_uid
;
248 /* Flag set by local-alloc or global-alloc if anything is live in
249 a call-clobbered reg across calls. */
250 int caller_save_needed
;
252 /* Set to 1 while reload_as_needed is operating.
253 Required by some machines to handle any generated moves differently. */
254 int reload_in_progress
= 0;
256 /* These arrays record the insn_code of insns that may be needed to
257 perform input and output reloads of special objects. They provide a
258 place to pass a scratch register. */
259 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
260 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
262 /* This obstack is used for allocation of rtl during register elimination.
263 The allocated storage can be freed once find_reloads has processed the
265 struct obstack reload_obstack
;
267 /* Points to the beginning of the reload_obstack. All insn_chain structures
268 are allocated first. */
269 char *reload_startobj
;
271 /* The point after all insn_chain structures. Used to quickly deallocate
272 memory used while processing one insn. */
273 char *reload_firstobj
;
275 #define obstack_chunk_alloc xmalloc
276 #define obstack_chunk_free free
278 /* List of labels that must never be deleted. */
279 extern rtx forced_labels
;
281 /* List of insn_chain instructions, one for every insn that reload needs to
283 struct insn_chain
*reload_insn_chain
;
286 extern tree current_function_decl
;
288 extern union tree_node
*current_function_decl
;
291 /* List of all insns needing reloads. */
292 static struct insn_chain
*insns_need_reload
;
294 /* This structure is used to record information about register eliminations.
295 Each array entry describes one possible way of eliminating a register
296 in favor of another. If there is more than one way of eliminating a
297 particular register, the most preferred should be specified first. */
301 int from
; /* Register number to be eliminated. */
302 int to
; /* Register number used as replacement. */
303 int initial_offset
; /* Initial difference between values. */
304 int can_eliminate
; /* Non-zero if this elimination can be done. */
305 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
306 insns made by reload. */
307 int offset
; /* Current offset between the two regs. */
308 int previous_offset
; /* Offset at end of previous insn. */
309 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
310 rtx from_rtx
; /* REG rtx for the register to be eliminated.
311 We cannot simply compare the number since
312 we might then spuriously replace a hard
313 register corresponding to a pseudo
314 assigned to the reg to be eliminated. */
315 rtx to_rtx
; /* REG rtx for the replacement. */
318 static struct elim_table
* reg_eliminate
= 0;
320 /* This is an intermediate structure to initialize the table. It has
321 exactly the members provided by ELIMINABLE_REGS. */
322 static struct elim_table_1
326 } reg_eliminate_1
[] =
328 /* If a set of eliminable registers was specified, define the table from it.
329 Otherwise, default to the normal case of the frame pointer being
330 replaced by the stack pointer. */
332 #ifdef ELIMINABLE_REGS
335 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
338 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
340 /* Record the number of pending eliminations that have an offset not equal
341 to their initial offset. If non-zero, we use a new copy of each
342 replacement result in any insns encountered. */
343 int num_not_at_initial_offset
;
345 /* Count the number of registers that we may be able to eliminate. */
346 static int num_eliminable
;
347 /* And the number of registers that are equivalent to a constant that
348 can be eliminated to frame_pointer / arg_pointer + constant. */
349 static int num_eliminable_invariants
;
351 /* For each label, we record the offset of each elimination. If we reach
352 a label by more than one path and an offset differs, we cannot do the
353 elimination. This information is indexed by the number of the label.
354 The first table is an array of flags that records whether we have yet
355 encountered a label and the second table is an array of arrays, one
356 entry in the latter array for each elimination. */
358 static char *offsets_known_at
;
359 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
361 /* Number of labels in the current function. */
363 static int num_labels
;
365 struct hard_reg_n_uses
371 static void maybe_fix_stack_asms
PROTO((void));
372 static void calculate_needs_all_insns
PROTO((int));
373 static void calculate_needs
PROTO((struct insn_chain
*));
374 static void find_reload_regs
PROTO((struct insn_chain
*chain
,
376 static void find_tworeg_group
PROTO((struct insn_chain
*, int,
378 static void find_group
PROTO((struct insn_chain
*, int,
380 static int possible_group_p
PROTO((struct insn_chain
*, int));
381 static void count_possible_groups
PROTO((struct insn_chain
*, int));
382 static int modes_equiv_for_class_p
PROTO((enum machine_mode
,
385 static void delete_caller_save_insns
PROTO((void));
387 static void spill_failure
PROTO((rtx
));
388 static void new_spill_reg
PROTO((struct insn_chain
*, int, int,
390 static void maybe_mark_pseudo_spilled
PROTO((int));
391 static void delete_dead_insn
PROTO((rtx
));
392 static void alter_reg
PROTO((int, int));
393 static void set_label_offsets
PROTO((rtx
, rtx
, int));
394 static int eliminate_regs_in_insn
PROTO((rtx
, int));
395 static void update_eliminable_offsets
PROTO((void));
396 static void mark_not_eliminable
PROTO((rtx
, rtx
));
397 static void set_initial_elim_offsets
PROTO((void));
398 static void verify_initial_elim_offsets
PROTO((void));
399 static void set_initial_label_offsets
PROTO((void));
400 static void set_offsets_for_label
PROTO((rtx
));
401 static void init_elim_table
PROTO((void));
402 static void update_eliminables
PROTO((HARD_REG_SET
*));
403 static void spill_hard_reg
PROTO((int, FILE *, int));
404 static int finish_spills
PROTO((int, FILE *));
405 static void ior_hard_reg_set
PROTO((HARD_REG_SET
*, HARD_REG_SET
*));
406 static void scan_paradoxical_subregs
PROTO((rtx
));
407 static int hard_reg_use_compare
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
408 static void count_pseudo
PROTO((struct hard_reg_n_uses
*, int));
409 static void order_regs_for_reload
PROTO((struct insn_chain
*));
410 static void reload_as_needed
PROTO((int));
411 static void forget_old_reloads_1
PROTO((rtx
, rtx
));
412 static int reload_reg_class_lower
PROTO((const GENERIC_PTR
, const GENERIC_PTR
));
413 static void mark_reload_reg_in_use
PROTO((int, int, enum reload_type
,
415 static void clear_reload_reg_in_use
PROTO((int, int, enum reload_type
,
417 static int reload_reg_free_p
PROTO((int, int, enum reload_type
));
418 static int reload_reg_free_for_value_p
PROTO((int, int, enum reload_type
, rtx
, rtx
, int, int));
419 static int reload_reg_reaches_end_p
PROTO((int, int, enum reload_type
));
420 static int allocate_reload_reg
PROTO((struct insn_chain
*, int, int,
422 static void choose_reload_regs
PROTO((struct insn_chain
*));
423 static void merge_assigned_reloads
PROTO((rtx
));
424 static void emit_reload_insns
PROTO((struct insn_chain
*));
425 static void delete_output_reload
PROTO((rtx
, int, int));
426 static void delete_address_reloads
PROTO((rtx
, rtx
));
427 static void delete_address_reloads_1
PROTO((rtx
, rtx
, rtx
));
428 static rtx inc_for_reload
PROTO((rtx
, rtx
, rtx
, int));
429 static int constraint_accepts_reg_p
PROTO((const char *, rtx
));
430 static void reload_cse_regs_1
PROTO((rtx
));
431 static void reload_cse_invalidate_regno
PROTO((int, enum machine_mode
, int));
432 static int reload_cse_mem_conflict_p
PROTO((rtx
, rtx
));
433 static void reload_cse_invalidate_mem
PROTO((rtx
));
434 static void reload_cse_invalidate_rtx
PROTO((rtx
, rtx
));
435 static int reload_cse_regno_equal_p
PROTO((int, rtx
, enum machine_mode
));
436 static int reload_cse_noop_set_p
PROTO((rtx
, rtx
));
437 static int reload_cse_simplify_set
PROTO((rtx
, rtx
));
438 static int reload_cse_simplify_operands
PROTO((rtx
));
439 static void reload_cse_check_clobber
PROTO((rtx
, rtx
));
440 static void reload_cse_record_set
PROTO((rtx
, rtx
));
441 static void reload_combine
PROTO((void));
442 static void reload_combine_note_use
PROTO((rtx
*, rtx
));
443 static void reload_combine_note_store
PROTO((rtx
, rtx
));
444 static void reload_cse_move2add
PROTO((rtx
));
445 static void move2add_note_store
PROTO((rtx
, rtx
));
447 static void add_auto_inc_notes
PROTO((rtx
, rtx
));
450 /* Initialize the reload pass once per compilation. */
457 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
458 Set spill_indirect_levels to the number of levels such addressing is
459 permitted, zero if it is not permitted at all. */
462 = gen_rtx_MEM (Pmode
,
464 gen_rtx_REG (Pmode
, LAST_VIRTUAL_REGISTER
+ 1),
466 spill_indirect_levels
= 0;
468 while (memory_address_p (QImode
, tem
))
470 spill_indirect_levels
++;
471 tem
= gen_rtx_MEM (Pmode
, tem
);
474 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
476 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
477 indirect_symref_ok
= memory_address_p (QImode
, tem
);
479 /* See if reg+reg is a valid (and offsettable) address. */
481 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
483 tem
= gen_rtx_PLUS (Pmode
,
484 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
485 gen_rtx_REG (Pmode
, i
));
486 /* This way, we make sure that reg+reg is an offsettable address. */
487 tem
= plus_constant (tem
, 4);
489 if (memory_address_p (QImode
, tem
))
491 double_reg_address_ok
= 1;
496 /* Initialize obstack for our rtl allocation. */
497 gcc_obstack_init (&reload_obstack
);
498 reload_startobj
= (char *) obstack_alloc (&reload_obstack
, 0);
501 /* List of insn chains that are currently unused. */
502 static struct insn_chain
*unused_insn_chains
= 0;
504 /* Allocate an empty insn_chain structure. */
508 struct insn_chain
*c
;
510 if (unused_insn_chains
== 0)
512 c
= (struct insn_chain
*)
513 obstack_alloc (&reload_obstack
, sizeof (struct insn_chain
));
514 c
->live_before
= OBSTACK_ALLOC_REG_SET (&reload_obstack
);
515 c
->live_after
= OBSTACK_ALLOC_REG_SET (&reload_obstack
);
519 c
= unused_insn_chains
;
520 unused_insn_chains
= c
->next
;
522 c
->is_caller_save_insn
= 0;
523 c
->need_operand_change
= 0;
529 /* Small utility function to set all regs in hard reg set TO which are
530 allocated to pseudos in regset FROM. */
532 compute_use_by_pseudos (to
, from
)
537 EXECUTE_IF_SET_IN_REG_SET
538 (from
, FIRST_PSEUDO_REGISTER
, regno
,
540 int r
= reg_renumber
[regno
];
544 /* reload_combine uses the information from
545 BASIC_BLOCK->global_live_at_start, which might still
546 contain registers that have not actually been allocated
547 since they have an equivalence. */
548 if (! reload_completed
)
553 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (regno
));
555 SET_HARD_REG_BIT (*to
, r
+ nregs
);
560 /* Global variables used by reload and its subroutines. */
562 /* Set during calculate_needs if an insn needs register elimination. */
563 static int something_needs_elimination
;
564 /* Set during calculate_needs if an insn needs an operand changed. */
565 int something_needs_operands_changed
;
567 /* Nonzero means we couldn't get enough spill regs. */
570 /* Main entry point for the reload pass.
572 FIRST is the first insn of the function being compiled.
574 GLOBAL nonzero means we were called from global_alloc
575 and should attempt to reallocate any pseudoregs that we
576 displace from hard regs we will use for reloads.
577 If GLOBAL is zero, we do not have enough information to do that,
578 so any pseudo reg that is spilled must go to the stack.
580 DUMPFILE is the global-reg debugging dump file stream, or 0.
581 If it is nonzero, messages are written to it to describe
582 which registers are seized as reload regs, which pseudo regs
583 are spilled from them, and where the pseudo regs are reallocated to.
585 Return value is nonzero if reload failed
586 and we must not do any more for this function. */
589 reload (first
, global
, dumpfile
)
596 register struct elim_table
*ep
;
598 /* The two pointers used to track the true location of the memory used
599 for label offsets. */
600 char *real_known_ptr
= NULL_PTR
;
601 int (*real_at_ptr
)[NUM_ELIMINABLE_REGS
];
603 /* Make sure even insns with volatile mem refs are recognizable. */
608 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
610 /* Make sure that the last insn in the chain
611 is not something that needs reloading. */
612 emit_note (NULL_PTR
, NOTE_INSN_DELETED
);
614 /* Enable find_equiv_reg to distinguish insns made by reload. */
615 reload_first_uid
= get_max_uid ();
617 #ifdef SECONDARY_MEMORY_NEEDED
618 /* Initialize the secondary memory table. */
619 clear_secondary_mem ();
622 /* We don't have a stack slot for any spill reg yet. */
623 bzero ((char *) spill_stack_slot
, sizeof spill_stack_slot
);
624 bzero ((char *) spill_stack_slot_width
, sizeof spill_stack_slot_width
);
626 /* Initialize the save area information for caller-save, in case some
630 /* Compute which hard registers are now in use
631 as homes for pseudo registers.
632 This is done here rather than (eg) in global_alloc
633 because this point is reached even if not optimizing. */
634 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
637 /* A function that receives a nonlocal goto must save all call-saved
639 if (current_function_has_nonlocal_label
)
640 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
642 if (! call_used_regs
[i
] && ! fixed_regs
[i
])
643 regs_ever_live
[i
] = 1;
646 /* Find all the pseudo registers that didn't get hard regs
647 but do have known equivalent constants or memory slots.
648 These include parameters (known equivalent to parameter slots)
649 and cse'd or loop-moved constant memory addresses.
651 Record constant equivalents in reg_equiv_constant
652 so they will be substituted by find_reloads.
653 Record memory equivalents in reg_mem_equiv so they can
654 be substituted eventually by altering the REG-rtx's. */
656 reg_equiv_constant
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
657 bzero ((char *) reg_equiv_constant
, max_regno
* sizeof (rtx
));
658 reg_equiv_memory_loc
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
659 bzero ((char *) reg_equiv_memory_loc
, max_regno
* sizeof (rtx
));
660 reg_equiv_mem
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
661 bzero ((char *) reg_equiv_mem
, max_regno
* sizeof (rtx
));
662 reg_equiv_init
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
663 bzero ((char *) reg_equiv_init
, max_regno
* sizeof (rtx
));
664 reg_equiv_address
= (rtx
*) xmalloc (max_regno
* sizeof (rtx
));
665 bzero ((char *) reg_equiv_address
, max_regno
* sizeof (rtx
));
666 reg_max_ref_width
= (int *) xmalloc (max_regno
* sizeof (int));
667 bzero ((char *) reg_max_ref_width
, max_regno
* sizeof (int));
668 reg_old_renumber
= (short *) xmalloc (max_regno
* sizeof (short));
669 bcopy ((PTR
) reg_renumber
, (PTR
) reg_old_renumber
, max_regno
* sizeof (short));
670 pseudo_forbidden_regs
671 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
673 = (HARD_REG_SET
*) xmalloc (max_regno
* sizeof (HARD_REG_SET
));
675 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
676 bzero ((char *) pseudo_previous_regs
, max_regno
* sizeof (HARD_REG_SET
));
678 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
679 Also find all paradoxical subregs and find largest such for each pseudo.
680 On machines with small register classes, record hard registers that
681 are used for user variables. These can never be used for spills.
682 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
683 caller-saved registers must be marked live. */
685 num_eliminable_invariants
= 0;
686 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
688 rtx set
= single_set (insn
);
690 if (GET_CODE (insn
) == NOTE
&& CONST_CALL_P (insn
)
691 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
692 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
693 if (! call_used_regs
[i
])
694 regs_ever_live
[i
] = 1;
696 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
698 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
700 #ifdef LEGITIMATE_PIC_OPERAND_P
701 && (! function_invariant_p (XEXP (note
, 0))
703 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
707 rtx x
= XEXP (note
, 0);
708 i
= REGNO (SET_DEST (set
));
709 if (i
> LAST_VIRTUAL_REGISTER
)
711 if (GET_CODE (x
) == MEM
)
713 /* If the operand is a PLUS, the MEM may be shared,
714 so make sure we have an unshared copy here. */
715 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
718 reg_equiv_memory_loc
[i
] = x
;
720 else if (function_invariant_p (x
))
722 if (GET_CODE (x
) == PLUS
)
724 /* This is PLUS of frame pointer and a constant,
725 and might be shared. Unshare it. */
726 reg_equiv_constant
[i
] = copy_rtx (x
);
727 num_eliminable_invariants
++;
729 else if (x
== frame_pointer_rtx
730 || x
== arg_pointer_rtx
)
732 reg_equiv_constant
[i
] = x
;
733 num_eliminable_invariants
++;
735 else if (LEGITIMATE_CONSTANT_P (x
))
736 reg_equiv_constant
[i
] = x
;
738 reg_equiv_memory_loc
[i
]
739 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
744 /* If this register is being made equivalent to a MEM
745 and the MEM is not SET_SRC, the equivalencing insn
746 is one with the MEM as a SET_DEST and it occurs later.
747 So don't mark this insn now. */
748 if (GET_CODE (x
) != MEM
749 || rtx_equal_p (SET_SRC (set
), x
))
751 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init
[i
]);
756 /* If this insn is setting a MEM from a register equivalent to it,
757 this is the equivalencing insn. */
758 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
759 && GET_CODE (SET_SRC (set
)) == REG
760 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
761 && rtx_equal_p (SET_DEST (set
),
762 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
763 reg_equiv_init
[REGNO (SET_SRC (set
))]
764 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
765 reg_equiv_init
[REGNO (SET_SRC (set
))]);
767 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
768 scan_paradoxical_subregs (PATTERN (insn
));
773 num_labels
= max_label_num () - get_first_label_num ();
775 /* Allocate the tables used to store offset information at labels. */
776 /* We used to use alloca here, but the size of what it would try to
777 allocate would occasionally cause it to exceed the stack limit and
778 cause a core dump. */
779 real_known_ptr
= xmalloc (num_labels
);
781 = (int (*)[NUM_ELIMINABLE_REGS
])
782 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
784 offsets_known_at
= real_known_ptr
- get_first_label_num ();
786 = (int (*)[NUM_ELIMINABLE_REGS
]) (real_at_ptr
- get_first_label_num ());
788 /* Alter each pseudo-reg rtx to contain its hard reg number.
789 Assign stack slots to the pseudos that lack hard regs or equivalents.
790 Do not touch virtual registers. */
792 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
795 /* If we have some registers we think can be eliminated, scan all insns to
796 see if there is an insn that sets one of these registers to something
797 other than itself plus a constant. If so, the register cannot be
798 eliminated. Doing this scan here eliminates an extra pass through the
799 main reload loop in the most common case where register elimination
801 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
802 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
803 || GET_CODE (insn
) == CALL_INSN
)
804 note_stores (PATTERN (insn
), mark_not_eliminable
);
806 #ifndef REGISTER_CONSTRAINTS
807 /* If all the pseudo regs have hard regs,
808 except for those that are never referenced,
809 we know that no reloads are needed. */
810 /* But that is not true if there are register constraints, since
811 in that case some pseudos might be in the wrong kind of hard reg. */
813 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
814 if (reg_renumber
[i
] == -1 && REG_N_REFS (i
) != 0)
817 if (i
== max_regno
&& num_eliminable
== 0 && ! caller_save_needed
)
819 free (real_known_ptr
);
821 free (reg_equiv_constant
);
822 free (reg_equiv_memory_loc
);
823 free (reg_equiv_mem
);
824 free (reg_equiv_init
);
825 free (reg_equiv_address
);
826 free (reg_max_ref_width
);
827 free (reg_old_renumber
);
828 free (pseudo_previous_regs
);
829 free (pseudo_forbidden_regs
);
834 maybe_fix_stack_asms ();
836 insns_need_reload
= 0;
837 something_needs_elimination
= 0;
839 /* Initialize to -1, which means take the first spill register. */
842 spilled_pseudos
= ALLOCA_REG_SET ();
844 /* Spill any hard regs that we know we can't eliminate. */
845 CLEAR_HARD_REG_SET (used_spill_regs
);
846 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
847 if (! ep
->can_eliminate
)
848 spill_hard_reg (ep
->from
, dumpfile
, 1);
850 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
851 if (frame_pointer_needed
)
852 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, dumpfile
, 1);
854 finish_spills (global
, dumpfile
);
856 /* From now on, we may need to generate moves differently. We may also
857 allow modifications of insns which cause them to not be recognized.
858 Any such modifications will be cleaned up during reload itself. */
859 reload_in_progress
= 1;
861 /* This loop scans the entire function each go-round
862 and repeats until one repetition spills no additional hard regs. */
865 int something_changed
;
867 struct insn_chain
*chain
;
869 HOST_WIDE_INT starting_frame_size
;
871 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done
872 here because the stack size may be a part of the offset computation
873 for register elimination, and there might have been new stack slots
874 created in the last iteration of this loop. */
875 assign_stack_local (BLKmode
, 0, 0);
877 starting_frame_size
= get_frame_size ();
879 set_initial_elim_offsets ();
880 set_initial_label_offsets ();
882 /* For each pseudo register that has an equivalent location defined,
883 try to eliminate any eliminable registers (such as the frame pointer)
884 assuming initial offsets for the replacement register, which
887 If the resulting location is directly addressable, substitute
888 the MEM we just got directly for the old REG.
890 If it is not addressable but is a constant or the sum of a hard reg
891 and constant, it is probably not addressable because the constant is
892 out of range, in that case record the address; we will generate
893 hairy code to compute the address in a register each time it is
894 needed. Similarly if it is a hard register, but one that is not
895 valid as an address register.
897 If the location is not addressable, but does not have one of the
898 above forms, assign a stack slot. We have to do this to avoid the
899 potential of producing lots of reloads if, e.g., a location involves
900 a pseudo that didn't get a hard register and has an equivalent memory
901 location that also involves a pseudo that didn't get a hard register.
903 Perhaps at some point we will improve reload_when_needed handling
904 so this problem goes away. But that's very hairy. */
906 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
907 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
909 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
911 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
913 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
914 else if (CONSTANT_P (XEXP (x
, 0))
915 || (GET_CODE (XEXP (x
, 0)) == REG
916 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
917 || (GET_CODE (XEXP (x
, 0)) == PLUS
918 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
919 && (REGNO (XEXP (XEXP (x
, 0), 0))
920 < FIRST_PSEUDO_REGISTER
)
921 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
922 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
925 /* Make a new stack slot. Then indicate that something
926 changed so we go back and recompute offsets for
927 eliminable registers because the allocation of memory
928 below might change some offset. reg_equiv_{mem,address}
929 will be set up for this pseudo on the next pass around
931 reg_equiv_memory_loc
[i
] = 0;
932 reg_equiv_init
[i
] = 0;
937 if (caller_save_needed
)
940 /* If we allocated another stack slot, redo elimination bookkeeping. */
941 if (starting_frame_size
!= get_frame_size ())
944 if (caller_save_needed
)
946 save_call_clobbered_regs ();
947 /* That might have allocated new insn_chain structures. */
948 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
951 calculate_needs_all_insns (global
);
953 CLEAR_REG_SET (spilled_pseudos
);
956 something_changed
= 0;
958 /* If we allocated any new memory locations, make another pass
959 since it might have changed elimination offsets. */
960 if (starting_frame_size
!= get_frame_size ())
961 something_changed
= 1;
964 HARD_REG_SET to_spill
;
965 CLEAR_HARD_REG_SET (to_spill
);
966 update_eliminables (&to_spill
);
967 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
968 if (TEST_HARD_REG_BIT (to_spill
, i
))
970 spill_hard_reg (i
, dumpfile
, 1);
973 /* Regardless of the state of spills, if we previously had
974 a register that we thought we could eliminate, but no can
975 not eliminate, we must run another pass.
977 Consider pseudos which have an entry in reg_equiv_* which
978 reference an eliminable register. We must make another pass
979 to update reg_equiv_* so that we do not substitute in the
980 old value from when we thought the elimination could be
982 something_changed
= 1;
986 CLEAR_HARD_REG_SET (used_spill_regs
);
987 /* Try to satisfy the needs for each insn. */
988 for (chain
= insns_need_reload
; chain
!= 0;
989 chain
= chain
->next_need_reload
)
990 find_reload_regs (chain
, dumpfile
);
995 if (insns_need_reload
!= 0 || did_spill
)
996 something_changed
|= finish_spills (global
, dumpfile
);
998 if (! something_changed
)
1001 if (caller_save_needed
)
1002 delete_caller_save_insns ();
1005 /* If global-alloc was run, notify it of any register eliminations we have
1008 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1009 if (ep
->can_eliminate
)
1010 mark_elimination (ep
->from
, ep
->to
);
1012 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1013 If that insn didn't set the register (i.e., it copied the register to
1014 memory), just delete that insn instead of the equivalencing insn plus
1015 anything now dead. If we call delete_dead_insn on that insn, we may
1016 delete the insn that actually sets the register if the register dies
1017 there and that is incorrect. */
1019 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1021 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0)
1024 for (list
= reg_equiv_init
[i
]; list
; list
= XEXP (list
, 1))
1026 rtx equiv_insn
= XEXP (list
, 0);
1027 if (GET_CODE (equiv_insn
) == NOTE
)
1029 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
1030 delete_dead_insn (equiv_insn
);
1033 PUT_CODE (equiv_insn
, NOTE
);
1034 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1035 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1041 /* Use the reload registers where necessary
1042 by generating move instructions to move the must-be-register
1043 values into or out of the reload registers. */
1045 if (insns_need_reload
!= 0 || something_needs_elimination
1046 || something_needs_operands_changed
)
1048 int old_frame_size
= get_frame_size ();
1050 reload_as_needed (global
);
1052 if (old_frame_size
!= get_frame_size ())
1056 verify_initial_elim_offsets ();
1059 /* If we were able to eliminate the frame pointer, show that it is no
1060 longer live at the start of any basic block. If it ls live by
1061 virtue of being in a pseudo, that pseudo will be marked live
1062 and hence the frame pointer will be known to be live via that
1065 if (! frame_pointer_needed
)
1066 for (i
= 0; i
< n_basic_blocks
; i
++)
1067 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i
)->global_live_at_start
,
1068 HARD_FRAME_POINTER_REGNUM
);
1070 /* Come here (with failure set nonzero) if we can't get enough spill regs
1071 and we decide not to abort about it. */
1074 reload_in_progress
= 0;
1076 /* Now eliminate all pseudo regs by modifying them into
1077 their equivalent memory references.
1078 The REG-rtx's for the pseudos are modified in place,
1079 so all insns that used to refer to them now refer to memory.
1081 For a reg that has a reg_equiv_address, all those insns
1082 were changed by reloading so that no insns refer to it any longer;
1083 but the DECL_RTL of a variable decl may refer to it,
1084 and if so this causes the debugging info to mention the variable. */
1086 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1091 int is_readonly
= 0;
1093 if (reg_equiv_memory_loc
[i
])
1095 in_struct
= MEM_IN_STRUCT_P (reg_equiv_memory_loc
[i
]);
1096 is_scalar
= MEM_SCALAR_P (reg_equiv_memory_loc
[i
]);
1097 is_readonly
= RTX_UNCHANGING_P (reg_equiv_memory_loc
[i
]);
1100 if (reg_equiv_mem
[i
])
1101 addr
= XEXP (reg_equiv_mem
[i
], 0);
1103 if (reg_equiv_address
[i
])
1104 addr
= reg_equiv_address
[i
];
1108 if (reg_renumber
[i
] < 0)
1110 rtx reg
= regno_reg_rtx
[i
];
1111 XEXP (reg
, 0) = addr
;
1112 REG_USERVAR_P (reg
) = 0;
1113 RTX_UNCHANGING_P (reg
) = is_readonly
;
1114 MEM_IN_STRUCT_P (reg
) = in_struct
;
1115 MEM_SCALAR_P (reg
) = is_scalar
;
1116 /* We have no alias information about this newly created
1118 MEM_ALIAS_SET (reg
) = 0;
1119 PUT_CODE (reg
, MEM
);
1121 else if (reg_equiv_mem
[i
])
1122 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1126 /* We must set reload_completed now since the cleanup_subreg_operands call
1127 below will re-recognize each insn and reload may have generated insns
1128 which are only valid during and after reload. */
1129 reload_completed
= 1;
1131 /* Make a pass over all the insns and delete all USEs which we
1132 inserted only to tag a REG_EQUAL note on them. Remove all
1133 REG_DEAD and REG_UNUSED notes. Delete all CLOBBER insns and
1134 simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1135 REG_LIBCALL notes since they are no longer useful or accurate.
1136 Strip and regenerate REG_INC notes that may have been moved
1139 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1140 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1144 if ((GET_CODE (PATTERN (insn
)) == USE
1145 && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1146 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
1148 PUT_CODE (insn
, NOTE
);
1149 NOTE_SOURCE_FILE (insn
) = 0;
1150 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1154 pnote
= ®_NOTES (insn
);
1157 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1158 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1159 || REG_NOTE_KIND (*pnote
) == REG_INC
1160 || REG_NOTE_KIND (*pnote
) == REG_RETVAL
1161 || REG_NOTE_KIND (*pnote
) == REG_LIBCALL
)
1162 *pnote
= XEXP (*pnote
, 1);
1164 pnote
= &XEXP (*pnote
, 1);
1168 add_auto_inc_notes (insn
, PATTERN (insn
));
1171 /* And simplify (subreg (reg)) if it appears as an operand. */
1172 cleanup_subreg_operands (insn
);
1175 /* If we are doing stack checking, give a warning if this function's
1176 frame size is larger than we expect. */
1177 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1179 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1181 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1182 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1183 size
+= UNITS_PER_WORD
;
1185 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1186 warning ("frame size too large for reliable stack checking");
1189 /* If we are doing stack checking, give a warning if this function's
1190 frame size is larger than we expect. */
1191 if (flag_stack_check
&& ! STACK_CHECK_BUILTIN
)
1193 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1194 static int verbose_warned
= 0;
1196 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1197 if (regs_ever_live
[i
] && ! fixed_regs
[i
] && call_used_regs
[i
])
1198 size
+= UNITS_PER_WORD
;
1200 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1202 warning ("frame size too large for reliable stack checking");
1203 if (! verbose_warned
)
1205 warning ("try reducing the number of local variables");
1211 /* Indicate that we no longer have known memory locations or constants. */
1212 if (reg_equiv_constant
)
1213 free (reg_equiv_constant
);
1214 reg_equiv_constant
= 0;
1215 if (reg_equiv_memory_loc
)
1216 free (reg_equiv_memory_loc
);
1217 reg_equiv_memory_loc
= 0;
1220 free (real_known_ptr
);
1224 free (reg_equiv_mem
);
1225 free (reg_equiv_init
);
1226 free (reg_equiv_address
);
1227 free (reg_max_ref_width
);
1228 free (reg_old_renumber
);
1229 free (pseudo_previous_regs
);
1230 free (pseudo_forbidden_regs
);
1232 FREE_REG_SET (spilled_pseudos
);
1234 CLEAR_HARD_REG_SET (used_spill_regs
);
1235 for (i
= 0; i
< n_spills
; i
++)
1236 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1238 /* Free all the insn_chain structures at once. */
1239 obstack_free (&reload_obstack
, reload_startobj
);
1240 unused_insn_chains
= 0;
1245 /* Yet another special case. Unfortunately, reg-stack forces people to
1246 write incorrect clobbers in asm statements. These clobbers must not
1247 cause the register to appear in bad_spill_regs, otherwise we'll call
1248 fatal_insn later. We clear the corresponding regnos in the live
1249 register sets to avoid this.
1250 The whole thing is rather sick, I'm afraid. */
1252 maybe_fix_stack_asms ()
1255 char *constraints
[MAX_RECOG_OPERANDS
];
1256 enum machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1257 struct insn_chain
*chain
;
1259 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1262 HARD_REG_SET clobbered
, allowed
;
1265 if (GET_RTX_CLASS (GET_CODE (chain
->insn
)) != 'i'
1266 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1268 pat
= PATTERN (chain
->insn
);
1269 if (GET_CODE (pat
) != PARALLEL
)
1272 CLEAR_HARD_REG_SET (clobbered
);
1273 CLEAR_HARD_REG_SET (allowed
);
1275 /* First, make a mask of all stack regs that are clobbered. */
1276 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1278 rtx t
= XVECEXP (pat
, 0, i
);
1279 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1280 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1283 /* Get the operand values and constraints out of the insn. */
1284 decode_asm_operands (pat
, recog_operand
, recog_operand_loc
,
1285 constraints
, operand_mode
);
1287 /* For every operand, see what registers are allowed. */
1288 for (i
= 0; i
< noperands
; i
++)
1290 char *p
= constraints
[i
];
1291 /* For every alternative, we compute the class of registers allowed
1292 for reloading in CLS, and merge its contents into the reg set
1294 int cls
= (int) NO_REGS
;
1300 if (c
== '\0' || c
== ',' || c
== '#')
1302 /* End of one alternative - mark the regs in the current
1303 class, and reset the class. */
1304 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1309 } while (c
!= '\0' && c
!= ',');
1317 case '=': case '+': case '*': case '%': case '?': case '!':
1318 case '0': case '1': case '2': case '3': case '4': case 'm':
1319 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1320 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1321 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1323 #ifdef EXTRA_CONSTRAINT
1324 case 'Q': case 'R': case 'S': case 'T': case 'U':
1329 cls
= (int) reg_class_subunion
[cls
][(int) BASE_REG_CLASS
];
1334 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1338 cls
= (int) reg_class_subunion
[cls
][(int) REG_CLASS_FROM_LETTER (c
)];
1343 /* Those of the registers which are clobbered, but allowed by the
1344 constraints, must be usable as reload registers. So clear them
1345 out of the life information. */
1346 AND_HARD_REG_SET (allowed
, clobbered
);
1347 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1348 if (TEST_HARD_REG_BIT (allowed
, i
))
1350 CLEAR_REGNO_REG_SET (chain
->live_before
, i
);
1351 CLEAR_REGNO_REG_SET (chain
->live_after
, i
);
1359 /* Walk the chain of insns, and determine for each whether it needs reloads
1360 and/or eliminations. Build the corresponding insns_need_reload list, and
1361 set something_needs_elimination as appropriate. */
1363 calculate_needs_all_insns (global
)
1366 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1367 struct insn_chain
**pchain
;
1369 something_needs_elimination
= 0;
1371 for (pchain
= &reload_insn_chain
; *pchain
!= 0; pchain
= &(*pchain
)->next
)
1374 struct insn_chain
*chain
;
1379 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1380 include REG_LABEL), we need to see what effects this has on the
1381 known offsets at labels. */
1383 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
1384 || (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
1385 && REG_NOTES (insn
) != 0))
1386 set_label_offsets (insn
, insn
, 0);
1388 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1390 rtx old_body
= PATTERN (insn
);
1391 int old_code
= INSN_CODE (insn
);
1392 rtx old_notes
= REG_NOTES (insn
);
1393 int did_elimination
= 0;
1394 int operands_changed
= 0;
1395 rtx set
= single_set (insn
);
1397 /* Skip insns that only set an equivalence. */
1398 if (set
&& GET_CODE (SET_DEST (set
)) == REG
1399 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1400 && reg_equiv_constant
[REGNO (SET_DEST (set
))])
1402 /* Must clear out the shortcuts, in case they were set last
1404 chain
->need_elim
= 0;
1405 chain
->need_reload
= 0;
1406 chain
->need_operand_change
= 0;
1410 /* If needed, eliminate any eliminable registers. */
1411 if (num_eliminable
|| num_eliminable_invariants
)
1412 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1414 /* Analyze the instruction. */
1415 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1416 global
, spill_reg_order
);
1418 /* If a no-op set needs more than one reload, this is likely
1419 to be something that needs input address reloads. We
1420 can't get rid of this cleanly later, and it is of no use
1421 anyway, so discard it now.
1422 We only do this when expensive_optimizations is enabled,
1423 since this complements reload inheritance / output
1424 reload deletion, and it can make debugging harder. */
1425 if (flag_expensive_optimizations
&& n_reloads
> 1)
1427 rtx set
= single_set (insn
);
1429 && SET_SRC (set
) == SET_DEST (set
)
1430 && GET_CODE (SET_SRC (set
)) == REG
1431 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1433 PUT_CODE (insn
, NOTE
);
1434 NOTE_SOURCE_FILE (insn
) = 0;
1435 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
1440 update_eliminable_offsets ();
1442 /* Remember for later shortcuts which insns had any reloads or
1443 register eliminations. */
1444 chain
->need_elim
= did_elimination
;
1445 chain
->need_reload
= n_reloads
> 0;
1446 chain
->need_operand_change
= operands_changed
;
1448 /* Discard any register replacements done. */
1449 if (did_elimination
)
1451 obstack_free (&reload_obstack
, reload_firstobj
);
1452 PATTERN (insn
) = old_body
;
1453 INSN_CODE (insn
) = old_code
;
1454 REG_NOTES (insn
) = old_notes
;
1455 something_needs_elimination
= 1;
1458 something_needs_operands_changed
|= operands_changed
;
1462 *pprev_reload
= chain
;
1463 pprev_reload
= &chain
->next_need_reload
;
1465 calculate_needs (chain
);
1472 /* Compute the most additional registers needed by one instruction,
1473 given by CHAIN. Collect information separately for each class of regs.
1475 To compute the number of reload registers of each class needed for an
1476 insn, we must simulate what choose_reload_regs can do. We do this by
1477 splitting an insn into an "input" and an "output" part. RELOAD_OTHER
1478 reloads are used in both. The input part uses those reloads,
1479 RELOAD_FOR_INPUT reloads, which must be live over the entire input section
1480 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
1481 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs.
1483 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT,
1484 which are live for the entire output portion, and the maximum of all the
1485 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand.
1487 The total number of registers needed is the maximum of the
1488 inputs and outputs. */
1491 calculate_needs (chain
)
1492 struct insn_chain
*chain
;
1496 /* Each `struct needs' corresponds to one RELOAD_... type. */
1500 struct needs output
;
1502 struct needs other_addr
;
1503 struct needs op_addr
;
1504 struct needs op_addr_reload
;
1505 struct needs in_addr
[MAX_RECOG_OPERANDS
];
1506 struct needs in_addr_addr
[MAX_RECOG_OPERANDS
];
1507 struct needs out_addr
[MAX_RECOG_OPERANDS
];
1508 struct needs out_addr_addr
[MAX_RECOG_OPERANDS
];
1511 bzero ((char *) chain
->group_size
, sizeof chain
->group_size
);
1512 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1513 chain
->group_mode
[i
] = VOIDmode
;
1514 bzero ((char *) &insn_needs
, sizeof insn_needs
);
1516 /* Count each reload once in every class
1517 containing the reload's own class. */
1519 for (i
= 0; i
< n_reloads
; i
++)
1521 register enum reg_class
*p
;
1522 enum reg_class
class = reload_reg_class
[i
];
1524 enum machine_mode mode
;
1525 struct needs
*this_needs
;
1527 /* Don't count the dummy reloads, for which one of the
1528 regs mentioned in the insn can be used for reloading.
1529 Don't count optional reloads.
1530 Don't count reloads that got combined with others. */
1531 if (reload_reg_rtx
[i
] != 0
1532 || reload_optional
[i
] != 0
1533 || (reload_out
[i
] == 0 && reload_in
[i
] == 0
1534 && ! reload_secondary_p
[i
]))
1537 mode
= reload_inmode
[i
];
1538 if (GET_MODE_SIZE (reload_outmode
[i
]) > GET_MODE_SIZE (mode
))
1539 mode
= reload_outmode
[i
];
1540 size
= CLASS_MAX_NREGS (class, mode
);
1542 /* Decide which time-of-use to count this reload for. */
1543 switch (reload_when_needed
[i
])
1546 this_needs
= &insn_needs
.other
;
1548 case RELOAD_FOR_INPUT
:
1549 this_needs
= &insn_needs
.input
;
1551 case RELOAD_FOR_OUTPUT
:
1552 this_needs
= &insn_needs
.output
;
1554 case RELOAD_FOR_INSN
:
1555 this_needs
= &insn_needs
.insn
;
1557 case RELOAD_FOR_OTHER_ADDRESS
:
1558 this_needs
= &insn_needs
.other_addr
;
1560 case RELOAD_FOR_INPUT_ADDRESS
:
1561 this_needs
= &insn_needs
.in_addr
[reload_opnum
[i
]];
1563 case RELOAD_FOR_INPADDR_ADDRESS
:
1564 this_needs
= &insn_needs
.in_addr_addr
[reload_opnum
[i
]];
1566 case RELOAD_FOR_OUTPUT_ADDRESS
:
1567 this_needs
= &insn_needs
.out_addr
[reload_opnum
[i
]];
1569 case RELOAD_FOR_OUTADDR_ADDRESS
:
1570 this_needs
= &insn_needs
.out_addr_addr
[reload_opnum
[i
]];
1572 case RELOAD_FOR_OPERAND_ADDRESS
:
1573 this_needs
= &insn_needs
.op_addr
;
1575 case RELOAD_FOR_OPADDR_ADDR
:
1576 this_needs
= &insn_needs
.op_addr_reload
;
1584 enum machine_mode other_mode
, allocate_mode
;
1586 /* Count number of groups needed separately from
1587 number of individual regs needed. */
1588 this_needs
->groups
[(int) class]++;
1589 p
= reg_class_superclasses
[(int) class];
1590 while (*p
!= LIM_REG_CLASSES
)
1591 this_needs
->groups
[(int) *p
++]++;
1593 /* Record size and mode of a group of this class. */
1594 /* If more than one size group is needed,
1595 make all groups the largest needed size. */
1596 if (chain
->group_size
[(int) class] < size
)
1598 other_mode
= chain
->group_mode
[(int) class];
1599 allocate_mode
= mode
;
1601 chain
->group_size
[(int) class] = size
;
1602 chain
->group_mode
[(int) class] = mode
;
1607 allocate_mode
= chain
->group_mode
[(int) class];
1610 /* Crash if two dissimilar machine modes both need
1611 groups of consecutive regs of the same class. */
1613 if (other_mode
!= VOIDmode
&& other_mode
!= allocate_mode
1614 && ! modes_equiv_for_class_p (allocate_mode
,
1616 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class",
1621 this_needs
->regs
[(unsigned char)reload_nongroup
[i
]][(int) class] += 1;
1622 p
= reg_class_superclasses
[(int) class];
1623 while (*p
!= LIM_REG_CLASSES
)
1624 this_needs
->regs
[(unsigned char)reload_nongroup
[i
]][(int) *p
++] += 1;
1630 /* All reloads have been counted for this insn;
1631 now merge the various times of use.
1632 This sets insn_needs, etc., to the maximum total number
1633 of registers needed at any point in this insn. */
1635 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1637 int j
, in_max
, out_max
;
1639 /* Compute normal and nongroup needs. */
1640 for (j
= 0; j
<= 1; j
++)
1643 for (in_max
= 0, out_max
= 0, k
= 0; k
< reload_n_operands
; k
++)
1645 in_max
= MAX (in_max
,
1646 (insn_needs
.in_addr
[k
].regs
[j
][i
]
1647 + insn_needs
.in_addr_addr
[k
].regs
[j
][i
]));
1648 out_max
= MAX (out_max
, insn_needs
.out_addr
[k
].regs
[j
][i
]);
1649 out_max
= MAX (out_max
,
1650 insn_needs
.out_addr_addr
[k
].regs
[j
][i
]);
1653 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1654 and operand addresses but not things used to reload
1655 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads
1656 don't conflict with things needed to reload inputs or
1659 in_max
= MAX (MAX (insn_needs
.op_addr
.regs
[j
][i
],
1660 insn_needs
.op_addr_reload
.regs
[j
][i
]),
1663 out_max
= MAX (out_max
, insn_needs
.insn
.regs
[j
][i
]);
1665 insn_needs
.input
.regs
[j
][i
]
1666 = MAX (insn_needs
.input
.regs
[j
][i
]
1667 + insn_needs
.op_addr
.regs
[j
][i
]
1668 + insn_needs
.insn
.regs
[j
][i
],
1669 in_max
+ insn_needs
.input
.regs
[j
][i
]);
1671 insn_needs
.output
.regs
[j
][i
] += out_max
;
1672 insn_needs
.other
.regs
[j
][i
]
1673 += MAX (MAX (insn_needs
.input
.regs
[j
][i
],
1674 insn_needs
.output
.regs
[j
][i
]),
1675 insn_needs
.other_addr
.regs
[j
][i
]);
1679 /* Now compute group needs. */
1680 for (in_max
= 0, out_max
= 0, j
= 0; j
< reload_n_operands
; j
++)
1682 in_max
= MAX (in_max
, insn_needs
.in_addr
[j
].groups
[i
]);
1683 in_max
= MAX (in_max
, insn_needs
.in_addr_addr
[j
].groups
[i
]);
1684 out_max
= MAX (out_max
, insn_needs
.out_addr
[j
].groups
[i
]);
1685 out_max
= MAX (out_max
, insn_needs
.out_addr_addr
[j
].groups
[i
]);
1688 in_max
= MAX (MAX (insn_needs
.op_addr
.groups
[i
],
1689 insn_needs
.op_addr_reload
.groups
[i
]),
1691 out_max
= MAX (out_max
, insn_needs
.insn
.groups
[i
]);
1693 insn_needs
.input
.groups
[i
]
1694 = MAX (insn_needs
.input
.groups
[i
]
1695 + insn_needs
.op_addr
.groups
[i
]
1696 + insn_needs
.insn
.groups
[i
],
1697 in_max
+ insn_needs
.input
.groups
[i
]);
1699 insn_needs
.output
.groups
[i
] += out_max
;
1700 insn_needs
.other
.groups
[i
]
1701 += MAX (MAX (insn_needs
.input
.groups
[i
],
1702 insn_needs
.output
.groups
[i
]),
1703 insn_needs
.other_addr
.groups
[i
]);
1706 /* Record the needs for later. */
1707 chain
->need
= insn_needs
.other
;
1710 /* Find a group of exactly 2 registers.
1712 First try to fill out the group by spilling a single register which
1713 would allow completion of the group.
1715 Then try to create a new group from a pair of registers, neither of
1716 which are explicitly used.
1718 Then try to create a group from any pair of registers. */
1721 find_tworeg_group (chain
, class, dumpfile
)
1722 struct insn_chain
*chain
;
1727 /* First, look for a register that will complete a group. */
1728 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1732 j
= potential_reload_regs
[i
];
1733 if (j
>= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
)
1734 && ((j
> 0 && (other
= j
- 1, spill_reg_order
[other
] >= 0)
1735 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1736 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1737 && HARD_REGNO_MODE_OK (other
, chain
->group_mode
[class])
1738 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, other
)
1739 /* We don't want one part of another group.
1740 We could get "two groups" that overlap! */
1741 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, other
))
1742 || (j
< FIRST_PSEUDO_REGISTER
- 1
1743 && (other
= j
+ 1, spill_reg_order
[other
] >= 0)
1744 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1745 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1746 && HARD_REGNO_MODE_OK (j
, chain
->group_mode
[class])
1747 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, other
)
1748 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, other
))))
1750 register enum reg_class
*p
;
1752 /* We have found one that will complete a group,
1753 so count off one group as provided. */
1754 chain
->need
.groups
[class]--;
1755 p
= reg_class_superclasses
[class];
1756 while (*p
!= LIM_REG_CLASSES
)
1758 if (chain
->group_size
[(int) *p
] <= chain
->group_size
[class])
1759 chain
->need
.groups
[(int) *p
]--;
1763 /* Indicate both these regs are part of a group. */
1764 SET_HARD_REG_BIT (chain
->counted_for_groups
, j
);
1765 SET_HARD_REG_BIT (chain
->counted_for_groups
, other
);
1769 /* We can't complete a group, so start one. */
1770 if (i
== FIRST_PSEUDO_REGISTER
)
1771 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1774 j
= potential_reload_regs
[i
];
1775 /* Verify that J+1 is a potential reload reg. */
1776 for (k
= 0; k
< FIRST_PSEUDO_REGISTER
; k
++)
1777 if (potential_reload_regs
[k
] == j
+ 1)
1779 if (j
>= 0 && j
+ 1 < FIRST_PSEUDO_REGISTER
1780 && k
< FIRST_PSEUDO_REGISTER
1781 && spill_reg_order
[j
] < 0 && spill_reg_order
[j
+ 1] < 0
1782 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1783 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ 1)
1784 && HARD_REGNO_MODE_OK (j
, chain
->group_mode
[class])
1785 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, j
+ 1)
1786 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ 1))
1790 /* I should be the index in potential_reload_regs
1791 of the new reload reg we have found. */
1793 new_spill_reg (chain
, i
, class, 0, dumpfile
);
1796 /* Find a group of more than 2 registers.
1797 Look for a sufficient sequence of unspilled registers, and spill them all
1801 find_group (chain
, class, dumpfile
)
1802 struct insn_chain
*chain
;
1808 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1810 int j
= potential_reload_regs
[i
];
1813 && j
+ chain
->group_size
[class] <= FIRST_PSEUDO_REGISTER
1814 && HARD_REGNO_MODE_OK (j
, chain
->group_mode
[class]))
1817 /* Check each reg in the sequence. */
1818 for (k
= 0; k
< chain
->group_size
[class]; k
++)
1819 if (! (spill_reg_order
[j
+ k
] < 0
1820 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ k
)
1821 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ k
)))
1823 /* We got a full sequence, so spill them all. */
1824 if (k
== chain
->group_size
[class])
1826 register enum reg_class
*p
;
1827 for (k
= 0; k
< chain
->group_size
[class]; k
++)
1830 SET_HARD_REG_BIT (chain
->counted_for_groups
, j
+ k
);
1831 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
1832 if (potential_reload_regs
[idx
] == j
+ k
)
1834 new_spill_reg (chain
, idx
, class, 0, dumpfile
);
1837 /* We have found one that will complete a group,
1838 so count off one group as provided. */
1839 chain
->need
.groups
[class]--;
1840 p
= reg_class_superclasses
[class];
1841 while (*p
!= LIM_REG_CLASSES
)
1843 if (chain
->group_size
[(int) *p
]
1844 <= chain
->group_size
[class])
1845 chain
->need
.groups
[(int) *p
]--;
1852 /* There are no groups left. */
1853 spill_failure (chain
->insn
);
1857 /* If pseudo REG conflicts with one of our reload registers, mark it as
1860 maybe_mark_pseudo_spilled (reg
)
1864 int r
= reg_renumber
[reg
];
1869 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
1870 for (i
= 0; i
< n_spills
; i
++)
1871 if (r
<= spill_regs
[i
] && r
+ nregs
> spill_regs
[i
])
1873 SET_REGNO_REG_SET (spilled_pseudos
, reg
);
1878 /* Find more reload regs to satisfy the remaining need of an insn, which
1880 Do it by ascending class number, since otherwise a reg
1881 might be spilled for a big class and might fail to count
1882 for a smaller class even though it belongs to that class.
1884 Count spilled regs in `spills', and add entries to
1885 `spill_regs' and `spill_reg_order'.
1887 ??? Note there is a problem here.
1888 When there is a need for a group in a high-numbered class,
1889 and also need for non-group regs that come from a lower class,
1890 the non-group regs are chosen first. If there aren't many regs,
1891 they might leave no room for a group.
1893 This was happening on the 386. To fix it, we added the code
1894 that calls possible_group_p, so that the lower class won't
1895 break up the last possible group.
1897 Really fixing the problem would require changes above
1898 in counting the regs already spilled, and in choose_reload_regs.
1899 It might be hard to avoid introducing bugs there. */
1902 find_reload_regs (chain
, dumpfile
)
1903 struct insn_chain
*chain
;
1907 short *group_needs
= chain
->need
.groups
;
1908 short *simple_needs
= chain
->need
.regs
[0];
1909 short *nongroup_needs
= chain
->need
.regs
[1];
1912 fprintf (dumpfile
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1914 /* Compute the order of preference for hard registers to spill.
1915 Store them by decreasing preference in potential_reload_regs. */
1917 order_regs_for_reload (chain
);
1919 /* So far, no hard regs have been spilled. */
1921 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1922 spill_reg_order
[i
] = -1;
1924 CLEAR_HARD_REG_SET (chain
->used_spill_regs
);
1925 CLEAR_HARD_REG_SET (chain
->counted_for_groups
);
1926 CLEAR_HARD_REG_SET (chain
->counted_for_nongroups
);
1928 for (class = 0; class < N_REG_CLASSES
; class++)
1930 /* First get the groups of registers.
1931 If we got single registers first, we might fragment
1933 while (group_needs
[class] > 0)
1935 /* If any single spilled regs happen to form groups,
1936 count them now. Maybe we don't really need
1937 to spill another group. */
1938 count_possible_groups (chain
, class);
1940 if (group_needs
[class] <= 0)
1943 /* Groups of size 2, the only groups used on most machines,
1944 are treated specially. */
1945 if (chain
->group_size
[class] == 2)
1946 find_tworeg_group (chain
, class, dumpfile
);
1948 find_group (chain
, class, dumpfile
);
1953 /* Now similarly satisfy all need for single registers. */
1955 while (simple_needs
[class] > 0 || nongroup_needs
[class] > 0)
1957 /* If we spilled enough regs, but they weren't counted
1958 against the non-group need, see if we can count them now.
1959 If so, we can avoid some actual spilling. */
1960 if (simple_needs
[class] <= 0 && nongroup_needs
[class] > 0)
1961 for (i
= 0; i
< n_spills
; i
++)
1963 int regno
= spill_regs
[i
];
1964 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1965 && !TEST_HARD_REG_BIT (chain
->counted_for_groups
, regno
)
1966 && !TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
)
1967 && nongroup_needs
[class] > 0)
1969 register enum reg_class
*p
;
1971 SET_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
);
1972 nongroup_needs
[class]--;
1973 p
= reg_class_superclasses
[class];
1974 while (*p
!= LIM_REG_CLASSES
)
1975 nongroup_needs
[(int) *p
++]--;
1979 if (simple_needs
[class] <= 0 && nongroup_needs
[class] <= 0)
1982 /* Consider the potential reload regs that aren't
1983 yet in use as reload regs, in order of preference.
1984 Find the most preferred one that's in this class. */
1986 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1988 int regno
= potential_reload_regs
[i
];
1990 && TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1991 /* If this reg will not be available for groups,
1992 pick one that does not foreclose possible groups.
1993 This is a kludge, and not very general,
1994 but it should be sufficient to make the 386 work,
1995 and the problem should not occur on machines with
1997 && (nongroup_needs
[class] == 0
1998 || possible_group_p (chain
, regno
)))
2002 /* If we couldn't get a register, try to get one even if we
2003 might foreclose possible groups. This may cause problems
2004 later, but that's better than aborting now, since it is
2005 possible that we will, in fact, be able to form the needed
2006 group even with this allocation. */
2008 if (i
>= FIRST_PSEUDO_REGISTER
2009 && asm_noperands (chain
->insn
) < 0)
2010 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2011 if (potential_reload_regs
[i
] >= 0
2012 && TEST_HARD_REG_BIT (reg_class_contents
[class],
2013 potential_reload_regs
[i
]))
2016 /* I should be the index in potential_reload_regs
2017 of the new reload reg we have found. */
2019 new_spill_reg (chain
, i
, class, 1, dumpfile
);
2025 /* We know which hard regs to use, now mark the pseudos that live in them
2026 as needing to be kicked out. */
2027 EXECUTE_IF_SET_IN_REG_SET
2028 (chain
->live_before
, FIRST_PSEUDO_REGISTER
, i
,
2030 maybe_mark_pseudo_spilled (i
);
2032 EXECUTE_IF_SET_IN_REG_SET
2033 (chain
->live_after
, FIRST_PSEUDO_REGISTER
, i
,
2035 maybe_mark_pseudo_spilled (i
);
2038 IOR_HARD_REG_SET (used_spill_regs
, chain
->used_spill_regs
);
2042 dump_needs (chain
, dumpfile
)
2043 struct insn_chain
*chain
;
2046 static char *reg_class_names
[] = REG_CLASS_NAMES
;
2048 struct needs
*n
= &chain
->need
;
2050 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2052 if (n
->regs
[i
][0] > 0)
2054 ";; Need %d reg%s of class %s.\n",
2055 n
->regs
[i
][0], n
->regs
[i
][0] == 1 ? "" : "s",
2056 reg_class_names
[i
]);
2057 if (n
->regs
[i
][1] > 0)
2059 ";; Need %d nongroup reg%s of class %s.\n",
2060 n
->regs
[i
][1], n
->regs
[i
][1] == 1 ? "" : "s",
2061 reg_class_names
[i
]);
2062 if (n
->groups
[i
] > 0)
2064 ";; Need %d group%s (%smode) of class %s.\n",
2065 n
->groups
[i
], n
->groups
[i
] == 1 ? "" : "s",
2066 mode_name
[(int) chain
->group_mode
[i
]],
2067 reg_class_names
[i
]);
2071 /* Delete all insns that were inserted by emit_caller_save_insns during
2074 delete_caller_save_insns ()
2076 struct insn_chain
*c
= reload_insn_chain
;
2080 while (c
!= 0 && c
->is_caller_save_insn
)
2082 struct insn_chain
*next
= c
->next
;
2085 if (insn
== BLOCK_HEAD (c
->block
))
2086 BLOCK_HEAD (c
->block
) = NEXT_INSN (insn
);
2087 if (insn
== BLOCK_END (c
->block
))
2088 BLOCK_END (c
->block
) = PREV_INSN (insn
);
2089 if (c
== reload_insn_chain
)
2090 reload_insn_chain
= next
;
2092 if (NEXT_INSN (insn
) != 0)
2093 PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2094 if (PREV_INSN (insn
) != 0)
2095 NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2098 next
->prev
= c
->prev
;
2100 c
->prev
->next
= next
;
2101 c
->next
= unused_insn_chains
;
2102 unused_insn_chains
= c
;
2110 /* Nonzero if, after spilling reg REGNO for non-groups,
2111 it will still be possible to find a group if we still need one. */
2114 possible_group_p (chain
, regno
)
2115 struct insn_chain
*chain
;
2119 int class = (int) NO_REGS
;
2121 for (i
= 0; i
< (int) N_REG_CLASSES
; i
++)
2122 if (chain
->need
.groups
[i
] > 0)
2128 if (class == (int) NO_REGS
)
2131 /* Consider each pair of consecutive registers. */
2132 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
- 1; i
++)
2134 /* Ignore pairs that include reg REGNO. */
2135 if (i
== regno
|| i
+ 1 == regno
)
2138 /* Ignore pairs that are outside the class that needs the group.
2139 ??? Here we fail to handle the case where two different classes
2140 independently need groups. But this never happens with our
2141 current machine descriptions. */
2142 if (! (TEST_HARD_REG_BIT (reg_class_contents
[class], i
)
2143 && TEST_HARD_REG_BIT (reg_class_contents
[class], i
+ 1)))
2146 /* A pair of consecutive regs we can still spill does the trick. */
2147 if (spill_reg_order
[i
] < 0 && spill_reg_order
[i
+ 1] < 0
2148 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2149 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1))
2152 /* A pair of one already spilled and one we can spill does it
2153 provided the one already spilled is not otherwise reserved. */
2154 if (spill_reg_order
[i
] < 0
2155 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2156 && spill_reg_order
[i
+ 1] >= 0
2157 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, i
+ 1)
2158 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, i
+ 1))
2160 if (spill_reg_order
[i
+ 1] < 0
2161 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1)
2162 && spill_reg_order
[i
] >= 0
2163 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, i
)
2164 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, i
))
2171 /* Count any groups of CLASS that can be formed from the registers recently
2175 count_possible_groups (chain
, class)
2176 struct insn_chain
*chain
;
2182 /* Now find all consecutive groups of spilled registers
2183 and mark each group off against the need for such groups.
2184 But don't count them against ordinary need, yet. */
2186 if (chain
->group_size
[class] == 0)
2189 CLEAR_HARD_REG_SET (new);
2191 /* Make a mask of all the regs that are spill regs in class I. */
2192 for (i
= 0; i
< n_spills
; i
++)
2194 int regno
= spill_regs
[i
];
2196 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
2197 && ! TEST_HARD_REG_BIT (chain
->counted_for_groups
, regno
)
2198 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
))
2199 SET_HARD_REG_BIT (new, regno
);
2202 /* Find each consecutive group of them. */
2203 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
&& chain
->need
.groups
[class] > 0; i
++)
2204 if (TEST_HARD_REG_BIT (new, i
)
2205 && i
+ chain
->group_size
[class] <= FIRST_PSEUDO_REGISTER
2206 && HARD_REGNO_MODE_OK (i
, chain
->group_mode
[class]))
2208 for (j
= 1; j
< chain
->group_size
[class]; j
++)
2209 if (! TEST_HARD_REG_BIT (new, i
+ j
))
2212 if (j
== chain
->group_size
[class])
2214 /* We found a group. Mark it off against this class's need for
2215 groups, and against each superclass too. */
2216 register enum reg_class
*p
;
2218 chain
->need
.groups
[class]--;
2219 p
= reg_class_superclasses
[class];
2220 while (*p
!= LIM_REG_CLASSES
)
2222 if (chain
->group_size
[(int) *p
] <= chain
->group_size
[class])
2223 chain
->need
.groups
[(int) *p
]--;
2227 /* Don't count these registers again. */
2228 for (j
= 0; j
< chain
->group_size
[class]; j
++)
2229 SET_HARD_REG_BIT (chain
->counted_for_groups
, i
+ j
);
2232 /* Skip to the last reg in this group. When i is incremented above,
2233 it will then point to the first reg of the next possible group. */
2238 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2239 another mode that needs to be reloaded for the same register class CLASS.
2240 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2241 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2243 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2244 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2245 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2246 causes unnecessary failures on machines requiring alignment of register
2247 groups when the two modes are different sizes, because the larger mode has
2248 more strict alignment rules than the smaller mode. */
2251 modes_equiv_for_class_p (allocate_mode
, other_mode
, class)
2252 enum machine_mode allocate_mode
, other_mode
;
2253 enum reg_class
class;
2256 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2258 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
)
2259 && HARD_REGNO_MODE_OK (regno
, allocate_mode
)
2260 && ! HARD_REGNO_MODE_OK (regno
, other_mode
))
2266 /* Handle the failure to find a register to spill.
2267 INSN should be one of the insns which needed this particular spill reg. */
2270 spill_failure (insn
)
2273 if (asm_noperands (PATTERN (insn
)) >= 0)
2274 error_for_asm (insn
, "`asm' needs too many reloads");
2276 fatal_insn ("Unable to find a register to spill.", insn
);
2279 /* Add a new register to the tables of available spill-registers.
2280 CHAIN is the insn for which the register will be used; we decrease the
2282 I is the index of this register in potential_reload_regs.
2283 CLASS is the regclass whose need is being satisfied.
2284 NONGROUP is 0 if this register is part of a group.
2285 DUMPFILE is the same as the one that `reload' got. */
2288 new_spill_reg (chain
, i
, class, nongroup
, dumpfile
)
2289 struct insn_chain
*chain
;
2295 register enum reg_class
*p
;
2296 int regno
= potential_reload_regs
[i
];
2298 if (i
>= FIRST_PSEUDO_REGISTER
)
2300 spill_failure (chain
->insn
);
2305 if (TEST_HARD_REG_BIT (bad_spill_regs
, regno
))
2307 static char *reg_class_names
[] = REG_CLASS_NAMES
;
2309 if (asm_noperands (PATTERN (chain
->insn
)) < 0)
2311 /* The error message is still correct - we know only that it wasn't
2312 an asm statement that caused the problem, but one of the global
2313 registers declared by the users might have screwed us. */
2314 error ("fixed or forbidden register %d (%s) was spilled for class %s.",
2315 regno
, reg_names
[regno
], reg_class_names
[class]);
2316 error ("This may be due to a compiler bug or to impossible asm");
2317 error ("statements or clauses.");
2318 fatal_insn ("This is the instruction:", chain
->insn
);
2320 error_for_asm (chain
->insn
, "Invalid `asm' statement:");
2321 error_for_asm (chain
->insn
,
2322 "fixed or forbidden register %d (%s) was spilled for class %s.",
2323 regno
, reg_names
[regno
], reg_class_names
[class]);
2328 /* Make reg REGNO an additional reload reg. */
2330 potential_reload_regs
[i
] = -1;
2331 spill_regs
[n_spills
] = regno
;
2332 spill_reg_order
[regno
] = n_spills
;
2334 fprintf (dumpfile
, "Spilling reg %d.\n", regno
);
2335 SET_HARD_REG_BIT (chain
->used_spill_regs
, regno
);
2337 /* Clear off the needs we just satisfied. */
2339 chain
->need
.regs
[0][class]--;
2340 p
= reg_class_superclasses
[class];
2341 while (*p
!= LIM_REG_CLASSES
)
2342 chain
->need
.regs
[0][(int) *p
++]--;
2344 if (nongroup
&& chain
->need
.regs
[1][class] > 0)
2346 SET_HARD_REG_BIT (chain
->counted_for_nongroups
, regno
);
2347 chain
->need
.regs
[1][class]--;
2348 p
= reg_class_superclasses
[class];
2349 while (*p
!= LIM_REG_CLASSES
)
2350 chain
->need
.regs
[1][(int) *p
++]--;
2356 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2357 data that is dead in INSN. */
2360 delete_dead_insn (insn
)
2363 rtx prev
= prev_real_insn (insn
);
2366 /* If the previous insn sets a register that dies in our insn, delete it
2368 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2369 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
2370 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2371 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2372 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2373 delete_dead_insn (prev
);
2375 PUT_CODE (insn
, NOTE
);
2376 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2377 NOTE_SOURCE_FILE (insn
) = 0;
2380 /* Modify the home of pseudo-reg I.
2381 The new home is present in reg_renumber[I].
2383 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2384 or it may be -1, meaning there is none or it is not relevant.
2385 This is used so that all pseudos spilled from a given hard reg
2386 can share one stack slot. */
2389 alter_reg (i
, from_reg
)
2393 /* When outputting an inline function, this can happen
2394 for a reg that isn't actually used. */
2395 if (regno_reg_rtx
[i
] == 0)
2398 /* If the reg got changed to a MEM at rtl-generation time,
2400 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
2403 /* Modify the reg-rtx to contain the new hard reg
2404 number or else to contain its pseudo reg number. */
2405 REGNO (regno_reg_rtx
[i
])
2406 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
2408 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2409 allocate a stack slot for it. */
2411 if (reg_renumber
[i
] < 0
2412 && REG_N_REFS (i
) > 0
2413 && reg_equiv_constant
[i
] == 0
2414 && reg_equiv_memory_loc
[i
] == 0)
2417 int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2418 int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2421 /* Each pseudo reg has an inherent size which comes from its own mode,
2422 and a total size which provides room for paradoxical subregs
2423 which refer to the pseudo reg in wider modes.
2425 We can use a slot already allocated if it provides both
2426 enough inherent space and enough total space.
2427 Otherwise, we allocate a new slot, making sure that it has no less
2428 inherent space, and no less total space, then the previous slot. */
2431 /* No known place to spill from => no slot to reuse. */
2432 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
,
2433 inherent_size
== total_size
? 0 : -1);
2434 if (BYTES_BIG_ENDIAN
)
2435 /* Cancel the big-endian correction done in assign_stack_local.
2436 Get the address of the beginning of the slot.
2437 This is so we can do a big-endian correction unconditionally
2439 adjust
= inherent_size
- total_size
;
2441 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2443 /* Reuse a stack slot if possible. */
2444 else if (spill_stack_slot
[from_reg
] != 0
2445 && spill_stack_slot_width
[from_reg
] >= total_size
2446 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2448 x
= spill_stack_slot
[from_reg
];
2449 /* Allocate a bigger slot. */
2452 /* Compute maximum size needed, both for inherent size
2453 and for total size. */
2454 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2456 if (spill_stack_slot
[from_reg
])
2458 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2460 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2461 if (spill_stack_slot_width
[from_reg
] > total_size
)
2462 total_size
= spill_stack_slot_width
[from_reg
];
2464 /* Make a slot with that size. */
2465 x
= assign_stack_local (mode
, total_size
,
2466 inherent_size
== total_size
? 0 : -1);
2468 if (BYTES_BIG_ENDIAN
)
2470 /* Cancel the big-endian correction done in assign_stack_local.
2471 Get the address of the beginning of the slot.
2472 This is so we can do a big-endian correction unconditionally
2474 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2476 stack_slot
= gen_rtx_MEM (mode_for_size (total_size
2479 plus_constant (XEXP (x
, 0), adjust
));
2481 spill_stack_slot
[from_reg
] = stack_slot
;
2482 spill_stack_slot_width
[from_reg
] = total_size
;
2485 /* On a big endian machine, the "address" of the slot
2486 is the address of the low part that fits its inherent mode. */
2487 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2488 adjust
+= (total_size
- inherent_size
);
2490 /* If we have any adjustment to make, or if the stack slot is the
2491 wrong mode, make a new stack slot. */
2492 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
2494 x
= gen_rtx_MEM (GET_MODE (regno_reg_rtx
[i
]),
2495 plus_constant (XEXP (x
, 0), adjust
));
2497 /* If this was shared among registers, must ensure we never
2498 set it readonly since that can cause scheduling
2499 problems. Note we would only have in this adjustment
2500 case in any event, since the code above doesn't set it. */
2503 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2506 /* Save the stack slot for later. */
2507 reg_equiv_memory_loc
[i
] = x
;
2511 /* Mark the slots in regs_ever_live for the hard regs
2512 used by pseudo-reg number REGNO. */
2515 mark_home_live (regno
)
2518 register int i
, lim
;
2519 i
= reg_renumber
[regno
];
2522 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2524 regs_ever_live
[i
++] = 1;
2527 /* This function handles the tracking of elimination offsets around branches.
2529 X is a piece of RTL being scanned.
2531 INSN is the insn that it came from, if any.
2533 INITIAL_P is non-zero if we are to set the offset to be the initial
2534 offset and zero if we are setting the offset of the label to be the
2538 set_label_offsets (x
, insn
, initial_p
)
2543 enum rtx_code code
= GET_CODE (x
);
2546 struct elim_table
*p
;
2551 if (LABEL_REF_NONLOCAL_P (x
))
2556 /* ... fall through ... */
2559 /* If we know nothing about this label, set the desired offsets. Note
2560 that this sets the offset at a label to be the offset before a label
2561 if we don't know anything about the label. This is not correct for
2562 the label after a BARRIER, but is the best guess we can make. If
2563 we guessed wrong, we will suppress an elimination that might have
2564 been possible had we been able to guess correctly. */
2566 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2568 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2569 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2570 = (initial_p
? reg_eliminate
[i
].initial_offset
2571 : reg_eliminate
[i
].offset
);
2572 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2575 /* Otherwise, if this is the definition of a label and it is
2576 preceded by a BARRIER, set our offsets to the known offset of
2580 && (tem
= prev_nonnote_insn (insn
)) != 0
2581 && GET_CODE (tem
) == BARRIER
)
2582 set_offsets_for_label (insn
);
2584 /* If neither of the above cases is true, compare each offset
2585 with those previously recorded and suppress any eliminations
2586 where the offsets disagree. */
2588 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2589 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2590 != (initial_p
? reg_eliminate
[i
].initial_offset
2591 : reg_eliminate
[i
].offset
))
2592 reg_eliminate
[i
].can_eliminate
= 0;
2597 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2599 /* ... fall through ... */
2603 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2604 and hence must have all eliminations at their initial offsets. */
2605 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2606 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2607 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2612 /* Each of the labels in the address vector must be at their initial
2613 offsets. We want the first field for ADDR_VEC and the second
2614 field for ADDR_DIFF_VEC. */
2616 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2617 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2622 /* We only care about setting PC. If the source is not RETURN,
2623 IF_THEN_ELSE, or a label, disable any eliminations not at
2624 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2625 isn't one of those possibilities. For branches to a label,
2626 call ourselves recursively.
2628 Note that this can disable elimination unnecessarily when we have
2629 a non-local goto since it will look like a non-constant jump to
2630 someplace in the current function. This isn't a significant
2631 problem since such jumps will normally be when all elimination
2632 pairs are back to their initial offsets. */
2634 if (SET_DEST (x
) != pc_rtx
)
2637 switch (GET_CODE (SET_SRC (x
)))
2644 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2648 tem
= XEXP (SET_SRC (x
), 1);
2649 if (GET_CODE (tem
) == LABEL_REF
)
2650 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2651 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2654 tem
= XEXP (SET_SRC (x
), 2);
2655 if (GET_CODE (tem
) == LABEL_REF
)
2656 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2657 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2665 /* If we reach here, all eliminations must be at their initial
2666 offset because we are doing a jump to a variable address. */
2667 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2668 if (p
->offset
!= p
->initial_offset
)
2669 p
->can_eliminate
= 0;
2677 /* Used for communication between the next two function to properly share
2678 the vector for an ASM_OPERANDS. */
2680 static struct rtvec_def
*old_asm_operands_vec
, *new_asm_operands_vec
;
2682 /* Scan X and replace any eliminable registers (such as fp) with a
2683 replacement (such as sp), plus an offset.
2685 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2686 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2687 MEM, we are allowed to replace a sum of a register and the constant zero
2688 with the register, which we cannot do outside a MEM. In addition, we need
2689 to record the fact that a register is referenced outside a MEM.
2691 If INSN is an insn, it is the insn containing X. If we replace a REG
2692 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2693 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2694 the REG is being modified.
2696 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2697 That's used when we eliminate in expressions stored in notes.
2698 This means, do not set ref_outside_mem even if the reference
2701 If we see a modification to a register we know about, take the
2702 appropriate action (see case SET, below).
2704 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2705 replacements done assuming all offsets are at their initial values. If
2706 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2707 encounter, return the actual location so that find_reloads will do
2708 the proper thing. */
2711 eliminate_regs (x
, mem_mode
, insn
)
2713 enum machine_mode mem_mode
;
2716 enum rtx_code code
= GET_CODE (x
);
2717 struct elim_table
*ep
;
2724 if (! current_function_decl
)
2743 /* This is only for the benefit of the debugging backends, which call
2744 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2745 removed after CSE. */
2746 new = eliminate_regs (XEXP (x
, 0), 0, insn
);
2747 if (GET_CODE (new) == MEM
)
2748 return XEXP (new, 0);
2754 /* First handle the case where we encounter a bare register that
2755 is eliminable. Replace it with a PLUS. */
2756 if (regno
< FIRST_PSEUDO_REGISTER
)
2758 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2760 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2763 /* Refs inside notes don't count for this purpose. */
2764 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2765 || GET_CODE (insn
) == INSN_LIST
)))
2766 ep
->ref_outside_mem
= 1;
2767 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2771 else if (reg_renumber
[regno
] < 0 && reg_equiv_constant
2772 && reg_equiv_constant
[regno
]
2773 && ! CONSTANT_P (reg_equiv_constant
[regno
]))
2774 return eliminate_regs (copy_rtx (reg_equiv_constant
[regno
]),
2779 /* If this is the sum of an eliminable register and a constant, rework
2781 if (GET_CODE (XEXP (x
, 0)) == REG
2782 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2783 && CONSTANT_P (XEXP (x
, 1)))
2785 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2787 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2790 /* Refs inside notes don't count for this purpose. */
2791 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2792 || GET_CODE (insn
) == INSN_LIST
)))
2793 ep
->ref_outside_mem
= 1;
2795 /* The only time we want to replace a PLUS with a REG (this
2796 occurs when the constant operand of the PLUS is the negative
2797 of the offset) is when we are inside a MEM. We won't want
2798 to do so at other times because that would change the
2799 structure of the insn in a way that reload can't handle.
2800 We special-case the commonest situation in
2801 eliminate_regs_in_insn, so just replace a PLUS with a
2802 PLUS here, unless inside a MEM. */
2803 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2804 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2807 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2808 plus_constant (XEXP (x
, 1),
2809 ep
->previous_offset
));
2812 /* If the register is not eliminable, we are done since the other
2813 operand is a constant. */
2817 /* If this is part of an address, we want to bring any constant to the
2818 outermost PLUS. We will do this by doing register replacement in
2819 our operands and seeing if a constant shows up in one of them.
2821 We assume here this is part of an address (or a "load address" insn)
2822 since an eliminable register is not likely to appear in any other
2825 If we have (plus (eliminable) (reg)), we want to produce
2826 (plus (plus (replacement) (reg) (const))). If this was part of a
2827 normal add insn, (plus (replacement) (reg)) will be pushed as a
2828 reload. This is the desired action. */
2831 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2832 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2834 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2836 /* If one side is a PLUS and the other side is a pseudo that
2837 didn't get a hard register but has a reg_equiv_constant,
2838 we must replace the constant here since it may no longer
2839 be in the position of any operand. */
2840 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2841 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2842 && reg_renumber
[REGNO (new1
)] < 0
2843 && reg_equiv_constant
!= 0
2844 && reg_equiv_constant
[REGNO (new1
)] != 0)
2845 new1
= reg_equiv_constant
[REGNO (new1
)];
2846 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2847 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2848 && reg_renumber
[REGNO (new0
)] < 0
2849 && reg_equiv_constant
[REGNO (new0
)] != 0)
2850 new0
= reg_equiv_constant
[REGNO (new0
)];
2852 new = form_sum (new0
, new1
);
2854 /* As above, if we are not inside a MEM we do not want to
2855 turn a PLUS into something else. We might try to do so here
2856 for an addition of 0 if we aren't optimizing. */
2857 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2858 return gen_rtx_PLUS (GET_MODE (x
), new, const0_rtx
);
2866 /* If this is the product of an eliminable register and a
2867 constant, apply the distribute law and move the constant out
2868 so that we have (plus (mult ..) ..). This is needed in order
2869 to keep load-address insns valid. This case is pathological.
2870 We ignore the possibility of overflow here. */
2871 if (GET_CODE (XEXP (x
, 0)) == REG
2872 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2873 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2874 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2876 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2879 /* Refs inside notes don't count for this purpose. */
2880 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2881 || GET_CODE (insn
) == INSN_LIST
)))
2882 ep
->ref_outside_mem
= 1;
2885 plus_constant (gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2886 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2889 /* ... fall through ... */
2894 case DIV
: case UDIV
:
2895 case MOD
: case UMOD
:
2896 case AND
: case IOR
: case XOR
:
2897 case ROTATERT
: case ROTATE
:
2898 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2900 case GE
: case GT
: case GEU
: case GTU
:
2901 case LE
: case LT
: case LEU
: case LTU
:
2903 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2905 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
) : 0;
2907 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2908 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2913 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2916 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2917 if (new != XEXP (x
, 0))
2919 /* If this is a REG_DEAD note, it is not valid anymore.
2920 Using the eliminated version could result in creating a
2921 REG_DEAD note for the stack or frame pointer. */
2922 if (GET_MODE (x
) == REG_DEAD
)
2924 ? eliminate_regs (XEXP (x
, 1), mem_mode
, insn
)
2927 x
= gen_rtx_EXPR_LIST (REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2931 /* ... fall through ... */
2934 /* Now do eliminations in the rest of the chain. If this was
2935 an EXPR_LIST, this might result in allocating more memory than is
2936 strictly needed, but it simplifies the code. */
2939 new = eliminate_regs (XEXP (x
, 1), mem_mode
, insn
);
2940 if (new != XEXP (x
, 1))
2941 return gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new);
2949 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2950 if (ep
->to_rtx
== XEXP (x
, 0))
2952 int size
= GET_MODE_SIZE (mem_mode
);
2954 /* If more bytes than MEM_MODE are pushed, account for them. */
2955 #ifdef PUSH_ROUNDING
2956 if (ep
->to_rtx
== stack_pointer_rtx
)
2957 size
= PUSH_ROUNDING (size
);
2959 if (code
== PRE_DEC
|| code
== POST_DEC
)
2965 /* Fall through to generic unary operation case. */
2966 case STRICT_LOW_PART
:
2968 case SIGN_EXTEND
: case ZERO_EXTEND
:
2969 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2970 case FLOAT
: case FIX
:
2971 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2975 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
2976 if (new != XEXP (x
, 0))
2977 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
2981 /* Similar to above processing, but preserve SUBREG_WORD.
2982 Convert (subreg (mem)) to (mem) if not paradoxical.
2983 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2984 pseudo didn't get a hard reg, we must replace this with the
2985 eliminated version of the memory location because push_reloads
2986 may do the replacement in certain circumstances. */
2987 if (GET_CODE (SUBREG_REG (x
)) == REG
2988 && (GET_MODE_SIZE (GET_MODE (x
))
2989 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2990 && reg_equiv_memory_loc
!= 0
2991 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2994 new = eliminate_regs (reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))],
2997 /* If we didn't change anything, we must retain the pseudo. */
2998 if (new == reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))])
2999 new = SUBREG_REG (x
);
3002 /* In this case, we must show that the pseudo is used in this
3003 insn so that delete_output_reload will do the right thing. */
3004 if (insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
3005 && GET_CODE (insn
) != INSN_LIST
)
3006 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode
,
3009 = gen_rtx_EXPR_LIST (REG_EQUAL
, new, NULL_RTX
);
3011 /* Ensure NEW isn't shared in case we have to reload it. */
3012 new = copy_rtx (new);
3015 new = SUBREG_REG (x
);
3019 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, insn
);
3021 if (new != XEXP (x
, 0))
3023 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
3024 int new_size
= GET_MODE_SIZE (GET_MODE (new));
3026 if (GET_CODE (new) == MEM
3027 && ((x_size
< new_size
3028 #ifdef WORD_REGISTER_OPERATIONS
3029 /* On these machines, combine can create rtl of the form
3030 (set (subreg:m1 (reg:m2 R) 0) ...)
3031 where m1 < m2, and expects something interesting to
3032 happen to the entire word. Moreover, it will use the
3033 (reg:m2 R) later, expecting all bits to be preserved.
3034 So if the number of words is the same, preserve the
3035 subreg so that push_reloads can see it. */
3036 && ! ((x_size
-1)/UNITS_PER_WORD
== (new_size
-1)/UNITS_PER_WORD
)
3039 || (x_size
== new_size
))
3042 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
3043 enum machine_mode mode
= GET_MODE (x
);
3045 if (BYTES_BIG_ENDIAN
)
3046 offset
+= (MIN (UNITS_PER_WORD
,
3047 GET_MODE_SIZE (GET_MODE (new)))
3048 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
3050 PUT_MODE (new, mode
);
3051 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
3055 return gen_rtx_SUBREG (GET_MODE (x
), new, SUBREG_WORD (x
));
3061 /* If using a register that is the source of an eliminate we still
3062 think can be performed, note it cannot be performed since we don't
3063 know how this register is used. */
3064 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3065 if (ep
->from_rtx
== XEXP (x
, 0))
3066 ep
->can_eliminate
= 0;
3068 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3069 if (new != XEXP (x
, 0))
3070 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3074 /* If clobbering a register that is the replacement register for an
3075 elimination we still think can be performed, note that it cannot
3076 be performed. Otherwise, we need not be concerned about it. */
3077 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3078 if (ep
->to_rtx
== XEXP (x
, 0))
3079 ep
->can_eliminate
= 0;
3081 new = eliminate_regs (XEXP (x
, 0), mem_mode
, insn
);
3082 if (new != XEXP (x
, 0))
3083 return gen_rtx_fmt_e (code
, GET_MODE (x
), new);
3089 /* Properly handle sharing input and constraint vectors. */
3090 if (ASM_OPERANDS_INPUT_VEC (x
) != old_asm_operands_vec
)
3092 /* When we come to a new vector not seen before,
3093 scan all its elements; keep the old vector if none
3094 of them changes; otherwise, make a copy. */
3095 old_asm_operands_vec
= ASM_OPERANDS_INPUT_VEC (x
);
3096 temp_vec
= (rtx
*) alloca (XVECLEN (x
, 3) * sizeof (rtx
));
3097 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
3098 temp_vec
[i
] = eliminate_regs (ASM_OPERANDS_INPUT (x
, i
),
3101 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
3102 if (temp_vec
[i
] != ASM_OPERANDS_INPUT (x
, i
))
3105 if (i
== ASM_OPERANDS_INPUT_LENGTH (x
))
3106 new_asm_operands_vec
= old_asm_operands_vec
;
3108 new_asm_operands_vec
3109 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x
), temp_vec
);
3112 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
3113 if (new_asm_operands_vec
== old_asm_operands_vec
)
3116 new = gen_rtx_ASM_OPERANDS (VOIDmode
, ASM_OPERANDS_TEMPLATE (x
),
3117 ASM_OPERANDS_OUTPUT_CONSTRAINT (x
),
3118 ASM_OPERANDS_OUTPUT_IDX (x
),
3119 new_asm_operands_vec
,
3120 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x
),
3121 ASM_OPERANDS_SOURCE_FILE (x
),
3122 ASM_OPERANDS_SOURCE_LINE (x
));
3123 new->volatil
= x
->volatil
;
3128 /* Check for setting a register that we know about. */
3129 if (GET_CODE (SET_DEST (x
)) == REG
)
3131 /* See if this is setting the replacement register for an
3134 If DEST is the hard frame pointer, we do nothing because we
3135 assume that all assignments to the frame pointer are for
3136 non-local gotos and are being done at a time when they are valid
3137 and do not disturb anything else. Some machines want to
3138 eliminate a fake argument pointer (or even a fake frame pointer)
3139 with either the real frame or the stack pointer. Assignments to
3140 the hard frame pointer must not prevent this elimination. */
3142 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3144 if (ep
->to_rtx
== SET_DEST (x
)
3145 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3147 /* If it is being incremented, adjust the offset. Otherwise,
3148 this elimination can't be done. */
3149 rtx src
= SET_SRC (x
);
3151 if (GET_CODE (src
) == PLUS
3152 && XEXP (src
, 0) == SET_DEST (x
)
3153 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
3154 ep
->offset
-= INTVAL (XEXP (src
, 1));
3156 ep
->can_eliminate
= 0;
3159 /* Now check to see we are assigning to a register that can be
3160 eliminated. If so, it must be as part of a PARALLEL, since we
3161 will not have been called if this is a single SET. So indicate
3162 that we can no longer eliminate this reg. */
3163 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3165 if (ep
->from_rtx
== SET_DEST (x
) && ep
->can_eliminate
)
3166 ep
->can_eliminate
= 0;
3169 /* Now avoid the loop below in this common case. */
3171 rtx new0
= eliminate_regs (SET_DEST (x
), 0, insn
);
3172 rtx new1
= eliminate_regs (SET_SRC (x
), 0, insn
);
3174 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3175 write a CLOBBER insn. */
3176 if (GET_CODE (SET_DEST (x
)) == REG
&& GET_CODE (new0
) == MEM
3177 && insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
3178 && GET_CODE (insn
) != INSN_LIST
)
3179 emit_insn_after (gen_rtx_CLOBBER (VOIDmode
, SET_DEST (x
)), insn
);
3181 if (new0
!= SET_DEST (x
) || new1
!= SET_SRC (x
))
3182 return gen_rtx_SET (VOIDmode
, new0
, new1
);
3188 /* This is only for the benefit of the debugging backends, which call
3189 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
3190 removed after CSE. */
3191 if (GET_CODE (XEXP (x
, 0)) == ADDRESSOF
)
3192 return eliminate_regs (XEXP (XEXP (x
, 0), 0), 0, insn
);
3194 /* Our only special processing is to pass the mode of the MEM to our
3195 recursive call and copy the flags. While we are here, handle this
3196 case more efficiently. */
3197 new = eliminate_regs (XEXP (x
, 0), GET_MODE (x
), insn
);
3198 if (new != XEXP (x
, 0))
3200 new = gen_rtx_MEM (GET_MODE (x
), new);
3201 new->volatil
= x
->volatil
;
3202 new->unchanging
= x
->unchanging
;
3203 new->in_struct
= x
->in_struct
;
3213 /* Process each of our operands recursively. If any have changed, make a
3215 fmt
= GET_RTX_FORMAT (code
);
3216 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3220 new = eliminate_regs (XEXP (x
, i
), mem_mode
, insn
);
3221 if (new != XEXP (x
, i
) && ! copied
)
3223 rtx new_x
= rtx_alloc (code
);
3224 bcopy ((char *) x
, (char *) new_x
,
3225 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3226 + sizeof (new_x
->fld
[0]) * GET_RTX_LENGTH (code
)));
3232 else if (*fmt
== 'E')
3235 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3237 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
3238 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
3240 rtvec new_v
= gen_rtvec_vv (XVECLEN (x
, i
),
3244 rtx new_x
= rtx_alloc (code
);
3245 bcopy ((char *) x
, (char *) new_x
,
3246 (sizeof (*new_x
) - sizeof (new_x
->fld
)
3247 + (sizeof (new_x
->fld
[0])
3248 * GET_RTX_LENGTH (code
))));
3252 XVEC (x
, i
) = new_v
;
3255 XVECEXP (x
, i
, j
) = new;
3263 /* Scan INSN and eliminate all eliminable registers in it.
3265 If REPLACE is nonzero, do the replacement destructively. Also
3266 delete the insn as dead it if it is setting an eliminable register.
3268 If REPLACE is zero, do all our allocations in reload_obstack.
3270 If no eliminations were done and this insn doesn't require any elimination
3271 processing (these are not identical conditions: it might be updating sp,
3272 but not referencing fp; this needs to be seen during reload_as_needed so
3273 that the offset between fp and sp can be taken into consideration), zero
3274 is returned. Otherwise, 1 is returned. */
3277 eliminate_regs_in_insn (insn
, replace
)
3281 rtx old_body
= PATTERN (insn
);
3282 rtx old_set
= single_set (insn
);
3285 struct elim_table
*ep
;
3288 push_obstacks (&reload_obstack
, &reload_obstack
);
3290 if (old_set
!= 0 && GET_CODE (SET_DEST (old_set
)) == REG
3291 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3293 /* Check for setting an eliminable register. */
3294 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3295 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3297 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3298 /* If this is setting the frame pointer register to the
3299 hardware frame pointer register and this is an elimination
3300 that will be done (tested above), this insn is really
3301 adjusting the frame pointer downward to compensate for
3302 the adjustment done before a nonlocal goto. */
3303 if (ep
->from
== FRAME_POINTER_REGNUM
3304 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3306 rtx src
= SET_SRC (old_set
);
3307 int offset
= 0, ok
= 0;
3308 rtx prev_insn
, prev_set
;
3310 if (src
== ep
->to_rtx
)
3312 else if (GET_CODE (src
) == PLUS
3313 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3314 && XEXP (src
, 1) == ep
->to_rtx
)
3315 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3316 else if (GET_CODE (src
) == PLUS
3317 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3318 && XEXP (src
, 0) == ep
->to_rtx
)
3319 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3320 else if ((prev_insn
= prev_nonnote_insn (insn
)) != 0
3321 && (prev_set
= single_set (prev_insn
)) != 0
3322 && rtx_equal_p (SET_DEST (prev_set
), src
))
3324 src
= SET_SRC (prev_set
);
3325 if (src
== ep
->to_rtx
)
3327 else if (GET_CODE (src
) == PLUS
3328 && GET_CODE (XEXP (src
, 0)) == CONST_INT
3329 && XEXP (src
, 1) == ep
->to_rtx
)
3330 offset
= INTVAL (XEXP (src
, 0)), ok
= 1;
3331 else if (GET_CODE (src
) == PLUS
3332 && GET_CODE (XEXP (src
, 1)) == CONST_INT
3333 && XEXP (src
, 0) == ep
->to_rtx
)
3334 offset
= INTVAL (XEXP (src
, 1)), ok
= 1;
3342 = plus_constant (ep
->to_rtx
, offset
- ep
->offset
);
3344 /* First see if this insn remains valid when we
3345 make the change. If not, keep the INSN_CODE
3346 the same and let reload fit it up. */
3347 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3348 validate_change (insn
, &SET_DEST (old_set
),
3350 if (! apply_change_group ())
3352 SET_SRC (old_set
) = src
;
3353 SET_DEST (old_set
) = ep
->to_rtx
;
3363 /* In this case this insn isn't serving a useful purpose. We
3364 will delete it in reload_as_needed once we know that this
3365 elimination is, in fact, being done.
3367 If REPLACE isn't set, we can't delete this insn, but needn't
3368 process it since it won't be used unless something changes. */
3370 delete_dead_insn (insn
);
3375 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3376 in the insn is the negative of the offset in FROM. Substitute
3377 (set (reg) (reg to)) for the insn and change its code.
3379 We have to do this here, rather than in eliminate_regs, so that we can
3380 change the insn code. */
3382 if (GET_CODE (SET_SRC (old_set
)) == PLUS
3383 && GET_CODE (XEXP (SET_SRC (old_set
), 0)) == REG
3384 && GET_CODE (XEXP (SET_SRC (old_set
), 1)) == CONST_INT
)
3385 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3387 if (ep
->from_rtx
== XEXP (SET_SRC (old_set
), 0)
3388 && ep
->can_eliminate
)
3390 /* We must stop at the first elimination that will be used.
3391 If this one would replace the PLUS with a REG, do it
3392 now. Otherwise, quit the loop and let eliminate_regs
3393 do its normal replacement. */
3394 if (ep
->offset
== - INTVAL (XEXP (SET_SRC (old_set
), 1)))
3396 /* We assume here that we don't need a PARALLEL of
3397 any CLOBBERs for this assignment. There's not
3398 much we can do if we do need it. */
3399 PATTERN (insn
) = gen_rtx_SET (VOIDmode
,
3402 INSN_CODE (insn
) = -1;
3411 old_asm_operands_vec
= 0;
3413 /* Replace the body of this insn with a substituted form. If we changed
3414 something, return non-zero.
3416 If we are replacing a body that was a (set X (plus Y Z)), try to
3417 re-recognize the insn. We do this in case we had a simple addition
3418 but now can do this as a load-address. This saves an insn in this
3421 new_body
= eliminate_regs (old_body
, 0, replace
? insn
: NULL_RTX
);
3422 if (new_body
!= old_body
)
3424 /* If we aren't replacing things permanently and we changed something,
3425 make another copy to ensure that all the RTL is new. Otherwise
3426 things can go wrong if find_reload swaps commutative operands
3427 and one is inside RTL that has been copied while the other is not. */
3429 /* Don't copy an asm_operands because (1) there's no need and (2)
3430 copy_rtx can't do it properly when there are multiple outputs. */
3431 if (! replace
&& asm_noperands (old_body
) < 0)
3432 new_body
= copy_rtx (new_body
);
3434 /* If we had a move insn but now we don't, rerecognize it. This will
3435 cause spurious re-recognition if the old move had a PARALLEL since
3436 the new one still will, but we can't call single_set without
3437 having put NEW_BODY into the insn and the re-recognition won't
3438 hurt in this rare case. */
3440 && ((GET_CODE (SET_SRC (old_set
)) == REG
3441 && (GET_CODE (new_body
) != SET
3442 || GET_CODE (SET_SRC (new_body
)) != REG
))
3443 /* If this was a load from or store to memory, compare
3444 the MEM in recog_operand to the one in the insn. If they
3445 are not equal, then rerecognize the insn. */
3447 && ((GET_CODE (SET_SRC (old_set
)) == MEM
3448 && SET_SRC (old_set
) != recog_operand
[1])
3449 || (GET_CODE (SET_DEST (old_set
)) == MEM
3450 && SET_DEST (old_set
) != recog_operand
[0])))
3451 /* If this was an add insn before, rerecognize. */
3452 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3454 if (! validate_change (insn
, &PATTERN (insn
), new_body
, 0))
3455 /* If recognition fails, store the new body anyway.
3456 It's normal to have recognition failures here
3457 due to bizarre memory addresses; reloading will fix them. */
3458 PATTERN (insn
) = new_body
;
3461 PATTERN (insn
) = new_body
;
3466 /* Loop through all elimination pairs. See if any have changed.
3468 We also detect a cases where register elimination cannot be done,
3469 namely, if a register would be both changed and referenced outside a MEM
3470 in the resulting insn since such an insn is often undefined and, even if
3471 not, we cannot know what meaning will be given to it. Note that it is
3472 valid to have a register used in an address in an insn that changes it
3473 (presumably with a pre- or post-increment or decrement).
3475 If anything changes, return nonzero. */
3477 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3479 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3480 ep
->can_eliminate
= 0;
3482 ep
->ref_outside_mem
= 0;
3484 if (ep
->previous_offset
!= ep
->offset
)
3489 /* If we changed something, perform elimination in REG_NOTES. This is
3490 needed even when REPLACE is zero because a REG_DEAD note might refer
3491 to a register that we eliminate and could cause a different number
3492 of spill registers to be needed in the final reload pass than in
3494 if (val
&& REG_NOTES (insn
) != 0)
3495 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3503 /* Loop through all elimination pairs.
3504 Recalculate the number not at initial offset.
3506 Compute the maximum offset (minimum offset if the stack does not
3507 grow downward) for each elimination pair. */
3510 update_eliminable_offsets ()
3512 struct elim_table
*ep
;
3514 num_not_at_initial_offset
= 0;
3515 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3517 ep
->previous_offset
= ep
->offset
;
3518 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3519 num_not_at_initial_offset
++;
3523 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3524 replacement we currently believe is valid, mark it as not eliminable if X
3525 modifies DEST in any way other than by adding a constant integer to it.
3527 If DEST is the frame pointer, we do nothing because we assume that
3528 all assignments to the hard frame pointer are nonlocal gotos and are being
3529 done at a time when they are valid and do not disturb anything else.
3530 Some machines want to eliminate a fake argument pointer with either the
3531 frame or stack pointer. Assignments to the hard frame pointer must not
3532 prevent this elimination.
3534 Called via note_stores from reload before starting its passes to scan
3535 the insns of the function. */
3538 mark_not_eliminable (dest
, x
)
3542 register unsigned int i
;
3544 /* A SUBREG of a hard register here is just changing its mode. We should
3545 not see a SUBREG of an eliminable hard register, but check just in
3547 if (GET_CODE (dest
) == SUBREG
)
3548 dest
= SUBREG_REG (dest
);
3550 if (dest
== hard_frame_pointer_rtx
)
3553 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3554 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3555 && (GET_CODE (x
) != SET
3556 || GET_CODE (SET_SRC (x
)) != PLUS
3557 || XEXP (SET_SRC (x
), 0) != dest
3558 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3560 reg_eliminate
[i
].can_eliminate_previous
3561 = reg_eliminate
[i
].can_eliminate
= 0;
3566 /* Verify that the initial elimination offsets did not change since the
3567 last call to set_initial_elim_offsets. This is used to catch cases
3568 where something illegal happened during reload_as_needed that could
3569 cause incorrect code to be generated if we did not check for it. */
3571 verify_initial_elim_offsets ()
3575 #ifdef ELIMINABLE_REGS
3576 struct elim_table
*ep
;
3578 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3580 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3581 if (t
!= ep
->initial_offset
)
3585 INITIAL_FRAME_POINTER_OFFSET (t
);
3586 if (t
!= reg_eliminate
[0].initial_offset
)
3591 /* Reset all offsets on eliminable registers to their initial values. */
3593 set_initial_elim_offsets ()
3595 struct elim_table
*ep
= reg_eliminate
;
3597 #ifdef ELIMINABLE_REGS
3598 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3600 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3601 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3604 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3605 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3608 num_not_at_initial_offset
= 0;
3611 /* Initialize the known label offsets.
3612 Set a known offset for each forced label to be at the initial offset
3613 of each elimination. We do this because we assume that all
3614 computed jumps occur from a location where each elimination is
3615 at its initial offset.
3616 For all other labels, show that we don't know the offsets. */
3619 set_initial_label_offsets ()
3622 bzero ((char *) &offsets_known_at
[get_first_label_num ()], num_labels
);
3624 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
3626 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
3629 /* Set all elimination offsets to the known values for the code label given
3632 set_offsets_for_label (insn
)
3636 int label_nr
= CODE_LABEL_NUMBER (insn
);
3637 struct elim_table
*ep
;
3639 num_not_at_initial_offset
= 0;
3640 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3642 ep
->offset
= ep
->previous_offset
= offsets_at
[label_nr
][i
];
3643 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3644 num_not_at_initial_offset
++;
3648 /* See if anything that happened changes which eliminations are valid.
3649 For example, on the Sparc, whether or not the frame pointer can
3650 be eliminated can depend on what registers have been used. We need
3651 not check some conditions again (such as flag_omit_frame_pointer)
3652 since they can't have changed. */
3655 update_eliminables (pset
)
3658 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3659 int previous_frame_pointer_needed
= frame_pointer_needed
;
3661 struct elim_table
*ep
;
3663 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3664 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
3665 #ifdef ELIMINABLE_REGS
3666 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
3669 ep
->can_eliminate
= 0;
3671 /* Look for the case where we have discovered that we can't replace
3672 register A with register B and that means that we will now be
3673 trying to replace register A with register C. This means we can
3674 no longer replace register C with register B and we need to disable
3675 such an elimination, if it exists. This occurs often with A == ap,
3676 B == sp, and C == fp. */
3678 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3680 struct elim_table
*op
;
3681 register int new_to
= -1;
3683 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3685 /* Find the current elimination for ep->from, if there is a
3687 for (op
= reg_eliminate
;
3688 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3689 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3695 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3697 for (op
= reg_eliminate
;
3698 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3699 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3700 op
->can_eliminate
= 0;
3704 /* See if any registers that we thought we could eliminate the previous
3705 time are no longer eliminable. If so, something has changed and we
3706 must spill the register. Also, recompute the number of eliminable
3707 registers and see if the frame pointer is needed; it is if there is
3708 no elimination of the frame pointer that we can perform. */
3710 frame_pointer_needed
= 1;
3711 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3713 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
3714 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
3715 frame_pointer_needed
= 0;
3717 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3719 ep
->can_eliminate_previous
= 0;
3720 SET_HARD_REG_BIT (*pset
, ep
->from
);
3725 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3726 /* If we didn't need a frame pointer last time, but we do now, spill
3727 the hard frame pointer. */
3728 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3729 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3733 /* Initialize the table of registers to eliminate. */
3737 struct elim_table
*ep
;
3738 #ifdef ELIMINABLE_REGS
3739 struct elim_table_1
*ep1
;
3744 reg_eliminate
= (struct elim_table
*)
3745 xmalloc(sizeof(struct elim_table
) * NUM_ELIMINABLE_REGS
);
3746 bzero ((PTR
) reg_eliminate
,
3747 sizeof(struct elim_table
) * NUM_ELIMINABLE_REGS
);
3750 /* Does this function require a frame pointer? */
3752 frame_pointer_needed
= (! flag_omit_frame_pointer
3753 #ifdef EXIT_IGNORE_STACK
3754 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3755 and restore sp for alloca. So we can't eliminate
3756 the frame pointer in that case. At some point,
3757 we should improve this by emitting the
3758 sp-adjusting insns for this case. */
3759 || (current_function_calls_alloca
3760 && EXIT_IGNORE_STACK
)
3762 || FRAME_POINTER_REQUIRED
);
3766 #ifdef ELIMINABLE_REGS
3767 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3768 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3770 ep
->from
= ep1
->from
;
3772 ep
->can_eliminate
= ep
->can_eliminate_previous
3773 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
3774 && ! (ep
->to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
3777 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
3778 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
3779 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
3780 = ! frame_pointer_needed
;
3783 /* Count the number of eliminable registers and build the FROM and TO
3784 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3785 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3786 We depend on this. */
3787 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3789 num_eliminable
+= ep
->can_eliminate
;
3790 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
3791 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
3795 /* Kick all pseudos out of hard register REGNO.
3796 If DUMPFILE is nonzero, log actions taken on that file.
3798 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3799 because we found we can't eliminate some register. In the case, no pseudos
3800 are allowed to be in the register, even if they are only in a block that
3801 doesn't require spill registers, unlike the case when we are spilling this
3802 hard reg to produce another spill register.
3804 Return nonzero if any pseudos needed to be kicked out. */
3807 spill_hard_reg (regno
, dumpfile
, cant_eliminate
)
3816 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
3817 regs_ever_live
[regno
] = 1;
3820 /* Spill every pseudo reg that was allocated to this reg
3821 or to something that overlaps this reg. */
3823 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3824 if (reg_renumber
[i
] >= 0
3825 && reg_renumber
[i
] <= regno
3827 + HARD_REGNO_NREGS (reg_renumber
[i
],
3828 PSEUDO_REGNO_MODE (i
))
3830 SET_REGNO_REG_SET (spilled_pseudos
, i
);
3833 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3834 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3836 ior_hard_reg_set (set1
, set2
)
3837 HARD_REG_SET
*set1
, *set2
;
3839 IOR_HARD_REG_SET (*set1
, *set2
);
3842 /* After find_reload_regs has been run for all insn that need reloads,
3843 and/or spill_hard_regs was called, this function is used to actually
3844 spill pseudo registers and try to reallocate them. It also sets up the
3845 spill_regs array for use by choose_reload_regs. */
3848 finish_spills (global
, dumpfile
)
3852 struct insn_chain
*chain
;
3853 int something_changed
= 0;
3856 /* Build the spill_regs array for the function. */
3857 /* If there are some registers still to eliminate and one of the spill regs
3858 wasn't ever used before, additional stack space may have to be
3859 allocated to store this register. Thus, we may have changed the offset
3860 between the stack and frame pointers, so mark that something has changed.
3862 One might think that we need only set VAL to 1 if this is a call-used
3863 register. However, the set of registers that must be saved by the
3864 prologue is not identical to the call-used set. For example, the
3865 register used by the call insn for the return PC is a call-used register,
3866 but must be saved by the prologue. */
3869 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3870 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
3872 spill_reg_order
[i
] = n_spills
;
3873 spill_regs
[n_spills
++] = i
;
3874 if (num_eliminable
&& ! regs_ever_live
[i
])
3875 something_changed
= 1;
3876 regs_ever_live
[i
] = 1;
3879 spill_reg_order
[i
] = -1;
3881 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3882 if (REGNO_REG_SET_P (spilled_pseudos
, i
))
3884 /* Record the current hard register the pseudo is allocated to in
3885 pseudo_previous_regs so we avoid reallocating it to the same
3886 hard reg in a later pass. */
3887 if (reg_renumber
[i
] < 0)
3889 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
3890 /* Mark it as no longer having a hard register home. */
3891 reg_renumber
[i
] = -1;
3892 /* We will need to scan everything again. */
3893 something_changed
= 1;
3896 /* Retry global register allocation if possible. */
3899 bzero ((char *) pseudo_forbidden_regs
, max_regno
* sizeof (HARD_REG_SET
));
3900 /* For every insn that needs reloads, set the registers used as spill
3901 regs in pseudo_forbidden_regs for every pseudo live across the
3903 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
3905 EXECUTE_IF_SET_IN_REG_SET
3906 (chain
->live_before
, FIRST_PSEUDO_REGISTER
, i
,
3908 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3909 &chain
->used_spill_regs
);
3911 EXECUTE_IF_SET_IN_REG_SET
3912 (chain
->live_after
, FIRST_PSEUDO_REGISTER
, i
,
3914 ior_hard_reg_set (pseudo_forbidden_regs
+ i
,
3915 &chain
->used_spill_regs
);
3919 /* Retry allocating the spilled pseudos. For each reg, merge the
3920 various reg sets that indicate which hard regs can't be used,
3921 and call retry_global_alloc.
3922 We change spill_pseudos here to only contain pseudos that did not
3923 get a new hard register. */
3924 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3925 if (reg_old_renumber
[i
] != reg_renumber
[i
])
3927 HARD_REG_SET forbidden
;
3928 COPY_HARD_REG_SET (forbidden
, bad_spill_regs_global
);
3929 IOR_HARD_REG_SET (forbidden
, pseudo_forbidden_regs
[i
]);
3930 IOR_HARD_REG_SET (forbidden
, pseudo_previous_regs
[i
]);
3931 retry_global_alloc (i
, forbidden
);
3932 if (reg_renumber
[i
] >= 0)
3933 CLEAR_REGNO_REG_SET (spilled_pseudos
, i
);
3937 /* Fix up the register information in the insn chain.
3938 This involves deleting those of the spilled pseudos which did not get
3939 a new hard register home from the live_{before,after} sets. */
3940 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
3942 HARD_REG_SET used_by_pseudos
;
3943 HARD_REG_SET used_by_pseudos2
;
3945 AND_COMPL_REG_SET (chain
->live_before
, spilled_pseudos
);
3946 AND_COMPL_REG_SET (chain
->live_after
, spilled_pseudos
);
3948 /* Mark any unallocated hard regs as available for spills. That
3949 makes inheritance work somewhat better. */
3950 if (chain
->need_reload
)
3952 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, chain
->live_before
);
3953 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, chain
->live_after
);
3954 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
3956 /* Save the old value for the sanity test below. */
3957 COPY_HARD_REG_SET (used_by_pseudos2
, chain
->used_spill_regs
);
3959 compute_use_by_pseudos (&used_by_pseudos
, chain
->live_before
);
3960 compute_use_by_pseudos (&used_by_pseudos
, chain
->live_after
);
3961 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
3962 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
3964 /* Make sure we only enlarge the set. */
3965 GO_IF_HARD_REG_SUBSET (used_by_pseudos2
, chain
->used_spill_regs
, ok
);
3971 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3972 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3974 int regno
= reg_renumber
[i
];
3975 if (reg_old_renumber
[i
] == regno
)
3978 alter_reg (i
, reg_old_renumber
[i
]);
3979 reg_old_renumber
[i
] = regno
;
3983 fprintf (dumpfile
, " Register %d now on stack.\n\n", i
);
3985 fprintf (dumpfile
, " Register %d now in %d.\n\n",
3986 i
, reg_renumber
[i
]);
3990 return something_changed
;
3993 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3994 Also mark any hard registers used to store user variables as
3995 forbidden from being used for spill registers. */
3998 scan_paradoxical_subregs (x
)
4003 register enum rtx_code code
= GET_CODE (x
);
4009 if (SMALL_REGISTER_CLASSES
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
4010 && REG_USERVAR_P (x
))
4011 SET_HARD_REG_BIT (bad_spill_regs_global
, REGNO (x
));
4027 if (GET_CODE (SUBREG_REG (x
)) == REG
4028 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
4029 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4030 = GET_MODE_SIZE (GET_MODE (x
));
4037 fmt
= GET_RTX_FORMAT (code
);
4038 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4041 scan_paradoxical_subregs (XEXP (x
, i
));
4042 else if (fmt
[i
] == 'E')
4045 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
4046 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4052 hard_reg_use_compare (p1p
, p2p
)
4053 const GENERIC_PTR p1p
;
4054 const GENERIC_PTR p2p
;
4056 struct hard_reg_n_uses
*p1
= (struct hard_reg_n_uses
*)p1p
;
4057 struct hard_reg_n_uses
*p2
= (struct hard_reg_n_uses
*)p2p
;
4058 int bad1
= TEST_HARD_REG_BIT (bad_spill_regs
, p1
->regno
);
4059 int bad2
= TEST_HARD_REG_BIT (bad_spill_regs
, p2
->regno
);
4061 return p1
->regno
- p2
->regno
;
4066 if (p1
->uses
> p2
->uses
)
4068 if (p1
->uses
< p2
->uses
)
4070 /* If regs are equally good, sort by regno,
4071 so that the results of qsort leave nothing to chance. */
4072 return p1
->regno
- p2
->regno
;
4075 /* Used for communication between order_regs_for_reload and count_pseudo.
4076 Used to avoid counting one pseudo twice. */
4077 static regset pseudos_counted
;
4079 /* Update the costs in N_USES, considering that pseudo REG is live. */
4081 count_pseudo (n_uses
, reg
)
4082 struct hard_reg_n_uses
*n_uses
;
4085 int r
= reg_renumber
[reg
];
4088 if (REGNO_REG_SET_P (pseudos_counted
, reg
))
4090 SET_REGNO_REG_SET (pseudos_counted
, reg
);
4095 nregs
= HARD_REGNO_NREGS (r
, PSEUDO_REGNO_MODE (reg
));
4097 n_uses
[r
++].uses
+= REG_N_REFS (reg
);
4099 /* Choose the order to consider regs for use as reload registers
4100 based on how much trouble would be caused by spilling one.
4101 Store them in order of decreasing preference in potential_reload_regs. */
4104 order_regs_for_reload (chain
)
4105 struct insn_chain
*chain
;
4109 struct hard_reg_n_uses hard_reg_n_uses
[FIRST_PSEUDO_REGISTER
];
4111 pseudos_counted
= ALLOCA_REG_SET ();
4113 COPY_HARD_REG_SET (bad_spill_regs
, bad_spill_regs_global
);
4115 /* Count number of uses of each hard reg by pseudo regs allocated to it
4116 and then order them by decreasing use. */
4118 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4122 hard_reg_n_uses
[i
].regno
= i
;
4123 hard_reg_n_uses
[i
].uses
= 0;
4125 /* Test the various reasons why we can't use a register for
4126 spilling in this insn. */
4128 || REGNO_REG_SET_P (chain
->live_before
, i
)
4129 || REGNO_REG_SET_P (chain
->live_after
, i
))
4131 SET_HARD_REG_BIT (bad_spill_regs
, i
);
4135 /* Now find out which pseudos are allocated to it, and update
4137 CLEAR_REG_SET (pseudos_counted
);
4139 EXECUTE_IF_SET_IN_REG_SET
4140 (chain
->live_before
, FIRST_PSEUDO_REGISTER
, j
,
4142 count_pseudo (hard_reg_n_uses
, j
);
4144 EXECUTE_IF_SET_IN_REG_SET
4145 (chain
->live_after
, FIRST_PSEUDO_REGISTER
, j
,
4147 count_pseudo (hard_reg_n_uses
, j
);
4151 FREE_REG_SET (pseudos_counted
);
4153 /* Prefer registers not so far used, for use in temporary loading.
4154 Among them, if REG_ALLOC_ORDER is defined, use that order.
4155 Otherwise, prefer registers not preserved by calls. */
4157 #ifdef REG_ALLOC_ORDER
4158 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4160 int regno
= reg_alloc_order
[i
];
4162 if (hard_reg_n_uses
[regno
].uses
== 0
4163 && ! TEST_HARD_REG_BIT (bad_spill_regs
, regno
))
4164 potential_reload_regs
[o
++] = regno
;
4167 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4169 if (hard_reg_n_uses
[i
].uses
== 0 && call_used_regs
[i
]
4170 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
))
4171 potential_reload_regs
[o
++] = i
;
4173 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4175 if (hard_reg_n_uses
[i
].uses
== 0 && ! call_used_regs
[i
]
4176 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
))
4177 potential_reload_regs
[o
++] = i
;
4181 qsort (hard_reg_n_uses
, FIRST_PSEUDO_REGISTER
,
4182 sizeof hard_reg_n_uses
[0], hard_reg_use_compare
);
4184 /* Now add the regs that are already used,
4185 preferring those used less often. The fixed and otherwise forbidden
4186 registers will be at the end of this list. */
4188 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4189 if (hard_reg_n_uses
[i
].uses
!= 0
4190 && ! TEST_HARD_REG_BIT (bad_spill_regs
, hard_reg_n_uses
[i
].regno
))
4191 potential_reload_regs
[o
++] = hard_reg_n_uses
[i
].regno
;
4192 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4193 if (TEST_HARD_REG_BIT (bad_spill_regs
, hard_reg_n_uses
[i
].regno
))
4194 potential_reload_regs
[o
++] = hard_reg_n_uses
[i
].regno
;
4197 /* Reload pseudo-registers into hard regs around each insn as needed.
4198 Additional register load insns are output before the insn that needs it
4199 and perhaps store insns after insns that modify the reloaded pseudo reg.
4201 reg_last_reload_reg and reg_reloaded_contents keep track of
4202 which registers are already available in reload registers.
4203 We update these for the reloads that we perform,
4204 as the insns are scanned. */
4207 reload_as_needed (live_known
)
4210 struct insn_chain
*chain
;
4211 #if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P)
4216 bzero ((char *) spill_reg_rtx
, sizeof spill_reg_rtx
);
4217 bzero ((char *) spill_reg_store
, sizeof spill_reg_store
);
4218 reg_last_reload_reg
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
4219 bzero ((char *) reg_last_reload_reg
, max_regno
* sizeof (rtx
));
4220 reg_has_output_reload
= (char *) alloca (max_regno
);
4221 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4223 set_initial_elim_offsets ();
4225 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4228 rtx insn
= chain
->insn
;
4229 rtx old_next
= NEXT_INSN (insn
);
4231 /* If we pass a label, copy the offsets from the label information
4232 into the current offsets of each elimination. */
4233 if (GET_CODE (insn
) == CODE_LABEL
)
4234 set_offsets_for_label (insn
);
4236 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
4238 rtx oldpat
= PATTERN (insn
);
4240 /* If this is a USE and CLOBBER of a MEM, ensure that any
4241 references to eliminable registers have been removed. */
4243 if ((GET_CODE (PATTERN (insn
)) == USE
4244 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4245 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
4246 XEXP (XEXP (PATTERN (insn
), 0), 0)
4247 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4248 GET_MODE (XEXP (PATTERN (insn
), 0)),
4251 /* If we need to do register elimination processing, do so.
4252 This might delete the insn, in which case we are done. */
4253 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4255 eliminate_regs_in_insn (insn
, 1);
4256 if (GET_CODE (insn
) == NOTE
)
4258 update_eliminable_offsets ();
4263 /* If need_elim is nonzero but need_reload is zero, one might think
4264 that we could simply set n_reloads to 0. However, find_reloads
4265 could have done some manipulation of the insn (such as swapping
4266 commutative operands), and these manipulations are lost during
4267 the first pass for every insn that needs register elimination.
4268 So the actions of find_reloads must be redone here. */
4270 if (! chain
->need_elim
&& ! chain
->need_reload
4271 && ! chain
->need_operand_change
)
4273 /* First find the pseudo regs that must be reloaded for this insn.
4274 This info is returned in the tables reload_... (see reload.h).
4275 Also modify the body of INSN by substituting RELOAD
4276 rtx's for those pseudo regs. */
4279 bzero (reg_has_output_reload
, max_regno
);
4280 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4282 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4286 if (num_eliminable
&& chain
->need_elim
)
4287 update_eliminable_offsets ();
4291 rtx next
= NEXT_INSN (insn
);
4294 prev
= PREV_INSN (insn
);
4296 /* Now compute which reload regs to reload them into. Perhaps
4297 reusing reload regs from previous insns, or else output
4298 load insns to reload them. Maybe output store insns too.
4299 Record the choices of reload reg in reload_reg_rtx. */
4300 choose_reload_regs (chain
);
4302 /* Merge any reloads that we didn't combine for fear of
4303 increasing the number of spill registers needed but now
4304 discover can be safely merged. */
4305 if (SMALL_REGISTER_CLASSES
)
4306 merge_assigned_reloads (insn
);
4308 /* Generate the insns to reload operands into or out of
4309 their reload regs. */
4310 emit_reload_insns (chain
);
4312 /* Substitute the chosen reload regs from reload_reg_rtx
4313 into the insn's body (or perhaps into the bodies of other
4314 load and store insn that we just made for reloading
4315 and that we moved the structure into). */
4318 /* If this was an ASM, make sure that all the reload insns
4319 we have generated are valid. If not, give an error
4322 if (asm_noperands (PATTERN (insn
)) >= 0)
4323 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
4324 if (p
!= insn
&& GET_RTX_CLASS (GET_CODE (p
)) == 'i'
4325 && (recog_memoized (p
) < 0
4326 || (extract_insn (p
), ! constrain_operands (1))))
4328 error_for_asm (insn
,
4329 "`asm' operand requires impossible reload");
4331 NOTE_SOURCE_FILE (p
) = 0;
4332 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
4335 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4336 is no longer validly lying around to save a future reload.
4337 Note that this does not detect pseudos that were reloaded
4338 for this insn in order to be stored in
4339 (obeying register constraints). That is correct; such reload
4340 registers ARE still valid. */
4341 note_stores (oldpat
, forget_old_reloads_1
);
4343 /* There may have been CLOBBER insns placed after INSN. So scan
4344 between INSN and NEXT and use them to forget old reloads. */
4345 for (x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4346 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
4347 note_stores (PATTERN (x
), forget_old_reloads_1
);
4350 /* Likewise for regs altered by auto-increment in this insn.
4351 REG_INC notes have been changed by reloading:
4352 find_reloads_address_1 records substitutions for them,
4353 which have been performed by subst_reloads above. */
4354 for (i
= n_reloads
- 1; i
>= 0; i
--)
4356 rtx in_reg
= reload_in_reg
[i
];
4359 enum rtx_code code
= GET_CODE (in_reg
);
4360 /* PRE_INC / PRE_DEC will have the reload register ending up
4361 with the same value as the stack slot, but that doesn't
4362 hold true for POST_INC / POST_DEC. Either we have to
4363 convert the memory access to a true POST_INC / POST_DEC,
4364 or we can't use the reload register for inheritance. */
4365 if ((code
== POST_INC
|| code
== POST_DEC
)
4366 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4367 REGNO (reload_reg_rtx
[i
]))
4368 /* Make sure it is the inc/dec pseudo, and not
4369 some other (e.g. output operand) pseudo. */
4370 && (reg_reloaded_contents
[REGNO (reload_reg_rtx
[i
])]
4371 == REGNO (XEXP (in_reg
, 0))))
4374 rtx reload_reg
= reload_reg_rtx
[i
];
4375 enum machine_mode mode
= GET_MODE (reload_reg
);
4379 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4381 /* We really want to ignore REG_INC notes here, so
4382 use PATTERN (p) as argument to reg_set_p . */
4383 if (reg_set_p (reload_reg
, PATTERN (p
)))
4385 n
= count_occurrences (PATTERN (p
), reload_reg
);
4390 n
= validate_replace_rtx (reload_reg
,
4391 gen_rtx (code
, mode
,
4395 /* We must also verify that the constraints
4396 are met after the replacement. */
4399 n
= constrain_operands (1);
4403 /* If the constraints were not met, then
4404 undo the replacement. */
4407 validate_replace_rtx (gen_rtx (code
, mode
,
4419 = gen_rtx_EXPR_LIST (REG_INC
, reload_reg
,
4421 /* Mark this as having an output reload so that the
4422 REG_INC processing code below won't invalidate
4423 the reload for inheritance. */
4424 SET_HARD_REG_BIT (reg_is_output_reload
,
4425 REGNO (reload_reg
));
4426 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4429 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
);
4431 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4432 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4433 REGNO (reload_reg_rtx
[i
]))
4434 /* Make sure it is the inc/dec pseudo, and not
4435 some other (e.g. output operand) pseudo. */
4436 && (reg_reloaded_contents
[REGNO (reload_reg_rtx
[i
])]
4437 == REGNO (XEXP (in_reg
, 0))))
4439 SET_HARD_REG_BIT (reg_is_output_reload
,
4440 REGNO (reload_reg_rtx
[i
]));
4441 reg_has_output_reload
[REGNO (XEXP (in_reg
, 0))] = 1;
4445 /* If a pseudo that got a hard register is auto-incremented,
4446 we must purge records of copying it into pseudos without
4448 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4449 if (REG_NOTE_KIND (x
) == REG_INC
)
4451 /* See if this pseudo reg was reloaded in this insn.
4452 If so, its last-reload info is still valid
4453 because it is based on this insn's reload. */
4454 for (i
= 0; i
< n_reloads
; i
++)
4455 if (reload_out
[i
] == XEXP (x
, 0))
4459 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
);
4463 /* A reload reg's contents are unknown after a label. */
4464 if (GET_CODE (insn
) == CODE_LABEL
)
4465 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4467 /* Don't assume a reload reg is still good after a call insn
4468 if it is a call-used reg. */
4469 else if (GET_CODE (insn
) == CALL_INSN
)
4470 AND_COMPL_HARD_REG_SET(reg_reloaded_valid
, call_used_reg_set
);
4472 /* In case registers overlap, allow certain insns to invalidate
4473 particular hard registers. */
4475 #ifdef INSN_CLOBBERS_REGNO_P
4476 for (i
= 0 ; i
< FIRST_PSEUDO_REGISTER
; i
++)
4477 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
4478 && INSN_CLOBBERS_REGNO_P (insn
, i
))
4479 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
);
4488 /* Discard all record of any value reloaded from X,
4489 or reloaded in X from someplace else;
4490 unless X is an output reload reg of the current insn.
4492 X may be a hard reg (the reload reg)
4493 or it may be a pseudo reg that was reloaded from. */
4496 forget_old_reloads_1 (x
, ignored
)
4498 rtx ignored ATTRIBUTE_UNUSED
;
4504 /* note_stores does give us subregs of hard regs. */
4505 while (GET_CODE (x
) == SUBREG
)
4507 offset
+= SUBREG_WORD (x
);
4511 if (GET_CODE (x
) != REG
)
4514 regno
= REGNO (x
) + offset
;
4516 if (regno
>= FIRST_PSEUDO_REGISTER
)
4521 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
4522 /* Storing into a spilled-reg invalidates its contents.
4523 This can happen if a block-local pseudo is allocated to that reg
4524 and it wasn't spilled because this block's total need is 0.
4525 Then some insn might have an optional reload and use this reg. */
4526 for (i
= 0; i
< nr
; i
++)
4527 /* But don't do this if the reg actually serves as an output
4528 reload reg in the current instruction. */
4530 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4531 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4534 /* Since value of X has changed,
4535 forget any value previously copied from it. */
4538 /* But don't forget a copy if this is the output reload
4539 that establishes the copy's validity. */
4540 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
4541 reg_last_reload_reg
[regno
+ nr
] = 0;
4544 /* For each reload, the mode of the reload register. */
4545 static enum machine_mode reload_mode
[MAX_RELOADS
];
4547 /* For each reload, the largest number of registers it will require. */
4548 static int reload_nregs
[MAX_RELOADS
];
4550 /* Comparison function for qsort to decide which of two reloads
4551 should be handled first. *P1 and *P2 are the reload numbers. */
4554 reload_reg_class_lower (r1p
, r2p
)
4555 const GENERIC_PTR r1p
;
4556 const GENERIC_PTR r2p
;
4558 register int r1
= *(short *)r1p
, r2
= *(short *)r2p
;
4561 /* Consider required reloads before optional ones. */
4562 t
= reload_optional
[r1
] - reload_optional
[r2
];
4566 /* Count all solitary classes before non-solitary ones. */
4567 t
= ((reg_class_size
[(int) reload_reg_class
[r2
]] == 1)
4568 - (reg_class_size
[(int) reload_reg_class
[r1
]] == 1));
4572 /* Aside from solitaires, consider all multi-reg groups first. */
4573 t
= reload_nregs
[r2
] - reload_nregs
[r1
];
4577 /* Consider reloads in order of increasing reg-class number. */
4578 t
= (int) reload_reg_class
[r1
] - (int) reload_reg_class
[r2
];
4582 /* If reloads are equally urgent, sort by reload number,
4583 so that the results of qsort leave nothing to chance. */
4587 /* The following HARD_REG_SETs indicate when each hard register is
4588 used for a reload of various parts of the current insn. */
4590 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4591 static HARD_REG_SET reload_reg_used
;
4592 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4593 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4594 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4595 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4596 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4597 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4598 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4599 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4600 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4601 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4602 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4603 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4604 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4605 static HARD_REG_SET reload_reg_used_in_op_addr
;
4606 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4607 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4608 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4609 static HARD_REG_SET reload_reg_used_in_insn
;
4610 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4611 static HARD_REG_SET reload_reg_used_in_other_addr
;
4613 /* If reg is in use as a reload reg for any sort of reload. */
4614 static HARD_REG_SET reload_reg_used_at_all
;
4616 /* If reg is use as an inherited reload. We just mark the first register
4618 static HARD_REG_SET reload_reg_used_for_inherit
;
4620 /* Records which hard regs are used in any way, either as explicit use or
4621 by being allocated to a pseudo during any point of the current insn. */
4622 static HARD_REG_SET reg_used_in_insn
;
4624 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4625 TYPE. MODE is used to indicate how many consecutive regs are
4629 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
4632 enum reload_type type
;
4633 enum machine_mode mode
;
4635 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4638 for (i
= regno
; i
< nregs
+ regno
; i
++)
4643 SET_HARD_REG_BIT (reload_reg_used
, i
);
4646 case RELOAD_FOR_INPUT_ADDRESS
:
4647 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4650 case RELOAD_FOR_INPADDR_ADDRESS
:
4651 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], i
);
4654 case RELOAD_FOR_OUTPUT_ADDRESS
:
4655 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4658 case RELOAD_FOR_OUTADDR_ADDRESS
:
4659 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], i
);
4662 case RELOAD_FOR_OPERAND_ADDRESS
:
4663 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4666 case RELOAD_FOR_OPADDR_ADDR
:
4667 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, i
);
4670 case RELOAD_FOR_OTHER_ADDRESS
:
4671 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4674 case RELOAD_FOR_INPUT
:
4675 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4678 case RELOAD_FOR_OUTPUT
:
4679 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4682 case RELOAD_FOR_INSN
:
4683 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4687 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4691 /* Similarly, but show REGNO is no longer in use for a reload. */
4694 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4697 enum reload_type type
;
4698 enum machine_mode mode
;
4700 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4701 int start_regno
, end_regno
;
4703 /* A complication is that for some reload types, inheritance might
4704 allow multiple reloads of the same types to share a reload register.
4705 We set check_opnum if we have to check only reloads with the same
4706 operand number, and check_any if we have to check all reloads. */
4707 int check_opnum
= 0;
4709 HARD_REG_SET
*used_in_set
;
4714 used_in_set
= &reload_reg_used
;
4717 case RELOAD_FOR_INPUT_ADDRESS
:
4718 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
4721 case RELOAD_FOR_INPADDR_ADDRESS
:
4723 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
4726 case RELOAD_FOR_OUTPUT_ADDRESS
:
4727 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
4730 case RELOAD_FOR_OUTADDR_ADDRESS
:
4732 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
4735 case RELOAD_FOR_OPERAND_ADDRESS
:
4736 used_in_set
= &reload_reg_used_in_op_addr
;
4739 case RELOAD_FOR_OPADDR_ADDR
:
4741 used_in_set
= &reload_reg_used_in_op_addr_reload
;
4744 case RELOAD_FOR_OTHER_ADDRESS
:
4745 used_in_set
= &reload_reg_used_in_other_addr
;
4749 case RELOAD_FOR_INPUT
:
4750 used_in_set
= &reload_reg_used_in_input
[opnum
];
4753 case RELOAD_FOR_OUTPUT
:
4754 used_in_set
= &reload_reg_used_in_output
[opnum
];
4757 case RELOAD_FOR_INSN
:
4758 used_in_set
= &reload_reg_used_in_insn
;
4763 /* We resolve conflicts with remaining reloads of the same type by
4764 excluding the intervals of of reload registers by them from the
4765 interval of freed reload registers. Since we only keep track of
4766 one set of interval bounds, we might have to exclude somewhat
4767 more then what would be necessary if we used a HARD_REG_SET here.
4768 But this should only happen very infrequently, so there should
4769 be no reason to worry about it. */
4771 start_regno
= regno
;
4772 end_regno
= regno
+ nregs
;
4773 if (check_opnum
|| check_any
)
4775 for (i
= n_reloads
- 1; i
>= 0; i
--)
4777 if (reload_when_needed
[i
] == type
4778 && (check_any
|| reload_opnum
[i
] == opnum
)
4779 && reload_reg_rtx
[i
])
4781 int conflict_start
= true_regnum (reload_reg_rtx
[i
]);
4784 + HARD_REGNO_NREGS (conflict_start
, reload_mode
[i
]));
4786 /* If there is an overlap with the first to-be-freed register,
4787 adjust the interval start. */
4788 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
4789 start_regno
= conflict_end
;
4790 /* Otherwise, if there is a conflict with one of the other
4791 to-be-freed registers, adjust the interval end. */
4792 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
4793 end_regno
= conflict_start
;
4797 for (i
= start_regno
; i
< end_regno
; i
++)
4798 CLEAR_HARD_REG_BIT (*used_in_set
, i
);
4801 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4802 specified by OPNUM and TYPE. */
4805 reload_reg_free_p (regno
, opnum
, type
)
4808 enum reload_type type
;
4812 /* In use for a RELOAD_OTHER means it's not available for anything. */
4813 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4819 /* In use for anything means we can't use it for RELOAD_OTHER. */
4820 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4821 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4825 for (i
= 0; i
< reload_n_operands
; i
++)
4826 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4827 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4828 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4829 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4830 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4831 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4836 case RELOAD_FOR_INPUT
:
4837 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4838 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4841 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
4844 /* If it is used for some other input, can't use it. */
4845 for (i
= 0; i
< reload_n_operands
; i
++)
4846 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4849 /* If it is used in a later operand's address, can't use it. */
4850 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4851 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4852 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
4857 case RELOAD_FOR_INPUT_ADDRESS
:
4858 /* Can't use a register if it is used for an input address for this
4859 operand or used as an input in an earlier one. */
4860 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
4861 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4864 for (i
= 0; i
< opnum
; i
++)
4865 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4870 case RELOAD_FOR_INPADDR_ADDRESS
:
4871 /* Can't use a register if it is used for an input address
4872 for this operand or used as an input in an earlier
4874 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
4877 for (i
= 0; i
< opnum
; i
++)
4878 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4883 case RELOAD_FOR_OUTPUT_ADDRESS
:
4884 /* Can't use a register if it is used for an output address for this
4885 operand or used as an output in this or a later operand. */
4886 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4889 for (i
= opnum
; i
< reload_n_operands
; i
++)
4890 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4895 case RELOAD_FOR_OUTADDR_ADDRESS
:
4896 /* Can't use a register if it is used for an output address
4897 for this operand or used as an output in this or a
4899 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
4902 for (i
= opnum
; i
< reload_n_operands
; i
++)
4903 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4908 case RELOAD_FOR_OPERAND_ADDRESS
:
4909 for (i
= 0; i
< reload_n_operands
; i
++)
4910 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4913 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4914 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4916 case RELOAD_FOR_OPADDR_ADDR
:
4917 for (i
= 0; i
< reload_n_operands
; i
++)
4918 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4921 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
4923 case RELOAD_FOR_OUTPUT
:
4924 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4925 outputs, or an operand address for this or an earlier output. */
4926 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4929 for (i
= 0; i
< reload_n_operands
; i
++)
4930 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4933 for (i
= 0; i
<= opnum
; i
++)
4934 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4935 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
4940 case RELOAD_FOR_INSN
:
4941 for (i
= 0; i
< reload_n_operands
; i
++)
4942 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4943 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4946 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4947 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4949 case RELOAD_FOR_OTHER_ADDRESS
:
4950 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4955 /* Return 1 if the value in reload reg REGNO, as used by a reload
4956 needed for the part of the insn specified by OPNUM and TYPE,
4957 is still available in REGNO at the end of the insn.
4959 We can assume that the reload reg was already tested for availability
4960 at the time it is needed, and we should not check this again,
4961 in case the reg has already been marked in use. */
4964 reload_reg_reaches_end_p (regno
, opnum
, type
)
4967 enum reload_type type
;
4974 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4975 its value must reach the end. */
4978 /* If this use is for part of the insn,
4979 its value reaches if no subsequent part uses the same register.
4980 Just like the above function, don't try to do this with lots
4983 case RELOAD_FOR_OTHER_ADDRESS
:
4984 /* Here we check for everything else, since these don't conflict
4985 with anything else and everything comes later. */
4987 for (i
= 0; i
< reload_n_operands
; i
++)
4988 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4989 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
4990 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4991 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4992 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
4993 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4996 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4997 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4998 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5000 case RELOAD_FOR_INPUT_ADDRESS
:
5001 case RELOAD_FOR_INPADDR_ADDRESS
:
5002 /* Similar, except that we check only for this and subsequent inputs
5003 and the address of only subsequent inputs and we do not need
5004 to check for RELOAD_OTHER objects since they are known not to
5007 for (i
= opnum
; i
< reload_n_operands
; i
++)
5008 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5011 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5012 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5013 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5016 for (i
= 0; i
< reload_n_operands
; i
++)
5017 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5018 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5019 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5022 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5025 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5026 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
5028 case RELOAD_FOR_INPUT
:
5029 /* Similar to input address, except we start at the next operand for
5030 both input and input address and we do not check for
5031 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5034 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5035 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5036 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5037 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5040 /* ... fall through ... */
5042 case RELOAD_FOR_OPERAND_ADDRESS
:
5043 /* Check outputs and their addresses. */
5045 for (i
= 0; i
< reload_n_operands
; i
++)
5046 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5047 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5048 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5053 case RELOAD_FOR_OPADDR_ADDR
:
5054 for (i
= 0; i
< reload_n_operands
; i
++)
5055 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5056 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5057 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5060 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5061 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
5063 case RELOAD_FOR_INSN
:
5064 /* These conflict with other outputs with RELOAD_OTHER. So
5065 we need only check for output addresses. */
5069 /* ... fall through ... */
5071 case RELOAD_FOR_OUTPUT
:
5072 case RELOAD_FOR_OUTPUT_ADDRESS
:
5073 case RELOAD_FOR_OUTADDR_ADDRESS
:
5074 /* We already know these can't conflict with a later output. So the
5075 only thing to check are later output addresses. */
5076 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5077 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5078 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5087 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5090 This function uses the same algorithm as reload_reg_free_p above. */
5093 reloads_conflict (r1
, r2
)
5096 enum reload_type r1_type
= reload_when_needed
[r1
];
5097 enum reload_type r2_type
= reload_when_needed
[r2
];
5098 int r1_opnum
= reload_opnum
[r1
];
5099 int r2_opnum
= reload_opnum
[r2
];
5101 /* RELOAD_OTHER conflicts with everything. */
5102 if (r2_type
== RELOAD_OTHER
)
5105 /* Otherwise, check conflicts differently for each type. */
5109 case RELOAD_FOR_INPUT
:
5110 return (r2_type
== RELOAD_FOR_INSN
5111 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5112 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5113 || r2_type
== RELOAD_FOR_INPUT
5114 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5115 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5116 && r2_opnum
> r1_opnum
));
5118 case RELOAD_FOR_INPUT_ADDRESS
:
5119 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5120 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5122 case RELOAD_FOR_INPADDR_ADDRESS
:
5123 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5124 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5126 case RELOAD_FOR_OUTPUT_ADDRESS
:
5127 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5128 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5130 case RELOAD_FOR_OUTADDR_ADDRESS
:
5131 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5132 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
>= r1_opnum
));
5134 case RELOAD_FOR_OPERAND_ADDRESS
:
5135 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5136 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5138 case RELOAD_FOR_OPADDR_ADDR
:
5139 return (r2_type
== RELOAD_FOR_INPUT
5140 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5142 case RELOAD_FOR_OUTPUT
:
5143 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5144 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5145 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5146 && r2_opnum
>= r1_opnum
));
5148 case RELOAD_FOR_INSN
:
5149 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5150 || r2_type
== RELOAD_FOR_INSN
5151 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5153 case RELOAD_FOR_OTHER_ADDRESS
:
5154 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5164 /* Vector of reload-numbers showing the order in which the reloads should
5166 short reload_order
[MAX_RELOADS
];
5168 /* Indexed by reload number, 1 if incoming value
5169 inherited from previous insns. */
5170 char reload_inherited
[MAX_RELOADS
];
5172 /* For an inherited reload, this is the insn the reload was inherited from,
5173 if we know it. Otherwise, this is 0. */
5174 rtx reload_inheritance_insn
[MAX_RELOADS
];
5176 /* If non-zero, this is a place to get the value of the reload,
5177 rather than using reload_in. */
5178 rtx reload_override_in
[MAX_RELOADS
];
5180 /* For each reload, the hard register number of the register used,
5181 or -1 if we did not need a register for this reload. */
5182 int reload_spill_index
[MAX_RELOADS
];
5184 /* Return 1 if the value in reload reg REGNO, as used by a reload
5185 needed for the part of the insn specified by OPNUM and TYPE,
5186 may be used to load VALUE into it.
5188 Other read-only reloads with the same value do not conflict
5189 unless OUT is non-zero and these other reloads have to live while
5190 output reloads live.
5191 If OUT is CONST0_RTX, this is a special case: it means that the
5192 test should not be for using register REGNO as reload register, but
5193 for copying from register REGNO into the reload register.
5195 RELOADNUM is the number of the reload we want to load this value for;
5196 a reload does not conflict with itself.
5198 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5199 reloads that load an address for the very reload we are considering.
5201 The caller has to make sure that there is no conflict with the return
5204 reload_reg_free_for_value_p (regno
, opnum
, type
, value
, out
, reloadnum
,
5205 ignore_address_reloads
)
5208 enum reload_type type
;
5211 int ignore_address_reloads
;
5217 if (out
== const0_rtx
)
5223 /* We use some pseudo 'time' value to check if the lifetimes of the
5224 new register use would overlap with the one of a previous reload
5225 that is not read-only or uses a different value.
5226 The 'time' used doesn't have to be linear in any shape or form, just
5228 Some reload types use different 'buckets' for each operand.
5229 So there are MAX_RECOG_OPERANDS different time values for each
5231 We compute TIME1 as the time when the register for the prospective
5232 new reload ceases to be live, and TIME2 for each existing
5233 reload as the time when that the reload register of that reload
5235 Where there is little to be gained by exact lifetime calculations,
5236 we just make conservative assumptions, i.e. a longer lifetime;
5237 this is done in the 'default:' cases. */
5240 case RELOAD_FOR_OTHER_ADDRESS
:
5244 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5246 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5247 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5248 respectively, to the time values for these, we get distinct time
5249 values. To get distinct time values for each operand, we have to
5250 multiply opnum by at least three. We round that up to four because
5251 multiply by four is often cheaper. */
5252 case RELOAD_FOR_INPADDR_ADDRESS
:
5253 time1
= opnum
* 4 + 2;
5255 case RELOAD_FOR_INPUT_ADDRESS
:
5256 time1
= opnum
* 4 + 3;
5258 case RELOAD_FOR_INPUT
:
5259 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5260 executes (inclusive). */
5261 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5263 case RELOAD_FOR_OPADDR_ADDR
:
5265 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5266 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5268 case RELOAD_FOR_OPERAND_ADDRESS
:
5269 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5271 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5273 case RELOAD_FOR_OUTADDR_ADDRESS
:
5274 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5276 case RELOAD_FOR_OUTPUT_ADDRESS
:
5277 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5280 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5283 for (i
= 0; i
< n_reloads
; i
++)
5285 rtx reg
= reload_reg_rtx
[i
];
5286 if (reg
&& GET_CODE (reg
) == REG
5287 && ((unsigned) regno
- true_regnum (reg
)
5288 <= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
)) - (unsigned)1)
5291 if (! reload_in
[i
] || ! rtx_equal_p (reload_in
[i
], value
)
5292 || reload_out
[i
] || out
)
5295 switch (reload_when_needed
[i
])
5297 case RELOAD_FOR_OTHER_ADDRESS
:
5300 case RELOAD_FOR_INPADDR_ADDRESS
:
5301 /* find_reloads makes sure that a
5302 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5303 by at most one - the first -
5304 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5305 address reload is inherited, the address address reload
5306 goes away, so we can ignore this conflict. */
5307 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5308 && ignore_address_reloads
5309 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5310 Then the address address is still needed to store
5311 back the new address. */
5312 && ! reload_out
[reloadnum
])
5314 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5315 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5317 if (type
== RELOAD_FOR_INPUT
&& opnum
== reload_opnum
[i
]
5318 && ignore_address_reloads
5319 /* Unless we are reloading an auto_inc expression. */
5320 && ! reload_out
[reloadnum
])
5322 time2
= reload_opnum
[i
] * 4 + 2;
5324 case RELOAD_FOR_INPUT_ADDRESS
:
5325 if (type
== RELOAD_FOR_INPUT
&& opnum
== reload_opnum
[i
]
5326 && ignore_address_reloads
5327 && ! reload_out
[reloadnum
])
5329 time2
= reload_opnum
[i
] * 4 + 3;
5331 case RELOAD_FOR_INPUT
:
5332 time2
= reload_opnum
[i
] * 4 + 4;
5334 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5335 == MAX_RECOG_OPERAND * 4 */
5336 case RELOAD_FOR_OPADDR_ADDR
:
5337 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5338 && ignore_address_reloads
5339 && ! reload_out
[reloadnum
])
5341 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5343 case RELOAD_FOR_OPERAND_ADDRESS
:
5344 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5346 case RELOAD_FOR_INSN
:
5347 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5349 case RELOAD_FOR_OUTPUT
:
5350 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5351 instruction is executed. */
5352 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5354 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5355 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5357 case RELOAD_FOR_OUTADDR_ADDRESS
:
5358 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5359 && ignore_address_reloads
5360 && ! reload_out
[reloadnum
])
5362 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + reload_opnum
[i
];
5364 case RELOAD_FOR_OUTPUT_ADDRESS
:
5365 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + reload_opnum
[i
];
5368 /* If there is no conflict in the input part, handle this
5369 like an output reload. */
5370 if (! reload_in
[i
] || rtx_equal_p (reload_in
[i
], value
))
5372 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5376 /* RELOAD_OTHER might be live beyond instruction execution,
5377 but this is not obvious when we set time2 = 1. So check
5378 here if there might be a problem with the new reload
5379 clobbering the register used by the RELOAD_OTHER. */
5387 && (! reload_in
[i
] || reload_out
[i
]
5388 || ! rtx_equal_p (reload_in
[i
], value
)))
5389 || (out
&& reload_out_reg
[reloadnum
]
5390 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5398 /* Find a spill register to use as a reload register for reload R.
5399 LAST_RELOAD is non-zero if this is the last reload for the insn being
5402 Set reload_reg_rtx[R] to the register allocated.
5404 If NOERROR is nonzero, we return 1 if successful,
5405 or 0 if we couldn't find a spill reg and we didn't change anything. */
5408 allocate_reload_reg (chain
, r
, last_reload
, noerror
)
5409 struct insn_chain
*chain
;
5414 rtx insn
= chain
->insn
;
5415 int i
, pass
, count
, regno
;
5418 /* If we put this reload ahead, thinking it is a group,
5419 then insist on finding a group. Otherwise we can grab a
5420 reg that some other reload needs.
5421 (That can happen when we have a 68000 DATA_OR_FP_REG
5422 which is a group of data regs or one fp reg.)
5423 We need not be so restrictive if there are no more reloads
5426 ??? Really it would be nicer to have smarter handling
5427 for that kind of reg class, where a problem like this is normal.
5428 Perhaps those classes should be avoided for reloading
5429 by use of more alternatives. */
5431 int force_group
= reload_nregs
[r
] > 1 && ! last_reload
;
5433 /* If we want a single register and haven't yet found one,
5434 take any reg in the right class and not in use.
5435 If we want a consecutive group, here is where we look for it.
5437 We use two passes so we can first look for reload regs to
5438 reuse, which are already in use for other reloads in this insn,
5439 and only then use additional registers.
5440 I think that maximizing reuse is needed to make sure we don't
5441 run out of reload regs. Suppose we have three reloads, and
5442 reloads A and B can share regs. These need two regs.
5443 Suppose A and B are given different regs.
5444 That leaves none for C. */
5445 for (pass
= 0; pass
< 2; pass
++)
5447 /* I is the index in spill_regs.
5448 We advance it round-robin between insns to use all spill regs
5449 equally, so that inherited reloads have a chance
5450 of leapfrogging each other. Don't do this, however, when we have
5451 group needs and failure would be fatal; if we only have a relatively
5452 small number of spill registers, and more than one of them has
5453 group needs, then by starting in the middle, we may end up
5454 allocating the first one in such a way that we are not left with
5455 sufficient groups to handle the rest. */
5457 if (noerror
|| ! force_group
)
5462 for (count
= 0; count
< n_spills
; count
++)
5464 int class = (int) reload_reg_class
[r
];
5470 regnum
= spill_regs
[i
];
5472 if ((reload_reg_free_p (regnum
, reload_opnum
[r
],
5473 reload_when_needed
[r
])
5475 /* We check reload_reg_used to make sure we
5476 don't clobber the return register. */
5477 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
5478 && reload_reg_free_for_value_p (regnum
,
5480 reload_when_needed
[r
],
5482 reload_out
[r
], r
, 1)))
5483 && TEST_HARD_REG_BIT (reg_class_contents
[class], regnum
)
5484 && HARD_REGNO_MODE_OK (regnum
, reload_mode
[r
])
5485 /* Look first for regs to share, then for unshared. But
5486 don't share regs used for inherited reloads; they are
5487 the ones we want to preserve. */
5489 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
5491 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
5494 int nr
= HARD_REGNO_NREGS (regnum
, reload_mode
[r
]);
5495 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5496 (on 68000) got us two FP regs. If NR is 1,
5497 we would reject both of them. */
5499 nr
= CLASS_MAX_NREGS (reload_reg_class
[r
], reload_mode
[r
]);
5500 /* If we need only one reg, we have already won. */
5503 /* But reject a single reg if we demand a group. */
5508 /* Otherwise check that as many consecutive regs as we need
5510 Also, don't use for a group registers that are
5511 needed for nongroups. */
5512 if (! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
, regnum
))
5515 regno
= regnum
+ nr
- 1;
5516 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
5517 && spill_reg_order
[regno
] >= 0
5518 && reload_reg_free_p (regno
, reload_opnum
[r
],
5519 reload_when_needed
[r
])
5520 && ! TEST_HARD_REG_BIT (chain
->counted_for_nongroups
,
5530 /* If we found something on pass 1, omit pass 2. */
5531 if (count
< n_spills
)
5535 /* We should have found a spill register by now. */
5536 if (count
== n_spills
)
5543 /* I is the index in SPILL_REG_RTX of the reload register we are to
5544 allocate. Get an rtx for it and find its register number. */
5546 new = spill_reg_rtx
[i
];
5548 if (new == 0 || GET_MODE (new) != reload_mode
[r
])
5549 spill_reg_rtx
[i
] = new
5550 = gen_rtx_REG (reload_mode
[r
], spill_regs
[i
]);
5552 regno
= true_regnum (new);
5554 /* Detect when the reload reg can't hold the reload mode.
5555 This used to be one `if', but Sequent compiler can't handle that. */
5556 if (HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
5558 enum machine_mode test_mode
= VOIDmode
;
5560 test_mode
= GET_MODE (reload_in
[r
]);
5561 /* If reload_in[r] has VOIDmode, it means we will load it
5562 in whatever mode the reload reg has: to wit, reload_mode[r].
5563 We have already tested that for validity. */
5564 /* Aside from that, we need to test that the expressions
5565 to reload from or into have modes which are valid for this
5566 reload register. Otherwise the reload insns would be invalid. */
5567 if (! (reload_in
[r
] != 0 && test_mode
!= VOIDmode
5568 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
5569 if (! (reload_out
[r
] != 0
5570 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (reload_out
[r
]))))
5572 /* The reg is OK. */
5575 /* Mark as in use for this insn the reload regs we use
5577 mark_reload_reg_in_use (spill_regs
[i
], reload_opnum
[r
],
5578 reload_when_needed
[r
], reload_mode
[r
]);
5580 reload_reg_rtx
[r
] = new;
5581 reload_spill_index
[r
] = spill_regs
[i
];
5586 /* The reg is not OK. */
5591 if (asm_noperands (PATTERN (insn
)) < 0)
5592 /* It's the compiler's fault. */
5593 fatal_insn ("Could not find a spill register", insn
);
5595 /* It's the user's fault; the operand's mode and constraint
5596 don't match. Disable this reload so we don't crash in final. */
5597 error_for_asm (insn
,
5598 "`asm' operand constraint incompatible with operand size");
5601 reload_reg_rtx
[r
] = 0;
5602 reload_optional
[r
] = 1;
5603 reload_secondary_p
[r
] = 1;
5608 /* Assign hard reg targets for the pseudo-registers we must reload
5609 into hard regs for this insn.
5610 Also output the instructions to copy them in and out of the hard regs.
5612 For machines with register classes, we are responsible for
5613 finding a reload reg in the proper class. */
5616 choose_reload_regs (chain
)
5617 struct insn_chain
*chain
;
5619 rtx insn
= chain
->insn
;
5621 int max_group_size
= 1;
5622 enum reg_class group_class
= NO_REGS
;
5626 rtx save_reload_reg_rtx
[MAX_RELOADS
];
5627 char save_reload_inherited
[MAX_RELOADS
];
5628 rtx save_reload_inheritance_insn
[MAX_RELOADS
];
5629 rtx save_reload_override_in
[MAX_RELOADS
];
5630 int save_reload_spill_index
[MAX_RELOADS
];
5631 HARD_REG_SET save_reload_reg_used
;
5632 HARD_REG_SET save_reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5633 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5634 HARD_REG_SET save_reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5635 HARD_REG_SET save_reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5636 HARD_REG_SET save_reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5637 HARD_REG_SET save_reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5638 HARD_REG_SET save_reload_reg_used_in_op_addr
;
5639 HARD_REG_SET save_reload_reg_used_in_op_addr_reload
;
5640 HARD_REG_SET save_reload_reg_used_in_insn
;
5641 HARD_REG_SET save_reload_reg_used_in_other_addr
;
5642 HARD_REG_SET save_reload_reg_used_at_all
;
5644 bzero (reload_inherited
, MAX_RELOADS
);
5645 bzero ((char *) reload_inheritance_insn
, MAX_RELOADS
* sizeof (rtx
));
5646 bzero ((char *) reload_override_in
, MAX_RELOADS
* sizeof (rtx
));
5648 CLEAR_HARD_REG_SET (reload_reg_used
);
5649 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
5650 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
5651 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
5652 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
5653 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
5655 CLEAR_HARD_REG_SET (reg_used_in_insn
);
5658 REG_SET_TO_HARD_REG_SET (tmp
, chain
->live_before
);
5659 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5660 REG_SET_TO_HARD_REG_SET (tmp
, chain
->live_after
);
5661 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
5662 compute_use_by_pseudos (®_used_in_insn
, chain
->live_before
);
5663 compute_use_by_pseudos (®_used_in_insn
, chain
->live_after
);
5665 for (i
= 0; i
< reload_n_operands
; i
++)
5667 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
5668 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
5669 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
5670 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
5671 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
5672 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
5675 IOR_COMPL_HARD_REG_SET (reload_reg_used
, chain
->used_spill_regs
);
5677 #if 0 /* Not needed, now that we can always retry without inheritance. */
5678 /* See if we have more mandatory reloads than spill regs.
5679 If so, then we cannot risk optimizations that could prevent
5680 reloads from sharing one spill register.
5682 Since we will try finding a better register than reload_reg_rtx
5683 unless it is equal to reload_in or reload_out, count such reloads. */
5687 for (j
= 0; j
< n_reloads
; j
++)
5688 if (! reload_optional
[j
]
5689 && (reload_in
[j
] != 0 || reload_out
[j
] != 0 || reload_secondary_p
[j
])
5690 && (reload_reg_rtx
[j
] == 0
5691 || (! rtx_equal_p (reload_reg_rtx
[j
], reload_in
[j
])
5692 && ! rtx_equal_p (reload_reg_rtx
[j
], reload_out
[j
]))))
5699 /* In order to be certain of getting the registers we need,
5700 we must sort the reloads into order of increasing register class.
5701 Then our grabbing of reload registers will parallel the process
5702 that provided the reload registers.
5704 Also note whether any of the reloads wants a consecutive group of regs.
5705 If so, record the maximum size of the group desired and what
5706 register class contains all the groups needed by this insn. */
5708 for (j
= 0; j
< n_reloads
; j
++)
5710 reload_order
[j
] = j
;
5711 reload_spill_index
[j
] = -1;
5714 = (reload_inmode
[j
] == VOIDmode
5715 || (GET_MODE_SIZE (reload_outmode
[j
])
5716 > GET_MODE_SIZE (reload_inmode
[j
])))
5717 ? reload_outmode
[j
] : reload_inmode
[j
];
5719 reload_nregs
[j
] = CLASS_MAX_NREGS (reload_reg_class
[j
], reload_mode
[j
]);
5721 if (reload_nregs
[j
] > 1)
5723 max_group_size
= MAX (reload_nregs
[j
], max_group_size
);
5724 group_class
= reg_class_superunion
[(int)reload_reg_class
[j
]][(int)group_class
];
5727 /* If we have already decided to use a certain register,
5728 don't use it in another way. */
5729 if (reload_reg_rtx
[j
])
5730 mark_reload_reg_in_use (REGNO (reload_reg_rtx
[j
]), reload_opnum
[j
],
5731 reload_when_needed
[j
], reload_mode
[j
]);
5735 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
5737 bcopy ((char *) reload_reg_rtx
, (char *) save_reload_reg_rtx
,
5738 sizeof reload_reg_rtx
);
5739 bcopy (reload_inherited
, save_reload_inherited
, sizeof reload_inherited
);
5740 bcopy ((char *) reload_inheritance_insn
,
5741 (char *) save_reload_inheritance_insn
,
5742 sizeof reload_inheritance_insn
);
5743 bcopy ((char *) reload_override_in
, (char *) save_reload_override_in
,
5744 sizeof reload_override_in
);
5745 bcopy ((char *) reload_spill_index
, (char *) save_reload_spill_index
,
5746 sizeof reload_spill_index
);
5747 COPY_HARD_REG_SET (save_reload_reg_used
, reload_reg_used
);
5748 COPY_HARD_REG_SET (save_reload_reg_used_at_all
, reload_reg_used_at_all
);
5749 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr
,
5750 reload_reg_used_in_op_addr
);
5752 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload
,
5753 reload_reg_used_in_op_addr_reload
);
5755 COPY_HARD_REG_SET (save_reload_reg_used_in_insn
,
5756 reload_reg_used_in_insn
);
5757 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr
,
5758 reload_reg_used_in_other_addr
);
5760 for (i
= 0; i
< reload_n_operands
; i
++)
5762 COPY_HARD_REG_SET (save_reload_reg_used_in_output
[i
],
5763 reload_reg_used_in_output
[i
]);
5764 COPY_HARD_REG_SET (save_reload_reg_used_in_input
[i
],
5765 reload_reg_used_in_input
[i
]);
5766 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr
[i
],
5767 reload_reg_used_in_input_addr
[i
]);
5768 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr
[i
],
5769 reload_reg_used_in_inpaddr_addr
[i
]);
5770 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr
[i
],
5771 reload_reg_used_in_output_addr
[i
]);
5772 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr
[i
],
5773 reload_reg_used_in_outaddr_addr
[i
]);
5776 /* If -O, try first with inheritance, then turning it off.
5777 If not -O, don't do inheritance.
5778 Using inheritance when not optimizing leads to paradoxes
5779 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5780 because one side of the comparison might be inherited. */
5782 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
5784 /* Process the reloads in order of preference just found.
5785 Beyond this point, subregs can be found in reload_reg_rtx.
5787 This used to look for an existing reloaded home for all
5788 of the reloads, and only then perform any new reloads.
5789 But that could lose if the reloads were done out of reg-class order
5790 because a later reload with a looser constraint might have an old
5791 home in a register needed by an earlier reload with a tighter constraint.
5793 To solve this, we make two passes over the reloads, in the order
5794 described above. In the first pass we try to inherit a reload
5795 from a previous insn. If there is a later reload that needs a
5796 class that is a proper subset of the class being processed, we must
5797 also allocate a spill register during the first pass.
5799 Then make a second pass over the reloads to allocate any reloads
5800 that haven't been given registers yet. */
5802 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
5804 for (j
= 0; j
< n_reloads
; j
++)
5806 register int r
= reload_order
[j
];
5808 /* Ignore reloads that got marked inoperative. */
5809 if (reload_out
[r
] == 0 && reload_in
[r
] == 0
5810 && ! reload_secondary_p
[r
])
5813 /* If find_reloads chose to use reload_in or reload_out as a reload
5814 register, we don't need to chose one. Otherwise, try even if it
5815 found one since we might save an insn if we find the value lying
5817 Try also when reload_in is a pseudo without a hard reg. */
5818 if (reload_in
[r
] != 0 && reload_reg_rtx
[r
] != 0
5819 && (rtx_equal_p (reload_in
[r
], reload_reg_rtx
[r
])
5820 || (rtx_equal_p (reload_out
[r
], reload_reg_rtx
[r
])
5821 && GET_CODE (reload_in
[r
]) != MEM
5822 && true_regnum (reload_in
[r
]) < FIRST_PSEUDO_REGISTER
)))
5825 #if 0 /* No longer needed for correct operation.
5826 It might give better code, or might not; worth an experiment? */
5827 /* If this is an optional reload, we can't inherit from earlier insns
5828 until we are sure that any non-optional reloads have been allocated.
5829 The following code takes advantage of the fact that optional reloads
5830 are at the end of reload_order. */
5831 if (reload_optional
[r
] != 0)
5832 for (i
= 0; i
< j
; i
++)
5833 if ((reload_out
[reload_order
[i
]] != 0
5834 || reload_in
[reload_order
[i
]] != 0
5835 || reload_secondary_p
[reload_order
[i
]])
5836 && ! reload_optional
[reload_order
[i
]]
5837 && reload_reg_rtx
[reload_order
[i
]] == 0)
5838 allocate_reload_reg (chain
, reload_order
[i
], 0, inheritance
);
5841 /* First see if this pseudo is already available as reloaded
5842 for a previous insn. We cannot try to inherit for reloads
5843 that are smaller than the maximum number of registers needed
5844 for groups unless the register we would allocate cannot be used
5847 We could check here to see if this is a secondary reload for
5848 an object that is already in a register of the desired class.
5849 This would avoid the need for the secondary reload register.
5850 But this is complex because we can't easily determine what
5851 objects might want to be loaded via this reload. So let a
5852 register be allocated here. In `emit_reload_insns' we suppress
5853 one of the loads in the case described above. */
5858 register int regno
= -1;
5859 enum machine_mode mode
;
5861 if (reload_in
[r
] == 0)
5863 else if (GET_CODE (reload_in
[r
]) == REG
)
5865 regno
= REGNO (reload_in
[r
]);
5866 mode
= GET_MODE (reload_in
[r
]);
5868 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
5870 regno
= REGNO (reload_in_reg
[r
]);
5871 mode
= GET_MODE (reload_in_reg
[r
]);
5873 else if (GET_CODE (reload_in_reg
[r
]) == SUBREG
5874 && GET_CODE (SUBREG_REG (reload_in_reg
[r
])) == REG
)
5876 word
= SUBREG_WORD (reload_in_reg
[r
]);
5877 regno
= REGNO (SUBREG_REG (reload_in_reg
[r
]));
5878 if (regno
< FIRST_PSEUDO_REGISTER
)
5880 mode
= GET_MODE (reload_in_reg
[r
]);
5883 else if ((GET_CODE (reload_in_reg
[r
]) == PRE_INC
5884 || GET_CODE (reload_in_reg
[r
]) == PRE_DEC
5885 || GET_CODE (reload_in_reg
[r
]) == POST_INC
5886 || GET_CODE (reload_in_reg
[r
]) == POST_DEC
)
5887 && GET_CODE (XEXP (reload_in_reg
[r
], 0)) == REG
)
5889 regno
= REGNO (XEXP (reload_in_reg
[r
], 0));
5890 mode
= GET_MODE (XEXP (reload_in_reg
[r
], 0));
5891 reload_out
[r
] = reload_in
[r
];
5895 /* This won't work, since REGNO can be a pseudo reg number.
5896 Also, it takes much more hair to keep track of all the things
5897 that can invalidate an inherited reload of part of a pseudoreg. */
5898 else if (GET_CODE (reload_in
[r
]) == SUBREG
5899 && GET_CODE (SUBREG_REG (reload_in
[r
])) == REG
)
5900 regno
= REGNO (SUBREG_REG (reload_in
[r
])) + SUBREG_WORD (reload_in
[r
]);
5903 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
5905 enum reg_class
class = reload_reg_class
[r
], last_class
;
5906 rtx last_reg
= reg_last_reload_reg
[regno
];
5908 i
= REGNO (last_reg
) + word
;
5909 last_class
= REGNO_REG_CLASS (i
);
5910 if ((GET_MODE_SIZE (GET_MODE (last_reg
))
5911 >= GET_MODE_SIZE (mode
) + word
* UNITS_PER_WORD
)
5912 && reg_reloaded_contents
[i
] == regno
5913 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
5914 && HARD_REGNO_MODE_OK (i
, reload_mode
[r
])
5915 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], i
)
5916 /* Even if we can't use this register as a reload
5917 register, we might use it for reload_override_in,
5918 if copying it to the desired class is cheap
5920 || ((REGISTER_MOVE_COST (last_class
, class)
5921 < MEMORY_MOVE_COST (mode
, class, 1))
5922 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5923 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode
,
5927 #ifdef SECONDARY_MEMORY_NEEDED
5928 && ! SECONDARY_MEMORY_NEEDED (last_class
, class,
5933 && (reload_nregs
[r
] == max_group_size
5934 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
5936 && reload_reg_free_for_value_p (i
, reload_opnum
[r
],
5937 reload_when_needed
[r
],
5941 /* If a group is needed, verify that all the subsequent
5942 registers still have their values intact. */
5944 = HARD_REGNO_NREGS (i
, reload_mode
[r
]);
5947 for (k
= 1; k
< nr
; k
++)
5948 if (reg_reloaded_contents
[i
+ k
] != regno
5949 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
5956 last_reg
= (GET_MODE (last_reg
) == mode
5957 ? last_reg
: gen_rtx_REG (mode
, i
));
5959 /* We found a register that contains the
5960 value we need. If this register is the
5961 same as an `earlyclobber' operand of the
5962 current insn, just mark it as a place to
5963 reload from since we can't use it as the
5964 reload register itself. */
5966 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
5967 if (reg_overlap_mentioned_for_reload_p
5968 (reg_last_reload_reg
[regno
],
5969 reload_earlyclobbers
[i1
]))
5972 if (i1
!= n_earlyclobbers
5973 || ! (reload_reg_free_for_value_p
5974 (i
, reload_opnum
[r
], reload_when_needed
[r
],
5975 reload_in
[r
], reload_out
[r
], r
, 1))
5976 /* Don't use it if we'd clobber a pseudo reg. */
5977 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
5979 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
5980 /* Don't clobber the frame pointer. */
5981 || (i
== HARD_FRAME_POINTER_REGNUM
5983 /* Don't really use the inherited spill reg
5984 if we need it wider than we've got it. */
5985 || (GET_MODE_SIZE (reload_mode
[r
])
5986 > GET_MODE_SIZE (mode
))
5987 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
5990 /* If find_reloads chose reload_out as reload
5991 register, stay with it - that leaves the
5992 inherited register for subsequent reloads. */
5993 || (reload_out
[r
] && reload_reg_rtx
[r
]
5994 && rtx_equal_p (reload_out
[r
],
5995 reload_reg_rtx
[r
])))
5997 reload_override_in
[r
] = last_reg
;
5998 reload_inheritance_insn
[r
]
5999 = reg_reloaded_insn
[i
];
6004 /* We can use this as a reload reg. */
6005 /* Mark the register as in use for this part of
6007 mark_reload_reg_in_use (i
,
6009 reload_when_needed
[r
],
6011 reload_reg_rtx
[r
] = last_reg
;
6012 reload_inherited
[r
] = 1;
6013 reload_inheritance_insn
[r
]
6014 = reg_reloaded_insn
[i
];
6015 reload_spill_index
[r
] = i
;
6016 for (k
= 0; k
< nr
; k
++)
6017 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6025 /* Here's another way to see if the value is already lying around. */
6027 && reload_in
[r
] != 0
6028 && ! reload_inherited
[r
]
6029 && reload_out
[r
] == 0
6030 && (CONSTANT_P (reload_in
[r
])
6031 || GET_CODE (reload_in
[r
]) == PLUS
6032 || GET_CODE (reload_in
[r
]) == REG
6033 || GET_CODE (reload_in
[r
]) == MEM
)
6034 && (reload_nregs
[r
] == max_group_size
6035 || ! reg_classes_intersect_p (reload_reg_class
[r
], group_class
)))
6038 = find_equiv_reg (reload_in
[r
], insn
, reload_reg_class
[r
],
6039 -1, NULL_PTR
, 0, reload_mode
[r
]);
6044 if (GET_CODE (equiv
) == REG
)
6045 regno
= REGNO (equiv
);
6046 else if (GET_CODE (equiv
) == SUBREG
)
6048 /* This must be a SUBREG of a hard register.
6049 Make a new REG since this might be used in an
6050 address and not all machines support SUBREGs
6052 regno
= REGNO (SUBREG_REG (equiv
)) + SUBREG_WORD (equiv
);
6053 equiv
= gen_rtx_REG (reload_mode
[r
], regno
);
6059 /* If we found a spill reg, reject it unless it is free
6060 and of the desired class. */
6062 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
)
6063 && ! reload_reg_free_for_value_p (regno
, reload_opnum
[r
],
6064 reload_when_needed
[r
],
6066 reload_out
[r
], r
, 1))
6067 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
6071 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
6074 /* We found a register that contains the value we need.
6075 If this register is the same as an `earlyclobber' operand
6076 of the current insn, just mark it as a place to reload from
6077 since we can't use it as the reload register itself. */
6080 for (i
= 0; i
< n_earlyclobbers
; i
++)
6081 if (reg_overlap_mentioned_for_reload_p (equiv
,
6082 reload_earlyclobbers
[i
]))
6084 reload_override_in
[r
] = equiv
;
6089 /* If the equiv register we have found is explicitly clobbered
6090 in the current insn, it depends on the reload type if we
6091 can use it, use it for reload_override_in, or not at all.
6092 In particular, we then can't use EQUIV for a
6093 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6095 if (equiv
!= 0 && regno_clobbered_p (regno
, insn
))
6097 switch (reload_when_needed
[r
])
6099 case RELOAD_FOR_OTHER_ADDRESS
:
6100 case RELOAD_FOR_INPADDR_ADDRESS
:
6101 case RELOAD_FOR_INPUT_ADDRESS
:
6102 case RELOAD_FOR_OPADDR_ADDR
:
6105 case RELOAD_FOR_INPUT
:
6106 case RELOAD_FOR_OPERAND_ADDRESS
:
6107 reload_override_in
[r
] = equiv
;
6115 /* If we found an equivalent reg, say no code need be generated
6116 to load it, and use it as our reload reg. */
6117 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
6119 int nr
= HARD_REGNO_NREGS (regno
, reload_mode
[r
]);
6121 reload_reg_rtx
[r
] = equiv
;
6122 reload_inherited
[r
] = 1;
6124 /* If reg_reloaded_valid is not set for this register,
6125 there might be a stale spill_reg_store lying around.
6126 We must clear it, since otherwise emit_reload_insns
6127 might delete the store. */
6128 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6129 spill_reg_store
[regno
] = NULL_RTX
;
6130 /* If any of the hard registers in EQUIV are spill
6131 registers, mark them as in use for this insn. */
6132 for (k
= 0; k
< nr
; k
++)
6134 i
= spill_reg_order
[regno
+ k
];
6137 mark_reload_reg_in_use (regno
, reload_opnum
[r
],
6138 reload_when_needed
[r
],
6140 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6147 /* If we found a register to use already, or if this is an optional
6148 reload, we are done. */
6149 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
] != 0)
6152 #if 0 /* No longer needed for correct operation. Might or might not
6153 give better code on the average. Want to experiment? */
6155 /* See if there is a later reload that has a class different from our
6156 class that intersects our class or that requires less register
6157 than our reload. If so, we must allocate a register to this
6158 reload now, since that reload might inherit a previous reload
6159 and take the only available register in our class. Don't do this
6160 for optional reloads since they will force all previous reloads
6161 to be allocated. Also don't do this for reloads that have been
6164 for (i
= j
+ 1; i
< n_reloads
; i
++)
6166 int s
= reload_order
[i
];
6168 if ((reload_in
[s
] == 0 && reload_out
[s
] == 0
6169 && ! reload_secondary_p
[s
])
6170 || reload_optional
[s
])
6173 if ((reload_reg_class
[s
] != reload_reg_class
[r
]
6174 && reg_classes_intersect_p (reload_reg_class
[r
],
6175 reload_reg_class
[s
]))
6176 || reload_nregs
[s
] < reload_nregs
[r
])
6183 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1, inheritance
);
6187 /* Now allocate reload registers for anything non-optional that
6188 didn't get one yet. */
6189 for (j
= 0; j
< n_reloads
; j
++)
6191 register int r
= reload_order
[j
];
6193 /* Ignore reloads that got marked inoperative. */
6194 if (reload_out
[r
] == 0 && reload_in
[r
] == 0 && ! reload_secondary_p
[r
])
6197 /* Skip reloads that already have a register allocated or are
6199 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
])
6202 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1, inheritance
))
6206 /* If that loop got all the way, we have won. */
6210 /* Loop around and try without any inheritance. */
6211 /* First undo everything done by the failed attempt
6212 to allocate with inheritance. */
6213 bcopy ((char *) save_reload_reg_rtx
, (char *) reload_reg_rtx
,
6214 sizeof reload_reg_rtx
);
6215 bcopy ((char *) save_reload_inherited
, (char *) reload_inherited
,
6216 sizeof reload_inherited
);
6217 bcopy ((char *) save_reload_inheritance_insn
,
6218 (char *) reload_inheritance_insn
,
6219 sizeof reload_inheritance_insn
);
6220 bcopy ((char *) save_reload_override_in
, (char *) reload_override_in
,
6221 sizeof reload_override_in
);
6222 bcopy ((char *) save_reload_spill_index
, (char *) reload_spill_index
,
6223 sizeof reload_spill_index
);
6224 COPY_HARD_REG_SET (reload_reg_used
, save_reload_reg_used
);
6225 COPY_HARD_REG_SET (reload_reg_used_at_all
, save_reload_reg_used_at_all
);
6226 COPY_HARD_REG_SET (reload_reg_used_in_op_addr
,
6227 save_reload_reg_used_in_op_addr
);
6228 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload
,
6229 save_reload_reg_used_in_op_addr_reload
);
6230 COPY_HARD_REG_SET (reload_reg_used_in_insn
,
6231 save_reload_reg_used_in_insn
);
6232 COPY_HARD_REG_SET (reload_reg_used_in_other_addr
,
6233 save_reload_reg_used_in_other_addr
);
6235 for (i
= 0; i
< reload_n_operands
; i
++)
6237 COPY_HARD_REG_SET (reload_reg_used_in_input
[i
],
6238 save_reload_reg_used_in_input
[i
]);
6239 COPY_HARD_REG_SET (reload_reg_used_in_output
[i
],
6240 save_reload_reg_used_in_output
[i
]);
6241 COPY_HARD_REG_SET (reload_reg_used_in_input_addr
[i
],
6242 save_reload_reg_used_in_input_addr
[i
]);
6243 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
],
6244 save_reload_reg_used_in_inpaddr_addr
[i
]);
6245 COPY_HARD_REG_SET (reload_reg_used_in_output_addr
[i
],
6246 save_reload_reg_used_in_output_addr
[i
]);
6247 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
],
6248 save_reload_reg_used_in_outaddr_addr
[i
]);
6252 /* If we thought we could inherit a reload, because it seemed that
6253 nothing else wanted the same reload register earlier in the insn,
6254 verify that assumption, now that all reloads have been assigned.
6255 Likewise for reloads where reload_override_in has been set. */
6257 /* If doing expensive optimizations, do one preliminary pass that doesn't
6258 cancel any inheritance, but removes reloads that have been needed only
6259 for reloads that we know can be inherited. */
6260 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6262 for (j
= 0; j
< n_reloads
; j
++)
6264 register int r
= reload_order
[j
];
6266 if (reload_inherited
[r
] && reload_reg_rtx
[r
])
6267 check_reg
= reload_reg_rtx
[r
];
6268 else if (reload_override_in
[r
]
6269 && (GET_CODE (reload_override_in
[r
]) == REG
6270 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6271 check_reg
= reload_override_in
[r
];
6274 if (! reload_reg_free_for_value_p (true_regnum (check_reg
),
6276 reload_when_needed
[r
],
6278 (reload_inherited
[r
]
6279 ? reload_out
[r
] : const0_rtx
),
6284 reload_inherited
[r
] = 0;
6285 reload_override_in
[r
] = 0;
6287 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6288 reload_override_in, then we do not need its related
6289 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6290 likewise for other reload types.
6291 We handle this by removing a reload when its only replacement
6292 is mentioned in reload_in of the reload we are going to inherit.
6293 A special case are auto_inc expressions; even if the input is
6294 inherited, we still need the address for the output. We can
6295 recognize them because they have RELOAD_OUT set but not
6297 If we suceeded removing some reload and we are doing a preliminary
6298 pass just to remove such reloads, make another pass, since the
6299 removal of one reload might allow us to inherit another one. */
6300 else if ((! reload_out
[r
] || reload_out_reg
[r
])
6301 && remove_address_replacements (reload_in
[r
]) && pass
)
6306 /* Now that reload_override_in is known valid,
6307 actually override reload_in. */
6308 for (j
= 0; j
< n_reloads
; j
++)
6309 if (reload_override_in
[j
])
6310 reload_in
[j
] = reload_override_in
[j
];
6312 /* If this reload won't be done because it has been cancelled or is
6313 optional and not inherited, clear reload_reg_rtx so other
6314 routines (such as subst_reloads) don't get confused. */
6315 for (j
= 0; j
< n_reloads
; j
++)
6316 if (reload_reg_rtx
[j
] != 0
6317 && ((reload_optional
[j
] && ! reload_inherited
[j
])
6318 || (reload_in
[j
] == 0 && reload_out
[j
] == 0
6319 && ! reload_secondary_p
[j
])))
6321 int regno
= true_regnum (reload_reg_rtx
[j
]);
6323 if (spill_reg_order
[regno
] >= 0)
6324 clear_reload_reg_in_use (regno
, reload_opnum
[j
],
6325 reload_when_needed
[j
], reload_mode
[j
]);
6326 reload_reg_rtx
[j
] = 0;
6329 /* Record which pseudos and which spill regs have output reloads. */
6330 for (j
= 0; j
< n_reloads
; j
++)
6332 register int r
= reload_order
[j
];
6334 i
= reload_spill_index
[r
];
6336 /* I is nonneg if this reload uses a register.
6337 If reload_reg_rtx[r] is 0, this is an optional reload
6338 that we opted to ignore. */
6339 if (reload_out_reg
[r
] != 0 && GET_CODE (reload_out_reg
[r
]) == REG
6340 && reload_reg_rtx
[r
] != 0)
6342 register int nregno
= REGNO (reload_out_reg
[r
]);
6345 if (nregno
< FIRST_PSEUDO_REGISTER
)
6346 nr
= HARD_REGNO_NREGS (nregno
, reload_mode
[r
]);
6349 reg_has_output_reload
[nregno
+ nr
] = 1;
6353 nr
= HARD_REGNO_NREGS (i
, reload_mode
[r
]);
6355 SET_HARD_REG_BIT (reg_is_output_reload
, i
+ nr
);
6358 if (reload_when_needed
[r
] != RELOAD_OTHER
6359 && reload_when_needed
[r
] != RELOAD_FOR_OUTPUT
6360 && reload_when_needed
[r
] != RELOAD_FOR_INSN
)
6366 /* Deallocate the reload register for reload R. This is called from
6367 remove_address_replacements. */
6369 deallocate_reload_reg (r
)
6374 if (! reload_reg_rtx
[r
])
6376 regno
= true_regnum (reload_reg_rtx
[r
]);
6377 reload_reg_rtx
[r
] = 0;
6378 if (spill_reg_order
[regno
] >= 0)
6379 clear_reload_reg_in_use (regno
, reload_opnum
[r
], reload_when_needed
[r
],
6381 reload_spill_index
[r
] = -1;
6384 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
6385 reloads of the same item for fear that we might not have enough reload
6386 registers. However, normally they will get the same reload register
6387 and hence actually need not be loaded twice.
6389 Here we check for the most common case of this phenomenon: when we have
6390 a number of reloads for the same object, each of which were allocated
6391 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6392 reload, and is not modified in the insn itself. If we find such,
6393 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6394 This will not increase the number of spill registers needed and will
6395 prevent redundant code. */
6398 merge_assigned_reloads (insn
)
6403 /* Scan all the reloads looking for ones that only load values and
6404 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6405 assigned and not modified by INSN. */
6407 for (i
= 0; i
< n_reloads
; i
++)
6409 int conflicting_input
= 0;
6410 int max_input_address_opnum
= -1;
6411 int min_conflicting_input_opnum
= MAX_RECOG_OPERANDS
;
6413 if (reload_in
[i
] == 0 || reload_when_needed
[i
] == RELOAD_OTHER
6414 || reload_out
[i
] != 0 || reload_reg_rtx
[i
] == 0
6415 || reg_set_p (reload_reg_rtx
[i
], insn
))
6418 /* Look at all other reloads. Ensure that the only use of this
6419 reload_reg_rtx is in a reload that just loads the same value
6420 as we do. Note that any secondary reloads must be of the identical
6421 class since the values, modes, and result registers are the
6422 same, so we need not do anything with any secondary reloads. */
6424 for (j
= 0; j
< n_reloads
; j
++)
6426 if (i
== j
|| reload_reg_rtx
[j
] == 0
6427 || ! reg_overlap_mentioned_p (reload_reg_rtx
[j
],
6431 if (reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6432 && reload_opnum
[j
] > max_input_address_opnum
)
6433 max_input_address_opnum
= reload_opnum
[j
];
6435 /* If the reload regs aren't exactly the same (e.g, different modes)
6436 or if the values are different, we can't merge this reload.
6437 But if it is an input reload, we might still merge
6438 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6440 if (! rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6441 || reload_out
[j
] != 0 || reload_in
[j
] == 0
6442 || ! rtx_equal_p (reload_in
[i
], reload_in
[j
]))
6444 if (reload_when_needed
[j
] != RELOAD_FOR_INPUT
6445 || ((reload_when_needed
[i
] != RELOAD_FOR_INPUT_ADDRESS
6446 || reload_opnum
[i
] > reload_opnum
[j
])
6447 && reload_when_needed
[i
] != RELOAD_FOR_OTHER_ADDRESS
))
6449 conflicting_input
= 1;
6450 if (min_conflicting_input_opnum
> reload_opnum
[j
])
6451 min_conflicting_input_opnum
= reload_opnum
[j
];
6455 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6456 we, in fact, found any matching reloads. */
6459 && max_input_address_opnum
<= min_conflicting_input_opnum
)
6461 for (j
= 0; j
< n_reloads
; j
++)
6462 if (i
!= j
&& reload_reg_rtx
[j
] != 0
6463 && rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
6464 && (! conflicting_input
6465 || reload_when_needed
[j
] == RELOAD_FOR_INPUT_ADDRESS
6466 || reload_when_needed
[j
] == RELOAD_FOR_OTHER_ADDRESS
))
6468 reload_when_needed
[i
] = RELOAD_OTHER
;
6470 reload_spill_index
[j
] = -1;
6471 transfer_replacements (i
, j
);
6474 /* If this is now RELOAD_OTHER, look for any reloads that load
6475 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6476 if they were for inputs, RELOAD_OTHER for outputs. Note that
6477 this test is equivalent to looking for reloads for this operand
6480 if (reload_when_needed
[i
] == RELOAD_OTHER
)
6481 for (j
= 0; j
< n_reloads
; j
++)
6482 if (reload_in
[j
] != 0
6483 && reload_when_needed
[i
] != RELOAD_OTHER
6484 && reg_overlap_mentioned_for_reload_p (reload_in
[j
],
6486 reload_when_needed
[j
]
6487 = ((reload_when_needed
[i
] == RELOAD_FOR_INPUT_ADDRESS
6488 || reload_when_needed
[i
] == RELOAD_FOR_INPADDR_ADDRESS
)
6489 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
);
6495 /* Output insns to reload values in and out of the chosen reload regs. */
6498 emit_reload_insns (chain
)
6499 struct insn_chain
*chain
;
6501 rtx insn
= chain
->insn
;
6504 rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
6505 rtx other_input_address_reload_insns
= 0;
6506 rtx other_input_reload_insns
= 0;
6507 rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
6508 rtx inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6509 rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
6510 rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
6511 rtx outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
6512 rtx operand_reload_insns
= 0;
6513 rtx other_operand_reload_insns
= 0;
6514 rtx other_output_reload_insns
[MAX_RECOG_OPERANDS
];
6515 rtx following_insn
= NEXT_INSN (insn
);
6516 rtx before_insn
= PREV_INSN (insn
);
6518 /* Values to be put in spill_reg_store are put here first. */
6519 rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
6520 HARD_REG_SET reg_reloaded_died
;
6522 CLEAR_HARD_REG_SET (reg_reloaded_died
);
6524 for (j
= 0; j
< reload_n_operands
; j
++)
6525 input_reload_insns
[j
] = input_address_reload_insns
[j
]
6526 = inpaddr_address_reload_insns
[j
]
6527 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
6528 = outaddr_address_reload_insns
[j
]
6529 = other_output_reload_insns
[j
] = 0;
6531 /* Now output the instructions to copy the data into and out of the
6532 reload registers. Do these in the order that the reloads were reported,
6533 since reloads of base and index registers precede reloads of operands
6534 and the operands may need the base and index registers reloaded. */
6536 for (j
= 0; j
< n_reloads
; j
++)
6539 rtx oldequiv_reg
= 0;
6540 rtx this_reload_insn
= 0;
6541 int expect_occurrences
= 1;
6543 if (reload_reg_rtx
[j
]
6544 && REGNO (reload_reg_rtx
[j
]) < FIRST_PSEUDO_REGISTER
)
6545 new_spill_reg_store
[REGNO (reload_reg_rtx
[j
])] = 0;
6547 old
= (reload_in
[j
] && GET_CODE (reload_in
[j
]) == MEM
6548 ? reload_in_reg
[j
] : reload_in
[j
]);
6551 /* AUTO_INC reloads need to be handled even if inherited. We got an
6552 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6553 && (! reload_inherited
[j
] || (reload_out
[j
] && ! reload_out_reg
[j
]))
6554 && ! rtx_equal_p (reload_reg_rtx
[j
], old
)
6555 && reload_reg_rtx
[j
] != 0)
6557 register rtx reloadreg
= reload_reg_rtx
[j
];
6559 enum machine_mode mode
;
6562 /* Determine the mode to reload in.
6563 This is very tricky because we have three to choose from.
6564 There is the mode the insn operand wants (reload_inmode[J]).
6565 There is the mode of the reload register RELOADREG.
6566 There is the intrinsic mode of the operand, which we could find
6567 by stripping some SUBREGs.
6568 It turns out that RELOADREG's mode is irrelevant:
6569 we can change that arbitrarily.
6571 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6572 then the reload reg may not support QImode moves, so use SImode.
6573 If foo is in memory due to spilling a pseudo reg, this is safe,
6574 because the QImode value is in the least significant part of a
6575 slot big enough for a SImode. If foo is some other sort of
6576 memory reference, then it is impossible to reload this case,
6577 so previous passes had better make sure this never happens.
6579 Then consider a one-word union which has SImode and one of its
6580 members is a float, being fetched as (SUBREG:SF union:SI).
6581 We must fetch that as SFmode because we could be loading into
6582 a float-only register. In this case OLD's mode is correct.
6584 Consider an immediate integer: it has VOIDmode. Here we need
6585 to get a mode from something else.
6587 In some cases, there is a fourth mode, the operand's
6588 containing mode. If the insn specifies a containing mode for
6589 this operand, it overrides all others.
6591 I am not sure whether the algorithm here is always right,
6592 but it does the right things in those cases. */
6594 mode
= GET_MODE (old
);
6595 if (mode
== VOIDmode
)
6596 mode
= reload_inmode
[j
];
6598 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6599 /* If we need a secondary register for this operation, see if
6600 the value is already in a register in that class. Don't
6601 do this if the secondary register will be used as a scratch
6604 if (reload_secondary_in_reload
[j
] >= 0
6605 && reload_secondary_in_icode
[j
] == CODE_FOR_nothing
6608 = find_equiv_reg (old
, insn
,
6609 reload_reg_class
[reload_secondary_in_reload
[j
]],
6610 -1, NULL_PTR
, 0, mode
);
6613 /* If reloading from memory, see if there is a register
6614 that already holds the same value. If so, reload from there.
6615 We can pass 0 as the reload_reg_p argument because
6616 any other reload has either already been emitted,
6617 in which case find_equiv_reg will see the reload-insn,
6618 or has yet to be emitted, in which case it doesn't matter
6619 because we will use this equiv reg right away. */
6621 if (oldequiv
== 0 && optimize
6622 && (GET_CODE (old
) == MEM
6623 || (GET_CODE (old
) == REG
6624 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6625 && reg_renumber
[REGNO (old
)] < 0)))
6626 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
,
6627 -1, NULL_PTR
, 0, mode
);
6631 int regno
= true_regnum (oldequiv
);
6633 /* Don't use OLDEQUIV if any other reload changes it at an
6634 earlier stage of this insn or at this stage. */
6635 if (! reload_reg_free_for_value_p (regno
, reload_opnum
[j
],
6636 reload_when_needed
[j
],
6637 reload_in
[j
], const0_rtx
, j
,
6641 /* If it is no cheaper to copy from OLDEQUIV into the
6642 reload register than it would be to move from memory,
6643 don't use it. Likewise, if we need a secondary register
6647 && ((REGNO_REG_CLASS (regno
) != reload_reg_class
[j
]
6648 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno
),
6649 reload_reg_class
[j
])
6650 >= MEMORY_MOVE_COST (mode
, reload_reg_class
[j
], 1)))
6651 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6652 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
6656 #ifdef SECONDARY_MEMORY_NEEDED
6657 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno
),
6658 reload_reg_class
[j
],
6665 /* delete_output_reload is only invoked properly if old contains
6666 the original pseudo register. Since this is replaced with a
6667 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6668 find the pseudo in RELOAD_IN_REG. */
6670 && reload_override_in
[j
]
6671 && GET_CODE (reload_in_reg
[j
]) == REG
)
6674 old
= reload_in_reg
[j
];
6678 else if (GET_CODE (oldequiv
) == REG
)
6679 oldequiv_reg
= oldequiv
;
6680 else if (GET_CODE (oldequiv
) == SUBREG
)
6681 oldequiv_reg
= SUBREG_REG (oldequiv
);
6683 /* If we are reloading from a register that was recently stored in
6684 with an output-reload, see if we can prove there was
6685 actually no need to store the old value in it. */
6687 if (optimize
&& GET_CODE (oldequiv
) == REG
6688 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6689 && spill_reg_store
[REGNO (oldequiv
)]
6690 && GET_CODE (old
) == REG
6691 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
6692 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6693 reload_out_reg
[j
])))
6694 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6696 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6697 then load RELOADREG from OLDEQUIV. Note that we cannot use
6698 gen_lowpart_common since it can do the wrong thing when
6699 RELOADREG has a multi-word mode. Note that RELOADREG
6700 must always be a REG here. */
6702 if (GET_MODE (reloadreg
) != mode
)
6703 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
6704 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
6705 oldequiv
= SUBREG_REG (oldequiv
);
6706 if (GET_MODE (oldequiv
) != VOIDmode
6707 && mode
!= GET_MODE (oldequiv
))
6708 oldequiv
= gen_rtx_SUBREG (mode
, oldequiv
, 0);
6710 /* Switch to the right place to emit the reload insns. */
6711 switch (reload_when_needed
[j
])
6714 where
= &other_input_reload_insns
;
6716 case RELOAD_FOR_INPUT
:
6717 where
= &input_reload_insns
[reload_opnum
[j
]];
6719 case RELOAD_FOR_INPUT_ADDRESS
:
6720 where
= &input_address_reload_insns
[reload_opnum
[j
]];
6722 case RELOAD_FOR_INPADDR_ADDRESS
:
6723 where
= &inpaddr_address_reload_insns
[reload_opnum
[j
]];
6725 case RELOAD_FOR_OUTPUT_ADDRESS
:
6726 where
= &output_address_reload_insns
[reload_opnum
[j
]];
6728 case RELOAD_FOR_OUTADDR_ADDRESS
:
6729 where
= &outaddr_address_reload_insns
[reload_opnum
[j
]];
6731 case RELOAD_FOR_OPERAND_ADDRESS
:
6732 where
= &operand_reload_insns
;
6734 case RELOAD_FOR_OPADDR_ADDR
:
6735 where
= &other_operand_reload_insns
;
6737 case RELOAD_FOR_OTHER_ADDRESS
:
6738 where
= &other_input_address_reload_insns
;
6744 push_to_sequence (*where
);
6747 /* Auto-increment addresses must be reloaded in a special way. */
6748 if (reload_out
[j
] && ! reload_out_reg
[j
])
6750 /* We are not going to bother supporting the case where a
6751 incremented register can't be copied directly from
6752 OLDEQUIV since this seems highly unlikely. */
6753 if (reload_secondary_in_reload
[j
] >= 0)
6756 if (reload_inherited
[j
])
6757 oldequiv
= reloadreg
;
6759 old
= XEXP (reload_in_reg
[j
], 0);
6761 if (optimize
&& GET_CODE (oldequiv
) == REG
6762 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
6763 && spill_reg_store
[REGNO (oldequiv
)]
6764 && GET_CODE (old
) == REG
6765 && (dead_or_set_p (insn
,
6766 spill_reg_stored_to
[REGNO (oldequiv
)])
6767 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
6769 delete_output_reload (insn
, j
, REGNO (oldequiv
));
6771 /* Prevent normal processing of this reload. */
6773 /* Output a special code sequence for this case. */
6774 new_spill_reg_store
[REGNO (reloadreg
)]
6775 = inc_for_reload (reloadreg
, oldequiv
, reload_out
[j
],
6779 /* If we are reloading a pseudo-register that was set by the previous
6780 insn, see if we can get rid of that pseudo-register entirely
6781 by redirecting the previous insn into our reload register. */
6783 else if (optimize
&& GET_CODE (old
) == REG
6784 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6785 && dead_or_set_p (insn
, old
)
6786 /* This is unsafe if some other reload
6787 uses the same reg first. */
6788 && reload_reg_free_for_value_p (REGNO (reloadreg
),
6790 reload_when_needed
[j
],
6794 rtx temp
= PREV_INSN (insn
);
6795 while (temp
&& GET_CODE (temp
) == NOTE
)
6796 temp
= PREV_INSN (temp
);
6798 && GET_CODE (temp
) == INSN
6799 && GET_CODE (PATTERN (temp
)) == SET
6800 && SET_DEST (PATTERN (temp
)) == old
6801 /* Make sure we can access insn_operand_constraint. */
6802 && asm_noperands (PATTERN (temp
)) < 0
6803 /* This is unsafe if prev insn rejects our reload reg. */
6804 && constraint_accepts_reg_p (insn_operand_constraint
[recog_memoized (temp
)][0],
6806 /* This is unsafe if operand occurs more than once in current
6807 insn. Perhaps some occurrences aren't reloaded. */
6808 && count_occurrences (PATTERN (insn
), old
) == 1
6809 /* Don't risk splitting a matching pair of operands. */
6810 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
6812 /* Store into the reload register instead of the pseudo. */
6813 SET_DEST (PATTERN (temp
)) = reloadreg
;
6815 /* If the previous insn is an output reload, the source is
6816 a reload register, and its spill_reg_store entry will
6817 contain the previous destination. This is now
6819 if (GET_CODE (SET_SRC (PATTERN (temp
))) == REG
6820 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
6822 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6823 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
6826 /* If these are the only uses of the pseudo reg,
6827 pretend for GDB it lives in the reload reg we used. */
6828 if (REG_N_DEATHS (REGNO (old
)) == 1
6829 && REG_N_SETS (REGNO (old
)) == 1)
6831 reg_renumber
[REGNO (old
)] = REGNO (reload_reg_rtx
[j
]);
6832 alter_reg (REGNO (old
), -1);
6838 /* We can't do that, so output an insn to load RELOADREG. */
6842 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6843 rtx second_reload_reg
= 0;
6844 enum insn_code icode
;
6846 /* If we have a secondary reload, pick up the secondary register
6847 and icode, if any. If OLDEQUIV and OLD are different or
6848 if this is an in-out reload, recompute whether or not we
6849 still need a secondary register and what the icode should
6850 be. If we still need a secondary register and the class or
6851 icode is different, go back to reloading from OLD if using
6852 OLDEQUIV means that we got the wrong type of register. We
6853 cannot have different class or icode due to an in-out reload
6854 because we don't make such reloads when both the input and
6855 output need secondary reload registers. */
6857 if (reload_secondary_in_reload
[j
] >= 0)
6859 int secondary_reload
= reload_secondary_in_reload
[j
];
6860 rtx real_oldequiv
= oldequiv
;
6863 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6864 and similarly for OLD.
6865 See comments in get_secondary_reload in reload.c. */
6866 /* If it is a pseudo that cannot be replaced with its
6867 equivalent MEM, we must fall back to reload_in, which
6868 will have all the necessary substitutions registered.
6869 Likewise for a pseudo that can't be replaced with its
6870 equivalent constant. */
6872 if (GET_CODE (oldequiv
) == REG
6873 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6874 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6875 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6877 if (! reg_equiv_mem
[REGNO (oldequiv
)]
6878 || num_not_at_initial_offset
)
6879 real_oldequiv
= reload_in
[j
];
6881 real_oldequiv
= reg_equiv_mem
[REGNO (oldequiv
)];
6884 if (GET_CODE (old
) == REG
6885 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
6886 && (reg_equiv_memory_loc
[REGNO (old
)] != 0
6887 || reg_equiv_constant
[REGNO (old
)] != 0))
6889 if (! reg_equiv_mem
[REGNO (old
)]
6890 || num_not_at_initial_offset
)
6891 real_old
= reload_in
[j
];
6893 real_old
= reg_equiv_mem
[REGNO (old
)];
6896 second_reload_reg
= reload_reg_rtx
[secondary_reload
];
6897 icode
= reload_secondary_in_icode
[j
];
6899 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
6900 || (reload_in
[j
] != 0 && reload_out
[j
] != 0))
6902 enum reg_class new_class
6903 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
6904 mode
, real_oldequiv
);
6906 if (new_class
== NO_REGS
)
6907 second_reload_reg
= 0;
6910 enum insn_code new_icode
;
6911 enum machine_mode new_mode
;
6913 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
6914 REGNO (second_reload_reg
)))
6915 oldequiv
= old
, real_oldequiv
= real_old
;
6918 new_icode
= reload_in_optab
[(int) mode
];
6919 if (new_icode
!= CODE_FOR_nothing
6920 && ((insn_operand_predicate
[(int) new_icode
][0]
6921 && ! ((*insn_operand_predicate
[(int) new_icode
][0])
6923 || (insn_operand_predicate
[(int) new_icode
][1]
6924 && ! ((*insn_operand_predicate
[(int) new_icode
][1])
6925 (real_oldequiv
, mode
)))))
6926 new_icode
= CODE_FOR_nothing
;
6928 if (new_icode
== CODE_FOR_nothing
)
6931 new_mode
= insn_operand_mode
[(int) new_icode
][2];
6933 if (GET_MODE (second_reload_reg
) != new_mode
)
6935 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
6937 oldequiv
= old
, real_oldequiv
= real_old
;
6940 = gen_rtx_REG (new_mode
,
6941 REGNO (second_reload_reg
));
6947 /* If we still need a secondary reload register, check
6948 to see if it is being used as a scratch or intermediate
6949 register and generate code appropriately. If we need
6950 a scratch register, use REAL_OLDEQUIV since the form of
6951 the insn may depend on the actual address if it is
6954 if (second_reload_reg
)
6956 if (icode
!= CODE_FOR_nothing
)
6958 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
6959 second_reload_reg
));
6964 /* See if we need a scratch register to load the
6965 intermediate register (a tertiary reload). */
6966 enum insn_code tertiary_icode
6967 = reload_secondary_in_icode
[secondary_reload
];
6969 if (tertiary_icode
!= CODE_FOR_nothing
)
6971 rtx third_reload_reg
6972 = reload_reg_rtx
[reload_secondary_in_reload
[secondary_reload
]];
6974 emit_insn ((GEN_FCN (tertiary_icode
)
6975 (second_reload_reg
, real_oldequiv
,
6976 third_reload_reg
)));
6979 gen_reload (second_reload_reg
, real_oldequiv
,
6981 reload_when_needed
[j
]);
6983 oldequiv
= second_reload_reg
;
6989 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
6991 rtx real_oldequiv
= oldequiv
;
6993 if ((GET_CODE (oldequiv
) == REG
6994 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
6995 && (reg_equiv_memory_loc
[REGNO (oldequiv
)] != 0
6996 || reg_equiv_constant
[REGNO (oldequiv
)] != 0))
6997 || (GET_CODE (oldequiv
) == SUBREG
6998 && GET_CODE (SUBREG_REG (oldequiv
)) == REG
6999 && (REGNO (SUBREG_REG (oldequiv
))
7000 >= FIRST_PSEUDO_REGISTER
)
7001 && ((reg_equiv_memory_loc
7002 [REGNO (SUBREG_REG (oldequiv
))] != 0)
7003 || (reg_equiv_constant
7004 [REGNO (SUBREG_REG (oldequiv
))] != 0))))
7005 real_oldequiv
= reload_in
[j
];
7006 gen_reload (reloadreg
, real_oldequiv
, reload_opnum
[j
],
7007 reload_when_needed
[j
]);
7012 this_reload_insn
= get_last_insn ();
7013 /* End this sequence. */
7014 *where
= get_insns ();
7017 /* Update reload_override_in so that delete_address_reloads_1
7018 can see the actual register usage. */
7020 reload_override_in
[j
] = oldequiv
;
7023 /* When inheriting a wider reload, we have a MEM in reload_in[j],
7024 e.g. inheriting a SImode output reload for
7025 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7026 if (optimize
&& reload_inherited
[j
] && reload_in
[j
]
7027 && GET_CODE (reload_in
[j
]) == MEM
7028 && GET_CODE (reload_in_reg
[j
]) == MEM
7029 && reload_spill_index
[j
] >= 0
7030 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7033 = count_occurrences (PATTERN (insn
), reload_in
[j
]) == 1 ? 0 : -1;
7035 = regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7038 /* If we are reloading a register that was recently stored in with an
7039 output-reload, see if we can prove there was
7040 actually no need to store the old value in it. */
7043 && (reload_inherited
[j
] || reload_override_in
[j
])
7044 && reload_reg_rtx
[j
]
7045 && GET_CODE (reload_reg_rtx
[j
]) == REG
7046 && spill_reg_store
[REGNO (reload_reg_rtx
[j
])] != 0
7048 /* There doesn't seem to be any reason to restrict this to pseudos
7049 and doing so loses in the case where we are copying from a
7050 register of the wrong class. */
7051 && REGNO (spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])])
7052 >= FIRST_PSEUDO_REGISTER
7054 /* The insn might have already some references to stackslots
7055 replaced by MEMs, while reload_out_reg still names the
7057 && (dead_or_set_p (insn
,
7058 spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])])
7059 || rtx_equal_p (spill_reg_stored_to
[REGNO (reload_reg_rtx
[j
])],
7060 reload_out_reg
[j
])))
7061 delete_output_reload (insn
, j
, REGNO (reload_reg_rtx
[j
]));
7063 /* Input-reloading is done. Now do output-reloading,
7064 storing the value from the reload-register after the main insn
7065 if reload_out[j] is nonzero.
7067 ??? At some point we need to support handling output reloads of
7068 JUMP_INSNs or insns that set cc0. */
7070 /* If this is an output reload that stores something that is
7071 not loaded in this same reload, see if we can eliminate a previous
7074 rtx pseudo
= reload_out_reg
[j
];
7077 && GET_CODE (pseudo
) == REG
7078 && ! rtx_equal_p (reload_in_reg
[j
], pseudo
)
7079 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7080 && reg_last_reload_reg
[REGNO (pseudo
)])
7082 int pseudo_no
= REGNO (pseudo
);
7083 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7085 /* We don't need to test full validity of last_regno for
7086 inherit here; we only want to know if the store actually
7087 matches the pseudo. */
7088 if (reg_reloaded_contents
[last_regno
] == pseudo_no
7089 && spill_reg_store
[last_regno
]
7090 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7091 delete_output_reload (insn
, j
, last_regno
);
7095 old
= reload_out_reg
[j
];
7097 && reload_reg_rtx
[j
] != old
7098 && reload_reg_rtx
[j
] != 0)
7100 register rtx reloadreg
= reload_reg_rtx
[j
];
7101 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7102 register rtx second_reloadreg
= 0;
7105 enum machine_mode mode
;
7108 /* An output operand that dies right away does need a reload,
7109 but need not be copied from it. Show the new location in the
7111 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
7112 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7114 XEXP (note
, 0) = reload_reg_rtx
[j
];
7117 /* Likewise for a SUBREG of an operand that dies. */
7118 else if (GET_CODE (old
) == SUBREG
7119 && GET_CODE (SUBREG_REG (old
)) == REG
7120 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
7123 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
),
7127 else if (GET_CODE (old
) == SCRATCH
)
7128 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7129 but we don't want to make an output reload. */
7133 /* Strip off of OLD any size-increasing SUBREGs such as
7134 (SUBREG:SI foo:QI 0). */
7136 while (GET_CODE (old
) == SUBREG
&& SUBREG_WORD (old
) == 0
7137 && (GET_MODE_SIZE (GET_MODE (old
))
7138 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old
)))))
7139 old
= SUBREG_REG (old
);
7142 /* If is a JUMP_INSN, we can't support output reloads yet. */
7143 if (GET_CODE (insn
) == JUMP_INSN
)
7146 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7149 push_to_sequence (output_reload_insns
[reload_opnum
[j
]]);
7151 old
= reload_out
[j
];
7153 /* Determine the mode to reload in.
7154 See comments above (for input reloading). */
7156 mode
= GET_MODE (old
);
7157 if (mode
== VOIDmode
)
7159 /* VOIDmode should never happen for an output. */
7160 if (asm_noperands (PATTERN (insn
)) < 0)
7161 /* It's the compiler's fault. */
7162 fatal_insn ("VOIDmode on an output", insn
);
7163 error_for_asm (insn
, "output operand is constant in `asm'");
7164 /* Prevent crash--use something we know is valid. */
7166 old
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7169 if (GET_MODE (reloadreg
) != mode
)
7170 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7172 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
7174 /* If we need two reload regs, set RELOADREG to the intermediate
7175 one, since it will be stored into OLD. We might need a secondary
7176 register only for an input reload, so check again here. */
7178 if (reload_secondary_out_reload
[j
] >= 0)
7182 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
7183 && reg_equiv_mem
[REGNO (old
)] != 0)
7184 real_old
= reg_equiv_mem
[REGNO (old
)];
7186 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class
[j
],
7190 second_reloadreg
= reloadreg
;
7191 reloadreg
= reload_reg_rtx
[reload_secondary_out_reload
[j
]];
7193 /* See if RELOADREG is to be used as a scratch register
7194 or as an intermediate register. */
7195 if (reload_secondary_out_icode
[j
] != CODE_FOR_nothing
)
7197 emit_insn ((GEN_FCN (reload_secondary_out_icode
[j
])
7198 (real_old
, second_reloadreg
, reloadreg
)));
7203 /* See if we need both a scratch and intermediate reload
7206 int secondary_reload
= reload_secondary_out_reload
[j
];
7207 enum insn_code tertiary_icode
7208 = reload_secondary_out_icode
[secondary_reload
];
7210 if (GET_MODE (reloadreg
) != mode
)
7211 reloadreg
= gen_rtx_REG (mode
, REGNO (reloadreg
));
7213 if (tertiary_icode
!= CODE_FOR_nothing
)
7216 = reload_reg_rtx
[reload_secondary_out_reload
[secondary_reload
]];
7219 /* Copy primary reload reg to secondary reload reg.
7220 (Note that these have been swapped above, then
7221 secondary reload reg to OLD using our insn. */
7223 /* If REAL_OLD is a paradoxical SUBREG, remove it
7224 and try to put the opposite SUBREG on
7226 if (GET_CODE (real_old
) == SUBREG
7227 && (GET_MODE_SIZE (GET_MODE (real_old
))
7228 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old
))))
7229 && 0 != (tem
= gen_lowpart_common
7230 (GET_MODE (SUBREG_REG (real_old
)),
7232 real_old
= SUBREG_REG (real_old
), reloadreg
= tem
;
7234 gen_reload (reloadreg
, second_reloadreg
,
7235 reload_opnum
[j
], reload_when_needed
[j
]);
7236 emit_insn ((GEN_FCN (tertiary_icode
)
7237 (real_old
, reloadreg
, third_reloadreg
)));
7242 /* Copy between the reload regs here and then to
7245 gen_reload (reloadreg
, second_reloadreg
,
7246 reload_opnum
[j
], reload_when_needed
[j
]);
7252 /* Output the last reload insn. */
7257 /* Don't output the last reload if OLD is not the dest of
7258 INSN and is in the src and is clobbered by INSN. */
7259 if (! flag_expensive_optimizations
7260 || GET_CODE (old
) != REG
7261 || !(set
= single_set (insn
))
7262 || rtx_equal_p (old
, SET_DEST (set
))
7263 || !reg_mentioned_p (old
, SET_SRC (set
))
7264 || !regno_clobbered_p (REGNO (old
), insn
))
7265 gen_reload (old
, reloadreg
, reload_opnum
[j
],
7266 reload_when_needed
[j
]);
7269 /* Look at all insns we emitted, just to be safe. */
7270 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7271 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
7273 rtx pat
= PATTERN (p
);
7275 /* If this output reload doesn't come from a spill reg,
7276 clear any memory of reloaded copies of the pseudo reg.
7277 If this output reload comes from a spill reg,
7278 reg_has_output_reload will make this do nothing. */
7279 note_stores (pat
, forget_old_reloads_1
);
7281 if (reg_mentioned_p (reload_reg_rtx
[j
], pat
))
7283 rtx set
= single_set (insn
);
7284 if (reload_spill_index
[j
] < 0
7286 && SET_SRC (set
) == reload_reg_rtx
[j
])
7288 int src
= REGNO (SET_SRC (set
));
7290 reload_spill_index
[j
] = src
;
7291 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7292 if (find_regno_note (insn
, REG_DEAD
, src
))
7293 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7295 if (REGNO (reload_reg_rtx
[j
]) < FIRST_PSEUDO_REGISTER
)
7297 int s
= reload_secondary_out_reload
[j
];
7298 set
= single_set (p
);
7299 /* If this reload copies only to the secondary reload
7300 register, the secondary reload does the actual
7302 if (s
>= 0 && set
== NULL_RTX
)
7303 ; /* We can't tell what function the secondary reload
7304 has and where the actual store to the pseudo is
7305 made; leave new_spill_reg_store alone. */
7307 && SET_SRC (set
) == reload_reg_rtx
[j
]
7308 && SET_DEST (set
) == reload_reg_rtx
[s
])
7310 /* Usually the next instruction will be the
7311 secondary reload insn; if we can confirm
7312 that it is, setting new_spill_reg_store to
7313 that insn will allow an extra optimization. */
7314 rtx s_reg
= reload_reg_rtx
[s
];
7315 rtx next
= NEXT_INSN (p
);
7316 reload_out
[s
] = reload_out
[j
];
7317 reload_out_reg
[s
] = reload_out_reg
[j
];
7318 set
= single_set (next
);
7319 if (set
&& SET_SRC (set
) == s_reg
7320 && ! new_spill_reg_store
[REGNO (s_reg
)])
7322 SET_HARD_REG_BIT (reg_is_output_reload
,
7324 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7328 new_spill_reg_store
[REGNO (reload_reg_rtx
[j
])] = p
;
7333 if (reload_when_needed
[j
] == RELOAD_OTHER
)
7335 emit_insns (other_output_reload_insns
[reload_opnum
[j
]]);
7336 other_output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7339 output_reload_insns
[reload_opnum
[j
]] = get_insns ();
7345 /* Now write all the insns we made for reloads in the order expected by
7346 the allocation functions. Prior to the insn being reloaded, we write
7347 the following reloads:
7349 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7351 RELOAD_OTHER reloads.
7353 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7354 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7355 RELOAD_FOR_INPUT reload for the operand.
7357 RELOAD_FOR_OPADDR_ADDRS reloads.
7359 RELOAD_FOR_OPERAND_ADDRESS reloads.
7361 After the insn being reloaded, we write the following:
7363 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7364 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7365 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7366 reloads for the operand. The RELOAD_OTHER output reloads are
7367 output in descending order by reload number. */
7369 emit_insns_before (other_input_address_reload_insns
, insn
);
7370 emit_insns_before (other_input_reload_insns
, insn
);
7372 for (j
= 0; j
< reload_n_operands
; j
++)
7374 emit_insns_before (inpaddr_address_reload_insns
[j
], insn
);
7375 emit_insns_before (input_address_reload_insns
[j
], insn
);
7376 emit_insns_before (input_reload_insns
[j
], insn
);
7379 emit_insns_before (other_operand_reload_insns
, insn
);
7380 emit_insns_before (operand_reload_insns
, insn
);
7382 for (j
= 0; j
< reload_n_operands
; j
++)
7384 emit_insns_before (outaddr_address_reload_insns
[j
], following_insn
);
7385 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
7386 emit_insns_before (output_reload_insns
[j
], following_insn
);
7387 emit_insns_before (other_output_reload_insns
[j
], following_insn
);
7390 /* Keep basic block info up to date. */
7393 if (BLOCK_HEAD (chain
->block
) == insn
)
7394 BLOCK_HEAD (chain
->block
) = NEXT_INSN (before_insn
);
7395 if (BLOCK_END (chain
->block
) == insn
)
7396 BLOCK_END (chain
->block
) = PREV_INSN (following_insn
);
7399 /* For all the spill regs newly reloaded in this instruction,
7400 record what they were reloaded from, so subsequent instructions
7401 can inherit the reloads.
7403 Update spill_reg_store for the reloads of this insn.
7404 Copy the elements that were updated in the loop above. */
7406 for (j
= 0; j
< n_reloads
; j
++)
7408 register int r
= reload_order
[j
];
7409 register int i
= reload_spill_index
[r
];
7411 /* If this is a non-inherited input reload from a pseudo, we must
7412 clear any memory of a previous store to the same pseudo. Only do
7413 something if there will not be an output reload for the pseudo
7415 if (reload_in_reg
[r
] != 0
7416 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
7418 rtx reg
= reload_in_reg
[r
];
7420 if (GET_CODE (reg
) == SUBREG
)
7421 reg
= SUBREG_REG (reg
);
7423 if (GET_CODE (reg
) == REG
7424 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
7425 && ! reg_has_output_reload
[REGNO (reg
)])
7427 int nregno
= REGNO (reg
);
7429 if (reg_last_reload_reg
[nregno
])
7431 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
7433 if (reg_reloaded_contents
[last_regno
] == nregno
)
7434 spill_reg_store
[last_regno
] = 0;
7439 /* I is nonneg if this reload used a register.
7440 If reload_reg_rtx[r] is 0, this is an optional reload
7441 that we opted to ignore. */
7443 if (i
>= 0 && reload_reg_rtx
[r
] != 0)
7446 = HARD_REGNO_NREGS (i
, GET_MODE (reload_reg_rtx
[r
]));
7448 int part_reaches_end
= 0;
7449 int all_reaches_end
= 1;
7451 /* For a multi register reload, we need to check if all or part
7452 of the value lives to the end. */
7453 for (k
= 0; k
< nr
; k
++)
7455 if (reload_reg_reaches_end_p (i
+ k
, reload_opnum
[r
],
7456 reload_when_needed
[r
]))
7457 part_reaches_end
= 1;
7459 all_reaches_end
= 0;
7462 /* Ignore reloads that don't reach the end of the insn in
7464 if (all_reaches_end
)
7466 /* First, clear out memory of what used to be in this spill reg.
7467 If consecutive registers are used, clear them all. */
7469 for (k
= 0; k
< nr
; k
++)
7470 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7472 /* Maybe the spill reg contains a copy of reload_out. */
7473 if (reload_out
[r
] != 0
7474 && (GET_CODE (reload_out
[r
]) == REG
7476 || ! reload_out_reg
[r
]
7478 || GET_CODE (reload_out_reg
[r
]) == REG
))
7480 rtx out
= (GET_CODE (reload_out
[r
]) == REG
7484 /* AUTO_INC */ : XEXP (reload_in_reg
[r
], 0));
7485 register int nregno
= REGNO (out
);
7486 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7487 : HARD_REGNO_NREGS (nregno
,
7488 GET_MODE (reload_reg_rtx
[r
])));
7490 spill_reg_store
[i
] = new_spill_reg_store
[i
];
7491 spill_reg_stored_to
[i
] = out
;
7492 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7494 /* If NREGNO is a hard register, it may occupy more than
7495 one register. If it does, say what is in the
7496 rest of the registers assuming that both registers
7497 agree on how many words the object takes. If not,
7498 invalidate the subsequent registers. */
7500 if (nregno
< FIRST_PSEUDO_REGISTER
)
7501 for (k
= 1; k
< nnr
; k
++)
7502 reg_last_reload_reg
[nregno
+ k
]
7504 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7505 REGNO (reload_reg_rtx
[r
]) + k
)
7508 /* Now do the inverse operation. */
7509 for (k
= 0; k
< nr
; k
++)
7511 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7512 reg_reloaded_contents
[i
+ k
]
7513 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7516 reg_reloaded_insn
[i
+ k
] = insn
;
7517 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7521 /* Maybe the spill reg contains a copy of reload_in. Only do
7522 something if there will not be an output reload for
7523 the register being reloaded. */
7524 else if (reload_out_reg
[r
] == 0
7525 && reload_in
[r
] != 0
7526 && ((GET_CODE (reload_in
[r
]) == REG
7527 && REGNO (reload_in
[r
]) >= FIRST_PSEUDO_REGISTER
7528 && ! reg_has_output_reload
[REGNO (reload_in
[r
])])
7529 || (GET_CODE (reload_in_reg
[r
]) == REG
7530 && ! reg_has_output_reload
[REGNO (reload_in_reg
[r
])]))
7531 && ! reg_set_p (reload_reg_rtx
[r
], PATTERN (insn
)))
7533 register int nregno
;
7536 if (GET_CODE (reload_in
[r
]) == REG
7537 && REGNO (reload_in
[r
]) >= FIRST_PSEUDO_REGISTER
)
7538 nregno
= REGNO (reload_in
[r
]);
7539 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
7540 nregno
= REGNO (reload_in_reg
[r
]);
7542 nregno
= REGNO (XEXP (reload_in_reg
[r
], 0));
7544 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
7545 : HARD_REGNO_NREGS (nregno
,
7546 GET_MODE (reload_reg_rtx
[r
])));
7548 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
7550 if (nregno
< FIRST_PSEUDO_REGISTER
)
7551 for (k
= 1; k
< nnr
; k
++)
7552 reg_last_reload_reg
[nregno
+ k
]
7554 ? gen_rtx_REG (reg_raw_mode
[REGNO (reload_reg_rtx
[r
]) + k
],
7555 REGNO (reload_reg_rtx
[r
]) + k
)
7558 /* Unless we inherited this reload, show we haven't
7559 recently done a store.
7560 Previous stores of inherited auto_inc expressions
7561 also have to be discarded. */
7562 if (! reload_inherited
[r
]
7563 || (reload_out
[r
] && ! reload_out_reg
[r
]))
7564 spill_reg_store
[i
] = 0;
7566 for (k
= 0; k
< nr
; k
++)
7568 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, i
+ k
);
7569 reg_reloaded_contents
[i
+ k
]
7570 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
7573 reg_reloaded_insn
[i
+ k
] = insn
;
7574 SET_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7579 /* However, if part of the reload reaches the end, then we must
7580 invalidate the old info for the part that survives to the end. */
7581 else if (part_reaches_end
)
7583 for (k
= 0; k
< nr
; k
++)
7584 if (reload_reg_reaches_end_p (i
+ k
,
7586 reload_when_needed
[r
]))
7587 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
7591 /* The following if-statement was #if 0'd in 1.34 (or before...).
7592 It's reenabled in 1.35 because supposedly nothing else
7593 deals with this problem. */
7595 /* If a register gets output-reloaded from a non-spill register,
7596 that invalidates any previous reloaded copy of it.
7597 But forget_old_reloads_1 won't get to see it, because
7598 it thinks only about the original insn. So invalidate it here. */
7599 if (i
< 0 && reload_out
[r
] != 0
7600 && (GET_CODE (reload_out
[r
]) == REG
7601 || (GET_CODE (reload_out
[r
]) == MEM
7602 && GET_CODE (reload_out_reg
[r
]) == REG
)))
7604 rtx out
= (GET_CODE (reload_out
[r
]) == REG
7605 ? reload_out
[r
] : reload_out_reg
[r
]);
7606 register int nregno
= REGNO (out
);
7607 if (nregno
>= FIRST_PSEUDO_REGISTER
)
7609 rtx src_reg
, store_insn
;
7611 reg_last_reload_reg
[nregno
] = 0;
7613 /* If we can find a hard register that is stored, record
7614 the storing insn so that we may delete this insn with
7615 delete_output_reload. */
7616 src_reg
= reload_reg_rtx
[r
];
7618 /* If this is an optional reload, try to find the source reg
7619 from an input reload. */
7622 rtx set
= single_set (insn
);
7623 if (set
&& SET_DEST (set
) == reload_out
[r
])
7627 src_reg
= SET_SRC (set
);
7629 for (k
= 0; k
< n_reloads
; k
++)
7631 if (reload_in
[k
] == src_reg
)
7633 src_reg
= reload_reg_rtx
[k
];
7640 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
7641 if (src_reg
&& GET_CODE (src_reg
) == REG
7642 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
7644 int src_regno
= REGNO (src_reg
);
7645 int nr
= HARD_REGNO_NREGS (src_regno
, reload_mode
[r
]);
7646 /* The place where to find a death note varies with
7647 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7648 necessarily checked exactly in the code that moves
7649 notes, so just check both locations. */
7650 rtx note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
7652 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
7655 spill_reg_store
[src_regno
+ nr
] = store_insn
;
7656 spill_reg_stored_to
[src_regno
+ nr
] = out
;
7657 reg_reloaded_contents
[src_regno
+ nr
] = nregno
;
7658 reg_reloaded_insn
[src_regno
+ nr
] = store_insn
;
7659 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ nr
);
7660 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ nr
);
7661 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ nr
);
7663 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7665 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
7667 reg_last_reload_reg
[nregno
] = src_reg
;
7672 int num_regs
= HARD_REGNO_NREGS (nregno
,GET_MODE (reload_out
[r
]));
7674 while (num_regs
-- > 0)
7675 reg_last_reload_reg
[nregno
+ num_regs
] = 0;
7679 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
7682 /* Emit code to perform a reload from IN (which may be a reload register) to
7683 OUT (which may also be a reload register). IN or OUT is from operand
7684 OPNUM with reload type TYPE.
7686 Returns first insn emitted. */
7689 gen_reload (out
, in
, opnum
, type
)
7693 enum reload_type type
;
7695 rtx last
= get_last_insn ();
7698 /* If IN is a paradoxical SUBREG, remove it and try to put the
7699 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7700 if (GET_CODE (in
) == SUBREG
7701 && (GET_MODE_SIZE (GET_MODE (in
))
7702 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in
))))
7703 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (in
)), out
)) != 0)
7704 in
= SUBREG_REG (in
), out
= tem
;
7705 else if (GET_CODE (out
) == SUBREG
7706 && (GET_MODE_SIZE (GET_MODE (out
))
7707 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out
))))
7708 && (tem
= gen_lowpart_common (GET_MODE (SUBREG_REG (out
)), in
)) != 0)
7709 out
= SUBREG_REG (out
), in
= tem
;
7711 /* How to do this reload can get quite tricky. Normally, we are being
7712 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7713 register that didn't get a hard register. In that case we can just
7714 call emit_move_insn.
7716 We can also be asked to reload a PLUS that adds a register or a MEM to
7717 another register, constant or MEM. This can occur during frame pointer
7718 elimination and while reloading addresses. This case is handled by
7719 trying to emit a single insn to perform the add. If it is not valid,
7720 we use a two insn sequence.
7722 Finally, we could be called to handle an 'o' constraint by putting
7723 an address into a register. In that case, we first try to do this
7724 with a named pattern of "reload_load_address". If no such pattern
7725 exists, we just emit a SET insn and hope for the best (it will normally
7726 be valid on machines that use 'o').
7728 This entire process is made complex because reload will never
7729 process the insns we generate here and so we must ensure that
7730 they will fit their constraints and also by the fact that parts of
7731 IN might be being reloaded separately and replaced with spill registers.
7732 Because of this, we are, in some sense, just guessing the right approach
7733 here. The one listed above seems to work.
7735 ??? At some point, this whole thing needs to be rethought. */
7737 if (GET_CODE (in
) == PLUS
7738 && (GET_CODE (XEXP (in
, 0)) == REG
7739 || GET_CODE (XEXP (in
, 0)) == SUBREG
7740 || GET_CODE (XEXP (in
, 0)) == MEM
)
7741 && (GET_CODE (XEXP (in
, 1)) == REG
7742 || GET_CODE (XEXP (in
, 1)) == SUBREG
7743 || CONSTANT_P (XEXP (in
, 1))
7744 || GET_CODE (XEXP (in
, 1)) == MEM
))
7746 /* We need to compute the sum of a register or a MEM and another
7747 register, constant, or MEM, and put it into the reload
7748 register. The best possible way of doing this is if the machine
7749 has a three-operand ADD insn that accepts the required operands.
7751 The simplest approach is to try to generate such an insn and see if it
7752 is recognized and matches its constraints. If so, it can be used.
7754 It might be better not to actually emit the insn unless it is valid,
7755 but we need to pass the insn as an operand to `recog' and
7756 `extract_insn' and it is simpler to emit and then delete the insn if
7757 not valid than to dummy things up. */
7759 rtx op0
, op1
, tem
, insn
;
7762 op0
= find_replacement (&XEXP (in
, 0));
7763 op1
= find_replacement (&XEXP (in
, 1));
7765 /* Since constraint checking is strict, commutativity won't be
7766 checked, so we need to do that here to avoid spurious failure
7767 if the add instruction is two-address and the second operand
7768 of the add is the same as the reload reg, which is frequently
7769 the case. If the insn would be A = B + A, rearrange it so
7770 it will be A = A + B as constrain_operands expects. */
7772 if (GET_CODE (XEXP (in
, 1)) == REG
7773 && REGNO (out
) == REGNO (XEXP (in
, 1)))
7774 tem
= op0
, op0
= op1
, op1
= tem
;
7776 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
7777 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
7779 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7780 code
= recog_memoized (insn
);
7784 extract_insn (insn
);
7785 /* We want constrain operands to treat this insn strictly in
7786 its validity determination, i.e., the way it would after reload
7788 if (constrain_operands (1))
7792 delete_insns_since (last
);
7794 /* If that failed, we must use a conservative two-insn sequence.
7795 use move to copy constant, MEM, or pseudo register to the reload
7796 register since "move" will be able to handle an arbitrary operand,
7797 unlike add which can't, in general. Then add the registers.
7799 If there is another way to do this for a specific machine, a
7800 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7803 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
|| GET_CODE (op1
) == SUBREG
7804 || (GET_CODE (op1
) == REG
7805 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
))
7806 tem
= op0
, op0
= op1
, op1
= tem
;
7808 gen_reload (out
, op0
, opnum
, type
);
7810 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7811 This fixes a problem on the 32K where the stack pointer cannot
7812 be used as an operand of an add insn. */
7814 if (rtx_equal_p (op0
, op1
))
7817 insn
= emit_insn (gen_add2_insn (out
, op1
));
7819 /* If that failed, copy the address register to the reload register.
7820 Then add the constant to the reload register. */
7822 code
= recog_memoized (insn
);
7826 extract_insn (insn
);
7827 /* We want constrain operands to treat this insn strictly in
7828 its validity determination, i.e., the way it would after reload
7830 if (constrain_operands (1))
7832 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7834 = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7839 delete_insns_since (last
);
7841 gen_reload (out
, op1
, opnum
, type
);
7842 insn
= emit_insn (gen_add2_insn (out
, op0
));
7843 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUIV
, in
, REG_NOTES (insn
));
7846 #ifdef SECONDARY_MEMORY_NEEDED
7847 /* If we need a memory location to do the move, do it that way. */
7848 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
7849 && GET_CODE (out
) == REG
&& REGNO (out
) < FIRST_PSEUDO_REGISTER
7850 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
7851 REGNO_REG_CLASS (REGNO (out
)),
7854 /* Get the memory to use and rewrite both registers to its mode. */
7855 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
7857 if (GET_MODE (loc
) != GET_MODE (out
))
7858 out
= gen_rtx_REG (GET_MODE (loc
), REGNO (out
));
7860 if (GET_MODE (loc
) != GET_MODE (in
))
7861 in
= gen_rtx_REG (GET_MODE (loc
), REGNO (in
));
7863 gen_reload (loc
, in
, opnum
, type
);
7864 gen_reload (out
, loc
, opnum
, type
);
7868 /* If IN is a simple operand, use gen_move_insn. */
7869 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
7870 emit_insn (gen_move_insn (out
, in
));
7872 #ifdef HAVE_reload_load_address
7873 else if (HAVE_reload_load_address
)
7874 emit_insn (gen_reload_load_address (out
, in
));
7877 /* Otherwise, just write (set OUT IN) and hope for the best. */
7879 emit_insn (gen_rtx_SET (VOIDmode
, out
, in
));
7881 /* Return the first insn emitted.
7882 We can not just return get_last_insn, because there may have
7883 been multiple instructions emitted. Also note that gen_move_insn may
7884 emit more than one insn itself, so we can not assume that there is one
7885 insn emitted per emit_insn_before call. */
7887 return last
? NEXT_INSN (last
) : get_insns ();
7890 /* Delete a previously made output-reload
7891 whose result we now believe is not needed.
7892 First we double-check.
7894 INSN is the insn now being processed.
7895 LAST_RELOAD_REG is the hard register number for which we want to delete
7896 the last output reload.
7897 J is the reload-number that originally used REG. The caller has made
7898 certain that reload J doesn't use REG any longer for input. */
7901 delete_output_reload (insn
, j
, last_reload_reg
)
7904 int last_reload_reg
;
7906 rtx output_reload_insn
= spill_reg_store
[last_reload_reg
];
7907 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
7910 int n_inherited
= 0;
7914 /* Get the raw pseudo-register referred to. */
7916 while (GET_CODE (reg
) == SUBREG
)
7917 reg
= SUBREG_REG (reg
);
7918 substed
= reg_equiv_memory_loc
[REGNO (reg
)];
7920 /* This is unsafe if the operand occurs more often in the current
7921 insn than it is inherited. */
7922 for (k
= n_reloads
- 1; k
>= 0; k
--)
7924 rtx reg2
= reload_in
[k
];
7927 if (GET_CODE (reg2
) == MEM
|| reload_override_in
[k
])
7928 reg2
= reload_in_reg
[k
];
7930 if (reload_out
[k
] && ! reload_out_reg
[k
])
7931 reg2
= XEXP (reload_in_reg
[k
], 0);
7933 while (GET_CODE (reg2
) == SUBREG
)
7934 reg2
= SUBREG_REG (reg2
);
7935 if (rtx_equal_p (reg2
, reg
))
7937 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
7940 reg2
= reload_out_reg
[k
];
7943 while (GET_CODE (reg2
) == SUBREG
)
7944 reg2
= XEXP (reg2
, 0);
7945 if (rtx_equal_p (reg2
, reg
))
7952 n_occurrences
= count_occurrences (PATTERN (insn
), reg
);
7954 n_occurrences
+= count_occurrences (PATTERN (insn
), substed
);
7955 if (n_occurrences
> n_inherited
)
7958 /* If the pseudo-reg we are reloading is no longer referenced
7959 anywhere between the store into it and here,
7960 and no jumps or labels intervene, then the value can get
7961 here through the reload reg alone.
7962 Otherwise, give up--return. */
7963 for (i1
= NEXT_INSN (output_reload_insn
);
7964 i1
!= insn
; i1
= NEXT_INSN (i1
))
7966 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
7968 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
7969 && reg_mentioned_p (reg
, PATTERN (i1
)))
7971 /* If this is USE in front of INSN, we only have to check that
7972 there are no more references than accounted for by inheritance. */
7973 while (GET_CODE (i1
) == INSN
&& GET_CODE (PATTERN (i1
)) == USE
)
7975 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
7976 i1
= NEXT_INSN (i1
);
7978 if (n_occurrences
<= n_inherited
&& i1
== insn
)
7984 /* The caller has already checked that REG dies or is set in INSN.
7985 It has also checked that we are optimizing, and thus some inaccurancies
7986 in the debugging information are acceptable.
7987 So we could just delete output_reload_insn.
7988 But in some cases we can improve the debugging information without
7989 sacrificing optimization - maybe even improving the code:
7990 See if the pseudo reg has been completely replaced
7991 with reload regs. If so, delete the store insn
7992 and forget we had a stack slot for the pseudo. */
7993 if (reload_out
[j
] != reload_in
[j
]
7994 && REG_N_DEATHS (REGNO (reg
)) == 1
7995 && REG_N_SETS (REGNO (reg
)) == 1
7996 && REG_BASIC_BLOCK (REGNO (reg
)) >= 0
7997 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8001 /* We know that it was used only between here
8002 and the beginning of the current basic block.
8003 (We also know that the last use before INSN was
8004 the output reload we are thinking of deleting, but never mind that.)
8005 Search that range; see if any ref remains. */
8006 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8008 rtx set
= single_set (i2
);
8010 /* Uses which just store in the pseudo don't count,
8011 since if they are the only uses, they are dead. */
8012 if (set
!= 0 && SET_DEST (set
) == reg
)
8014 if (GET_CODE (i2
) == CODE_LABEL
8015 || GET_CODE (i2
) == JUMP_INSN
)
8017 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
8018 && reg_mentioned_p (reg
, PATTERN (i2
)))
8020 /* Some other ref remains; just delete the output reload we
8022 delete_address_reloads (output_reload_insn
, insn
);
8023 PUT_CODE (output_reload_insn
, NOTE
);
8024 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
8025 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
8030 /* Delete the now-dead stores into this pseudo. */
8031 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8033 rtx set
= single_set (i2
);
8035 if (set
!= 0 && SET_DEST (set
) == reg
)
8037 delete_address_reloads (i2
, insn
);
8038 /* This might be a basic block head,
8039 thus don't use delete_insn. */
8040 PUT_CODE (i2
, NOTE
);
8041 NOTE_SOURCE_FILE (i2
) = 0;
8042 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
8044 if (GET_CODE (i2
) == CODE_LABEL
8045 || GET_CODE (i2
) == JUMP_INSN
)
8049 /* For the debugging info,
8050 say the pseudo lives in this reload reg. */
8051 reg_renumber
[REGNO (reg
)] = REGNO (reload_reg_rtx
[j
]);
8052 alter_reg (REGNO (reg
), -1);
8054 delete_address_reloads (output_reload_insn
, insn
);
8055 PUT_CODE (output_reload_insn
, NOTE
);
8056 NOTE_SOURCE_FILE (output_reload_insn
) = 0;
8057 NOTE_LINE_NUMBER (output_reload_insn
) = NOTE_INSN_DELETED
;
8061 /* We are going to delete DEAD_INSN. Recursively delete loads of
8062 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8063 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8065 delete_address_reloads (dead_insn
, current_insn
)
8066 rtx dead_insn
, current_insn
;
8068 rtx set
= single_set (dead_insn
);
8069 rtx set2
, dst
, prev
, next
;
8072 rtx dst
= SET_DEST (set
);
8073 if (GET_CODE (dst
) == MEM
)
8074 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8076 /* If we deleted the store from a reloaded post_{in,de}c expression,
8077 we can delete the matching adds. */
8078 prev
= PREV_INSN (dead_insn
);
8079 next
= NEXT_INSN (dead_insn
);
8080 if (! prev
|| ! next
)
8082 set
= single_set (next
);
8083 set2
= single_set (prev
);
8085 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8086 || GET_CODE (XEXP (SET_SRC (set
), 1)) != CONST_INT
8087 || GET_CODE (XEXP (SET_SRC (set2
), 1)) != CONST_INT
)
8089 dst
= SET_DEST (set
);
8090 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8091 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8092 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8093 || (INTVAL (XEXP (SET_SRC (set
), 1))
8094 != - INTVAL (XEXP (SET_SRC (set2
), 1))))
8100 /* Subfunction of delete_address_reloads: process registers found in X. */
8102 delete_address_reloads_1 (dead_insn
, x
, current_insn
)
8103 rtx dead_insn
, x
, current_insn
;
8105 rtx prev
, set
, dst
, i2
;
8107 enum rtx_code code
= GET_CODE (x
);
8111 char *fmt
= GET_RTX_FORMAT (code
);
8112 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8115 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8116 else if (fmt
[i
] == 'E')
8118 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
8119 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8126 if (spill_reg_order
[REGNO (x
)] < 0)
8129 /* Scan backwards for the insn that sets x. This might be a way back due
8131 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8133 code
= GET_CODE (prev
);
8134 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8136 if (GET_RTX_CLASS (code
) != 'i')
8138 if (reg_set_p (x
, PATTERN (prev
)))
8140 if (reg_referenced_p (x
, PATTERN (prev
)))
8143 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8145 /* Check that PREV only sets the reload register. */
8146 set
= single_set (prev
);
8149 dst
= SET_DEST (set
);
8150 if (GET_CODE (dst
) != REG
8151 || ! rtx_equal_p (dst
, x
))
8153 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8155 /* Check if DST was used in a later insn -
8156 it might have been inherited. */
8157 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8159 if (GET_CODE (i2
) == CODE_LABEL
)
8161 if (GET_RTX_CLASS (GET_CODE (i2
)) != 'i')
8163 if (reg_referenced_p (dst
, PATTERN (i2
)))
8165 /* If there is a reference to the register in the current insn,
8166 it might be loaded in a non-inherited reload. If no other
8167 reload uses it, that means the register is set before
8169 if (i2
== current_insn
)
8171 for (j
= n_reloads
- 1; j
>= 0; j
--)
8172 if ((reload_reg_rtx
[j
] == dst
&& reload_inherited
[j
])
8173 || reload_override_in
[j
] == dst
)
8175 for (j
= n_reloads
- 1; j
>= 0; j
--)
8176 if (reload_in
[j
] && reload_reg_rtx
[j
] == dst
)
8183 if (GET_CODE (i2
) == JUMP_INSN
)
8185 /* If DST is still live at CURRENT_INSN, check if it is used for
8186 any reload. Note that even if CURRENT_INSN sets DST, we still
8187 have to check the reloads. */
8188 if (i2
== current_insn
)
8190 for (j
= n_reloads
- 1; j
>= 0; j
--)
8191 if ((reload_reg_rtx
[j
] == dst
&& reload_inherited
[j
])
8192 || reload_override_in
[j
] == dst
)
8194 /* ??? We can't finish the loop here, because dst might be
8195 allocated to a pseudo in this block if no reload in this
8196 block needs any of the clsses containing DST - see
8197 spill_hard_reg. There is no easy way to tell this, so we
8198 have to scan till the end of the basic block. */
8200 if (reg_set_p (dst
, PATTERN (i2
)))
8204 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
8205 reg_reloaded_contents
[REGNO (dst
)] = -1;
8206 /* Can't use delete_insn here because PREV might be a basic block head. */
8207 PUT_CODE (prev
, NOTE
);
8208 NOTE_LINE_NUMBER (prev
) = NOTE_INSN_DELETED
;
8209 NOTE_SOURCE_FILE (prev
) = 0;
8212 /* Output reload-insns to reload VALUE into RELOADREG.
8213 VALUE is an autoincrement or autodecrement RTX whose operand
8214 is a register or memory location;
8215 so reloading involves incrementing that location.
8216 IN is either identical to VALUE, or some cheaper place to reload from.
8218 INC_AMOUNT is the number to increment or decrement by (always positive).
8219 This cannot be deduced from VALUE.
8221 Return the instruction that stores into RELOADREG. */
8224 inc_for_reload (reloadreg
, in
, value
, inc_amount
)
8229 /* REG or MEM to be copied and incremented. */
8230 rtx incloc
= XEXP (value
, 0);
8231 /* Nonzero if increment after copying. */
8232 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
8238 rtx real_in
= in
== value
? XEXP (in
, 0) : in
;
8240 /* No hard register is equivalent to this register after
8241 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
8242 we could inc/dec that register as well (maybe even using it for
8243 the source), but I'm not sure it's worth worrying about. */
8244 if (GET_CODE (incloc
) == REG
)
8245 reg_last_reload_reg
[REGNO (incloc
)] = 0;
8247 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
8248 inc_amount
= - inc_amount
;
8250 inc
= GEN_INT (inc_amount
);
8252 /* If this is post-increment, first copy the location to the reload reg. */
8253 if (post
&& real_in
!= reloadreg
)
8254 emit_insn (gen_move_insn (reloadreg
, real_in
));
8258 /* See if we can directly increment INCLOC. Use a method similar to
8259 that in gen_reload. */
8261 last
= get_last_insn ();
8262 add_insn
= emit_insn (gen_rtx_SET (VOIDmode
, incloc
,
8263 gen_rtx_PLUS (GET_MODE (incloc
),
8266 code
= recog_memoized (add_insn
);
8269 extract_insn (add_insn
);
8270 if (constrain_operands (1))
8272 /* If this is a pre-increment and we have incremented the value
8273 where it lives, copy the incremented value to RELOADREG to
8274 be used as an address. */
8277 emit_insn (gen_move_insn (reloadreg
, incloc
));
8282 delete_insns_since (last
);
8285 /* If couldn't do the increment directly, must increment in RELOADREG.
8286 The way we do this depends on whether this is pre- or post-increment.
8287 For pre-increment, copy INCLOC to the reload register, increment it
8288 there, then save back. */
8292 if (in
!= reloadreg
)
8293 emit_insn (gen_move_insn (reloadreg
, real_in
));
8294 emit_insn (gen_add2_insn (reloadreg
, inc
));
8295 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8300 Because this might be a jump insn or a compare, and because RELOADREG
8301 may not be available after the insn in an input reload, we must do
8302 the incrementation before the insn being reloaded for.
8304 We have already copied IN to RELOADREG. Increment the copy in
8305 RELOADREG, save that back, then decrement RELOADREG so it has
8306 the original value. */
8308 emit_insn (gen_add2_insn (reloadreg
, inc
));
8309 store
= emit_insn (gen_move_insn (incloc
, reloadreg
));
8310 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
8316 /* Return 1 if we are certain that the constraint-string STRING allows
8317 the hard register REG. Return 0 if we can't be sure of this. */
8320 constraint_accepts_reg_p (string
, reg
)
8325 int regno
= true_regnum (reg
);
8328 /* Initialize for first alternative. */
8330 /* Check that each alternative contains `g' or `r'. */
8332 switch (c
= *string
++)
8335 /* If an alternative lacks `g' or `r', we lose. */
8338 /* If an alternative lacks `g' or `r', we lose. */
8341 /* Initialize for next alternative. */
8346 /* Any general reg wins for this alternative. */
8347 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
8351 /* Any reg in specified class wins for this alternative. */
8353 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
8355 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
8361 /* Return the number of places FIND appears within X, but don't count
8362 an occurrence if some SET_DEST is FIND. */
8365 count_occurrences (x
, find
)
8366 register rtx x
, find
;
8369 register enum rtx_code code
;
8370 register char *format_ptr
;
8378 code
= GET_CODE (x
);
8393 if (GET_CODE (find
) == MEM
&& rtx_equal_p (x
, find
))
8397 if (SET_DEST (x
) == find
)
8398 return count_occurrences (SET_SRC (x
), find
);
8405 format_ptr
= GET_RTX_FORMAT (code
);
8408 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8410 switch (*format_ptr
++)
8413 count
+= count_occurrences (XEXP (x
, i
), find
);
8417 if (XVEC (x
, i
) != NULL
)
8419 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8420 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
);
8428 /* This array holds values which are equivalent to a hard register
8429 during reload_cse_regs. Each array element is an EXPR_LIST of
8430 values. Each time a hard register is set, we set the corresponding
8431 array element to the value. Each time a hard register is copied
8432 into memory, we add the memory location to the corresponding array
8433 element. We don't store values or memory addresses with side
8434 effects in this array.
8436 If the value is a CONST_INT, then the mode of the containing
8437 EXPR_LIST is the mode in which that CONST_INT was referenced.
8439 We sometimes clobber a specific entry in a list. In that case, we
8440 just set XEXP (list-entry, 0) to 0. */
8442 static rtx
*reg_values
;
8444 /* This is a preallocated REG rtx which we use as a temporary in
8445 reload_cse_invalidate_regno, so that we don't need to allocate a
8446 new one each time through a loop in that function. */
8448 static rtx invalidate_regno_rtx
;
8450 /* Invalidate any entries in reg_values which depend on REGNO,
8451 including those for REGNO itself. This is called if REGNO is
8452 changing. If CLOBBER is true, then always forget anything we
8453 currently know about REGNO. MODE is the mode of the assignment to
8454 REGNO, which is used to determine how many hard registers are being
8455 changed. If MODE is VOIDmode, then only REGNO is being changed;
8456 this is used when invalidating call clobbered registers across a
8460 reload_cse_invalidate_regno (regno
, mode
, clobber
)
8462 enum machine_mode mode
;
8468 /* Our callers don't always go through true_regnum; we may see a
8469 pseudo-register here from a CLOBBER or the like. We probably
8470 won't ever see a pseudo-register that has a real register number,
8471 for we check anyhow for safety. */
8472 if (regno
>= FIRST_PSEUDO_REGISTER
)
8473 regno
= reg_renumber
[regno
];
8477 if (mode
== VOIDmode
)
8478 endregno
= regno
+ 1;
8480 endregno
= regno
+ HARD_REGNO_NREGS (regno
, mode
);
8483 for (i
= regno
; i
< endregno
; i
++)
8486 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8490 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8492 if (XEXP (x
, 0) != 0
8493 && refers_to_regno_p (regno
, endregno
, XEXP (x
, 0), NULL_PTR
))
8495 /* If this is the only entry on the list, clear
8496 reg_values[i]. Otherwise, just clear this entry on
8498 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8508 /* We must look at earlier registers, in case REGNO is part of a
8509 multi word value but is not the first register. If an earlier
8510 register has a value in a mode which overlaps REGNO, then we must
8511 invalidate that earlier register. Note that we do not need to
8512 check REGNO or later registers (we must not check REGNO itself,
8513 because we would incorrectly conclude that there was a conflict). */
8515 for (i
= 0; i
< regno
; i
++)
8519 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8521 if (XEXP (x
, 0) != 0)
8523 PUT_MODE (invalidate_regno_rtx
, GET_MODE (x
));
8524 REGNO (invalidate_regno_rtx
) = i
;
8525 if (refers_to_regno_p (regno
, endregno
, invalidate_regno_rtx
,
8528 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8536 /* The memory at address MEM_BASE is being changed.
8537 Return whether this change will invalidate VAL. */
8540 reload_cse_mem_conflict_p (mem_base
, val
)
8548 code
= GET_CODE (val
);
8551 /* Get rid of a few simple cases quickly. */
8564 if (GET_MODE (mem_base
) == BLKmode
8565 || GET_MODE (val
) == BLKmode
)
8567 if (anti_dependence (val
, mem_base
))
8569 /* The address may contain nested MEMs. */
8576 fmt
= GET_RTX_FORMAT (code
);
8578 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8582 if (reload_cse_mem_conflict_p (mem_base
, XEXP (val
, i
)))
8585 else if (fmt
[i
] == 'E')
8589 for (j
= 0; j
< XVECLEN (val
, i
); j
++)
8590 if (reload_cse_mem_conflict_p (mem_base
, XVECEXP (val
, i
, j
)))
8598 /* Invalidate any entries in reg_values which are changed because of a
8599 store to MEM_RTX. If this is called because of a non-const call
8600 instruction, MEM_RTX is (mem:BLK const0_rtx). */
8603 reload_cse_invalidate_mem (mem_rtx
)
8608 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8612 for (x
= reg_values
[i
]; x
; x
= XEXP (x
, 1))
8614 if (XEXP (x
, 0) != 0
8615 && reload_cse_mem_conflict_p (mem_rtx
, XEXP (x
, 0)))
8617 /* If this is the only entry on the list, clear
8618 reg_values[i]. Otherwise, just clear this entry on
8620 if (XEXP (x
, 1) == 0 && x
== reg_values
[i
])
8631 /* Invalidate DEST, which is being assigned to or clobbered. The
8632 second parameter exists so that this function can be passed to
8633 note_stores; it is ignored. */
8636 reload_cse_invalidate_rtx (dest
, ignore
)
8638 rtx ignore ATTRIBUTE_UNUSED
;
8640 while (GET_CODE (dest
) == STRICT_LOW_PART
8641 || GET_CODE (dest
) == SIGN_EXTRACT
8642 || GET_CODE (dest
) == ZERO_EXTRACT
8643 || GET_CODE (dest
) == SUBREG
)
8644 dest
= XEXP (dest
, 0);
8646 if (GET_CODE (dest
) == REG
)
8647 reload_cse_invalidate_regno (REGNO (dest
), GET_MODE (dest
), 1);
8648 else if (GET_CODE (dest
) == MEM
)
8649 reload_cse_invalidate_mem (dest
);
8652 /* Do a very simple CSE pass over the hard registers.
8654 This function detects no-op moves where we happened to assign two
8655 different pseudo-registers to the same hard register, and then
8656 copied one to the other. Reload will generate a useless
8657 instruction copying a register to itself.
8659 This function also detects cases where we load a value from memory
8660 into two different registers, and (if memory is more expensive than
8661 registers) changes it to simply copy the first register into the
8664 Another optimization is performed that scans the operands of each
8665 instruction to see whether the value is already available in a
8666 hard register. It then replaces the operand with the hard register
8667 if possible, much like an optional reload would. */
8670 reload_cse_regs_1 (first
)
8678 init_alias_analysis ();
8680 reg_values
= (rtx
*) alloca (FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8681 bzero ((char *)reg_values
, FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
8683 /* Create our EXPR_LIST structures on reload_obstack, so that we can
8684 free them when we are done. */
8685 push_obstacks (&reload_obstack
, &reload_obstack
);
8686 firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
8688 /* We pass this to reload_cse_invalidate_mem to invalidate all of
8689 memory for a non-const call instruction. */
8690 callmem
= gen_rtx_MEM (BLKmode
, const0_rtx
);
8692 /* This is used in reload_cse_invalidate_regno to avoid consing a
8693 new REG in a loop in that function. */
8694 invalidate_regno_rtx
= gen_rtx_REG (VOIDmode
, 0);
8696 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
8700 if (GET_CODE (insn
) == CODE_LABEL
)
8702 /* Forget all the register values at a code label. We don't
8703 try to do anything clever around jumps. */
8704 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8710 #ifdef NON_SAVING_SETJMP
8711 if (NON_SAVING_SETJMP
&& GET_CODE (insn
) == NOTE
8712 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_SETJMP
)
8714 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8721 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
8724 /* If this is a call instruction, forget anything stored in a
8725 call clobbered register, or, if this is not a const call, in
8727 if (GET_CODE (insn
) == CALL_INSN
)
8729 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
8730 if (call_used_regs
[i
])
8731 reload_cse_invalidate_regno (i
, VOIDmode
, 1);
8733 if (! CONST_CALL_P (insn
))
8734 reload_cse_invalidate_mem (callmem
);
8737 body
= PATTERN (insn
);
8738 if (GET_CODE (body
) == SET
)
8741 if (reload_cse_noop_set_p (body
, insn
))
8743 /* If this sets the return value of the function, we must keep
8744 a USE around, in case this is in a different basic block
8745 than the final USE. Otherwise, we could loose important
8746 register lifeness information on SMALL_REGISTER_CLASSES
8747 machines, where return registers might be used as spills:
8748 subsequent passes assume that spill registers are dead at
8749 the end of a basic block. */
8750 if (REG_FUNCTION_VALUE_P (SET_DEST (body
)))
8753 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, SET_DEST (body
));
8754 INSN_CODE (insn
) = -1;
8755 REG_NOTES (insn
) = NULL_RTX
;
8756 push_obstacks (&reload_obstack
, &reload_obstack
);
8760 PUT_CODE (insn
, NOTE
);
8761 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8762 NOTE_SOURCE_FILE (insn
) = 0;
8765 /* We're done with this insn. */
8769 /* It's not a no-op, but we can try to simplify it. */
8770 count
+= reload_cse_simplify_set (body
, insn
);
8773 apply_change_group ();
8775 reload_cse_simplify_operands (insn
);
8777 reload_cse_record_set (body
, body
);
8779 else if (GET_CODE (body
) == PARALLEL
)
8782 rtx value
= NULL_RTX
;
8784 /* If every action in a PARALLEL is a noop, we can delete
8785 the entire PARALLEL. */
8786 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8788 rtx part
= XVECEXP (body
, 0, i
);
8789 if (GET_CODE (part
) == SET
)
8791 if (! reload_cse_noop_set_p (part
, insn
))
8793 if (REG_FUNCTION_VALUE_P (SET_DEST (part
)))
8797 value
= SET_DEST (part
);
8800 else if (GET_CODE (part
) != CLOBBER
)
8808 PATTERN (insn
) = gen_rtx_USE (VOIDmode
, value
);
8809 INSN_CODE (insn
) = -1;
8810 REG_NOTES (insn
) = NULL_RTX
;
8811 push_obstacks (&reload_obstack
, &reload_obstack
);
8815 PUT_CODE (insn
, NOTE
);
8816 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
8817 NOTE_SOURCE_FILE (insn
) = 0;
8820 /* We're done with this insn. */
8824 /* It's not a no-op, but we can try to simplify it. */
8825 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8826 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
8827 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
8830 apply_change_group ();
8832 reload_cse_simplify_operands (insn
);
8834 /* Look through the PARALLEL and record the values being
8835 set, if possible. Also handle any CLOBBERs. */
8836 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
8838 rtx x
= XVECEXP (body
, 0, i
);
8840 if (GET_CODE (x
) == SET
)
8841 reload_cse_record_set (x
, body
);
8843 note_stores (x
, reload_cse_invalidate_rtx
);
8847 note_stores (body
, reload_cse_invalidate_rtx
);
8850 /* Clobber any registers which appear in REG_INC notes. We
8851 could keep track of the changes to their values, but it is
8852 unlikely to help. */
8856 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
8857 if (REG_NOTE_KIND (x
) == REG_INC
)
8858 reload_cse_invalidate_rtx (XEXP (x
, 0), NULL_RTX
);
8862 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only
8863 after we have processed the insn. */
8864 if (GET_CODE (insn
) == CALL_INSN
)
8868 for (x
= CALL_INSN_FUNCTION_USAGE (insn
); x
; x
= XEXP (x
, 1))
8869 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
8870 reload_cse_invalidate_rtx (XEXP (XEXP (x
, 0), 0), NULL_RTX
);
8874 /* Free all the temporary structures we created, and go back to the
8875 regular obstacks. */
8876 obstack_free (&reload_obstack
, firstobj
);
8880 /* Call cse / combine like post-reload optimization phases.
8881 FIRST is the first instruction. */
8883 reload_cse_regs (first
)
8886 reload_cse_regs_1 (first
);
8888 reload_cse_move2add (first
);
8889 if (flag_expensive_optimizations
)
8890 reload_cse_regs_1 (first
);
8893 /* Return whether the values known for REGNO are equal to VAL. MODE
8894 is the mode of the object that VAL is being copied to; this matters
8895 if VAL is a CONST_INT. */
8898 reload_cse_regno_equal_p (regno
, val
, mode
)
8901 enum machine_mode mode
;
8908 for (x
= reg_values
[regno
]; x
; x
= XEXP (x
, 1))
8909 if (XEXP (x
, 0) != 0
8910 && rtx_equal_p (XEXP (x
, 0), val
)
8911 && (! flag_float_store
|| GET_CODE (XEXP (x
, 0)) != MEM
8912 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
8913 && (GET_CODE (val
) != CONST_INT
8914 || mode
== GET_MODE (x
)
8915 || (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8916 /* On a big endian machine if the value spans more than
8917 one register then this register holds the high part of
8918 it and we can't use it.
8920 ??? We should also compare with the high part of the
8922 && !(WORDS_BIG_ENDIAN
8923 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
8924 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
8925 GET_MODE_BITSIZE (GET_MODE (x
))))))
8931 /* See whether a single set is a noop. SET is the set instruction we
8932 are should check, and INSN is the instruction from which it came. */
8935 reload_cse_noop_set_p (set
, insn
)
8940 enum machine_mode dest_mode
;
8944 src
= SET_SRC (set
);
8945 dest
= SET_DEST (set
);
8946 dest_mode
= GET_MODE (dest
);
8948 if (side_effects_p (src
))
8951 dreg
= true_regnum (dest
);
8952 sreg
= true_regnum (src
);
8954 /* Check for setting a register to itself. In this case, we don't
8955 have to worry about REG_DEAD notes. */
8956 if (dreg
>= 0 && dreg
== sreg
)
8962 /* Check for setting a register to itself. */
8966 /* Check for setting a register to a value which we already know
8967 is in the register. */
8968 else if (reload_cse_regno_equal_p (dreg
, src
, dest_mode
))
8971 /* Check for setting a register DREG to another register SREG
8972 where SREG is equal to a value which is already in DREG. */
8977 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
8981 if (XEXP (x
, 0) == 0)
8984 if (dest_mode
== GET_MODE (x
))
8986 else if (GET_MODE_BITSIZE (dest_mode
)
8987 < GET_MODE_BITSIZE (GET_MODE (x
)))
8988 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
8993 && reload_cse_regno_equal_p (dreg
, tmp
, dest_mode
))
9001 else if (GET_CODE (dest
) == MEM
)
9003 /* Check for storing a register to memory when we know that the
9004 register is equivalent to the memory location. */
9006 && reload_cse_regno_equal_p (sreg
, dest
, dest_mode
)
9007 && ! side_effects_p (dest
))
9014 /* Try to simplify a single SET instruction. SET is the set pattern.
9015 INSN is the instruction it came from.
9016 This function only handles one case: if we set a register to a value
9017 which is not a register, we try to find that value in some other register
9018 and change the set into a register copy. */
9021 reload_cse_simplify_set (set
, insn
)
9027 enum machine_mode dest_mode
;
9028 enum reg_class dclass
;
9031 dreg
= true_regnum (SET_DEST (set
));
9035 src
= SET_SRC (set
);
9036 if (side_effects_p (src
) || true_regnum (src
) >= 0)
9039 dclass
= REGNO_REG_CLASS (dreg
);
9041 /* If memory loads are cheaper than register copies, don't change them. */
9042 if (GET_CODE (src
) == MEM
9043 && MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1) < 2)
9046 /* If the constant is cheaper than a register, don't change it. */
9047 if (CONSTANT_P (src
)
9048 && rtx_cost (src
, SET
) < 2)
9051 dest_mode
= GET_MODE (SET_DEST (set
));
9052 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
9055 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i
), dclass
) == 2
9056 && reload_cse_regno_equal_p (i
, src
, dest_mode
))
9060 /* Pop back to the real obstacks while changing the insn. */
9063 validated
= validate_change (insn
, &SET_SRC (set
),
9064 gen_rtx_REG (dest_mode
, i
), 1);
9066 /* Go back to the obstack we are using for temporary
9068 push_obstacks (&reload_obstack
, &reload_obstack
);
9077 /* Try to replace operands in INSN with equivalent values that are already
9078 in registers. This can be viewed as optional reloading.
9080 For each non-register operand in the insn, see if any hard regs are
9081 known to be equivalent to that operand. Record the alternatives which
9082 can accept these hard registers. Among all alternatives, select the
9083 ones which are better or equal to the one currently matching, where
9084 "better" is in terms of '?' and '!' constraints. Among the remaining
9085 alternatives, select the one which replaces most operands with
9089 reload_cse_simplify_operands (insn
)
9092 #ifdef REGISTER_CONSTRAINTS
9095 const char *constraints
[MAX_RECOG_OPERANDS
];
9097 /* Vector recording how bad an alternative is. */
9098 int *alternative_reject
;
9099 /* Vector recording how many registers can be introduced by choosing
9100 this alternative. */
9101 int *alternative_nregs
;
9102 /* Array of vectors recording, for each operand and each alternative,
9103 which hard register to substitute, or -1 if the operand should be
9105 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
9106 /* Array of alternatives, sorted in order of decreasing desirability. */
9107 int *alternative_order
;
9108 rtx reg
= gen_rtx_REG (VOIDmode
, -1);
9110 extract_insn (insn
);
9112 if (recog_n_alternatives
== 0 || recog_n_operands
== 0)
9115 /* Figure out which alternative currently matches. */
9116 if (! constrain_operands (1))
9117 fatal_insn_not_found (insn
);
9119 alternative_reject
= (int *) alloca (recog_n_alternatives
* sizeof (int));
9120 alternative_nregs
= (int *) alloca (recog_n_alternatives
* sizeof (int));
9121 alternative_order
= (int *) alloca (recog_n_alternatives
* sizeof (int));
9122 bzero ((char *)alternative_reject
, recog_n_alternatives
* sizeof (int));
9123 bzero ((char *)alternative_nregs
, recog_n_alternatives
* sizeof (int));
9125 for (i
= 0; i
< recog_n_operands
; i
++)
9127 enum machine_mode mode
;
9131 op_alt_regno
[i
] = (int *) alloca (recog_n_alternatives
* sizeof (int));
9132 for (j
= 0; j
< recog_n_alternatives
; j
++)
9133 op_alt_regno
[i
][j
] = -1;
9135 p
= constraints
[i
] = recog_constraints
[i
];
9136 mode
= recog_operand_mode
[i
];
9138 /* Add the reject values for each alternative given by the constraints
9139 for this operand. */
9147 alternative_reject
[j
] += 3;
9149 alternative_reject
[j
] += 300;
9152 /* We won't change operands which are already registers. We
9153 also don't want to modify output operands. */
9154 regno
= true_regnum (recog_operand
[i
]);
9156 || constraints
[i
][0] == '='
9157 || constraints
[i
][0] == '+')
9160 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
9162 int class = (int) NO_REGS
;
9164 if (! reload_cse_regno_equal_p (regno
, recog_operand
[i
], mode
))
9167 REGNO (reg
) = regno
;
9168 PUT_MODE (reg
, mode
);
9170 /* We found a register equal to this operand. Now look for all
9171 alternatives that can accept this register and have not been
9172 assigned a register they can use yet. */
9181 case '=': case '+': case '?':
9182 case '#': case '&': case '!':
9184 case '0': case '1': case '2': case '3': case '4':
9185 case 'm': case '<': case '>': case 'V': case 'o':
9186 case 'E': case 'F': case 'G': case 'H':
9187 case 's': case 'i': case 'n':
9188 case 'I': case 'J': case 'K': case 'L':
9189 case 'M': case 'N': case 'O': case 'P':
9190 #ifdef EXTRA_CONSTRAINT
9191 case 'Q': case 'R': case 'S': case 'T': case 'U':
9194 /* These don't say anything we care about. */
9198 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
9203 = reg_class_subunion
[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
9206 case ',': case '\0':
9207 /* See if REGNO fits this alternative, and set it up as the
9208 replacement register if we don't have one for this
9209 alternative yet and the operand being replaced is not
9210 a cheap CONST_INT. */
9211 if (op_alt_regno
[i
][j
] == -1
9212 && reg_fits_class_p (reg
, class, 0, mode
)
9213 && (GET_CODE (recog_operand
[i
]) != CONST_INT
9214 || rtx_cost (recog_operand
[i
], SET
) > rtx_cost (reg
, SET
)))
9216 alternative_nregs
[j
]++;
9217 op_alt_regno
[i
][j
] = regno
;
9229 /* Record all alternatives which are better or equal to the currently
9230 matching one in the alternative_order array. */
9231 for (i
= j
= 0; i
< recog_n_alternatives
; i
++)
9232 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
9233 alternative_order
[j
++] = i
;
9234 recog_n_alternatives
= j
;
9236 /* Sort it. Given a small number of alternatives, a dumb algorithm
9237 won't hurt too much. */
9238 for (i
= 0; i
< recog_n_alternatives
- 1; i
++)
9241 int best_reject
= alternative_reject
[alternative_order
[i
]];
9242 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
9245 for (j
= i
+ 1; j
< recog_n_alternatives
; j
++)
9247 int this_reject
= alternative_reject
[alternative_order
[j
]];
9248 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
9250 if (this_reject
< best_reject
9251 || (this_reject
== best_reject
&& this_nregs
< best_nregs
))
9254 best_reject
= this_reject
;
9255 best_nregs
= this_nregs
;
9259 tmp
= alternative_order
[best
];
9260 alternative_order
[best
] = alternative_order
[i
];
9261 alternative_order
[i
] = tmp
;
9264 /* Substitute the operands as determined by op_alt_regno for the best
9266 j
= alternative_order
[0];
9268 /* Pop back to the real obstacks while changing the insn. */
9271 for (i
= 0; i
< recog_n_operands
; i
++)
9273 enum machine_mode mode
= recog_operand_mode
[i
];
9274 if (op_alt_regno
[i
][j
] == -1)
9277 validate_change (insn
, recog_operand_loc
[i
],
9278 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
9281 for (i
= recog_n_dups
- 1; i
>= 0; i
--)
9283 int op
= recog_dup_num
[i
];
9284 enum machine_mode mode
= recog_operand_mode
[op
];
9286 if (op_alt_regno
[op
][j
] == -1)
9289 validate_change (insn
, recog_dup_loc
[i
],
9290 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
9293 /* Go back to the obstack we are using for temporary
9295 push_obstacks (&reload_obstack
, &reload_obstack
);
9297 return apply_change_group ();
9303 /* These two variables are used to pass information from
9304 reload_cse_record_set to reload_cse_check_clobber. */
9306 static int reload_cse_check_clobbered
;
9307 static rtx reload_cse_check_src
;
9309 /* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set
9310 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The
9311 second argument, which is passed by note_stores, is ignored. */
9314 reload_cse_check_clobber (dest
, ignore
)
9316 rtx ignore ATTRIBUTE_UNUSED
;
9318 if (reg_overlap_mentioned_p (dest
, reload_cse_check_src
))
9319 reload_cse_check_clobbered
= 1;
9322 /* Record the result of a SET instruction. SET is the set pattern.
9323 BODY is the pattern of the insn that it came from. */
9326 reload_cse_record_set (set
, body
)
9332 enum machine_mode dest_mode
;
9334 dest
= SET_DEST (set
);
9335 src
= SET_SRC (set
);
9336 dreg
= true_regnum (dest
);
9337 sreg
= true_regnum (src
);
9338 dest_mode
= GET_MODE (dest
);
9340 /* Some machines don't define AUTO_INC_DEC, but they still use push
9341 instructions. We need to catch that case here in order to
9342 invalidate the stack pointer correctly. Note that invalidating
9343 the stack pointer is different from invalidating DEST. */
9345 while (GET_CODE (x
) == SUBREG
9346 || GET_CODE (x
) == ZERO_EXTRACT
9347 || GET_CODE (x
) == SIGN_EXTRACT
9348 || GET_CODE (x
) == STRICT_LOW_PART
)
9350 if (push_operand (x
, GET_MODE (x
)))
9352 reload_cse_invalidate_rtx (stack_pointer_rtx
, NULL_RTX
);
9353 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9357 /* We can only handle an assignment to a register, or a store of a
9358 register to a memory location. For other cases, we just clobber
9359 the destination. We also have to just clobber if there are side
9360 effects in SRC or DEST. */
9361 if ((dreg
< 0 && GET_CODE (dest
) != MEM
)
9362 || side_effects_p (src
)
9363 || side_effects_p (dest
))
9365 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9370 /* We don't try to handle values involving CC, because it's a pain
9371 to keep track of when they have to be invalidated. */
9372 if (reg_mentioned_p (cc0_rtx
, src
)
9373 || reg_mentioned_p (cc0_rtx
, dest
))
9375 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9380 /* If BODY is a PARALLEL, then we need to see whether the source of
9381 SET is clobbered by some other instruction in the PARALLEL. */
9382 if (GET_CODE (body
) == PARALLEL
)
9386 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
9390 x
= XVECEXP (body
, 0, i
);
9394 reload_cse_check_clobbered
= 0;
9395 reload_cse_check_src
= src
;
9396 note_stores (x
, reload_cse_check_clobber
);
9397 if (reload_cse_check_clobbered
)
9399 reload_cse_invalidate_rtx (dest
, NULL_RTX
);
9409 /* This is an assignment to a register. Update the value we
9410 have stored for the register. */
9415 /* This is a copy from one register to another. Any values
9416 which were valid for SREG are now valid for DREG. If the
9417 mode changes, we use gen_lowpart_common to extract only
9418 the part of the value that is copied. */
9419 reg_values
[dreg
] = 0;
9420 for (x
= reg_values
[sreg
]; x
; x
= XEXP (x
, 1))
9424 if (XEXP (x
, 0) == 0)
9426 if (dest_mode
== GET_MODE (XEXP (x
, 0)))
9428 else if (GET_MODE_BITSIZE (dest_mode
)
9429 > GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
9432 tmp
= gen_lowpart_common (dest_mode
, XEXP (x
, 0));
9434 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, tmp
,
9439 reg_values
[dreg
] = gen_rtx_EXPR_LIST (dest_mode
, src
, NULL_RTX
);
9441 /* We've changed DREG, so invalidate any values held by other
9442 registers that depend upon it. */
9443 reload_cse_invalidate_regno (dreg
, dest_mode
, 0);
9445 /* If this assignment changes more than one hard register,
9446 forget anything we know about the others. */
9447 for (i
= 1; i
< HARD_REGNO_NREGS (dreg
, dest_mode
); i
++)
9448 reg_values
[dreg
+ i
] = 0;
9450 else if (GET_CODE (dest
) == MEM
)
9452 /* Invalidate conflicting memory locations. */
9453 reload_cse_invalidate_mem (dest
);
9455 /* If we're storing a register to memory, add DEST to the list
9457 if (sreg
>= 0 && ! side_effects_p (dest
))
9458 reg_values
[sreg
] = gen_rtx_EXPR_LIST (dest_mode
, dest
,
9463 /* We should have bailed out earlier. */
9468 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
9470 This code might also be useful when reload gave up on reg+reg addresssing
9471 because of clashes between the return register and INDEX_REG_CLASS. */
9473 /* The maximum number of uses of a register we can keep track of to
9474 replace them with reg+reg addressing. */
9475 #define RELOAD_COMBINE_MAX_USES 6
9477 /* INSN is the insn where a register has ben used, and USEP points to the
9478 location of the register within the rtl. */
9479 struct reg_use
{ rtx insn
, *usep
; };
9481 /* If the register is used in some unknown fashion, USE_INDEX is negative.
9482 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
9483 indicates where it becomes live again.
9484 Otherwise, USE_INDEX is the index of the last encountered use of the
9485 register (which is first among these we have seen since we scan backwards),
9486 OFFSET contains the constant offset that is added to the register in
9487 all encountered uses, and USE_RUID indicates the first encountered, i.e.
9488 last, of these uses.
9489 STORE_RUID is always meaningful if we only want to use a value in a
9490 register in a different place: it denotes the next insn in the insn
9491 stream (i.e. the last ecountered) that sets or clobbers the register. */
9494 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
9499 } reg_state
[FIRST_PSEUDO_REGISTER
];
9501 /* Reverse linear uid. This is increased in reload_combine while scanning
9502 the instructions from last to first. It is used to set last_label_ruid
9503 and the store_ruid / use_ruid fields in reg_state. */
9504 static int reload_combine_ruid
;
9506 #define LABEL_LIVE(LABEL) \
9507 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
9513 int first_index_reg
= 1, last_index_reg
= 0;
9515 int last_label_ruid
;
9516 int min_labelno
, n_labels
;
9517 HARD_REG_SET ever_live_at_start
, *label_live
;
9519 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
9520 reload has already used it where appropriate, so there is no use in
9521 trying to generate it now. */
9522 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
9525 /* To avoid wasting too much time later searching for an index register,
9526 determine the minimum and maximum index register numbers. */
9527 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9529 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
))
9531 if (! last_index_reg
)
9533 first_index_reg
= i
;
9536 /* If no index register is available, we can quit now. */
9537 if (first_index_reg
> last_index_reg
)
9540 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
9541 information is a bit fuzzy immediately after reload, but it's
9542 still good enough to determine which registers are live at a jump
9544 min_labelno
= get_first_label_num ();
9545 n_labels
= max_label_num () - min_labelno
;
9546 label_live
= (HARD_REG_SET
*) xmalloc (n_labels
* sizeof (HARD_REG_SET
));
9547 CLEAR_HARD_REG_SET (ever_live_at_start
);
9548 for (i
= n_basic_blocks
- 1; i
>= 0; i
--)
9550 insn
= BLOCK_HEAD (i
);
9551 if (GET_CODE (insn
) == CODE_LABEL
)
9555 REG_SET_TO_HARD_REG_SET (live
, BASIC_BLOCK (i
)->global_live_at_start
);
9556 compute_use_by_pseudos (&live
, BASIC_BLOCK (i
)->global_live_at_start
);
9557 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
9558 IOR_HARD_REG_SET (ever_live_at_start
, live
);
9562 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
9563 last_label_ruid
= reload_combine_ruid
= 0;
9564 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9566 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9568 reg_state
[i
].use_index
= -1;
9570 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9573 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
9577 /* We cannot do our optimization across labels. Invalidating all the use
9578 information we have would be costly, so we just note where the label
9579 is and then later disable any optimization that would cross it. */
9580 if (GET_CODE (insn
) == CODE_LABEL
)
9581 last_label_ruid
= reload_combine_ruid
;
9582 if (GET_CODE (insn
) == BARRIER
)
9584 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9585 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9587 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
9589 reload_combine_ruid
++;
9591 /* Look for (set (REGX) (CONST_INT))
9592 (set (REGX) (PLUS (REGX) (REGY)))
9594 ... (MEM (REGX)) ...
9596 (set (REGZ) (CONST_INT))
9598 ... (MEM (PLUS (REGZ) (REGY)))... .
9600 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
9601 and that we know all uses of REGX before it dies. */
9602 set
= single_set (insn
);
9604 && GET_CODE (SET_DEST (set
)) == REG
9605 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set
)),
9606 GET_MODE (SET_DEST (set
)))
9608 && GET_CODE (SET_SRC (set
)) == PLUS
9609 && GET_CODE (XEXP (SET_SRC (set
), 1)) == REG
9610 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
9611 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
9613 rtx reg
= SET_DEST (set
);
9614 rtx plus
= SET_SRC (set
);
9615 rtx base
= XEXP (plus
, 1);
9616 rtx prev
= prev_nonnote_insn (insn
);
9617 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
9618 int regno
= REGNO (reg
);
9620 rtx reg_sum
= NULL_RTX
;
9622 /* Now, we need an index register.
9623 We'll set index_reg to this index register, const_reg to the
9624 register that is to be loaded with the constant
9625 (denoted as REGZ in the substitution illustration above),
9626 and reg_sum to the register-register that we want to use to
9627 substitute uses of REG (typically in MEMs) with.
9628 First check REG and BASE for being index registers;
9629 we can use them even if they are not dead. */
9630 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
9631 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
9639 /* Otherwise, look for a free index register. Since we have
9640 checked above that neiter REG nor BASE are index registers,
9641 if we find anything at all, it will be different from these
9643 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
9645 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
9646 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
9647 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
9648 && HARD_REGNO_NREGS (i
, GET_MODE (reg
)) == 1)
9650 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
9651 const_reg
= index_reg
;
9652 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
9657 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
9658 (REGY), i.e. BASE, is not clobbered before the last use we'll
9661 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
9662 && rtx_equal_p (SET_DEST (prev_set
), reg
)
9663 && reg_state
[regno
].use_index
>= 0
9664 && reg_state
[REGNO (base
)].store_ruid
<= reg_state
[regno
].use_ruid
9669 /* Change destination register and - if necessary - the
9670 constant value in PREV, the constant loading instruction. */
9671 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
9672 if (reg_state
[regno
].offset
!= const0_rtx
)
9673 validate_change (prev
,
9674 &SET_SRC (prev_set
),
9675 GEN_INT (INTVAL (SET_SRC (prev_set
))
9676 + INTVAL (reg_state
[regno
].offset
)),
9678 /* Now for every use of REG that we have recorded, replace REG
9680 for (i
= reg_state
[regno
].use_index
;
9681 i
< RELOAD_COMBINE_MAX_USES
; i
++)
9682 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
9683 reg_state
[regno
].reg_use
[i
].usep
,
9686 if (apply_change_group ())
9690 /* Delete the reg-reg addition. */
9691 PUT_CODE (insn
, NOTE
);
9692 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
9693 NOTE_SOURCE_FILE (insn
) = 0;
9695 if (reg_state
[regno
].offset
!= const0_rtx
)
9697 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
9699 for (np
= ®_NOTES (prev
); *np
; )
9701 if (REG_NOTE_KIND (*np
) == REG_EQUAL
9702 || REG_NOTE_KIND (*np
) == REG_EQUIV
)
9703 *np
= XEXP (*np
, 1);
9705 np
= &XEXP (*np
, 1);
9708 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
9709 reg_state
[REGNO (const_reg
)].store_ruid
= reload_combine_ruid
;
9714 note_stores (PATTERN (insn
), reload_combine_note_store
);
9715 if (GET_CODE (insn
) == CALL_INSN
)
9719 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9721 if (call_used_regs
[i
])
9723 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9724 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9727 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
9728 link
= XEXP (link
, 1))
9730 rtx use
= XEXP (link
, 0);
9731 int regno
= REGNO (XEXP (use
, 0));
9732 if (GET_CODE (use
) == CLOBBER
)
9734 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
9735 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
9738 reg_state
[regno
].use_index
= -1;
9741 if (GET_CODE (insn
) == JUMP_INSN
&& GET_CODE (PATTERN (insn
)) != RETURN
)
9743 /* Non-spill registers might be used at the call destination in
9744 some unknown fashion, so we have to mark the unknown use. */
9746 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
9747 && JUMP_LABEL (insn
))
9748 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
9750 live
= &ever_live_at_start
;
9751 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
9753 if (TEST_HARD_REG_BIT (*live
, i
))
9754 reg_state
[i
].use_index
= -1;
9757 reload_combine_note_use (&PATTERN (insn
), insn
);
9758 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
9760 if (REG_NOTE_KIND (note
) == REG_INC
9761 && GET_CODE (XEXP (note
, 0)) == REG
)
9763 int regno
= REGNO (XEXP (note
, 0));
9765 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
9766 reg_state
[regno
].use_index
= -1;
9773 /* Check if DST is a register or a subreg of a register; if it is,
9774 update reg_state[regno].store_ruid and reg_state[regno].use_index
9775 accordingly. Called via note_stores from reload_combine. */
9777 reload_combine_note_store (dst
, set
)
9782 unsigned size
= GET_MODE_SIZE (GET_MODE (dst
));
9784 if (GET_CODE (dst
) == SUBREG
)
9786 regno
= SUBREG_WORD (dst
);
9787 dst
= SUBREG_REG (dst
);
9789 if (GET_CODE (dst
) != REG
)
9791 regno
+= REGNO (dst
);
9793 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
9794 careful with registers / register parts that are not full words.
9796 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
9797 if (GET_CODE (set
) != SET
9798 || GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
9799 || GET_CODE (SET_DEST (set
)) == SIGN_EXTRACT
9800 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
9802 for (i
= (size
- 1) / UNITS_PER_WORD
+ regno
; i
>= regno
; i
--)
9804 reg_state
[i
].use_index
= -1;
9805 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9810 for (i
= (size
- 1) / UNITS_PER_WORD
+ regno
; i
>= regno
; i
--)
9812 reg_state
[i
].store_ruid
= reload_combine_ruid
;
9813 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
9818 /* XP points to a piece of rtl that has to be checked for any uses of
9820 *XP is the pattern of INSN, or a part of it.
9821 Called from reload_combine, and recursively by itself. */
9823 reload_combine_note_use (xp
, insn
)
9827 enum rtx_code code
= x
->code
;
9830 rtx offset
= const0_rtx
; /* For the REG case below. */
9835 if (GET_CODE (SET_DEST (x
)) == REG
)
9837 reload_combine_note_use (&SET_SRC (x
), insn
);
9843 if (GET_CODE (SET_DEST (x
)) == REG
)
9848 /* We are interested in (plus (reg) (const_int)) . */
9849 if (GET_CODE (XEXP (x
, 0)) != REG
|| GET_CODE (XEXP (x
, 1)) != CONST_INT
)
9851 offset
= XEXP (x
, 1);
9856 int regno
= REGNO (x
);
9859 /* Some spurious USEs of pseudo registers might remain.
9860 Just ignore them. */
9861 if (regno
>= FIRST_PSEUDO_REGISTER
)
9864 /* If this register is already used in some unknown fashion, we
9866 If we decrement the index from zero to -1, we can't store more
9867 uses, so this register becomes used in an unknown fashion. */
9868 use_index
= --reg_state
[regno
].use_index
;
9872 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
9874 /* We have found another use for a register that is already
9875 used later. Check if the offsets match; if not, mark the
9876 register as used in an unknown fashion. */
9877 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
9879 reg_state
[regno
].use_index
= -1;
9885 /* This is the first use of this register we have seen since we
9886 marked it as dead. */
9887 reg_state
[regno
].offset
= offset
;
9888 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
9890 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
9891 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
9899 /* Recursively process the components of X. */
9900 fmt
= GET_RTX_FORMAT (code
);
9901 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9904 reload_combine_note_use (&XEXP (x
, i
), insn
);
9905 else if (fmt
[i
] == 'E')
9907 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9908 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
9913 /* See if we can reduce the cost of a constant by replacing a move with
9915 /* We cannot do our optimization across labels. Invalidating all the
9916 information about register contents we have would be costly, so we
9917 use last_label_luid (local variable of reload_cse_move2add) to note
9918 where the label is and then later disable any optimization that would
9920 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9921 reg_set_luid[n] is larger than last_label_luid[n] . */
9922 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
9923 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
9924 reg_mode[n] to be valid.
9925 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
9926 has been set to reg_offset[n] in mode reg_mode[n] .
9927 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
9928 register n has been set to the sum of reg_offset[n] and register
9929 reg_base_reg[n], calculated in mode reg_mode[n] . */
9930 static rtx reg_offset
[FIRST_PSEUDO_REGISTER
];
9931 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
9932 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
9933 /* move2add_luid is linearily increased while scanning the instructions
9934 from first to last. It is used to set reg_set_luid in
9935 reload_cse_move2add and move2add_note_store. */
9936 static int move2add_luid
;
9939 reload_cse_move2add (first
)
9944 int last_label_luid
;
9946 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
9947 reg_set_luid
[i
] = 0;
9949 last_label_luid
= 0;
9951 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
9955 if (GET_CODE (insn
) == CODE_LABEL
)
9956 last_label_luid
= move2add_luid
;
9957 if (GET_RTX_CLASS (GET_CODE (insn
)) != 'i')
9959 pat
= PATTERN (insn
);
9960 /* For simplicity, we only perform this optimization on
9961 straightforward SETs. */
9962 if (GET_CODE (pat
) == SET
9963 && GET_CODE (SET_DEST (pat
)) == REG
)
9965 rtx reg
= SET_DEST (pat
);
9966 int regno
= REGNO (reg
);
9967 rtx src
= SET_SRC (pat
);
9969 /* Check if we have valid information on the contents of this
9970 register in the mode of REG. */
9971 /* ??? We don't know how zero / sign extension is handled, hence
9972 we can't go from a narrower to a wider mode. */
9973 if (reg_set_luid
[regno
] > last_label_luid
9974 && (GET_MODE_SIZE (GET_MODE (reg
))
9975 <= GET_MODE_SIZE (reg_mode
[regno
]))
9976 && GET_CODE (reg_offset
[regno
]) == CONST_INT
)
9978 /* Try to transform (set (REGX) (CONST_INT A))
9980 (set (REGX) (CONST_INT B))
9982 (set (REGX) (CONST_INT A))
9984 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9986 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
9989 rtx new_src
= GEN_INT (INTVAL (src
)
9990 - INTVAL (reg_offset
[regno
]));
9991 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9992 use (set (reg) (reg)) instead.
9993 We don't delete this insn, nor do we convert it into a
9994 note, to avoid losing register notes or the return
9995 value flag. jump2 already knowns how to get rid of
9997 if (new_src
== const0_rtx
)
9998 success
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
9999 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
10000 && have_add2_insn (GET_MODE (reg
)))
10001 success
= validate_change (insn
, &PATTERN (insn
),
10002 gen_add2_insn (reg
, new_src
), 0);
10003 reg_set_luid
[regno
] = move2add_luid
;
10004 reg_mode
[regno
] = GET_MODE (reg
);
10005 reg_offset
[regno
] = src
;
10009 /* Try to transform (set (REGX) (REGY))
10010 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10012 (set (REGX) (REGY))
10013 (set (REGX) (PLUS (REGX) (CONST_INT B)))
10016 (set (REGX) (PLUS (REGX) (CONST_INT A)))
10018 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
10019 else if (GET_CODE (src
) == REG
10020 && reg_base_reg
[regno
] == REGNO (src
)
10021 && reg_set_luid
[regno
] > reg_set_luid
[REGNO (src
)])
10023 rtx next
= next_nonnote_insn (insn
);
10026 set
= single_set (next
);
10029 && SET_DEST (set
) == reg
10030 && GET_CODE (SET_SRC (set
)) == PLUS
10031 && XEXP (SET_SRC (set
), 0) == reg
10032 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
10034 rtx src3
= XEXP (SET_SRC (set
), 1);
10035 rtx new_src
= GEN_INT (INTVAL (src3
)
10036 - INTVAL (reg_offset
[regno
]));
10039 if (new_src
== const0_rtx
)
10040 /* See above why we create (set (reg) (reg)) here. */
10042 = validate_change (next
, &SET_SRC (set
), reg
, 0);
10043 else if ((rtx_cost (new_src
, PLUS
)
10044 < 2 + rtx_cost (src3
, SET
))
10045 && have_add2_insn (GET_MODE (reg
)))
10047 = validate_change (next
, &PATTERN (next
),
10048 gen_add2_insn (reg
, new_src
), 0);
10051 /* INSN might be the first insn in a basic block
10052 if the preceding insn is a conditional jump
10053 or a possible-throwing call. */
10054 PUT_CODE (insn
, NOTE
);
10055 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
10056 NOTE_SOURCE_FILE (insn
) = 0;
10059 reg_set_luid
[regno
] = move2add_luid
;
10060 reg_mode
[regno
] = GET_MODE (reg
);
10061 reg_offset
[regno
] = src3
;
10068 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
10070 if (REG_NOTE_KIND (note
) == REG_INC
10071 && GET_CODE (XEXP (note
, 0)) == REG
)
10073 /* Indicate that this register has been recently written to,
10074 but the exact contents are not available. */
10075 int regno
= REGNO (XEXP (note
, 0));
10076 if (regno
< FIRST_PSEUDO_REGISTER
)
10078 reg_set_luid
[regno
] = move2add_luid
;
10079 reg_offset
[regno
] = note
;
10083 note_stores (PATTERN (insn
), move2add_note_store
);
10084 /* If this is a CALL_INSN, all call used registers are stored with
10086 if (GET_CODE (insn
) == CALL_INSN
)
10088 for (i
= FIRST_PSEUDO_REGISTER
-1; i
>= 0; i
--)
10090 if (call_used_regs
[i
])
10092 reg_set_luid
[i
] = move2add_luid
;
10093 reg_offset
[i
] = insn
; /* Invalidate contents. */
10100 /* SET is a SET or CLOBBER that sets DST.
10101 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
10102 Called from reload_cse_move2add via note_stores. */
10104 move2add_note_store (dst
, set
)
10110 enum machine_mode mode
= GET_MODE (dst
);
10111 if (GET_CODE (dst
) == SUBREG
)
10113 regno
= SUBREG_WORD (dst
);
10114 dst
= SUBREG_REG (dst
);
10116 if (GET_CODE (dst
) != REG
)
10119 regno
+= REGNO (dst
);
10121 if (HARD_REGNO_NREGS (regno
, mode
) == 1 && GET_CODE (set
) == SET
10122 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
10123 && GET_CODE (SET_DEST (set
)) != SIGN_EXTRACT
10124 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
10126 rtx src
= SET_SRC (set
);
10128 reg_mode
[regno
] = mode
;
10129 switch (GET_CODE (src
))
10133 rtx src0
= XEXP (src
, 0);
10134 if (GET_CODE (src0
) == REG
)
10136 if (REGNO (src0
) != regno
10137 || reg_offset
[regno
] != const0_rtx
)
10139 reg_base_reg
[regno
] = REGNO (src0
);
10140 reg_set_luid
[regno
] = move2add_luid
;
10142 reg_offset
[regno
] = XEXP (src
, 1);
10145 reg_set_luid
[regno
] = move2add_luid
;
10146 reg_offset
[regno
] = set
; /* Invalidate contents. */
10151 reg_base_reg
[regno
] = REGNO (SET_SRC (set
));
10152 reg_offset
[regno
] = const0_rtx
;
10153 reg_set_luid
[regno
] = move2add_luid
;
10157 reg_base_reg
[regno
] = -1;
10158 reg_offset
[regno
] = SET_SRC (set
);
10159 reg_set_luid
[regno
] = move2add_luid
;
10165 for (i
= regno
+ HARD_REGNO_NREGS (regno
, mode
) - 1; i
>= regno
; i
--)
10167 /* Indicate that this register has been recently written to,
10168 but the exact contents are not available. */
10169 reg_set_luid
[i
] = move2add_luid
;
10170 reg_offset
[i
] = dst
;
10175 #ifdef AUTO_INC_DEC
10177 add_auto_inc_notes (insn
, x
)
10181 enum rtx_code code
= GET_CODE (x
);
10185 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
10188 = gen_rtx_EXPR_LIST (REG_INC
, XEXP (XEXP (x
, 0), 0), REG_NOTES (insn
));
10192 /* Scan all the operand sub-expressions. */
10193 fmt
= GET_RTX_FORMAT (code
);
10194 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10197 add_auto_inc_notes (insn
, XEXP (x
, i
));
10198 else if (fmt
[i
] == 'E')
10199 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
10200 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));