1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25 #include "insn-config.h"
26 #include "insn-flags.h"
27 #include "insn-codes.h"
31 #include "hard-reg-set.h"
34 #include "basic-block.h"
37 /* This file contains the reload pass of the compiler, which is
38 run after register allocation has been done. It checks that
39 each insn is valid (operands required to be in registers really
40 are in registers of the proper class) and fixes up invalid ones
41 by copying values temporarily into registers for the insns
44 The results of register allocation are described by the vector
45 reg_renumber; the insns still contain pseudo regs, but reg_renumber
46 can be used to find which hard reg, if any, a pseudo reg is in.
48 The technique we always use is to free up a few hard regs that are
49 called ``reload regs'', and for each place where a pseudo reg
50 must be in a hard reg, copy it temporarily into one of the reload regs.
52 All the pseudos that were formerly allocated to the hard regs that
53 are now in use as reload regs must be ``spilled''. This means
54 that they go to other hard regs, or to stack slots if no other
55 available hard regs can be found. Spilling can invalidate more
56 insns, requiring additional need for reloads, so we must keep checking
57 until the process stabilizes.
59 For machines with different classes of registers, we must keep track
60 of the register class needed for each reload, and make sure that
61 we allocate enough reload registers of each class.
63 The file reload.c contains the code that checks one insn for
64 validity and reports the reloads that it needs. This file
65 is in charge of scanning the entire rtl code, accumulating the
66 reload needs, spilling, assigning reload registers to use for
67 fixing up each insn, and generating the new insns to copy values
68 into the reload registers. */
71 #ifndef REGISTER_MOVE_COST
72 #define REGISTER_MOVE_COST(x, y) 2
75 #ifndef MEMORY_MOVE_COST
76 #define MEMORY_MOVE_COST(x) 4
79 /* During reload_as_needed, element N contains a REG rtx for the hard reg
80 into which reg N has been reloaded (perhaps for a previous insn). */
81 static rtx
*reg_last_reload_reg
;
83 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
84 for an output reload that stores into reg N. */
85 static char *reg_has_output_reload
;
87 /* Indicates which hard regs are reload-registers for an output reload
88 in the current insn. */
89 static HARD_REG_SET reg_is_output_reload
;
91 /* Element N is the constant value to which pseudo reg N is equivalent,
92 or zero if pseudo reg N is not equivalent to a constant.
93 find_reloads looks at this in order to replace pseudo reg N
94 with the constant it stands for. */
95 rtx
*reg_equiv_constant
;
97 /* Element N is a memory location to which pseudo reg N is equivalent,
98 prior to any register elimination (such as frame pointer to stack
99 pointer). Depending on whether or not it is a valid address, this value
100 is transferred to either reg_equiv_address or reg_equiv_mem. */
101 rtx
*reg_equiv_memory_loc
;
103 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
104 This is used when the address is not valid as a memory address
105 (because its displacement is too big for the machine.) */
106 rtx
*reg_equiv_address
;
108 /* Element N is the memory slot to which pseudo reg N is equivalent,
109 or zero if pseudo reg N is not equivalent to a memory slot. */
112 /* Widest width in which each pseudo reg is referred to (via subreg). */
113 static int *reg_max_ref_width
;
115 /* Element N is the insn that initialized reg N from its equivalent
116 constant or memory slot. */
117 static rtx
*reg_equiv_init
;
119 /* During reload_as_needed, element N contains the last pseudo regno
120 reloaded into the Nth reload register. This vector is in parallel
121 with spill_regs. If that pseudo reg occupied more than one register,
122 reg_reloaded_contents points to that pseudo for each spill register in
123 use; all of these must remain set for an inheritance to occur. */
124 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
126 /* During reload_as_needed, element N contains the insn for which
127 the Nth reload register was last used. This vector is in parallel
128 with spill_regs, and its contents are significant only when
129 reg_reloaded_contents is significant. */
130 static rtx reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
132 /* Number of spill-regs so far; number of valid elements of spill_regs. */
135 /* In parallel with spill_regs, contains REG rtx's for those regs.
136 Holds the last rtx used for any given reg, or 0 if it has never
137 been used for spilling yet. This rtx is reused, provided it has
139 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
141 /* In parallel with spill_regs, contains nonzero for a spill reg
142 that was stored after the last time it was used.
143 The precise value is the insn generated to do the store. */
144 static rtx spill_reg_store
[FIRST_PSEUDO_REGISTER
];
146 /* This table is the inverse mapping of spill_regs:
147 indexed by hard reg number,
148 it contains the position of that reg in spill_regs,
149 or -1 for something that is not in spill_regs. */
150 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
152 /* This reg set indicates registers that may not be used for retrying global
153 allocation. The registers that may not be used include all spill registers
154 and the frame pointer (if we are using one). */
155 HARD_REG_SET forbidden_regs
;
157 /* This reg set indicates registers that are not good for spill registers.
158 They will not be used to complete groups of spill registers. This includes
159 all fixed registers, registers that may be eliminated, and, if
160 SMALL_REGISTER_CLASSES is not defined, registers explicitly used in the rtl.
162 (spill_reg_order prevents these registers from being used to start a
164 static HARD_REG_SET bad_spill_regs
;
166 /* Describes order of use of registers for reloading
167 of spilled pseudo-registers. `spills' is the number of
168 elements that are actually valid; new ones are added at the end. */
169 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
171 /* Describes order of preference for putting regs into spill_regs.
172 Contains the numbers of all the hard regs, in order most preferred first.
173 This order is different for each function.
174 It is set up by order_regs_for_reload.
175 Empty elements at the end contain -1. */
176 static short potential_reload_regs
[FIRST_PSEUDO_REGISTER
];
178 /* 1 for a hard register that appears explicitly in the rtl
179 (for example, function value registers, special registers
180 used by insns, structure value pointer registers). */
181 static char regs_explicitly_used
[FIRST_PSEUDO_REGISTER
];
183 /* Indicates if a register was counted against the need for
184 groups. 0 means it can count against max_nongroup instead. */
185 static HARD_REG_SET counted_for_groups
;
187 /* Indicates if a register was counted against the need for
188 non-groups. 0 means it can become part of a new group.
189 During choose_reload_regs, 1 here means don't use this reg
190 as part of a group, even if it seems to be otherwise ok. */
191 static HARD_REG_SET counted_for_nongroups
;
193 /* Indexed by pseudo reg number N,
194 says may not delete stores into the real (memory) home of pseudo N.
195 This is set if we already substituted a memory equivalent in some uses,
196 which happens when we have to eliminate the fp from it. */
197 static char *cannot_omit_stores
;
199 /* Nonzero if indirect addressing is supported on the machine; this means
200 that spilling (REG n) does not require reloading it into a register in
201 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
202 value indicates the level of indirect addressing supported, e.g., two
203 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
206 static char spill_indirect_levels
;
208 /* Nonzero if indirect addressing is supported when the innermost MEM is
209 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
210 which these are valid is the same as spill_indirect_levels, above. */
212 char indirect_symref_ok
;
214 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
216 char double_reg_address_ok
;
218 /* Record the stack slot for each spilled hard register. */
220 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
222 /* Width allocated so far for that stack slot. */
224 static int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
226 /* Indexed by register class and basic block number, nonzero if there is
227 any need for a spill register of that class in that basic block.
228 The pointer is 0 if we did stupid allocation and don't know
229 the structure of basic blocks. */
231 char *basic_block_needs
[N_REG_CLASSES
];
233 /* First uid used by insns created by reload in this function.
234 Used in find_equiv_reg. */
235 int reload_first_uid
;
237 /* Flag set by local-alloc or global-alloc if anything is live in
238 a call-clobbered reg across calls. */
240 int caller_save_needed
;
242 /* Set to 1 while reload_as_needed is operating.
243 Required by some machines to handle any generated moves differently. */
245 int reload_in_progress
= 0;
247 /* These arrays record the insn_code of insns that may be needed to
248 perform input and output reloads of special objects. They provide a
249 place to pass a scratch register. */
251 enum insn_code reload_in_optab
[NUM_MACHINE_MODES
];
252 enum insn_code reload_out_optab
[NUM_MACHINE_MODES
];
254 /* This obstack is used for allocation of rtl during register elimination.
255 The allocated storage can be freed once find_reloads has processed the
258 struct obstack reload_obstack
;
259 char *reload_firstobj
;
261 #define obstack_chunk_alloc xmalloc
262 #define obstack_chunk_free free
264 /* List of labels that must never be deleted. */
265 extern rtx forced_labels
;
267 /* This structure is used to record information about register eliminations.
268 Each array entry describes one possible way of eliminating a register
269 in favor of another. If there is more than one way of eliminating a
270 particular register, the most preferred should be specified first. */
272 static struct elim_table
274 int from
; /* Register number to be eliminated. */
275 int to
; /* Register number used as replacement. */
276 int initial_offset
; /* Initial difference between values. */
277 int can_eliminate
; /* Non-zero if this elimination can be done. */
278 int can_eliminate_previous
; /* Value of CAN_ELIMINATE in previous scan over
279 insns made by reload. */
280 int offset
; /* Current offset between the two regs. */
281 int max_offset
; /* Maximum offset between the two regs. */
282 int previous_offset
; /* Offset at end of previous insn. */
283 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
284 rtx from_rtx
; /* REG rtx for the register to be eliminated.
285 We cannot simply compare the number since
286 we might then spuriously replace a hard
287 register corresponding to a pseudo
288 assigned to the reg to be eliminated. */
289 rtx to_rtx
; /* REG rtx for the replacement. */
292 /* If a set of eliminable registers was specified, define the table from it.
293 Otherwise, default to the normal case of the frame pointer being
294 replaced by the stack pointer. */
296 #ifdef ELIMINABLE_REGS
299 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
302 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0])
304 /* Record the number of pending eliminations that have an offset not equal
305 to their initial offset. If non-zero, we use a new copy of each
306 replacement result in any insns encountered. */
307 static int num_not_at_initial_offset
;
309 /* Count the number of registers that we may be able to eliminate. */
310 static int num_eliminable
;
312 /* For each label, we record the offset of each elimination. If we reach
313 a label by more than one path and an offset differs, we cannot do the
314 elimination. This information is indexed by the number of the label.
315 The first table is an array of flags that records whether we have yet
316 encountered a label and the second table is an array of arrays, one
317 entry in the latter array for each elimination. */
319 static char *offsets_known_at
;
320 static int (*offsets_at
)[NUM_ELIMINABLE_REGS
];
322 /* Number of labels in the current function. */
324 static int num_labels
;
326 struct hard_reg_n_uses
{ int regno
; int uses
; };
328 static int possible_group_p
PROTO((int, int *));
329 static void count_possible_groups
PROTO((int *, enum machine_mode
*,
331 static int modes_equiv_for_class_p
PROTO((enum machine_mode
,
334 static void spill_failure
PROTO((rtx
));
335 static int new_spill_reg
PROTO((int, int, int *, int *, int,
337 static void delete_dead_insn
PROTO((rtx
));
338 static void alter_reg
PROTO((int, int));
339 static void mark_scratch_live
PROTO((rtx
));
340 static void set_label_offsets
PROTO((rtx
, rtx
, int));
341 static int eliminate_regs_in_insn
PROTO((rtx
, int));
342 static void mark_not_eliminable
PROTO((rtx
, rtx
));
343 static int spill_hard_reg
PROTO((int, int, FILE *, int));
344 static void scan_paradoxical_subregs
PROTO((rtx
));
345 static int hard_reg_use_compare
PROTO((struct hard_reg_n_uses
*,
346 struct hard_reg_n_uses
*));
347 static void order_regs_for_reload
PROTO((void));
348 static void reload_as_needed
PROTO((rtx
, int));
349 static void forget_old_reloads_1
PROTO((rtx
, rtx
));
350 static int reload_reg_class_lower
PROTO((short *, short *));
351 static void mark_reload_reg_in_use
PROTO((int, int, enum reload_type
,
353 static void clear_reload_reg_in_use
PROTO((int, int, enum reload_type
,
355 static int reload_reg_free_p
PROTO((int, int, enum reload_type
));
356 static int reload_reg_free_before_p
PROTO((int, int, enum reload_type
));
357 static int reload_reg_reaches_end_p
PROTO((int, int, enum reload_type
));
358 static int allocate_reload_reg
PROTO((int, rtx
, int, int));
359 static void choose_reload_regs
PROTO((rtx
, rtx
));
360 static void merge_assigned_reloads
PROTO((rtx
));
361 static void emit_reload_insns
PROTO((rtx
));
362 static void delete_output_reload
PROTO((rtx
, int, rtx
));
363 static void inc_for_reload
PROTO((rtx
, rtx
, int));
364 static int constraint_accepts_reg_p
PROTO((char *, rtx
));
365 static int count_occurrences
PROTO((rtx
, rtx
));
367 /* Initialize the reload pass once per compilation. */
374 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
375 Set spill_indirect_levels to the number of levels such addressing is
376 permitted, zero if it is not permitted at all. */
379 = gen_rtx (MEM
, Pmode
,
380 gen_rtx (PLUS
, Pmode
,
381 gen_rtx (REG
, Pmode
, LAST_VIRTUAL_REGISTER
+ 1),
383 spill_indirect_levels
= 0;
385 while (memory_address_p (QImode
, tem
))
387 spill_indirect_levels
++;
388 tem
= gen_rtx (MEM
, Pmode
, tem
);
391 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
393 tem
= gen_rtx (MEM
, Pmode
, gen_rtx (SYMBOL_REF
, Pmode
, "foo"));
394 indirect_symref_ok
= memory_address_p (QImode
, tem
);
396 /* See if reg+reg is a valid (and offsettable) address. */
398 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
400 tem
= gen_rtx (PLUS
, Pmode
,
401 gen_rtx (REG
, Pmode
, HARD_FRAME_POINTER_REGNUM
),
402 gen_rtx (REG
, Pmode
, i
));
403 /* This way, we make sure that reg+reg is an offsettable address. */
404 tem
= plus_constant (tem
, 4);
406 if (memory_address_p (QImode
, tem
))
408 double_reg_address_ok
= 1;
413 /* Initialize obstack for our rtl allocation. */
414 gcc_obstack_init (&reload_obstack
);
415 reload_firstobj
= (char *) obstack_alloc (&reload_obstack
, 0);
418 /* Main entry point for the reload pass.
420 FIRST is the first insn of the function being compiled.
422 GLOBAL nonzero means we were called from global_alloc
423 and should attempt to reallocate any pseudoregs that we
424 displace from hard regs we will use for reloads.
425 If GLOBAL is zero, we do not have enough information to do that,
426 so any pseudo reg that is spilled must go to the stack.
428 DUMPFILE is the global-reg debugging dump file stream, or 0.
429 If it is nonzero, messages are written to it to describe
430 which registers are seized as reload regs, which pseudo regs
431 are spilled from them, and where the pseudo regs are reallocated to.
433 Return value is nonzero if reload failed
434 and we must not do any more for this function. */
437 reload (first
, global
, dumpfile
)
445 register struct elim_table
*ep
;
447 int something_changed
;
448 int something_needs_reloads
;
449 int something_needs_elimination
;
450 int new_basic_block_needs
;
451 enum reg_class caller_save_spill_class
= NO_REGS
;
452 int caller_save_group_size
= 1;
454 /* Nonzero means we couldn't get enough spill regs. */
457 /* The basic block number currently being processed for INSN. */
460 /* Make sure even insns with volatile mem refs are recognizable. */
463 /* Enable find_equiv_reg to distinguish insns made by reload. */
464 reload_first_uid
= get_max_uid ();
466 for (i
= 0; i
< N_REG_CLASSES
; i
++)
467 basic_block_needs
[i
] = 0;
469 #ifdef SECONDARY_MEMORY_NEEDED
470 /* Initialize the secondary memory table. */
471 clear_secondary_mem ();
474 /* Remember which hard regs appear explicitly
475 before we merge into `regs_ever_live' the ones in which
476 pseudo regs have been allocated. */
477 bcopy (regs_ever_live
, regs_explicitly_used
, sizeof regs_ever_live
);
479 /* We don't have a stack slot for any spill reg yet. */
480 bzero (spill_stack_slot
, sizeof spill_stack_slot
);
481 bzero (spill_stack_slot_width
, sizeof spill_stack_slot_width
);
483 /* Initialize the save area information for caller-save, in case some
487 /* Compute which hard registers are now in use
488 as homes for pseudo registers.
489 This is done here rather than (eg) in global_alloc
490 because this point is reached even if not optimizing. */
492 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
495 for (i
= 0; i
< scratch_list_length
; i
++)
497 mark_scratch_live (scratch_list
[i
]);
499 /* Make sure that the last insn in the chain
500 is not something that needs reloading. */
501 emit_note (NULL_PTR
, NOTE_INSN_DELETED
);
503 /* Find all the pseudo registers that didn't get hard regs
504 but do have known equivalent constants or memory slots.
505 These include parameters (known equivalent to parameter slots)
506 and cse'd or loop-moved constant memory addresses.
508 Record constant equivalents in reg_equiv_constant
509 so they will be substituted by find_reloads.
510 Record memory equivalents in reg_mem_equiv so they can
511 be substituted eventually by altering the REG-rtx's. */
513 reg_equiv_constant
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
514 bzero (reg_equiv_constant
, max_regno
* sizeof (rtx
));
515 reg_equiv_memory_loc
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
516 bzero (reg_equiv_memory_loc
, max_regno
* sizeof (rtx
));
517 reg_equiv_mem
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
518 bzero (reg_equiv_mem
, max_regno
* sizeof (rtx
));
519 reg_equiv_init
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
520 bzero (reg_equiv_init
, max_regno
* sizeof (rtx
));
521 reg_equiv_address
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
522 bzero (reg_equiv_address
, max_regno
* sizeof (rtx
));
523 reg_max_ref_width
= (int *) alloca (max_regno
* sizeof (int));
524 bzero (reg_max_ref_width
, max_regno
* sizeof (int));
525 cannot_omit_stores
= (char *) alloca (max_regno
);
526 bzero (cannot_omit_stores
, max_regno
);
528 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
529 Also find all paradoxical subregs
530 and find largest such for each pseudo. */
532 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
534 rtx set
= single_set (insn
);
536 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
)
538 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
540 #ifdef LEGITIMATE_PIC_OPERAND_P
541 && (! CONSTANT_P (XEXP (note
, 0)) || ! flag_pic
542 || LEGITIMATE_PIC_OPERAND_P (XEXP (note
, 0)))
546 rtx x
= XEXP (note
, 0);
547 i
= REGNO (SET_DEST (set
));
548 if (i
> LAST_VIRTUAL_REGISTER
)
550 if (GET_CODE (x
) == MEM
)
551 reg_equiv_memory_loc
[i
] = x
;
552 else if (CONSTANT_P (x
))
554 if (LEGITIMATE_CONSTANT_P (x
))
555 reg_equiv_constant
[i
] = x
;
557 reg_equiv_memory_loc
[i
]
558 = force_const_mem (GET_MODE (SET_DEST (set
)), x
);
563 /* If this register is being made equivalent to a MEM
564 and the MEM is not SET_SRC, the equivalencing insn
565 is one with the MEM as a SET_DEST and it occurs later.
566 So don't mark this insn now. */
567 if (GET_CODE (x
) != MEM
568 || rtx_equal_p (SET_SRC (set
), x
))
569 reg_equiv_init
[i
] = insn
;
574 /* If this insn is setting a MEM from a register equivalent to it,
575 this is the equivalencing insn. */
576 else if (set
&& GET_CODE (SET_DEST (set
)) == MEM
577 && GET_CODE (SET_SRC (set
)) == REG
578 && reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]
579 && rtx_equal_p (SET_DEST (set
),
580 reg_equiv_memory_loc
[REGNO (SET_SRC (set
))]))
581 reg_equiv_init
[REGNO (SET_SRC (set
))] = insn
;
583 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
584 scan_paradoxical_subregs (PATTERN (insn
));
587 /* Does this function require a frame pointer? */
589 frame_pointer_needed
= (! flag_omit_frame_pointer
590 #ifdef EXIT_IGNORE_STACK
591 /* ?? If EXIT_IGNORE_STACK is set, we will not save
592 and restore sp for alloca. So we can't eliminate
593 the frame pointer in that case. At some point,
594 we should improve this by emitting the
595 sp-adjusting insns for this case. */
596 || (current_function_calls_alloca
597 && EXIT_IGNORE_STACK
)
599 || FRAME_POINTER_REQUIRED
);
603 /* Initialize the table of registers to eliminate. The way we do this
604 depends on how the eliminable registers were defined. */
605 #ifdef ELIMINABLE_REGS
606 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
608 ep
->can_eliminate
= ep
->can_eliminate_previous
609 = (CAN_ELIMINATE (ep
->from
, ep
->to
)
610 && (ep
->from
!= HARD_FRAME_POINTER_REGNUM
611 || ! frame_pointer_needed
));
614 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
615 = ! frame_pointer_needed
;
618 /* Count the number of eliminable registers and build the FROM and TO
619 REG rtx's. Note that code in gen_rtx will cause, e.g.,
620 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
621 We depend on this. */
622 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
624 num_eliminable
+= ep
->can_eliminate
;
625 ep
->from_rtx
= gen_rtx (REG
, Pmode
, ep
->from
);
626 ep
->to_rtx
= gen_rtx (REG
, Pmode
, ep
->to
);
629 num_labels
= max_label_num () - get_first_label_num ();
631 /* Allocate the tables used to store offset information at labels. */
632 offsets_known_at
= (char *) alloca (num_labels
);
634 = (int (*)[NUM_ELIMINABLE_REGS
])
635 alloca (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (int));
637 offsets_known_at
-= get_first_label_num ();
638 offsets_at
-= get_first_label_num ();
640 /* Alter each pseudo-reg rtx to contain its hard reg number.
641 Assign stack slots to the pseudos that lack hard regs or equivalents.
642 Do not touch virtual registers. */
644 for (i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
647 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done here
648 because the stack size may be a part of the offset computation for
649 register elimination. */
650 assign_stack_local (BLKmode
, 0, 0);
652 /* If we have some registers we think can be eliminated, scan all insns to
653 see if there is an insn that sets one of these registers to something
654 other than itself plus a constant. If so, the register cannot be
655 eliminated. Doing this scan here eliminates an extra pass through the
656 main reload loop in the most common case where register elimination
658 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
659 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == JUMP_INSN
660 || GET_CODE (insn
) == CALL_INSN
)
661 note_stores (PATTERN (insn
), mark_not_eliminable
);
663 #ifndef REGISTER_CONSTRAINTS
664 /* If all the pseudo regs have hard regs,
665 except for those that are never referenced,
666 we know that no reloads are needed. */
667 /* But that is not true if there are register constraints, since
668 in that case some pseudos might be in the wrong kind of hard reg. */
670 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
671 if (reg_renumber
[i
] == -1 && reg_n_refs
[i
] != 0)
674 if (i
== max_regno
&& num_eliminable
== 0 && ! caller_save_needed
)
678 /* Compute the order of preference for hard registers to spill.
679 Store them by decreasing preference in potential_reload_regs. */
681 order_regs_for_reload ();
683 /* So far, no hard regs have been spilled. */
685 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
686 spill_reg_order
[i
] = -1;
688 /* On most machines, we can't use any register explicitly used in the
689 rtl as a spill register. But on some, we have to. Those will have
690 taken care to keep the life of hard regs as short as possible. */
692 #ifdef SMALL_REGISTER_CLASSES
693 CLEAR_HARD_REG_SET (forbidden_regs
);
695 COPY_HARD_REG_SET (forbidden_regs
, bad_spill_regs
);
698 /* Spill any hard regs that we know we can't eliminate. */
699 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
700 if (! ep
->can_eliminate
)
702 spill_hard_reg (ep
->from
, global
, dumpfile
, 1);
703 regs_ever_live
[ep
->from
] = 1;
707 for (i
= 0; i
< N_REG_CLASSES
; i
++)
709 basic_block_needs
[i
] = (char *)alloca (n_basic_blocks
);
710 bzero (basic_block_needs
[i
], n_basic_blocks
);
713 /* From now on, we need to emit any moves without making new pseudos. */
714 reload_in_progress
= 1;
716 /* This loop scans the entire function each go-round
717 and repeats until one repetition spills no additional hard regs. */
719 /* This flag is set when a pseudo reg is spilled,
720 to require another pass. Note that getting an additional reload
721 reg does not necessarily imply any pseudo reg was spilled;
722 sometimes we find a reload reg that no pseudo reg was allocated in. */
723 something_changed
= 1;
724 /* This flag is set if there are any insns that require reloading. */
725 something_needs_reloads
= 0;
726 /* This flag is set if there are any insns that require register
728 something_needs_elimination
= 0;
729 while (something_changed
)
733 /* For each class, number of reload regs needed in that class.
734 This is the maximum over all insns of the needs in that class
735 of the individual insn. */
736 int max_needs
[N_REG_CLASSES
];
737 /* For each class, size of group of consecutive regs
738 that is needed for the reloads of this class. */
739 int group_size
[N_REG_CLASSES
];
740 /* For each class, max number of consecutive groups needed.
741 (Each group contains group_size[CLASS] consecutive registers.) */
742 int max_groups
[N_REG_CLASSES
];
743 /* For each class, max number needed of regs that don't belong
744 to any of the groups. */
745 int max_nongroups
[N_REG_CLASSES
];
746 /* For each class, the machine mode which requires consecutive
747 groups of regs of that class.
748 If two different modes ever require groups of one class,
749 they must be the same size and equally restrictive for that class,
750 otherwise we can't handle the complexity. */
751 enum machine_mode group_mode
[N_REG_CLASSES
];
752 /* Record the insn where each maximum need is first found. */
753 rtx max_needs_insn
[N_REG_CLASSES
];
754 rtx max_groups_insn
[N_REG_CLASSES
];
755 rtx max_nongroups_insn
[N_REG_CLASSES
];
757 int starting_frame_size
= get_frame_size ();
758 static char *reg_class_names
[] = REG_CLASS_NAMES
;
760 something_changed
= 0;
761 bzero (max_needs
, sizeof max_needs
);
762 bzero (max_groups
, sizeof max_groups
);
763 bzero (max_nongroups
, sizeof max_nongroups
);
764 bzero (max_needs_insn
, sizeof max_needs_insn
);
765 bzero (max_groups_insn
, sizeof max_groups_insn
);
766 bzero (max_nongroups_insn
, sizeof max_nongroups_insn
);
767 bzero (group_size
, sizeof group_size
);
768 for (i
= 0; i
< N_REG_CLASSES
; i
++)
769 group_mode
[i
] = VOIDmode
;
771 /* Keep track of which basic blocks are needing the reloads. */
774 /* Remember whether any element of basic_block_needs
775 changes from 0 to 1 in this pass. */
776 new_basic_block_needs
= 0;
778 /* Reset all offsets on eliminable registers to their initial values. */
779 #ifdef ELIMINABLE_REGS
780 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
782 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
783 ep
->previous_offset
= ep
->offset
784 = ep
->max_offset
= ep
->initial_offset
;
787 #ifdef INITIAL_FRAME_POINTER_OFFSET
788 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate
[0].initial_offset
);
790 if (!FRAME_POINTER_REQUIRED
)
792 reg_eliminate
[0].initial_offset
= 0;
794 reg_eliminate
[0].previous_offset
= reg_eliminate
[0].max_offset
795 = reg_eliminate
[0].offset
= reg_eliminate
[0].initial_offset
;
798 num_not_at_initial_offset
= 0;
800 bzero (&offsets_known_at
[get_first_label_num ()], num_labels
);
802 /* Set a known offset for each forced label to be at the initial offset
803 of each elimination. We do this because we assume that all
804 computed jumps occur from a location where each elimination is
805 at its initial offset. */
807 for (x
= forced_labels
; x
; x
= XEXP (x
, 1))
809 set_label_offsets (XEXP (x
, 0), NULL_RTX
, 1);
811 /* For each pseudo register that has an equivalent location defined,
812 try to eliminate any eliminable registers (such as the frame pointer)
813 assuming initial offsets for the replacement register, which
816 If the resulting location is directly addressable, substitute
817 the MEM we just got directly for the old REG.
819 If it is not addressable but is a constant or the sum of a hard reg
820 and constant, it is probably not addressable because the constant is
821 out of range, in that case record the address; we will generate
822 hairy code to compute the address in a register each time it is
823 needed. Similarly if it is a hard register, but one that is not
824 valid as an address register.
826 If the location is not addressable, but does not have one of the
827 above forms, assign a stack slot. We have to do this to avoid the
828 potential of producing lots of reloads if, e.g., a location involves
829 a pseudo that didn't get a hard register and has an equivalent memory
830 location that also involves a pseudo that didn't get a hard register.
832 Perhaps at some point we will improve reload_when_needed handling
833 so this problem goes away. But that's very hairy. */
835 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
836 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc
[i
])
838 rtx x
= eliminate_regs (reg_equiv_memory_loc
[i
], 0, NULL_RTX
);
840 if (strict_memory_address_p (GET_MODE (regno_reg_rtx
[i
]),
842 reg_equiv_mem
[i
] = x
, reg_equiv_address
[i
] = 0;
843 else if (CONSTANT_P (XEXP (x
, 0))
844 || (GET_CODE (XEXP (x
, 0)) == REG
845 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
846 || (GET_CODE (XEXP (x
, 0)) == PLUS
847 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
848 && (REGNO (XEXP (XEXP (x
, 0), 0))
849 < FIRST_PSEUDO_REGISTER
)
850 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
851 reg_equiv_address
[i
] = XEXP (x
, 0), reg_equiv_mem
[i
] = 0;
854 /* Make a new stack slot. Then indicate that something
855 changed so we go back and recompute offsets for
856 eliminable registers because the allocation of memory
857 below might change some offset. reg_equiv_{mem,address}
858 will be set up for this pseudo on the next pass around
860 reg_equiv_memory_loc
[i
] = 0;
861 reg_equiv_init
[i
] = 0;
863 something_changed
= 1;
867 /* If we allocated another pseudo to the stack, redo elimination
869 if (something_changed
)
872 /* If caller-saves needs a group, initialize the group to include
873 the size and mode required for caller-saves. */
875 if (caller_save_group_size
> 1)
877 group_mode
[(int) caller_save_spill_class
] = Pmode
;
878 group_size
[(int) caller_save_spill_class
] = caller_save_group_size
;
881 /* Compute the most additional registers needed by any instruction.
882 Collect information separately for each class of regs. */
884 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
886 if (global
&& this_block
+ 1 < n_basic_blocks
887 && insn
== basic_block_head
[this_block
+1])
890 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which
891 might include REG_LABEL), we need to see what effects this
892 has on the known offsets at labels. */
894 if (GET_CODE (insn
) == CODE_LABEL
|| GET_CODE (insn
) == JUMP_INSN
895 || (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
896 && REG_NOTES (insn
) != 0))
897 set_label_offsets (insn
, insn
, 0);
899 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
901 /* Nonzero means don't use a reload reg that overlaps
902 the place where a function value can be returned. */
903 rtx avoid_return_reg
= 0;
905 rtx old_body
= PATTERN (insn
);
906 int old_code
= INSN_CODE (insn
);
907 rtx old_notes
= REG_NOTES (insn
);
908 int did_elimination
= 0;
909 int max_total_input_groups
= 0, max_total_output_groups
= 0;
911 /* To compute the number of reload registers of each class
912 needed for an insn, we must similate what choose_reload_regs
913 can do. We do this by splitting an insn into an "input" and
914 an "output" part. RELOAD_OTHER reloads are used in both.
915 The input part uses those reloads, RELOAD_FOR_INPUT reloads,
916 which must be live over the entire input section of reloads,
917 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and
918 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the
921 The registers needed for output are RELOAD_OTHER and
922 RELOAD_FOR_OUTPUT, which are live for the entire output
923 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS
924 reloads for each operand.
926 The total number of registers needed is the maximum of the
927 inputs and outputs. */
929 /* These just count RELOAD_OTHER. */
930 int insn_needs
[N_REG_CLASSES
];
931 int insn_groups
[N_REG_CLASSES
];
932 int insn_total_groups
= 0;
934 /* Count RELOAD_FOR_INPUT reloads. */
935 int insn_needs_for_inputs
[N_REG_CLASSES
];
936 int insn_groups_for_inputs
[N_REG_CLASSES
];
937 int insn_total_groups_for_inputs
= 0;
939 /* Count RELOAD_FOR_OUTPUT reloads. */
940 int insn_needs_for_outputs
[N_REG_CLASSES
];
941 int insn_groups_for_outputs
[N_REG_CLASSES
];
942 int insn_total_groups_for_outputs
= 0;
944 /* Count RELOAD_FOR_INSN reloads. */
945 int insn_needs_for_insn
[N_REG_CLASSES
];
946 int insn_groups_for_insn
[N_REG_CLASSES
];
947 int insn_total_groups_for_insn
= 0;
949 /* Count RELOAD_FOR_OTHER_ADDRESS reloads. */
950 int insn_needs_for_other_addr
[N_REG_CLASSES
];
951 int insn_groups_for_other_addr
[N_REG_CLASSES
];
952 int insn_total_groups_for_other_addr
= 0;
954 /* Count RELOAD_FOR_INPUT_ADDRESS reloads. */
955 int insn_needs_for_in_addr
[MAX_RECOG_OPERANDS
][N_REG_CLASSES
];
956 int insn_groups_for_in_addr
[MAX_RECOG_OPERANDS
][N_REG_CLASSES
];
957 int insn_total_groups_for_in_addr
[MAX_RECOG_OPERANDS
];
959 /* Count RELOAD_FOR_OUTPUT_ADDRESS reloads. */
960 int insn_needs_for_out_addr
[MAX_RECOG_OPERANDS
][N_REG_CLASSES
];
961 int insn_groups_for_out_addr
[MAX_RECOG_OPERANDS
][N_REG_CLASSES
];
962 int insn_total_groups_for_out_addr
[MAX_RECOG_OPERANDS
];
964 /* Count RELOAD_FOR_OPERAND_ADDRESS reloads. */
965 int insn_needs_for_op_addr
[N_REG_CLASSES
];
966 int insn_groups_for_op_addr
[N_REG_CLASSES
];
967 int insn_total_groups_for_op_addr
= 0;
969 #if 0 /* This wouldn't work nowadays, since optimize_bit_field
970 looks for non-strict memory addresses. */
971 /* Optimization: a bit-field instruction whose field
972 happens to be a byte or halfword in memory
973 can be changed to a move instruction. */
975 if (GET_CODE (PATTERN (insn
)) == SET
)
977 rtx dest
= SET_DEST (PATTERN (insn
));
978 rtx src
= SET_SRC (PATTERN (insn
));
980 if (GET_CODE (dest
) == ZERO_EXTRACT
981 || GET_CODE (dest
) == SIGN_EXTRACT
)
982 optimize_bit_field (PATTERN (insn
), insn
, reg_equiv_mem
);
983 if (GET_CODE (src
) == ZERO_EXTRACT
984 || GET_CODE (src
) == SIGN_EXTRACT
)
985 optimize_bit_field (PATTERN (insn
), insn
, reg_equiv_mem
);
989 /* If needed, eliminate any eliminable registers. */
991 did_elimination
= eliminate_regs_in_insn (insn
, 0);
993 #ifdef SMALL_REGISTER_CLASSES
994 /* Set avoid_return_reg if this is an insn
995 that might use the value of a function call. */
996 if (GET_CODE (insn
) == CALL_INSN
)
998 if (GET_CODE (PATTERN (insn
)) == SET
)
999 after_call
= SET_DEST (PATTERN (insn
));
1000 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1001 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1002 after_call
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
1006 else if (after_call
!= 0
1007 && !(GET_CODE (PATTERN (insn
)) == SET
1008 && SET_DEST (PATTERN (insn
)) == stack_pointer_rtx
))
1010 if (reg_mentioned_p (after_call
, PATTERN (insn
)))
1011 avoid_return_reg
= after_call
;
1014 #endif /* SMALL_REGISTER_CLASSES */
1016 /* Analyze the instruction. */
1017 find_reloads (insn
, 0, spill_indirect_levels
, global
,
1020 /* Remember for later shortcuts which insns had any reloads or
1021 register eliminations.
1023 One might think that it would be worthwhile to mark insns
1024 that need register replacements but not reloads, but this is
1025 not safe because find_reloads may do some manipulation of
1026 the insn (such as swapping commutative operands), which would
1027 be lost when we restore the old pattern after register
1028 replacement. So the actions of find_reloads must be redone in
1029 subsequent passes or in reload_as_needed.
1031 However, it is safe to mark insns that need reloads
1032 but not register replacement. */
1034 PUT_MODE (insn
, (did_elimination
? QImode
1035 : n_reloads
? HImode
1036 : GET_MODE (insn
) == DImode
? DImode
1039 /* Discard any register replacements done. */
1040 if (did_elimination
)
1042 obstack_free (&reload_obstack
, reload_firstobj
);
1043 PATTERN (insn
) = old_body
;
1044 INSN_CODE (insn
) = old_code
;
1045 REG_NOTES (insn
) = old_notes
;
1046 something_needs_elimination
= 1;
1049 /* If this insn has no reloads, we need not do anything except
1050 in the case of a CALL_INSN when we have caller-saves and
1051 caller-save needs reloads. */
1054 && ! (GET_CODE (insn
) == CALL_INSN
1055 && caller_save_spill_class
!= NO_REGS
))
1058 something_needs_reloads
= 1;
1060 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1062 insn_needs
[i
] = 0, insn_groups
[i
] = 0;
1063 insn_needs_for_inputs
[i
] = 0, insn_groups_for_inputs
[i
] = 0;
1064 insn_needs_for_outputs
[i
] = 0, insn_groups_for_outputs
[i
] = 0;
1065 insn_needs_for_insn
[i
] = 0, insn_groups_for_insn
[i
] = 0;
1066 insn_needs_for_op_addr
[i
] = 0, insn_groups_for_op_addr
[i
] = 0;
1067 insn_needs_for_other_addr
[i
] = 0;
1068 insn_groups_for_other_addr
[i
] = 0;
1071 for (i
= 0; i
< reload_n_operands
; i
++)
1073 insn_total_groups_for_in_addr
[i
] = 0;
1074 insn_total_groups_for_out_addr
[i
] = 0;
1076 for (j
= 0; j
< N_REG_CLASSES
; j
++)
1078 insn_needs_for_in_addr
[i
][j
] = 0;
1079 insn_needs_for_out_addr
[i
][j
] = 0;
1080 insn_groups_for_in_addr
[i
][j
] = 0;
1081 insn_groups_for_out_addr
[i
][j
] = 0;
1085 /* Count each reload once in every class
1086 containing the reload's own class. */
1088 for (i
= 0; i
< n_reloads
; i
++)
1090 register enum reg_class
*p
;
1091 enum reg_class
class = reload_reg_class
[i
];
1093 enum machine_mode mode
;
1096 int *this_total_groups
;
1098 /* Don't count the dummy reloads, for which one of the
1099 regs mentioned in the insn can be used for reloading.
1100 Don't count optional reloads.
1101 Don't count reloads that got combined with others. */
1102 if (reload_reg_rtx
[i
] != 0
1103 || reload_optional
[i
] != 0
1104 || (reload_out
[i
] == 0 && reload_in
[i
] == 0
1105 && ! reload_secondary_p
[i
]))
1108 /* Show that a reload register of this class is needed
1109 in this basic block. We do not use insn_needs and
1110 insn_groups because they are overly conservative for
1112 if (global
&& ! basic_block_needs
[(int) class][this_block
])
1114 basic_block_needs
[(int) class][this_block
] = 1;
1115 new_basic_block_needs
= 1;
1118 /* Decide which time-of-use to count this reload for. */
1119 switch (reload_when_needed
[i
])
1122 this_needs
= insn_needs
;
1123 this_groups
= insn_groups
;
1124 this_total_groups
= &insn_total_groups
;
1127 case RELOAD_FOR_INPUT
:
1128 this_needs
= insn_needs_for_inputs
;
1129 this_groups
= insn_groups_for_inputs
;
1130 this_total_groups
= &insn_total_groups_for_inputs
;
1133 case RELOAD_FOR_OUTPUT
:
1134 this_needs
= insn_needs_for_outputs
;
1135 this_groups
= insn_groups_for_outputs
;
1136 this_total_groups
= &insn_total_groups_for_outputs
;
1139 case RELOAD_FOR_INSN
:
1140 this_needs
= insn_needs_for_insn
;
1141 this_groups
= insn_groups_for_outputs
;
1142 this_total_groups
= &insn_total_groups_for_insn
;
1145 case RELOAD_FOR_OTHER_ADDRESS
:
1146 this_needs
= insn_needs_for_other_addr
;
1147 this_groups
= insn_groups_for_other_addr
;
1148 this_total_groups
= &insn_total_groups_for_other_addr
;
1151 case RELOAD_FOR_INPUT_ADDRESS
:
1152 this_needs
= insn_needs_for_in_addr
[reload_opnum
[i
]];
1153 this_groups
= insn_groups_for_in_addr
[reload_opnum
[i
]];
1155 = &insn_total_groups_for_in_addr
[reload_opnum
[i
]];
1158 case RELOAD_FOR_OUTPUT_ADDRESS
:
1159 this_needs
= insn_needs_for_out_addr
[reload_opnum
[i
]];
1160 this_groups
= insn_groups_for_out_addr
[reload_opnum
[i
]];
1162 = &insn_total_groups_for_out_addr
[reload_opnum
[i
]];
1165 case RELOAD_FOR_OPERAND_ADDRESS
:
1166 this_needs
= insn_needs_for_op_addr
;
1167 this_groups
= insn_groups_for_op_addr
;
1168 this_total_groups
= &insn_total_groups_for_op_addr
;
1172 mode
= reload_inmode
[i
];
1173 if (GET_MODE_SIZE (reload_outmode
[i
]) > GET_MODE_SIZE (mode
))
1174 mode
= reload_outmode
[i
];
1175 size
= CLASS_MAX_NREGS (class, mode
);
1178 enum machine_mode other_mode
, allocate_mode
;
1180 /* Count number of groups needed separately from
1181 number of individual regs needed. */
1182 this_groups
[(int) class]++;
1183 p
= reg_class_superclasses
[(int) class];
1184 while (*p
!= LIM_REG_CLASSES
)
1185 this_groups
[(int) *p
++]++;
1186 (*this_total_groups
)++;
1188 /* Record size and mode of a group of this class. */
1189 /* If more than one size group is needed,
1190 make all groups the largest needed size. */
1191 if (group_size
[(int) class] < size
)
1193 other_mode
= group_mode
[(int) class];
1194 allocate_mode
= mode
;
1196 group_size
[(int) class] = size
;
1197 group_mode
[(int) class] = mode
;
1202 allocate_mode
= group_mode
[(int) class];
1205 /* Crash if two dissimilar machine modes both need
1206 groups of consecutive regs of the same class. */
1208 if (other_mode
!= VOIDmode
1209 && other_mode
!= allocate_mode
1210 && ! modes_equiv_for_class_p (allocate_mode
,
1217 this_needs
[(int) class] += 1;
1218 p
= reg_class_superclasses
[(int) class];
1219 while (*p
!= LIM_REG_CLASSES
)
1220 this_needs
[(int) *p
++] += 1;
1226 /* All reloads have been counted for this insn;
1227 now merge the various times of use.
1228 This sets insn_needs, etc., to the maximum total number
1229 of registers needed at any point in this insn. */
1231 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1233 int in_max
, out_max
;
1235 for (in_max
= 0, out_max
= 0, j
= 0;
1236 j
< reload_n_operands
; j
++)
1238 in_max
= MAX (in_max
, insn_needs_for_in_addr
[j
][i
]);
1239 out_max
= MAX (out_max
, insn_needs_for_out_addr
[j
][i
]);
1242 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs,
1243 and operand addresses but not things used to reload them.
1244 Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads don't
1245 conflict with things needed to reload inputs or
1248 in_max
= MAX (in_max
, insn_needs_for_op_addr
[i
]);
1249 out_max
= MAX (out_max
, insn_needs_for_insn
[i
]);
1251 insn_needs_for_inputs
[i
]
1252 = MAX (insn_needs_for_inputs
[i
]
1253 + insn_needs_for_op_addr
[i
]
1254 + insn_needs_for_insn
[i
],
1255 in_max
+ insn_needs_for_inputs
[i
]);
1257 insn_needs_for_outputs
[i
] += out_max
;
1258 insn_needs
[i
] += MAX (MAX (insn_needs_for_inputs
[i
],
1259 insn_needs_for_outputs
[i
]),
1260 insn_needs_for_other_addr
[i
]);
1262 for (in_max
= 0, out_max
= 0, j
= 0;
1263 j
< reload_n_operands
; j
++)
1265 in_max
= MAX (in_max
, insn_groups_for_in_addr
[j
][i
]);
1266 out_max
= MAX (out_max
, insn_groups_for_out_addr
[j
][i
]);
1269 in_max
= MAX (in_max
, insn_groups_for_op_addr
[i
]);
1270 out_max
= MAX (out_max
, insn_groups_for_insn
[i
]);
1272 insn_groups_for_inputs
[i
]
1273 = MAX (insn_groups_for_inputs
[i
]
1274 + insn_groups_for_op_addr
[i
]
1275 + insn_groups_for_insn
[i
],
1276 in_max
+ insn_groups_for_inputs
[i
]);
1278 insn_groups_for_outputs
[i
] += out_max
;
1279 insn_groups
[i
] += MAX (MAX (insn_groups_for_inputs
[i
],
1280 insn_groups_for_outputs
[i
]),
1281 insn_groups_for_other_addr
[i
]);
1284 for (i
= 0; i
< reload_n_operands
; i
++)
1286 max_total_input_groups
1287 = MAX (max_total_input_groups
,
1288 insn_total_groups_for_in_addr
[i
]);
1289 max_total_output_groups
1290 = MAX (max_total_output_groups
,
1291 insn_total_groups_for_out_addr
[i
]);
1294 max_total_input_groups
= MAX (max_total_input_groups
,
1295 insn_total_groups_for_op_addr
);
1296 max_total_output_groups
= MAX (max_total_output_groups
,
1297 insn_total_groups_for_insn
);
1299 insn_total_groups_for_inputs
1300 = MAX (max_total_input_groups
+ insn_total_groups_for_op_addr
1301 + insn_total_groups_for_insn
,
1302 max_total_input_groups
+ insn_total_groups_for_inputs
);
1304 insn_total_groups_for_outputs
+= max_total_output_groups
;
1306 insn_total_groups
+= MAX (MAX (insn_total_groups_for_outputs
,
1307 insn_total_groups_for_inputs
),
1308 insn_total_groups_for_other_addr
);
1310 /* If this is a CALL_INSN and caller-saves will need
1311 a spill register, act as if the spill register is
1312 needed for this insn. However, the spill register
1313 can be used by any reload of this insn, so we only
1314 need do something if no need for that class has
1317 The assumption that every CALL_INSN will trigger a
1318 caller-save is highly conservative, however, the number
1319 of cases where caller-saves will need a spill register but
1320 a block containing a CALL_INSN won't need a spill register
1321 of that class should be quite rare.
1323 If a group is needed, the size and mode of the group will
1324 have been set up at the beginning of this loop. */
1326 if (GET_CODE (insn
) == CALL_INSN
1327 && caller_save_spill_class
!= NO_REGS
)
1329 int *caller_save_needs
1330 = (caller_save_group_size
> 1 ? insn_groups
: insn_needs
);
1332 if (caller_save_needs
[(int) caller_save_spill_class
] == 0)
1334 register enum reg_class
*p
1335 = reg_class_superclasses
[(int) caller_save_spill_class
];
1337 caller_save_needs
[(int) caller_save_spill_class
]++;
1339 while (*p
!= LIM_REG_CLASSES
)
1340 caller_save_needs
[(int) *p
++] += 1;
1343 if (caller_save_group_size
> 1)
1344 insn_total_groups
= MAX (insn_total_groups
, 1);
1347 /* Show that this basic block will need a register of
1351 && ! (basic_block_needs
[(int) caller_save_spill_class
]
1354 basic_block_needs
[(int) caller_save_spill_class
]
1356 new_basic_block_needs
= 1;
1360 #ifdef SMALL_REGISTER_CLASSES
1361 /* If this insn stores the value of a function call,
1362 and that value is in a register that has been spilled,
1363 and if the insn needs a reload in a class
1364 that might use that register as the reload register,
1365 then add add an extra need in that class.
1366 This makes sure we have a register available that does
1367 not overlap the return value. */
1368 if (avoid_return_reg
)
1370 int regno
= REGNO (avoid_return_reg
);
1372 = HARD_REGNO_NREGS (regno
, GET_MODE (avoid_return_reg
));
1374 int basic_needs
[N_REG_CLASSES
], basic_groups
[N_REG_CLASSES
];
1376 /* First compute the "basic needs", which counts a
1377 need only in the smallest class in which it
1380 bcopy (insn_needs
, basic_needs
, sizeof basic_needs
);
1381 bcopy (insn_groups
, basic_groups
, sizeof basic_groups
);
1383 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1387 if (basic_needs
[i
] >= 0)
1388 for (p
= reg_class_superclasses
[i
];
1389 *p
!= LIM_REG_CLASSES
; p
++)
1390 basic_needs
[(int) *p
] -= basic_needs
[i
];
1392 if (basic_groups
[i
] >= 0)
1393 for (p
= reg_class_superclasses
[i
];
1394 *p
!= LIM_REG_CLASSES
; p
++)
1395 basic_groups
[(int) *p
] -= basic_groups
[i
];
1398 /* Now count extra regs if there might be a conflict with
1399 the return value register.
1401 ??? This is not quite correct because we don't properly
1402 handle the case of groups, but if we end up doing
1403 something wrong, it either will end up not mattering or
1404 we will abort elsewhere. */
1406 for (r
= regno
; r
< regno
+ nregs
; r
++)
1407 if (spill_reg_order
[r
] >= 0)
1408 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1409 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], r
))
1411 if (basic_needs
[i
] > 0 || basic_groups
[i
] > 0)
1416 p
= reg_class_superclasses
[i
];
1417 while (*p
!= LIM_REG_CLASSES
)
1418 insn_needs
[(int) *p
++]++;
1422 #endif /* SMALL_REGISTER_CLASSES */
1424 /* For each class, collect maximum need of any insn. */
1426 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1428 if (max_needs
[i
] < insn_needs
[i
])
1430 max_needs
[i
] = insn_needs
[i
];
1431 max_needs_insn
[i
] = insn
;
1433 if (max_groups
[i
] < insn_groups
[i
])
1435 max_groups
[i
] = insn_groups
[i
];
1436 max_groups_insn
[i
] = insn
;
1438 if (insn_total_groups
> 0)
1439 if (max_nongroups
[i
] < insn_needs
[i
])
1441 max_nongroups
[i
] = insn_needs
[i
];
1442 max_nongroups_insn
[i
] = insn
;
1446 /* Note that there is a continue statement above. */
1449 /* If we allocated any new memory locations, make another pass
1450 since it might have changed elimination offsets. */
1451 if (starting_frame_size
!= get_frame_size ())
1452 something_changed
= 1;
1455 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1457 if (max_needs
[i
] > 0)
1459 ";; Need %d reg%s of class %s (for insn %d).\n",
1460 max_needs
[i
], max_needs
[i
] == 1 ? "" : "s",
1461 reg_class_names
[i
], INSN_UID (max_needs_insn
[i
]));
1462 if (max_nongroups
[i
] > 0)
1464 ";; Need %d nongroup reg%s of class %s (for insn %d).\n",
1465 max_nongroups
[i
], max_nongroups
[i
] == 1 ? "" : "s",
1466 reg_class_names
[i
], INSN_UID (max_nongroups_insn
[i
]));
1467 if (max_groups
[i
] > 0)
1469 ";; Need %d group%s (%smode) of class %s (for insn %d).\n",
1470 max_groups
[i
], max_groups
[i
] == 1 ? "" : "s",
1471 mode_name
[(int) group_mode
[i
]],
1472 reg_class_names
[i
], INSN_UID (max_groups_insn
[i
]));
1475 /* If we have caller-saves, set up the save areas and see if caller-save
1476 will need a spill register. */
1478 if (caller_save_needed
1479 && ! setup_save_areas (&something_changed
)
1480 && caller_save_spill_class
== NO_REGS
)
1482 /* The class we will need depends on whether the machine
1483 supports the sum of two registers for an address; see
1484 find_address_reloads for details. */
1486 caller_save_spill_class
1487 = double_reg_address_ok
? INDEX_REG_CLASS
: BASE_REG_CLASS
;
1488 caller_save_group_size
1489 = CLASS_MAX_NREGS (caller_save_spill_class
, Pmode
);
1490 something_changed
= 1;
1493 /* See if anything that happened changes which eliminations are valid.
1494 For example, on the Sparc, whether or not the frame pointer can
1495 be eliminated can depend on what registers have been used. We need
1496 not check some conditions again (such as flag_omit_frame_pointer)
1497 since they can't have changed. */
1499 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1500 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
&& FRAME_POINTER_REQUIRED
)
1501 #ifdef ELIMINABLE_REGS
1502 || ! CAN_ELIMINATE (ep
->from
, ep
->to
)
1505 ep
->can_eliminate
= 0;
1507 /* Look for the case where we have discovered that we can't replace
1508 register A with register B and that means that we will now be
1509 trying to replace register A with register C. This means we can
1510 no longer replace register C with register B and we need to disable
1511 such an elimination, if it exists. This occurs often with A == ap,
1512 B == sp, and C == fp. */
1514 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1516 struct elim_table
*op
;
1517 register int new_to
= -1;
1519 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
1521 /* Find the current elimination for ep->from, if there is a
1523 for (op
= reg_eliminate
;
1524 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
1525 if (op
->from
== ep
->from
&& op
->can_eliminate
)
1531 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
1533 for (op
= reg_eliminate
;
1534 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
1535 if (op
->from
== new_to
&& op
->to
== ep
->to
)
1536 op
->can_eliminate
= 0;
1540 /* See if any registers that we thought we could eliminate the previous
1541 time are no longer eliminable. If so, something has changed and we
1542 must spill the register. Also, recompute the number of eliminable
1543 registers and see if the frame pointer is needed; it is if there is
1544 no elimination of the frame pointer that we can perform. */
1546 frame_pointer_needed
= 1;
1547 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1549 if (ep
->can_eliminate
&& ep
->from
== FRAME_POINTER_REGNUM
1550 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
)
1551 frame_pointer_needed
= 0;
1553 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
1555 ep
->can_eliminate_previous
= 0;
1556 spill_hard_reg (ep
->from
, global
, dumpfile
, 1);
1557 regs_ever_live
[ep
->from
] = 1;
1558 something_changed
= 1;
1563 /* If all needs are met, we win. */
1565 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1566 if (max_needs
[i
] > 0 || max_groups
[i
] > 0 || max_nongroups
[i
] > 0)
1568 if (i
== N_REG_CLASSES
&& !new_basic_block_needs
&& ! something_changed
)
1571 /* Not all needs are met; must spill some hard regs. */
1573 /* Put all registers spilled so far back in potential_reload_regs, but
1574 put them at the front, since we've already spilled most of the
1575 psuedos in them (we might have left some pseudos unspilled if they
1576 were in a block that didn't need any spill registers of a conflicting
1577 class. We used to try to mark off the need for those registers,
1578 but doing so properly is very complex and reallocating them is the
1579 simpler approach. First, "pack" potential_reload_regs by pushing
1580 any nonnegative entries towards the end. That will leave room
1581 for the registers we already spilled.
1583 Also, undo the marking of the spill registers from the last time
1584 around in FORBIDDEN_REGS since we will be probably be allocating
1587 ??? It is theoretically possible that we might end up not using one
1588 of our previously-spilled registers in this allocation, even though
1589 they are at the head of the list. It's not clear what to do about
1590 this, but it was no better before, when we marked off the needs met
1591 by the previously-spilled registers. With the current code, globals
1592 can be allocated into these registers, but locals cannot. */
1596 for (i
= j
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1597 if (potential_reload_regs
[i
] != -1)
1598 potential_reload_regs
[j
--] = potential_reload_regs
[i
];
1600 for (i
= 0; i
< n_spills
; i
++)
1602 potential_reload_regs
[i
] = spill_regs
[i
];
1603 spill_reg_order
[spill_regs
[i
]] = -1;
1604 CLEAR_HARD_REG_BIT (forbidden_regs
, spill_regs
[i
]);
1610 /* Now find more reload regs to satisfy the remaining need
1611 Do it by ascending class number, since otherwise a reg
1612 might be spilled for a big class and might fail to count
1613 for a smaller class even though it belongs to that class.
1615 Count spilled regs in `spills', and add entries to
1616 `spill_regs' and `spill_reg_order'.
1618 ??? Note there is a problem here.
1619 When there is a need for a group in a high-numbered class,
1620 and also need for non-group regs that come from a lower class,
1621 the non-group regs are chosen first. If there aren't many regs,
1622 they might leave no room for a group.
1624 This was happening on the 386. To fix it, we added the code
1625 that calls possible_group_p, so that the lower class won't
1626 break up the last possible group.
1628 Really fixing the problem would require changes above
1629 in counting the regs already spilled, and in choose_reload_regs.
1630 It might be hard to avoid introducing bugs there. */
1632 CLEAR_HARD_REG_SET (counted_for_groups
);
1633 CLEAR_HARD_REG_SET (counted_for_nongroups
);
1635 for (class = 0; class < N_REG_CLASSES
; class++)
1637 /* First get the groups of registers.
1638 If we got single registers first, we might fragment
1640 while (max_groups
[class] > 0)
1642 /* If any single spilled regs happen to form groups,
1643 count them now. Maybe we don't really need
1644 to spill another group. */
1645 count_possible_groups (group_size
, group_mode
, max_groups
);
1647 if (max_groups
[class] <= 0)
1650 /* Groups of size 2 (the only groups used on most machines)
1651 are treated specially. */
1652 if (group_size
[class] == 2)
1654 /* First, look for a register that will complete a group. */
1655 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1659 j
= potential_reload_regs
[i
];
1660 if (j
>= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
)
1662 ((j
> 0 && (other
= j
- 1, spill_reg_order
[other
] >= 0)
1663 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1664 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1665 && HARD_REGNO_MODE_OK (other
, group_mode
[class])
1666 && ! TEST_HARD_REG_BIT (counted_for_nongroups
,
1668 /* We don't want one part of another group.
1669 We could get "two groups" that overlap! */
1670 && ! TEST_HARD_REG_BIT (counted_for_groups
, other
))
1672 (j
< FIRST_PSEUDO_REGISTER
- 1
1673 && (other
= j
+ 1, spill_reg_order
[other
] >= 0)
1674 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1675 && TEST_HARD_REG_BIT (reg_class_contents
[class], other
)
1676 && HARD_REGNO_MODE_OK (j
, group_mode
[class])
1677 && ! TEST_HARD_REG_BIT (counted_for_nongroups
,
1679 && ! TEST_HARD_REG_BIT (counted_for_groups
,
1682 register enum reg_class
*p
;
1684 /* We have found one that will complete a group,
1685 so count off one group as provided. */
1686 max_groups
[class]--;
1687 p
= reg_class_superclasses
[class];
1688 while (*p
!= LIM_REG_CLASSES
)
1689 max_groups
[(int) *p
++]--;
1691 /* Indicate both these regs are part of a group. */
1692 SET_HARD_REG_BIT (counted_for_groups
, j
);
1693 SET_HARD_REG_BIT (counted_for_groups
, other
);
1697 /* We can't complete a group, so start one. */
1698 if (i
== FIRST_PSEUDO_REGISTER
)
1699 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1702 j
= potential_reload_regs
[i
];
1703 /* Verify that J+1 is a potential reload reg. */
1704 for (k
= 0; k
< FIRST_PSEUDO_REGISTER
; k
++)
1705 if (potential_reload_regs
[k
] == j
+ 1)
1707 if (j
>= 0 && j
+ 1 < FIRST_PSEUDO_REGISTER
1708 && k
< FIRST_PSEUDO_REGISTER
1709 && spill_reg_order
[j
] < 0 && spill_reg_order
[j
+ 1] < 0
1710 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
)
1711 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ 1)
1712 && HARD_REGNO_MODE_OK (j
, group_mode
[class])
1713 && ! TEST_HARD_REG_BIT (counted_for_nongroups
,
1715 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ 1))
1719 /* I should be the index in potential_reload_regs
1720 of the new reload reg we have found. */
1722 if (i
>= FIRST_PSEUDO_REGISTER
)
1724 /* There are no groups left to spill. */
1725 spill_failure (max_groups_insn
[class]);
1731 |= new_spill_reg (i
, class, max_needs
, NULL_PTR
,
1736 /* For groups of more than 2 registers,
1737 look for a sufficient sequence of unspilled registers,
1738 and spill them all at once. */
1739 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1743 j
= potential_reload_regs
[i
];
1745 && j
+ group_size
[class] <= FIRST_PSEUDO_REGISTER
1746 && HARD_REGNO_MODE_OK (j
, group_mode
[class]))
1748 /* Check each reg in the sequence. */
1749 for (k
= 0; k
< group_size
[class]; k
++)
1750 if (! (spill_reg_order
[j
+ k
] < 0
1751 && ! TEST_HARD_REG_BIT (bad_spill_regs
, j
+ k
)
1752 && TEST_HARD_REG_BIT (reg_class_contents
[class], j
+ k
)))
1754 /* We got a full sequence, so spill them all. */
1755 if (k
== group_size
[class])
1757 register enum reg_class
*p
;
1758 for (k
= 0; k
< group_size
[class]; k
++)
1761 SET_HARD_REG_BIT (counted_for_groups
, j
+ k
);
1762 for (idx
= 0; idx
< FIRST_PSEUDO_REGISTER
; idx
++)
1763 if (potential_reload_regs
[idx
] == j
+ k
)
1766 |= new_spill_reg (idx
, class,
1767 max_needs
, NULL_PTR
,
1771 /* We have found one that will complete a group,
1772 so count off one group as provided. */
1773 max_groups
[class]--;
1774 p
= reg_class_superclasses
[class];
1775 while (*p
!= LIM_REG_CLASSES
)
1776 max_groups
[(int) *p
++]--;
1782 /* We couldn't find any registers for this reload.
1783 Avoid going into an infinite loop. */
1784 if (i
>= FIRST_PSEUDO_REGISTER
)
1786 /* There are no groups left. */
1787 spill_failure (max_groups_insn
[class]);
1794 /* Now similarly satisfy all need for single registers. */
1796 while (max_needs
[class] > 0 || max_nongroups
[class] > 0)
1798 #ifdef SMALL_REGISTER_CLASSES
1799 /* This should be right for all machines, but only the 386
1800 is known to need it, so this conditional plays safe.
1801 ??? For 2.5, try making this unconditional. */
1802 /* If we spilled enough regs, but they weren't counted
1803 against the non-group need, see if we can count them now.
1804 If so, we can avoid some actual spilling. */
1805 if (max_needs
[class] <= 0 && max_nongroups
[class] > 0)
1806 for (i
= 0; i
< n_spills
; i
++)
1807 if (TEST_HARD_REG_BIT (reg_class_contents
[class],
1809 && !TEST_HARD_REG_BIT (counted_for_groups
,
1811 && !TEST_HARD_REG_BIT (counted_for_nongroups
,
1813 && max_nongroups
[class] > 0)
1815 register enum reg_class
*p
;
1817 SET_HARD_REG_BIT (counted_for_nongroups
, spill_regs
[i
]);
1818 max_nongroups
[class]--;
1819 p
= reg_class_superclasses
[class];
1820 while (*p
!= LIM_REG_CLASSES
)
1821 max_nongroups
[(int) *p
++]--;
1823 if (max_needs
[class] <= 0 && max_nongroups
[class] <= 0)
1827 /* Consider the potential reload regs that aren't
1828 yet in use as reload regs, in order of preference.
1829 Find the most preferred one that's in this class. */
1831 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1832 if (potential_reload_regs
[i
] >= 0
1833 && TEST_HARD_REG_BIT (reg_class_contents
[class],
1834 potential_reload_regs
[i
])
1835 /* If this reg will not be available for groups,
1836 pick one that does not foreclose possible groups.
1837 This is a kludge, and not very general,
1838 but it should be sufficient to make the 386 work,
1839 and the problem should not occur on machines with
1841 && (max_nongroups
[class] == 0
1842 || possible_group_p (potential_reload_regs
[i
], max_groups
)))
1845 /* If we couldn't get a register, try to get one even if we
1846 might foreclose possible groups. This may cause problems
1847 later, but that's better than aborting now, since it is
1848 possible that we will, in fact, be able to form the needed
1849 group even with this allocation. */
1851 if (i
>= FIRST_PSEUDO_REGISTER
1852 && (asm_noperands (max_needs
[class] > 0
1853 ? max_needs_insn
[class]
1854 : max_nongroups_insn
[class])
1856 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1857 if (potential_reload_regs
[i
] >= 0
1858 && TEST_HARD_REG_BIT (reg_class_contents
[class],
1859 potential_reload_regs
[i
]))
1862 /* I should be the index in potential_reload_regs
1863 of the new reload reg we have found. */
1865 if (i
>= FIRST_PSEUDO_REGISTER
)
1867 /* There are no possible registers left to spill. */
1868 spill_failure (max_needs
[class] > 0 ? max_needs_insn
[class]
1869 : max_nongroups_insn
[class]);
1875 |= new_spill_reg (i
, class, max_needs
, max_nongroups
,
1881 /* If global-alloc was run, notify it of any register eliminations we have
1884 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1885 if (ep
->can_eliminate
)
1886 mark_elimination (ep
->from
, ep
->to
);
1888 /* Insert code to save and restore call-clobbered hard regs
1889 around calls. Tell if what mode to use so that we will process
1890 those insns in reload_as_needed if we have to. */
1892 if (caller_save_needed
)
1893 save_call_clobbered_regs (num_eliminable
? QImode
1894 : caller_save_spill_class
!= NO_REGS
? HImode
1897 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1898 If that insn didn't set the register (i.e., it copied the register to
1899 memory), just delete that insn instead of the equivalencing insn plus
1900 anything now dead. If we call delete_dead_insn on that insn, we may
1901 delete the insn that actually sets the register if the register die
1902 there and that is incorrect. */
1904 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1905 if (reg_renumber
[i
] < 0 && reg_equiv_init
[i
] != 0
1906 && GET_CODE (reg_equiv_init
[i
]) != NOTE
)
1908 if (reg_set_p (regno_reg_rtx
[i
], PATTERN (reg_equiv_init
[i
])))
1909 delete_dead_insn (reg_equiv_init
[i
]);
1912 PUT_CODE (reg_equiv_init
[i
], NOTE
);
1913 NOTE_SOURCE_FILE (reg_equiv_init
[i
]) = 0;
1914 NOTE_LINE_NUMBER (reg_equiv_init
[i
]) = NOTE_INSN_DELETED
;
1918 /* Use the reload registers where necessary
1919 by generating move instructions to move the must-be-register
1920 values into or out of the reload registers. */
1922 if (something_needs_reloads
|| something_needs_elimination
1923 || (caller_save_needed
&& num_eliminable
)
1924 || caller_save_spill_class
!= NO_REGS
)
1925 reload_as_needed (first
, global
);
1927 /* If we were able to eliminate the frame pointer, show that it is no
1928 longer live at the start of any basic block. If it ls live by
1929 virtue of being in a pseudo, that pseudo will be marked live
1930 and hence the frame pointer will be known to be live via that
1933 if (! frame_pointer_needed
)
1934 for (i
= 0; i
< n_basic_blocks
; i
++)
1935 basic_block_live_at_start
[i
][HARD_FRAME_POINTER_REGNUM
/ REGSET_ELT_BITS
]
1936 &= ~ ((REGSET_ELT_TYPE
) 1 << (HARD_FRAME_POINTER_REGNUM
1937 % REGSET_ELT_BITS
));
1939 /* Come here (with failure set nonzero) if we can't get enough spill regs
1940 and we decide not to abort about it. */
1943 reload_in_progress
= 0;
1945 /* Now eliminate all pseudo regs by modifying them into
1946 their equivalent memory references.
1947 The REG-rtx's for the pseudos are modified in place,
1948 so all insns that used to refer to them now refer to memory.
1950 For a reg that has a reg_equiv_address, all those insns
1951 were changed by reloading so that no insns refer to it any longer;
1952 but the DECL_RTL of a variable decl may refer to it,
1953 and if so this causes the debugging info to mention the variable. */
1955 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1959 if (reg_equiv_mem
[i
])
1961 addr
= XEXP (reg_equiv_mem
[i
], 0);
1962 in_struct
= MEM_IN_STRUCT_P (reg_equiv_mem
[i
]);
1964 if (reg_equiv_address
[i
])
1965 addr
= reg_equiv_address
[i
];
1968 if (reg_renumber
[i
] < 0)
1970 rtx reg
= regno_reg_rtx
[i
];
1971 XEXP (reg
, 0) = addr
;
1972 REG_USERVAR_P (reg
) = 0;
1973 MEM_IN_STRUCT_P (reg
) = in_struct
;
1974 PUT_CODE (reg
, MEM
);
1976 else if (reg_equiv_mem
[i
])
1977 XEXP (reg_equiv_mem
[i
], 0) = addr
;
1981 #ifdef PRESERVE_DEATH_INFO_REGNO_P
1982 /* Make a pass over all the insns and remove death notes for things that
1983 are no longer registers or no longer die in the insn (e.g., an input
1984 and output pseudo being tied). */
1986 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1987 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
1991 for (note
= REG_NOTES (insn
); note
; note
= next
)
1993 next
= XEXP (note
, 1);
1994 if (REG_NOTE_KIND (note
) == REG_DEAD
1995 && (GET_CODE (XEXP (note
, 0)) != REG
1996 || reg_set_p (XEXP (note
, 0), PATTERN (insn
))))
1997 remove_note (insn
, note
);
2002 /* Indicate that we no longer have known memory locations or constants. */
2003 reg_equiv_constant
= 0;
2004 reg_equiv_memory_loc
= 0;
2007 free (scratch_list
);
2010 free (scratch_block
);
2016 /* Nonzero if, after spilling reg REGNO for non-groups,
2017 it will still be possible to find a group if we still need one. */
2020 possible_group_p (regno
, max_groups
)
2025 int class = (int) NO_REGS
;
2027 for (i
= 0; i
< (int) N_REG_CLASSES
; i
++)
2028 if (max_groups
[i
] > 0)
2034 if (class == (int) NO_REGS
)
2037 /* Consider each pair of consecutive registers. */
2038 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
- 1; i
++)
2040 /* Ignore pairs that include reg REGNO. */
2041 if (i
== regno
|| i
+ 1 == regno
)
2044 /* Ignore pairs that are outside the class that needs the group.
2045 ??? Here we fail to handle the case where two different classes
2046 independently need groups. But this never happens with our
2047 current machine descriptions. */
2048 if (! (TEST_HARD_REG_BIT (reg_class_contents
[class], i
)
2049 && TEST_HARD_REG_BIT (reg_class_contents
[class], i
+ 1)))
2052 /* A pair of consecutive regs we can still spill does the trick. */
2053 if (spill_reg_order
[i
] < 0 && spill_reg_order
[i
+ 1] < 0
2054 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2055 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1))
2058 /* A pair of one already spilled and one we can spill does it
2059 provided the one already spilled is not otherwise reserved. */
2060 if (spill_reg_order
[i
] < 0
2061 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
)
2062 && spill_reg_order
[i
+ 1] >= 0
2063 && ! TEST_HARD_REG_BIT (counted_for_groups
, i
+ 1)
2064 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, i
+ 1))
2066 if (spill_reg_order
[i
+ 1] < 0
2067 && ! TEST_HARD_REG_BIT (bad_spill_regs
, i
+ 1)
2068 && spill_reg_order
[i
] >= 0
2069 && ! TEST_HARD_REG_BIT (counted_for_groups
, i
)
2070 && ! TEST_HARD_REG_BIT (counted_for_nongroups
, i
))
2077 /* Count any groups that can be formed from the registers recently spilled.
2078 This is done class by class, in order of ascending class number. */
2081 count_possible_groups (group_size
, group_mode
, max_groups
)
2083 enum machine_mode
*group_mode
;
2087 /* Now find all consecutive groups of spilled registers
2088 and mark each group off against the need for such groups.
2089 But don't count them against ordinary need, yet. */
2091 for (i
= 0; i
< N_REG_CLASSES
; i
++)
2092 if (group_size
[i
] > 1)
2097 CLEAR_HARD_REG_SET (new);
2099 /* Make a mask of all the regs that are spill regs in class I. */
2100 for (j
= 0; j
< n_spills
; j
++)
2101 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], spill_regs
[j
])
2102 && ! TEST_HARD_REG_BIT (counted_for_groups
, spill_regs
[j
])
2103 && ! TEST_HARD_REG_BIT (counted_for_nongroups
,
2105 SET_HARD_REG_BIT (new, spill_regs
[j
]);
2107 /* Find each consecutive group of them. */
2108 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
&& max_groups
[i
] > 0; j
++)
2109 if (TEST_HARD_REG_BIT (new, j
)
2110 && j
+ group_size
[i
] <= FIRST_PSEUDO_REGISTER
2111 /* Next line in case group-mode for this class
2112 demands an even-odd pair. */
2113 && HARD_REGNO_MODE_OK (j
, group_mode
[i
]))
2116 for (k
= 1; k
< group_size
[i
]; k
++)
2117 if (! TEST_HARD_REG_BIT (new, j
+ k
))
2119 if (k
== group_size
[i
])
2121 /* We found a group. Mark it off against this class's
2122 need for groups, and against each superclass too. */
2123 register enum reg_class
*p
;
2125 p
= reg_class_superclasses
[i
];
2126 while (*p
!= LIM_REG_CLASSES
)
2127 max_groups
[(int) *p
++]--;
2128 /* Don't count these registers again. */
2129 for (k
= 0; k
< group_size
[i
]; k
++)
2130 SET_HARD_REG_BIT (counted_for_groups
, j
+ k
);
2132 /* Skip to the last reg in this group. When j is incremented
2133 above, it will then point to the first reg of the next
2141 /* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is
2142 another mode that needs to be reloaded for the same register class CLASS.
2143 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail.
2144 ALLOCATE_MODE will never be smaller than OTHER_MODE.
2146 This code used to also fail if any reg in CLASS allows OTHER_MODE but not
2147 ALLOCATE_MODE. This test is unnecessary, because we will never try to put
2148 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this
2149 causes unnecessary failures on machines requiring alignment of register
2150 groups when the two modes are different sizes, because the larger mode has
2151 more strict alignment rules than the smaller mode. */
2154 modes_equiv_for_class_p (allocate_mode
, other_mode
, class)
2155 enum machine_mode allocate_mode
, other_mode
;
2156 enum reg_class
class;
2159 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
2161 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
)
2162 && HARD_REGNO_MODE_OK (regno
, allocate_mode
)
2163 && ! HARD_REGNO_MODE_OK (regno
, other_mode
))
2169 /* Handle the failure to find a register to spill.
2170 INSN should be one of the insns which needed this particular spill reg. */
2173 spill_failure (insn
)
2176 if (asm_noperands (PATTERN (insn
)) >= 0)
2177 error_for_asm (insn
, "`asm' needs too many reloads");
2182 /* Add a new register to the tables of available spill-registers
2183 (as well as spilling all pseudos allocated to the register).
2184 I is the index of this register in potential_reload_regs.
2185 CLASS is the regclass whose need is being satisfied.
2186 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs,
2187 so that this register can count off against them.
2188 MAX_NONGROUPS is 0 if this register is part of a group.
2189 GLOBAL and DUMPFILE are the same as the args that `reload' got. */
2192 new_spill_reg (i
, class, max_needs
, max_nongroups
, global
, dumpfile
)
2200 register enum reg_class
*p
;
2202 int regno
= potential_reload_regs
[i
];
2204 if (i
>= FIRST_PSEUDO_REGISTER
)
2205 abort (); /* Caller failed to find any register. */
2207 if (fixed_regs
[regno
] || TEST_HARD_REG_BIT (forbidden_regs
, regno
))
2208 fatal ("fixed or forbidden register was spilled.\n\
2209 This may be due to a compiler bug or to impossible asm statements.");
2211 /* Make reg REGNO an additional reload reg. */
2213 potential_reload_regs
[i
] = -1;
2214 spill_regs
[n_spills
] = regno
;
2215 spill_reg_order
[regno
] = n_spills
;
2217 fprintf (dumpfile
, "Spilling reg %d.\n", spill_regs
[n_spills
]);
2219 /* Clear off the needs we just satisfied. */
2222 p
= reg_class_superclasses
[class];
2223 while (*p
!= LIM_REG_CLASSES
)
2224 max_needs
[(int) *p
++]--;
2226 if (max_nongroups
&& max_nongroups
[class] > 0)
2228 SET_HARD_REG_BIT (counted_for_nongroups
, regno
);
2229 max_nongroups
[class]--;
2230 p
= reg_class_superclasses
[class];
2231 while (*p
!= LIM_REG_CLASSES
)
2232 max_nongroups
[(int) *p
++]--;
2235 /* Spill every pseudo reg that was allocated to this reg
2236 or to something that overlaps this reg. */
2238 val
= spill_hard_reg (spill_regs
[n_spills
], global
, dumpfile
, 0);
2240 /* If there are some registers still to eliminate and this register
2241 wasn't ever used before, additional stack space may have to be
2242 allocated to store this register. Thus, we may have changed the offset
2243 between the stack and frame pointers, so mark that something has changed.
2244 (If new pseudos were spilled, thus requiring more space, VAL would have
2245 been set non-zero by the call to spill_hard_reg above since additional
2246 reloads may be needed in that case.
2248 One might think that we need only set VAL to 1 if this is a call-used
2249 register. However, the set of registers that must be saved by the
2250 prologue is not identical to the call-used set. For example, the
2251 register used by the call insn for the return PC is a call-used register,
2252 but must be saved by the prologue. */
2253 if (num_eliminable
&& ! regs_ever_live
[spill_regs
[n_spills
]])
2256 regs_ever_live
[spill_regs
[n_spills
]] = 1;
2262 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2263 data that is dead in INSN. */
2266 delete_dead_insn (insn
)
2269 rtx prev
= prev_real_insn (insn
);
2272 /* If the previous insn sets a register that dies in our insn, delete it
2274 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
2275 && (prev_dest
= SET_DEST (PATTERN (prev
)), GET_CODE (prev_dest
) == REG
)
2276 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2277 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
)))
2278 delete_dead_insn (prev
);
2280 PUT_CODE (insn
, NOTE
);
2281 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2282 NOTE_SOURCE_FILE (insn
) = 0;
2285 /* Modify the home of pseudo-reg I.
2286 The new home is present in reg_renumber[I].
2288 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2289 or it may be -1, meaning there is none or it is not relevant.
2290 This is used so that all pseudos spilled from a given hard reg
2291 can share one stack slot. */
2294 alter_reg (i
, from_reg
)
2298 /* When outputting an inline function, this can happen
2299 for a reg that isn't actually used. */
2300 if (regno_reg_rtx
[i
] == 0)
2303 /* If the reg got changed to a MEM at rtl-generation time,
2305 if (GET_CODE (regno_reg_rtx
[i
]) != REG
)
2308 /* Modify the reg-rtx to contain the new hard reg
2309 number or else to contain its pseudo reg number. */
2310 REGNO (regno_reg_rtx
[i
])
2311 = reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
;
2313 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2314 allocate a stack slot for it. */
2316 if (reg_renumber
[i
] < 0
2317 && reg_n_refs
[i
] > 0
2318 && reg_equiv_constant
[i
] == 0
2319 && reg_equiv_memory_loc
[i
] == 0)
2322 int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2323 int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2326 /* Each pseudo reg has an inherent size which comes from its own mode,
2327 and a total size which provides room for paradoxical subregs
2328 which refer to the pseudo reg in wider modes.
2330 We can use a slot already allocated if it provides both
2331 enough inherent space and enough total space.
2332 Otherwise, we allocate a new slot, making sure that it has no less
2333 inherent space, and no less total space, then the previous slot. */
2336 /* No known place to spill from => no slot to reuse. */
2337 x
= assign_stack_local (GET_MODE (regno_reg_rtx
[i
]), total_size
, -1);
2338 #if BYTES_BIG_ENDIAN
2339 /* Cancel the big-endian correction done in assign_stack_local.
2340 Get the address of the beginning of the slot.
2341 This is so we can do a big-endian correction unconditionally
2343 adjust
= inherent_size
- total_size
;
2346 /* Reuse a stack slot if possible. */
2347 else if (spill_stack_slot
[from_reg
] != 0
2348 && spill_stack_slot_width
[from_reg
] >= total_size
2349 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2351 x
= spill_stack_slot
[from_reg
];
2352 /* Allocate a bigger slot. */
2355 /* Compute maximum size needed, both for inherent size
2356 and for total size. */
2357 enum machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2358 if (spill_stack_slot
[from_reg
])
2360 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2362 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2363 if (spill_stack_slot_width
[from_reg
] > total_size
)
2364 total_size
= spill_stack_slot_width
[from_reg
];
2366 /* Make a slot with that size. */
2367 x
= assign_stack_local (mode
, total_size
, -1);
2368 #if BYTES_BIG_ENDIAN
2369 /* Cancel the big-endian correction done in assign_stack_local.
2370 Get the address of the beginning of the slot.
2371 This is so we can do a big-endian correction unconditionally
2373 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2375 spill_stack_slot
[from_reg
] = x
;
2376 spill_stack_slot_width
[from_reg
] = total_size
;
2379 #if BYTES_BIG_ENDIAN
2380 /* On a big endian machine, the "address" of the slot
2381 is the address of the low part that fits its inherent mode. */
2382 if (inherent_size
< total_size
)
2383 adjust
+= (total_size
- inherent_size
);
2384 #endif /* BYTES_BIG_ENDIAN */
2386 /* If we have any adjustment to make, or if the stack slot is the
2387 wrong mode, make a new stack slot. */
2388 if (adjust
!= 0 || GET_MODE (x
) != GET_MODE (regno_reg_rtx
[i
]))
2390 x
= gen_rtx (MEM
, GET_MODE (regno_reg_rtx
[i
]),
2391 plus_constant (XEXP (x
, 0), adjust
));
2392 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (regno_reg_rtx
[i
]);
2395 /* Save the stack slot for later. */
2396 reg_equiv_memory_loc
[i
] = x
;
2400 /* Mark the slots in regs_ever_live for the hard regs
2401 used by pseudo-reg number REGNO. */
2404 mark_home_live (regno
)
2407 register int i
, lim
;
2408 i
= reg_renumber
[regno
];
2411 lim
= i
+ HARD_REGNO_NREGS (i
, PSEUDO_REGNO_MODE (regno
));
2413 regs_ever_live
[i
++] = 1;
2416 /* Mark the registers used in SCRATCH as being live. */
2419 mark_scratch_live (scratch
)
2423 int regno
= REGNO (scratch
);
2424 int lim
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (scratch
));
2426 for (i
= regno
; i
< lim
; i
++)
2427 regs_ever_live
[i
] = 1;
2430 /* This function handles the tracking of elimination offsets around branches.
2432 X is a piece of RTL being scanned.
2434 INSN is the insn that it came from, if any.
2436 INITIAL_P is non-zero if we are to set the offset to be the initial
2437 offset and zero if we are setting the offset of the label to be the
2441 set_label_offsets (x
, insn
, initial_p
)
2446 enum rtx_code code
= GET_CODE (x
);
2449 struct elim_table
*p
;
2454 if (LABEL_REF_NONLOCAL_P (x
))
2459 /* ... fall through ... */
2462 /* If we know nothing about this label, set the desired offsets. Note
2463 that this sets the offset at a label to be the offset before a label
2464 if we don't know anything about the label. This is not correct for
2465 the label after a BARRIER, but is the best guess we can make. If
2466 we guessed wrong, we will suppress an elimination that might have
2467 been possible had we been able to guess correctly. */
2469 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
)])
2471 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2472 offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2473 = (initial_p
? reg_eliminate
[i
].initial_offset
2474 : reg_eliminate
[i
].offset
);
2475 offsets_known_at
[CODE_LABEL_NUMBER (x
)] = 1;
2478 /* Otherwise, if this is the definition of a label and it is
2479 preceded by a BARRIER, set our offsets to the known offset of
2483 && (tem
= prev_nonnote_insn (insn
)) != 0
2484 && GET_CODE (tem
) == BARRIER
)
2486 num_not_at_initial_offset
= 0;
2487 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2489 reg_eliminate
[i
].offset
= reg_eliminate
[i
].previous_offset
2490 = offsets_at
[CODE_LABEL_NUMBER (x
)][i
];
2491 if (reg_eliminate
[i
].can_eliminate
2492 && (reg_eliminate
[i
].offset
2493 != reg_eliminate
[i
].initial_offset
))
2494 num_not_at_initial_offset
++;
2499 /* If neither of the above cases is true, compare each offset
2500 with those previously recorded and suppress any eliminations
2501 where the offsets disagree. */
2503 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2504 if (offsets_at
[CODE_LABEL_NUMBER (x
)][i
]
2505 != (initial_p
? reg_eliminate
[i
].initial_offset
2506 : reg_eliminate
[i
].offset
))
2507 reg_eliminate
[i
].can_eliminate
= 0;
2512 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2514 /* ... fall through ... */
2518 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2519 and hence must have all eliminations at their initial offsets. */
2520 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2521 if (REG_NOTE_KIND (tem
) == REG_LABEL
)
2522 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2527 /* Each of the labels in the address vector must be at their initial
2528 offsets. We want the first first for ADDR_VEC and the second
2529 field for ADDR_DIFF_VEC. */
2531 for (i
= 0; i
< XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2532 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2537 /* We only care about setting PC. If the source is not RETURN,
2538 IF_THEN_ELSE, or a label, disable any eliminations not at
2539 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2540 isn't one of those possibilities. For branches to a label,
2541 call ourselves recursively.
2543 Note that this can disable elimination unnecessarily when we have
2544 a non-local goto since it will look like a non-constant jump to
2545 someplace in the current function. This isn't a significant
2546 problem since such jumps will normally be when all elimination
2547 pairs are back to their initial offsets. */
2549 if (SET_DEST (x
) != pc_rtx
)
2552 switch (GET_CODE (SET_SRC (x
)))
2559 set_label_offsets (XEXP (SET_SRC (x
), 0), insn
, initial_p
);
2563 tem
= XEXP (SET_SRC (x
), 1);
2564 if (GET_CODE (tem
) == LABEL_REF
)
2565 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2566 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2569 tem
= XEXP (SET_SRC (x
), 2);
2570 if (GET_CODE (tem
) == LABEL_REF
)
2571 set_label_offsets (XEXP (tem
, 0), insn
, initial_p
);
2572 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2577 /* If we reach here, all eliminations must be at their initial
2578 offset because we are doing a jump to a variable address. */
2579 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2580 if (p
->offset
!= p
->initial_offset
)
2581 p
->can_eliminate
= 0;
2585 /* Used for communication between the next two function to properly share
2586 the vector for an ASM_OPERANDS. */
2588 static struct rtvec_def
*old_asm_operands_vec
, *new_asm_operands_vec
;
2590 /* Scan X and replace any eliminable registers (such as fp) with a
2591 replacement (such as sp), plus an offset.
2593 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2594 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2595 MEM, we are allowed to replace a sum of a register and the constant zero
2596 with the register, which we cannot do outside a MEM. In addition, we need
2597 to record the fact that a register is referenced outside a MEM.
2599 If INSN is an insn, it is the insn containing X. If we replace a REG
2600 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2601 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2602 that the REG is being modified.
2604 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2605 That's used when we eliminate in expressions stored in notes.
2606 This means, do not set ref_outside_mem even if the reference
2609 If we see a modification to a register we know about, take the
2610 appropriate action (see case SET, below).
2612 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2613 replacements done assuming all offsets are at their initial values. If
2614 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2615 encounter, return the actual location so that find_reloads will do
2616 the proper thing. */
2619 eliminate_regs (x
, mem_mode
, insn
)
2621 enum machine_mode mem_mode
;
2624 enum rtx_code code
= GET_CODE (x
);
2625 struct elim_table
*ep
;
2650 /* First handle the case where we encounter a bare register that
2651 is eliminable. Replace it with a PLUS. */
2652 if (regno
< FIRST_PSEUDO_REGISTER
)
2654 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2656 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2659 /* Refs inside notes don't count for this purpose. */
2660 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2661 || GET_CODE (insn
) == INSN_LIST
)))
2662 ep
->ref_outside_mem
= 1;
2663 return plus_constant (ep
->to_rtx
, ep
->previous_offset
);
2667 else if (reg_equiv_memory_loc
&& reg_equiv_memory_loc
[regno
]
2668 && (reg_equiv_address
[regno
] || num_not_at_initial_offset
))
2670 /* In this case, find_reloads would attempt to either use an
2671 incorrect address (if something is not at its initial offset)
2672 or substitute an replaced address into an insn (which loses
2673 if the offset is changed by some later action). So we simply
2674 return the replaced stack slot (assuming it is changed by
2675 elimination) and ignore the fact that this is actually a
2676 reference to the pseudo. Ensure we make a copy of the
2677 address in case it is shared. */
2678 new = eliminate_regs (reg_equiv_memory_loc
[regno
],
2679 mem_mode
, NULL_RTX
);
2680 if (new != reg_equiv_memory_loc
[regno
])
2682 cannot_omit_stores
[regno
] = 1;
2683 return copy_rtx (new);
2689 /* If this is the sum of an eliminable register and a constant, rework
2691 if (GET_CODE (XEXP (x
, 0)) == REG
2692 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2693 && CONSTANT_P (XEXP (x
, 1)))
2695 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2697 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2700 ep
->ref_outside_mem
= 1;
2702 /* The only time we want to replace a PLUS with a REG (this
2703 occurs when the constant operand of the PLUS is the negative
2704 of the offset) is when we are inside a MEM. We won't want
2705 to do so at other times because that would change the
2706 structure of the insn in a way that reload can't handle.
2707 We special-case the commonest situation in
2708 eliminate_regs_in_insn, so just replace a PLUS with a
2709 PLUS here, unless inside a MEM. */
2710 if (mem_mode
!= 0 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2711 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2714 return gen_rtx (PLUS
, Pmode
, ep
->to_rtx
,
2715 plus_constant (XEXP (x
, 1),
2716 ep
->previous_offset
));
2719 /* If the register is not eliminable, we are done since the other
2720 operand is a constant. */
2724 /* If this is part of an address, we want to bring any constant to the
2725 outermost PLUS. We will do this by doing register replacement in
2726 our operands and seeing if a constant shows up in one of them.
2728 We assume here this is part of an address (or a "load address" insn)
2729 since an eliminable register is not likely to appear in any other
2732 If we have (plus (eliminable) (reg)), we want to produce
2733 (plus (plus (replacement) (reg) (const))). If this was part of a
2734 normal add insn, (plus (replacement) (reg)) will be pushed as a
2735 reload. This is the desired action. */
2738 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, NULL_RTX
);
2739 rtx new1
= eliminate_regs (XEXP (x
, 1), mem_mode
, NULL_RTX
);
2741 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2743 /* If one side is a PLUS and the other side is a pseudo that
2744 didn't get a hard register but has a reg_equiv_constant,
2745 we must replace the constant here since it may no longer
2746 be in the position of any operand. */
2747 if (GET_CODE (new0
) == PLUS
&& GET_CODE (new1
) == REG
2748 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2749 && reg_renumber
[REGNO (new1
)] < 0
2750 && reg_equiv_constant
!= 0
2751 && reg_equiv_constant
[REGNO (new1
)] != 0)
2752 new1
= reg_equiv_constant
[REGNO (new1
)];
2753 else if (GET_CODE (new1
) == PLUS
&& GET_CODE (new0
) == REG
2754 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2755 && reg_renumber
[REGNO (new0
)] < 0
2756 && reg_equiv_constant
[REGNO (new0
)] != 0)
2757 new0
= reg_equiv_constant
[REGNO (new0
)];
2759 new = form_sum (new0
, new1
);
2761 /* As above, if we are not inside a MEM we do not want to
2762 turn a PLUS into something else. We might try to do so here
2763 for an addition of 0 if we aren't optimizing. */
2764 if (! mem_mode
&& GET_CODE (new) != PLUS
)
2765 return gen_rtx (PLUS
, GET_MODE (x
), new, const0_rtx
);
2773 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2776 new = eliminate_regs (XEXP (x
, 0), mem_mode
, NULL_RTX
);
2777 if (new != XEXP (x
, 0))
2778 x
= gen_rtx (EXPR_LIST
, REG_NOTE_KIND (x
), new, XEXP (x
, 1));
2781 /* ... fall through ... */
2784 /* Now do eliminations in the rest of the chain. If this was
2785 an EXPR_LIST, this might result in allocating more memory than is
2786 strictly needed, but it simplifies the code. */
2789 new = eliminate_regs (XEXP (x
, 1), mem_mode
, NULL_RTX
);
2790 if (new != XEXP (x
, 1))
2791 return gen_rtx (INSN_LIST
, GET_MODE (x
), XEXP (x
, 0), new);
2799 case DIV
: case UDIV
:
2800 case MOD
: case UMOD
:
2801 case AND
: case IOR
: case XOR
:
2802 case LSHIFT
: case ASHIFT
: case ROTATE
:
2803 case ASHIFTRT
: case LSHIFTRT
: case ROTATERT
:
2805 case GE
: case GT
: case GEU
: case GTU
:
2806 case LE
: case LT
: case LEU
: case LTU
:
2808 rtx new0
= eliminate_regs (XEXP (x
, 0), mem_mode
, NULL_RTX
);
2810 = XEXP (x
, 1) ? eliminate_regs (XEXP (x
, 1), mem_mode
, NULL_RTX
) : 0;
2812 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2813 return gen_rtx (code
, GET_MODE (x
), new0
, new1
);
2821 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2822 if (ep
->to_rtx
== XEXP (x
, 0))
2824 int size
= GET_MODE_SIZE (mem_mode
);
2826 /* If more bytes than MEM_MODE are pushed, account for them. */
2827 #ifdef PUSH_ROUNDING
2828 if (ep
->to_rtx
== stack_pointer_rtx
)
2829 size
= PUSH_ROUNDING (size
);
2831 if (code
== PRE_DEC
|| code
== POST_DEC
)
2837 /* Fall through to generic unary operation case. */
2839 case STRICT_LOW_PART
:
2841 case SIGN_EXTEND
: case ZERO_EXTEND
:
2842 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2843 case FLOAT
: case FIX
:
2844 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2848 new = eliminate_regs (XEXP (x
, 0), mem_mode
, NULL_RTX
);
2849 if (new != XEXP (x
, 0))
2850 return gen_rtx (code
, GET_MODE (x
), new);
2854 /* Similar to above processing, but preserve SUBREG_WORD.
2855 Convert (subreg (mem)) to (mem) if not paradoxical.
2856 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2857 pseudo didn't get a hard reg, we must replace this with the
2858 eliminated version of the memory location because push_reloads
2859 may do the replacement in certain circumstances. */
2860 if (GET_CODE (SUBREG_REG (x
)) == REG
2861 && (GET_MODE_SIZE (GET_MODE (x
))
2862 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
2863 && reg_equiv_memory_loc
!= 0
2864 && reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))] != 0)
2866 new = eliminate_regs (reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))],
2867 mem_mode
, NULL_RTX
);
2869 /* If we didn't change anything, we must retain the pseudo. */
2870 if (new == reg_equiv_memory_loc
[REGNO (SUBREG_REG (x
))])
2873 /* Otherwise, ensure NEW isn't shared in case we have to reload
2875 new = copy_rtx (new);
2878 new = eliminate_regs (SUBREG_REG (x
), mem_mode
, NULL_RTX
);
2880 if (new != XEXP (x
, 0))
2882 if (GET_CODE (new) == MEM
2883 && (GET_MODE_SIZE (GET_MODE (x
))
2884 <= GET_MODE_SIZE (GET_MODE (new)))
2885 #ifdef LOAD_EXTEND_OP
2886 /* On these machines we will be reloading what is
2887 inside the SUBREG if it originally was a pseudo and
2888 the inner and outer modes are both a word or
2889 smaller. So leave the SUBREG then. */
2890 && ! (GET_CODE (SUBREG_REG (x
)) == REG
2891 && GET_MODE_SIZE (GET_MODE (x
)) <= UNITS_PER_WORD
2892 && GET_MODE_SIZE (GET_MODE (new)) <= UNITS_PER_WORD
)
2896 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
2897 enum machine_mode mode
= GET_MODE (x
);
2899 #if BYTES_BIG_ENDIAN
2900 offset
+= (MIN (UNITS_PER_WORD
,
2901 GET_MODE_SIZE (GET_MODE (new)))
2902 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
2905 PUT_MODE (new, mode
);
2906 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset
);
2910 return gen_rtx (SUBREG
, GET_MODE (x
), new, SUBREG_WORD (x
));
2916 /* If clobbering a register that is the replacement register for an
2917 elimination we still think can be performed, note that it cannot
2918 be performed. Otherwise, we need not be concerned about it. */
2919 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2920 if (ep
->to_rtx
== XEXP (x
, 0))
2921 ep
->can_eliminate
= 0;
2923 new = eliminate_regs (XEXP (x
, 0), mem_mode
, NULL_RTX
);
2924 if (new != XEXP (x
, 0))
2925 return gen_rtx (code
, GET_MODE (x
), new);
2931 /* Properly handle sharing input and constraint vectors. */
2932 if (ASM_OPERANDS_INPUT_VEC (x
) != old_asm_operands_vec
)
2934 /* When we come to a new vector not seen before,
2935 scan all its elements; keep the old vector if none
2936 of them changes; otherwise, make a copy. */
2937 old_asm_operands_vec
= ASM_OPERANDS_INPUT_VEC (x
);
2938 temp_vec
= (rtx
*) alloca (XVECLEN (x
, 3) * sizeof (rtx
));
2939 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
2940 temp_vec
[i
] = eliminate_regs (ASM_OPERANDS_INPUT (x
, i
),
2941 mem_mode
, NULL_RTX
);
2943 for (i
= 0; i
< ASM_OPERANDS_INPUT_LENGTH (x
); i
++)
2944 if (temp_vec
[i
] != ASM_OPERANDS_INPUT (x
, i
))
2947 if (i
== ASM_OPERANDS_INPUT_LENGTH (x
))
2948 new_asm_operands_vec
= old_asm_operands_vec
;
2950 new_asm_operands_vec
2951 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x
), temp_vec
);
2954 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */
2955 if (new_asm_operands_vec
== old_asm_operands_vec
)
2958 new = gen_rtx (ASM_OPERANDS
, VOIDmode
, ASM_OPERANDS_TEMPLATE (x
),
2959 ASM_OPERANDS_OUTPUT_CONSTRAINT (x
),
2960 ASM_OPERANDS_OUTPUT_IDX (x
), new_asm_operands_vec
,
2961 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x
),
2962 ASM_OPERANDS_SOURCE_FILE (x
),
2963 ASM_OPERANDS_SOURCE_LINE (x
));
2964 new->volatil
= x
->volatil
;
2969 /* Check for setting a register that we know about. */
2970 if (GET_CODE (SET_DEST (x
)) == REG
)
2972 /* See if this is setting the replacement register for an
2975 If DEST is the hard frame pointer, we do nothing because we
2976 assume that all assignments to the frame pointer are for
2977 non-local gotos and are being done at a time when they are valid
2978 and do not disturb anything else. Some machines want to
2979 eliminate a fake argument pointer (or even a fake frame pointer)
2980 with either the real frame or the stack pointer. Assignments to
2981 the hard frame pointer must not prevent this elimination. */
2983 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2985 if (ep
->to_rtx
== SET_DEST (x
)
2986 && SET_DEST (x
) != hard_frame_pointer_rtx
)
2988 /* If it is being incremented, adjust the offset. Otherwise,
2989 this elimination can't be done. */
2990 rtx src
= SET_SRC (x
);
2992 if (GET_CODE (src
) == PLUS
2993 && XEXP (src
, 0) == SET_DEST (x
)
2994 && GET_CODE (XEXP (src
, 1)) == CONST_INT
)
2995 ep
->offset
-= INTVAL (XEXP (src
, 1));
2997 ep
->can_eliminate
= 0;
3000 /* Now check to see we are assigning to a register that can be
3001 eliminated. If so, it must be as part of a PARALLEL, since we
3002 will not have been called if this is a single SET. So indicate
3003 that we can no longer eliminate this reg. */
3004 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3006 if (ep
->from_rtx
== SET_DEST (x
) && ep
->can_eliminate
)
3007 ep
->can_eliminate
= 0;
3010 /* Now avoid the loop below in this common case. */
3012 rtx new0
= eliminate_regs (SET_DEST (x
), 0, NULL_RTX
);
3013 rtx new1
= eliminate_regs (SET_SRC (x
), 0, NULL_RTX
);
3015 /* If SET_DEST changed from a REG to a MEM and INSN is an insn,
3016 write a CLOBBER insn. */
3017 if (GET_CODE (SET_DEST (x
)) == REG
&& GET_CODE (new0
) == MEM
3018 && insn
!= 0 && GET_CODE (insn
) != EXPR_LIST
3019 && GET_CODE (insn
) != INSN_LIST
)
3020 emit_insn_after (gen_rtx (CLOBBER
, VOIDmode
, SET_DEST (x
)), insn
);
3022 if (new0
!= SET_DEST (x
) || new1
!= SET_SRC (x
))
3023 return gen_rtx (SET
, VOIDmode
, new0
, new1
);
3029 /* Our only special processing is to pass the mode of the MEM to our
3030 recursive call and copy the flags. While we are here, handle this
3031 case more efficiently. */
3032 new = eliminate_regs (XEXP (x
, 0), GET_MODE (x
), NULL_RTX
);
3033 if (new != XEXP (x
, 0))
3035 new = gen_rtx (MEM
, GET_MODE (x
), new);
3036 new->volatil
= x
->volatil
;
3037 new->unchanging
= x
->unchanging
;
3038 new->in_struct
= x
->in_struct
;
3045 /* Process each of our operands recursively. If any have changed, make a
3047 fmt
= GET_RTX_FORMAT (code
);
3048 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3052 new = eliminate_regs (XEXP (x
, i
), mem_mode
, NULL_RTX
);
3053 if (new != XEXP (x
, i
) && ! copied
)
3055 rtx new_x
= rtx_alloc (code
);
3056 bcopy (x
, new_x
, (sizeof (*new_x
) - sizeof (new_x
->fld
)
3057 + (sizeof (new_x
->fld
[0])
3058 * GET_RTX_LENGTH (code
))));
3064 else if (*fmt
== 'E')
3067 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3069 new = eliminate_regs (XVECEXP (x
, i
, j
), mem_mode
, insn
);
3070 if (new != XVECEXP (x
, i
, j
) && ! copied_vec
)
3072 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
3073 &XVECEXP (x
, i
, 0));
3076 rtx new_x
= rtx_alloc (code
);
3077 bcopy (x
, new_x
, (sizeof (*new_x
) - sizeof (new_x
->fld
)
3078 + (sizeof (new_x
->fld
[0])
3079 * GET_RTX_LENGTH (code
))));
3083 XVEC (x
, i
) = new_v
;
3086 XVECEXP (x
, i
, j
) = new;
3094 /* Scan INSN and eliminate all eliminable registers in it.
3096 If REPLACE is nonzero, do the replacement destructively. Also
3097 delete the insn as dead it if it is setting an eliminable register.
3099 If REPLACE is zero, do all our allocations in reload_obstack.
3101 If no eliminations were done and this insn doesn't require any elimination
3102 processing (these are not identical conditions: it might be updating sp,
3103 but not referencing fp; this needs to be seen during reload_as_needed so
3104 that the offset between fp and sp can be taken into consideration), zero
3105 is returned. Otherwise, 1 is returned. */
3108 eliminate_regs_in_insn (insn
, replace
)
3112 rtx old_body
= PATTERN (insn
);
3115 struct elim_table
*ep
;
3118 push_obstacks (&reload_obstack
, &reload_obstack
);
3120 if (GET_CODE (old_body
) == SET
&& GET_CODE (SET_DEST (old_body
)) == REG
3121 && REGNO (SET_DEST (old_body
)) < FIRST_PSEUDO_REGISTER
)
3123 /* Check for setting an eliminable register. */
3124 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3125 if (ep
->from_rtx
== SET_DEST (old_body
) && ep
->can_eliminate
)
3127 /* In this case this insn isn't serving a useful purpose. We
3128 will delete it in reload_as_needed once we know that this
3129 elimination is, in fact, being done.
3131 If REPLACE isn't set, we can't delete this insn, but neededn't
3132 process it since it won't be used unless something changes. */
3134 delete_dead_insn (insn
);
3139 /* Check for (set (reg) (plus (reg from) (offset))) where the offset
3140 in the insn is the negative of the offset in FROM. Substitute
3141 (set (reg) (reg to)) for the insn and change its code.
3143 We have to do this here, rather than in eliminate_regs, do that we can
3144 change the insn code. */
3146 if (GET_CODE (SET_SRC (old_body
)) == PLUS
3147 && GET_CODE (XEXP (SET_SRC (old_body
), 0)) == REG
3148 && GET_CODE (XEXP (SET_SRC (old_body
), 1)) == CONST_INT
)
3149 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3151 if (ep
->from_rtx
== XEXP (SET_SRC (old_body
), 0)
3152 && ep
->can_eliminate
)
3154 /* We must stop at the first elimination that will be used.
3155 If this one would replace the PLUS with a REG, do it
3156 now. Otherwise, quit the loop and let eliminate_regs
3157 do its normal replacement. */
3158 if (ep
->offset
== - INTVAL (XEXP (SET_SRC (old_body
), 1)))
3160 PATTERN (insn
) = gen_rtx (SET
, VOIDmode
,
3161 SET_DEST (old_body
), ep
->to_rtx
);
3162 INSN_CODE (insn
) = -1;
3171 old_asm_operands_vec
= 0;
3173 /* Replace the body of this insn with a substituted form. If we changed
3174 something, return non-zero.
3176 If we are replacing a body that was a (set X (plus Y Z)), try to
3177 re-recognize the insn. We do this in case we had a simple addition
3178 but now can do this as a load-address. This saves an insn in this
3181 new_body
= eliminate_regs (old_body
, 0, replace
? insn
: NULL_RTX
);
3182 if (new_body
!= old_body
)
3184 /* If we aren't replacing things permanently and we changed something,
3185 make another copy to ensure that all the RTL is new. Otherwise
3186 things can go wrong if find_reload swaps commutative operands
3187 and one is inside RTL that has been copied while the other is not. */
3189 /* Don't copy an asm_operands because (1) there's no need and (2)
3190 copy_rtx can't do it properly when there are multiple outputs. */
3191 if (! replace
&& asm_noperands (old_body
) < 0)
3192 new_body
= copy_rtx (new_body
);
3194 /* If we had a move insn but now we don't, rerecognize it. */
3195 if ((GET_CODE (old_body
) == SET
&& GET_CODE (SET_SRC (old_body
)) == REG
3196 && (GET_CODE (new_body
) != SET
3197 || GET_CODE (SET_SRC (new_body
)) != REG
))
3198 /* If this was an add insn before, rerecognize. */
3200 (GET_CODE (old_body
) == SET
3201 && GET_CODE (SET_SRC (old_body
)) == PLUS
))
3203 if (! validate_change (insn
, &PATTERN (insn
), new_body
, 0))
3204 /* If recognition fails, store the new body anyway.
3205 It's normal to have recognition failures here
3206 due to bizarre memory addresses; reloading will fix them. */
3207 PATTERN (insn
) = new_body
;
3210 PATTERN (insn
) = new_body
;
3215 /* Loop through all elimination pairs. See if any have changed and
3216 recalculate the number not at initial offset.
3218 Compute the maximum offset (minimum offset if the stack does not
3219 grow downward) for each elimination pair.
3221 We also detect a cases where register elimination cannot be done,
3222 namely, if a register would be both changed and referenced outside a MEM
3223 in the resulting insn since such an insn is often undefined and, even if
3224 not, we cannot know what meaning will be given to it. Note that it is
3225 valid to have a register used in an address in an insn that changes it
3226 (presumably with a pre- or post-increment or decrement).
3228 If anything changes, return nonzero. */
3230 num_not_at_initial_offset
= 0;
3231 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3233 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3234 ep
->can_eliminate
= 0;
3236 ep
->ref_outside_mem
= 0;
3238 if (ep
->previous_offset
!= ep
->offset
)
3241 ep
->previous_offset
= ep
->offset
;
3242 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3243 num_not_at_initial_offset
++;
3245 #ifdef STACK_GROWS_DOWNWARD
3246 ep
->max_offset
= MAX (ep
->max_offset
, ep
->offset
);
3248 ep
->max_offset
= MIN (ep
->max_offset
, ep
->offset
);
3253 /* If we changed something, perform elmination in REG_NOTES. This is
3254 needed even when REPLACE is zero because a REG_DEAD note might refer
3255 to a register that we eliminate and could cause a different number
3256 of spill registers to be needed in the final reload pass than in
3258 if (val
&& REG_NOTES (insn
) != 0)
3259 REG_NOTES (insn
) = eliminate_regs (REG_NOTES (insn
), 0, REG_NOTES (insn
));
3267 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3268 replacement we currently believe is valid, mark it as not eliminable if X
3269 modifies DEST in any way other than by adding a constant integer to it.
3271 If DEST is the frame pointer, we do nothing because we assume that
3272 all assignments to the hard frame pointer are nonlocal gotos and are being
3273 done at a time when they are valid and do not disturb anything else.
3274 Some machines want to eliminate a fake argument pointer with either the
3275 frame or stack pointer. Assignments to the hard frame pointer must not
3276 prevent this elimination.
3278 Called via note_stores from reload before starting its passes to scan
3279 the insns of the function. */
3282 mark_not_eliminable (dest
, x
)
3288 /* A SUBREG of a hard register here is just changing its mode. We should
3289 not see a SUBREG of an eliminable hard register, but check just in
3291 if (GET_CODE (dest
) == SUBREG
)
3292 dest
= SUBREG_REG (dest
);
3294 if (dest
== hard_frame_pointer_rtx
)
3297 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3298 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3299 && (GET_CODE (x
) != SET
3300 || GET_CODE (SET_SRC (x
)) != PLUS
3301 || XEXP (SET_SRC (x
), 0) != dest
3302 || GET_CODE (XEXP (SET_SRC (x
), 1)) != CONST_INT
))
3304 reg_eliminate
[i
].can_eliminate_previous
3305 = reg_eliminate
[i
].can_eliminate
= 0;
3310 /* Kick all pseudos out of hard register REGNO.
3311 If GLOBAL is nonzero, try to find someplace else to put them.
3312 If DUMPFILE is nonzero, log actions taken on that file.
3314 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3315 because we found we can't eliminate some register. In the case, no pseudos
3316 are allowed to be in the register, even if they are only in a block that
3317 doesn't require spill registers, unlike the case when we are spilling this
3318 hard reg to produce another spill register.
3320 Return nonzero if any pseudos needed to be kicked out. */
3323 spill_hard_reg (regno
, global
, dumpfile
, cant_eliminate
)
3329 enum reg_class
class = REGNO_REG_CLASS (regno
);
3330 int something_changed
= 0;
3333 SET_HARD_REG_BIT (forbidden_regs
, regno
);
3335 /* Spill every pseudo reg that was allocated to this reg
3336 or to something that overlaps this reg. */
3338 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3339 if (reg_renumber
[i
] >= 0
3340 && reg_renumber
[i
] <= regno
3342 + HARD_REGNO_NREGS (reg_renumber
[i
],
3343 PSEUDO_REGNO_MODE (i
))
3346 /* If this register belongs solely to a basic block which needed no
3347 spilling of any class that this register is contained in,
3348 leave it be, unless we are spilling this register because
3349 it was a hard register that can't be eliminated. */
3351 if (! cant_eliminate
3352 && basic_block_needs
[0]
3353 && reg_basic_block
[i
] >= 0
3354 && basic_block_needs
[(int) class][reg_basic_block
[i
]] == 0)
3358 for (p
= reg_class_superclasses
[(int) class];
3359 *p
!= LIM_REG_CLASSES
; p
++)
3360 if (basic_block_needs
[(int) *p
][reg_basic_block
[i
]] > 0)
3363 if (*p
== LIM_REG_CLASSES
)
3367 /* Mark it as no longer having a hard register home. */
3368 reg_renumber
[i
] = -1;
3369 /* We will need to scan everything again. */
3370 something_changed
= 1;
3372 retry_global_alloc (i
, forbidden_regs
);
3374 alter_reg (i
, regno
);
3377 if (reg_renumber
[i
] == -1)
3378 fprintf (dumpfile
, " Register %d now on stack.\n\n", i
);
3380 fprintf (dumpfile
, " Register %d now in %d.\n\n",
3381 i
, reg_renumber
[i
]);
3384 for (i
= 0; i
< scratch_list_length
; i
++)
3386 if (scratch_list
[i
] && REGNO (scratch_list
[i
]) == regno
)
3388 if (! cant_eliminate
&& basic_block_needs
[0]
3389 && ! basic_block_needs
[(int) class][scratch_block
[i
]])
3393 for (p
= reg_class_superclasses
[(int) class];
3394 *p
!= LIM_REG_CLASSES
; p
++)
3395 if (basic_block_needs
[(int) *p
][scratch_block
[i
]] > 0)
3398 if (*p
== LIM_REG_CLASSES
)
3401 PUT_CODE (scratch_list
[i
], SCRATCH
);
3402 scratch_list
[i
] = 0;
3403 something_changed
= 1;
3408 return something_changed
;
3411 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3414 scan_paradoxical_subregs (x
)
3419 register enum rtx_code code
= GET_CODE (x
);
3436 if (GET_CODE (SUBREG_REG (x
)) == REG
3437 && GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3438 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
3439 = GET_MODE_SIZE (GET_MODE (x
));
3443 fmt
= GET_RTX_FORMAT (code
);
3444 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3447 scan_paradoxical_subregs (XEXP (x
, i
));
3448 else if (fmt
[i
] == 'E')
3451 for (j
= XVECLEN (x
, i
) - 1; j
>=0; j
--)
3452 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
3458 hard_reg_use_compare (p1
, p2
)
3459 struct hard_reg_n_uses
*p1
, *p2
;
3461 int tem
= p1
->uses
- p2
->uses
;
3462 if (tem
!= 0) return tem
;
3463 /* If regs are equally good, sort by regno,
3464 so that the results of qsort leave nothing to chance. */
3465 return p1
->regno
- p2
->regno
;
3468 /* Choose the order to consider regs for use as reload registers
3469 based on how much trouble would be caused by spilling one.
3470 Store them in order of decreasing preference in potential_reload_regs. */
3473 order_regs_for_reload ()
3479 struct hard_reg_n_uses hard_reg_n_uses
[FIRST_PSEUDO_REGISTER
];
3481 CLEAR_HARD_REG_SET (bad_spill_regs
);
3483 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3484 potential_reload_regs
[i
] = -1;
3486 /* Count number of uses of each hard reg by pseudo regs allocated to it
3487 and then order them by decreasing use. */
3489 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3491 hard_reg_n_uses
[i
].uses
= 0;
3492 hard_reg_n_uses
[i
].regno
= i
;
3495 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
3497 int regno
= reg_renumber
[i
];
3500 int lim
= regno
+ HARD_REGNO_NREGS (regno
, PSEUDO_REGNO_MODE (i
));
3502 hard_reg_n_uses
[regno
++].uses
+= reg_n_refs
[i
];
3504 large
+= reg_n_refs
[i
];
3507 /* Now fixed registers (which cannot safely be used for reloading)
3508 get a very high use count so they will be considered least desirable.
3509 Registers used explicitly in the rtl code are almost as bad. */
3511 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3515 hard_reg_n_uses
[i
].uses
+= 2 * large
+ 2;
3516 SET_HARD_REG_BIT (bad_spill_regs
, i
);
3518 else if (regs_explicitly_used
[i
])
3520 hard_reg_n_uses
[i
].uses
+= large
+ 1;
3521 #ifndef SMALL_REGISTER_CLASSES
3522 /* ??? We are doing this here because of the potential that
3523 bad code may be generated if a register explicitly used in
3524 an insn was used as a spill register for that insn. But
3525 not using these are spill registers may lose on some machine.
3526 We'll have to see how this works out. */
3527 SET_HARD_REG_BIT (bad_spill_regs
, i
);
3531 hard_reg_n_uses
[HARD_FRAME_POINTER_REGNUM
].uses
+= 2 * large
+ 2;
3532 SET_HARD_REG_BIT (bad_spill_regs
, HARD_FRAME_POINTER_REGNUM
);
3534 #ifdef ELIMINABLE_REGS
3535 /* If registers other than the frame pointer are eliminable, mark them as
3537 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3539 hard_reg_n_uses
[reg_eliminate
[i
].from
].uses
+= 2 * large
+ 2;
3540 SET_HARD_REG_BIT (bad_spill_regs
, reg_eliminate
[i
].from
);
3544 /* Prefer registers not so far used, for use in temporary loading.
3545 Among them, if REG_ALLOC_ORDER is defined, use that order.
3546 Otherwise, prefer registers not preserved by calls. */
3548 #ifdef REG_ALLOC_ORDER
3549 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3551 int regno
= reg_alloc_order
[i
];
3553 if (hard_reg_n_uses
[regno
].uses
== 0)
3554 potential_reload_regs
[o
++] = regno
;
3557 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3559 if (hard_reg_n_uses
[i
].uses
== 0 && call_used_regs
[i
])
3560 potential_reload_regs
[o
++] = i
;
3562 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3564 if (hard_reg_n_uses
[i
].uses
== 0 && ! call_used_regs
[i
])
3565 potential_reload_regs
[o
++] = i
;
3569 qsort (hard_reg_n_uses
, FIRST_PSEUDO_REGISTER
,
3570 sizeof hard_reg_n_uses
[0], hard_reg_use_compare
);
3572 /* Now add the regs that are already used,
3573 preferring those used less often. The fixed and otherwise forbidden
3574 registers will be at the end of this list. */
3576 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3577 if (hard_reg_n_uses
[i
].uses
!= 0)
3578 potential_reload_regs
[o
++] = hard_reg_n_uses
[i
].regno
;
3581 /* Reload pseudo-registers into hard regs around each insn as needed.
3582 Additional register load insns are output before the insn that needs it
3583 and perhaps store insns after insns that modify the reloaded pseudo reg.
3585 reg_last_reload_reg and reg_reloaded_contents keep track of
3586 which registers are already available in reload registers.
3587 We update these for the reloads that we perform,
3588 as the insns are scanned. */
3591 reload_as_needed (first
, live_known
)
3601 bzero (spill_reg_rtx
, sizeof spill_reg_rtx
);
3602 reg_last_reload_reg
= (rtx
*) alloca (max_regno
* sizeof (rtx
));
3603 bzero (reg_last_reload_reg
, max_regno
* sizeof (rtx
));
3604 reg_has_output_reload
= (char *) alloca (max_regno
);
3605 for (i
= 0; i
< n_spills
; i
++)
3607 reg_reloaded_contents
[i
] = -1;
3608 reg_reloaded_insn
[i
] = 0;
3611 /* Reset all offsets on eliminable registers to their initial values. */
3612 #ifdef ELIMINABLE_REGS
3613 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3615 INITIAL_ELIMINATION_OFFSET (reg_eliminate
[i
].from
, reg_eliminate
[i
].to
,
3616 reg_eliminate
[i
].initial_offset
);
3617 reg_eliminate
[i
].previous_offset
3618 = reg_eliminate
[i
].offset
= reg_eliminate
[i
].initial_offset
;
3621 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate
[0].initial_offset
);
3622 reg_eliminate
[0].previous_offset
3623 = reg_eliminate
[0].offset
= reg_eliminate
[0].initial_offset
;
3626 num_not_at_initial_offset
= 0;
3628 for (insn
= first
; insn
;)
3630 register rtx next
= NEXT_INSN (insn
);
3632 /* Notice when we move to a new basic block. */
3633 if (live_known
&& this_block
+ 1 < n_basic_blocks
3634 && insn
== basic_block_head
[this_block
+1])
3637 /* If we pass a label, copy the offsets from the label information
3638 into the current offsets of each elimination. */
3639 if (GET_CODE (insn
) == CODE_LABEL
)
3641 num_not_at_initial_offset
= 0;
3642 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3644 reg_eliminate
[i
].offset
= reg_eliminate
[i
].previous_offset
3645 = offsets_at
[CODE_LABEL_NUMBER (insn
)][i
];
3646 if (reg_eliminate
[i
].can_eliminate
3647 && (reg_eliminate
[i
].offset
3648 != reg_eliminate
[i
].initial_offset
))
3649 num_not_at_initial_offset
++;
3653 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
3655 rtx avoid_return_reg
= 0;
3657 #ifdef SMALL_REGISTER_CLASSES
3658 /* Set avoid_return_reg if this is an insn
3659 that might use the value of a function call. */
3660 if (GET_CODE (insn
) == CALL_INSN
)
3662 if (GET_CODE (PATTERN (insn
)) == SET
)
3663 after_call
= SET_DEST (PATTERN (insn
));
3664 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
3665 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
3666 after_call
= SET_DEST (XVECEXP (PATTERN (insn
), 0, 0));
3670 else if (after_call
!= 0
3671 && !(GET_CODE (PATTERN (insn
)) == SET
3672 && SET_DEST (PATTERN (insn
)) == stack_pointer_rtx
))
3674 if (reg_mentioned_p (after_call
, PATTERN (insn
)))
3675 avoid_return_reg
= after_call
;
3678 #endif /* SMALL_REGISTER_CLASSES */
3680 /* If this is a USE and CLOBBER of a MEM, ensure that any
3681 references to eliminable registers have been removed. */
3683 if ((GET_CODE (PATTERN (insn
)) == USE
3684 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
3685 && GET_CODE (XEXP (PATTERN (insn
), 0)) == MEM
)
3686 XEXP (XEXP (PATTERN (insn
), 0), 0)
3687 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
3688 GET_MODE (XEXP (PATTERN (insn
), 0)), NULL_RTX
);
3690 /* If we need to do register elimination processing, do so.
3691 This might delete the insn, in which case we are done. */
3692 if (num_eliminable
&& GET_MODE (insn
) == QImode
)
3694 eliminate_regs_in_insn (insn
, 1);
3695 if (GET_CODE (insn
) == NOTE
)
3702 if (GET_MODE (insn
) == VOIDmode
)
3704 /* First find the pseudo regs that must be reloaded for this insn.
3705 This info is returned in the tables reload_... (see reload.h).
3706 Also modify the body of INSN by substituting RELOAD
3707 rtx's for those pseudo regs. */
3710 bzero (reg_has_output_reload
, max_regno
);
3711 CLEAR_HARD_REG_SET (reg_is_output_reload
);
3713 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
3719 rtx prev
= PREV_INSN (insn
), next
= NEXT_INSN (insn
);
3723 /* If this block has not had spilling done for a
3724 particular clas and we have any non-optionals that need a
3725 spill reg in that class, abort. */
3727 for (class = 0; class < N_REG_CLASSES
; class++)
3728 if (basic_block_needs
[class] != 0
3729 && basic_block_needs
[class][this_block
] == 0)
3730 for (i
= 0; i
< n_reloads
; i
++)
3731 if (class == (int) reload_reg_class
[i
]
3732 && reload_reg_rtx
[i
] == 0
3733 && ! reload_optional
[i
]
3734 && (reload_in
[i
] != 0 || reload_out
[i
] != 0
3735 || reload_secondary_p
[i
] != 0))
3738 /* Now compute which reload regs to reload them into. Perhaps
3739 reusing reload regs from previous insns, or else output
3740 load insns to reload them. Maybe output store insns too.
3741 Record the choices of reload reg in reload_reg_rtx. */
3742 choose_reload_regs (insn
, avoid_return_reg
);
3744 #ifdef SMALL_REGISTER_CLASSES
3745 /* Merge any reloads that we didn't combine for fear of
3746 increasing the number of spill registers needed but now
3747 discover can be safely merged. */
3748 merge_assigned_reloads (insn
);
3751 /* Generate the insns to reload operands into or out of
3752 their reload regs. */
3753 emit_reload_insns (insn
);
3755 /* Substitute the chosen reload regs from reload_reg_rtx
3756 into the insn's body (or perhaps into the bodies of other
3757 load and store insn that we just made for reloading
3758 and that we moved the structure into). */
3761 /* If this was an ASM, make sure that all the reload insns
3762 we have generated are valid. If not, give an error
3765 if (asm_noperands (PATTERN (insn
)) >= 0)
3766 for (p
= NEXT_INSN (prev
); p
!= next
; p
= NEXT_INSN (p
))
3767 if (p
!= insn
&& GET_RTX_CLASS (GET_CODE (p
)) == 'i'
3768 && (recog_memoized (p
) < 0
3769 || (insn_extract (p
),
3770 ! constrain_operands (INSN_CODE (p
), 1))))
3772 error_for_asm (insn
,
3773 "`asm' operand requires impossible reload");
3775 NOTE_SOURCE_FILE (p
) = 0;
3776 NOTE_LINE_NUMBER (p
) = NOTE_INSN_DELETED
;
3779 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3780 is no longer validly lying around to save a future reload.
3781 Note that this does not detect pseudos that were reloaded
3782 for this insn in order to be stored in
3783 (obeying register constraints). That is correct; such reload
3784 registers ARE still valid. */
3785 note_stores (PATTERN (insn
), forget_old_reloads_1
);
3787 /* There may have been CLOBBER insns placed after INSN. So scan
3788 between INSN and NEXT and use them to forget old reloads. */
3789 for (x
= NEXT_INSN (insn
); x
!= next
; x
= NEXT_INSN (x
))
3790 if (GET_CODE (x
) == INSN
&& GET_CODE (PATTERN (x
)) == CLOBBER
)
3791 note_stores (PATTERN (x
), forget_old_reloads_1
);
3794 /* Likewise for regs altered by auto-increment in this insn.
3795 But note that the reg-notes are not changed by reloading:
3796 they still contain the pseudo-regs, not the spill regs. */
3797 for (x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
3798 if (REG_NOTE_KIND (x
) == REG_INC
)
3800 /* See if this pseudo reg was reloaded in this insn.
3801 If so, its last-reload info is still valid
3802 because it is based on this insn's reload. */
3803 for (i
= 0; i
< n_reloads
; i
++)
3804 if (reload_out
[i
] == XEXP (x
, 0))
3808 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
);
3812 /* A reload reg's contents are unknown after a label. */
3813 if (GET_CODE (insn
) == CODE_LABEL
)
3814 for (i
= 0; i
< n_spills
; i
++)
3816 reg_reloaded_contents
[i
] = -1;
3817 reg_reloaded_insn
[i
] = 0;
3820 /* Don't assume a reload reg is still good after a call insn
3821 if it is a call-used reg. */
3822 else if (GET_CODE (insn
) == CALL_INSN
)
3823 for (i
= 0; i
< n_spills
; i
++)
3824 if (call_used_regs
[spill_regs
[i
]])
3826 reg_reloaded_contents
[i
] = -1;
3827 reg_reloaded_insn
[i
] = 0;
3830 /* In case registers overlap, allow certain insns to invalidate
3831 particular hard registers. */
3833 #ifdef INSN_CLOBBERS_REGNO_P
3834 for (i
= 0 ; i
< n_spills
; i
++)
3835 if (INSN_CLOBBERS_REGNO_P (insn
, spill_regs
[i
]))
3837 reg_reloaded_contents
[i
] = -1;
3838 reg_reloaded_insn
[i
] = 0;
3850 /* Discard all record of any value reloaded from X,
3851 or reloaded in X from someplace else;
3852 unless X is an output reload reg of the current insn.
3854 X may be a hard reg (the reload reg)
3855 or it may be a pseudo reg that was reloaded from. */
3858 forget_old_reloads_1 (x
, ignored
)
3866 /* note_stores does give us subregs of hard regs. */
3867 while (GET_CODE (x
) == SUBREG
)
3869 offset
+= SUBREG_WORD (x
);
3873 if (GET_CODE (x
) != REG
)
3876 regno
= REGNO (x
) + offset
;
3878 if (regno
>= FIRST_PSEUDO_REGISTER
)
3883 nr
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
3884 /* Storing into a spilled-reg invalidates its contents.
3885 This can happen if a block-local pseudo is allocated to that reg
3886 and it wasn't spilled because this block's total need is 0.
3887 Then some insn might have an optional reload and use this reg. */
3888 for (i
= 0; i
< nr
; i
++)
3889 if (spill_reg_order
[regno
+ i
] >= 0
3890 /* But don't do this if the reg actually serves as an output
3891 reload reg in the current instruction. */
3893 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
)))
3895 reg_reloaded_contents
[spill_reg_order
[regno
+ i
]] = -1;
3896 reg_reloaded_insn
[spill_reg_order
[regno
+ i
]] = 0;
3900 /* Since value of X has changed,
3901 forget any value previously copied from it. */
3904 /* But don't forget a copy if this is the output reload
3905 that establishes the copy's validity. */
3906 if (n_reloads
== 0 || reg_has_output_reload
[regno
+ nr
] == 0)
3907 reg_last_reload_reg
[regno
+ nr
] = 0;
3910 /* For each reload, the mode of the reload register. */
3911 static enum machine_mode reload_mode
[MAX_RELOADS
];
3913 /* For each reload, the largest number of registers it will require. */
3914 static int reload_nregs
[MAX_RELOADS
];
3916 /* Comparison function for qsort to decide which of two reloads
3917 should be handled first. *P1 and *P2 are the reload numbers. */
3920 reload_reg_class_lower (p1
, p2
)
3923 register int r1
= *p1
, r2
= *p2
;
3926 /* Consider required reloads before optional ones. */
3927 t
= reload_optional
[r1
] - reload_optional
[r2
];
3931 /* Count all solitary classes before non-solitary ones. */
3932 t
= ((reg_class_size
[(int) reload_reg_class
[r2
]] == 1)
3933 - (reg_class_size
[(int) reload_reg_class
[r1
]] == 1));
3937 /* Aside from solitaires, consider all multi-reg groups first. */
3938 t
= reload_nregs
[r2
] - reload_nregs
[r1
];
3942 /* Consider reloads in order of increasing reg-class number. */
3943 t
= (int) reload_reg_class
[r1
] - (int) reload_reg_class
[r2
];
3947 /* If reloads are equally urgent, sort by reload number,
3948 so that the results of qsort leave nothing to chance. */
3952 /* The following HARD_REG_SETs indicate when each hard register is
3953 used for a reload of various parts of the current insn. */
3955 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
3956 static HARD_REG_SET reload_reg_used
;
3957 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
3958 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
3959 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
3960 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
3961 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
3962 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
3963 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
3964 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
3965 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
3966 static HARD_REG_SET reload_reg_used_in_op_addr
;
3967 /* If reg is in use for a RELOAD_FOR_INSN reload. */
3968 static HARD_REG_SET reload_reg_used_in_insn
;
3969 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
3970 static HARD_REG_SET reload_reg_used_in_other_addr
;
3972 /* If reg is in use as a reload reg for any sort of reload. */
3973 static HARD_REG_SET reload_reg_used_at_all
;
3975 /* If reg is use as an inherited reload. We just mark the first register
3977 static HARD_REG_SET reload_reg_used_for_inherit
;
3979 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
3980 TYPE. MODE is used to indicate how many consecutive regs are
3984 mark_reload_reg_in_use (regno
, opnum
, type
, mode
)
3987 enum reload_type type
;
3988 enum machine_mode mode
;
3990 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
3993 for (i
= regno
; i
< nregs
+ regno
; i
++)
3998 SET_HARD_REG_BIT (reload_reg_used
, i
);
4001 case RELOAD_FOR_INPUT_ADDRESS
:
4002 SET_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4005 case RELOAD_FOR_OUTPUT_ADDRESS
:
4006 SET_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4009 case RELOAD_FOR_OPERAND_ADDRESS
:
4010 SET_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4013 case RELOAD_FOR_OTHER_ADDRESS
:
4014 SET_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4017 case RELOAD_FOR_INPUT
:
4018 SET_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4021 case RELOAD_FOR_OUTPUT
:
4022 SET_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4025 case RELOAD_FOR_INSN
:
4026 SET_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4030 SET_HARD_REG_BIT (reload_reg_used_at_all
, i
);
4034 /* Similarly, but show REGNO is no longer in use for a reload. */
4037 clear_reload_reg_in_use (regno
, opnum
, type
, mode
)
4040 enum reload_type type
;
4041 enum machine_mode mode
;
4043 int nregs
= HARD_REGNO_NREGS (regno
, mode
);
4046 for (i
= regno
; i
< nregs
+ regno
; i
++)
4051 CLEAR_HARD_REG_BIT (reload_reg_used
, i
);
4054 case RELOAD_FOR_INPUT_ADDRESS
:
4055 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], i
);
4058 case RELOAD_FOR_OUTPUT_ADDRESS
:
4059 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], i
);
4062 case RELOAD_FOR_OPERAND_ADDRESS
:
4063 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr
, i
);
4066 case RELOAD_FOR_OTHER_ADDRESS
:
4067 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr
, i
);
4070 case RELOAD_FOR_INPUT
:
4071 CLEAR_HARD_REG_BIT (reload_reg_used_in_input
[opnum
], i
);
4074 case RELOAD_FOR_OUTPUT
:
4075 CLEAR_HARD_REG_BIT (reload_reg_used_in_output
[opnum
], i
);
4078 case RELOAD_FOR_INSN
:
4079 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn
, i
);
4085 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4086 specified by OPNUM and TYPE. */
4089 reload_reg_free_p (regno
, opnum
, type
)
4092 enum reload_type type
;
4096 /* In use for a RELOAD_OTHER means it's not available for anything except
4097 RELOAD_FOR_OTHER_ADDRESS. Recall that RELOAD_FOR_OTHER_ADDRESS is known
4098 to be used only for inputs. */
4100 if (type
!= RELOAD_FOR_OTHER_ADDRESS
4101 && TEST_HARD_REG_BIT (reload_reg_used
, regno
))
4107 /* In use for anything means not available for a RELOAD_OTHER. */
4108 return ! TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
);
4110 /* The other kinds of use can sometimes share a register. */
4111 case RELOAD_FOR_INPUT
:
4112 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4113 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4116 /* If it is used for some other input, can't use it. */
4117 for (i
= 0; i
< reload_n_operands
; i
++)
4118 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4121 /* If it is used in a later operand's address, can't use it. */
4122 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4123 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
))
4128 case RELOAD_FOR_INPUT_ADDRESS
:
4129 /* Can't use a register if it is used for an input address for this
4130 operand or used as an input in an earlier one. */
4131 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
4134 for (i
= 0; i
< opnum
; i
++)
4135 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4140 case RELOAD_FOR_OUTPUT_ADDRESS
:
4141 /* Can't use a register if it is used for an output address for this
4142 operand or used as an output in this or a later operand. */
4143 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4146 for (i
= opnum
; i
< reload_n_operands
; i
++)
4147 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4152 case RELOAD_FOR_OPERAND_ADDRESS
:
4153 for (i
= 0; i
< reload_n_operands
; i
++)
4154 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4157 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4158 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4160 case RELOAD_FOR_OUTPUT
:
4161 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4162 outputs, or an operand address for this or an earlier output. */
4163 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4166 for (i
= 0; i
< reload_n_operands
; i
++)
4167 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4170 for (i
= 0; i
<= opnum
; i
++)
4171 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
))
4176 case RELOAD_FOR_INSN
:
4177 for (i
= 0; i
< reload_n_operands
; i
++)
4178 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4179 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4182 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4183 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4185 case RELOAD_FOR_OTHER_ADDRESS
:
4186 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4191 /* Return 1 if the value in reload reg REGNO, as used by a reload
4192 needed for the part of the insn specified by OPNUM and TYPE,
4193 is not in use for a reload in any prior part of the insn.
4195 We can assume that the reload reg was already tested for availability
4196 at the time it is needed, and we should not check this again,
4197 in case the reg has already been marked in use. */
4200 reload_reg_free_before_p (regno
, opnum
, type
)
4203 enum reload_type type
;
4209 case RELOAD_FOR_OTHER_ADDRESS
:
4210 /* These always come first. */
4214 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4216 /* If this use is for part of the insn,
4217 check the reg is not in use for any prior part. It is tempting
4218 to try to do this by falling through from objecs that occur
4219 later in the insn to ones that occur earlier, but that will not
4220 correctly take into account the fact that here we MUST ignore
4221 things that would prevent the register from being allocated in
4222 the first place, since we know that it was allocated. */
4224 case RELOAD_FOR_OUTPUT_ADDRESS
:
4225 /* Earlier reloads are for earlier outputs or their addresses,
4226 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any
4227 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with
4229 for (i
= 0; i
< opnum
; i
++)
4230 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4231 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4234 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
4237 for (i
= 0; i
< reload_n_operands
; i
++)
4238 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4239 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4242 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
4243 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4244 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
4246 case RELOAD_FOR_OUTPUT
:
4247 /* This can't be used in the output address for this operand and
4248 anything that can't be used for it, except that we've already
4249 tested for RELOAD_FOR_INSN objects. */
4251 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
4254 for (i
= 0; i
< opnum
; i
++)
4255 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4256 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4259 for (i
= 0; i
< reload_n_operands
; i
++)
4260 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4261 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
4262 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
4265 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4267 case RELOAD_FOR_OPERAND_ADDRESS
:
4268 case RELOAD_FOR_INSN
:
4269 /* These can't conflict with inputs, or each other, so all we have to
4270 test is input addresses and the addresses of OTHER items. */
4272 for (i
= 0; i
< reload_n_operands
; i
++)
4273 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
))
4276 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4278 case RELOAD_FOR_INPUT
:
4279 /* The only things earlier are the address for this and
4280 earlier inputs, other inputs (which we know we don't conflict
4281 with), and addresses of RELOAD_OTHER objects. */
4283 for (i
= 0; i
<= opnum
; i
++)
4284 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
))
4287 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4289 case RELOAD_FOR_INPUT_ADDRESS
:
4290 /* Similarly, all we have to check is for use in earlier inputs'
4292 for (i
= 0; i
< opnum
; i
++)
4293 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
))
4296 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
4301 /* Return 1 if the value in reload reg REGNO, as used by a reload
4302 needed for the part of the insn specified by OPNUM and TYPE,
4303 is still available in REGNO at the end of the insn.
4305 We can assume that the reload reg was already tested for availability
4306 at the time it is needed, and we should not check this again,
4307 in case the reg has already been marked in use. */
4310 reload_reg_reaches_end_p (regno
, opnum
, type
)
4313 enum reload_type type
;
4320 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4321 its value must reach the end. */
4324 /* If this use is for part of the insn,
4325 its value reaches if no subsequent part uses the same register.
4326 Just like the above function, don't try to do this with lots
4329 case RELOAD_FOR_OTHER_ADDRESS
:
4330 /* Here we check for everything else, since these don't conflict
4331 with anything else and everything comes later. */
4333 for (i
= 0; i
< reload_n_operands
; i
++)
4334 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4335 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
4336 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4337 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4340 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4341 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
4342 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
4344 case RELOAD_FOR_INPUT_ADDRESS
:
4345 /* Similar, except that we check only for this and subsequent inputs
4346 and the address of only subsequent inputs and we do not need
4347 to check for RELOAD_OTHER objects since they are known not to
4350 for (i
= opnum
; i
< reload_n_operands
; i
++)
4351 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4354 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4355 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
))
4358 for (i
= 0; i
< reload_n_operands
; i
++)
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4360 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4363 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
4364 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
));
4366 case RELOAD_FOR_INPUT
:
4367 /* Similar to input address, except we start at the next operand for
4368 both input and input address and we do not check for
4369 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4372 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
4374 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
4377 /* ... fall through ... */
4379 case RELOAD_FOR_OPERAND_ADDRESS
:
4380 /* Check outputs and their addresses. */
4382 for (i
= 0; i
< reload_n_operands
; i
++)
4383 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
4384 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
4389 case RELOAD_FOR_INSN
:
4390 /* These conflict with other outputs with with RELOAD_OTHER. So
4391 we need only check for output addresses. */
4395 /* ... fall through ... */
4397 case RELOAD_FOR_OUTPUT
:
4398 case RELOAD_FOR_OUTPUT_ADDRESS
:
4399 /* We already know these can't conflict with a later output. So the
4400 only thing to check are later output addresses. */
4401 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
))
4411 /* Vector of reload-numbers showing the order in which the reloads should
4413 short reload_order
[MAX_RELOADS
];
4415 /* Indexed by reload number, 1 if incoming value
4416 inherited from previous insns. */
4417 char reload_inherited
[MAX_RELOADS
];
4419 /* For an inherited reload, this is the insn the reload was inherited from,
4420 if we know it. Otherwise, this is 0. */
4421 rtx reload_inheritance_insn
[MAX_RELOADS
];
4423 /* If non-zero, this is a place to get the value of the reload,
4424 rather than using reload_in. */
4425 rtx reload_override_in
[MAX_RELOADS
];
4427 /* For each reload, the index in spill_regs of the spill register used,
4428 or -1 if we did not need one of the spill registers for this reload. */
4429 int reload_spill_index
[MAX_RELOADS
];
4431 /* Index of last register assigned as a spill register. We allocate in
4432 a round-robin fashio. */
4434 static int last_spill_reg
= 0;
4436 /* Find a spill register to use as a reload register for reload R.
4437 LAST_RELOAD is non-zero if this is the last reload for the insn being
4440 Set reload_reg_rtx[R] to the register allocated.
4442 If NOERROR is nonzero, we return 1 if successful,
4443 or 0 if we couldn't find a spill reg and we didn't change anything. */
4446 allocate_reload_reg (r
, insn
, last_reload
, noerror
)
4458 /* If we put this reload ahead, thinking it is a group,
4459 then insist on finding a group. Otherwise we can grab a
4460 reg that some other reload needs.
4461 (That can happen when we have a 68000 DATA_OR_FP_REG
4462 which is a group of data regs or one fp reg.)
4463 We need not be so restrictive if there are no more reloads
4466 ??? Really it would be nicer to have smarter handling
4467 for that kind of reg class, where a problem like this is normal.
4468 Perhaps those classes should be avoided for reloading
4469 by use of more alternatives. */
4471 int force_group
= reload_nregs
[r
] > 1 && ! last_reload
;
4473 /* If we want a single register and haven't yet found one,
4474 take any reg in the right class and not in use.
4475 If we want a consecutive group, here is where we look for it.
4477 We use two passes so we can first look for reload regs to
4478 reuse, which are already in use for other reloads in this insn,
4479 and only then use additional registers.
4480 I think that maximizing reuse is needed to make sure we don't
4481 run out of reload regs. Suppose we have three reloads, and
4482 reloads A and B can share regs. These need two regs.
4483 Suppose A and B are given different regs.
4484 That leaves none for C. */
4485 for (pass
= 0; pass
< 2; pass
++)
4487 /* I is the index in spill_regs.
4488 We advance it round-robin between insns to use all spill regs
4489 equally, so that inherited reloads have a chance
4490 of leapfrogging each other. */
4492 for (count
= 0, i
= last_spill_reg
; count
< n_spills
; count
++)
4494 int class = (int) reload_reg_class
[r
];
4496 i
= (i
+ 1) % n_spills
;
4498 if (reload_reg_free_p (spill_regs
[i
], reload_opnum
[r
],
4499 reload_when_needed
[r
])
4500 && TEST_HARD_REG_BIT (reg_class_contents
[class], spill_regs
[i
])
4501 && HARD_REGNO_MODE_OK (spill_regs
[i
], reload_mode
[r
])
4502 /* Look first for regs to share, then for unshared. But
4503 don't share regs used for inherited reloads; they are
4504 the ones we want to preserve. */
4506 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
4508 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
4511 int nr
= HARD_REGNO_NREGS (spill_regs
[i
], reload_mode
[r
]);
4512 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
4513 (on 68000) got us two FP regs. If NR is 1,
4514 we would reject both of them. */
4516 nr
= CLASS_MAX_NREGS (reload_reg_class
[r
], reload_mode
[r
]);
4517 /* If we need only one reg, we have already won. */
4520 /* But reject a single reg if we demand a group. */
4525 /* Otherwise check that as many consecutive regs as we need
4527 Also, don't use for a group registers that are
4528 needed for nongroups. */
4529 if (! TEST_HARD_REG_BIT (counted_for_nongroups
, spill_regs
[i
]))
4532 regno
= spill_regs
[i
] + nr
- 1;
4533 if (!(TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
4534 && spill_reg_order
[regno
] >= 0
4535 && reload_reg_free_p (regno
, reload_opnum
[r
],
4536 reload_when_needed
[r
])
4537 && ! TEST_HARD_REG_BIT (counted_for_nongroups
,
4547 /* If we found something on pass 1, omit pass 2. */
4548 if (count
< n_spills
)
4552 /* We should have found a spill register by now. */
4553 if (count
== n_spills
)
4560 /* I is the index in SPILL_REG_RTX of the reload register we are to
4561 allocate. Get an rtx for it and find its register number. */
4563 new = spill_reg_rtx
[i
];
4565 if (new == 0 || GET_MODE (new) != reload_mode
[r
])
4566 spill_reg_rtx
[i
] = new
4567 = gen_rtx (REG
, reload_mode
[r
], spill_regs
[i
]);
4569 regno
= true_regnum (new);
4571 /* Detect when the reload reg can't hold the reload mode.
4572 This used to be one `if', but Sequent compiler can't handle that. */
4573 if (HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
4575 enum machine_mode test_mode
= VOIDmode
;
4577 test_mode
= GET_MODE (reload_in
[r
]);
4578 /* If reload_in[r] has VOIDmode, it means we will load it
4579 in whatever mode the reload reg has: to wit, reload_mode[r].
4580 We have already tested that for validity. */
4581 /* Aside from that, we need to test that the expressions
4582 to reload from or into have modes which are valid for this
4583 reload register. Otherwise the reload insns would be invalid. */
4584 if (! (reload_in
[r
] != 0 && test_mode
!= VOIDmode
4585 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
4586 if (! (reload_out
[r
] != 0
4587 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (reload_out
[r
]))))
4589 /* The reg is OK. */
4592 /* Mark as in use for this insn the reload regs we use
4594 mark_reload_reg_in_use (spill_regs
[i
], reload_opnum
[r
],
4595 reload_when_needed
[r
], reload_mode
[r
]);
4597 reload_reg_rtx
[r
] = new;
4598 reload_spill_index
[r
] = i
;
4603 /* The reg is not OK. */
4608 if (asm_noperands (PATTERN (insn
)) < 0)
4609 /* It's the compiler's fault. */
4612 /* It's the user's fault; the operand's mode and constraint
4613 don't match. Disable this reload so we don't crash in final. */
4614 error_for_asm (insn
,
4615 "`asm' operand constraint incompatible with operand size");
4618 reload_reg_rtx
[r
] = 0;
4619 reload_optional
[r
] = 1;
4620 reload_secondary_p
[r
] = 1;
4625 /* Assign hard reg targets for the pseudo-registers we must reload
4626 into hard regs for this insn.
4627 Also output the instructions to copy them in and out of the hard regs.
4629 For machines with register classes, we are responsible for
4630 finding a reload reg in the proper class. */
4633 choose_reload_regs (insn
, avoid_return_reg
)
4635 rtx avoid_return_reg
;
4638 int max_group_size
= 1;
4639 enum reg_class group_class
= NO_REGS
;
4642 rtx save_reload_reg_rtx
[MAX_RELOADS
];
4643 char save_reload_inherited
[MAX_RELOADS
];
4644 rtx save_reload_inheritance_insn
[MAX_RELOADS
];
4645 rtx save_reload_override_in
[MAX_RELOADS
];
4646 int save_reload_spill_index
[MAX_RELOADS
];
4647 HARD_REG_SET save_reload_reg_used
;
4648 HARD_REG_SET save_reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4649 HARD_REG_SET save_reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4650 HARD_REG_SET save_reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4651 HARD_REG_SET save_reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4652 HARD_REG_SET save_reload_reg_used_in_op_addr
;
4653 HARD_REG_SET save_reload_reg_used_in_insn
;
4654 HARD_REG_SET save_reload_reg_used_in_other_addr
;
4655 HARD_REG_SET save_reload_reg_used_at_all
;
4657 bzero (reload_inherited
, MAX_RELOADS
);
4658 bzero (reload_inheritance_insn
, MAX_RELOADS
* sizeof (rtx
));
4659 bzero (reload_override_in
, MAX_RELOADS
* sizeof (rtx
));
4661 CLEAR_HARD_REG_SET (reload_reg_used
);
4662 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
4663 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
4664 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
4665 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
4667 for (i
= 0; i
< reload_n_operands
; i
++)
4669 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
4670 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
4671 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
4672 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
4675 #ifdef SMALL_REGISTER_CLASSES
4676 /* Don't bother with avoiding the return reg
4677 if we have no mandatory reload that could use it. */
4678 if (avoid_return_reg
)
4681 int regno
= REGNO (avoid_return_reg
);
4683 = HARD_REGNO_NREGS (regno
, GET_MODE (avoid_return_reg
));
4686 for (r
= regno
; r
< regno
+ nregs
; r
++)
4687 if (spill_reg_order
[r
] >= 0)
4688 for (j
= 0; j
< n_reloads
; j
++)
4689 if (!reload_optional
[j
] && reload_reg_rtx
[j
] == 0
4690 && (reload_in
[j
] != 0 || reload_out
[j
] != 0
4691 || reload_secondary_p
[j
])
4693 TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[j
]], r
))
4696 avoid_return_reg
= 0;
4698 #endif /* SMALL_REGISTER_CLASSES */
4700 #if 0 /* Not needed, now that we can always retry without inheritance. */
4701 /* See if we have more mandatory reloads than spill regs.
4702 If so, then we cannot risk optimizations that could prevent
4703 reloads from sharing one spill register.
4705 Since we will try finding a better register than reload_reg_rtx
4706 unless it is equal to reload_in or reload_out, count such reloads. */
4710 #ifdef SMALL_REGISTER_CLASSES
4711 int tem
= (avoid_return_reg
!= 0);
4713 for (j
= 0; j
< n_reloads
; j
++)
4714 if (! reload_optional
[j
]
4715 && (reload_in
[j
] != 0 || reload_out
[j
] != 0 || reload_secondary_p
[j
])
4716 && (reload_reg_rtx
[j
] == 0
4717 || (! rtx_equal_p (reload_reg_rtx
[j
], reload_in
[j
])
4718 && ! rtx_equal_p (reload_reg_rtx
[j
], reload_out
[j
]))))
4725 #ifdef SMALL_REGISTER_CLASSES
4726 /* Don't use the subroutine call return reg for a reload
4727 if we are supposed to avoid it. */
4728 if (avoid_return_reg
)
4730 int regno
= REGNO (avoid_return_reg
);
4732 = HARD_REGNO_NREGS (regno
, GET_MODE (avoid_return_reg
));
4735 for (r
= regno
; r
< regno
+ nregs
; r
++)
4736 if (spill_reg_order
[r
] >= 0)
4737 SET_HARD_REG_BIT (reload_reg_used
, r
);
4739 #endif /* SMALL_REGISTER_CLASSES */
4741 /* In order to be certain of getting the registers we need,
4742 we must sort the reloads into order of increasing register class.
4743 Then our grabbing of reload registers will parallel the process
4744 that provided the reload registers.
4746 Also note whether any of the reloads wants a consecutive group of regs.
4747 If so, record the maximum size of the group desired and what
4748 register class contains all the groups needed by this insn. */
4750 for (j
= 0; j
< n_reloads
; j
++)
4752 reload_order
[j
] = j
;
4753 reload_spill_index
[j
] = -1;
4756 = (reload_inmode
[j
] == VOIDmode
4757 || (GET_MODE_SIZE (reload_outmode
[j
])
4758 > GET_MODE_SIZE (reload_inmode
[j
])))
4759 ? reload_outmode
[j
] : reload_inmode
[j
];
4761 reload_nregs
[j
] = CLASS_MAX_NREGS (reload_reg_class
[j
], reload_mode
[j
]);
4763 if (reload_nregs
[j
] > 1)
4765 max_group_size
= MAX (reload_nregs
[j
], max_group_size
);
4766 group_class
= reg_class_superunion
[(int)reload_reg_class
[j
]][(int)group_class
];
4769 /* If we have already decided to use a certain register,
4770 don't use it in another way. */
4771 if (reload_reg_rtx
[j
])
4772 mark_reload_reg_in_use (REGNO (reload_reg_rtx
[j
]), reload_opnum
[j
],
4773 reload_when_needed
[j
], reload_mode
[j
]);
4777 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
4779 bcopy (reload_reg_rtx
, save_reload_reg_rtx
, sizeof reload_reg_rtx
);
4780 bcopy (reload_inherited
, save_reload_inherited
, sizeof reload_inherited
);
4781 bcopy (reload_inheritance_insn
, save_reload_inheritance_insn
,
4782 sizeof reload_inheritance_insn
);
4783 bcopy (reload_override_in
, save_reload_override_in
,
4784 sizeof reload_override_in
);
4785 bcopy (reload_spill_index
, save_reload_spill_index
,
4786 sizeof reload_spill_index
);
4787 COPY_HARD_REG_SET (save_reload_reg_used
, reload_reg_used
);
4788 COPY_HARD_REG_SET (save_reload_reg_used_at_all
, reload_reg_used_at_all
);
4789 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr
,
4790 reload_reg_used_in_op_addr
);
4791 COPY_HARD_REG_SET (save_reload_reg_used_in_insn
,
4792 reload_reg_used_in_insn
);
4793 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr
,
4794 reload_reg_used_in_other_addr
);
4796 for (i
= 0; i
< reload_n_operands
; i
++)
4798 COPY_HARD_REG_SET (save_reload_reg_used_in_output
[i
],
4799 reload_reg_used_in_output
[i
]);
4800 COPY_HARD_REG_SET (save_reload_reg_used_in_input
[i
],
4801 reload_reg_used_in_input
[i
]);
4802 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr
[i
],
4803 reload_reg_used_in_input_addr
[i
]);
4804 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr
[i
],
4805 reload_reg_used_in_output_addr
[i
]);
4808 /* If -O, try first with inheritance, then turning it off.
4809 If not -O, don't do inheritance.
4810 Using inheritance when not optimizing leads to paradoxes
4811 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
4812 because one side of the comparison might be inherited. */
4814 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
4816 /* Process the reloads in order of preference just found.
4817 Beyond this point, subregs can be found in reload_reg_rtx.
4819 This used to look for an existing reloaded home for all
4820 of the reloads, and only then perform any new reloads.
4821 But that could lose if the reloads were done out of reg-class order
4822 because a later reload with a looser constraint might have an old
4823 home in a register needed by an earlier reload with a tighter constraint.
4825 To solve this, we make two passes over the reloads, in the order
4826 described above. In the first pass we try to inherit a reload
4827 from a previous insn. If there is a later reload that needs a
4828 class that is a proper subset of the class being processed, we must
4829 also allocate a spill register during the first pass.
4831 Then make a second pass over the reloads to allocate any reloads
4832 that haven't been given registers yet. */
4834 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
4836 for (j
= 0; j
< n_reloads
; j
++)
4838 register int r
= reload_order
[j
];
4840 /* Ignore reloads that got marked inoperative. */
4841 if (reload_out
[r
] == 0 && reload_in
[r
] == 0 && ! reload_secondary_p
[r
])
4844 /* If find_reloads chose a to use reload_in or reload_out as a reload
4845 register, we don't need to chose one. Otherwise, try even if it found
4846 one since we might save an insn if we find the value lying around. */
4847 if (reload_in
[r
] != 0 && reload_reg_rtx
[r
] != 0
4848 && (rtx_equal_p (reload_in
[r
], reload_reg_rtx
[r
])
4849 || rtx_equal_p (reload_out
[r
], reload_reg_rtx
[r
])))
4852 #if 0 /* No longer needed for correct operation.
4853 It might give better code, or might not; worth an experiment? */
4854 /* If this is an optional reload, we can't inherit from earlier insns
4855 until we are sure that any non-optional reloads have been allocated.
4856 The following code takes advantage of the fact that optional reloads
4857 are at the end of reload_order. */
4858 if (reload_optional
[r
] != 0)
4859 for (i
= 0; i
< j
; i
++)
4860 if ((reload_out
[reload_order
[i
]] != 0
4861 || reload_in
[reload_order
[i
]] != 0
4862 || reload_secondary_p
[reload_order
[i
]])
4863 && ! reload_optional
[reload_order
[i
]]
4864 && reload_reg_rtx
[reload_order
[i
]] == 0)
4865 allocate_reload_reg (reload_order
[i
], insn
, 0, inheritance
);
4868 /* First see if this pseudo is already available as reloaded
4869 for a previous insn. We cannot try to inherit for reloads
4870 that are smaller than the maximum number of registers needed
4871 for groups unless the register we would allocate cannot be used
4874 We could check here to see if this is a secondary reload for
4875 an object that is already in a register of the desired class.
4876 This would avoid the need for the secondary reload register.
4877 But this is complex because we can't easily determine what
4878 objects might want to be loaded via this reload. So let a register
4879 be allocated here. In `emit_reload_insns' we suppress one of the
4880 loads in the case described above. */
4884 register int regno
= -1;
4885 enum machine_mode mode
;
4887 if (reload_in
[r
] == 0)
4889 else if (GET_CODE (reload_in
[r
]) == REG
)
4891 regno
= REGNO (reload_in
[r
]);
4892 mode
= GET_MODE (reload_in
[r
]);
4894 else if (GET_CODE (reload_in_reg
[r
]) == REG
)
4896 regno
= REGNO (reload_in_reg
[r
]);
4897 mode
= GET_MODE (reload_in_reg
[r
]);
4900 /* This won't work, since REGNO can be a pseudo reg number.
4901 Also, it takes much more hair to keep track of all the things
4902 that can invalidate an inherited reload of part of a pseudoreg. */
4903 else if (GET_CODE (reload_in
[r
]) == SUBREG
4904 && GET_CODE (SUBREG_REG (reload_in
[r
])) == REG
)
4905 regno
= REGNO (SUBREG_REG (reload_in
[r
])) + SUBREG_WORD (reload_in
[r
]);
4908 if (regno
>= 0 && reg_last_reload_reg
[regno
] != 0)
4910 i
= spill_reg_order
[REGNO (reg_last_reload_reg
[regno
])];
4912 if (reg_reloaded_contents
[i
] == regno
4913 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
4914 >= GET_MODE_SIZE (mode
))
4915 && HARD_REGNO_MODE_OK (spill_regs
[i
], reload_mode
[r
])
4916 && TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
4918 && (reload_nregs
[r
] == max_group_size
4919 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
4921 && reload_reg_free_p (spill_regs
[i
], reload_opnum
[r
],
4922 reload_when_needed
[r
])
4923 && reload_reg_free_before_p (spill_regs
[i
],
4925 reload_when_needed
[r
]))
4927 /* If a group is needed, verify that all the subsequent
4928 registers still have their values intact. */
4930 = HARD_REGNO_NREGS (spill_regs
[i
], reload_mode
[r
]);
4933 for (k
= 1; k
< nr
; k
++)
4934 if (reg_reloaded_contents
[spill_reg_order
[spill_regs
[i
] + k
]]
4942 /* We found a register that contains the
4943 value we need. If this register is the
4944 same as an `earlyclobber' operand of the
4945 current insn, just mark it as a place to
4946 reload from since we can't use it as the
4947 reload register itself. */
4949 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
4950 if (reg_overlap_mentioned_for_reload_p
4951 (reg_last_reload_reg
[regno
],
4952 reload_earlyclobbers
[i1
]))
4955 if (i1
!= n_earlyclobbers
4956 /* Don't really use the inherited spill reg
4957 if we need it wider than we've got it. */
4958 || (GET_MODE_SIZE (reload_mode
[r
])
4959 > GET_MODE_SIZE (mode
)))
4960 reload_override_in
[r
] = reg_last_reload_reg
[regno
];
4963 /* We can use this as a reload reg. */
4964 /* Mark the register as in use for this part of
4966 mark_reload_reg_in_use (spill_regs
[i
],
4968 reload_when_needed
[r
],
4970 reload_reg_rtx
[r
] = reg_last_reload_reg
[regno
];
4971 reload_inherited
[r
] = 1;
4972 reload_inheritance_insn
[r
]
4973 = reg_reloaded_insn
[i
];
4974 reload_spill_index
[r
] = i
;
4975 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
4983 /* Here's another way to see if the value is already lying around. */
4985 && reload_in
[r
] != 0
4986 && ! reload_inherited
[r
]
4987 && reload_out
[r
] == 0
4988 && (CONSTANT_P (reload_in
[r
])
4989 || GET_CODE (reload_in
[r
]) == PLUS
4990 || GET_CODE (reload_in
[r
]) == REG
4991 || GET_CODE (reload_in
[r
]) == MEM
)
4992 && (reload_nregs
[r
] == max_group_size
4993 || ! reg_classes_intersect_p (reload_reg_class
[r
], group_class
)))
4996 = find_equiv_reg (reload_in
[r
], insn
, reload_reg_class
[r
],
4997 -1, NULL_PTR
, 0, reload_mode
[r
]);
5002 if (GET_CODE (equiv
) == REG
)
5003 regno
= REGNO (equiv
);
5004 else if (GET_CODE (equiv
) == SUBREG
)
5006 regno
= REGNO (SUBREG_REG (equiv
));
5007 if (regno
< FIRST_PSEUDO_REGISTER
)
5008 regno
+= SUBREG_WORD (equiv
);
5014 /* If we found a spill reg, reject it unless it is free
5015 and of the desired class. */
5017 && ((spill_reg_order
[regno
] >= 0
5018 && ! reload_reg_free_before_p (regno
, reload_opnum
[r
],
5019 reload_when_needed
[r
]))
5020 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) reload_reg_class
[r
]],
5024 if (equiv
!= 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all
, regno
))
5027 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, reload_mode
[r
]))
5030 /* We found a register that contains the value we need.
5031 If this register is the same as an `earlyclobber' operand
5032 of the current insn, just mark it as a place to reload from
5033 since we can't use it as the reload register itself. */
5036 for (i
= 0; i
< n_earlyclobbers
; i
++)
5037 if (reg_overlap_mentioned_for_reload_p (equiv
,
5038 reload_earlyclobbers
[i
]))
5040 reload_override_in
[r
] = equiv
;
5045 /* JRV: If the equiv register we have found is explicitly
5046 clobbered in the current insn, mark but don't use, as above. */
5048 if (equiv
!= 0 && regno_clobbered_p (regno
, insn
))
5050 reload_override_in
[r
] = equiv
;
5054 /* If we found an equivalent reg, say no code need be generated
5055 to load it, and use it as our reload reg. */
5056 if (equiv
!= 0 && regno
!= HARD_FRAME_POINTER_REGNUM
)
5058 reload_reg_rtx
[r
] = equiv
;
5059 reload_inherited
[r
] = 1;
5060 /* If it is a spill reg,
5061 mark the spill reg as in use for this insn. */
5062 i
= spill_reg_order
[regno
];
5065 mark_reload_reg_in_use (regno
, reload_opnum
[r
],
5066 reload_when_needed
[r
],
5068 SET_HARD_REG_BIT (reload_reg_used_for_inherit
, regno
);
5073 /* If we found a register to use already, or if this is an optional
5074 reload, we are done. */
5075 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
] != 0)
5078 #if 0 /* No longer needed for correct operation. Might or might not
5079 give better code on the average. Want to experiment? */
5081 /* See if there is a later reload that has a class different from our
5082 class that intersects our class or that requires less register
5083 than our reload. If so, we must allocate a register to this
5084 reload now, since that reload might inherit a previous reload
5085 and take the only available register in our class. Don't do this
5086 for optional reloads since they will force all previous reloads
5087 to be allocated. Also don't do this for reloads that have been
5090 for (i
= j
+ 1; i
< n_reloads
; i
++)
5092 int s
= reload_order
[i
];
5094 if ((reload_in
[s
] == 0 && reload_out
[s
] == 0
5095 && ! reload_secondary_p
[s
])
5096 || reload_optional
[s
])
5099 if ((reload_reg_class
[s
] != reload_reg_class
[r
]
5100 && reg_classes_intersect_p (reload_reg_class
[r
],
5101 reload_reg_class
[s
]))
5102 || reload_nregs
[s
] < reload_nregs
[r
])
5109 allocate_reload_reg (r
, insn
, j
== n_reloads
- 1, inheritance
);
5113 /* Now allocate reload registers for anything non-optional that
5114 didn't get one yet. */
5115 for (j
= 0; j
< n_reloads
; j
++)
5117 register int r
= reload_order
[j
];
5119 /* Ignore reloads that got marked inoperative. */
5120 if (reload_out
[r
] == 0 && reload_in
[r
] == 0 && ! reload_secondary_p
[r
])
5123 /* Skip reloads that already have a register allocated or are
5125 if (reload_reg_rtx
[r
] != 0 || reload_optional
[r
])
5128 if (! allocate_reload_reg (r
, insn
, j
== n_reloads
- 1, inheritance
))
5132 /* If that loop got all the way, we have won. */
5137 /* Loop around and try without any inheritance. */
5138 /* First undo everything done by the failed attempt
5139 to allocate with inheritance. */
5140 bcopy (save_reload_reg_rtx
, reload_reg_rtx
, sizeof reload_reg_rtx
);
5141 bcopy (save_reload_inherited
, reload_inherited
, sizeof reload_inherited
);
5142 bcopy (save_reload_inheritance_insn
, reload_inheritance_insn
,
5143 sizeof reload_inheritance_insn
);
5144 bcopy (save_reload_override_in
, reload_override_in
,
5145 sizeof reload_override_in
);
5146 bcopy (save_reload_spill_index
, reload_spill_index
,
5147 sizeof reload_spill_index
);
5148 COPY_HARD_REG_SET (reload_reg_used
, save_reload_reg_used
);
5149 COPY_HARD_REG_SET (reload_reg_used_at_all
, save_reload_reg_used_at_all
);
5150 COPY_HARD_REG_SET (reload_reg_used_in_op_addr
,
5151 save_reload_reg_used_in_op_addr
);
5152 COPY_HARD_REG_SET (reload_reg_used_in_insn
,
5153 save_reload_reg_used_in_insn
);
5154 COPY_HARD_REG_SET (reload_reg_used_in_other_addr
,
5155 save_reload_reg_used_in_other_addr
);
5157 for (i
= 0; i
< reload_n_operands
; i
++)
5159 COPY_HARD_REG_SET (reload_reg_used_in_input
[i
],
5160 save_reload_reg_used_in_input
[i
]);
5161 COPY_HARD_REG_SET (reload_reg_used_in_output
[i
],
5162 save_reload_reg_used_in_output
[i
]);
5163 COPY_HARD_REG_SET (reload_reg_used_in_input_addr
[i
],
5164 save_reload_reg_used_in_input_addr
[i
]);
5165 COPY_HARD_REG_SET (reload_reg_used_in_output_addr
[i
],
5166 save_reload_reg_used_in_output_addr
[i
]);
5170 /* If we thought we could inherit a reload, because it seemed that
5171 nothing else wanted the same reload register earlier in the insn,
5172 verify that assumption, now that all reloads have been assigned. */
5174 for (j
= 0; j
< n_reloads
; j
++)
5176 register int r
= reload_order
[j
];
5178 if (reload_inherited
[r
] && reload_reg_rtx
[r
] != 0
5179 && ! reload_reg_free_before_p (true_regnum (reload_reg_rtx
[r
]),
5181 reload_when_needed
[r
]))
5182 reload_inherited
[r
] = 0;
5184 /* If we found a better place to reload from,
5185 validate it in the same fashion, if it is a reload reg. */
5186 if (reload_override_in
[r
]
5187 && (GET_CODE (reload_override_in
[r
]) == REG
5188 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
5190 int regno
= true_regnum (reload_override_in
[r
]);
5191 if (spill_reg_order
[regno
] >= 0
5192 && ! reload_reg_free_before_p (regno
, reload_opnum
[r
],
5193 reload_when_needed
[r
]))
5194 reload_override_in
[r
] = 0;
5198 /* Now that reload_override_in is known valid,
5199 actually override reload_in. */
5200 for (j
= 0; j
< n_reloads
; j
++)
5201 if (reload_override_in
[j
])
5202 reload_in
[j
] = reload_override_in
[j
];
5204 /* If this reload won't be done because it has been cancelled or is
5205 optional and not inherited, clear reload_reg_rtx so other
5206 routines (such as subst_reloads) don't get confused. */
5207 for (j
= 0; j
< n_reloads
; j
++)
5208 if (reload_reg_rtx
[j
] != 0
5209 && ((reload_optional
[j
] && ! reload_inherited
[j
])
5210 || (reload_in
[j
] == 0 && reload_out
[j
] == 0
5211 && ! reload_secondary_p
[j
])))
5213 int regno
= true_regnum (reload_reg_rtx
[j
]);
5215 if (spill_reg_order
[regno
] >= 0)
5216 clear_reload_reg_in_use (regno
, reload_opnum
[j
],
5217 reload_when_needed
[j
], reload_mode
[j
]);
5218 reload_reg_rtx
[j
] = 0;
5221 /* Record which pseudos and which spill regs have output reloads. */
5222 for (j
= 0; j
< n_reloads
; j
++)
5224 register int r
= reload_order
[j
];
5226 i
= reload_spill_index
[r
];
5228 /* I is nonneg if this reload used one of the spill regs.
5229 If reload_reg_rtx[r] is 0, this is an optional reload
5230 that we opted to ignore. */
5231 if (reload_out
[r
] != 0 && GET_CODE (reload_out
[r
]) == REG
5232 && reload_reg_rtx
[r
] != 0)
5234 register int nregno
= REGNO (reload_out
[r
]);
5237 if (nregno
< FIRST_PSEUDO_REGISTER
)
5238 nr
= HARD_REGNO_NREGS (nregno
, reload_mode
[r
]);
5241 reg_has_output_reload
[nregno
+ nr
] = 1;
5245 nr
= HARD_REGNO_NREGS (spill_regs
[i
], reload_mode
[r
]);
5247 SET_HARD_REG_BIT (reg_is_output_reload
, spill_regs
[i
] + nr
);
5250 if (reload_when_needed
[r
] != RELOAD_OTHER
5251 && reload_when_needed
[r
] != RELOAD_FOR_OUTPUT
5252 && reload_when_needed
[r
] != RELOAD_FOR_INSN
)
5258 /* If SMALL_REGISTER_CLASSES are defined, we may not have merged two
5259 reloads of the same item for fear that we might not have enough reload
5260 registers. However, normally they will get the same reload register
5261 and hence actually need not be loaded twice.
5263 Here we check for the most common case of this phenomenon: when we have
5264 a number of reloads for the same object, each of which were allocated
5265 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5266 reload, and is not modified in the insn itself. If we find such,
5267 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5268 This will not increase the number of spill registers needed and will
5269 prevent redundant code. */
5271 #ifdef SMALL_REGISTER_CLASSES
5274 merge_assigned_reloads (insn
)
5279 /* Scan all the reloads looking for ones that only load values and
5280 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5281 assigned and not modified by INSN. */
5283 for (i
= 0; i
< n_reloads
; i
++)
5285 if (reload_in
[i
] == 0 || reload_when_needed
[i
] == RELOAD_OTHER
5286 || reload_out
[i
] != 0 || reload_reg_rtx
[i
] == 0
5287 || reg_set_p (reload_reg_rtx
[i
], insn
))
5290 /* Look at all other reloads. Ensure that the only use of this
5291 reload_reg_rtx is in a reload that just loads the same value
5292 as we do. Note that any secondary reloads must be of the identical
5293 class since the values, modes, and result registers are the
5294 same, so we need not do anything with any secondary reloads. */
5296 for (j
= 0; j
< n_reloads
; j
++)
5298 if (i
== j
|| reload_reg_rtx
[j
] == 0
5299 || ! reg_overlap_mentioned_p (reload_reg_rtx
[j
],
5303 /* If the reload regs aren't exactly the same (e.g, different modes)
5304 or if the values are different, we can't merge anything with this
5307 if (! rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
])
5308 || reload_out
[j
] != 0 || reload_in
[j
] == 0
5309 || ! rtx_equal_p (reload_in
[i
], reload_in
[j
]))
5313 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5314 we, in fact, found any matching reloads. */
5318 for (j
= 0; j
< n_reloads
; j
++)
5319 if (i
!= j
&& reload_reg_rtx
[j
] != 0
5320 && rtx_equal_p (reload_reg_rtx
[i
], reload_reg_rtx
[j
]))
5322 reload_when_needed
[i
] = RELOAD_OTHER
;
5324 transfer_replacements (i
, j
);
5327 /* If this is now RELOAD_OTHER, look for any reloads that load
5328 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5329 if they were for inputs, RELOAD_OTHER for outputs. Note that
5330 this test is equivalent to looking for reloads for this operand
5333 if (reload_when_needed
[i
] == RELOAD_OTHER
)
5334 for (j
= 0; j
< n_reloads
; j
++)
5335 if (reload_in
[j
] != 0
5336 && reload_when_needed
[i
] != RELOAD_OTHER
5337 && reg_overlap_mentioned_for_reload_p (reload_in
[j
],
5339 reload_when_needed
[j
]
5340 = reload_when_needed
[i
] == RELOAD_FOR_INPUT_ADDRESS
5341 ? RELOAD_FOR_OTHER_ADDRESS
: RELOAD_OTHER
;
5345 #endif /* SMALL_RELOAD_CLASSES */
5347 /* Output insns to reload values in and out of the chosen reload regs. */
5350 emit_reload_insns (insn
)
5354 rtx input_reload_insns
[MAX_RECOG_OPERANDS
];
5355 rtx other_input_address_reload_insns
= 0;
5356 rtx other_input_reload_insns
= 0;
5357 rtx input_address_reload_insns
[MAX_RECOG_OPERANDS
];
5358 rtx output_reload_insns
[MAX_RECOG_OPERANDS
];
5359 rtx output_address_reload_insns
[MAX_RECOG_OPERANDS
];
5360 rtx operand_reload_insns
= 0;
5361 rtx following_insn
= NEXT_INSN (insn
);
5362 rtx before_insn
= insn
;
5364 /* Values to be put in spill_reg_store are put here first. */
5365 rtx new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
5367 for (j
= 0; j
< reload_n_operands
; j
++)
5368 input_reload_insns
[j
] = input_address_reload_insns
[j
]
5369 = output_reload_insns
[j
] = output_address_reload_insns
[j
] = 0;
5371 /* If this is a CALL_INSN preceded by USE insns, any reload insns
5372 must go in front of the first USE insn, not in front of INSN. */
5374 if (GET_CODE (insn
) == CALL_INSN
&& GET_CODE (PREV_INSN (insn
)) == INSN
5375 && GET_CODE (PATTERN (PREV_INSN (insn
))) == USE
)
5376 while (GET_CODE (PREV_INSN (before_insn
)) == INSN
5377 && GET_CODE (PATTERN (PREV_INSN (before_insn
))) == USE
)
5378 before_insn
= PREV_INSN (before_insn
);
5380 /* If INSN is followed by any CLOBBER insns made by find_reloads,
5381 put our reloads after them since they may otherwise be
5384 while (GET_CODE (following_insn
) == INSN
5385 && GET_MODE (following_insn
) == DImode
5386 && GET_CODE (PATTERN (following_insn
)) == CLOBBER
5387 && NEXT_INSN (following_insn
) != 0)
5388 following_insn
= NEXT_INSN (following_insn
);
5390 /* Now output the instructions to copy the data into and out of the
5391 reload registers. Do these in the order that the reloads were reported,
5392 since reloads of base and index registers precede reloads of operands
5393 and the operands may need the base and index registers reloaded. */
5395 for (j
= 0; j
< n_reloads
; j
++)
5398 rtx oldequiv_reg
= 0;
5402 if (old
!= 0 && ! reload_inherited
[j
]
5403 && ! rtx_equal_p (reload_reg_rtx
[j
], old
)
5404 && reload_reg_rtx
[j
] != 0)
5406 register rtx reloadreg
= reload_reg_rtx
[j
];
5408 enum machine_mode mode
;
5411 /* Determine the mode to reload in.
5412 This is very tricky because we have three to choose from.
5413 There is the mode the insn operand wants (reload_inmode[J]).
5414 There is the mode of the reload register RELOADREG.
5415 There is the intrinsic mode of the operand, which we could find
5416 by stripping some SUBREGs.
5417 It turns out that RELOADREG's mode is irrelevant:
5418 we can change that arbitrarily.
5420 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5421 then the reload reg may not support QImode moves, so use SImode.
5422 If foo is in memory due to spilling a pseudo reg, this is safe,
5423 because the QImode value is in the least significant part of a
5424 slot big enough for a SImode. If foo is some other sort of
5425 memory reference, then it is impossible to reload this case,
5426 so previous passes had better make sure this never happens.
5428 Then consider a one-word union which has SImode and one of its
5429 members is a float, being fetched as (SUBREG:SF union:SI).
5430 We must fetch that as SFmode because we could be loading into
5431 a float-only register. In this case OLD's mode is correct.
5433 Consider an immediate integer: it has VOIDmode. Here we need
5434 to get a mode from something else.
5436 In some cases, there is a fourth mode, the operand's
5437 containing mode. If the insn specifies a containing mode for
5438 this operand, it overrides all others.
5440 I am not sure whether the algorithm here is always right,
5441 but it does the right things in those cases. */
5443 mode
= GET_MODE (old
);
5444 if (mode
== VOIDmode
)
5445 mode
= reload_inmode
[j
];
5447 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5448 /* If we need a secondary register for this operation, see if
5449 the value is already in a register in that class. Don't
5450 do this if the secondary register will be used as a scratch
5453 if (reload_secondary_reload
[j
] >= 0
5454 && reload_secondary_icode
[j
] == CODE_FOR_nothing
5457 = find_equiv_reg (old
, insn
,
5458 reload_reg_class
[reload_secondary_reload
[j
]],
5459 -1, NULL_PTR
, 0, mode
);
5462 /* If reloading from memory, see if there is a register
5463 that already holds the same value. If so, reload from there.
5464 We can pass 0 as the reload_reg_p argument because
5465 any other reload has either already been emitted,
5466 in which case find_equiv_reg will see the reload-insn,
5467 or has yet to be emitted, in which case it doesn't matter
5468 because we will use this equiv reg right away. */
5470 if (oldequiv
== 0 && optimize
5471 && (GET_CODE (old
) == MEM
5472 || (GET_CODE (old
) == REG
5473 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
5474 && reg_renumber
[REGNO (old
)] < 0)))
5475 oldequiv
= find_equiv_reg (old
, insn
, ALL_REGS
,
5476 -1, NULL_PTR
, 0, mode
);
5480 int regno
= true_regnum (oldequiv
);
5482 /* If OLDEQUIV is a spill register, don't use it for this
5483 if any other reload needs it at an earlier stage of this insn
5484 or at this stage. */
5485 if (spill_reg_order
[regno
] >= 0
5486 && (! reload_reg_free_p (regno
, reload_opnum
[j
],
5487 reload_when_needed
[j
])
5488 || ! reload_reg_free_before_p (regno
, reload_opnum
[j
],
5489 reload_when_needed
[j
])))
5492 /* If OLDEQUIV is not a spill register,
5493 don't use it if any other reload wants it. */
5494 if (spill_reg_order
[regno
] < 0)
5497 for (k
= 0; k
< n_reloads
; k
++)
5498 if (reload_reg_rtx
[k
] != 0 && k
!= j
5499 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx
[k
],
5507 /* If it is no cheaper to copy from OLDEQUIV into the
5508 reload register than it would be to move from memory,
5509 don't use it. Likewise, if we need a secondary register
5513 && ((REGNO_REG_CLASS (regno
) != reload_reg_class
[j
]
5514 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno
),
5515 reload_reg_class
[j
])
5516 >= MEMORY_MOVE_COST (mode
)))
5517 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5518 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
5522 #ifdef SECONDARY_MEMORY_NEEDED
5523 || SECONDARY_MEMORY_NEEDED (reload_reg_class
[j
],
5524 REGNO_REG_CLASS (regno
),
5533 else if (GET_CODE (oldequiv
) == REG
)
5534 oldequiv_reg
= oldequiv
;
5535 else if (GET_CODE (oldequiv
) == SUBREG
)
5536 oldequiv_reg
= SUBREG_REG (oldequiv
);
5538 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
5539 then load RELOADREG from OLDEQUIV. Note that we cannot use
5540 gen_lowpart_common since it can do the wrong thing when
5541 RELOADREG has a multi-word mode. Note that RELOADREG
5542 must always be a REG here. */
5544 if (GET_MODE (reloadreg
) != mode
)
5545 reloadreg
= gen_rtx (REG
, mode
, REGNO (reloadreg
));
5546 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
5547 oldequiv
= SUBREG_REG (oldequiv
);
5548 if (GET_MODE (oldequiv
) != VOIDmode
5549 && mode
!= GET_MODE (oldequiv
))
5550 oldequiv
= gen_rtx (SUBREG
, mode
, oldequiv
, 0);
5552 /* Switch to the right place to emit the reload insns. */
5553 switch (reload_when_needed
[j
])
5556 where
= &other_input_reload_insns
;
5558 case RELOAD_FOR_INPUT
:
5559 where
= &input_reload_insns
[reload_opnum
[j
]];
5561 case RELOAD_FOR_INPUT_ADDRESS
:
5562 where
= &input_address_reload_insns
[reload_opnum
[j
]];
5564 case RELOAD_FOR_OUTPUT_ADDRESS
:
5565 where
= &output_address_reload_insns
[reload_opnum
[j
]];
5567 case RELOAD_FOR_OPERAND_ADDRESS
:
5568 where
= &operand_reload_insns
;
5570 case RELOAD_FOR_OTHER_ADDRESS
:
5571 where
= &other_input_address_reload_insns
;
5577 push_to_sequence (*where
);
5580 /* Auto-increment addresses must be reloaded in a special way. */
5581 if (GET_CODE (oldequiv
) == POST_INC
5582 || GET_CODE (oldequiv
) == POST_DEC
5583 || GET_CODE (oldequiv
) == PRE_INC
5584 || GET_CODE (oldequiv
) == PRE_DEC
)
5586 /* We are not going to bother supporting the case where a
5587 incremented register can't be copied directly from
5588 OLDEQUIV since this seems highly unlikely. */
5589 if (reload_secondary_reload
[j
] >= 0)
5591 /* Prevent normal processing of this reload. */
5593 /* Output a special code sequence for this case. */
5594 inc_for_reload (reloadreg
, oldequiv
, reload_inc
[j
]);
5597 /* If we are reloading a pseudo-register that was set by the previous
5598 insn, see if we can get rid of that pseudo-register entirely
5599 by redirecting the previous insn into our reload register. */
5601 else if (optimize
&& GET_CODE (old
) == REG
5602 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
5603 && dead_or_set_p (insn
, old
)
5604 /* This is unsafe if some other reload
5605 uses the same reg first. */
5606 && reload_reg_free_before_p (REGNO (reloadreg
),
5608 reload_when_needed
[j
]))
5610 rtx temp
= PREV_INSN (insn
);
5611 while (temp
&& GET_CODE (temp
) == NOTE
)
5612 temp
= PREV_INSN (temp
);
5614 && GET_CODE (temp
) == INSN
5615 && GET_CODE (PATTERN (temp
)) == SET
5616 && SET_DEST (PATTERN (temp
)) == old
5617 /* Make sure we can access insn_operand_constraint. */
5618 && asm_noperands (PATTERN (temp
)) < 0
5619 /* This is unsafe if prev insn rejects our reload reg. */
5620 && constraint_accepts_reg_p (insn_operand_constraint
[recog_memoized (temp
)][0],
5622 /* This is unsafe if operand occurs more than once in current
5623 insn. Perhaps some occurrences aren't reloaded. */
5624 && count_occurrences (PATTERN (insn
), old
) == 1
5625 /* Don't risk splitting a matching pair of operands. */
5626 && ! reg_mentioned_p (old
, SET_SRC (PATTERN (temp
))))
5628 /* Store into the reload register instead of the pseudo. */
5629 SET_DEST (PATTERN (temp
)) = reloadreg
;
5630 /* If these are the only uses of the pseudo reg,
5631 pretend for GDB it lives in the reload reg we used. */
5632 if (reg_n_deaths
[REGNO (old
)] == 1
5633 && reg_n_sets
[REGNO (old
)] == 1)
5635 reg_renumber
[REGNO (old
)] = REGNO (reload_reg_rtx
[j
]);
5636 alter_reg (REGNO (old
), -1);
5642 /* We can't do that, so output an insn to load RELOADREG. */
5646 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5647 rtx second_reload_reg
= 0;
5648 enum insn_code icode
;
5650 /* If we have a secondary reload, pick up the secondary register
5651 and icode, if any. If OLDEQUIV and OLD are different or
5652 if this is an in-out reload, recompute whether or not we
5653 still need a secondary register and what the icode should
5654 be. If we still need a secondary register and the class or
5655 icode is different, go back to reloading from OLD if using
5656 OLDEQUIV means that we got the wrong type of register. We
5657 cannot have different class or icode due to an in-out reload
5658 because we don't make such reloads when both the input and
5659 output need secondary reload registers. */
5661 if (reload_secondary_reload
[j
] >= 0)
5663 int secondary_reload
= reload_secondary_reload
[j
];
5664 rtx real_oldequiv
= oldequiv
;
5667 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
5668 and similarly for OLD.
5669 See comments in find_secondary_reload in reload.c. */
5670 if (GET_CODE (oldequiv
) == REG
5671 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
5672 && reg_equiv_mem
[REGNO (oldequiv
)] != 0)
5673 real_oldequiv
= reg_equiv_mem
[REGNO (oldequiv
)];
5675 if (GET_CODE (old
) == REG
5676 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
5677 && reg_equiv_mem
[REGNO (old
)] != 0)
5678 real_old
= reg_equiv_mem
[REGNO (old
)];
5680 second_reload_reg
= reload_reg_rtx
[secondary_reload
];
5681 icode
= reload_secondary_icode
[j
];
5683 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
5684 || (reload_in
[j
] != 0 && reload_out
[j
] != 0))
5686 enum reg_class new_class
5687 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class
[j
],
5688 mode
, real_oldequiv
);
5690 if (new_class
== NO_REGS
)
5691 second_reload_reg
= 0;
5694 enum insn_code new_icode
;
5695 enum machine_mode new_mode
;
5697 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
],
5698 REGNO (second_reload_reg
)))
5699 oldequiv
= old
, real_oldequiv
= real_old
;
5702 new_icode
= reload_in_optab
[(int) mode
];
5703 if (new_icode
!= CODE_FOR_nothing
5704 && ((insn_operand_predicate
[(int) new_icode
][0]
5705 && ! ((*insn_operand_predicate
[(int) new_icode
][0])
5707 || (insn_operand_predicate
[(int) new_icode
][1]
5708 && ! ((*insn_operand_predicate
[(int) new_icode
][1])
5709 (real_oldequiv
, mode
)))))
5710 new_icode
= CODE_FOR_nothing
;
5712 if (new_icode
== CODE_FOR_nothing
)
5715 new_mode
= insn_operand_mode
[(int) new_icode
][2];
5717 if (GET_MODE (second_reload_reg
) != new_mode
)
5719 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg
),
5721 oldequiv
= old
, real_oldequiv
= real_old
;
5724 = gen_rtx (REG
, new_mode
,
5725 REGNO (second_reload_reg
));
5731 /* If we still need a secondary reload register, check
5732 to see if it is being used as a scratch or intermediate
5733 register and generate code appropriately. If we need
5734 a scratch register, use REAL_OLDEQUIV since the form of
5735 the insn may depend on the actual address if it is
5738 if (second_reload_reg
)
5740 if (icode
!= CODE_FOR_nothing
)
5742 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
5743 second_reload_reg
));
5748 /* See if we need a scratch register to load the
5749 intermediate register (a tertiary reload). */
5750 enum insn_code tertiary_icode
5751 = reload_secondary_icode
[secondary_reload
];
5753 if (tertiary_icode
!= CODE_FOR_nothing
)
5755 rtx third_reload_reg
5756 = reload_reg_rtx
[reload_secondary_reload
[secondary_reload
]];
5758 emit_insn ((GEN_FCN (tertiary_icode
)
5759 (second_reload_reg
, real_oldequiv
,
5760 third_reload_reg
)));
5763 gen_input_reload (second_reload_reg
, oldequiv
,
5765 reload_when_needed
[j
]);
5767 oldequiv
= second_reload_reg
;
5774 gen_input_reload (reloadreg
, oldequiv
, reload_opnum
[j
],
5775 reload_when_needed
[j
]);
5777 #if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P)
5778 /* We may have to make a REG_DEAD note for the secondary reload
5779 register in the insns we just made. Find the last insn that
5780 mentioned the register. */
5781 if (! special
&& second_reload_reg
5782 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg
)))
5786 for (prev
= get_last_insn (); prev
;
5787 prev
= PREV_INSN (prev
))
5788 if (GET_RTX_CLASS (GET_CODE (prev
) == 'i')
5789 && reg_overlap_mentioned_for_reload_p (second_reload_reg
,
5792 REG_NOTES (prev
) = gen_rtx (EXPR_LIST
, REG_DEAD
,
5801 /* End this sequence. */
5802 *where
= get_insns ();
5806 /* Add a note saying the input reload reg
5807 dies in this insn, if anyone cares. */
5808 #ifdef PRESERVE_DEATH_INFO_REGNO_P
5810 && reload_reg_rtx
[j
] != old
5811 && reload_reg_rtx
[j
] != 0
5812 && reload_out
[j
] == 0
5813 && ! reload_inherited
[j
]
5814 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx
[j
])))
5816 register rtx reloadreg
= reload_reg_rtx
[j
];
5819 /* We can't abort here because we need to support this for sched.c.
5820 It's not terrible to miss a REG_DEAD note, but we should try
5821 to figure out how to do this correctly. */
5822 /* The code below is incorrect for address-only reloads. */
5823 if (reload_when_needed
[j
] != RELOAD_OTHER
5824 && reload_when_needed
[j
] != RELOAD_FOR_INPUT
)
5828 /* Add a death note to this insn, for an input reload. */
5830 if ((reload_when_needed
[j
] == RELOAD_OTHER
5831 || reload_when_needed
[j
] == RELOAD_FOR_INPUT
)
5832 && ! dead_or_set_p (insn
, reloadreg
))
5834 = gen_rtx (EXPR_LIST
, REG_DEAD
,
5835 reloadreg
, REG_NOTES (insn
));
5838 /* When we inherit a reload, the last marked death of the reload reg
5839 may no longer really be a death. */
5840 if (reload_reg_rtx
[j
] != 0
5841 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx
[j
]))
5842 && reload_inherited
[j
])
5844 /* Handle inheriting an output reload.
5845 Remove the death note from the output reload insn. */
5846 if (reload_spill_index
[j
] >= 0
5847 && GET_CODE (reload_in
[j
]) == REG
5848 && spill_reg_store
[reload_spill_index
[j
]] != 0
5849 && find_regno_note (spill_reg_store
[reload_spill_index
[j
]],
5850 REG_DEAD
, REGNO (reload_reg_rtx
[j
])))
5851 remove_death (REGNO (reload_reg_rtx
[j
]),
5852 spill_reg_store
[reload_spill_index
[j
]]);
5853 /* Likewise for input reloads that were inherited. */
5854 else if (reload_spill_index
[j
] >= 0
5855 && GET_CODE (reload_in
[j
]) == REG
5856 && spill_reg_store
[reload_spill_index
[j
]] == 0
5857 && reload_inheritance_insn
[j
] != 0
5858 && find_regno_note (reload_inheritance_insn
[j
], REG_DEAD
,
5859 REGNO (reload_reg_rtx
[j
])))
5860 remove_death (REGNO (reload_reg_rtx
[j
]),
5861 reload_inheritance_insn
[j
]);
5866 /* We got this register from find_equiv_reg.
5867 Search back for its last death note and get rid of it.
5868 But don't search back too far.
5869 Don't go past a place where this reg is set,
5870 since a death note before that remains valid. */
5871 for (prev
= PREV_INSN (insn
);
5872 prev
&& GET_CODE (prev
) != CODE_LABEL
;
5873 prev
= PREV_INSN (prev
))
5874 if (GET_RTX_CLASS (GET_CODE (prev
)) == 'i'
5875 && dead_or_set_p (prev
, reload_reg_rtx
[j
]))
5877 if (find_regno_note (prev
, REG_DEAD
,
5878 REGNO (reload_reg_rtx
[j
])))
5879 remove_death (REGNO (reload_reg_rtx
[j
]), prev
);
5885 /* We might have used find_equiv_reg above to choose an alternate
5886 place from which to reload. If so, and it died, we need to remove
5887 that death and move it to one of the insns we just made. */
5889 if (oldequiv_reg
!= 0
5890 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg
)))
5894 for (prev
= PREV_INSN (insn
); prev
&& GET_CODE (prev
) != CODE_LABEL
;
5895 prev
= PREV_INSN (prev
))
5896 if (GET_RTX_CLASS (GET_CODE (prev
)) == 'i'
5897 && dead_or_set_p (prev
, oldequiv_reg
))
5899 if (find_regno_note (prev
, REG_DEAD
, REGNO (oldequiv_reg
)))
5901 for (prev1
= this_reload_insn
;
5902 prev1
; prev1
= PREV_INSN (prev1
))
5903 if (GET_RTX_CLASS (GET_CODE (prev1
) == 'i')
5904 && reg_overlap_mentioned_for_reload_p (oldequiv_reg
,
5907 REG_NOTES (prev1
) = gen_rtx (EXPR_LIST
, REG_DEAD
,
5912 remove_death (REGNO (oldequiv_reg
), prev
);
5919 /* If we are reloading a register that was recently stored in with an
5920 output-reload, see if we can prove there was
5921 actually no need to store the old value in it. */
5923 if (optimize
&& reload_inherited
[j
] && reload_spill_index
[j
] >= 0
5924 && reload_in
[j
] != 0
5925 && GET_CODE (reload_in
[j
]) == REG
5927 /* There doesn't seem to be any reason to restrict this to pseudos
5928 and doing so loses in the case where we are copying from a
5929 register of the wrong class. */
5930 && REGNO (reload_in
[j
]) >= FIRST_PSEUDO_REGISTER
5932 && spill_reg_store
[reload_spill_index
[j
]] != 0
5933 /* This is unsafe if some other reload uses the same reg first. */
5934 && reload_reg_free_before_p (spill_regs
[reload_spill_index
[j
]],
5935 reload_opnum
[j
], reload_when_needed
[j
])
5936 && dead_or_set_p (insn
, reload_in
[j
])
5937 /* This is unsafe if operand occurs more than once in current
5938 insn. Perhaps some occurrences weren't reloaded. */
5939 && count_occurrences (PATTERN (insn
), reload_in
[j
]) == 1)
5940 delete_output_reload (insn
, j
,
5941 spill_reg_store
[reload_spill_index
[j
]]);
5943 /* Input-reloading is done. Now do output-reloading,
5944 storing the value from the reload-register after the main insn
5945 if reload_out[j] is nonzero.
5947 ??? At some point we need to support handling output reloads of
5948 JUMP_INSNs or insns that set cc0. */
5949 old
= reload_out
[j
];
5951 && reload_reg_rtx
[j
] != old
5952 && reload_reg_rtx
[j
] != 0)
5954 register rtx reloadreg
= reload_reg_rtx
[j
];
5955 register rtx second_reloadreg
= 0;
5957 enum machine_mode mode
;
5960 /* An output operand that dies right away does need a reload,
5961 but need not be copied from it. Show the new location in the
5963 if ((GET_CODE (old
) == REG
|| GET_CODE (old
) == SCRATCH
)
5964 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
5966 XEXP (note
, 0) = reload_reg_rtx
[j
];
5969 else if (GET_CODE (old
) == SCRATCH
)
5970 /* If we aren't optimizing, there won't be a REG_UNUSED note,
5971 but we don't want to make an output reload. */
5975 /* Strip off of OLD any size-increasing SUBREGs such as
5976 (SUBREG:SI foo:QI 0). */
5978 while (GET_CODE (old
) == SUBREG
&& SUBREG_WORD (old
) == 0
5979 && (GET_MODE_SIZE (GET_MODE (old
))
5980 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old
)))))
5981 old
= SUBREG_REG (old
);
5984 /* If is a JUMP_INSN, we can't support output reloads yet. */
5985 if (GET_CODE (insn
) == JUMP_INSN
)
5988 push_to_sequence (output_reload_insns
[reload_opnum
[j
]]);
5990 /* Determine the mode to reload in.
5991 See comments above (for input reloading). */
5993 mode
= GET_MODE (old
);
5994 if (mode
== VOIDmode
)
5996 /* VOIDmode should never happen for an output. */
5997 if (asm_noperands (PATTERN (insn
)) < 0)
5998 /* It's the compiler's fault. */
6000 error_for_asm (insn
, "output operand is constant in `asm'");
6001 /* Prevent crash--use something we know is valid. */
6003 old
= gen_rtx (REG
, mode
, REGNO (reloadreg
));
6006 if (GET_MODE (reloadreg
) != mode
)
6007 reloadreg
= gen_rtx (REG
, mode
, REGNO (reloadreg
));
6009 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6011 /* If we need two reload regs, set RELOADREG to the intermediate
6012 one, since it will be stored into OUT. We might need a secondary
6013 register only for an input reload, so check again here. */
6015 if (reload_secondary_reload
[j
] >= 0)
6019 if (GET_CODE (old
) == REG
&& REGNO (old
) >= FIRST_PSEUDO_REGISTER
6020 && reg_equiv_mem
[REGNO (old
)] != 0)
6021 real_old
= reg_equiv_mem
[REGNO (old
)];
6023 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class
[j
],
6027 second_reloadreg
= reloadreg
;
6028 reloadreg
= reload_reg_rtx
[reload_secondary_reload
[j
]];
6030 /* See if RELOADREG is to be used as a scratch register
6031 or as an intermediate register. */
6032 if (reload_secondary_icode
[j
] != CODE_FOR_nothing
)
6034 emit_insn ((GEN_FCN (reload_secondary_icode
[j
])
6035 (real_old
, second_reloadreg
, reloadreg
)));
6040 /* See if we need both a scratch and intermediate reload
6042 int secondary_reload
= reload_secondary_reload
[j
];
6043 enum insn_code tertiary_icode
6044 = reload_secondary_icode
[secondary_reload
];
6047 if (GET_MODE (reloadreg
) != mode
)
6048 reloadreg
= gen_rtx (REG
, mode
, REGNO (reloadreg
));
6050 if (tertiary_icode
!= CODE_FOR_nothing
)
6053 = reload_reg_rtx
[reload_secondary_reload
[secondary_reload
]];
6054 pat
= (GEN_FCN (tertiary_icode
)
6055 (reloadreg
, second_reloadreg
, third_reloadreg
));
6057 #ifdef SECONDARY_MEMORY_NEEDED
6058 /* If we need a memory location to do the move, do it that way. */
6059 else if (GET_CODE (reloadreg
) == REG
6060 && REGNO (reloadreg
) < FIRST_PSEUDO_REGISTER
6061 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (reloadreg
)),
6062 REGNO_REG_CLASS (REGNO (second_reloadreg
)),
6063 GET_MODE (second_reloadreg
)))
6065 /* Get the memory to use and rewrite both registers
6068 = get_secondary_mem (reloadreg
,
6069 GET_MODE (second_reloadreg
),
6071 reload_when_needed
[j
]);
6074 if (GET_MODE (loc
) != GET_MODE (second_reloadreg
))
6075 second_reloadreg
= gen_rtx (REG
, GET_MODE (loc
),
6076 REGNO (second_reloadreg
));
6078 if (GET_MODE (loc
) != GET_MODE (reloadreg
))
6079 tmp_reloadreg
= gen_rtx (REG
, GET_MODE (loc
),
6082 tmp_reloadreg
= reloadreg
;
6084 emit_move_insn (loc
, second_reloadreg
);
6085 pat
= gen_move_insn (tmp_reloadreg
, loc
);
6089 pat
= gen_move_insn (reloadreg
, second_reloadreg
);
6097 /* Output the last reload insn. */
6100 #ifdef SECONDARY_MEMORY_NEEDED
6101 /* If we need a memory location to do the move, do it that way. */
6102 if (GET_CODE (old
) == REG
&& REGNO (old
) < FIRST_PSEUDO_REGISTER
6103 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (old
)),
6104 REGNO_REG_CLASS (REGNO (reloadreg
)),
6105 GET_MODE (reloadreg
)))
6107 /* Get the memory to use and rewrite both registers to
6109 rtx loc
= get_secondary_mem (old
, GET_MODE (reloadreg
),
6111 reload_when_needed
[j
]);
6113 if (GET_MODE (loc
) != GET_MODE (reloadreg
))
6114 reloadreg
= gen_rtx (REG
, GET_MODE (loc
),
6117 if (GET_MODE (loc
) != GET_MODE (old
))
6118 old
= gen_rtx (REG
, GET_MODE (loc
), REGNO (old
));
6120 emit_insn (gen_move_insn (loc
, reloadreg
));
6121 emit_insn (gen_move_insn (old
, loc
));
6125 emit_insn (gen_move_insn (old
, reloadreg
));
6128 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6129 /* If final will look at death notes for this reg,
6130 put one on the last output-reload insn to use it. Similarly
6131 for any secondary register. */
6132 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg
)))
6133 for (p
= get_last_insn (); p
; p
= PREV_INSN (p
))
6134 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
6135 && reg_overlap_mentioned_for_reload_p (reloadreg
,
6137 REG_NOTES (p
) = gen_rtx (EXPR_LIST
, REG_DEAD
,
6138 reloadreg
, REG_NOTES (p
));
6140 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6142 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg
)))
6143 for (p
= get_last_insn (); p
; p
= PREV_INSN (p
))
6144 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
6145 && reg_overlap_mentioned_for_reload_p (second_reloadreg
,
6147 REG_NOTES (p
) = gen_rtx (EXPR_LIST
, REG_DEAD
,
6148 second_reloadreg
, REG_NOTES (p
));
6151 /* Look at all insns we emitted, just to be safe. */
6152 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
6153 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i')
6155 /* If this output reload doesn't come from a spill reg,
6156 clear any memory of reloaded copies of the pseudo reg.
6157 If this output reload comes from a spill reg,
6158 reg_has_output_reload will make this do nothing. */
6159 note_stores (PATTERN (p
), forget_old_reloads_1
);
6161 if (reg_mentioned_p (reload_reg_rtx
[j
], PATTERN (p
)))
6165 output_reload_insns
[reload_opnum
[j
]] = get_insns ();
6170 if (reload_spill_index
[j
] >= 0)
6171 new_spill_reg_store
[reload_spill_index
[j
]] = store_insn
;
6174 /* Now write all the insns we made for reloads in the order expected by
6175 the allocation functions. Prior to the insn being reloaded, we write
6176 the following reloads:
6178 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6180 RELOAD_OTHER reloads.
6182 For each operand, any RELOAD_FOR_INPUT_ADDRESS reloads followed by
6183 the RELOAD_FOR_INPUT reload for the operand.
6185 RELOAD_FOR_OPERAND_ADDRESS reloads.
6187 After the insn being reloaded, we write the following:
6189 For each operand, any RELOAD_FOR_OUTPUT_ADDRESS reload followed by
6190 the RELOAD_FOR_OUTPUT reload for that operand. */
6192 emit_insns_before (other_input_address_reload_insns
, before_insn
);
6193 emit_insns_before (other_input_reload_insns
, before_insn
);
6195 for (j
= 0; j
< reload_n_operands
; j
++)
6197 emit_insns_before (input_address_reload_insns
[j
], before_insn
);
6198 emit_insns_before (input_reload_insns
[j
], before_insn
);
6201 emit_insns_before (operand_reload_insns
, before_insn
);
6203 for (j
= 0; j
< reload_n_operands
; j
++)
6205 emit_insns_before (output_address_reload_insns
[j
], following_insn
);
6206 emit_insns_before (output_reload_insns
[j
], following_insn
);
6209 /* Move death notes from INSN
6210 to output-operand-address and output reload insns. */
6211 #ifdef PRESERVE_DEATH_INFO_REGNO_P
6214 /* Loop over those insns, last ones first. */
6215 for (insn1
= PREV_INSN (following_insn
); insn1
!= insn
;
6216 insn1
= PREV_INSN (insn1
))
6217 if (GET_CODE (insn1
) == INSN
&& GET_CODE (PATTERN (insn1
)) == SET
)
6219 rtx source
= SET_SRC (PATTERN (insn1
));
6220 rtx dest
= SET_DEST (PATTERN (insn1
));
6222 /* The note we will examine next. */
6223 rtx reg_notes
= REG_NOTES (insn
);
6224 /* The place that pointed to this note. */
6225 rtx
*prev_reg_note
= ®_NOTES (insn
);
6227 /* If the note is for something used in the source of this
6228 reload insn, or in the output address, move the note. */
6231 rtx next_reg_notes
= XEXP (reg_notes
, 1);
6232 if (REG_NOTE_KIND (reg_notes
) == REG_DEAD
6233 && GET_CODE (XEXP (reg_notes
, 0)) == REG
6234 && ((GET_CODE (dest
) != REG
6235 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes
, 0),
6237 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes
, 0),
6240 *prev_reg_note
= next_reg_notes
;
6241 XEXP (reg_notes
, 1) = REG_NOTES (insn1
);
6242 REG_NOTES (insn1
) = reg_notes
;
6245 prev_reg_note
= &XEXP (reg_notes
, 1);
6247 reg_notes
= next_reg_notes
;
6253 /* For all the spill regs newly reloaded in this instruction,
6254 record what they were reloaded from, so subsequent instructions
6255 can inherit the reloads.
6257 Update spill_reg_store for the reloads of this insn.
6258 Copy the elements that were updated in the loop above. */
6260 for (j
= 0; j
< n_reloads
; j
++)
6262 register int r
= reload_order
[j
];
6263 register int i
= reload_spill_index
[r
];
6265 /* I is nonneg if this reload used one of the spill regs.
6266 If reload_reg_rtx[r] is 0, this is an optional reload
6267 that we opted to ignore.
6269 Also ignore reloads that don't reach the end of the insn,
6270 since we will eventually see the one that does. */
6272 if (i
>= 0 && reload_reg_rtx
[r
] != 0
6273 && reload_reg_reaches_end_p (spill_regs
[i
], reload_opnum
[r
],
6274 reload_when_needed
[r
]))
6276 /* First, clear out memory of what used to be in this spill reg.
6277 If consecutive registers are used, clear them all. */
6279 = HARD_REGNO_NREGS (spill_regs
[i
], GET_MODE (reload_reg_rtx
[r
]));
6282 for (k
= 0; k
< nr
; k
++)
6284 reg_reloaded_contents
[spill_reg_order
[spill_regs
[i
] + k
]] = -1;
6285 reg_reloaded_insn
[spill_reg_order
[spill_regs
[i
] + k
]] = 0;
6288 /* Maybe the spill reg contains a copy of reload_out. */
6289 if (reload_out
[r
] != 0 && GET_CODE (reload_out
[r
]) == REG
)
6291 register int nregno
= REGNO (reload_out
[r
]);
6292 int nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
6293 : HARD_REGNO_NREGS (nregno
,
6294 GET_MODE (reload_reg_rtx
[r
])));
6296 spill_reg_store
[i
] = new_spill_reg_store
[i
];
6297 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
6299 /* If NREGNO is a hard register, it may occupy more than
6300 one register. If it does, say what is in the
6301 rest of the registers assuming that both registers
6302 agree on how many words the object takes. If not,
6303 invalidate the subsequent registers. */
6305 if (nregno
< FIRST_PSEUDO_REGISTER
)
6306 for (k
= 1; k
< nnr
; k
++)
6307 reg_last_reload_reg
[nregno
+ k
]
6308 = (nr
== nnr
? gen_rtx (REG
, word_mode
,
6309 REGNO (reload_reg_rtx
[r
]) + k
)
6312 /* Now do the inverse operation. */
6313 for (k
= 0; k
< nr
; k
++)
6315 reg_reloaded_contents
[spill_reg_order
[spill_regs
[i
] + k
]]
6316 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
? nregno
6318 reg_reloaded_insn
[spill_reg_order
[spill_regs
[i
] + k
]] = insn
;
6322 /* Maybe the spill reg contains a copy of reload_in. Only do
6323 something if there will not be an output reload for
6324 the register being reloaded. */
6325 else if (reload_out
[r
] == 0
6326 && reload_in
[r
] != 0
6327 && ((GET_CODE (reload_in
[r
]) == REG
6328 && ! reg_has_output_reload
[REGNO (reload_in
[r
])]
6329 || (GET_CODE (reload_in_reg
[r
]) == REG
6330 && ! reg_has_output_reload
[REGNO (reload_in_reg
[r
])]))))
6332 register int nregno
;
6335 if (GET_CODE (reload_in
[r
]) == REG
)
6336 nregno
= REGNO (reload_in
[r
]);
6338 nregno
= REGNO (reload_in_reg
[r
]);
6340 nnr
= (nregno
>= FIRST_PSEUDO_REGISTER
? 1
6341 : HARD_REGNO_NREGS (nregno
,
6342 GET_MODE (reload_reg_rtx
[r
])));
6344 reg_last_reload_reg
[nregno
] = reload_reg_rtx
[r
];
6346 if (nregno
< FIRST_PSEUDO_REGISTER
)
6347 for (k
= 1; k
< nnr
; k
++)
6348 reg_last_reload_reg
[nregno
+ k
]
6349 = (nr
== nnr
? gen_rtx (REG
, word_mode
,
6350 REGNO (reload_reg_rtx
[r
]) + k
)
6353 /* Unless we inherited this reload, show we haven't
6354 recently done a store. */
6355 if (! reload_inherited
[r
])
6356 spill_reg_store
[i
] = 0;
6358 for (k
= 0; k
< nr
; k
++)
6360 reg_reloaded_contents
[spill_reg_order
[spill_regs
[i
] + k
]]
6361 = (nregno
>= FIRST_PSEUDO_REGISTER
|| nr
!= nnr
? nregno
6363 reg_reloaded_insn
[spill_reg_order
[spill_regs
[i
] + k
]]
6369 /* The following if-statement was #if 0'd in 1.34 (or before...).
6370 It's reenabled in 1.35 because supposedly nothing else
6371 deals with this problem. */
6373 /* If a register gets output-reloaded from a non-spill register,
6374 that invalidates any previous reloaded copy of it.
6375 But forget_old_reloads_1 won't get to see it, because
6376 it thinks only about the original insn. So invalidate it here. */
6377 if (i
< 0 && reload_out
[r
] != 0 && GET_CODE (reload_out
[r
]) == REG
)
6379 register int nregno
= REGNO (reload_out
[r
]);
6380 reg_last_reload_reg
[nregno
] = 0;
6385 /* Emit code to perform an input reload of IN to RELOADREG. IN is from
6386 operand OPNUM with reload type TYPE.
6388 Returns first insn emitted. */
6391 gen_input_reload (reloadreg
, in
, opnum
, type
)
6395 enum reload_type type
;
6397 rtx last
= get_last_insn ();
6399 /* How to do this reload can get quite tricky. Normally, we are being
6400 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
6401 register that didn't get a hard register. In that case we can just
6402 call emit_move_insn.
6404 We can also be asked to reload a PLUS that adds either two registers, or
6405 a register and a constant or MEM, or a MEM and a constant. This can
6406 occur during frame pointer elimination and while reloading addresses.
6407 This case is handled by trying to emit a single insn
6408 to perform the add. If it is not valid, we use a two insn sequence.
6410 Finally, we could be called to handle an 'o' constraint by putting
6411 an address into a register. In that case, we first try to do this
6412 with a named pattern of "reload_load_address". If no such pattern
6413 exists, we just emit a SET insn and hope for the best (it will normally
6414 be valid on machines that use 'o').
6416 This entire process is made complex because reload will never
6417 process the insns we generate here and so we must ensure that
6418 they will fit their constraints and also by the fact that parts of
6419 IN might be being reloaded separately and replaced with spill registers.
6420 Because of this, we are, in some sense, just guessing the right approach
6421 here. The one listed above seems to work.
6423 ??? At some point, this whole thing needs to be rethought. */
6425 if (GET_CODE (in
) == PLUS
6426 && ((GET_CODE (XEXP (in
, 0)) == REG
6427 && (GET_CODE (XEXP (in
, 1)) == REG
6428 || CONSTANT_P (XEXP (in
, 1))
6429 || GET_CODE (XEXP (in
, 1)) == MEM
))
6430 || (GET_CODE (XEXP (in
, 0)) == MEM
6431 && CONSTANT_P (XEXP (in
, 1)))))
6433 /* We need to compute the sum of what is either a register and a
6434 constant, a register and memory, a hard register and a pseudo
6435 register, or memory and a constant and put it into the reload
6436 register. The best possible way of doing this is if the machine
6437 has a three-operand ADD insn that accepts the required operands.
6439 The simplest approach is to try to generate such an insn and see if it
6440 is recognized and matches its constraints. If so, it can be used.
6442 It might be better not to actually emit the insn unless it is valid,
6443 but we need to pass the insn as an operand to `recog' and
6444 `insn_extract' and it is simpler to emit and then delete the insn if
6445 not valid than to dummy things up. */
6447 rtx op0
, op1
, tem
, insn
;
6450 op0
= find_replacement (&XEXP (in
, 0));
6451 op1
= find_replacement (&XEXP (in
, 1));
6453 /* Since constraint checking is strict, commutativity won't be
6454 checked, so we need to do that here to avoid spurious failure
6455 if the add instruction is two-address and the second operand
6456 of the add is the same as the reload reg, which is frequently
6457 the case. If the insn would be A = B + A, rearrange it so
6458 it will be A = A + B as constrain_operands expects. */
6460 if (GET_CODE (XEXP (in
, 1)) == REG
6461 && REGNO (reloadreg
) == REGNO (XEXP (in
, 1)))
6462 tem
= op0
, op0
= op1
, op1
= tem
;
6464 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
6465 in
= gen_rtx (PLUS
, GET_MODE (in
), op0
, op1
);
6467 insn
= emit_insn (gen_rtx (SET
, VOIDmode
, reloadreg
, in
));
6468 code
= recog_memoized (insn
);
6472 insn_extract (insn
);
6473 /* We want constrain operands to treat this insn strictly in
6474 its validity determination, i.e., the way it would after reload
6476 if (constrain_operands (code
, 1))
6480 delete_insns_since (last
);
6482 /* If that failed, we must use a conservative two-insn sequence.
6483 use move to copy constant, MEM, or pseudo register to the reload
6484 register since "move" will be able to handle an arbitrary operand,
6485 unlike add which can't, in general. Then add the registers.
6487 If there is another way to do this for a specific machine, a
6488 DEFINE_PEEPHOLE should be specified that recognizes the sequence
6491 if (CONSTANT_P (op1
) || GET_CODE (op1
) == MEM
6492 || (GET_CODE (op1
) == REG
6493 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
))
6494 tem
= op0
, op0
= op1
, op1
= tem
;
6496 emit_insn (gen_move_insn (reloadreg
, op0
));
6498 /* If OP0 and OP1 are the same, we can use RELOADREG for OP1.
6499 This fixes a problem on the 32K where the stack pointer cannot
6500 be used as an operand of an add insn. */
6502 if (rtx_equal_p (op0
, op1
))
6505 emit_insn (gen_add2_insn (reloadreg
, op1
));
6508 #ifdef SECONDARY_MEMORY_NEEDED
6509 /* If we need a memory location to do the move, do it that way. */
6510 else if (GET_CODE (in
) == REG
&& REGNO (in
) < FIRST_PSEUDO_REGISTER
6511 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in
)),
6512 REGNO_REG_CLASS (REGNO (reloadreg
)),
6513 GET_MODE (reloadreg
)))
6515 /* Get the memory to use and rewrite both registers to its mode. */
6516 rtx loc
= get_secondary_mem (in
, GET_MODE (reloadreg
), opnum
, type
);
6518 if (GET_MODE (loc
) != GET_MODE (reloadreg
))
6519 reloadreg
= gen_rtx (REG
, GET_MODE (loc
), REGNO (reloadreg
));
6521 if (GET_MODE (loc
) != GET_MODE (in
))
6522 in
= gen_rtx (REG
, GET_MODE (loc
), REGNO (in
));
6524 emit_insn (gen_move_insn (loc
, in
));
6525 emit_insn (gen_move_insn (reloadreg
, loc
));
6529 /* If IN is a simple operand, use gen_move_insn. */
6530 else if (GET_RTX_CLASS (GET_CODE (in
)) == 'o' || GET_CODE (in
) == SUBREG
)
6531 emit_insn (gen_move_insn (reloadreg
, in
));
6533 #ifdef HAVE_reload_load_address
6534 else if (HAVE_reload_load_address
)
6535 emit_insn (gen_reload_load_address (reloadreg
, in
));
6538 /* Otherwise, just write (set REGLOADREG IN) and hope for the best. */
6540 emit_insn (gen_rtx (SET
, VOIDmode
, reloadreg
, in
));
6542 /* Return the first insn emitted.
6543 We can not just return get_last_insn, because there may have
6544 been multiple instructions emitted. Also note that gen_move_insn may
6545 emit more than one insn itself, so we can not assume that there is one
6546 insn emitted per emit_insn_before call. */
6548 return last
? NEXT_INSN (last
) : get_insns ();
6551 /* Delete a previously made output-reload
6552 whose result we now believe is not needed.
6553 First we double-check.
6555 INSN is the insn now being processed.
6556 OUTPUT_RELOAD_INSN is the insn of the output reload.
6557 J is the reload-number for this insn. */
6560 delete_output_reload (insn
, j
, output_reload_insn
)
6563 rtx output_reload_insn
;
6567 /* Get the raw pseudo-register referred to. */
6569 rtx reg
= reload_in
[j
];
6570 while (GET_CODE (reg
) == SUBREG
)
6571 reg
= SUBREG_REG (reg
);
6573 /* If the pseudo-reg we are reloading is no longer referenced
6574 anywhere between the store into it and here,
6575 and no jumps or labels intervene, then the value can get
6576 here through the reload reg alone.
6577 Otherwise, give up--return. */
6578 for (i1
= NEXT_INSN (output_reload_insn
);
6579 i1
!= insn
; i1
= NEXT_INSN (i1
))
6581 if (GET_CODE (i1
) == CODE_LABEL
|| GET_CODE (i1
) == JUMP_INSN
)
6583 if ((GET_CODE (i1
) == INSN
|| GET_CODE (i1
) == CALL_INSN
)
6584 && reg_mentioned_p (reg
, PATTERN (i1
)))
6588 if (cannot_omit_stores
[REGNO (reg
)])
6591 /* If this insn will store in the pseudo again,
6592 the previous store can be removed. */
6593 if (reload_out
[j
] == reload_in
[j
])
6594 delete_insn (output_reload_insn
);
6596 /* See if the pseudo reg has been completely replaced
6597 with reload regs. If so, delete the store insn
6598 and forget we had a stack slot for the pseudo. */
6599 else if (reg_n_deaths
[REGNO (reg
)] == 1
6600 && reg_basic_block
[REGNO (reg
)] >= 0
6601 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
6605 /* We know that it was used only between here
6606 and the beginning of the current basic block.
6607 (We also know that the last use before INSN was
6608 the output reload we are thinking of deleting, but never mind that.)
6609 Search that range; see if any ref remains. */
6610 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
6612 rtx set
= single_set (i2
);
6614 /* Uses which just store in the pseudo don't count,
6615 since if they are the only uses, they are dead. */
6616 if (set
!= 0 && SET_DEST (set
) == reg
)
6618 if (GET_CODE (i2
) == CODE_LABEL
6619 || GET_CODE (i2
) == JUMP_INSN
)
6621 if ((GET_CODE (i2
) == INSN
|| GET_CODE (i2
) == CALL_INSN
)
6622 && reg_mentioned_p (reg
, PATTERN (i2
)))
6623 /* Some other ref remains;
6624 we can't do anything. */
6628 /* Delete the now-dead stores into this pseudo. */
6629 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
6631 rtx set
= single_set (i2
);
6633 if (set
!= 0 && SET_DEST (set
) == reg
)
6635 if (GET_CODE (i2
) == CODE_LABEL
6636 || GET_CODE (i2
) == JUMP_INSN
)
6640 /* For the debugging info,
6641 say the pseudo lives in this reload reg. */
6642 reg_renumber
[REGNO (reg
)] = REGNO (reload_reg_rtx
[j
]);
6643 alter_reg (REGNO (reg
), -1);
6647 /* Output reload-insns to reload VALUE into RELOADREG.
6648 VALUE is an autoincrement or autodecrement RTX whose operand
6649 is a register or memory location;
6650 so reloading involves incrementing that location.
6652 INC_AMOUNT is the number to increment or decrement by (always positive).
6653 This cannot be deduced from VALUE. */
6656 inc_for_reload (reloadreg
, value
, inc_amount
)
6661 /* REG or MEM to be copied and incremented. */
6662 rtx incloc
= XEXP (value
, 0);
6663 /* Nonzero if increment after copying. */
6664 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
);
6670 /* No hard register is equivalent to this register after
6671 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
6672 we could inc/dec that register as well (maybe even using it for
6673 the source), but I'm not sure it's worth worrying about. */
6674 if (GET_CODE (incloc
) == REG
)
6675 reg_last_reload_reg
[REGNO (incloc
)] = 0;
6677 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
6678 inc_amount
= - inc_amount
;
6680 inc
= GEN_INT (inc_amount
);
6682 /* If this is post-increment, first copy the location to the reload reg. */
6684 emit_insn (gen_move_insn (reloadreg
, incloc
));
6686 /* See if we can directly increment INCLOC. Use a method similar to that
6687 in gen_input_reload. */
6689 last
= get_last_insn ();
6690 add_insn
= emit_insn (gen_rtx (SET
, VOIDmode
, incloc
,
6691 gen_rtx (PLUS
, GET_MODE (incloc
),
6694 code
= recog_memoized (add_insn
);
6697 insn_extract (add_insn
);
6698 if (constrain_operands (code
, 1))
6700 /* If this is a pre-increment and we have incremented the value
6701 where it lives, copy the incremented value to RELOADREG to
6702 be used as an address. */
6705 emit_insn (gen_move_insn (reloadreg
, incloc
));
6711 delete_insns_since (last
);
6713 /* If couldn't do the increment directly, must increment in RELOADREG.
6714 The way we do this depends on whether this is pre- or post-increment.
6715 For pre-increment, copy INCLOC to the reload register, increment it
6716 there, then save back. */
6720 emit_insn (gen_move_insn (reloadreg
, incloc
));
6721 emit_insn (gen_add2_insn (reloadreg
, inc
));
6722 emit_insn (gen_move_insn (incloc
, reloadreg
));
6727 Because this might be a jump insn or a compare, and because RELOADREG
6728 may not be available after the insn in an input reload, we must do
6729 the incrementation before the insn being reloaded for.
6731 We have already copied INCLOC to RELOADREG. Increment the copy in
6732 RELOADREG, save that back, then decrement RELOADREG so it has
6733 the original value. */
6735 emit_insn (gen_add2_insn (reloadreg
, inc
));
6736 emit_insn (gen_move_insn (incloc
, reloadreg
));
6737 emit_insn (gen_add2_insn (reloadreg
, GEN_INT (-inc_amount
)));
6743 /* Return 1 if we are certain that the constraint-string STRING allows
6744 the hard register REG. Return 0 if we can't be sure of this. */
6747 constraint_accepts_reg_p (string
, reg
)
6752 int regno
= true_regnum (reg
);
6755 /* Initialize for first alternative. */
6757 /* Check that each alternative contains `g' or `r'. */
6759 switch (c
= *string
++)
6762 /* If an alternative lacks `g' or `r', we lose. */
6765 /* If an alternative lacks `g' or `r', we lose. */
6768 /* Initialize for next alternative. */
6773 /* Any general reg wins for this alternative. */
6774 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) GENERAL_REGS
], regno
))
6778 /* Any reg in specified class wins for this alternative. */
6780 enum reg_class
class = REG_CLASS_FROM_LETTER (c
);
6782 if (TEST_HARD_REG_BIT (reg_class_contents
[(int) class], regno
))
6788 /* Return the number of places FIND appears within X, but don't count
6789 an occurrence if some SET_DEST is FIND. */
6792 count_occurrences (x
, find
)
6793 register rtx x
, find
;
6796 register enum rtx_code code
;
6797 register char *format_ptr
;
6805 code
= GET_CODE (x
);
6820 if (SET_DEST (x
) == find
)
6821 return count_occurrences (SET_SRC (x
), find
);
6825 format_ptr
= GET_RTX_FORMAT (code
);
6828 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6830 switch (*format_ptr
++)
6833 count
+= count_occurrences (XEXP (x
, i
), find
);
6837 if (XVEC (x
, i
) != NULL
)
6839 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
6840 count
+= count_occurrences (XVECEXP (x
, i
, j
), find
);