1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This file contains two passes of the compiler: reg_scan and reg_class.
22 It also defines some tables of information about the hardware registers
23 and a function init_reg_sets to initialize the tables. */
27 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
36 #ifndef REGISTER_MOVE_COST
37 #define REGISTER_MOVE_COST(x, y) 2
40 #ifndef MEMORY_MOVE_COST
41 #define MEMORY_MOVE_COST(x) 4
44 /* If we have auto-increment or auto-decrement and we can have secondary
45 reloads, we are not allowed to use classes requiring secondary
46 reloads for psuedos auto-incremented since reload can't handle it. */
49 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
50 #define FORBIDDEN_INC_DEC_CLASSES
54 /* Register tables used by many passes. */
56 /* Indexed by hard register number, contains 1 for registers
57 that are fixed use (stack pointer, pc, frame pointer, etc.).
58 These are the registers that cannot be used to allocate
59 a pseudo reg whose life does not cross calls. */
61 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
63 /* Same info as a HARD_REG_SET. */
65 HARD_REG_SET fixed_reg_set
;
67 /* Data for initializing the above. */
69 static char initial_fixed_regs
[] = FIXED_REGISTERS
;
71 /* Indexed by hard register number, contains 1 for registers
72 that are fixed use or are clobbered by function calls.
73 These are the registers that cannot be used to allocate
74 a pseudo reg whose life crosses calls. */
76 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
78 /* Same info as a HARD_REG_SET. */
80 HARD_REG_SET call_used_reg_set
;
82 /* Data for initializing the above. */
84 static char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
86 /* Indexed by hard register number, contains 1 for registers that are
87 fixed use -- i.e. in fixed_regs -- or a function value return register
88 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
89 registers that cannot hold quantities across calls even if we are
90 willing to save and restore them. */
92 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
94 /* The same info as a HARD_REG_SET. */
96 HARD_REG_SET call_fixed_reg_set
;
98 /* Number of non-fixed registers. */
100 int n_non_fixed_regs
;
102 /* Indexed by hard register number, contains 1 for registers
103 that are being used for global register decls.
104 These must be exempt from ordinary flow analysis
105 and are also considered fixed. */
107 char global_regs
[FIRST_PSEUDO_REGISTER
];
109 /* Table of register numbers in the order in which to try to use them. */
110 #ifdef REG_ALLOC_ORDER
111 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
114 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
116 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
118 /* The same information, but as an array of unsigned ints. We copy from
119 these unsigned ints to the table above. We do this so the tm.h files
120 do not have to be aware of the wordsize for machines with <= 64 regs. */
123 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
125 static unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
126 = REG_CLASS_CONTENTS
;
128 /* For each reg class, number of regs it contains. */
130 int reg_class_size
[N_REG_CLASSES
];
132 /* For each reg class, table listing all the containing classes. */
134 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
136 /* For each reg class, table listing all the classes contained in it. */
138 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
140 /* For each pair of reg classes,
141 a largest reg class contained in their union. */
143 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
145 /* For each pair of reg classes,
146 the smallest reg class containing their union. */
148 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
150 /* Array containing all of the register names */
152 char *reg_names
[] = REGISTER_NAMES
;
154 /* Indexed by n, gives number of times (REG n) is set or clobbered.
155 This information remains valid for the rest of the compilation
156 of the current function; it is used to control register allocation.
158 This information applies to both hard registers and pseudo registers,
159 unlike much of the information above. */
163 /* Maximum cost of moving from a register in one class to a register in
164 another class. Based on REGISTER_MOVE_COST. */
166 static int move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
168 /* Similar, but here we don't have to move if the first index is a subset
169 of the second so in that case the cost is zero. */
171 static int may_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
173 #ifdef FORBIDDEN_INC_DEC_CLASSES
175 /* These are the classes that regs which are auto-incremented or decremented
178 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
180 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
183 static char *in_inc_dec
;
185 #endif /* FORBIDDEN_INC_DEC_CLASSES */
187 /* Function called only once to initialize the above data on reg usage.
188 Once this is done, various switches may override. */
195 /* First copy the register information from the initial int form into
198 for (i
= 0; i
< N_REG_CLASSES
; i
++)
200 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
202 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
203 if (int_reg_class_contents
[i
][j
/ HOST_BITS_PER_INT
]
204 & ((unsigned) 1 << (j
% HOST_BITS_PER_INT
)))
205 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
208 bcopy (initial_fixed_regs
, fixed_regs
, sizeof fixed_regs
);
209 bcopy (initial_call_used_regs
, call_used_regs
, sizeof call_used_regs
);
210 bzero (global_regs
, sizeof global_regs
);
212 /* Compute number of hard regs in each class. */
214 bzero (reg_class_size
, sizeof reg_class_size
);
215 for (i
= 0; i
< N_REG_CLASSES
; i
++)
216 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
217 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
220 /* Initialize the table of subunions.
221 reg_class_subunion[I][J] gets the largest-numbered reg-class
222 that is contained in the union of classes I and J. */
224 for (i
= 0; i
< N_REG_CLASSES
; i
++)
226 for (j
= 0; j
< N_REG_CLASSES
; j
++)
229 register /* Declare it register if it's a scalar. */
234 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
235 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
236 for (k
= 0; k
< N_REG_CLASSES
; k
++)
238 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
243 /* keep the largest subclass */ /* SPEE 900308 */
244 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
245 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
247 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
254 /* Initialize the table of superunions.
255 reg_class_superunion[I][J] gets the smallest-numbered reg-class
256 containing the union of classes I and J. */
258 for (i
= 0; i
< N_REG_CLASSES
; i
++)
260 for (j
= 0; j
< N_REG_CLASSES
; j
++)
263 register /* Declare it register if it's a scalar. */
268 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
269 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
270 for (k
= 0; k
< N_REG_CLASSES
; k
++)
271 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
274 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
278 /* Initialize the tables of subclasses and superclasses of each reg class.
279 First clear the whole table, then add the elements as they are found. */
281 for (i
= 0; i
< N_REG_CLASSES
; i
++)
283 for (j
= 0; j
< N_REG_CLASSES
; j
++)
285 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
286 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
290 for (i
= 0; i
< N_REG_CLASSES
; i
++)
292 if (i
== (int) NO_REGS
)
295 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
299 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
303 /* Reg class I is a subclass of J.
304 Add J to the table of superclasses of I. */
305 p
= ®_class_superclasses
[i
][0];
306 while (*p
!= LIM_REG_CLASSES
) p
++;
307 *p
= (enum reg_class
) j
;
308 /* Add I to the table of superclasses of J. */
309 p
= ®_class_subclasses
[j
][0];
310 while (*p
!= LIM_REG_CLASSES
) p
++;
311 *p
= (enum reg_class
) i
;
315 /* Initialize the move cost table. Find every subset of each class
316 and take the maximum cost of moving any subset to any other. */
318 for (i
= 0; i
< N_REG_CLASSES
; i
++)
319 for (j
= 0; j
< N_REG_CLASSES
; j
++)
321 int cost
= i
== j
? 2 : REGISTER_MOVE_COST (i
, j
);
322 enum reg_class
*p1
, *p2
;
324 for (p2
= ®_class_subclasses
[j
][0]; *p2
!= LIM_REG_CLASSES
; p2
++)
326 cost
= MAX (cost
, REGISTER_MOVE_COST (i
, *p2
));
328 for (p1
= ®_class_subclasses
[i
][0]; *p1
!= LIM_REG_CLASSES
; p1
++)
331 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, j
));
333 for (p2
= ®_class_subclasses
[j
][0];
334 *p2
!= LIM_REG_CLASSES
; p2
++)
336 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, *p2
));
339 move_cost
[i
][j
] = cost
;
341 if (reg_class_subset_p (i
, j
))
344 may_move_cost
[i
][j
] = cost
;
348 /* After switches have been processed, which perhaps alter
349 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
356 /* This macro allows the fixed or call-used registers
357 to depend on target flags. */
359 #ifdef CONDITIONAL_REGISTER_USAGE
360 CONDITIONAL_REGISTER_USAGE
;
363 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
366 if (call_used_regs
[i
] && ! fixed_regs
[i
])
367 warning ("call-clobbered register used for global register variable");
369 /* Prevent saving/restoring of this reg. */
370 call_used_regs
[i
] = 1;
373 /* Initialize "constant" tables. */
375 CLEAR_HARD_REG_SET (fixed_reg_set
);
376 CLEAR_HARD_REG_SET (call_used_reg_set
);
377 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
379 bcopy (fixed_regs
, call_fixed_regs
, sizeof call_fixed_regs
);
380 #ifdef STRUCT_VALUE_REGNUM
381 call_fixed_regs
[STRUCT_VALUE_REGNUM
] = 1;
383 #ifdef STATIC_CHAIN_REGNUM
384 call_fixed_regs
[STATIC_CHAIN_REGNUM
] = 1;
387 n_non_fixed_regs
= 0;
389 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
391 if (FUNCTION_VALUE_REGNO_P (i
))
392 call_fixed_regs
[i
] = 1;
394 SET_HARD_REG_BIT (fixed_reg_set
, i
);
398 if (call_used_regs
[i
])
399 SET_HARD_REG_BIT (call_used_reg_set
, i
);
400 if (call_fixed_regs
[i
])
401 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
405 /* Specify the usage characteristics of the register named NAME.
406 It should be a fixed register if FIXED and a
407 call-used register if CALL_USED. */
410 fix_register (name
, fixed
, call_used
)
412 int fixed
, call_used
;
416 /* Decode the name and update the primary form of
417 the register info. */
419 if ((i
= decode_reg_name (name
)) >= 0)
421 fixed_regs
[i
] = fixed
;
422 call_used_regs
[i
] = call_used
;
426 warning ("unknown register name: %s", name
);
430 /* Now the data and code for the `regclass' pass, which happens
431 just before local-alloc. */
433 /* The `costs' struct records the cost of using a hard register of each class
434 and of using memory for each pseudo. We use this data to set up
435 register class preferences. */
439 int cost
[N_REG_CLASSES
];
443 /* Record the cost of each class for each pseudo. */
445 static struct costs
*costs
;
447 /* Record the same data by operand number, accumulated for each alternative
448 in an insn. The contribution to a pseudo is that of the minimum-cost
451 static struct costs op_costs
[MAX_RECOG_OPERANDS
];
453 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
454 This is available after `regclass' is run. */
456 static char *prefclass
;
458 /* altclass[R] is a register class that we should use for allocating
459 pseudo number R if no register in the preferred class is available.
460 If no register in this class is available, memory is preferred.
462 It might appear to be more general to have a bitmask of classes here,
463 but since it is recommended that there be a class corresponding to the
464 union of most major pair of classes, that generality is not required.
466 This is available after `regclass' is run. */
468 static char *altclass
;
470 /* Record the depth of loops that we are in. */
472 static int loop_depth
;
474 /* Account for the fact that insns within a loop are executed very commonly,
475 but don't keep doing this as loops go too deep. */
477 static int loop_cost
;
479 static int copy_cost ();
480 static void record_reg_classes ();
481 static void record_address_regs ();
484 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
485 This function is sometimes called before the info has been computed.
486 When that happens, just return GENERAL_REGS, which is innocuous. */
489 reg_preferred_class (regno
)
494 return (enum reg_class
) prefclass
[regno
];
498 reg_alternate_class (regno
)
503 return (enum reg_class
) altclass
[regno
];
506 /* This prevents dump_flow_info from losing if called
507 before regclass is run. */
515 /* This is a pass of the compiler that scans all instructions
516 and calculates the preferred class for each pseudo-register.
517 This information can be accessed later by calling `reg_preferred_class'.
518 This pass comes just before local register allocation. */
525 #ifdef REGISTER_CONSTRAINTS
528 struct costs init_cost
;
534 costs
= (struct costs
*) alloca (nregs
* sizeof (struct costs
));
536 #ifdef FORBIDDEN_INC_DEC_CLASSES
538 in_inc_dec
= (char *) alloca (nregs
);
540 /* Initialize information about which register classes can be used for
541 pseudos that are auto-incremented or auto-decremented. It would
542 seem better to put this in init_reg_sets, but we need to be able
543 to allocate rtx, which we can't do that early. */
545 for (i
= 0; i
< N_REG_CLASSES
; i
++)
547 rtx r
= gen_rtx (REG
, VOIDmode
, 0);
550 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
551 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
555 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
556 m
= (enum machine_mode
) ((int) m
+ 1))
557 if (HARD_REGNO_MODE_OK (j
, m
))
561 #ifdef SECONDARY_INPUT_RELOAD_CLASS
562 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
565 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
566 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
570 forbidden_inc_dec_class
[i
] = 1;
574 #endif /* FORBIDDEN_INC_DEC_CLASSES */
576 init_cost
.mem_cost
= 10000;
577 for (i
= 0; i
< N_REG_CLASSES
; i
++)
578 init_cost
.cost
[i
] = 10000;
580 /* Normally we scan the insns once and determine the best class to use for
581 each register. However, if -fexpensive_optimizations are on, we do so
582 twice, the second time using the tentative best classes to guide the
585 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
587 /* Zero out our accumulation of the cost of each class for each reg. */
589 bzero (costs
, nregs
* sizeof (struct costs
));
591 #ifdef FORBIDDEN_INC_DEC_CLASSES
592 bzero (in_inc_dec
, nregs
);
595 loop_depth
= 0, loop_cost
= 1;
597 /* Scan the instructions and record each time it would
598 save code to put a certain register in a certain class. */
600 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
602 char *constraints
[MAX_RECOG_OPERANDS
];
603 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
607 /* Show that an insn inside a loop is likely to be executed three
608 times more than insns outside a loop. This is much more aggressive
609 than the assumptions made elsewhere and is being tried as an
612 if (GET_CODE (insn
) == NOTE
613 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
614 loop_depth
++, loop_cost
= 1 << (2 * MIN (loop_depth
, 5));
615 else if (GET_CODE (insn
) == NOTE
616 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
617 loop_depth
--, loop_cost
= 1 << (2 * MIN (loop_depth
, 5));
619 else if ((GET_CODE (insn
) == INSN
620 && GET_CODE (PATTERN (insn
)) != USE
621 && GET_CODE (PATTERN (insn
)) != CLOBBER
622 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
623 || (GET_CODE (insn
) == JUMP_INSN
624 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
625 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
626 || GET_CODE (insn
) == CALL_INSN
)
628 if (GET_CODE (insn
) == INSN
629 && (noperands
= asm_noperands (PATTERN (insn
))) >= 0)
631 decode_asm_operands (PATTERN (insn
), recog_operand
, NULL_PTR
,
633 nalternatives
= (noperands
== 0 ? 0
634 : n_occurrences (',', constraints
[0]) + 1);
638 int insn_code_number
= recog_memoized (insn
);
641 set
= single_set (insn
);
644 nalternatives
= insn_n_alternatives
[insn_code_number
];
645 noperands
= insn_n_operands
[insn_code_number
];
647 /* If this insn loads a parameter from its stack slot, then
648 it represents a savings, rather than a cost, if the
649 parameter is stored in memory. Record this fact. */
651 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
652 && GET_CODE (SET_SRC (set
)) == MEM
653 && (note
= find_reg_note (insn
, REG_EQUIV
,
655 && GET_CODE (XEXP (note
, 0)) == MEM
)
657 costs
[REGNO (SET_DEST (set
))].mem_cost
658 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)))
660 record_address_regs (XEXP (SET_SRC (set
), 0),
661 BASE_REG_CLASS
, loop_cost
* 2);
665 /* Improve handling of two-address insns such as
666 (set X (ashift CONST Y)) where CONST must be made to
667 match X. Change it into two insns: (set X CONST)
668 (set X (ashift X Y)). If we left this for reloading, it
669 would probably get three insns because X and Y might go
670 in the same place. This prevents X and Y from receiving
673 We can only do this if the modes of operands 0 and 1
674 (which might not be the same) are tieable and we only need
675 do this during our first pass. */
677 if (pass
== 0 && optimize
679 && insn_operand_constraint
[insn_code_number
][1][0] == '0'
680 && insn_operand_constraint
[insn_code_number
][1][1] == 0
681 && CONSTANT_P (recog_operand
[1])
682 && ! rtx_equal_p (recog_operand
[0], recog_operand
[1])
683 && ! rtx_equal_p (recog_operand
[0], recog_operand
[2])
684 && GET_CODE (recog_operand
[0]) == REG
685 && MODES_TIEABLE_P (GET_MODE (recog_operand
[0]),
686 insn_operand_mode
[insn_code_number
][1]))
688 rtx previnsn
= prev_real_insn (insn
);
690 = gen_lowpart (insn_operand_mode
[insn_code_number
][1],
693 = emit_insn_before (gen_move_insn (dest
,
697 /* If this insn was the start of a basic block,
698 include the new insn in that block.
699 We need not check for code_label here;
700 while a basic block can start with a code_label,
701 INSN could not be at the beginning of that block. */
702 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
705 for (b
= 0; b
< n_basic_blocks
; b
++)
706 if (insn
== basic_block_head
[b
])
707 basic_block_head
[b
] = newinsn
;
710 /* This makes one more setting of new insns's dest. */
711 reg_n_sets
[REGNO (recog_operand
[0])]++;
713 *recog_operand_loc
[1] = recog_operand
[0];
714 for (i
= insn_n_dups
[insn_code_number
] - 1; i
>= 0; i
--)
715 if (recog_dup_num
[i
] == 1)
716 *recog_dup_loc
[i
] = recog_operand
[0];
718 insn
= PREV_INSN (newinsn
);
722 for (i
= 0; i
< noperands
; i
++)
725 = insn_operand_constraint
[insn_code_number
][i
];
726 modes
[i
] = insn_operand_mode
[insn_code_number
][i
];
730 /* If we get here, we are set up to record the costs of all the
731 operands for this insn. Start by initializing the costs.
732 Then handle any address registers. Finally record the desired
733 classes for any pseudos, doing it twice if some pair of
734 operands are commutative. */
736 for (i
= 0; i
< noperands
; i
++)
738 op_costs
[i
] = init_cost
;
740 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
741 recog_operand
[i
] = SUBREG_REG (recog_operand
[i
]);
743 if (GET_CODE (recog_operand
[i
]) == MEM
)
744 record_address_regs (XEXP (recog_operand
[i
], 0),
745 BASE_REG_CLASS
, loop_cost
* 2);
746 else if (constraints
[i
][0] == 'p')
747 record_address_regs (recog_operand
[i
],
748 BASE_REG_CLASS
, loop_cost
* 2);
751 /* Check for commutative in a separate loop so everything will
752 have been initialized. Don't bother doing anything if the
753 second operand is a constant since that is the case
754 for which the constraints should have been written. */
756 for (i
= 0; i
< noperands
- 1; i
++)
757 if (constraints
[i
][0] == '%'
758 && ! CONSTANT_P (recog_operand
[i
+1]))
760 char *xconstraints
[MAX_RECOG_OPERANDS
];
763 /* Handle commutative operands by swapping the constraints.
764 We assume the modes are the same. */
766 for (j
= 0; j
< noperands
; j
++)
767 xconstraints
[j
] = constraints
[j
];
769 xconstraints
[i
] = constraints
[i
+1];
770 xconstraints
[i
+1] = constraints
[i
];
771 record_reg_classes (nalternatives
, noperands
,
772 recog_operand
, modes
, xconstraints
,
776 record_reg_classes (nalternatives
, noperands
, recog_operand
,
777 modes
, constraints
, insn
);
779 /* Now add the cost for each operand to the total costs for
782 for (i
= 0; i
< noperands
; i
++)
783 if (GET_CODE (recog_operand
[i
]) == REG
784 && REGNO (recog_operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
786 int regno
= REGNO (recog_operand
[i
]);
787 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
789 p
->mem_cost
+= q
->mem_cost
* loop_cost
;
790 for (j
= 0; j
< N_REG_CLASSES
; j
++)
791 p
->cost
[j
] += q
->cost
[j
] * loop_cost
;
796 /* Now for each register look at how desirable each class is
797 and find which class is preferred. Store that in
798 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
799 class any of whose registers is better than memory. */
803 prefclass
= (char *) oballoc (nregs
);
804 altclass
= (char *) oballoc (nregs
);
807 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
809 register int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
810 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
811 /* This is an enum reg_class, but we call it an int
812 to save lots of casts. */
814 register struct costs
*p
= &costs
[i
];
816 for (class = (int) ALL_REGS
- 1; class > 0; class--)
818 /* Ignore classes that are too small for this operand or
819 invalid for a operand that was auto-incremented. */
820 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i
))
821 > reg_class_size
[class]
822 #ifdef FORBIDDEN_INC_DEC_CLASSES
823 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
827 else if (p
->cost
[class] < best_cost
)
829 best_cost
= p
->cost
[class];
830 best
= (enum reg_class
) class;
832 else if (p
->cost
[class] == best_cost
)
833 best
= reg_class_subunion
[(int)best
][class];
836 /* Record the alternate register class; i.e., a class for which
837 every register in it is better than using memory. If adding a
838 class would make a smaller class (i.e., no union of just those
839 classes exists), skip that class. The major unions of classes
840 should be provided as a register class. Don't do this if we
841 will be doing it again later. */
843 if (pass
== 1 || ! flag_expensive_optimizations
)
844 for (class = 0; class < N_REG_CLASSES
; class++)
845 if (p
->cost
[class] < p
->mem_cost
846 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
847 > reg_class_size
[(int) alt
])
848 #ifdef FORBIDDEN_INC_DEC_CLASSES
849 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
852 alt
= reg_class_subunion
[(int) alt
][class];
854 /* If we don't add any classes, nothing to try. */
858 /* We cast to (int) because (char) hits bugs in some compilers. */
859 prefclass
[i
] = (int) best
;
860 altclass
[i
] = (int) alt
;
863 #endif /* REGISTER_CONSTRAINTS */
866 #ifdef REGISTER_CONSTRAINTS
868 /* Record the cost of using memory or registers of various classes for
869 the operands in INSN.
871 N_ALTS is the number of alternatives.
873 N_OPS is the number of operands.
875 OPS is an array of the operands.
877 MODES are the modes of the operands, in case any are VOIDmode.
879 CONSTRAINTS are the constraints to use for the operands. This array
880 is modified by this procedure.
882 This procedure works alternative by alternative. For each alternative
883 we assume that we will be able to allocate all pseudos to their ideal
884 register class and calculate the cost of using that alternative. Then
885 we compute for each operand that is a pseudo-register, the cost of
886 having the pseudo allocated to each register class and using it in that
887 alternative. To this cost is added the cost of the alternative.
889 The cost of each class for this insn is its lowest cost among all the
893 record_reg_classes (n_alts
, n_ops
, ops
, modes
, constraints
, insn
)
897 enum machine_mode
*modes
;
902 enum op_type
{OP_READ
, OP_WRITE
, OP_READ_WRITE
} op_types
[MAX_RECOG_OPERANDS
];
905 /* By default, each operand is an input operand. */
907 for (i
= 0; i
< n_ops
; i
++)
908 op_types
[i
] = OP_READ
;
910 /* Process each alternative, each time minimizing an operand's cost with
911 the cost for each operand in that alternative. */
913 for (alt
= 0; alt
< n_alts
; alt
++)
915 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
918 enum reg_class classes
[MAX_RECOG_OPERANDS
];
921 for (i
= 0; i
< n_ops
; i
++)
923 char *p
= constraints
[i
];
925 enum machine_mode mode
= modes
[i
];
930 /* If this operand has no constraints at all, we can conclude
931 nothing about it since anything is valid. */
935 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
936 bzero ((char *) &this_op_costs
[i
], sizeof this_op_costs
[i
]);
944 /* If this alternative is only relevant when this operand
945 matches a previous operand, we do different things depending
946 on whether this operand is a pseudo-reg or not. */
948 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
951 classes
[i
] = classes
[j
];
953 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
955 /* If this matches the other operand, we have no added
957 if (rtx_equal_p (ops
[j
], op
))
960 /* If we can put the other operand into a register, add to
961 the cost of this alternative the cost to copy this
962 operand to the register used for the other operand. */
964 if (classes
[j
] != NO_REGS
)
965 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
967 else if (GET_CODE (ops
[j
]) != REG
968 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
970 /* This op is a pseudo but the one it matches is not. */
972 /* If we can't put the other operand into a register, this
973 alternative can't be used. */
975 if (classes
[j
] == NO_REGS
)
978 /* Otherwise, add to the cost of this alternative the cost
979 to copy the other operand to the register used for this
983 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
987 /* The costs of this operand are the same as that of the
988 other operand. However, if we cannot tie them, this
989 alternative needs to do a copy, which is one
992 this_op_costs
[i
] = this_op_costs
[j
];
993 if (! find_reg_note (insn
, REG_DEAD
, op
))
996 /* This is in place of ordinary cost computation
1002 /* Scan all the constraint letters. See if the operand matches
1003 any of the constraints. Collect the valid register classes
1004 and see if this operand accepts memory. */
1006 classes
[i
] = NO_REGS
;
1007 while (*p
&& (c
= *p
++) != ',')
1011 op_types
[i
] = OP_WRITE
;
1015 op_types
[i
] = OP_READ_WRITE
;
1019 /* Ignore the next letter for this pass. */
1024 case '?': case '!': case '#':
1026 case '0': case '1': case '2': case '3': case '4':
1030 case 'm': case 'o': case 'V':
1031 /* It doesn't seem worth distinguishing between offsettable
1032 and non-offsettable addresses here. */
1034 if (GET_CODE (op
) == MEM
)
1039 if (GET_CODE (op
) == MEM
1040 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1041 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1046 if (GET_CODE (op
) == MEM
1047 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1048 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1053 /* Match any floating double constant, but only if
1054 we can examine the bits of it reliably. */
1055 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1056 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1057 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1059 if (GET_CODE (op
) == CONST_DOUBLE
)
1064 if (GET_CODE (op
) == CONST_DOUBLE
)
1070 if (GET_CODE (op
) == CONST_DOUBLE
1071 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1076 if (GET_CODE (op
) == CONST_INT
1077 || (GET_CODE (op
) == CONST_DOUBLE
1078 && GET_MODE (op
) == VOIDmode
))
1082 #ifdef LEGITIMATE_PIC_OPERAND_P
1083 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1090 if (GET_CODE (op
) == CONST_INT
1091 || (GET_CODE (op
) == CONST_DOUBLE
1092 && GET_MODE (op
) == VOIDmode
))
1104 if (GET_CODE (op
) == CONST_INT
1105 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1113 #ifdef EXTRA_CONSTRAINT
1119 if (EXTRA_CONSTRAINT (op
, c
))
1125 if (GET_CODE (op
) == MEM
1127 #ifdef LEGITIMATE_PIC_OPERAND_P
1128 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1135 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1140 = reg_class_subunion
[(int) classes
[i
]]
1141 [(int) REG_CLASS_FROM_LETTER (c
)];
1146 /* How we account for this operand now depends on whether it is a
1147 pseudo register or not. If it is, we first check if any
1148 register classes are valid. If not, we ignore this alternative,
1149 since we want to assume that all pseudos get allocated for
1150 register preferencing. If some register class is valid, compute
1151 the costs of moving the pseudo into that class. */
1153 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1155 if (classes
[i
] == NO_REGS
)
1159 struct costs
*pp
= &this_op_costs
[i
];
1161 for (class = 0; class < N_REG_CLASSES
; class++)
1162 pp
->cost
[class] = may_move_cost
[class][(int) classes
[i
]];
1164 /* If the alternative actually allows memory, make things
1165 a bit cheaper since we won't need an extra insn to
1168 pp
->mem_cost
= MEMORY_MOVE_COST (mode
) - allows_mem
;
1170 /* If we have assigned a class to this register in our
1171 first pass, add a cost to this alternative corresponding
1172 to what we would add if this register were not in the
1173 appropriate class. */
1177 += may_move_cost
[prefclass
[REGNO (op
)]][(int) classes
[i
]];
1181 /* Otherwise, if this alternative wins, either because we
1182 have already determined that or if we have a hard register of
1183 the proper class, there is no cost for this alternative. */
1186 || (GET_CODE (op
) == REG
1187 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1190 /* If registers are valid, the cost of this alternative includes
1191 copying the object to and/or from a register. */
1193 else if (classes
[i
] != NO_REGS
)
1195 if (op_types
[i
] != OP_WRITE
)
1196 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1198 if (op_types
[i
] != OP_READ
)
1199 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1202 /* The only other way this alternative can be used is if this is a
1203 constant that could be placed into memory. */
1205 else if (CONSTANT_P (op
) && allows_mem
)
1206 alt_cost
+= MEMORY_MOVE_COST (mode
);
1214 /* Finally, update the costs with the information we've calculated
1215 about this alternative. */
1217 for (i
= 0; i
< n_ops
; i
++)
1218 if (GET_CODE (ops
[i
]) == REG
1219 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1221 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1222 int scale
= 1 + (op_types
[i
] == OP_READ_WRITE
);
1224 pp
->mem_cost
= MIN (pp
->mem_cost
,
1225 (qq
->mem_cost
+ alt_cost
) * scale
);
1227 for (class = 0; class < N_REG_CLASSES
; class++)
1228 pp
->cost
[class] = MIN (pp
->cost
[class],
1229 (qq
->cost
[class] + alt_cost
) * scale
);
1234 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1235 TO_P is zero) a register of class CLASS in mode MODE.
1237 X must not be a pseudo. */
1240 copy_cost (x
, mode
, class, to_p
)
1242 enum machine_mode mode
;
1243 enum reg_class
class;
1246 enum reg_class secondary_class
= NO_REGS
;
1248 /* If X is a SCRATCH, there is actually nothing to move since we are
1249 assuming optimal allocation. */
1251 if (GET_CODE (x
) == SCRATCH
)
1254 /* Get the class we will actually use for a reload. */
1255 class = PREFERRED_RELOAD_CLASS (x
, class);
1257 #ifdef HAVE_SECONDARY_RELOADS
1258 /* If we need a secondary reload (we assume here that we are using
1259 the secondary reload as an intermediate, not a scratch register), the
1260 cost is that to load the input into the intermediate register, then
1261 to copy them. We use a special value of TO_P to avoid recursion. */
1263 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1265 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1268 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1270 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1273 if (secondary_class
!= NO_REGS
)
1274 return (move_cost
[(int) secondary_class
][(int) class]
1275 + copy_cost (x
, mode
, secondary_class
, 2));
1276 #endif /* HAVE_SECONDARY_RELOADS */
1278 /* For memory, use the memory move cost, for (hard) registers, use the
1279 cost to move between the register classes, and use 2 for everything
1280 else (constants). */
1282 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1283 return MEMORY_MOVE_COST (mode
);
1285 else if (GET_CODE (x
) == REG
)
1286 return move_cost
[(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1289 /* If this is a constant, we may eventually want to call rtx_cost here. */
1293 /* Record the pseudo registers we must reload into hard registers
1294 in a subexpression of a memory address, X.
1296 CLASS is the class that the register needs to be in and is either
1297 BASE_REG_CLASS or INDEX_REG_CLASS.
1299 SCALE is twice the amount to multiply the cost by (it is twice so we
1300 can represent half-cost adjustments). */
1303 record_address_regs (x
, class, scale
)
1305 enum reg_class
class;
1308 register enum rtx_code code
= GET_CODE (x
);
1321 /* When we have an address that is a sum,
1322 we must determine whether registers are "base" or "index" regs.
1323 If there is a sum of two registers, we must choose one to be
1324 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1325 to make a good choice most of the time. We only need to do this
1326 on machines that can have two registers in an address and where
1327 the base and index register classes are different.
1329 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1330 that seems bogus since it should only be set when we are sure
1331 the register is being used as a pointer. */
1334 rtx arg0
= XEXP (x
, 0);
1335 rtx arg1
= XEXP (x
, 1);
1336 register enum rtx_code code0
= GET_CODE (arg0
);
1337 register enum rtx_code code1
= GET_CODE (arg1
);
1339 /* Look inside subregs. */
1340 if (code0
== SUBREG
)
1341 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1342 if (code1
== SUBREG
)
1343 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1345 /* If this machine only allows one register per address, it must
1346 be in the first operand. */
1348 if (MAX_REGS_PER_ADDRESS
== 1)
1349 record_address_regs (arg0
, class, scale
);
1351 /* If index and base registers are the same on this machine, just
1352 record registers in any non-constant operands. We assume here,
1353 as well as in the tests below, that all addresses are in
1356 else if (INDEX_REG_CLASS
== BASE_REG_CLASS
)
1358 record_address_regs (arg0
, class, scale
);
1359 if (! CONSTANT_P (arg1
))
1360 record_address_regs (arg1
, class, scale
);
1363 /* If the second operand is a constant integer, it doesn't change
1364 what class the first operand must be. */
1366 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1367 record_address_regs (arg0
, class, scale
);
1369 /* If the second operand is a symbolic constant, the first operand
1370 must be an index register. */
1372 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1373 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1375 /* If this the sum of two registers where the first is known to be a
1376 pointer, it must be a base register with the second an index. */
1378 else if (code0
== REG
&& code1
== REG
1379 && REGNO_POINTER_FLAG (REGNO (arg0
)))
1381 record_address_regs (arg0
, BASE_REG_CLASS
, scale
);
1382 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
1385 /* If this is the sum of two registers and neither is known to
1386 be a pointer, count equal chances that each might be a base
1387 or index register. This case should be rare. */
1389 else if (code0
== REG
&& code1
== REG
1390 && ! REGNO_POINTER_FLAG (REGNO (arg0
))
1391 && ! REGNO_POINTER_FLAG (REGNO (arg1
)))
1393 record_address_regs (arg0
, BASE_REG_CLASS
, scale
/ 2);
1394 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
1395 record_address_regs (arg1
, BASE_REG_CLASS
, scale
/ 2);
1396 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
1399 /* In all other cases, the first operand is an index and the
1400 second is the base. */
1404 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1405 record_address_regs (arg1
, BASE_REG_CLASS
, scale
);
1414 /* Double the importance of a pseudo register that is incremented
1415 or decremented, since it would take two extra insns
1416 if it ends up in the wrong place. If the operand is a pseudo,
1417 show it is being used in an INC_DEC context. */
1419 #ifdef FORBIDDEN_INC_DEC_CLASSES
1420 if (GET_CODE (XEXP (x
, 0)) == REG
1421 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
1422 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
1425 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
1430 register struct costs
*pp
= &costs
[REGNO (x
)];
1433 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
) * scale
) / 2;
1435 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1436 pp
->cost
[i
] += (may_move_cost
[i
][(int) class] * scale
) / 2;
1442 register char *fmt
= GET_RTX_FORMAT (code
);
1444 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1446 record_address_regs (XEXP (x
, i
), class, scale
);
1450 #endif /* REGISTER_CONSTRAINTS */
1452 /* This is the `regscan' pass of the compiler, run just before cse
1453 and again just before loop.
1455 It finds the first and last use of each pseudo-register
1456 and records them in the vectors regno_first_uid, regno_last_uid
1457 and counts the number of sets in the vector reg_n_sets.
1459 REPEAT is nonzero the second time this is called. */
1461 /* Indexed by pseudo register number, gives uid of first insn using the reg
1462 (as of the time reg_scan is called). */
1464 int *regno_first_uid
;
1466 /* Indexed by pseudo register number, gives uid of last insn using the reg
1467 (as of the time reg_scan is called). */
1469 int *regno_last_uid
;
1471 /* Record the number of registers we used when we allocated the above two
1472 tables. If we are called again with more than this, we must re-allocate
1475 static int highest_regno_in_uid_map
;
1477 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1478 Always at least 3, since the combiner could put that many togetherm
1479 and we want this to remain correct for all the remaining passes. */
1483 void reg_scan_mark_refs ();
1486 reg_scan (f
, nregs
, repeat
)
1493 if (!repeat
|| nregs
> highest_regno_in_uid_map
)
1495 /* Leave some spare space in case more regs are allocated. */
1496 highest_regno_in_uid_map
= nregs
+ nregs
/ 20;
1498 = (int *) oballoc (highest_regno_in_uid_map
* sizeof (int));
1500 = (int *) oballoc (highest_regno_in_uid_map
* sizeof (int));
1502 = (short *) oballoc (highest_regno_in_uid_map
* sizeof (short));
1505 bzero (regno_first_uid
, highest_regno_in_uid_map
* sizeof (int));
1506 bzero (regno_last_uid
, highest_regno_in_uid_map
* sizeof (int));
1507 bzero (reg_n_sets
, highest_regno_in_uid_map
* sizeof (short));
1511 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1512 if (GET_CODE (insn
) == INSN
1513 || GET_CODE (insn
) == CALL_INSN
1514 || GET_CODE (insn
) == JUMP_INSN
)
1516 if (GET_CODE (PATTERN (insn
)) == PARALLEL
1517 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
1518 max_parallel
= XVECLEN (PATTERN (insn
), 0);
1519 reg_scan_mark_refs (PATTERN (insn
), insn
);
1524 reg_scan_mark_refs (x
, insn
)
1528 register enum rtx_code code
= GET_CODE (x
);
1547 register int regno
= REGNO (x
);
1549 regno_last_uid
[regno
] = INSN_UID (insn
);
1550 if (regno_first_uid
[regno
] == 0)
1551 regno_first_uid
[regno
] = INSN_UID (insn
);
1556 /* Count a set of the destination if it is a register. */
1557 for (dest
= SET_DEST (x
);
1558 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
1559 || GET_CODE (dest
) == ZERO_EXTEND
;
1560 dest
= XEXP (dest
, 0))
1563 if (GET_CODE (dest
) == REG
)
1564 reg_n_sets
[REGNO (dest
)]++;
1566 /* If this is setting a pseudo from another pseudo or the sum of a
1567 pseudo and a constant integer and the other pseudo is known to be
1568 a pointer, set the destination to be a pointer as well.
1570 Likewise if it is setting the destination from an address or from a
1571 value equivalent to an address or to the sum of an address and
1574 But don't do any of this if the pseudo corresponds to a user
1575 variable since it should have already been set as a pointer based
1578 if (GET_CODE (SET_DEST (x
)) == REG
1579 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
1580 && ! REG_USERVAR_P (SET_DEST (x
))
1581 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x
)))
1582 && ((GET_CODE (SET_SRC (x
)) == REG
1583 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x
))))
1584 || ((GET_CODE (SET_SRC (x
)) == PLUS
1585 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
1586 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
1587 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
1588 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x
), 0))))
1589 || GET_CODE (SET_SRC (x
)) == CONST
1590 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
1591 || GET_CODE (SET_SRC (x
)) == LABEL_REF
1592 || (GET_CODE (SET_SRC (x
)) == HIGH
1593 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
1594 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
1595 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
1596 || ((GET_CODE (SET_SRC (x
)) == PLUS
1597 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
1598 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
1599 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
1600 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
1601 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
1602 && (GET_CODE (XEXP (note
, 0)) == CONST
1603 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
1604 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
1605 REGNO_POINTER_FLAG (REGNO (SET_DEST (x
))) = 1;
1607 /* ... fall through ... */
1611 register char *fmt
= GET_RTX_FORMAT (code
);
1613 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1616 reg_scan_mark_refs (XEXP (x
, i
), insn
);
1617 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
1620 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1621 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
);
1628 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
1632 reg_class_subset_p (c1
, c2
)
1633 register enum reg_class c1
;
1634 register enum reg_class c2
;
1636 if (c1
== c2
) return 1;
1641 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int)c1
],
1642 reg_class_contents
[(int)c2
],
1647 /* Return nonzero if there is a register that is in both C1 and C2. */
1650 reg_classes_intersect_p (c1
, c2
)
1651 register enum reg_class c1
;
1652 register enum reg_class c2
;
1659 if (c1
== c2
) return 1;
1661 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
1664 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
1665 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
1667 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);