]>
gcc.gnu.org Git - gcc.git/blob - gcc/recog.c
1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 88, 91, 92, 93, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "insn-config.h"
26 #include "insn-attr.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
31 #include "hard-reg-set.h"
35 #ifndef STACK_PUSH_CODE
36 #ifdef STACK_GROWS_DOWNWARD
37 #define STACK_PUSH_CODE PRE_DEC
39 #define STACK_PUSH_CODE PRE_INC
43 /* Import from final.c: */
44 extern rtx
alter_subreg ();
46 int strict_memory_address_p ();
47 int memory_address_p ();
49 /* Nonzero means allow operands to be volatile.
50 This should be 0 if you are generating rtl, such as if you are calling
51 the functions in optabs.c and expmed.c (most of the time).
52 This should be 1 if all valid insns need to be recognized,
53 such as in regclass.c and final.c and reload.c.
55 init_recog and init_recog_no_volatile are responsible for setting this. */
59 /* On return from `constrain_operands', indicate which alternative
62 int which_alternative
;
64 /* Nonzero after end of reload pass.
65 Set to 1 or 0 by toplev.c.
66 Controls the significance of (SUBREG (MEM)). */
70 /* Initialize data used by the function `recog'.
71 This must be called once in the compilation of a function
72 before any insn recognition may be done in the function. */
75 init_recog_no_volatile ()
86 /* Try recognizing the instruction INSN,
87 and return the code number that results.
88 Remember the code so that repeated calls do not
89 need to spend the time for actual rerecognition.
91 This function is the normal interface to instruction recognition.
92 The automatically-generated function `recog' is normally called
93 through this one. (The only exception is in combine.c.) */
99 if (INSN_CODE (insn
) < 0)
100 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, NULL_PTR
);
101 return INSN_CODE (insn
);
104 /* Check that X is an insn-body for an `asm' with operands
105 and that the operands mentioned in it are legitimate. */
108 check_asm_operands (x
)
111 int noperands
= asm_noperands (x
);
120 operands
= (rtx
*) alloca (noperands
* sizeof (rtx
));
121 decode_asm_operands (x
, operands
, NULL_PTR
, NULL_PTR
, NULL_PTR
);
123 for (i
= 0; i
< noperands
; i
++)
124 if (!general_operand (operands
[i
], VOIDmode
))
130 /* Static data for the next two routines.
132 The maximum number of changes supported is defined as the maximum
133 number of operands times 5. This allows for repeated substitutions
134 inside complex indexed address, or, alternatively, changes in up
137 #define MAX_CHANGE_LOCS (MAX_RECOG_OPERANDS * 5)
139 static rtx change_objects
[MAX_CHANGE_LOCS
];
140 static int change_old_codes
[MAX_CHANGE_LOCS
];
141 static rtx
*change_locs
[MAX_CHANGE_LOCS
];
142 static rtx change_olds
[MAX_CHANGE_LOCS
];
144 static int num_changes
= 0;
146 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
147 at which NEW will be placed. If OBJECT is zero, no validation is done,
148 the change is simply made.
150 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
151 will be called with the address and mode as parameters. If OBJECT is
152 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
155 IN_GROUP is non-zero if this is part of a group of changes that must be
156 performed as a group. In that case, the changes will be stored. The
157 function `apply_change_group' will validate and apply the changes.
159 If IN_GROUP is zero, this is a single change. Try to recognize the insn
160 or validate the memory reference with the change applied. If the result
161 is not valid for the machine, suppress the change and return zero.
162 Otherwise, perform the change and return 1. */
165 validate_change (object
, loc
, new, in_group
)
173 if (old
== new || rtx_equal_p (old
, new))
176 if (num_changes
>= MAX_CHANGE_LOCS
177 || (in_group
== 0 && num_changes
!= 0))
182 /* Save the information describing this change. */
183 change_objects
[num_changes
] = object
;
184 change_locs
[num_changes
] = loc
;
185 change_olds
[num_changes
] = old
;
187 if (object
&& GET_CODE (object
) != MEM
)
189 /* Set INSN_CODE to force rerecognition of insn. Save old code in
191 change_old_codes
[num_changes
] = INSN_CODE (object
);
192 INSN_CODE (object
) = -1;
197 /* If we are making a group of changes, return 1. Otherwise, validate the
198 change group we made. */
203 return apply_change_group ();
206 /* Apply a group of changes previously issued with `validate_change'.
207 Return 1 if all changes are valid, zero otherwise. */
210 apply_change_group ()
214 /* The changes have been applied and all INSN_CODEs have been reset to force
217 The changes are valid if we aren't given an object, or if we are
218 given a MEM and it still is a valid address, or if this is in insn
219 and it is recognized. In the latter case, if reload has completed,
220 we also require that the operands meet the constraints for
221 the insn. We do not allow modifying an ASM_OPERANDS after reload
222 has completed because verifying the constraints is too difficult. */
224 for (i
= 0; i
< num_changes
; i
++)
226 rtx object
= change_objects
[i
];
231 if (GET_CODE (object
) == MEM
)
233 if (! memory_address_p (GET_MODE (object
), XEXP (object
, 0)))
236 else if ((recog_memoized (object
) < 0
237 && (asm_noperands (PATTERN (object
)) < 0
238 || ! check_asm_operands (PATTERN (object
))
239 || reload_completed
))
241 && (insn_extract (object
),
242 ! constrain_operands (INSN_CODE (object
), 1))))
244 rtx pat
= PATTERN (object
);
246 /* Perhaps we couldn't recognize the insn because there were
247 extra CLOBBERs at the end. If so, try to re-recognize
248 without the last CLOBBER (later iterations will cause each of
249 them to be eliminated, in turn). But don't do this if we
250 have an ASM_OPERAND. */
251 if (GET_CODE (pat
) == PARALLEL
252 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
253 && asm_noperands (PATTERN (object
)) < 0)
257 if (XVECLEN (pat
, 0) == 2)
258 newpat
= XVECEXP (pat
, 0, 0);
263 newpat
= gen_rtx (PARALLEL
, VOIDmode
,
264 gen_rtvec (XVECLEN (pat
, 0) - 1));
265 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
266 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
269 /* Add a new change to this group to replace the pattern
270 with this new pattern. Then consider this change
271 as having succeeded. The change we added will
272 cause the entire call to fail if things remain invalid.
274 Note that this can lose if a later change than the one
275 we are processing specified &XVECEXP (PATTERN (object), 0, X)
276 but this shouldn't occur. */
278 validate_change (object
, &PATTERN (object
), newpat
, 1);
280 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
281 /* If this insn is a CLOBBER or USE, it is always valid, but is
289 if (i
== num_changes
)
301 /* Return the number of changes so far in the current group. */
304 num_validated_changes ()
309 /* Retract the changes numbered NUM and up. */
317 /* Back out all the changes. Do this in the opposite order in which
319 for (i
= num_changes
- 1; i
>= num
; i
--)
321 *change_locs
[i
] = change_olds
[i
];
322 if (change_objects
[i
] && GET_CODE (change_objects
[i
]) != MEM
)
323 INSN_CODE (change_objects
[i
]) = change_old_codes
[i
];
328 /* Replace every occurrence of FROM in X with TO. Mark each change with
329 validate_change passing OBJECT. */
332 validate_replace_rtx_1 (loc
, from
, to
, object
)
334 rtx from
, to
, object
;
338 register rtx x
= *loc
;
339 enum rtx_code code
= GET_CODE (x
);
341 /* X matches FROM if it is the same rtx or they are both referring to the
342 same register in the same mode. Avoid calling rtx_equal_p unless the
343 operands look similar. */
346 || (GET_CODE (x
) == REG
&& GET_CODE (from
) == REG
347 && GET_MODE (x
) == GET_MODE (from
)
348 && REGNO (x
) == REGNO (from
))
349 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
350 && rtx_equal_p (x
, from
)))
352 validate_change (object
, loc
, to
, 1);
356 /* For commutative or comparison operations, try replacing each argument
357 separately and seeing if we made any changes. If so, put a constant
359 if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
361 int prev_changes
= num_changes
;
363 validate_replace_rtx_1 (&XEXP (x
, 0), from
, to
, object
);
364 validate_replace_rtx_1 (&XEXP (x
, 1), from
, to
, object
);
365 if (prev_changes
!= num_changes
&& CONSTANT_P (XEXP (x
, 0)))
367 validate_change (object
, loc
,
368 gen_rtx (GET_RTX_CLASS (code
) == 'c' ? code
369 : swap_condition (code
),
370 GET_MODE (x
), XEXP (x
, 1), XEXP (x
, 0)),
380 /* If we have have a PLUS whose second operand is now a CONST_INT, use
381 plus_constant to try to simplify it. */
382 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& XEXP (x
, 1) == to
)
383 validate_change (object
, loc
,
384 plus_constant (XEXP (x
, 0), INTVAL (XEXP (x
, 1))), 1);
389 /* In these cases, the operation to be performed depends on the mode
390 of the operand. If we are replacing the operand with a VOIDmode
391 constant, we lose the information. So try to simplify the operation
392 in that case. If it fails, substitute in something that we know
393 won't be recognized. */
394 if (GET_MODE (to
) == VOIDmode
395 && (XEXP (x
, 0) == from
396 || (GET_CODE (XEXP (x
, 0)) == REG
&& GET_CODE (from
) == REG
397 && GET_MODE (XEXP (x
, 0)) == GET_MODE (from
)
398 && REGNO (XEXP (x
, 0)) == REGNO (from
))))
400 rtx
new = simplify_unary_operation (code
, GET_MODE (x
), to
,
403 new = gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
405 validate_change (object
, loc
, new, 1);
411 /* If we have a SUBREG of a register that we are replacing and we are
412 replacing it with a MEM, make a new MEM and try replacing the
413 SUBREG with it. Don't do this if the MEM has a mode-dependent address
414 or if we would be widening it. */
416 if (SUBREG_REG (x
) == from
417 && GET_CODE (from
) == REG
418 && GET_CODE (to
) == MEM
419 && ! mode_dependent_address_p (XEXP (to
, 0))
420 && ! MEM_VOLATILE_P (to
)
421 && GET_MODE_SIZE (GET_MODE (x
)) <= GET_MODE_SIZE (GET_MODE (to
)))
423 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
424 enum machine_mode mode
= GET_MODE (x
);
427 if (BYTES_BIG_ENDIAN
)
428 offset
+= (MIN (UNITS_PER_WORD
,
429 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
430 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
432 new = gen_rtx (MEM
, mode
, plus_constant (XEXP (to
, 0), offset
));
433 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (to
);
434 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to
);
435 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (to
);
436 validate_change (object
, loc
, new, 1);
443 /* If we are replacing a register with memory, try to change the memory
444 to be the mode required for memory in extract operations (this isn't
445 likely to be an insertion operation; if it was, nothing bad will
446 happen, we might just fail in some cases). */
448 if (XEXP (x
, 0) == from
&& GET_CODE (from
) == REG
&& GET_CODE (to
) == MEM
449 && GET_CODE (XEXP (x
, 1)) == CONST_INT
450 && GET_CODE (XEXP (x
, 2)) == CONST_INT
451 && ! mode_dependent_address_p (XEXP (to
, 0))
452 && ! MEM_VOLATILE_P (to
))
454 enum machine_mode wanted_mode
= VOIDmode
;
455 enum machine_mode is_mode
= GET_MODE (to
);
456 int width
= INTVAL (XEXP (x
, 1));
457 int pos
= INTVAL (XEXP (x
, 2));
460 if (code
== ZERO_EXTRACT
)
461 wanted_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][1];
464 if (code
== SIGN_EXTRACT
)
465 wanted_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][1];
468 /* If we have a narrower mode, we can do something. */
469 if (wanted_mode
!= VOIDmode
470 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
472 int offset
= pos
/ BITS_PER_UNIT
;
475 /* If the bytes and bits are counted differently, we
476 must adjust the offset. */
477 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
478 offset
= (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
)
481 pos
%= GET_MODE_BITSIZE (wanted_mode
);
483 newmem
= gen_rtx (MEM
, wanted_mode
,
484 plus_constant (XEXP (to
, 0), offset
));
485 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (to
);
486 MEM_VOLATILE_P (newmem
) = MEM_VOLATILE_P (to
);
487 MEM_IN_STRUCT_P (newmem
) = MEM_IN_STRUCT_P (to
);
489 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
490 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
497 fmt
= GET_RTX_FORMAT (code
);
498 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
501 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
);
502 else if (fmt
[i
] == 'E')
503 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
504 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
);
508 /* Try replacing every occurrence of FROM in INSN with TO. After all
509 changes have been made, validate by seeing if INSN is still valid. */
512 validate_replace_rtx (from
, to
, insn
)
515 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
516 return apply_change_group ();
520 /* Return 1 if the insn using CC0 set by INSN does not contain
521 any ordered tests applied to the condition codes.
522 EQ and NE tests do not count. */
525 next_insn_tests_no_inequality (insn
)
528 register rtx next
= next_cc0_user (insn
);
530 /* If there is no next insn, we have to take the conservative choice. */
534 return ((GET_CODE (next
) == JUMP_INSN
535 || GET_CODE (next
) == INSN
536 || GET_CODE (next
) == CALL_INSN
)
537 && ! inequality_comparisons_p (PATTERN (next
)));
540 #if 0 /* This is useless since the insn that sets the cc's
541 must be followed immediately by the use of them. */
542 /* Return 1 if the CC value set up by INSN is not used. */
545 next_insns_test_no_inequality (insn
)
548 register rtx next
= NEXT_INSN (insn
);
550 for (; next
!= 0; next
= NEXT_INSN (next
))
552 if (GET_CODE (next
) == CODE_LABEL
553 || GET_CODE (next
) == BARRIER
)
555 if (GET_CODE (next
) == NOTE
)
557 if (inequality_comparisons_p (PATTERN (next
)))
559 if (sets_cc0_p (PATTERN (next
)) == 1)
561 if (! reg_mentioned_p (cc0_rtx
, PATTERN (next
)))
569 /* This is used by find_single_use to locate an rtx that contains exactly one
570 use of DEST, which is typically either a REG or CC0. It returns a
571 pointer to the innermost rtx expression containing DEST. Appearances of
572 DEST that are being used to totally replace it are not counted. */
575 find_single_use_1 (dest
, loc
)
580 enum rtx_code code
= GET_CODE (x
);
597 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
598 of a REG that occupies all of the REG, the insn uses DEST if
599 it is mentioned in the destination or the source. Otherwise, we
600 need just check the source. */
601 if (GET_CODE (SET_DEST (x
)) != CC0
602 && GET_CODE (SET_DEST (x
)) != PC
603 && GET_CODE (SET_DEST (x
)) != REG
604 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
605 && GET_CODE (SUBREG_REG (SET_DEST (x
))) == REG
606 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
607 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
608 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
609 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
612 return find_single_use_1 (dest
, &SET_SRC (x
));
616 return find_single_use_1 (dest
, &XEXP (x
, 0));
619 /* If it wasn't one of the common cases above, check each expression and
620 vector of this code. Look for a unique usage of DEST. */
622 fmt
= GET_RTX_FORMAT (code
);
623 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
627 if (dest
== XEXP (x
, i
)
628 || (GET_CODE (dest
) == REG
&& GET_CODE (XEXP (x
, i
)) == REG
629 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
632 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
635 result
= this_result
;
636 else if (this_result
)
637 /* Duplicate usage. */
640 else if (fmt
[i
] == 'E')
644 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
646 if (XVECEXP (x
, i
, j
) == dest
647 || (GET_CODE (dest
) == REG
648 && GET_CODE (XVECEXP (x
, i
, j
)) == REG
649 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
652 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
655 result
= this_result
;
656 else if (this_result
)
665 /* See if DEST, produced in INSN, is used only a single time in the
666 sequel. If so, return a pointer to the innermost rtx expression in which
669 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
671 This routine will return usually zero either before flow is called (because
672 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
673 note can't be trusted).
675 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
676 care about REG_DEAD notes or LOG_LINKS.
678 Otherwise, we find the single use by finding an insn that has a
679 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
680 only referenced once in that insn, we know that it must be the first
681 and last insn referencing DEST. */
684 find_single_use (dest
, insn
, ploc
)
696 next
= NEXT_INSN (insn
);
698 || (GET_CODE (next
) != INSN
&& GET_CODE (next
) != JUMP_INSN
))
701 result
= find_single_use_1 (dest
, &PATTERN (next
));
708 if (reload_completed
|| reload_in_progress
|| GET_CODE (dest
) != REG
)
711 for (next
= next_nonnote_insn (insn
);
712 next
!= 0 && GET_CODE (next
) != CODE_LABEL
;
713 next
= next_nonnote_insn (next
))
714 if (GET_RTX_CLASS (GET_CODE (next
)) == 'i' && dead_or_set_p (next
, dest
))
716 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
717 if (XEXP (link
, 0) == insn
)
722 result
= find_single_use_1 (dest
, &PATTERN (next
));
732 /* Return 1 if OP is a valid general operand for machine mode MODE.
733 This is either a register reference, a memory reference,
734 or a constant. In the case of a memory reference, the address
735 is checked for general validity for the target machine.
737 Register and memory references must have mode MODE in order to be valid,
738 but some constants have no machine mode and are valid for any mode.
740 If MODE is VOIDmode, OP is checked for validity for whatever mode
743 The main use of this function is as a predicate in match_operand
744 expressions in the machine description.
746 For an explanation of this function's behavior for registers of
747 class NO_REGS, see the comment for `register_operand'. */
750 general_operand (op
, mode
)
752 enum machine_mode mode
;
754 register enum rtx_code code
= GET_CODE (op
);
755 int mode_altering_drug
= 0;
757 if (mode
== VOIDmode
)
758 mode
= GET_MODE (op
);
760 /* Don't accept CONST_INT or anything similar
761 if the caller wants something floating. */
762 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
763 && GET_MODE_CLASS (mode
) != MODE_INT
764 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
768 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
)
769 #ifdef LEGITIMATE_PIC_OPERAND_P
770 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
772 && LEGITIMATE_CONSTANT_P (op
));
774 /* Except for certain constants with VOIDmode, already checked for,
775 OP's mode must match MODE if MODE specifies a mode. */
777 if (GET_MODE (op
) != mode
)
782 #ifdef INSN_SCHEDULING
783 /* On machines that have insn scheduling, we want all memory
784 reference to be explicit, so outlaw paradoxical SUBREGs. */
785 if (GET_CODE (SUBREG_REG (op
)) == MEM
786 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
790 op
= SUBREG_REG (op
);
791 code
= GET_CODE (op
);
793 /* No longer needed, since (SUBREG (MEM...))
794 will load the MEM into a reload reg in the MEM's own mode. */
795 mode_altering_drug
= 1;
800 /* A register whose class is NO_REGS is not a general operand. */
801 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
802 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
806 register rtx y
= XEXP (op
, 0);
807 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
809 /* Use the mem's mode, since it will be reloaded thus. */
810 mode
= GET_MODE (op
);
811 GO_IF_LEGITIMATE_ADDRESS (mode
, y
, win
);
816 if (mode_altering_drug
)
817 return ! mode_dependent_address_p (XEXP (op
, 0));
821 /* Return 1 if OP is a valid memory address for a memory reference
824 The main use of this function is as a predicate in match_operand
825 expressions in the machine description. */
828 address_operand (op
, mode
)
830 enum machine_mode mode
;
832 return memory_address_p (mode
, op
);
835 /* Return 1 if OP is a register reference of mode MODE.
836 If MODE is VOIDmode, accept a register in any mode.
838 The main use of this function is as a predicate in match_operand
839 expressions in the machine description.
841 As a special exception, registers whose class is NO_REGS are
842 not accepted by `register_operand'. The reason for this change
843 is to allow the representation of special architecture artifacts
844 (such as a condition code register) without extending the rtl
845 definitions. Since registers of class NO_REGS cannot be used
846 as registers in any case where register classes are examined,
847 it is most consistent to keep this function from accepting them. */
850 register_operand (op
, mode
)
852 enum machine_mode mode
;
854 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
857 if (GET_CODE (op
) == SUBREG
)
859 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
860 because it is guaranteed to be reloaded into one.
861 Just make sure the MEM is valid in itself.
862 (Ideally, (SUBREG (MEM)...) should not exist after reload,
863 but currently it does result from (SUBREG (REG)...) where the
864 reg went on the stack.) */
865 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
866 return general_operand (op
, mode
);
867 op
= SUBREG_REG (op
);
870 /* We don't consider registers whose class is NO_REGS
871 to be a register operand. */
872 return (GET_CODE (op
) == REG
873 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
874 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
877 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
878 or a hard register. */
881 scratch_operand (op
, mode
)
883 enum machine_mode mode
;
885 return (GET_MODE (op
) == mode
886 && (GET_CODE (op
) == SCRATCH
887 || (GET_CODE (op
) == REG
888 && REGNO (op
) < FIRST_PSEUDO_REGISTER
)));
891 /* Return 1 if OP is a valid immediate operand for mode MODE.
893 The main use of this function is as a predicate in match_operand
894 expressions in the machine description. */
897 immediate_operand (op
, mode
)
899 enum machine_mode mode
;
901 /* Don't accept CONST_INT or anything similar
902 if the caller wants something floating. */
903 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
904 && GET_MODE_CLASS (mode
) != MODE_INT
905 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
908 return (CONSTANT_P (op
)
909 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
910 || GET_MODE (op
) == VOIDmode
)
911 #ifdef LEGITIMATE_PIC_OPERAND_P
912 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
914 && LEGITIMATE_CONSTANT_P (op
));
917 /* Returns 1 if OP is an operand that is a CONST_INT. */
920 const_int_operand (op
, mode
)
922 enum machine_mode mode
;
924 return GET_CODE (op
) == CONST_INT
;
927 /* Returns 1 if OP is an operand that is a constant integer or constant
928 floating-point number. */
931 const_double_operand (op
, mode
)
933 enum machine_mode mode
;
935 /* Don't accept CONST_INT or anything similar
936 if the caller wants something floating. */
937 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
938 && GET_MODE_CLASS (mode
) != MODE_INT
939 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
942 return ((GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
)
943 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
944 || GET_MODE (op
) == VOIDmode
));
947 /* Return 1 if OP is a general operand that is not an immediate operand. */
950 nonimmediate_operand (op
, mode
)
952 enum machine_mode mode
;
954 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
957 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
960 nonmemory_operand (op
, mode
)
962 enum machine_mode mode
;
966 /* Don't accept CONST_INT or anything similar
967 if the caller wants something floating. */
968 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
969 && GET_MODE_CLASS (mode
) != MODE_INT
970 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
973 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
)
974 #ifdef LEGITIMATE_PIC_OPERAND_P
975 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
977 && LEGITIMATE_CONSTANT_P (op
));
980 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
983 if (GET_CODE (op
) == SUBREG
)
985 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
986 because it is guaranteed to be reloaded into one.
987 Just make sure the MEM is valid in itself.
988 (Ideally, (SUBREG (MEM)...) should not exist after reload,
989 but currently it does result from (SUBREG (REG)...) where the
990 reg went on the stack.) */
991 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
992 return general_operand (op
, mode
);
993 op
= SUBREG_REG (op
);
996 /* We don't consider registers whose class is NO_REGS
997 to be a register operand. */
998 return (GET_CODE (op
) == REG
999 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1000 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1003 /* Return 1 if OP is a valid operand that stands for pushing a
1004 value of mode MODE onto the stack.
1006 The main use of this function is as a predicate in match_operand
1007 expressions in the machine description. */
1010 push_operand (op
, mode
)
1012 enum machine_mode mode
;
1014 if (GET_CODE (op
) != MEM
)
1017 if (GET_MODE (op
) != mode
)
1022 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1025 return XEXP (op
, 0) == stack_pointer_rtx
;
1028 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1031 memory_address_p (mode
, addr
)
1032 enum machine_mode mode
;
1035 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1042 /* Return 1 if OP is a valid memory reference with mode MODE,
1043 including a valid address.
1045 The main use of this function is as a predicate in match_operand
1046 expressions in the machine description. */
1049 memory_operand (op
, mode
)
1051 enum machine_mode mode
;
1055 if (! reload_completed
)
1056 /* Note that no SUBREG is a memory operand before end of reload pass,
1057 because (SUBREG (MEM...)) forces reloading into a register. */
1058 return GET_CODE (op
) == MEM
&& general_operand (op
, mode
);
1060 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1064 if (GET_CODE (inner
) == SUBREG
)
1065 inner
= SUBREG_REG (inner
);
1067 return (GET_CODE (inner
) == MEM
&& general_operand (op
, mode
));
1070 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1071 that is, a memory reference whose address is a general_operand. */
1074 indirect_operand (op
, mode
)
1076 enum machine_mode mode
;
1078 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1079 if (! reload_completed
1080 && GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1082 register int offset
= SUBREG_WORD (op
) * UNITS_PER_WORD
;
1083 rtx inner
= SUBREG_REG (op
);
1085 if (BYTES_BIG_ENDIAN
)
1086 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (op
)))
1087 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (inner
))));
1089 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1092 /* The only way that we can have a general_operand as the resulting
1093 address is if OFFSET is zero and the address already is an operand
1094 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1097 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1098 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1099 && GET_CODE (XEXP (XEXP (inner
, 0), 1)) == CONST_INT
1100 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1101 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1104 return (GET_CODE (op
) == MEM
1105 && memory_operand (op
, mode
)
1106 && general_operand (XEXP (op
, 0), Pmode
));
1109 /* Return 1 if this is a comparison operator. This allows the use of
1110 MATCH_OPERATOR to recognize all the branch insns. */
1113 comparison_operator (op
, mode
)
1115 enum machine_mode mode
;
1117 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1118 && GET_RTX_CLASS (GET_CODE (op
)) == '<');
1121 /* If BODY is an insn body that uses ASM_OPERANDS,
1122 return the number of operands (both input and output) in the insn.
1123 Otherwise return -1. */
1126 asm_noperands (body
)
1129 if (GET_CODE (body
) == ASM_OPERANDS
)
1130 /* No output operands: return number of input operands. */
1131 return ASM_OPERANDS_INPUT_LENGTH (body
);
1132 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1133 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1134 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body
)) + 1;
1135 else if (GET_CODE (body
) == PARALLEL
1136 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
1137 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1139 /* Multiple output operands, or 1 output plus some clobbers:
1140 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1144 /* Count backwards through CLOBBERs to determine number of SETs. */
1145 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1147 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1149 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1153 /* N_SETS is now number of output operands. */
1156 /* Verify that all the SETs we have
1157 came from a single original asm_operands insn
1158 (so that invalid combinations are blocked). */
1159 for (i
= 0; i
< n_sets
; i
++)
1161 rtx elt
= XVECEXP (body
, 0, i
);
1162 if (GET_CODE (elt
) != SET
)
1164 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1166 /* If these ASM_OPERANDS rtx's came from different original insns
1167 then they aren't allowed together. */
1168 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1169 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body
, 0, 0))))
1172 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body
, 0, 0)))
1175 else if (GET_CODE (body
) == PARALLEL
1176 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1178 /* 0 outputs, but some clobbers:
1179 body is [(asm_operands ...) (clobber (reg ...))...]. */
1182 /* Make sure all the other parallel things really are clobbers. */
1183 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1184 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1187 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body
, 0, 0));
1193 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1194 copy its operands (both input and output) into the vector OPERANDS,
1195 the locations of the operands within the insn into the vector OPERAND_LOCS,
1196 and the constraints for the operands into CONSTRAINTS.
1197 Write the modes of the operands into MODES.
1198 Return the assembler-template.
1200 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1201 we don't store that info. */
1204 decode_asm_operands (body
, operands
, operand_locs
, constraints
, modes
)
1209 enum machine_mode
*modes
;
1215 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1217 rtx asmop
= SET_SRC (body
);
1218 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1220 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
) + 1;
1222 for (i
= 1; i
< noperands
; i
++)
1225 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
- 1);
1227 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
- 1);
1229 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
- 1);
1231 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
- 1);
1234 /* The output is in the SET.
1235 Its constraint is in the ASM_OPERANDS itself. */
1237 operands
[0] = SET_DEST (body
);
1239 operand_locs
[0] = &SET_DEST (body
);
1241 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1243 modes
[0] = GET_MODE (SET_DEST (body
));
1244 template = ASM_OPERANDS_TEMPLATE (asmop
);
1246 else if (GET_CODE (body
) == ASM_OPERANDS
)
1249 /* No output operands: BODY is (asm_operands ....). */
1251 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1253 /* The input operands are found in the 1st element vector. */
1254 /* Constraints for inputs are in the 2nd element vector. */
1255 for (i
= 0; i
< noperands
; i
++)
1258 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1260 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1262 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1264 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1266 template = ASM_OPERANDS_TEMPLATE (asmop
);
1268 else if (GET_CODE (body
) == PARALLEL
1269 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1271 rtx asmop
= SET_SRC (XVECEXP (body
, 0, 0));
1272 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1273 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1274 int nout
= 0; /* Does not include CLOBBERs. */
1276 /* At least one output, plus some CLOBBERs. */
1278 /* The outputs are in the SETs.
1279 Their constraints are in the ASM_OPERANDS itself. */
1280 for (i
= 0; i
< nparallel
; i
++)
1282 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1283 break; /* Past last SET */
1286 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1288 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1290 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1292 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1296 for (i
= 0; i
< nin
; i
++)
1299 operand_locs
[i
+ nout
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1301 operands
[i
+ nout
] = ASM_OPERANDS_INPUT (asmop
, i
);
1303 constraints
[i
+ nout
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1305 modes
[i
+ nout
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1308 template = ASM_OPERANDS_TEMPLATE (asmop
);
1310 else if (GET_CODE (body
) == PARALLEL
1311 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1313 /* No outputs, but some CLOBBERs. */
1315 rtx asmop
= XVECEXP (body
, 0, 0);
1316 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1318 for (i
= 0; i
< nin
; i
++)
1321 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1323 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1325 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1327 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1330 template = ASM_OPERANDS_TEMPLATE (asmop
);
1336 /* Given an rtx *P, if it is a sum containing an integer constant term,
1337 return the location (type rtx *) of the pointer to that constant term.
1338 Otherwise, return a null pointer. */
1341 find_constant_term_loc (p
)
1345 register enum rtx_code code
= GET_CODE (*p
);
1347 /* If *P IS such a constant term, P is its location. */
1349 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1353 /* Otherwise, if not a sum, it has no constant term. */
1355 if (GET_CODE (*p
) != PLUS
)
1358 /* If one of the summands is constant, return its location. */
1360 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1361 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1364 /* Otherwise, check each summand for containing a constant term. */
1366 if (XEXP (*p
, 0) != 0)
1368 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1373 if (XEXP (*p
, 1) != 0)
1375 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1383 /* Return 1 if OP is a memory reference
1384 whose address contains no side effects
1385 and remains valid after the addition
1386 of a positive integer less than the
1387 size of the object being referenced.
1389 We assume that the original address is valid and do not check it.
1391 This uses strict_memory_address_p as a subroutine, so
1392 don't use it before reload. */
1395 offsettable_memref_p (op
)
1398 return ((GET_CODE (op
) == MEM
)
1399 && offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)));
1402 /* Similar, but don't require a strictly valid mem ref:
1403 consider pseudo-regs valid as index or base regs. */
1406 offsettable_nonstrict_memref_p (op
)
1409 return ((GET_CODE (op
) == MEM
)
1410 && offsettable_address_p (0, GET_MODE (op
), XEXP (op
, 0)));
1413 /* Return 1 if Y is a memory address which contains no side effects
1414 and would remain valid after the addition of a positive integer
1415 less than the size of that mode.
1417 We assume that the original address is valid and do not check it.
1418 We do check that it is valid for narrower modes.
1420 If STRICTP is nonzero, we require a strictly valid address,
1421 for the sake of use in reload.c. */
1424 offsettable_address_p (strictp
, mode
, y
)
1426 enum machine_mode mode
;
1429 register enum rtx_code ycode
= GET_CODE (y
);
1433 int (*addressp
) () = (strictp
? strict_memory_address_p
: memory_address_p
);
1435 if (CONSTANT_ADDRESS_P (y
))
1438 /* Adjusting an offsettable address involves changing to a narrower mode.
1439 Make sure that's OK. */
1441 if (mode_dependent_address_p (y
))
1444 /* If the expression contains a constant term,
1445 see if it remains valid when max possible offset is added. */
1447 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1452 *y2
= plus_constant (*y2
, GET_MODE_SIZE (mode
) - 1);
1453 /* Use QImode because an odd displacement may be automatically invalid
1454 for any wider mode. But it should be valid for a single byte. */
1455 good
= (*addressp
) (QImode
, y
);
1457 /* In any case, restore old contents of memory. */
1462 if (ycode
== PRE_DEC
|| ycode
== PRE_INC
1463 || ycode
== POST_DEC
|| ycode
== POST_INC
)
1466 /* The offset added here is chosen as the maximum offset that
1467 any instruction could need to add when operating on something
1468 of the specified mode. We assume that if Y and Y+c are
1469 valid addresses then so is Y+d for all 0<d<c. */
1471 z
= plus_constant_for_output (y
, GET_MODE_SIZE (mode
) - 1);
1473 /* Use QImode because an odd displacement may be automatically invalid
1474 for any wider mode. But it should be valid for a single byte. */
1475 return (*addressp
) (QImode
, z
);
1478 /* Return 1 if ADDR is an address-expression whose effect depends
1479 on the mode of the memory reference it is used in.
1481 Autoincrement addressing is a typical example of mode-dependence
1482 because the amount of the increment depends on the mode. */
1485 mode_dependent_address_p (addr
)
1488 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, win
);
1494 /* Return 1 if OP is a general operand
1495 other than a memory ref with a mode dependent address. */
1498 mode_independent_operand (op
, mode
)
1499 enum machine_mode mode
;
1504 if (! general_operand (op
, mode
))
1507 if (GET_CODE (op
) != MEM
)
1510 addr
= XEXP (op
, 0);
1511 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, lose
);
1517 /* Given an operand OP that is a valid memory reference
1518 which satisfies offsettable_memref_p,
1519 return a new memory reference whose address has been adjusted by OFFSET.
1520 OFFSET should be positive and less than the size of the object referenced.
1524 adj_offsettable_operand (op
, offset
)
1528 register enum rtx_code code
= GET_CODE (op
);
1532 register rtx y
= XEXP (op
, 0);
1535 if (CONSTANT_ADDRESS_P (y
))
1537 new = gen_rtx (MEM
, GET_MODE (op
), plus_constant_for_output (y
, offset
));
1538 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op
);
1542 if (GET_CODE (y
) == PLUS
)
1545 register rtx
*const_loc
;
1549 const_loc
= find_constant_term_loc (&z
);
1552 *const_loc
= plus_constant_for_output (*const_loc
, offset
);
1557 new = gen_rtx (MEM
, GET_MODE (op
), plus_constant_for_output (y
, offset
));
1558 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op
);
1564 #ifdef REGISTER_CONSTRAINTS
1566 /* Check the operands of an insn (found in recog_operands)
1567 against the insn's operand constraints (found via INSN_CODE_NUM)
1568 and return 1 if they are valid.
1570 WHICH_ALTERNATIVE is set to a number which indicates which
1571 alternative of constraints was matched: 0 for the first alternative,
1572 1 for the next, etc.
1574 In addition, when two operands are match
1575 and it happens that the output operand is (reg) while the
1576 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
1577 make the output operand look like the input.
1578 This is because the output operand is the one the template will print.
1580 This is used in final, just before printing the assembler code and by
1581 the routines that determine an insn's attribute.
1583 If STRICT is a positive non-zero value, it means that we have been
1584 called after reload has been completed. In that case, we must
1585 do all checks strictly. If it is zero, it means that we have been called
1586 before reload has completed. In that case, we first try to see if we can
1587 find an alternative that matches strictly. If not, we try again, this
1588 time assuming that reload will fix up the insn. This provides a "best
1589 guess" for the alternative and is used to compute attributes of insns prior
1590 to reload. A negative value of STRICT is used for this internal call. */
1598 constrain_operands (insn_code_num
, strict
)
1602 char *constraints
[MAX_RECOG_OPERANDS
];
1603 int matching_operands
[MAX_RECOG_OPERANDS
];
1604 enum op_type
{OP_IN
, OP_OUT
, OP_INOUT
} op_types
[MAX_RECOG_OPERANDS
];
1605 int earlyclobber
[MAX_RECOG_OPERANDS
];
1607 int noperands
= insn_n_operands
[insn_code_num
];
1609 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
1610 int funny_match_index
;
1611 int nalternatives
= insn_n_alternatives
[insn_code_num
];
1613 if (noperands
== 0 || nalternatives
== 0)
1616 for (c
= 0; c
< noperands
; c
++)
1618 constraints
[c
] = insn_operand_constraint
[insn_code_num
][c
];
1619 matching_operands
[c
] = -1;
1620 op_types
[c
] = OP_IN
;
1623 which_alternative
= 0;
1625 while (which_alternative
< nalternatives
)
1629 funny_match_index
= 0;
1631 for (opno
= 0; opno
< noperands
; opno
++)
1633 register rtx op
= recog_operand
[opno
];
1634 enum machine_mode mode
= GET_MODE (op
);
1635 register char *p
= constraints
[opno
];
1640 earlyclobber
[opno
] = 0;
1642 if (GET_CODE (op
) == SUBREG
)
1644 if (GET_CODE (SUBREG_REG (op
)) == REG
1645 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
1646 offset
= SUBREG_WORD (op
);
1647 op
= SUBREG_REG (op
);
1650 /* An empty constraint or empty alternative
1651 allows anything which matched the pattern. */
1652 if (*p
== 0 || *p
== ',')
1655 while (*p
&& (c
= *p
++) != ',')
1665 /* Ignore rest of this alternative as far as
1666 constraint checking is concerned. */
1667 while (*p
&& *p
!= ',')
1672 op_types
[opno
] = OP_OUT
;
1676 op_types
[opno
] = OP_INOUT
;
1680 earlyclobber
[opno
] = 1;
1688 /* This operand must be the same as a previous one.
1689 This kind of constraint is used for instructions such
1690 as add when they take only two operands.
1692 Note that the lower-numbered operand is passed first.
1694 If we are not testing strictly, assume that this constraint
1695 will be satisfied. */
1699 val
= operands_match_p (recog_operand
[c
- '0'],
1700 recog_operand
[opno
]);
1702 matching_operands
[opno
] = c
- '0';
1703 matching_operands
[c
- '0'] = opno
;
1707 /* If output is *x and input is *--x,
1708 arrange later to change the output to *--x as well,
1709 since the output op is the one that will be printed. */
1710 if (val
== 2 && strict
> 0)
1712 funny_match
[funny_match_index
].this = opno
;
1713 funny_match
[funny_match_index
++].other
= c
- '0';
1718 /* p is used for address_operands. When we are called by
1719 gen_reload, no one will have checked that the address is
1720 strictly valid, i.e., that all pseudos requiring hard regs
1721 have gotten them. */
1723 || (strict_memory_address_p
1724 (insn_operand_mode
[insn_code_num
][opno
], op
)))
1728 /* No need to check general_operand again;
1729 it was done in insn-recog.c. */
1731 /* Anything goes unless it is a REG and really has a hard reg
1732 but the hard reg is not in the class GENERAL_REGS. */
1734 || GENERAL_REGS
== ALL_REGS
1735 || GET_CODE (op
) != REG
1736 || (reload_in_progress
1737 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1738 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
1745 && GET_CODE (op
) == REG
1746 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1747 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
1748 || (GET_CODE (op
) == REG
1749 && ((GENERAL_REGS
== ALL_REGS
1750 && REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1751 || reg_fits_class_p (op
, GENERAL_REGS
,
1757 /* This is used for a MATCH_SCRATCH in the cases when we
1758 don't actually need anything. So anything goes any time. */
1763 if (GET_CODE (op
) == MEM
1764 /* Before reload, accept what reload can turn into mem. */
1765 || (strict
< 0 && CONSTANT_P (op
))
1766 /* During reload, accept a pseudo */
1767 || (reload_in_progress
&& GET_CODE (op
) == REG
1768 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
1773 if (GET_CODE (op
) == MEM
1774 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1775 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1780 if (GET_CODE (op
) == MEM
1781 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1782 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1787 #ifndef REAL_ARITHMETIC
1788 /* Match any CONST_DOUBLE, but only if
1789 we can examine the bits of it reliably. */
1790 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1791 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1792 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1795 if (GET_CODE (op
) == CONST_DOUBLE
)
1800 if (GET_CODE (op
) == CONST_DOUBLE
)
1806 if (GET_CODE (op
) == CONST_DOUBLE
1807 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1812 if (GET_CODE (op
) == CONST_INT
1813 || (GET_CODE (op
) == CONST_DOUBLE
1814 && GET_MODE (op
) == VOIDmode
))
1817 if (CONSTANT_P (op
))
1822 if (GET_CODE (op
) == CONST_INT
1823 || (GET_CODE (op
) == CONST_DOUBLE
1824 && GET_MODE (op
) == VOIDmode
))
1836 if (GET_CODE (op
) == CONST_INT
1837 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1841 #ifdef EXTRA_CONSTRAINT
1847 if (EXTRA_CONSTRAINT (op
, c
))
1853 if (GET_CODE (op
) == MEM
1854 && ! offsettable_memref_p (op
))
1859 if ((strict
> 0 && offsettable_memref_p (op
))
1860 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
1861 /* Before reload, accept what reload can handle. */
1863 && (CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
1864 /* During reload, accept a pseudo */
1865 || (reload_in_progress
&& GET_CODE (op
) == REG
1866 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
1873 && GET_CODE (op
) == REG
1874 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1875 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
1876 || (GET_CODE (op
) == REG
1877 && reg_fits_class_p (op
, REG_CLASS_FROM_LETTER (c
),
1882 constraints
[opno
] = p
;
1883 /* If this operand did not win somehow,
1884 this alternative loses. */
1888 /* This alternative won; the operands are ok.
1889 Change whichever operands this alternative says to change. */
1894 /* See if any earlyclobber operand conflicts with some other
1898 for (eopno
= 0; eopno
< noperands
; eopno
++)
1899 /* Ignore earlyclobber operands now in memory,
1900 because we would often report failure when we have
1901 two memory operands, one of which was formerly a REG. */
1902 if (earlyclobber
[eopno
]
1903 && GET_CODE (recog_operand
[eopno
]) == REG
)
1904 for (opno
= 0; opno
< noperands
; opno
++)
1905 if ((GET_CODE (recog_operand
[opno
]) == MEM
1906 || op_types
[opno
] != OP_OUT
)
1908 /* Ignore things like match_operator operands. */
1909 && *constraints
[opno
] != 0
1910 && ! (matching_operands
[opno
] == eopno
1911 && rtx_equal_p (recog_operand
[opno
],
1912 recog_operand
[eopno
]))
1913 && ! safe_from_earlyclobber (recog_operand
[opno
],
1914 recog_operand
[eopno
]))
1919 while (--funny_match_index
>= 0)
1921 recog_operand
[funny_match
[funny_match_index
].other
]
1922 = recog_operand
[funny_match
[funny_match_index
].this];
1929 which_alternative
++;
1932 /* If we are about to reject this, but we are not to test strictly,
1933 try a very loose test. Only return failure if it fails also. */
1935 return constrain_operands (insn_code_num
, -1);
1940 /* Return 1 iff OPERAND (assumed to be a REG rtx)
1941 is a hard reg in class CLASS when its regno is offsetted by OFFSET
1942 and changed to mode MODE.
1943 If REG occupies multiple hard regs, all of them must be in CLASS. */
1946 reg_fits_class_p (operand
, class, offset
, mode
)
1948 register enum reg_class
class;
1950 enum machine_mode mode
;
1952 register int regno
= REGNO (operand
);
1953 if (regno
< FIRST_PSEUDO_REGISTER
1954 && TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
1959 for (sr
= HARD_REGNO_NREGS (regno
, mode
) - 1;
1961 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
1970 #endif /* REGISTER_CONSTRAINTS */
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