]>
gcc.gnu.org Git - gcc.git/blob - gcc/recog.c
1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 88, 91, 92, 93, 1994 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
25 #include "insn-config.h"
26 #include "insn-attr.h"
27 #include "insn-flags.h"
28 #include "insn-codes.h"
31 #include "hard-reg-set.h"
35 #ifndef STACK_PUSH_CODE
36 #ifdef STACK_GROWS_DOWNWARD
37 #define STACK_PUSH_CODE PRE_DEC
39 #define STACK_PUSH_CODE PRE_INC
43 /* Import from final.c: */
44 extern rtx
alter_subreg ();
46 int strict_memory_address_p ();
47 int memory_address_p ();
49 /* Nonzero means allow operands to be volatile.
50 This should be 0 if you are generating rtl, such as if you are calling
51 the functions in optabs.c and expmed.c (most of the time).
52 This should be 1 if all valid insns need to be recognized,
53 such as in regclass.c and final.c and reload.c.
55 init_recog and init_recog_no_volatile are responsible for setting this. */
59 /* On return from `constrain_operands', indicate which alternative
62 int which_alternative
;
64 /* Nonzero after end of reload pass.
65 Set to 1 or 0 by toplev.c.
66 Controls the significance of (SUBREG (MEM)). */
70 /* Initialize data used by the function `recog'.
71 This must be called once in the compilation of a function
72 before any insn recognition may be done in the function. */
75 init_recog_no_volatile ()
86 /* Try recognizing the instruction INSN,
87 and return the code number that results.
88 Remember the code so that repeated calls do not
89 need to spend the time for actual rerecognition.
91 This function is the normal interface to instruction recognition.
92 The automatically-generated function `recog' is normally called
93 through this one. (The only exception is in combine.c.) */
99 if (INSN_CODE (insn
) < 0)
100 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, NULL_PTR
);
101 return INSN_CODE (insn
);
104 /* Check that X is an insn-body for an `asm' with operands
105 and that the operands mentioned in it are legitimate. */
108 check_asm_operands (x
)
111 int noperands
= asm_noperands (x
);
120 operands
= (rtx
*) alloca (noperands
* sizeof (rtx
));
121 decode_asm_operands (x
, operands
, NULL_PTR
, NULL_PTR
, NULL_PTR
);
123 for (i
= 0; i
< noperands
; i
++)
124 if (!general_operand (operands
[i
], VOIDmode
))
130 /* Static data for the next two routines.
132 The maximum number of changes supported is defined as the maximum
133 number of operands times 5. This allows for repeated substitutions
134 inside complex indexed address, or, alternatively, changes in up
137 #define MAX_CHANGE_LOCS (MAX_RECOG_OPERANDS * 5)
139 static rtx change_objects
[MAX_CHANGE_LOCS
];
140 static int change_old_codes
[MAX_CHANGE_LOCS
];
141 static rtx
*change_locs
[MAX_CHANGE_LOCS
];
142 static rtx change_olds
[MAX_CHANGE_LOCS
];
144 static int num_changes
= 0;
146 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
147 at which NEW will be placed. If OBJECT is zero, no validation is done,
148 the change is simply made.
150 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
151 will be called with the address and mode as parameters. If OBJECT is
152 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
155 IN_GROUP is non-zero if this is part of a group of changes that must be
156 performed as a group. In that case, the changes will be stored. The
157 function `apply_change_group' will validate and apply the changes.
159 If IN_GROUP is zero, this is a single change. Try to recognize the insn
160 or validate the memory reference with the change applied. If the result
161 is not valid for the machine, suppress the change and return zero.
162 Otherwise, perform the change and return 1. */
165 validate_change (object
, loc
, new, in_group
)
173 if (old
== new || rtx_equal_p (old
, new))
176 if (num_changes
>= MAX_CHANGE_LOCS
177 || (in_group
== 0 && num_changes
!= 0))
182 /* Save the information describing this change. */
183 change_objects
[num_changes
] = object
;
184 change_locs
[num_changes
] = loc
;
185 change_olds
[num_changes
] = old
;
187 if (object
&& GET_CODE (object
) != MEM
)
189 /* Set INSN_CODE to force rerecognition of insn. Save old code in
191 change_old_codes
[num_changes
] = INSN_CODE (object
);
192 INSN_CODE (object
) = -1;
197 /* If we are making a group of changes, return 1. Otherwise, validate the
198 change group we made. */
203 return apply_change_group ();
206 /* Apply a group of changes previously issued with `validate_change'.
207 Return 1 if all changes are valid, zero otherwise. */
210 apply_change_group ()
214 /* The changes have been applied and all INSN_CODEs have been reset to force
217 The changes are valid if we aren't given an object, or if we are
218 given a MEM and it still is a valid address, or if this is in insn
219 and it is recognized. In the latter case, if reload has completed,
220 we also require that the operands meet the constraints for
221 the insn. We do not allow modifying an ASM_OPERANDS after reload
222 has completed because verifying the constraints is too difficult. */
224 for (i
= 0; i
< num_changes
; i
++)
226 rtx object
= change_objects
[i
];
231 if (GET_CODE (object
) == MEM
)
233 if (! memory_address_p (GET_MODE (object
), XEXP (object
, 0)))
236 else if ((recog_memoized (object
) < 0
237 && (asm_noperands (PATTERN (object
)) < 0
238 || ! check_asm_operands (PATTERN (object
))
239 || reload_completed
))
241 && (insn_extract (object
),
242 ! constrain_operands (INSN_CODE (object
), 1))))
244 rtx pat
= PATTERN (object
);
246 /* Perhaps we couldn't recognize the insn because there were
247 extra CLOBBERs at the end. If so, try to re-recognize
248 without the last CLOBBER (later iterations will cause each of
249 them to be eliminated, in turn). But don't do this if we
250 have an ASM_OPERAND. */
251 if (GET_CODE (pat
) == PARALLEL
252 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
253 && asm_noperands (PATTERN (object
)) < 0)
257 if (XVECLEN (pat
, 0) == 2)
258 newpat
= XVECEXP (pat
, 0, 0);
263 newpat
= gen_rtx (PARALLEL
, VOIDmode
,
264 gen_rtvec (XVECLEN (pat
, 0) - 1));
265 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
266 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
269 /* Add a new change to this group to replace the pattern
270 with this new pattern. Then consider this change
271 as having succeeded. The change we added will
272 cause the entire call to fail if things remain invalid.
274 Note that this can lose if a later change than the one
275 we are processing specified &XVECEXP (PATTERN (object), 0, X)
276 but this shouldn't occur. */
278 validate_change (object
, &PATTERN (object
), newpat
, 1);
280 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
281 /* If this insn is a CLOBBER or USE, it is always valid, but is
289 if (i
== num_changes
)
301 /* Return the number of changes so far in the current group. */
304 num_validated_changes ()
309 /* Retract the changes numbered NUM and up. */
317 /* Back out all the changes. Do this in the opposite order in which
319 for (i
= num_changes
- 1; i
>= num
; i
--)
321 *change_locs
[i
] = change_olds
[i
];
322 if (change_objects
[i
] && GET_CODE (change_objects
[i
]) != MEM
)
323 INSN_CODE (change_objects
[i
]) = change_old_codes
[i
];
328 /* Replace every occurrence of FROM in X with TO. Mark each change with
329 validate_change passing OBJECT. */
332 validate_replace_rtx_1 (loc
, from
, to
, object
)
334 rtx from
, to
, object
;
338 register rtx x
= *loc
;
339 enum rtx_code code
= GET_CODE (x
);
341 /* X matches FROM if it is the same rtx or they are both referring to the
342 same register in the same mode. Avoid calling rtx_equal_p unless the
343 operands look similar. */
346 || (GET_CODE (x
) == REG
&& GET_CODE (from
) == REG
347 && GET_MODE (x
) == GET_MODE (from
)
348 && REGNO (x
) == REGNO (from
))
349 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
350 && rtx_equal_p (x
, from
)))
352 validate_change (object
, loc
, to
, 1);
356 /* For commutative or comparison operations, try replacing each argument
357 separately and seeing if we made any changes. If so, put a constant
359 if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
361 int prev_changes
= num_changes
;
363 validate_replace_rtx_1 (&XEXP (x
, 0), from
, to
, object
);
364 validate_replace_rtx_1 (&XEXP (x
, 1), from
, to
, object
);
365 if (prev_changes
!= num_changes
&& CONSTANT_P (XEXP (x
, 0)))
367 validate_change (object
, loc
,
368 gen_rtx (GET_RTX_CLASS (code
) == 'c' ? code
369 : swap_condition (code
),
370 GET_MODE (x
), XEXP (x
, 1), XEXP (x
, 0)),
380 /* If we have have a PLUS whose second operand is now a CONST_INT, use
381 plus_constant to try to simplify it. */
382 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& XEXP (x
, 1) == to
)
383 validate_change (object
, loc
,
384 plus_constant (XEXP (x
, 0), INTVAL (XEXP (x
, 1))), 1);
389 /* In these cases, the operation to be performed depends on the mode
390 of the operand. If we are replacing the operand with a VOIDmode
391 constant, we lose the information. So try to simplify the operation
392 in that case. If it fails, substitute in something that we know
393 won't be recognized. */
394 if (GET_MODE (to
) == VOIDmode
395 && (XEXP (x
, 0) == from
396 || (GET_CODE (XEXP (x
, 0)) == REG
&& GET_CODE (from
) == REG
397 && GET_MODE (XEXP (x
, 0)) == GET_MODE (from
)
398 && REGNO (XEXP (x
, 0)) == REGNO (from
))))
400 rtx
new = simplify_unary_operation (code
, GET_MODE (x
), to
,
403 new = gen_rtx (CLOBBER
, GET_MODE (x
), const0_rtx
);
405 validate_change (object
, loc
, new, 1);
411 /* If we have a SUBREG of a register that we are replacing and we are
412 replacing it with a MEM, make a new MEM and try replacing the
413 SUBREG with it. Don't do this if the MEM has a mode-dependent address
414 or if we would be widening it. */
416 if (SUBREG_REG (x
) == from
417 && GET_CODE (from
) == REG
418 && GET_CODE (to
) == MEM
419 && ! mode_dependent_address_p (XEXP (to
, 0))
420 && ! MEM_VOLATILE_P (to
)
421 && GET_MODE_SIZE (GET_MODE (x
)) <= GET_MODE_SIZE (GET_MODE (to
)))
423 int offset
= SUBREG_WORD (x
) * UNITS_PER_WORD
;
424 enum machine_mode mode
= GET_MODE (x
);
427 if (BYTES_BIG_ENDIAN
)
428 offset
+= (MIN (UNITS_PER_WORD
,
429 GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
430 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
)));
432 new = gen_rtx (MEM
, mode
, plus_constant (XEXP (to
, 0), offset
));
433 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (to
);
434 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (to
);
435 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (to
);
436 validate_change (object
, loc
, new, 1);
443 /* If we are replacing a register with memory, try to change the memory
444 to be the mode required for memory in extract operations (this isn't
445 likely to be an insertion operation; if it was, nothing bad will
446 happen, we might just fail in some cases). */
448 if (XEXP (x
, 0) == from
&& GET_CODE (from
) == REG
&& GET_CODE (to
) == MEM
449 && GET_CODE (XEXP (x
, 1)) == CONST_INT
450 && GET_CODE (XEXP (x
, 2)) == CONST_INT
451 && ! mode_dependent_address_p (XEXP (to
, 0))
452 && ! MEM_VOLATILE_P (to
))
454 enum machine_mode wanted_mode
= VOIDmode
;
455 enum machine_mode is_mode
= GET_MODE (to
);
456 int width
= INTVAL (XEXP (x
, 1));
457 int pos
= INTVAL (XEXP (x
, 2));
460 if (code
== ZERO_EXTRACT
)
461 wanted_mode
= insn_operand_mode
[(int) CODE_FOR_extzv
][1];
464 if (code
== SIGN_EXTRACT
)
465 wanted_mode
= insn_operand_mode
[(int) CODE_FOR_extv
][1];
468 /* If we have a narrower mode, we can do something. */
469 if (wanted_mode
!= VOIDmode
470 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
472 int offset
= pos
/ BITS_PER_UNIT
;
475 /* If the bytes and bits are counted differently, we
476 must adjust the offset. */
477 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
478 offset
= (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
)
481 pos
%= GET_MODE_BITSIZE (wanted_mode
);
483 newmem
= gen_rtx (MEM
, wanted_mode
,
484 plus_constant (XEXP (to
, 0), offset
));
485 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (to
);
486 MEM_VOLATILE_P (newmem
) = MEM_VOLATILE_P (to
);
487 MEM_IN_STRUCT_P (newmem
) = MEM_IN_STRUCT_P (to
);
489 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
490 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
497 fmt
= GET_RTX_FORMAT (code
);
498 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
501 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
);
502 else if (fmt
[i
] == 'E')
503 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
504 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
);
508 /* Try replacing every occurrence of FROM in INSN with TO. After all
509 changes have been made, validate by seeing if INSN is still valid. */
512 validate_replace_rtx (from
, to
, insn
)
515 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
516 return apply_change_group ();
520 /* Return 1 if the insn using CC0 set by INSN does not contain
521 any ordered tests applied to the condition codes.
522 EQ and NE tests do not count. */
525 next_insn_tests_no_inequality (insn
)
528 register rtx next
= next_cc0_user (insn
);
530 /* If there is no next insn, we have to take the conservative choice. */
534 return ((GET_CODE (next
) == JUMP_INSN
535 || GET_CODE (next
) == INSN
536 || GET_CODE (next
) == CALL_INSN
)
537 && ! inequality_comparisons_p (PATTERN (next
)));
540 #if 0 /* This is useless since the insn that sets the cc's
541 must be followed immediately by the use of them. */
542 /* Return 1 if the CC value set up by INSN is not used. */
545 next_insns_test_no_inequality (insn
)
548 register rtx next
= NEXT_INSN (insn
);
550 for (; next
!= 0; next
= NEXT_INSN (next
))
552 if (GET_CODE (next
) == CODE_LABEL
553 || GET_CODE (next
) == BARRIER
)
555 if (GET_CODE (next
) == NOTE
)
557 if (inequality_comparisons_p (PATTERN (next
)))
559 if (sets_cc0_p (PATTERN (next
)) == 1)
561 if (! reg_mentioned_p (cc0_rtx
, PATTERN (next
)))
569 /* This is used by find_single_use to locate an rtx that contains exactly one
570 use of DEST, which is typically either a REG or CC0. It returns a
571 pointer to the innermost rtx expression containing DEST. Appearances of
572 DEST that are being used to totally replace it are not counted. */
575 find_single_use_1 (dest
, loc
)
580 enum rtx_code code
= GET_CODE (x
);
597 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
598 of a REG that occupies all of the REG, the insn uses DEST if
599 it is mentioned in the destination or the source. Otherwise, we
600 need just check the source. */
601 if (GET_CODE (SET_DEST (x
)) != CC0
602 && GET_CODE (SET_DEST (x
)) != PC
603 && GET_CODE (SET_DEST (x
)) != REG
604 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
605 && GET_CODE (SUBREG_REG (SET_DEST (x
))) == REG
606 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
607 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
608 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
609 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
612 return find_single_use_1 (dest
, &SET_SRC (x
));
616 return find_single_use_1 (dest
, &XEXP (x
, 0));
619 /* If it wasn't one of the common cases above, check each expression and
620 vector of this code. Look for a unique usage of DEST. */
622 fmt
= GET_RTX_FORMAT (code
);
623 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
627 if (dest
== XEXP (x
, i
)
628 || (GET_CODE (dest
) == REG
&& GET_CODE (XEXP (x
, i
)) == REG
629 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
632 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
635 result
= this_result
;
636 else if (this_result
)
637 /* Duplicate usage. */
640 else if (fmt
[i
] == 'E')
644 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
646 if (XVECEXP (x
, i
, j
) == dest
647 || (GET_CODE (dest
) == REG
648 && GET_CODE (XVECEXP (x
, i
, j
)) == REG
649 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
652 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
655 result
= this_result
;
656 else if (this_result
)
665 /* See if DEST, produced in INSN, is used only a single time in the
666 sequel. If so, return a pointer to the innermost rtx expression in which
669 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
671 This routine will return usually zero either before flow is called (because
672 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
673 note can't be trusted).
675 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
676 care about REG_DEAD notes or LOG_LINKS.
678 Otherwise, we find the single use by finding an insn that has a
679 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
680 only referenced once in that insn, we know that it must be the first
681 and last insn referencing DEST. */
684 find_single_use (dest
, insn
, ploc
)
696 next
= NEXT_INSN (insn
);
698 || (GET_CODE (next
) != INSN
&& GET_CODE (next
) != JUMP_INSN
))
701 result
= find_single_use_1 (dest
, &PATTERN (next
));
708 if (reload_completed
|| reload_in_progress
|| GET_CODE (dest
) != REG
)
711 for (next
= next_nonnote_insn (insn
);
712 next
!= 0 && GET_CODE (next
) != CODE_LABEL
;
713 next
= next_nonnote_insn (next
))
714 if (GET_RTX_CLASS (GET_CODE (next
)) == 'i' && dead_or_set_p (next
, dest
))
716 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
717 if (XEXP (link
, 0) == insn
)
722 result
= find_single_use_1 (dest
, &PATTERN (next
));
732 /* Return 1 if OP is a valid general operand for machine mode MODE.
733 This is either a register reference, a memory reference,
734 or a constant. In the case of a memory reference, the address
735 is checked for general validity for the target machine.
737 Register and memory references must have mode MODE in order to be valid,
738 but some constants have no machine mode and are valid for any mode.
740 If MODE is VOIDmode, OP is checked for validity for whatever mode
743 The main use of this function is as a predicate in match_operand
744 expressions in the machine description.
746 For an explanation of this function's behavior for registers of
747 class NO_REGS, see the comment for `register_operand'. */
750 general_operand (op
, mode
)
752 enum machine_mode mode
;
754 register enum rtx_code code
= GET_CODE (op
);
755 int mode_altering_drug
= 0;
757 if (mode
== VOIDmode
)
758 mode
= GET_MODE (op
);
760 /* Don't accept CONST_INT or anything similar
761 if the caller wants something floating. */
762 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
763 && GET_MODE_CLASS (mode
) != MODE_INT
764 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
768 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
)
769 #ifdef LEGITIMATE_PIC_OPERAND_P
770 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
772 && LEGITIMATE_CONSTANT_P (op
));
774 /* Except for certain constants with VOIDmode, already checked for,
775 OP's mode must match MODE if MODE specifies a mode. */
777 if (GET_MODE (op
) != mode
)
782 #ifdef INSN_SCHEDULING
783 /* On machines that have insn scheduling, we want all memory
784 reference to be explicit, so outlaw paradoxical SUBREGs. */
785 if (GET_CODE (SUBREG_REG (op
)) == MEM
786 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
790 op
= SUBREG_REG (op
);
791 code
= GET_CODE (op
);
793 /* No longer needed, since (SUBREG (MEM...))
794 will load the MEM into a reload reg in the MEM's own mode. */
795 mode_altering_drug
= 1;
800 /* A register whose class is NO_REGS is not a general operand. */
801 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
802 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
806 register rtx y
= XEXP (op
, 0);
807 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
809 /* Use the mem's mode, since it will be reloaded thus. */
810 mode
= GET_MODE (op
);
811 GO_IF_LEGITIMATE_ADDRESS (mode
, y
, win
);
816 if (mode_altering_drug
)
817 return ! mode_dependent_address_p (XEXP (op
, 0));
821 /* Return 1 if OP is a valid memory address for a memory reference
824 The main use of this function is as a predicate in match_operand
825 expressions in the machine description. */
828 address_operand (op
, mode
)
830 enum machine_mode mode
;
832 return memory_address_p (mode
, op
);
835 /* Return 1 if OP is a register reference of mode MODE.
836 If MODE is VOIDmode, accept a register in any mode.
838 The main use of this function is as a predicate in match_operand
839 expressions in the machine description.
841 As a special exception, registers whose class is NO_REGS are
842 not accepted by `register_operand'. The reason for this change
843 is to allow the representation of special architecture artifacts
844 (such as a condition code register) without extending the rtl
845 definitions. Since registers of class NO_REGS cannot be used
846 as registers in any case where register classes are examined,
847 it is most consistent to keep this function from accepting them. */
850 register_operand (op
, mode
)
852 enum machine_mode mode
;
854 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
857 if (GET_CODE (op
) == SUBREG
)
859 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
860 because it is guaranteed to be reloaded into one.
861 Just make sure the MEM is valid in itself.
862 (Ideally, (SUBREG (MEM)...) should not exist after reload,
863 but currently it does result from (SUBREG (REG)...) where the
864 reg went on the stack.) */
865 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
866 return general_operand (op
, mode
);
868 #ifdef CLASS_CANNOT_CHANGE_SIZE
869 if (GET_CODE (SUBREG_REG (op
)) == REG
870 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
871 && TEST_HARD_REG_BIT (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_SIZE
],
872 REGNO (SUBREG_REG (op
)))
873 && (GET_MODE_SIZE (mode
)
874 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
875 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_INT
876 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_FLOAT
)
880 op
= SUBREG_REG (op
);
883 /* We don't consider registers whose class is NO_REGS
884 to be a register operand. */
885 return (GET_CODE (op
) == REG
886 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
887 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
890 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
891 or a hard register. */
894 scratch_operand (op
, mode
)
896 enum machine_mode mode
;
898 return (GET_MODE (op
) == mode
899 && (GET_CODE (op
) == SCRATCH
900 || (GET_CODE (op
) == REG
901 && REGNO (op
) < FIRST_PSEUDO_REGISTER
)));
904 /* Return 1 if OP is a valid immediate operand for mode MODE.
906 The main use of this function is as a predicate in match_operand
907 expressions in the machine description. */
910 immediate_operand (op
, mode
)
912 enum machine_mode mode
;
914 /* Don't accept CONST_INT or anything similar
915 if the caller wants something floating. */
916 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
917 && GET_MODE_CLASS (mode
) != MODE_INT
918 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
921 return (CONSTANT_P (op
)
922 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
923 || GET_MODE (op
) == VOIDmode
)
924 #ifdef LEGITIMATE_PIC_OPERAND_P
925 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
927 && LEGITIMATE_CONSTANT_P (op
));
930 /* Returns 1 if OP is an operand that is a CONST_INT. */
933 const_int_operand (op
, mode
)
935 enum machine_mode mode
;
937 return GET_CODE (op
) == CONST_INT
;
940 /* Returns 1 if OP is an operand that is a constant integer or constant
941 floating-point number. */
944 const_double_operand (op
, mode
)
946 enum machine_mode mode
;
948 /* Don't accept CONST_INT or anything similar
949 if the caller wants something floating. */
950 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
951 && GET_MODE_CLASS (mode
) != MODE_INT
952 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
955 return ((GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
)
956 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
957 || GET_MODE (op
) == VOIDmode
));
960 /* Return 1 if OP is a general operand that is not an immediate operand. */
963 nonimmediate_operand (op
, mode
)
965 enum machine_mode mode
;
967 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
970 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
973 nonmemory_operand (op
, mode
)
975 enum machine_mode mode
;
979 /* Don't accept CONST_INT or anything similar
980 if the caller wants something floating. */
981 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
982 && GET_MODE_CLASS (mode
) != MODE_INT
983 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
986 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
)
987 #ifdef LEGITIMATE_PIC_OPERAND_P
988 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
990 && LEGITIMATE_CONSTANT_P (op
));
993 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
996 if (GET_CODE (op
) == SUBREG
)
998 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
999 because it is guaranteed to be reloaded into one.
1000 Just make sure the MEM is valid in itself.
1001 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1002 but currently it does result from (SUBREG (REG)...) where the
1003 reg went on the stack.) */
1004 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1005 return general_operand (op
, mode
);
1006 op
= SUBREG_REG (op
);
1009 /* We don't consider registers whose class is NO_REGS
1010 to be a register operand. */
1011 return (GET_CODE (op
) == REG
1012 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1013 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1016 /* Return 1 if OP is a valid operand that stands for pushing a
1017 value of mode MODE onto the stack.
1019 The main use of this function is as a predicate in match_operand
1020 expressions in the machine description. */
1023 push_operand (op
, mode
)
1025 enum machine_mode mode
;
1027 if (GET_CODE (op
) != MEM
)
1030 if (GET_MODE (op
) != mode
)
1035 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1038 return XEXP (op
, 0) == stack_pointer_rtx
;
1041 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1044 memory_address_p (mode
, addr
)
1045 enum machine_mode mode
;
1048 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1055 /* Return 1 if OP is a valid memory reference with mode MODE,
1056 including a valid address.
1058 The main use of this function is as a predicate in match_operand
1059 expressions in the machine description. */
1062 memory_operand (op
, mode
)
1064 enum machine_mode mode
;
1068 if (! reload_completed
)
1069 /* Note that no SUBREG is a memory operand before end of reload pass,
1070 because (SUBREG (MEM...)) forces reloading into a register. */
1071 return GET_CODE (op
) == MEM
&& general_operand (op
, mode
);
1073 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1077 if (GET_CODE (inner
) == SUBREG
)
1078 inner
= SUBREG_REG (inner
);
1080 return (GET_CODE (inner
) == MEM
&& general_operand (op
, mode
));
1083 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1084 that is, a memory reference whose address is a general_operand. */
1087 indirect_operand (op
, mode
)
1089 enum machine_mode mode
;
1091 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1092 if (! reload_completed
1093 && GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1095 register int offset
= SUBREG_WORD (op
) * UNITS_PER_WORD
;
1096 rtx inner
= SUBREG_REG (op
);
1098 if (BYTES_BIG_ENDIAN
)
1099 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (op
)))
1100 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (inner
))));
1102 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1105 /* The only way that we can have a general_operand as the resulting
1106 address is if OFFSET is zero and the address already is an operand
1107 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1110 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1111 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1112 && GET_CODE (XEXP (XEXP (inner
, 0), 1)) == CONST_INT
1113 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1114 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1117 return (GET_CODE (op
) == MEM
1118 && memory_operand (op
, mode
)
1119 && general_operand (XEXP (op
, 0), Pmode
));
1122 /* Return 1 if this is a comparison operator. This allows the use of
1123 MATCH_OPERATOR to recognize all the branch insns. */
1126 comparison_operator (op
, mode
)
1128 enum machine_mode mode
;
1130 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1131 && GET_RTX_CLASS (GET_CODE (op
)) == '<');
1134 /* If BODY is an insn body that uses ASM_OPERANDS,
1135 return the number of operands (both input and output) in the insn.
1136 Otherwise return -1. */
1139 asm_noperands (body
)
1142 if (GET_CODE (body
) == ASM_OPERANDS
)
1143 /* No output operands: return number of input operands. */
1144 return ASM_OPERANDS_INPUT_LENGTH (body
);
1145 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1146 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1147 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body
)) + 1;
1148 else if (GET_CODE (body
) == PARALLEL
1149 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
1150 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1152 /* Multiple output operands, or 1 output plus some clobbers:
1153 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1157 /* Count backwards through CLOBBERs to determine number of SETs. */
1158 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1160 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1162 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1166 /* N_SETS is now number of output operands. */
1169 /* Verify that all the SETs we have
1170 came from a single original asm_operands insn
1171 (so that invalid combinations are blocked). */
1172 for (i
= 0; i
< n_sets
; i
++)
1174 rtx elt
= XVECEXP (body
, 0, i
);
1175 if (GET_CODE (elt
) != SET
)
1177 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1179 /* If these ASM_OPERANDS rtx's came from different original insns
1180 then they aren't allowed together. */
1181 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1182 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body
, 0, 0))))
1185 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body
, 0, 0)))
1188 else if (GET_CODE (body
) == PARALLEL
1189 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1191 /* 0 outputs, but some clobbers:
1192 body is [(asm_operands ...) (clobber (reg ...))...]. */
1195 /* Make sure all the other parallel things really are clobbers. */
1196 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1197 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1200 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body
, 0, 0));
1206 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1207 copy its operands (both input and output) into the vector OPERANDS,
1208 the locations of the operands within the insn into the vector OPERAND_LOCS,
1209 and the constraints for the operands into CONSTRAINTS.
1210 Write the modes of the operands into MODES.
1211 Return the assembler-template.
1213 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1214 we don't store that info. */
1217 decode_asm_operands (body
, operands
, operand_locs
, constraints
, modes
)
1222 enum machine_mode
*modes
;
1228 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1230 rtx asmop
= SET_SRC (body
);
1231 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1233 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
) + 1;
1235 for (i
= 1; i
< noperands
; i
++)
1238 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
- 1);
1240 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
- 1);
1242 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
- 1);
1244 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
- 1);
1247 /* The output is in the SET.
1248 Its constraint is in the ASM_OPERANDS itself. */
1250 operands
[0] = SET_DEST (body
);
1252 operand_locs
[0] = &SET_DEST (body
);
1254 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1256 modes
[0] = GET_MODE (SET_DEST (body
));
1257 template = ASM_OPERANDS_TEMPLATE (asmop
);
1259 else if (GET_CODE (body
) == ASM_OPERANDS
)
1262 /* No output operands: BODY is (asm_operands ....). */
1264 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1266 /* The input operands are found in the 1st element vector. */
1267 /* Constraints for inputs are in the 2nd element vector. */
1268 for (i
= 0; i
< noperands
; i
++)
1271 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1273 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1275 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1277 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1279 template = ASM_OPERANDS_TEMPLATE (asmop
);
1281 else if (GET_CODE (body
) == PARALLEL
1282 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1284 rtx asmop
= SET_SRC (XVECEXP (body
, 0, 0));
1285 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1286 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1287 int nout
= 0; /* Does not include CLOBBERs. */
1289 /* At least one output, plus some CLOBBERs. */
1291 /* The outputs are in the SETs.
1292 Their constraints are in the ASM_OPERANDS itself. */
1293 for (i
= 0; i
< nparallel
; i
++)
1295 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1296 break; /* Past last SET */
1299 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1301 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1303 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1305 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1309 for (i
= 0; i
< nin
; i
++)
1312 operand_locs
[i
+ nout
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1314 operands
[i
+ nout
] = ASM_OPERANDS_INPUT (asmop
, i
);
1316 constraints
[i
+ nout
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1318 modes
[i
+ nout
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1321 template = ASM_OPERANDS_TEMPLATE (asmop
);
1323 else if (GET_CODE (body
) == PARALLEL
1324 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1326 /* No outputs, but some CLOBBERs. */
1328 rtx asmop
= XVECEXP (body
, 0, 0);
1329 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1331 for (i
= 0; i
< nin
; i
++)
1334 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1336 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1338 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1340 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1343 template = ASM_OPERANDS_TEMPLATE (asmop
);
1349 /* Given an rtx *P, if it is a sum containing an integer constant term,
1350 return the location (type rtx *) of the pointer to that constant term.
1351 Otherwise, return a null pointer. */
1354 find_constant_term_loc (p
)
1358 register enum rtx_code code
= GET_CODE (*p
);
1360 /* If *P IS such a constant term, P is its location. */
1362 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1366 /* Otherwise, if not a sum, it has no constant term. */
1368 if (GET_CODE (*p
) != PLUS
)
1371 /* If one of the summands is constant, return its location. */
1373 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1374 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1377 /* Otherwise, check each summand for containing a constant term. */
1379 if (XEXP (*p
, 0) != 0)
1381 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1386 if (XEXP (*p
, 1) != 0)
1388 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1396 /* Return 1 if OP is a memory reference
1397 whose address contains no side effects
1398 and remains valid after the addition
1399 of a positive integer less than the
1400 size of the object being referenced.
1402 We assume that the original address is valid and do not check it.
1404 This uses strict_memory_address_p as a subroutine, so
1405 don't use it before reload. */
1408 offsettable_memref_p (op
)
1411 return ((GET_CODE (op
) == MEM
)
1412 && offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)));
1415 /* Similar, but don't require a strictly valid mem ref:
1416 consider pseudo-regs valid as index or base regs. */
1419 offsettable_nonstrict_memref_p (op
)
1422 return ((GET_CODE (op
) == MEM
)
1423 && offsettable_address_p (0, GET_MODE (op
), XEXP (op
, 0)));
1426 /* Return 1 if Y is a memory address which contains no side effects
1427 and would remain valid after the addition of a positive integer
1428 less than the size of that mode.
1430 We assume that the original address is valid and do not check it.
1431 We do check that it is valid for narrower modes.
1433 If STRICTP is nonzero, we require a strictly valid address,
1434 for the sake of use in reload.c. */
1437 offsettable_address_p (strictp
, mode
, y
)
1439 enum machine_mode mode
;
1442 register enum rtx_code ycode
= GET_CODE (y
);
1446 int (*addressp
) () = (strictp
? strict_memory_address_p
: memory_address_p
);
1448 if (CONSTANT_ADDRESS_P (y
))
1451 /* Adjusting an offsettable address involves changing to a narrower mode.
1452 Make sure that's OK. */
1454 if (mode_dependent_address_p (y
))
1457 /* If the expression contains a constant term,
1458 see if it remains valid when max possible offset is added. */
1460 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1465 *y2
= plus_constant (*y2
, GET_MODE_SIZE (mode
) - 1);
1466 /* Use QImode because an odd displacement may be automatically invalid
1467 for any wider mode. But it should be valid for a single byte. */
1468 good
= (*addressp
) (QImode
, y
);
1470 /* In any case, restore old contents of memory. */
1475 if (ycode
== PRE_DEC
|| ycode
== PRE_INC
1476 || ycode
== POST_DEC
|| ycode
== POST_INC
)
1479 /* The offset added here is chosen as the maximum offset that
1480 any instruction could need to add when operating on something
1481 of the specified mode. We assume that if Y and Y+c are
1482 valid addresses then so is Y+d for all 0<d<c. */
1484 z
= plus_constant_for_output (y
, GET_MODE_SIZE (mode
) - 1);
1486 /* Use QImode because an odd displacement may be automatically invalid
1487 for any wider mode. But it should be valid for a single byte. */
1488 return (*addressp
) (QImode
, z
);
1491 /* Return 1 if ADDR is an address-expression whose effect depends
1492 on the mode of the memory reference it is used in.
1494 Autoincrement addressing is a typical example of mode-dependence
1495 because the amount of the increment depends on the mode. */
1498 mode_dependent_address_p (addr
)
1501 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, win
);
1507 /* Return 1 if OP is a general operand
1508 other than a memory ref with a mode dependent address. */
1511 mode_independent_operand (op
, mode
)
1512 enum machine_mode mode
;
1517 if (! general_operand (op
, mode
))
1520 if (GET_CODE (op
) != MEM
)
1523 addr
= XEXP (op
, 0);
1524 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, lose
);
1530 /* Given an operand OP that is a valid memory reference
1531 which satisfies offsettable_memref_p,
1532 return a new memory reference whose address has been adjusted by OFFSET.
1533 OFFSET should be positive and less than the size of the object referenced.
1537 adj_offsettable_operand (op
, offset
)
1541 register enum rtx_code code
= GET_CODE (op
);
1545 register rtx y
= XEXP (op
, 0);
1548 if (CONSTANT_ADDRESS_P (y
))
1550 new = gen_rtx (MEM
, GET_MODE (op
), plus_constant_for_output (y
, offset
));
1551 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op
);
1555 if (GET_CODE (y
) == PLUS
)
1558 register rtx
*const_loc
;
1562 const_loc
= find_constant_term_loc (&z
);
1565 *const_loc
= plus_constant_for_output (*const_loc
, offset
);
1570 new = gen_rtx (MEM
, GET_MODE (op
), plus_constant_for_output (y
, offset
));
1571 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (op
);
1577 #ifdef REGISTER_CONSTRAINTS
1579 /* Check the operands of an insn (found in recog_operands)
1580 against the insn's operand constraints (found via INSN_CODE_NUM)
1581 and return 1 if they are valid.
1583 WHICH_ALTERNATIVE is set to a number which indicates which
1584 alternative of constraints was matched: 0 for the first alternative,
1585 1 for the next, etc.
1587 In addition, when two operands are match
1588 and it happens that the output operand is (reg) while the
1589 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
1590 make the output operand look like the input.
1591 This is because the output operand is the one the template will print.
1593 This is used in final, just before printing the assembler code and by
1594 the routines that determine an insn's attribute.
1596 If STRICT is a positive non-zero value, it means that we have been
1597 called after reload has been completed. In that case, we must
1598 do all checks strictly. If it is zero, it means that we have been called
1599 before reload has completed. In that case, we first try to see if we can
1600 find an alternative that matches strictly. If not, we try again, this
1601 time assuming that reload will fix up the insn. This provides a "best
1602 guess" for the alternative and is used to compute attributes of insns prior
1603 to reload. A negative value of STRICT is used for this internal call. */
1611 constrain_operands (insn_code_num
, strict
)
1615 char *constraints
[MAX_RECOG_OPERANDS
];
1616 int matching_operands
[MAX_RECOG_OPERANDS
];
1617 enum op_type
{OP_IN
, OP_OUT
, OP_INOUT
} op_types
[MAX_RECOG_OPERANDS
];
1618 int earlyclobber
[MAX_RECOG_OPERANDS
];
1620 int noperands
= insn_n_operands
[insn_code_num
];
1622 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
1623 int funny_match_index
;
1624 int nalternatives
= insn_n_alternatives
[insn_code_num
];
1626 if (noperands
== 0 || nalternatives
== 0)
1629 for (c
= 0; c
< noperands
; c
++)
1631 constraints
[c
] = insn_operand_constraint
[insn_code_num
][c
];
1632 matching_operands
[c
] = -1;
1633 op_types
[c
] = OP_IN
;
1636 which_alternative
= 0;
1638 while (which_alternative
< nalternatives
)
1642 funny_match_index
= 0;
1644 for (opno
= 0; opno
< noperands
; opno
++)
1646 register rtx op
= recog_operand
[opno
];
1647 enum machine_mode mode
= GET_MODE (op
);
1648 register char *p
= constraints
[opno
];
1653 earlyclobber
[opno
] = 0;
1655 if (GET_CODE (op
) == SUBREG
)
1657 if (GET_CODE (SUBREG_REG (op
)) == REG
1658 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
1659 offset
= SUBREG_WORD (op
);
1660 op
= SUBREG_REG (op
);
1663 /* An empty constraint or empty alternative
1664 allows anything which matched the pattern. */
1665 if (*p
== 0 || *p
== ',')
1668 while (*p
&& (c
= *p
++) != ',')
1678 /* Ignore rest of this alternative as far as
1679 constraint checking is concerned. */
1680 while (*p
&& *p
!= ',')
1685 op_types
[opno
] = OP_OUT
;
1689 op_types
[opno
] = OP_INOUT
;
1693 earlyclobber
[opno
] = 1;
1701 /* This operand must be the same as a previous one.
1702 This kind of constraint is used for instructions such
1703 as add when they take only two operands.
1705 Note that the lower-numbered operand is passed first.
1707 If we are not testing strictly, assume that this constraint
1708 will be satisfied. */
1712 val
= operands_match_p (recog_operand
[c
- '0'],
1713 recog_operand
[opno
]);
1715 matching_operands
[opno
] = c
- '0';
1716 matching_operands
[c
- '0'] = opno
;
1720 /* If output is *x and input is *--x,
1721 arrange later to change the output to *--x as well,
1722 since the output op is the one that will be printed. */
1723 if (val
== 2 && strict
> 0)
1725 funny_match
[funny_match_index
].this = opno
;
1726 funny_match
[funny_match_index
++].other
= c
- '0';
1731 /* p is used for address_operands. When we are called by
1732 gen_reload, no one will have checked that the address is
1733 strictly valid, i.e., that all pseudos requiring hard regs
1734 have gotten them. */
1736 || (strict_memory_address_p
1737 (insn_operand_mode
[insn_code_num
][opno
], op
)))
1741 /* No need to check general_operand again;
1742 it was done in insn-recog.c. */
1744 /* Anything goes unless it is a REG and really has a hard reg
1745 but the hard reg is not in the class GENERAL_REGS. */
1747 || GENERAL_REGS
== ALL_REGS
1748 || GET_CODE (op
) != REG
1749 || (reload_in_progress
1750 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1751 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
1758 && GET_CODE (op
) == REG
1759 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1760 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
1761 || (GET_CODE (op
) == REG
1762 && ((GENERAL_REGS
== ALL_REGS
1763 && REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1764 || reg_fits_class_p (op
, GENERAL_REGS
,
1770 /* This is used for a MATCH_SCRATCH in the cases when
1771 we don't actually need anything. So anything goes
1777 if (GET_CODE (op
) == MEM
1778 /* Before reload, accept what reload can turn into mem. */
1779 || (strict
< 0 && CONSTANT_P (op
))
1780 /* During reload, accept a pseudo */
1781 || (reload_in_progress
&& GET_CODE (op
) == REG
1782 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
1787 if (GET_CODE (op
) == MEM
1788 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1789 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1794 if (GET_CODE (op
) == MEM
1795 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1796 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1801 #ifndef REAL_ARITHMETIC
1802 /* Match any CONST_DOUBLE, but only if
1803 we can examine the bits of it reliably. */
1804 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1805 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1806 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1809 if (GET_CODE (op
) == CONST_DOUBLE
)
1814 if (GET_CODE (op
) == CONST_DOUBLE
)
1820 if (GET_CODE (op
) == CONST_DOUBLE
1821 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1826 if (GET_CODE (op
) == CONST_INT
1827 || (GET_CODE (op
) == CONST_DOUBLE
1828 && GET_MODE (op
) == VOIDmode
))
1831 if (CONSTANT_P (op
))
1836 if (GET_CODE (op
) == CONST_INT
1837 || (GET_CODE (op
) == CONST_DOUBLE
1838 && GET_MODE (op
) == VOIDmode
))
1850 if (GET_CODE (op
) == CONST_INT
1851 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1855 #ifdef EXTRA_CONSTRAINT
1861 if (EXTRA_CONSTRAINT (op
, c
))
1867 if (GET_CODE (op
) == MEM
1868 && ((strict
> 0 && ! offsettable_memref_p (op
))
1870 && !(CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
1871 || (reload_in_progress
1872 && !(GET_CODE (op
) == REG
1873 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
1878 if ((strict
> 0 && offsettable_memref_p (op
))
1879 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
1880 /* Before reload, accept what reload can handle. */
1882 && (CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
1883 /* During reload, accept a pseudo */
1884 || (reload_in_progress
&& GET_CODE (op
) == REG
1885 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
1892 && GET_CODE (op
) == REG
1893 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1894 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
1895 || (GET_CODE (op
) == REG
1896 && reg_fits_class_p (op
, REG_CLASS_FROM_LETTER (c
),
1901 constraints
[opno
] = p
;
1902 /* If this operand did not win somehow,
1903 this alternative loses. */
1907 /* This alternative won; the operands are ok.
1908 Change whichever operands this alternative says to change. */
1913 /* See if any earlyclobber operand conflicts with some other
1917 for (eopno
= 0; eopno
< noperands
; eopno
++)
1918 /* Ignore earlyclobber operands now in memory,
1919 because we would often report failure when we have
1920 two memory operands, one of which was formerly a REG. */
1921 if (earlyclobber
[eopno
]
1922 && GET_CODE (recog_operand
[eopno
]) == REG
)
1923 for (opno
= 0; opno
< noperands
; opno
++)
1924 if ((GET_CODE (recog_operand
[opno
]) == MEM
1925 || op_types
[opno
] != OP_OUT
)
1927 /* Ignore things like match_operator operands. */
1928 && *insn_operand_constraint
[insn_code_num
][opno
] != 0
1929 && ! (matching_operands
[opno
] == eopno
1930 && rtx_equal_p (recog_operand
[opno
],
1931 recog_operand
[eopno
]))
1932 && ! safe_from_earlyclobber (recog_operand
[opno
],
1933 recog_operand
[eopno
]))
1938 while (--funny_match_index
>= 0)
1940 recog_operand
[funny_match
[funny_match_index
].other
]
1941 = recog_operand
[funny_match
[funny_match_index
].this];
1948 which_alternative
++;
1951 /* If we are about to reject this, but we are not to test strictly,
1952 try a very loose test. Only return failure if it fails also. */
1954 return constrain_operands (insn_code_num
, -1);
1959 /* Return 1 iff OPERAND (assumed to be a REG rtx)
1960 is a hard reg in class CLASS when its regno is offsetted by OFFSET
1961 and changed to mode MODE.
1962 If REG occupies multiple hard regs, all of them must be in CLASS. */
1965 reg_fits_class_p (operand
, class, offset
, mode
)
1967 register enum reg_class
class;
1969 enum machine_mode mode
;
1971 register int regno
= REGNO (operand
);
1972 if (regno
< FIRST_PSEUDO_REGISTER
1973 && TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
1978 for (sr
= HARD_REGNO_NREGS (regno
, mode
) - 1;
1980 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
1989 #endif /* REGISTER_CONSTRAINTS */
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