1 @c Copyright (C) 1988,89,92,93,94,96 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
7 @chapter Machine Descriptions
8 @cindex machine descriptions
10 A machine description has two parts: a file of instruction patterns
11 (@file{.md} file) and a C header file of macro definitions.
13 The @file{.md} file for a target machine contains a pattern for each
14 instruction that the target machine supports (or at least each instruction
15 that is worth telling the compiler about). It may also contain comments.
16 A semicolon causes the rest of the line to be a comment, unless the semicolon
17 is inside a quoted string.
19 See the next chapter for information on the C header file.
22 * Patterns:: How to write instruction patterns.
23 * Example:: An explained example of a @code{define_insn} pattern.
24 * RTL Template:: The RTL template defines what insns match a pattern.
25 * Output Template:: The output template says how to make assembler code
27 * Output Statement:: For more generality, write C code to output
29 * Constraints:: When not all operands are general operands.
30 * Standard Names:: Names mark patterns to use for code generation.
31 * Pattern Ordering:: When the order of patterns makes a difference.
32 * Dependent Patterns:: Having one pattern may make you need another.
33 * Jump Patterns:: Special considerations for patterns for jump insns.
34 * Insn Canonicalizations::Canonicalization of Instructions
35 * Peephole Definitions::Defining machine-specific peephole optimizations.
36 * Expander Definitions::Generating a sequence of several RTL insns
37 for a standard operation.
38 * Insn Splitting:: Splitting Instructions into Multiple Instructions
39 * Insn Attributes:: Specifying the value of attributes for generated insns.
43 @section Everything about Instruction Patterns
45 @cindex instruction patterns
48 Each instruction pattern contains an incomplete RTL expression, with pieces
49 to be filled in later, operand constraints that restrict how the pieces can
50 be filled in, and an output pattern or C code to generate the assembler
51 output, all wrapped up in a @code{define_insn} expression.
53 A @code{define_insn} is an RTL expression containing four or five operands:
57 An optional name. The presence of a name indicate that this instruction
58 pattern can perform a certain standard job for the RTL-generation
59 pass of the compiler. This pass knows certain names and will use
60 the instruction patterns with those names, if the names are defined
61 in the machine description.
63 The absence of a name is indicated by writing an empty string
64 where the name should go. Nameless instruction patterns are never
65 used for generating RTL code, but they may permit several simpler insns
66 to be combined later on.
68 Names that are not thus known and used in RTL-generation have no
69 effect; they are equivalent to no name at all.
72 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
73 RTL expressions which show what the instruction should look like. It is
74 incomplete because it may contain @code{match_operand},
75 @code{match_operator}, and @code{match_dup} expressions that stand for
76 operands of the instruction.
78 If the vector has only one element, that element is the template for the
79 instruction pattern. If the vector has multiple elements, then the
80 instruction pattern is a @code{parallel} expression containing the
84 @cindex pattern conditions
85 @cindex conditions, in patterns
86 A condition. This is a string which contains a C expression that is
87 the final test to decide whether an insn body matches this pattern.
89 @cindex named patterns and conditions
90 For a named pattern, the condition (if present) may not depend on
91 the data in the insn being matched, but only the target-machine-type
92 flags. The compiler needs to test these conditions during
93 initialization in order to learn exactly which named instructions are
94 available in a particular run.
97 For nameless patterns, the condition is applied only when matching an
98 individual insn, and only after the insn has matched the pattern's
99 recognition template. The insn's operands may be found in the vector
103 The @dfn{output template}: a string that says how to output matching
104 insns as assembler code. @samp{%} in this string specifies where
105 to substitute the value of an operand. @xref{Output Template}.
107 When simple substitution isn't general enough, you can specify a piece
108 of C code to compute the output. @xref{Output Statement}.
111 Optionally, a vector containing the values of attributes for insns matching
112 this pattern. @xref{Insn Attributes}.
116 @section Example of @code{define_insn}
117 @cindex @code{define_insn} example
119 Here is an actual example of an instruction pattern, for the 68000/68020.
124 (match_operand:SI 0 "general_operand" "rm"))]
127 @{ if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
129 return \"cmpl #0,%0\"; @}")
132 This is an instruction that sets the condition codes based on the value of
133 a general operand. It has no condition, so any insn whose RTL description
134 has the form shown may be handled according to this pattern. The name
135 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
136 pass that, when it is necessary to test such a value, an insn to do so
137 can be constructed using this pattern.
139 The output control string is a piece of C code which chooses which
140 output template to return based on the kind of operand and the specific
141 type of CPU for which code is being generated.
143 @samp{"rm"} is an operand constraint. Its meaning is explained below.
146 @section RTL Template
147 @cindex RTL insn template
148 @cindex generating insns
149 @cindex insns, generating
150 @cindex recognizing insns
151 @cindex insns, recognizing
153 The RTL template is used to define which insns match the particular pattern
154 and how to find their operands. For named patterns, the RTL template also
155 says how to construct an insn from specified operands.
157 Construction involves substituting specified operands into a copy of the
158 template. Matching involves determining the values that serve as the
159 operands in the insn being matched. Both of these activities are
160 controlled by special expression types that direct matching and
161 substitution of the operands.
164 @findex match_operand
165 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
166 This expression is a placeholder for operand number @var{n} of
167 the insn. When constructing an insn, operand number @var{n}
168 will be substituted at this point. When matching an insn, whatever
169 appears at this position in the insn will be taken as operand
170 number @var{n}; but it must satisfy @var{predicate} or this instruction
171 pattern will not match at all.
173 Operand numbers must be chosen consecutively counting from zero in
174 each instruction pattern. There may be only one @code{match_operand}
175 expression in the pattern for each operand number. Usually operands
176 are numbered in the order of appearance in @code{match_operand}
177 expressions. In the case of a @code{define_expand}, any operand numbers
178 used only in @code{match_dup} expressions have higher values than all
179 other operand numbers.
181 @var{predicate} is a string that is the name of a C function that accepts two
182 arguments, an expression and a machine mode. During matching, the
183 function will be called with the putative operand as the expression and
184 @var{m} as the mode argument (if @var{m} is not specified,
185 @code{VOIDmode} will be used, which normally causes @var{predicate} to accept
186 any mode). If it returns zero, this instruction pattern fails to match.
187 @var{predicate} may be an empty string; then it means no test is to be done
188 on the operand, so anything which occurs in this position is valid.
190 Most of the time, @var{predicate} will reject modes other than @var{m}---but
191 not always. For example, the predicate @code{address_operand} uses
192 @var{m} as the mode of memory ref that the address should be valid for.
193 Many predicates accept @code{const_int} nodes even though their mode is
196 @var{constraint} controls reloading and the choice of the best register
197 class to use for a value, as explained later (@pxref{Constraints}).
199 People are often unclear on the difference between the constraint and the
200 predicate. The predicate helps decide whether a given insn matches the
201 pattern. The constraint plays no role in this decision; instead, it
202 controls various decisions in the case of an insn which does match.
204 @findex general_operand
205 On CISC machines, the most common @var{predicate} is
206 @code{"general_operand"}. This function checks that the putative
207 operand is either a constant, a register or a memory reference, and that
208 it is valid for mode @var{m}.
210 @findex register_operand
211 For an operand that must be a register, @var{predicate} should be
212 @code{"register_operand"}. Using @code{"general_operand"} would be
213 valid, since the reload pass would copy any non-register operands
214 through registers, but this would make GNU CC do extra work, it would
215 prevent invariant operands (such as constant) from being removed from
216 loops, and it would prevent the register allocator from doing the best
217 possible job. On RISC machines, it is usually most efficient to allow
218 @var{predicate} to accept only objects that the constraints allow.
220 @findex immediate_operand
221 For an operand that must be a constant, you must be sure to either use
222 @code{"immediate_operand"} for @var{predicate}, or make the instruction
223 pattern's extra condition require a constant, or both. You cannot
224 expect the constraints to do this work! If the constraints allow only
225 constants, but the predicate allows something else, the compiler will
226 crash when that case arises.
228 @findex match_scratch
229 @item (match_scratch:@var{m} @var{n} @var{constraint})
230 This expression is also a placeholder for operand number @var{n}
231 and indicates that operand must be a @code{scratch} or @code{reg}
234 When matching patterns, this is equivalent to
237 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
240 but, when generating RTL, it produces a (@code{scratch}:@var{m})
243 If the last few expressions in a @code{parallel} are @code{clobber}
244 expressions whose operands are either a hard register or
245 @code{match_scratch}, the combiner can add or delete them when
246 necessary. @xref{Side Effects}.
249 @item (match_dup @var{n})
250 This expression is also a placeholder for operand number @var{n}.
251 It is used when the operand needs to appear more than once in the
254 In construction, @code{match_dup} acts just like @code{match_operand}:
255 the operand is substituted into the insn being constructed. But in
256 matching, @code{match_dup} behaves differently. It assumes that operand
257 number @var{n} has already been determined by a @code{match_operand}
258 appearing earlier in the recognition template, and it matches only an
259 identical-looking expression.
261 @findex match_operator
262 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
263 This pattern is a kind of placeholder for a variable RTL expression
266 When constructing an insn, it stands for an RTL expression whose
267 expression code is taken from that of operand @var{n}, and whose
268 operands are constructed from the patterns @var{operands}.
270 When matching an expression, it matches an expression if the function
271 @var{predicate} returns nonzero on that expression @emph{and} the
272 patterns @var{operands} match the operands of the expression.
274 Suppose that the function @code{commutative_operator} is defined as
275 follows, to match any expression whose operator is one of the
276 commutative arithmetic operators of RTL and whose mode is @var{mode}:
280 commutative_operator (x, mode)
282 enum machine_mode mode;
284 enum rtx_code code = GET_CODE (x);
285 if (GET_MODE (x) != mode)
287 return (GET_RTX_CLASS (code) == 'c'
288 || code == EQ || code == NE);
292 Then the following pattern will match any RTL expression consisting
293 of a commutative operator applied to two general operands:
296 (match_operator:SI 3 "commutative_operator"
297 [(match_operand:SI 1 "general_operand" "g")
298 (match_operand:SI 2 "general_operand" "g")])
301 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
302 because the expressions to be matched all contain two operands.
304 When this pattern does match, the two operands of the commutative
305 operator are recorded as operands 1 and 2 of the insn. (This is done
306 by the two instances of @code{match_operand}.) Operand 3 of the insn
307 will be the entire commutative expression: use @code{GET_CODE
308 (operands[3])} to see which commutative operator was used.
310 The machine mode @var{m} of @code{match_operator} works like that of
311 @code{match_operand}: it is passed as the second argument to the
312 predicate function, and that function is solely responsible for
313 deciding whether the expression to be matched ``has'' that mode.
315 When constructing an insn, argument 3 of the gen-function will specify
316 the operation (i.e. the expression code) for the expression to be
317 made. It should be an RTL expression, whose expression code is copied
318 into a new expression whose operands are arguments 1 and 2 of the
319 gen-function. The subexpressions of argument 3 are not used;
320 only its expression code matters.
322 When @code{match_operator} is used in a pattern for matching an insn,
323 it usually best if the operand number of the @code{match_operator}
324 is higher than that of the actual operands of the insn. This improves
325 register allocation because the register allocator often looks at
326 operands 1 and 2 of insns to see if it can do register tying.
328 There is no way to specify constraints in @code{match_operator}. The
329 operand of the insn which corresponds to the @code{match_operator}
330 never has any constraints because it is never reloaded as a whole.
331 However, if parts of its @var{operands} are matched by
332 @code{match_operand} patterns, those parts may have constraints of
336 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
337 Like @code{match_dup}, except that it applies to operators instead of
338 operands. When constructing an insn, operand number @var{n} will be
339 substituted at this point. But in matching, @code{match_op_dup} behaves
340 differently. It assumes that operand number @var{n} has already been
341 determined by a @code{match_operator} appearing earlier in the
342 recognition template, and it matches only an identical-looking
345 @findex match_parallel
346 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
347 This pattern is a placeholder for an insn that consists of a
348 @code{parallel} expression with a variable number of elements. This
349 expression should only appear at the top level of an insn pattern.
351 When constructing an insn, operand number @var{n} will be substituted at
352 this point. When matching an insn, it matches if the body of the insn
353 is a @code{parallel} expression with at least as many elements as the
354 vector of @var{subpat} expressions in the @code{match_parallel}, if each
355 @var{subpat} matches the corresponding element of the @code{parallel},
356 @emph{and} the function @var{predicate} returns nonzero on the
357 @code{parallel} that is the body of the insn. It is the responsibility
358 of the predicate to validate elements of the @code{parallel} beyond
359 those listed in the @code{match_parallel}.@refill
361 A typical use of @code{match_parallel} is to match load and store
362 multiple expressions, which can contain a variable number of elements
363 in a @code{parallel}. For example,
364 @c the following is *still* going over. need to change the code.
365 @c also need to work on grouping of this example. --mew 1feb93
369 [(match_parallel 0 "load_multiple_operation"
370 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
371 (match_operand:SI 2 "memory_operand" "m"))
373 (clobber (reg:SI 179))])]
378 This example comes from @file{a29k.md}. The function
379 @code{load_multiple_operations} is defined in @file{a29k.c} and checks
380 that subsequent elements in the @code{parallel} are the same as the
381 @code{set} in the pattern, except that they are referencing subsequent
382 registers and memory locations.
384 An insn that matches this pattern might look like:
388 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
390 (clobber (reg:SI 179))
392 (mem:SI (plus:SI (reg:SI 100)
395 (mem:SI (plus:SI (reg:SI 100)
399 @findex match_par_dup
400 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
401 Like @code{match_op_dup}, but for @code{match_parallel} instead of
402 @code{match_operator}.
405 @item (address (match_operand:@var{m} @var{n} "address_operand" ""))
406 This complex of expressions is a placeholder for an operand number
407 @var{n} in a ``load address'' instruction: an operand which specifies
408 a memory location in the usual way, but for which the actual operand
409 value used is the address of the location, not the contents of the
412 @code{address} expressions never appear in RTL code, only in machine
413 descriptions. And they are used only in machine descriptions that do
414 not use the operand constraint feature. When operand constraints are
415 in use, the letter @samp{p} in the constraint serves this purpose.
417 @var{m} is the machine mode of the @emph{memory location being
418 addressed}, not the machine mode of the address itself. That mode is
419 always the same on a given target machine (it is @code{Pmode}, which
420 normally is @code{SImode}), so there is no point in mentioning it;
421 thus, no machine mode is written in the @code{address} expression. If
422 some day support is added for machines in which addresses of different
423 kinds of objects appear differently or are used differently (such as
424 the PDP-10), different formats would perhaps need different machine
425 modes and these modes might be written in the @code{address}
429 @node Output Template
430 @section Output Templates and Operand Substitution
431 @cindex output templates
432 @cindex operand substitution
434 @cindex @samp{%} in template
436 The @dfn{output template} is a string which specifies how to output the
437 assembler code for an instruction pattern. Most of the template is a
438 fixed string which is output literally. The character @samp{%} is used
439 to specify where to substitute an operand; it can also be used to
440 identify places where different variants of the assembler require
443 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
444 operand @var{n} at that point in the string.
446 @samp{%} followed by a letter and a digit says to output an operand in an
447 alternate fashion. Four letters have standard, built-in meanings described
448 below. The machine description macro @code{PRINT_OPERAND} can define
449 additional letters with nonstandard meanings.
451 @samp{%c@var{digit}} can be used to substitute an operand that is a
452 constant value without the syntax that normally indicates an immediate
455 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
456 the constant is negated before printing.
458 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
459 memory reference, with the actual operand treated as the address. This may
460 be useful when outputting a ``load address'' instruction, because often the
461 assembler syntax for such an instruction requires you to write the operand
462 as if it were a memory reference.
464 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
467 @samp{%=} outputs a number which is unique to each instruction in the
468 entire compilation. This is useful for making local labels to be
469 referred to more than once in a single template that generates multiple
470 assembler instructions.
472 @samp{%} followed by a punctuation character specifies a substitution that
473 does not use an operand. Only one case is standard: @samp{%%} outputs a
474 @samp{%} into the assembler code. Other nonstandard cases can be
475 defined in the @code{PRINT_OPERAND} macro. You must also define
476 which punctuation characters are valid with the
477 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
481 The template may generate multiple assembler instructions. Write the text
482 for the instructions, with @samp{\;} between them.
484 @cindex matching operands
485 When the RTL contains two operands which are required by constraint to match
486 each other, the output template must refer only to the lower-numbered operand.
487 Matching operands are not always identical, and the rest of the compiler
488 arranges to put the proper RTL expression for printing into the lower-numbered
491 One use of nonstandard letters or punctuation following @samp{%} is to
492 distinguish between different assembler languages for the same machine; for
493 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
494 requires periods in most opcode names, while MIT syntax does not. For
495 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
496 syntax. The same file of patterns is used for both kinds of output syntax,
497 but the character sequence @samp{%.} is used in each place where Motorola
498 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
499 defines the sequence to output a period; the macro for MIT syntax defines
502 @cindex @code{#} in template
503 As a special case, a template consisting of the single character @code{#}
504 instructs the compiler to first split the insn, and then output the
505 resulting instructions separately. This helps eliminate redundancy in the
506 output templates. If you have a @code{define_insn} that needs to emit
507 multiple assembler instructions, and there is an matching @code{define_split}
508 already defined, then you can simply use @code{#} as the output template
509 instead of writing an output template that emits the multiple assembler
512 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
513 of the form @samp{@{option0|option1|option2@}} in the templates. These
514 describe multiple variants of assembler language syntax.
515 @xref{Instruction Output}.
517 @node Output Statement
518 @section C Statements for Assembler Output
519 @cindex output statements
520 @cindex C statements for assembler output
521 @cindex generating assembler output
523 Often a single fixed template string cannot produce correct and efficient
524 assembler code for all the cases that are recognized by a single
525 instruction pattern. For example, the opcodes may depend on the kinds of
526 operands; or some unfortunate combinations of operands may require extra
527 machine instructions.
529 If the output control string starts with a @samp{@@}, then it is actually
530 a series of templates, each on a separate line. (Blank lines and
531 leading spaces and tabs are ignored.) The templates correspond to the
532 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
533 if a target machine has a two-address add instruction @samp{addr} to add
534 into a register and another @samp{addm} to add a register to memory, you
535 might write this pattern:
538 (define_insn "addsi3"
539 [(set (match_operand:SI 0 "general_operand" "=r,m")
540 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
541 (match_operand:SI 2 "general_operand" "g,r")))]
548 @cindex @code{*} in template
549 @cindex asterisk in template
550 If the output control string starts with a @samp{*}, then it is not an
551 output template but rather a piece of C program that should compute a
552 template. It should execute a @code{return} statement to return the
553 template-string you want. Most such templates use C string literals, which
554 require doublequote characters to delimit them. To include these
555 doublequote characters in the string, prefix each one with @samp{\}.
557 The operands may be found in the array @code{operands}, whose C data type
560 It is very common to select different ways of generating assembler code
561 based on whether an immediate operand is within a certain range. Be
562 careful when doing this, because the result of @code{INTVAL} is an
563 integer on the host machine. If the host machine has more bits in an
564 @code{int} than the target machine has in the mode in which the constant
565 will be used, then some of the bits you get from @code{INTVAL} will be
566 superfluous. For proper results, you must carefully disregard the
567 values of those bits.
569 @findex output_asm_insn
570 It is possible to output an assembler instruction and then go on to output
571 or compute more of them, using the subroutine @code{output_asm_insn}. This
572 receives two arguments: a template-string and a vector of operands. The
573 vector may be @code{operands}, or it may be another array of @code{rtx}
574 that you declare locally and initialize yourself.
576 @findex which_alternative
577 When an insn pattern has multiple alternatives in its constraints, often
578 the appearance of the assembler code is determined mostly by which alternative
579 was matched. When this is so, the C code can test the variable
580 @code{which_alternative}, which is the ordinal number of the alternative
581 that was actually satisfied (0 for the first, 1 for the second alternative,
584 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
585 for registers and @samp{clrmem} for memory locations. Here is how
586 a pattern could use @code{which_alternative} to choose between them:
590 [(set (match_operand:SI 0 "general_operand" "=r,m")
594 return (which_alternative == 0
595 ? \"clrreg %0\" : \"clrmem %0\");
599 The example above, where the assembler code to generate was
600 @emph{solely} determined by the alternative, could also have been specified
601 as follows, having the output control string start with a @samp{@@}:
606 [(set (match_operand:SI 0 "general_operand" "=r,m")
616 @c Most of this node appears by itself (in a different place) even
617 @c when the INTERNALS flag is clear. Passages that require the full
618 @c manual's context are conditionalized to appear only in the full manual.
621 @section Operand Constraints
622 @cindex operand constraints
625 Each @code{match_operand} in an instruction pattern can specify a
626 constraint for the type of operands allowed.
630 @section Constraints for @code{asm} Operands
631 @cindex operand constraints, @code{asm}
632 @cindex constraints, @code{asm}
633 @cindex @code{asm} constraints
635 Here are specific details on what constraint letters you can use with
638 Constraints can say whether
639 an operand may be in a register, and which kinds of register; whether the
640 operand can be a memory reference, and which kinds of address; whether the
641 operand may be an immediate constant, and which possible values it may
642 have. Constraints can also require two operands to match.
646 * Simple Constraints:: Basic use of constraints.
647 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
648 * Class Preferences:: Constraints guide which hard register to put things in.
649 * Modifiers:: More precise control over effects of constraints.
650 * Machine Constraints:: Existing constraints for some particular machines.
651 * No Constraints:: Describing a clean machine without constraints.
657 * Simple Constraints:: Basic use of constraints.
658 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
659 * Modifiers:: More precise control over effects of constraints.
660 * Machine Constraints:: Special constraints for some particular machines.
664 @node Simple Constraints
665 @subsection Simple Constraints
666 @cindex simple constraints
668 The simplest kind of constraint is a string full of letters, each of
669 which describes one kind of operand that is permitted. Here are
670 the letters that are allowed:
673 @cindex @samp{m} in constraint
674 @cindex memory references in constraints
676 A memory operand is allowed, with any kind of address that the machine
679 @cindex offsettable address
680 @cindex @samp{o} in constraint
682 A memory operand is allowed, but only if the address is
683 @dfn{offsettable}. This means that adding a small integer (actually,
684 the width in bytes of the operand, as determined by its machine mode)
685 may be added to the address and the result is also a valid memory
688 @cindex autoincrement/decrement addressing
689 For example, an address which is constant is offsettable; so is an
690 address that is the sum of a register and a constant (as long as a
691 slightly larger constant is also within the range of address-offsets
692 supported by the machine); but an autoincrement or autodecrement
693 address is not offsettable. More complicated indirect/indexed
694 addresses may or may not be offsettable depending on the other
695 addressing modes that the machine supports.
697 Note that in an output operand which can be matched by another
698 operand, the constraint letter @samp{o} is valid only when accompanied
699 by both @samp{<} (if the target machine has predecrement addressing)
700 and @samp{>} (if the target machine has preincrement addressing).
702 @cindex @samp{V} in constraint
704 A memory operand that is not offsettable. In other words, anything that
705 would fit the @samp{m} constraint but not the @samp{o} constraint.
707 @cindex @samp{<} in constraint
709 A memory operand with autodecrement addressing (either predecrement or
710 postdecrement) is allowed.
712 @cindex @samp{>} in constraint
714 A memory operand with autoincrement addressing (either preincrement or
715 postincrement) is allowed.
717 @cindex @samp{r} in constraint
718 @cindex registers in constraints
720 A register operand is allowed provided that it is in a general
723 @cindex @samp{d} in constraint
724 @item @samp{d}, @samp{a}, @samp{f}, @dots{}
725 Other letters can be defined in machine-dependent fashion to stand for
726 particular classes of registers. @samp{d}, @samp{a} and @samp{f} are
727 defined on the 68000/68020 to stand for data, address and floating
730 @cindex constants in constraints
731 @cindex @samp{i} in constraint
733 An immediate integer operand (one with constant value) is allowed.
734 This includes symbolic constants whose values will be known only at
737 @cindex @samp{n} in constraint
739 An immediate integer operand with a known numeric value is allowed.
740 Many systems cannot support assembly-time constants for operands less
741 than a word wide. Constraints for these operands should use @samp{n}
742 rather than @samp{i}.
744 @cindex @samp{I} in constraint
745 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
746 Other letters in the range @samp{I} through @samp{P} may be defined in
747 a machine-dependent fashion to permit immediate integer operands with
748 explicit integer values in specified ranges. For example, on the
749 68000, @samp{I} is defined to stand for the range of values 1 to 8.
750 This is the range permitted as a shift count in the shift
753 @cindex @samp{E} in constraint
755 An immediate floating operand (expression code @code{const_double}) is
756 allowed, but only if the target floating point format is the same as
757 that of the host machine (on which the compiler is running).
759 @cindex @samp{F} in constraint
761 An immediate floating operand (expression code @code{const_double}) is
764 @cindex @samp{G} in constraint
765 @cindex @samp{H} in constraint
766 @item @samp{G}, @samp{H}
767 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
768 permit immediate floating operands in particular ranges of values.
770 @cindex @samp{s} in constraint
772 An immediate integer operand whose value is not an explicit integer is
775 This might appear strange; if an insn allows a constant operand with a
776 value not known at compile time, it certainly must allow any known
777 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
778 better code to be generated.
780 For example, on the 68000 in a fullword instruction it is possible to
781 use an immediate operand; but if the immediate value is between -128
782 and 127, better code results from loading the value into a register and
783 using the register. This is because the load into the register can be
784 done with a @samp{moveq} instruction. We arrange for this to happen
785 by defining the letter @samp{K} to mean ``any integer outside the
786 range -128 to 127'', and then specifying @samp{Ks} in the operand
789 @cindex @samp{g} in constraint
791 Any register, memory or immediate integer operand is allowed, except for
792 registers that are not general registers.
794 @cindex @samp{X} in constraint
797 Any operand whatsoever is allowed, even if it does not satisfy
798 @code{general_operand}. This is normally used in the constraint of
799 a @code{match_scratch} when certain alternatives will not actually
800 require a scratch register.
803 Any operand whatsoever is allowed.
806 @cindex @samp{0} in constraint
807 @cindex digits in constraint
808 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
809 An operand that matches the specified operand number is allowed. If a
810 digit is used together with letters within the same alternative, the
811 digit should come last.
813 @cindex matching constraint
814 @cindex constraint, matching
815 This is called a @dfn{matching constraint} and what it really means is
816 that the assembler has only a single operand that fills two roles
818 considered separate in the RTL insn. For example, an add insn has two
819 input operands and one output operand in the RTL, but on most CISC
822 which @code{asm} distinguishes. For example, an add instruction uses
823 two input operands and an output operand, but on most CISC
825 machines an add instruction really has only two operands, one of them an
826 input-output operand:
832 Matching constraints are used in these circumstances.
833 More precisely, the two operands that match must include one input-only
834 operand and one output-only operand. Moreover, the digit must be a
835 smaller number than the number of the operand that uses it in the
839 For operands to match in a particular case usually means that they
840 are identical-looking RTL expressions. But in a few special cases
841 specific kinds of dissimilarity are allowed. For example, @code{*x}
842 as an input operand will match @code{*x++} as an output operand.
843 For proper results in such cases, the output template should always
844 use the output-operand's number when printing the operand.
847 @cindex load address instruction
848 @cindex push address instruction
849 @cindex address constraints
850 @cindex @samp{p} in constraint
852 An operand that is a valid memory address is allowed. This is
853 for ``load address'' and ``push address'' instructions.
855 @findex address_operand
856 @samp{p} in the constraint must be accompanied by @code{address_operand}
857 as the predicate in the @code{match_operand}. This predicate interprets
858 the mode specified in the @code{match_operand} as the mode of the memory
859 reference for which the address would be valid.
861 @cindex extensible constraints
862 @cindex @samp{Q}, in constraint
863 @item @samp{Q}, @samp{R}, @samp{S}, @dots{} @samp{U}
864 Letters in the range @samp{Q} through @samp{U} may be defined in a
865 machine-dependent fashion to stand for arbitrary operand types.
867 The machine description macro @code{EXTRA_CONSTRAINT} is passed the
868 operand as its first argument and the constraint letter as its
871 A typical use for this would be to distinguish certain types of
872 memory references that affect other insn operands.
874 Do not define these constraint letters to accept register references
875 (@code{reg}); the reload pass does not expect this and would not handle
881 In order to have valid assembler code, each operand must satisfy
882 its constraint. But a failure to do so does not prevent the pattern
883 from applying to an insn. Instead, it directs the compiler to modify
884 the code so that the constraint will be satisfied. Usually this is
885 done by copying an operand into a register.
887 Contrast, therefore, the two instruction patterns that follow:
891 [(set (match_operand:SI 0 "general_operand" "=r")
892 (plus:SI (match_dup 0)
893 (match_operand:SI 1 "general_operand" "r")))]
899 which has two operands, one of which must appear in two places, and
903 [(set (match_operand:SI 0 "general_operand" "=r")
904 (plus:SI (match_operand:SI 1 "general_operand" "0")
905 (match_operand:SI 2 "general_operand" "r")))]
911 which has three operands, two of which are required by a constraint to be
912 identical. If we are considering an insn of the form
915 (insn @var{n} @var{prev} @var{next}
917 (plus:SI (reg:SI 6) (reg:SI 109)))
922 the first pattern would not apply at all, because this insn does not
923 contain two identical subexpressions in the right place. The pattern would
924 say, ``That does not look like an add instruction; try other patterns.''
925 The second pattern would say, ``Yes, that's an add instruction, but there
926 is something wrong with it.'' It would direct the reload pass of the
927 compiler to generate additional insns to make the constraint true. The
928 results might look like this:
931 (insn @var{n2} @var{prev} @var{n}
932 (set (reg:SI 3) (reg:SI 6))
935 (insn @var{n} @var{n2} @var{next}
937 (plus:SI (reg:SI 3) (reg:SI 109)))
941 It is up to you to make sure that each operand, in each pattern, has
942 constraints that can handle any RTL expression that could be present for
943 that operand. (When multiple alternatives are in use, each pattern must,
944 for each possible combination of operand expressions, have at least one
945 alternative which can handle that combination of operands.) The
946 constraints don't need to @emph{allow} any possible operand---when this is
947 the case, they do not constrain---but they must at least point the way to
948 reloading any possible operand so that it will fit.
952 If the constraint accepts whatever operands the predicate permits,
953 there is no problem: reloading is never necessary for this operand.
955 For example, an operand whose constraints permit everything except
956 registers is safe provided its predicate rejects registers.
958 An operand whose predicate accepts only constant values is safe
959 provided its constraints include the letter @samp{i}. If any possible
960 constant value is accepted, then nothing less than @samp{i} will do;
961 if the predicate is more selective, then the constraints may also be
965 Any operand expression can be reloaded by copying it into a register.
966 So if an operand's constraints allow some kind of register, it is
967 certain to be safe. It need not permit all classes of registers; the
968 compiler knows how to copy a register into another register of the
969 proper class in order to make an instruction valid.
971 @cindex nonoffsettable memory reference
972 @cindex memory reference, nonoffsettable
974 A nonoffsettable memory reference can be reloaded by copying the
975 address into a register. So if the constraint uses the letter
976 @samp{o}, all memory references are taken care of.
979 A constant operand can be reloaded by allocating space in memory to
980 hold it as preinitialized data. Then the memory reference can be used
981 in place of the constant. So if the constraint uses the letters
982 @samp{o} or @samp{m}, constant operands are not a problem.
985 If the constraint permits a constant and a pseudo register used in an insn
986 was not allocated to a hard register and is equivalent to a constant,
987 the register will be replaced with the constant. If the predicate does
988 not permit a constant and the insn is re-recognized for some reason, the
989 compiler will crash. Thus the predicate must always recognize any
990 objects allowed by the constraint.
993 If the operand's predicate can recognize registers, but the constraint does
994 not permit them, it can make the compiler crash. When this operand happens
995 to be a register, the reload pass will be stymied, because it does not know
996 how to copy a register temporarily into memory.
998 If the predicate accepts a unary operator, the constraint applies to the
999 operand. For example, the MIPS processor at ISA level 3 supports an
1000 instruction which adds two registers in @code{SImode} to produce a
1001 @code{DImode} result, but only if the registers are correctly sign
1002 extended. This predicate for the input operands accepts a
1003 @code{sign_extend} of an @code{SImode} register. Write the constraint
1004 to indicate the type of register that is required for the operand of the
1008 @node Multi-Alternative
1009 @subsection Multiple Alternative Constraints
1010 @cindex multiple alternative constraints
1012 Sometimes a single instruction has multiple alternative sets of possible
1013 operands. For example, on the 68000, a logical-or instruction can combine
1014 register or an immediate value into memory, or it can combine any kind of
1015 operand into a register; but it cannot combine one memory location into
1018 These constraints are represented as multiple alternatives. An alternative
1019 can be described by a series of letters for each operand. The overall
1020 constraint for an operand is made from the letters for this operand
1021 from the first alternative, a comma, the letters for this operand from
1022 the second alternative, a comma, and so on until the last alternative.
1024 Here is how it is done for fullword logical-or on the 68000:
1027 (define_insn "iorsi3"
1028 [(set (match_operand:SI 0 "general_operand" "=m,d")
1029 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1030 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1034 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1035 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1036 2. The second alternative has @samp{d} (data register) for operand 0,
1037 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1038 @samp{%} in the constraints apply to all the alternatives; their
1039 meaning is explained in the next section (@pxref{Class Preferences}).
1042 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1043 If all the operands fit any one alternative, the instruction is valid.
1044 Otherwise, for each alternative, the compiler counts how many instructions
1045 must be added to copy the operands so that that alternative applies.
1046 The alternative requiring the least copying is chosen. If two alternatives
1047 need the same amount of copying, the one that comes first is chosen.
1048 These choices can be altered with the @samp{?} and @samp{!} characters:
1051 @cindex @samp{?} in constraint
1052 @cindex question mark
1054 Disparage slightly the alternative that the @samp{?} appears in,
1055 as a choice when no alternative applies exactly. The compiler regards
1056 this alternative as one unit more costly for each @samp{?} that appears
1059 @cindex @samp{!} in constraint
1060 @cindex exclamation point
1062 Disparage severely the alternative that the @samp{!} appears in.
1063 This alternative can still be used if it fits without reloading,
1064 but if reloading is needed, some other alternative will be used.
1068 When an insn pattern has multiple alternatives in its constraints, often
1069 the appearance of the assembler code is determined mostly by which
1070 alternative was matched. When this is so, the C code for writing the
1071 assembler code can use the variable @code{which_alternative}, which is
1072 the ordinal number of the alternative that was actually satisfied (0 for
1073 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1077 @node Class Preferences
1078 @subsection Register Class Preferences
1079 @cindex class preference constraints
1080 @cindex register class preference constraints
1082 @cindex voting between constraint alternatives
1083 The operand constraints have another function: they enable the compiler
1084 to decide which kind of hardware register a pseudo register is best
1085 allocated to. The compiler examines the constraints that apply to the
1086 insns that use the pseudo register, looking for the machine-dependent
1087 letters such as @samp{d} and @samp{a} that specify classes of registers.
1088 The pseudo register is put in whichever class gets the most ``votes''.
1089 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1090 favor of a general register. The machine description says which registers
1091 are considered general.
1093 Of course, on some machines all registers are equivalent, and no register
1094 classes are defined. Then none of this complexity is relevant.
1098 @subsection Constraint Modifier Characters
1099 @cindex modifiers in constraints
1100 @cindex constraint modifier characters
1102 @c prevent bad page break with this line
1103 Here are constraint modifier characters.
1106 @cindex @samp{=} in constraint
1108 Means that this operand is write-only for this instruction: the previous
1109 value is discarded and replaced by output data.
1111 @cindex @samp{+} in constraint
1113 Means that this operand is both read and written by the instruction.
1115 When the compiler fixes up the operands to satisfy the constraints,
1116 it needs to know which operands are inputs to the instruction and
1117 which are outputs from it. @samp{=} identifies an output; @samp{+}
1118 identifies an operand that is both input and output; all other operands
1119 are assumed to be input only.
1121 @cindex @samp{&} in constraint
1122 @cindex earlyclobber operand
1124 Means (in a particular alternative) that this operand is an
1125 @dfn{earlyclobber} operand, which is modified before the instruction is
1126 finished using the input operands. Therefore, this operand may not lie
1127 in a register that is used as an input operand or as part of any memory
1130 @samp{&} applies only to the alternative in which it is written. In
1131 constraints with multiple alternatives, sometimes one alternative
1132 requires @samp{&} while others do not. See, for example, the
1133 @samp{movdf} insn of the 68000.
1135 An input operand can be tied to an earlyclobber operand if its only
1136 use as an input occurs before the early result is written. Adding
1137 alternatives of this form often allows GCC to produce better code
1138 when only some of the inputs can be affected by the earlyclobber.
1139 See, for example, the @samp{mulsi3} insn of the ARM.
1141 @samp{&} does not obviate the need to write @samp{=}.
1143 @cindex @samp{%} in constraint
1145 Declares the instruction to be commutative for this operand and the
1146 following operand. This means that the compiler may interchange the
1147 two operands if that is the cheapest way to make all operands fit the
1150 This is often used in patterns for addition instructions
1151 that really have only two operands: the result must go in one of the
1152 arguments. Here for example, is how the 68000 halfword-add
1153 instruction is defined:
1156 (define_insn "addhi3"
1157 [(set (match_operand:HI 0 "general_operand" "=m,r")
1158 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1159 (match_operand:HI 2 "general_operand" "di,g")))]
1164 @cindex @samp{#} in constraint
1166 Says that all following characters, up to the next comma, are to be
1167 ignored as a constraint. They are significant only for choosing
1168 register preferences.
1171 @cindex @samp{*} in constraint
1173 Says that the following character should be ignored when choosing
1174 register preferences. @samp{*} has no effect on the meaning of the
1175 constraint as a constraint, and no effect on reloading.
1177 Here is an example: the 68000 has an instruction to sign-extend a
1178 halfword in a data register, and can also sign-extend a value by
1179 copying it into an address register. While either kind of register is
1180 acceptable, the constraints on an address-register destination are
1181 less strict, so it is best if register allocation makes an address
1182 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1183 constraint letter (for data register) is ignored when computing
1184 register preferences.
1187 (define_insn "extendhisi2"
1188 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1190 (match_operand:HI 1 "general_operand" "0,g")))]
1196 @node Machine Constraints
1197 @subsection Constraints for Particular Machines
1198 @cindex machine specific constraints
1199 @cindex constraints, machine specific
1201 Whenever possible, you should use the general-purpose constraint letters
1202 in @code{asm} arguments, since they will convey meaning more readily to
1203 people reading your code. Failing that, use the constraint letters
1204 that usually have very similar meanings across architectures. The most
1205 commonly used constraints are @samp{m} and @samp{r} (for memory and
1206 general-purpose registers respectively; @pxref{Simple Constraints}), and
1207 @samp{I}, usually the letter indicating the most common
1208 immediate-constant format.
1210 For each machine architecture, the @file{config/@var{machine}.h} file
1211 defines additional constraints. These constraints are used by the
1212 compiler itself for instruction generation, as well as for @code{asm}
1213 statements; therefore, some of the constraints are not particularly
1214 interesting for @code{asm}. The constraints are defined through these
1218 @item REG_CLASS_FROM_LETTER
1219 Register class constraints (usually lower case).
1221 @item CONST_OK_FOR_LETTER_P
1222 Immediate constant constraints, for non-floating point constants of
1223 word size or smaller precision (usually upper case).
1225 @item CONST_DOUBLE_OK_FOR_LETTER_P
1226 Immediate constant constraints, for all floating point constants and for
1227 constants of greater than word size precision (usually upper case).
1229 @item EXTRA_CONSTRAINT
1230 Special cases of registers or memory. This macro is not required, and
1231 is only defined for some machines.
1234 Inspecting these macro definitions in the compiler source for your
1235 machine is the best way to be certain you have the right constraints.
1236 However, here is a summary of the machine-dependent constraints
1237 available on some particular machines.
1240 @item ARM family---@file{arm.h}
1243 Floating-point register
1246 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1250 Floating-point constant that would satisfy the constraint @samp{F} if it
1254 Integer that is valid as an immediate operand in a data processing
1255 instruction. That is, an integer in the range 0 to 255 rotated by a
1259 Integer in the range -4095 to 4095
1262 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1265 Integer that satisfies constraint @samp{I} when negated (twos complement)
1268 Integer in the range 0 to 32
1271 A memory reference where the exact address is in a single register
1272 (`@samp{m}' is preferable for @code{asm} statements)
1275 An item in the constant pool
1278 A symbol in the text segment of the current file
1281 @item AMD 29000 family---@file{a29k.h}
1287 Byte Pointer (@samp{BP}) register
1293 Special purpose register
1296 First accumulator register
1299 Other accumulator register
1302 Floating point register
1305 Constant greater than 0, less than 0x100
1308 Constant greater than 0, less than 0x10000
1311 Constant whose high 24 bits are on (1)
1314 16 bit constant whose high 8 bits are on (1)
1317 32 bit constant whose high 16 bits are on (1)
1320 32 bit negative constant that fits in 8 bits
1323 The constant 0x80000000 or, on the 29050, any 32 bit constant
1324 whose low 16 bits are 0.
1327 16 bit negative constant that fits in 8 bits
1331 A floating point constant (in @code{asm} statements, use the machine
1332 independent @samp{E} or @samp{F} instead)
1335 @item IBM RS6000---@file{rs6000.h}
1338 Address base register
1341 Floating point register
1344 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
1353 @samp{LINK} register
1356 @samp{CR} register (condition register) number 0
1359 @samp{CR} register (condition register)
1362 Signed 16 bit constant
1365 Constant whose low 16 bits are 0
1368 Constant whose high 16 bits are 0
1371 Constant suitable as a mask operand
1374 Constant larger than 31
1383 Constant whose negation is a signed 16 bit constant
1386 Floating point constant that can be loaded into a register with one
1387 instruction per word
1390 Memory operand that is an offset from a register (@samp{m} is preferable
1391 for @code{asm} statements)
1397 Windows NT SYMBOL_REF
1400 Windows NT LABEL_REF
1403 System V Release 4 small data area reference
1406 @item Intel 386---@file{i386.h}
1409 @samp{a}, @code{b}, @code{c}, or @code{d} register
1412 @samp{a}, or @code{d} register (for 64-bit ints)
1415 Floating point register
1418 First (top of stack) floating point register
1421 Second floating point register
1442 Constant in range 0 to 31 (for 32 bit shifts)
1445 Constant in range 0 to 63 (for 64 bit shifts)
1454 0, 1, 2, or 3 (shifts for @code{lea} instruction)
1457 Constant in range 0 to 255 (for @code{out} instruction)
1460 Standard 80387 floating point constant
1463 @item Intel 960---@file{i960.h}
1466 Floating point register (@code{fp0} to @code{fp3})
1469 Local register (@code{r0} to @code{r15})
1472 Global register (@code{g0} to @code{g15})
1475 Any local or global register
1478 Integers from 0 to 31
1484 Integers from -31 to 0
1493 @item MIPS---@file{mips.h}
1496 General-purpose integer register
1499 Floating-point register (if available)
1508 @samp{Hi} or @samp{Lo} register
1511 General-purpose integer register
1514 Floating-point status register
1517 Signed 16 bit constant (for arithmetic instructions)
1523 Zero-extended 16-bit constant (for logic instructions)
1526 Constant with low 16 bits zero (can be loaded with @code{lui})
1529 32 bit constant which requires two instructions to load (a constant
1530 which is not @samp{I}, @samp{K}, or @samp{L})
1533 Negative 16 bit constant
1539 Positive 16 bit constant
1545 Memory reference that can be loaded with more than one instruction
1546 (@samp{m} is preferable for @code{asm} statements)
1549 Memory reference that can be loaded with one instruction
1550 (@samp{m} is preferable for @code{asm} statements)
1553 Memory reference in external OSF/rose PIC format
1554 (@samp{m} is preferable for @code{asm} statements)
1557 @item Motorola 680x0---@file{m68k.h}
1566 68881 floating-point register, if available
1569 Sun FPA (floating-point) register, if available
1572 First 16 Sun FPA registers, if available
1575 Integer in the range 1 to 8
1578 16 bit signed number
1581 Signed number whose magnitude is greater than 0x80
1584 Integer in the range -8 to -1
1587 Signed number whose magnitude is greater than 0x100
1590 Floating point constant that is not a 68881 constant
1593 Floating point constant that can be used by Sun FPA
1597 @item SPARC---@file{sparc.h}
1600 Floating-point register that can hold 32 or 64 bit values.
1603 Floating-point register that can hold 64 or 128 bit values.
1606 Signed 13 bit constant
1612 32 bit constant with the low 12 bits clear (a constant that can be
1613 loaded with the @code{sethi} instruction)
1619 Signed 13 bit constant, sign-extended to 32 or 64 bits
1622 Memory reference that can be loaded with one instruction (@samp{m} is
1623 more appropriate for @code{asm} statements)
1626 Constant, or memory address
1629 Memory address aligned to an 8-byte boundary
1637 @node No Constraints
1638 @subsection Not Using Constraints
1639 @cindex no constraints
1640 @cindex not using constraints
1642 Some machines are so clean that operand constraints are not required. For
1643 example, on the Vax, an operand valid in one context is valid in any other
1644 context. On such a machine, every operand constraint would be @samp{g},
1645 excepting only operands of ``load address'' instructions which are
1646 written as if they referred to a memory location's contents but actual
1647 refer to its address. They would have constraint @samp{p}.
1649 @cindex empty constraints
1650 For such machines, instead of writing @samp{g} and @samp{p} for all
1651 the constraints, you can choose to write a description with empty constraints.
1652 Then you write @samp{""} for the constraint in every @code{match_operand}.
1653 Address operands are identified by writing an @code{address} expression
1654 around the @code{match_operand}, not by their constraints.
1656 When the machine description has just empty constraints, certain parts
1657 of compilation are skipped, making the compiler faster. However,
1658 few machines actually do not need constraints; all machine descriptions
1659 now in existence use constraints.
1663 @node Standard Names
1664 @section Standard Pattern Names For Generation
1665 @cindex standard pattern names
1666 @cindex pattern names
1667 @cindex names, pattern
1669 Here is a table of the instruction names that are meaningful in the RTL
1670 generation pass of the compiler. Giving one of these names to an
1671 instruction pattern tells the RTL generation pass that it can use the
1672 pattern in to accomplish a certain task.
1675 @cindex @code{mov@var{m}} instruction pattern
1676 @item @samp{mov@var{m}}
1677 Here @var{m} stands for a two-letter machine mode name, in lower case.
1678 This instruction pattern moves data with that machine mode from operand
1679 1 to operand 0. For example, @samp{movsi} moves full-word data.
1681 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
1682 own mode is wider than @var{m}, the effect of this instruction is
1683 to store the specified value in the part of the register that corresponds
1684 to mode @var{m}. The effect on the rest of the register is undefined.
1686 This class of patterns is special in several ways. First of all, each
1687 of these names @emph{must} be defined, because there is no other way
1688 to copy a datum from one place to another.
1690 Second, these patterns are not used solely in the RTL generation pass.
1691 Even the reload pass can generate move insns to copy values from stack
1692 slots into temporary registers. When it does so, one of the operands is
1693 a hard register and the other is an operand that can need to be reloaded
1697 Therefore, when given such a pair of operands, the pattern must generate
1698 RTL which needs no reloading and needs no temporary registers---no
1699 registers other than the operands. For example, if you support the
1700 pattern with a @code{define_expand}, then in such a case the
1701 @code{define_expand} mustn't call @code{force_reg} or any other such
1702 function which might generate new pseudo registers.
1704 This requirement exists even for subword modes on a RISC machine where
1705 fetching those modes from memory normally requires several insns and
1706 some temporary registers. Look in @file{spur.md} to see how the
1707 requirement can be satisfied.
1709 @findex change_address
1710 During reload a memory reference with an invalid address may be passed
1711 as an operand. Such an address will be replaced with a valid address
1712 later in the reload pass. In this case, nothing may be done with the
1713 address except to use it as it stands. If it is copied, it will not be
1714 replaced with a valid address. No attempt should be made to make such
1715 an address into a valid address and no routine (such as
1716 @code{change_address}) that will do so may be called. Note that
1717 @code{general_operand} will fail when applied to such an address.
1719 @findex reload_in_progress
1720 The global variable @code{reload_in_progress} (which must be explicitly
1721 declared if required) can be used to determine whether such special
1722 handling is required.
1724 The variety of operands that have reloads depends on the rest of the
1725 machine description, but typically on a RISC machine these can only be
1726 pseudo registers that did not get hard registers, while on other
1727 machines explicit memory references will get optional reloads.
1729 If a scratch register is required to move an object to or from memory,
1730 it can be allocated using @code{gen_reg_rtx} prior to reload. But this
1731 is impossible during and after reload. If there are cases needing
1732 scratch registers after reload, you must define
1733 @code{SECONDARY_INPUT_RELOAD_CLASS} and perhaps also
1734 @code{SECONDARY_OUTPUT_RELOAD_CLASS} to detect them, and provide
1735 patterns @samp{reload_in@var{m}} or @samp{reload_out@var{m}} to handle
1736 them. @xref{Register Classes}.
1738 The constraints on a @samp{mov@var{m}} must permit moving any hard
1739 register to any other hard register provided that
1740 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
1741 @code{REGISTER_MOVE_COST} applied to their classes returns a value of 2.
1743 It is obligatory to support floating point @samp{mov@var{m}}
1744 instructions into and out of any registers that can hold fixed point
1745 values, because unions and structures (which have modes @code{SImode} or
1746 @code{DImode}) can be in those registers and they may have floating
1749 There may also be a need to support fixed point @samp{mov@var{m}}
1750 instructions in and out of floating point registers. Unfortunately, I
1751 have forgotten why this was so, and I don't know whether it is still
1752 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
1753 floating point registers, then the constraints of the fixed point
1754 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
1755 reload into a floating point register.
1757 @cindex @code{reload_in} instruction pattern
1758 @cindex @code{reload_out} instruction pattern
1759 @item @samp{reload_in@var{m}}
1760 @itemx @samp{reload_out@var{m}}
1761 Like @samp{mov@var{m}}, but used when a scratch register is required to
1762 move between operand 0 and operand 1. Operand 2 describes the scratch
1763 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
1764 macro in @pxref{Register Classes}.
1766 @cindex @code{movstrict@var{m}} instruction pattern
1767 @item @samp{movstrict@var{m}}
1768 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
1769 with mode @var{m} of a register whose natural mode is wider,
1770 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
1771 any of the register except the part which belongs to mode @var{m}.
1773 @cindex @code{load_multiple} instruction pattern
1774 @item @samp{load_multiple}
1775 Load several consecutive memory locations into consecutive registers.
1776 Operand 0 is the first of the consecutive registers, operand 1
1777 is the first memory location, and operand 2 is a constant: the
1778 number of consecutive registers.
1780 Define this only if the target machine really has such an instruction;
1781 do not define this if the most efficient way of loading consecutive
1782 registers from memory is to do them one at a time.
1784 On some machines, there are restrictions as to which consecutive
1785 registers can be stored into memory, such as particular starting or
1786 ending register numbers or only a range of valid counts. For those
1787 machines, use a @code{define_expand} (@pxref{Expander Definitions})
1788 and make the pattern fail if the restrictions are not met.
1790 Write the generated insn as a @code{parallel} with elements being a
1791 @code{set} of one register from the appropriate memory location (you may
1792 also need @code{use} or @code{clobber} elements). Use a
1793 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
1794 @file{a29k.md} and @file{rs6000.md} for examples of the use of this insn
1797 @cindex @samp{store_multiple} instruction pattern
1798 @item @samp{store_multiple}
1799 Similar to @samp{load_multiple}, but store several consecutive registers
1800 into consecutive memory locations. Operand 0 is the first of the
1801 consecutive memory locations, operand 1 is the first register, and
1802 operand 2 is a constant: the number of consecutive registers.
1804 @cindex @code{add@var{m}3} instruction pattern
1805 @item @samp{add@var{m}3}
1806 Add operand 2 and operand 1, storing the result in operand 0. All operands
1807 must have mode @var{m}. This can be used even on two-address machines, by
1808 means of constraints requiring operands 1 and 0 to be the same location.
1810 @cindex @code{sub@var{m}3} instruction pattern
1811 @cindex @code{mul@var{m}3} instruction pattern
1812 @cindex @code{div@var{m}3} instruction pattern
1813 @cindex @code{udiv@var{m}3} instruction pattern
1814 @cindex @code{mod@var{m}3} instruction pattern
1815 @cindex @code{umod@var{m}3} instruction pattern
1816 @cindex @code{smin@var{m}3} instruction pattern
1817 @cindex @code{smax@var{m}3} instruction pattern
1818 @cindex @code{umin@var{m}3} instruction pattern
1819 @cindex @code{umax@var{m}3} instruction pattern
1820 @cindex @code{and@var{m}3} instruction pattern
1821 @cindex @code{ior@var{m}3} instruction pattern
1822 @cindex @code{xor@var{m}3} instruction pattern
1823 @item @samp{sub@var{m}3}, @samp{mul@var{m}3}
1824 @itemx @samp{div@var{m}3}, @samp{udiv@var{m}3}, @samp{mod@var{m}3}, @samp{umod@var{m}3}
1825 @itemx @samp{smin@var{m}3}, @samp{smax@var{m}3}, @samp{umin@var{m}3}, @samp{umax@var{m}3}
1826 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
1827 Similar, for other arithmetic operations.
1829 @cindex @code{mulhisi3} instruction pattern
1830 @item @samp{mulhisi3}
1831 Multiply operands 1 and 2, which have mode @code{HImode}, and store
1832 a @code{SImode} product in operand 0.
1834 @cindex @code{mulqihi3} instruction pattern
1835 @cindex @code{mulsidi3} instruction pattern
1836 @item @samp{mulqihi3}, @samp{mulsidi3}
1837 Similar widening-multiplication instructions of other widths.
1839 @cindex @code{umulqihi3} instruction pattern
1840 @cindex @code{umulhisi3} instruction pattern
1841 @cindex @code{umulsidi3} instruction pattern
1842 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
1843 Similar widening-multiplication instructions that do unsigned
1846 @cindex @code{smul@var{m}3_highpart} instruction pattern
1847 @item @samp{mul@var{m}3_highpart}
1848 Perform a signed multiplication of operands 1 and 2, which have mode
1849 @var{m}, and store the most significant half of the product in operand 0.
1850 The least significant half of the product is discarded.
1852 @cindex @code{umul@var{m}3_highpart} instruction pattern
1853 @item @samp{umul@var{m}3_highpart}
1854 Similar, but the multiplication is unsigned.
1856 @cindex @code{divmod@var{m}4} instruction pattern
1857 @item @samp{divmod@var{m}4}
1858 Signed division that produces both a quotient and a remainder.
1859 Operand 1 is divided by operand 2 to produce a quotient stored
1860 in operand 0 and a remainder stored in operand 3.
1862 For machines with an instruction that produces both a quotient and a
1863 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
1864 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
1865 allows optimization in the relatively common case when both the quotient
1866 and remainder are computed.
1868 If an instruction that just produces a quotient or just a remainder
1869 exists and is more efficient than the instruction that produces both,
1870 write the output routine of @samp{divmod@var{m}4} to call
1871 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
1872 quotient or remainder and generate the appropriate instruction.
1874 @cindex @code{udivmod@var{m}4} instruction pattern
1875 @item @samp{udivmod@var{m}4}
1876 Similar, but does unsigned division.
1878 @cindex @code{ashl@var{m}3} instruction pattern
1879 @item @samp{ashl@var{m}3}
1880 Arithmetic-shift operand 1 left by a number of bits specified by operand
1881 2, and store the result in operand 0. Here @var{m} is the mode of
1882 operand 0 and operand 1; operand 2's mode is specified by the
1883 instruction pattern, and the compiler will convert the operand to that
1884 mode before generating the instruction.
1886 @cindex @code{ashr@var{m}3} instruction pattern
1887 @cindex @code{lshr@var{m}3} instruction pattern
1888 @cindex @code{rotl@var{m}3} instruction pattern
1889 @cindex @code{rotr@var{m}3} instruction pattern
1890 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
1891 Other shift and rotate instructions, analogous to the
1892 @code{ashl@var{m}3} instructions.
1894 @cindex @code{neg@var{m}2} instruction pattern
1895 @item @samp{neg@var{m}2}
1896 Negate operand 1 and store the result in operand 0.
1898 @cindex @code{abs@var{m}2} instruction pattern
1899 @item @samp{abs@var{m}2}
1900 Store the absolute value of operand 1 into operand 0.
1902 @cindex @code{sqrt@var{m}2} instruction pattern
1903 @item @samp{sqrt@var{m}2}
1904 Store the square root of operand 1 into operand 0.
1906 The @code{sqrt} built-in function of C always uses the mode which
1907 corresponds to the C data type @code{double}.
1909 @cindex @code{ffs@var{m}2} instruction pattern
1910 @item @samp{ffs@var{m}2}
1911 Store into operand 0 one plus the index of the least significant 1-bit
1912 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
1913 of operand 0; operand 1's mode is specified by the instruction
1914 pattern, and the compiler will convert the operand to that mode before
1915 generating the instruction.
1917 The @code{ffs} built-in function of C always uses the mode which
1918 corresponds to the C data type @code{int}.
1920 @cindex @code{one_cmpl@var{m}2} instruction pattern
1921 @item @samp{one_cmpl@var{m}2}
1922 Store the bitwise-complement of operand 1 into operand 0.
1924 @cindex @code{cmp@var{m}} instruction pattern
1925 @item @samp{cmp@var{m}}
1926 Compare operand 0 and operand 1, and set the condition codes.
1927 The RTL pattern should look like this:
1930 (set (cc0) (compare (match_operand:@var{m} 0 @dots{})
1931 (match_operand:@var{m} 1 @dots{})))
1934 @cindex @code{tst@var{m}} instruction pattern
1935 @item @samp{tst@var{m}}
1936 Compare operand 0 against zero, and set the condition codes.
1937 The RTL pattern should look like this:
1940 (set (cc0) (match_operand:@var{m} 0 @dots{}))
1943 @samp{tst@var{m}} patterns should not be defined for machines that do
1944 not use @code{(cc0)}. Doing so would confuse the optimizer since it
1945 would no longer be clear which @code{set} operations were comparisons.
1946 The @samp{cmp@var{m}} patterns should be used instead.
1948 @cindex @code{movstr@var{m}} instruction pattern
1949 @item @samp{movstr@var{m}}
1950 Block move instruction. The addresses of the destination and source
1951 strings are the first two operands, and both are in mode @code{Pmode}.
1952 The number of bytes to move is the third operand, in mode @var{m}.
1954 The fourth operand is the known shared alignment of the source and
1955 destination, in the form of a @code{const_int} rtx. Thus, if the
1956 compiler knows that both source and destination are word-aligned,
1957 it may provide the value 4 for this operand.
1959 These patterns need not give special consideration to the possibility
1960 that the source and destination strings might overlap.
1962 @cindex @code{clrstr@var{m}} instruction pattern
1963 @item @samp{clrstr@var{m}}
1964 Block clear instruction. The addresses of the destination string is the
1965 first operand, in mode @code{Pmode}. The number of bytes to clear is
1966 the second operand, in mode @var{m}.
1968 The third operand is the known alignment of the destination, in the form
1969 of a @code{const_int} rtx. Thus, if the compiler knows that the
1970 destination is word-aligned, it may provide the value 4 for this
1973 @cindex @code{cmpstr@var{m}} instruction pattern
1974 @item @samp{cmpstr@var{m}}
1975 Block compare instruction, with five operands. Operand 0 is the output;
1976 it has mode @var{m}. The remaining four operands are like the operands
1977 of @samp{movstr@var{m}}. The two memory blocks specified are compared
1978 byte by byte in lexicographic order. The effect of the instruction is
1979 to store a value in operand 0 whose sign indicates the result of the
1982 @cindex @code{strlen@var{m}} instruction pattern
1983 @item @samp{strlen@var{m}}
1984 Compute the length of a string, with three operands.
1985 Operand 0 is the result (of mode @var{m}), operand 1 is
1986 a @code{mem} referring to the first character of the string,
1987 operand 2 is the character to search for (normally zero),
1988 and operand 3 is a constant describing the known alignment
1989 of the beginning of the string.
1991 @cindex @code{float@var{mn}2} instruction pattern
1992 @item @samp{float@var{m}@var{n}2}
1993 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
1994 floating point mode @var{n} and store in operand 0 (which has mode
1997 @cindex @code{floatuns@var{mn}2} instruction pattern
1998 @item @samp{floatuns@var{m}@var{n}2}
1999 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
2000 to floating point mode @var{n} and store in operand 0 (which has mode
2003 @cindex @code{fix@var{mn}2} instruction pattern
2004 @item @samp{fix@var{m}@var{n}2}
2005 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2006 point mode @var{n} as a signed number and store in operand 0 (which
2007 has mode @var{n}). This instruction's result is defined only when
2008 the value of operand 1 is an integer.
2010 @cindex @code{fixuns@var{mn}2} instruction pattern
2011 @item @samp{fixuns@var{m}@var{n}2}
2012 Convert operand 1 (valid for floating point mode @var{m}) to fixed
2013 point mode @var{n} as an unsigned number and store in operand 0 (which
2014 has mode @var{n}). This instruction's result is defined only when the
2015 value of operand 1 is an integer.
2017 @cindex @code{ftrunc@var{m}2} instruction pattern
2018 @item @samp{ftrunc@var{m}2}
2019 Convert operand 1 (valid for floating point mode @var{m}) to an
2020 integer value, still represented in floating point mode @var{m}, and
2021 store it in operand 0 (valid for floating point mode @var{m}).
2023 @cindex @code{fix_trunc@var{mn}2} instruction pattern
2024 @item @samp{fix_trunc@var{m}@var{n}2}
2025 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
2026 of mode @var{m} by converting the value to an integer.
2028 @cindex @code{fixuns_trunc@var{mn}2} instruction pattern
2029 @item @samp{fixuns_trunc@var{m}@var{n}2}
2030 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
2031 value of mode @var{m} by converting the value to an integer.
2033 @cindex @code{trunc@var{mn}2} instruction pattern
2034 @item @samp{trunc@var{m}@var{n}2}
2035 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
2036 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2037 point or both floating point.
2039 @cindex @code{extend@var{mn}2} instruction pattern
2040 @item @samp{extend@var{m}@var{n}2}
2041 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2042 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2043 point or both floating point.
2045 @cindex @code{zero_extend@var{mn}2} instruction pattern
2046 @item @samp{zero_extend@var{m}@var{n}2}
2047 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
2048 store in operand 0 (which has mode @var{n}). Both modes must be fixed
2051 @cindex @code{extv} instruction pattern
2053 Extract a bit field from operand 1 (a register or memory operand), where
2054 operand 2 specifies the width in bits and operand 3 the starting bit,
2055 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
2056 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
2057 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
2058 be valid for @code{word_mode}.
2060 The RTL generation pass generates this instruction only with constants
2061 for operands 2 and 3.
2063 The bit-field value is sign-extended to a full word integer
2064 before it is stored in operand 0.
2066 @cindex @code{extzv} instruction pattern
2068 Like @samp{extv} except that the bit-field value is zero-extended.
2070 @cindex @code{insv} instruction pattern
2072 Store operand 3 (which must be valid for @code{word_mode}) into a bit
2073 field in operand 0, where operand 1 specifies the width in bits and
2074 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
2075 @code{word_mode}; often @code{word_mode} is allowed only for registers.
2076 Operands 1 and 2 must be valid for @code{word_mode}.
2078 The RTL generation pass generates this instruction only with constants
2079 for operands 1 and 2.
2081 @cindex @code{mov@var{mode}cc} instruction pattern
2082 @item @samp{mov@var{mode}cc}
2083 Conditionally move operand 2 or operand 3 into operand 0 according to the
2084 comparison in operand 1. If the comparison is true, operand 2 is moved
2085 into operand 0, otherwise operand 3 is moved.
2087 The mode of the operands being compared need not be the same as the operands
2088 being moved. Some machines, sparc64 for example, have instructions that
2089 conditionally move an integer value based on the floating point condition
2090 codes and vice versa.
2092 If the machine does not have conditional move instructions, do not
2093 define these patterns.
2095 @cindex @code{s@var{cond}} instruction pattern
2096 @item @samp{s@var{cond}}
2097 Store zero or nonzero in the operand according to the condition codes.
2098 Value stored is nonzero iff the condition @var{cond} is true.
2099 @var{cond} is the name of a comparison operation expression code, such
2100 as @code{eq}, @code{lt} or @code{leu}.
2102 You specify the mode that the operand must have when you write the
2103 @code{match_operand} expression. The compiler automatically sees
2104 which mode you have used and supplies an operand of that mode.
2106 The value stored for a true condition must have 1 as its low bit, or
2107 else must be negative. Otherwise the instruction is not suitable and
2108 you should omit it from the machine description. You describe to the
2109 compiler exactly which value is stored by defining the macro
2110 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
2111 found that can be used for all the @samp{s@var{cond}} patterns, you
2112 should omit those operations from the machine description.
2114 These operations may fail, but should do so only in relatively
2115 uncommon cases; if they would fail for common cases involving
2116 integer comparisons, it is best to omit these patterns.
2118 If these operations are omitted, the compiler will usually generate code
2119 that copies the constant one to the target and branches around an
2120 assignment of zero to the target. If this code is more efficient than
2121 the potential instructions used for the @samp{s@var{cond}} pattern
2122 followed by those required to convert the result into a 1 or a zero in
2123 @code{SImode}, you should omit the @samp{s@var{cond}} operations from
2124 the machine description.
2126 @cindex @code{b@var{cond}} instruction pattern
2127 @item @samp{b@var{cond}}
2128 Conditional branch instruction. Operand 0 is a @code{label_ref} that
2129 refers to the label to jump to. Jump if the condition codes meet
2130 condition @var{cond}.
2132 Some machines do not follow the model assumed here where a comparison
2133 instruction is followed by a conditional branch instruction. In that
2134 case, the @samp{cmp@var{m}} (and @samp{tst@var{m}}) patterns should
2135 simply store the operands away and generate all the required insns in a
2136 @code{define_expand} (@pxref{Expander Definitions}) for the conditional
2137 branch operations. All calls to expand @samp{b@var{cond}} patterns are
2138 immediately preceded by calls to expand either a @samp{cmp@var{m}}
2139 pattern or a @samp{tst@var{m}} pattern.
2141 Machines that use a pseudo register for the condition code value, or
2142 where the mode used for the comparison depends on the condition being
2143 tested, should also use the above mechanism. @xref{Jump Patterns}
2145 The above discussion also applies to the @samp{mov@var{mode}cc} and
2146 @samp{s@var{cond}} patterns.
2148 @cindex @code{call} instruction pattern
2150 Subroutine call instruction returning no value. Operand 0 is the
2151 function to call; operand 1 is the number of bytes of arguments pushed
2152 (in mode @code{SImode}, except it is normally a @code{const_int});
2153 operand 2 is the number of registers used as operands.
2155 On most machines, operand 2 is not actually stored into the RTL
2156 pattern. It is supplied for the sake of some RISC machines which need
2157 to put this information into the assembler code; they can put it in
2158 the RTL instead of operand 1.
2160 Operand 0 should be a @code{mem} RTX whose address is the address of the
2161 function. Note, however, that this address can be a @code{symbol_ref}
2162 expression even if it would not be a legitimate memory address on the
2163 target machine. If it is also not a valid argument for a call
2164 instruction, the pattern for this operation should be a
2165 @code{define_expand} (@pxref{Expander Definitions}) that places the
2166 address into a register and uses that register in the call instruction.
2168 @cindex @code{call_value} instruction pattern
2169 @item @samp{call_value}
2170 Subroutine call instruction returning a value. Operand 0 is the hard
2171 register in which the value is returned. There are three more
2172 operands, the same as the three operands of the @samp{call}
2173 instruction (but with numbers increased by one).
2175 Subroutines that return @code{BLKmode} objects use the @samp{call}
2178 @cindex @code{call_pop} instruction pattern
2179 @cindex @code{call_value_pop} instruction pattern
2180 @item @samp{call_pop}, @samp{call_value_pop}
2181 Similar to @samp{call} and @samp{call_value}, except used if defined and
2182 if @code{RETURN_POPS_ARGS} is non-zero. They should emit a @code{parallel}
2183 that contains both the function call and a @code{set} to indicate the
2184 adjustment made to the frame pointer.
2186 For machines where @code{RETURN_POPS_ARGS} can be non-zero, the use of these
2187 patterns increases the number of functions for which the frame pointer
2188 can be eliminated, if desired.
2190 @cindex @code{untyped_call} instruction pattern
2191 @item @samp{untyped_call}
2192 Subroutine call instruction returning a value of any type. Operand 0 is
2193 the function to call; operand 1 is a memory location where the result of
2194 calling the function is to be stored; operand 2 is a @code{parallel}
2195 expression where each element is a @code{set} expression that indicates
2196 the saving of a function return value into the result block.
2198 This instruction pattern should be defined to support
2199 @code{__builtin_apply} on machines where special instructions are needed
2200 to call a subroutine with arbitrary arguments or to save the value
2201 returned. This instruction pattern is required on machines that have
2202 multiple registers that can hold a return value (i.e.
2203 @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
2205 @cindex @code{return} instruction pattern
2207 Subroutine return instruction. This instruction pattern name should be
2208 defined only if a single instruction can do all the work of returning
2211 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
2212 RTL generation phase. In this case it is to support machines where
2213 multiple instructions are usually needed to return from a function, but
2214 some class of functions only requires one instruction to implement a
2215 return. Normally, the applicable functions are those which do not need
2216 to save any registers or allocate stack space.
2218 @findex reload_completed
2219 @findex leaf_function_p
2220 For such machines, the condition specified in this pattern should only
2221 be true when @code{reload_completed} is non-zero and the function's
2222 epilogue would only be a single instruction. For machines with register
2223 windows, the routine @code{leaf_function_p} may be used to determine if
2224 a register window push is required.
2226 Machines that have conditional return instructions should define patterns
2232 (if_then_else (match_operator
2233 0 "comparison_operator"
2234 [(cc0) (const_int 0)])
2241 where @var{condition} would normally be the same condition specified on the
2242 named @samp{return} pattern.
2244 @cindex @code{untyped_return} instruction pattern
2245 @item @samp{untyped_return}
2246 Untyped subroutine return instruction. This instruction pattern should
2247 be defined to support @code{__builtin_return} on machines where special
2248 instructions are needed to return a value of any type.
2250 Operand 0 is a memory location where the result of calling a function
2251 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
2252 expression where each element is a @code{set} expression that indicates
2253 the restoring of a function return value from the result block.
2255 @cindex @code{nop} instruction pattern
2257 No-op instruction. This instruction pattern name should always be defined
2258 to output a no-op in assembler code. @code{(const_int 0)} will do as an
2261 @cindex @code{indirect_jump} instruction pattern
2262 @item @samp{indirect_jump}
2263 An instruction to jump to an address which is operand zero.
2264 This pattern name is mandatory on all machines.
2266 @cindex @code{casesi} instruction pattern
2268 Instruction to jump through a dispatch table, including bounds checking.
2269 This instruction takes five operands:
2273 The index to dispatch on, which has mode @code{SImode}.
2276 The lower bound for indices in the table, an integer constant.
2279 The total range of indices in the table---the largest index
2280 minus the smallest one (both inclusive).
2283 A label that precedes the table itself.
2286 A label to jump to if the index has a value outside the bounds.
2287 (If the machine-description macro @code{CASE_DROPS_THROUGH} is defined,
2288 then an out-of-bounds index drops through to the code following
2289 the jump table instead of jumping to this label. In that case,
2290 this label is not actually used by the @samp{casesi} instruction,
2291 but it is always provided as an operand.)
2294 The table is a @code{addr_vec} or @code{addr_diff_vec} inside of a
2295 @code{jump_insn}. The number of elements in the table is one plus the
2296 difference between the upper bound and the lower bound.
2298 @cindex @code{tablejump} instruction pattern
2299 @item @samp{tablejump}
2300 Instruction to jump to a variable address. This is a low-level
2301 capability which can be used to implement a dispatch table when there
2302 is no @samp{casesi} pattern.
2304 This pattern requires two operands: the address or offset, and a label
2305 which should immediately precede the jump table. If the macro
2306 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
2307 operand is an offset which counts from the address of the table; otherwise,
2308 it is an absolute address to jump to. In either case, the first operand has
2311 The @samp{tablejump} insn is always the last insn before the jump
2312 table it uses. Its assembler code normally has no need to use the
2313 second operand, but you should incorporate it in the RTL pattern so
2314 that the jump optimizer will not delete the table as unreachable code.
2316 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
2317 @item @samp{canonicalize_funcptr_for_compare}
2318 Canonicalize the function pointer in operand 1 and store the result
2321 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
2322 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
2323 and also has mode @code{Pmode}.
2325 Canonicalization of a function pointer usually involves computing
2326 the address of the function which would be called if the function
2327 pointer were used in an indirect call.
2329 Only define this pattern if function pointers on the target machine
2330 can have different values but still call the same function when
2331 used in an indirect call.
2333 @cindex @code{save_stack_block} instruction pattern
2334 @cindex @code{save_stack_function} instruction pattern
2335 @cindex @code{save_stack_nonlocal} instruction pattern
2336 @cindex @code{restore_stack_block} instruction pattern
2337 @cindex @code{restore_stack_function} instruction pattern
2338 @cindex @code{restore_stack_nonlocal} instruction pattern
2339 @item @samp{save_stack_block}
2340 @itemx @samp{save_stack_function}
2341 @itemx @samp{save_stack_nonlocal}
2342 @itemx @samp{restore_stack_block}
2343 @itemx @samp{restore_stack_function}
2344 @itemx @samp{restore_stack_nonlocal}
2345 Most machines save and restore the stack pointer by copying it to or
2346 from an object of mode @code{Pmode}. Do not define these patterns on
2349 Some machines require special handling for stack pointer saves and
2350 restores. On those machines, define the patterns corresponding to the
2351 non-standard cases by using a @code{define_expand} (@pxref{Expander
2352 Definitions}) that produces the required insns. The three types of
2353 saves and restores are:
2357 @samp{save_stack_block} saves the stack pointer at the start of a block
2358 that allocates a variable-sized object, and @samp{restore_stack_block}
2359 restores the stack pointer when the block is exited.
2362 @samp{save_stack_function} and @samp{restore_stack_function} do a
2363 similar job for the outermost block of a function and are used when the
2364 function allocates variable-sized objects or calls @code{alloca}. Only
2365 the epilogue uses the restored stack pointer, allowing a simpler save or
2366 restore sequence on some machines.
2369 @samp{save_stack_nonlocal} is used in functions that contain labels
2370 branched to by nested functions. It saves the stack pointer in such a
2371 way that the inner function can use @samp{restore_stack_nonlocal} to
2372 restore the stack pointer. The compiler generates code to restore the
2373 frame and argument pointer registers, but some machines require saving
2374 and restoring additional data such as register window information or
2375 stack backchains. Place insns in these patterns to save and restore any
2379 When saving the stack pointer, operand 0 is the save area and operand 1
2380 is the stack pointer. The mode used to allocate the save area is the
2381 mode of operand 0. You must specify an integral mode, or
2382 @code{VOIDmode} if no save area is needed for a particular type of save
2383 (either because no save is needed or because a machine-specific save
2384 area can be used). Operand 0 is the stack pointer and operand 1 is the
2385 save area for restore operations. If @samp{save_stack_block} is
2386 defined, operand 0 must not be @code{VOIDmode} since these saves can be
2389 A save area is a @code{mem} that is at a constant offset from
2390 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
2391 nonlocal gotos and a @code{reg} in the other two cases.
2393 @cindex @code{allocate_stack} instruction pattern
2394 @item @samp{allocate_stack}
2395 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
2396 the stack pointer to create space for dynamically allocated data.
2398 Store the resultant pointer to this space into operand 0. If you
2399 are allocating space from the main stack, do this by emitting a
2400 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
2401 If you are allocating the space elsewhere, generate code to copy the
2402 location of the space to operand 0. In the latter case, you must
2403 ensure this space gets freed when the corresponding space on the main
2406 Do not define this pattern if all that must be done is the subtraction.
2407 Some machines require other operations such as stack probes or
2408 maintaining the back chain. Define this pattern to emit those
2409 operations in addition to updating the stack pointer.
2411 @cindex @code{probe} instruction pattern
2413 Some machines require instructions to be executed after space is
2414 allocated from the stack, for example to generate a reference at
2415 the bottom of the stack.
2417 If you need to emit instructions before the stack has been adjusted,
2418 put them into the @samp{allocate_stack} pattern. Otherwise, define
2419 this pattern to emit the required instructions.
2421 No operands are provided.
2423 @cindex @code{check_stack} instruction pattern
2424 @item @samp{check_stack}
2425 If stack checking cannot be done on your system by probing the stack with
2426 a load or store instruction (@pxref{Stack Checking}), define this pattern
2427 to perform the needed check and signaling an error if the stack
2428 has overflowed. The single operand is the location in the stack furthest
2429 from the current stack pointer that you need to validate. Normally,
2430 on machines where this pattern is needed, you would obtain the stack
2431 limit from a global or thread-specific variable or register.
2433 @cindex @code{nonlocal_goto} instruction pattern
2434 @item @samp{nonlocal_goto}
2435 Emit code to generate a non-local goto, e.g., a jump from one function
2436 to a label in an outer function. This pattern has four arguments,
2437 each representing a value to be used in the jump. The first
2438 argument is to be loadedd into the frame pointer, the second is
2439 the address to branch to (code to dispatch to the actual label),
2440 the third is the address of a location where the stack is saved,
2441 and the last is the address of the label, to be placed in the
2442 location for the incoming static chain.
2444 On most machines you need not define this pattern, since GNU CC will
2445 already generate the correct code, which is to load the frame pointer
2446 and static chain, restore the stack (using the
2447 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
2448 to the dispatcher. You need only define this pattern if this code will
2449 not work on your machine.
2451 @cindex @code{nonlocal_goto_receiver} instruction pattern
2452 @item @samp{nonlocal_goto_receiver}
2453 This pattern, if defined, contains code needed at the target of a
2454 nonlocal goto after the code already generated by GNU CC. You will not
2455 normally need to define this pattern. A typical reason why you might
2456 need this pattern is if some value, such as a pointer to a global table,
2457 must be restored when the frame pointer is restored. There are no
2460 @cindex @code{exception_receiver} instruction pattern
2461 @item @samp{exception_receiver}
2462 This pattern, if defined, contains code needed at the site of an
2463 exception handler that isn't needed at the site of a nonlocal goto. You
2464 will not normally need to define this pattern. A typical reason why you
2465 might need this pattern is if some value, such as a pointer to a global
2466 table, must be restored after control flow is branched to the handler of
2467 an exception. There are no arguments.
2470 @node Pattern Ordering
2471 @section When the Order of Patterns Matters
2472 @cindex Pattern Ordering
2473 @cindex Ordering of Patterns
2475 Sometimes an insn can match more than one instruction pattern. Then the
2476 pattern that appears first in the machine description is the one used.
2477 Therefore, more specific patterns (patterns that will match fewer things)
2478 and faster instructions (those that will produce better code when they
2479 do match) should usually go first in the description.
2481 In some cases the effect of ordering the patterns can be used to hide
2482 a pattern when it is not valid. For example, the 68000 has an
2483 instruction for converting a fullword to floating point and another
2484 for converting a byte to floating point. An instruction converting
2485 an integer to floating point could match either one. We put the
2486 pattern to convert the fullword first to make sure that one will
2487 be used rather than the other. (Otherwise a large integer might
2488 be generated as a single-byte immediate quantity, which would not work.)
2489 Instead of using this pattern ordering it would be possible to make the
2490 pattern for convert-a-byte smart enough to deal properly with any
2493 @node Dependent Patterns
2494 @section Interdependence of Patterns
2495 @cindex Dependent Patterns
2496 @cindex Interdependence of Patterns
2498 Every machine description must have a named pattern for each of the
2499 conditional branch names @samp{b@var{cond}}. The recognition template
2500 must always have the form
2504 (if_then_else (@var{cond} (cc0) (const_int 0))
2505 (label_ref (match_operand 0 "" ""))
2510 In addition, every machine description must have an anonymous pattern
2511 for each of the possible reverse-conditional branches. Their templates
2516 (if_then_else (@var{cond} (cc0) (const_int 0))
2518 (label_ref (match_operand 0 "" ""))))
2522 They are necessary because jump optimization can turn direct-conditional
2523 branches into reverse-conditional branches.
2525 It is often convenient to use the @code{match_operator} construct to
2526 reduce the number of patterns that must be specified for branches. For
2532 (if_then_else (match_operator 0 "comparison_operator"
2533 [(cc0) (const_int 0)])
2535 (label_ref (match_operand 1 "" ""))))]
2540 In some cases machines support instructions identical except for the
2541 machine mode of one or more operands. For example, there may be
2542 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
2546 (set (match_operand:SI 0 @dots{})
2547 (extend:SI (match_operand:HI 1 @dots{})))
2549 (set (match_operand:SI 0 @dots{})
2550 (extend:SI (match_operand:QI 1 @dots{})))
2554 Constant integers do not specify a machine mode, so an instruction to
2555 extend a constant value could match either pattern. The pattern it
2556 actually will match is the one that appears first in the file. For correct
2557 results, this must be the one for the widest possible mode (@code{HImode},
2558 here). If the pattern matches the @code{QImode} instruction, the results
2559 will be incorrect if the constant value does not actually fit that mode.
2561 Such instructions to extend constants are rarely generated because they are
2562 optimized away, but they do occasionally happen in nonoptimized
2565 If a constraint in a pattern allows a constant, the reload pass may
2566 replace a register with a constant permitted by the constraint in some
2567 cases. Similarly for memory references. Because of this substitution,
2568 you should not provide separate patterns for increment and decrement
2569 instructions. Instead, they should be generated from the same pattern
2570 that supports register-register add insns by examining the operands and
2571 generating the appropriate machine instruction.
2574 @section Defining Jump Instruction Patterns
2575 @cindex jump instruction patterns
2576 @cindex defining jump instruction patterns
2578 For most machines, GNU CC assumes that the machine has a condition code.
2579 A comparison insn sets the condition code, recording the results of both
2580 signed and unsigned comparison of the given operands. A separate branch
2581 insn tests the condition code and branches or not according its value.
2582 The branch insns come in distinct signed and unsigned flavors. Many
2583 common machines, such as the Vax, the 68000 and the 32000, work this
2586 Some machines have distinct signed and unsigned compare instructions, and
2587 only one set of conditional branch instructions. The easiest way to handle
2588 these machines is to treat them just like the others until the final stage
2589 where assembly code is written. At this time, when outputting code for the
2590 compare instruction, peek ahead at the following branch using
2591 @code{next_cc0_user (insn)}. (The variable @code{insn} refers to the insn
2592 being output, in the output-writing code in an instruction pattern.) If
2593 the RTL says that is an unsigned branch, output an unsigned compare;
2594 otherwise output a signed compare. When the branch itself is output, you
2595 can treat signed and unsigned branches identically.
2597 The reason you can do this is that GNU CC always generates a pair of
2598 consecutive RTL insns, possibly separated by @code{note} insns, one to
2599 set the condition code and one to test it, and keeps the pair inviolate
2602 To go with this technique, you must define the machine-description macro
2603 @code{NOTICE_UPDATE_CC} to do @code{CC_STATUS_INIT}; in other words, no
2604 compare instruction is superfluous.
2606 Some machines have compare-and-branch instructions and no condition code.
2607 A similar technique works for them. When it is time to ``output'' a
2608 compare instruction, record its operands in two static variables. When
2609 outputting the branch-on-condition-code instruction that follows, actually
2610 output a compare-and-branch instruction that uses the remembered operands.
2612 It also works to define patterns for compare-and-branch instructions.
2613 In optimizing compilation, the pair of compare and branch instructions
2614 will be combined according to these patterns. But this does not happen
2615 if optimization is not requested. So you must use one of the solutions
2616 above in addition to any special patterns you define.
2618 In many RISC machines, most instructions do not affect the condition
2619 code and there may not even be a separate condition code register. On
2620 these machines, the restriction that the definition and use of the
2621 condition code be adjacent insns is not necessary and can prevent
2622 important optimizations. For example, on the IBM RS/6000, there is a
2623 delay for taken branches unless the condition code register is set three
2624 instructions earlier than the conditional branch. The instruction
2625 scheduler cannot perform this optimization if it is not permitted to
2626 separate the definition and use of the condition code register.
2628 On these machines, do not use @code{(cc0)}, but instead use a register
2629 to represent the condition code. If there is a specific condition code
2630 register in the machine, use a hard register. If the condition code or
2631 comparison result can be placed in any general register, or if there are
2632 multiple condition registers, use a pseudo register.
2634 @findex prev_cc0_setter
2635 @findex next_cc0_user
2636 On some machines, the type of branch instruction generated may depend on
2637 the way the condition code was produced; for example, on the 68k and
2638 Sparc, setting the condition code directly from an add or subtract
2639 instruction does not clear the overflow bit the way that a test
2640 instruction does, so a different branch instruction must be used for
2641 some conditional branches. For machines that use @code{(cc0)}, the set
2642 and use of the condition code must be adjacent (separated only by
2643 @code{note} insns) allowing flags in @code{cc_status} to be used.
2644 (@xref{Condition Code}.) Also, the comparison and branch insns can be
2645 located from each other by using the functions @code{prev_cc0_setter}
2646 and @code{next_cc0_user}.
2648 However, this is not true on machines that do not use @code{(cc0)}. On
2649 those machines, no assumptions can be made about the adjacency of the
2650 compare and branch insns and the above methods cannot be used. Instead,
2651 we use the machine mode of the condition code register to record
2652 different formats of the condition code register.
2654 Registers used to store the condition code value should have a mode that
2655 is in class @code{MODE_CC}. Normally, it will be @code{CCmode}. If
2656 additional modes are required (as for the add example mentioned above in
2657 the Sparc), define the macro @code{EXTRA_CC_MODES} to list the
2658 additional modes required (@pxref{Condition Code}). Also define
2659 @code{EXTRA_CC_NAMES} to list the names of those modes and
2660 @code{SELECT_CC_MODE} to choose a mode given an operand of a compare.
2662 If it is known during RTL generation that a different mode will be
2663 required (for example, if the machine has separate compare instructions
2664 for signed and unsigned quantities, like most IBM processors), they can
2665 be specified at that time.
2667 If the cases that require different modes would be made by instruction
2668 combination, the macro @code{SELECT_CC_MODE} determines which machine
2669 mode should be used for the comparison result. The patterns should be
2670 written using that mode. To support the case of the add on the Sparc
2671 discussed above, we have the pattern
2675 [(set (reg:CC_NOOV 0)
2677 (plus:SI (match_operand:SI 0 "register_operand" "%r")
2678 (match_operand:SI 1 "arith_operand" "rI"))
2684 The @code{SELECT_CC_MODE} macro on the Sparc returns @code{CC_NOOVmode}
2685 for comparisons whose argument is a @code{plus}.
2687 @node Insn Canonicalizations
2688 @section Canonicalization of Instructions
2689 @cindex canonicalization of instructions
2690 @cindex insn canonicalization
2692 There are often cases where multiple RTL expressions could represent an
2693 operation performed by a single machine instruction. This situation is
2694 most commonly encountered with logical, branch, and multiply-accumulate
2695 instructions. In such cases, the compiler attempts to convert these
2696 multiple RTL expressions into a single canonical form to reduce the
2697 number of insn patterns required.
2699 In addition to algebraic simplifications, following canonicalizations
2704 For commutative and comparison operators, a constant is always made the
2705 second operand. If a machine only supports a constant as the second
2706 operand, only patterns that match a constant in the second operand need
2709 @cindex @code{neg}, canonicalization of
2710 @cindex @code{not}, canonicalization of
2711 @cindex @code{mult}, canonicalization of
2712 @cindex @code{plus}, canonicalization of
2713 @cindex @code{minus}, canonicalization of
2714 For these operators, if only one operand is a @code{neg}, @code{not},
2715 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
2718 @cindex @code{compare}, canonicalization of
2720 For the @code{compare} operator, a constant is always the second operand
2721 on machines where @code{cc0} is used (@pxref{Jump Patterns}). On other
2722 machines, there are rare cases where the compiler might want to construct
2723 a @code{compare} with a constant as the first operand. However, these
2724 cases are not common enough for it to be worthwhile to provide a pattern
2725 matching a constant as the first operand unless the machine actually has
2726 such an instruction.
2728 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
2729 @code{minus} is made the first operand under the same conditions as
2733 @code{(minus @var{x} (const_int @var{n}))} is converted to
2734 @code{(plus @var{x} (const_int @var{-n}))}.
2737 Within address computations (i.e., inside @code{mem}), a left shift is
2738 converted into the appropriate multiplication by a power of two.
2740 @cindex @code{ior}, canonicalization of
2741 @cindex @code{and}, canonicalization of
2742 @cindex De Morgan's law
2744 De`Morgan's Law is used to move bitwise negation inside a bitwise
2745 logical-and or logical-or operation. If this results in only one
2746 operand being a @code{not} expression, it will be the first one.
2748 A machine that has an instruction that performs a bitwise logical-and of one
2749 operand with the bitwise negation of the other should specify the pattern
2750 for that instruction as
2754 [(set (match_operand:@var{m} 0 @dots{})
2755 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
2756 (match_operand:@var{m} 2 @dots{})))]
2762 Similarly, a pattern for a ``NAND'' instruction should be written
2766 [(set (match_operand:@var{m} 0 @dots{})
2767 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
2768 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
2773 In both cases, it is not necessary to include patterns for the many
2774 logically equivalent RTL expressions.
2776 @cindex @code{xor}, canonicalization of
2778 The only possible RTL expressions involving both bitwise exclusive-or
2779 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
2780 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.@refill
2783 The sum of three items, one of which is a constant, will only appear in
2787 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
2791 On machines that do not use @code{cc0},
2792 @code{(compare @var{x} (const_int 0))} will be converted to
2795 @cindex @code{zero_extract}, canonicalization of
2796 @cindex @code{sign_extract}, canonicalization of
2798 Equality comparisons of a group of bits (usually a single bit) with zero
2799 will be written using @code{zero_extract} rather than the equivalent
2800 @code{and} or @code{sign_extract} operations.
2804 @node Peephole Definitions
2805 @section Machine-Specific Peephole Optimizers
2806 @cindex peephole optimizer definitions
2807 @cindex defining peephole optimizers
2809 In addition to instruction patterns the @file{md} file may contain
2810 definitions of machine-specific peephole optimizations.
2812 The combiner does not notice certain peephole optimizations when the data
2813 flow in the program does not suggest that it should try them. For example,
2814 sometimes two consecutive insns related in purpose can be combined even
2815 though the second one does not appear to use a register computed in the
2816 first one. A machine-specific peephole optimizer can detect such
2820 A definition looks like this:
2824 [@var{insn-pattern-1}
2825 @var{insn-pattern-2}
2829 "@var{optional insn-attributes}")
2833 The last string operand may be omitted if you are not using any
2834 machine-specific information in this machine description. If present,
2835 it must obey the same rules as in a @code{define_insn}.
2837 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
2838 consecutive insns. The optimization applies to a sequence of insns when
2839 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
2840 the next, and so on.@refill
2842 Each of the insns matched by a peephole must also match a
2843 @code{define_insn}. Peepholes are checked only at the last stage just
2844 before code generation, and only optionally. Therefore, any insn which
2845 would match a peephole but no @code{define_insn} will cause a crash in code
2846 generation in an unoptimized compilation, or at various optimization
2849 The operands of the insns are matched with @code{match_operands},
2850 @code{match_operator}, and @code{match_dup}, as usual. What is not
2851 usual is that the operand numbers apply to all the insn patterns in the
2852 definition. So, you can check for identical operands in two insns by
2853 using @code{match_operand} in one insn and @code{match_dup} in the
2856 The operand constraints used in @code{match_operand} patterns do not have
2857 any direct effect on the applicability of the peephole, but they will
2858 be validated afterward, so make sure your constraints are general enough
2859 to apply whenever the peephole matches. If the peephole matches
2860 but the constraints are not satisfied, the compiler will crash.
2862 It is safe to omit constraints in all the operands of the peephole; or
2863 you can write constraints which serve as a double-check on the criteria
2866 Once a sequence of insns matches the patterns, the @var{condition} is
2867 checked. This is a C expression which makes the final decision whether to
2868 perform the optimization (we do so if the expression is nonzero). If
2869 @var{condition} is omitted (in other words, the string is empty) then the
2870 optimization is applied to every sequence of insns that matches the
2873 The defined peephole optimizations are applied after register allocation
2874 is complete. Therefore, the peephole definition can check which
2875 operands have ended up in which kinds of registers, just by looking at
2878 @findex prev_active_insn
2879 The way to refer to the operands in @var{condition} is to write
2880 @code{operands[@var{i}]} for operand number @var{i} (as matched by
2881 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
2882 to refer to the last of the insns being matched; use
2883 @code{prev_active_insn} to find the preceding insns.
2885 @findex dead_or_set_p
2886 When optimizing computations with intermediate results, you can use
2887 @var{condition} to match only when the intermediate results are not used
2888 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
2889 @var{op})}, where @var{insn} is the insn in which you expect the value
2890 to be used for the last time (from the value of @code{insn}, together
2891 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
2892 value (from @code{operands[@var{i}]}).@refill
2894 Applying the optimization means replacing the sequence of insns with one
2895 new insn. The @var{template} controls ultimate output of assembler code
2896 for this combined insn. It works exactly like the template of a
2897 @code{define_insn}. Operand numbers in this template are the same ones
2898 used in matching the original sequence of insns.
2900 The result of a defined peephole optimizer does not need to match any of
2901 the insn patterns in the machine description; it does not even have an
2902 opportunity to match them. The peephole optimizer definition itself serves
2903 as the insn pattern to control how the insn is output.
2905 Defined peephole optimizers are run as assembler code is being output,
2906 so the insns they produce are never combined or rearranged in any way.
2908 Here is an example, taken from the 68000 machine description:
2912 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
2913 (set (match_operand:DF 0 "register_operand" "=f")
2914 (match_operand:DF 1 "register_operand" "ad"))]
2915 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
2919 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
2921 output_asm_insn (\"move.l %1,(sp)\", xoperands);
2922 output_asm_insn (\"move.l %1,-(sp)\", operands);
2923 return \"fmove.d (sp)+,%0\";
2925 output_asm_insn (\"movel %1,sp@@\", xoperands);
2926 output_asm_insn (\"movel %1,sp@@-\", operands);
2927 return \"fmoved sp@@+,%0\";
2934 The effect of this optimization is to change
2960 If a peephole matches a sequence including one or more jump insns, you must
2961 take account of the flags such as @code{CC_REVERSED} which specify that the
2962 condition codes are represented in an unusual manner. The compiler
2963 automatically alters any ordinary conditional jumps which occur in such
2964 situations, but the compiler cannot alter jumps which have been replaced by
2965 peephole optimizations. So it is up to you to alter the assembler code
2966 that the peephole produces. Supply C code to write the assembler output,
2967 and in this C code check the condition code status flags and change the
2968 assembler code as appropriate.
2971 @var{insn-pattern-1} and so on look @emph{almost} like the second
2972 operand of @code{define_insn}. There is one important difference: the
2973 second operand of @code{define_insn} consists of one or more RTX's
2974 enclosed in square brackets. Usually, there is only one: then the same
2975 action can be written as an element of a @code{define_peephole}. But
2976 when there are multiple actions in a @code{define_insn}, they are
2977 implicitly enclosed in a @code{parallel}. Then you must explicitly
2978 write the @code{parallel}, and the square brackets within it, in the
2979 @code{define_peephole}. Thus, if an insn pattern looks like this,
2982 (define_insn "divmodsi4"
2983 [(set (match_operand:SI 0 "general_operand" "=d")
2984 (div:SI (match_operand:SI 1 "general_operand" "0")
2985 (match_operand:SI 2 "general_operand" "dmsK")))
2986 (set (match_operand:SI 3 "general_operand" "=d")
2987 (mod:SI (match_dup 1) (match_dup 2)))]
2989 "divsl%.l %2,%3:%0")
2993 then the way to mention this insn in a peephole is as follows:
2999 [(set (match_operand:SI 0 "general_operand" "=d")
3000 (div:SI (match_operand:SI 1 "general_operand" "0")
3001 (match_operand:SI 2 "general_operand" "dmsK")))
3002 (set (match_operand:SI 3 "general_operand" "=d")
3003 (mod:SI (match_dup 1) (match_dup 2)))])
3008 @node Expander Definitions
3009 @section Defining RTL Sequences for Code Generation
3010 @cindex expander definitions
3011 @cindex code generation RTL sequences
3012 @cindex defining RTL sequences for code generation
3014 On some target machines, some standard pattern names for RTL generation
3015 cannot be handled with single insn, but a sequence of RTL insns can
3016 represent them. For these target machines, you can write a
3017 @code{define_expand} to specify how to generate the sequence of RTL.
3019 @findex define_expand
3020 A @code{define_expand} is an RTL expression that looks almost like a
3021 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
3022 only for RTL generation and it can produce more than one RTL insn.
3024 A @code{define_expand} RTX has four operands:
3028 The name. Each @code{define_expand} must have a name, since the only
3029 use for it is to refer to it by name.
3031 @findex define_peephole
3033 The RTL template. This is just like the RTL template for a
3034 @code{define_peephole} in that it is a vector of RTL expressions
3035 each being one insn.
3038 The condition, a string containing a C expression. This expression is
3039 used to express how the availability of this pattern depends on
3040 subclasses of target machine, selected by command-line options when GNU
3041 CC is run. This is just like the condition of a @code{define_insn} that
3042 has a standard name. Therefore, the condition (if present) may not
3043 depend on the data in the insn being matched, but only the
3044 target-machine-type flags. The compiler needs to test these conditions
3045 during initialization in order to learn exactly which named instructions
3046 are available in a particular run.
3049 The preparation statements, a string containing zero or more C
3050 statements which are to be executed before RTL code is generated from
3053 Usually these statements prepare temporary registers for use as
3054 internal operands in the RTL template, but they can also generate RTL
3055 insns directly by calling routines such as @code{emit_insn}, etc.
3056 Any such insns precede the ones that come from the RTL template.
3059 Every RTL insn emitted by a @code{define_expand} must match some
3060 @code{define_insn} in the machine description. Otherwise, the compiler
3061 will crash when trying to generate code for the insn or trying to optimize
3064 The RTL template, in addition to controlling generation of RTL insns,
3065 also describes the operands that need to be specified when this pattern
3066 is used. In particular, it gives a predicate for each operand.
3068 A true operand, which needs to be specified in order to generate RTL from
3069 the pattern, should be described with a @code{match_operand} in its first
3070 occurrence in the RTL template. This enters information on the operand's
3071 predicate into the tables that record such things. GNU CC uses the
3072 information to preload the operand into a register if that is required for
3073 valid RTL code. If the operand is referred to more than once, subsequent
3074 references should use @code{match_dup}.
3076 The RTL template may also refer to internal ``operands'' which are
3077 temporary registers or labels used only within the sequence made by the
3078 @code{define_expand}. Internal operands are substituted into the RTL
3079 template with @code{match_dup}, never with @code{match_operand}. The
3080 values of the internal operands are not passed in as arguments by the
3081 compiler when it requests use of this pattern. Instead, they are computed
3082 within the pattern, in the preparation statements. These statements
3083 compute the values and store them into the appropriate elements of
3084 @code{operands} so that @code{match_dup} can find them.
3086 There are two special macros defined for use in the preparation statements:
3087 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
3094 Use the @code{DONE} macro to end RTL generation for the pattern. The
3095 only RTL insns resulting from the pattern on this occasion will be
3096 those already emitted by explicit calls to @code{emit_insn} within the
3097 preparation statements; the RTL template will not be generated.
3101 Make the pattern fail on this occasion. When a pattern fails, it means
3102 that the pattern was not truly available. The calling routines in the
3103 compiler will try other strategies for code generation using other patterns.
3105 Failure is currently supported only for binary (addition, multiplication,
3106 shifting, etc.) and bitfield (@code{extv}, @code{extzv}, and @code{insv})
3110 Here is an example, the definition of left-shift for the SPUR chip:
3114 (define_expand "ashlsi3"
3115 [(set (match_operand:SI 0 "register_operand" "")
3119 (match_operand:SI 1 "register_operand" "")
3120 (match_operand:SI 2 "nonmemory_operand" "")))]
3129 if (GET_CODE (operands[2]) != CONST_INT
3130 || (unsigned) INTVAL (operands[2]) > 3)
3137 This example uses @code{define_expand} so that it can generate an RTL insn
3138 for shifting when the shift-count is in the supported range of 0 to 3 but
3139 fail in other cases where machine insns aren't available. When it fails,
3140 the compiler tries another strategy using different patterns (such as, a
3143 If the compiler were able to handle nontrivial condition-strings in
3144 patterns with names, then it would be possible to use a
3145 @code{define_insn} in that case. Here is another case (zero-extension
3146 on the 68000) which makes more use of the power of @code{define_expand}:
3149 (define_expand "zero_extendhisi2"
3150 [(set (match_operand:SI 0 "general_operand" "")
3152 (set (strict_low_part
3156 (match_operand:HI 1 "general_operand" ""))]
3158 "operands[1] = make_safe_from (operands[1], operands[0]);")
3162 @findex make_safe_from
3163 Here two RTL insns are generated, one to clear the entire output operand
3164 and the other to copy the input operand into its low half. This sequence
3165 is incorrect if the input operand refers to [the old value of] the output
3166 operand, so the preparation statement makes sure this isn't so. The
3167 function @code{make_safe_from} copies the @code{operands[1]} into a
3168 temporary register if it refers to @code{operands[0]}. It does this
3169 by emitting another RTL insn.
3171 Finally, a third example shows the use of an internal operand.
3172 Zero-extension on the SPUR chip is done by @code{and}-ing the result
3173 against a halfword mask. But this mask cannot be represented by a
3174 @code{const_int} because the constant value is too large to be legitimate
3175 on this machine. So it must be copied into a register with
3176 @code{force_reg} and then the register used in the @code{and}.
3179 (define_expand "zero_extendhisi2"
3180 [(set (match_operand:SI 0 "register_operand" "")
3182 (match_operand:HI 1 "register_operand" "")
3187 = force_reg (SImode, gen_rtx (CONST_INT,
3188 VOIDmode, 65535)); ")
3191 @strong{Note:} If the @code{define_expand} is used to serve a
3192 standard binary or unary arithmetic operation or a bitfield operation,
3193 then the last insn it generates must not be a @code{code_label},
3194 @code{barrier} or @code{note}. It must be an @code{insn},
3195 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
3196 at the end, emit an insn to copy the result of the operation into
3197 itself. Such an insn will generate no code, but it can avoid problems
3198 in the compiler.@refill
3200 @node Insn Splitting
3201 @section Defining How to Split Instructions
3202 @cindex insn splitting
3203 @cindex instruction splitting
3204 @cindex splitting instructions
3206 There are two cases where you should specify how to split a pattern into
3207 multiple insns. On machines that have instructions requiring delay
3208 slots (@pxref{Delay Slots}) or that have instructions whose output is
3209 not available for multiple cycles (@pxref{Function Units}), the compiler
3210 phases that optimize these cases need to be able to move insns into
3211 one-instruction delay slots. However, some insns may generate more than one
3212 machine instruction. These insns cannot be placed into a delay slot.
3214 Often you can rewrite the single insn as a list of individual insns,
3215 each corresponding to one machine instruction. The disadvantage of
3216 doing so is that it will cause the compilation to be slower and require
3217 more space. If the resulting insns are too complex, it may also
3218 suppress some optimizations. The compiler splits the insn if there is a
3219 reason to believe that it might improve instruction or delay slot
3222 The insn combiner phase also splits putative insns. If three insns are
3223 merged into one insn with a complex expression that cannot be matched by
3224 some @code{define_insn} pattern, the combiner phase attempts to split
3225 the complex pattern into two insns that are recognized. Usually it can
3226 break the complex pattern into two patterns by splitting out some
3227 subexpression. However, in some other cases, such as performing an
3228 addition of a large constant in two insns on a RISC machine, the way to
3229 split the addition into two insns is machine-dependent.
3231 @cindex define_split
3232 The @code{define_split} definition tells the compiler how to split a
3233 complex insn into several simpler insns. It looks like this:
3237 [@var{insn-pattern}]
3239 [@var{new-insn-pattern-1}
3240 @var{new-insn-pattern-2}
3242 "@var{preparation statements}")
3245 @var{insn-pattern} is a pattern that needs to be split and
3246 @var{condition} is the final condition to be tested, as in a
3247 @code{define_insn}. When an insn matching @var{insn-pattern} and
3248 satisfying @var{condition} is found, it is replaced in the insn list
3249 with the insns given by @var{new-insn-pattern-1},
3250 @var{new-insn-pattern-2}, etc.
3252 The @var{preparation statements} are similar to those statements that
3253 are specified for @code{define_expand} (@pxref{Expander Definitions})
3254 and are executed before the new RTL is generated to prepare for the
3255 generated code or emit some insns whose pattern is not fixed. Unlike
3256 those in @code{define_expand}, however, these statements must not
3257 generate any new pseudo-registers. Once reload has completed, they also
3258 must not allocate any space in the stack frame.
3260 Patterns are matched against @var{insn-pattern} in two different
3261 circumstances. If an insn needs to be split for delay slot scheduling
3262 or insn scheduling, the insn is already known to be valid, which means
3263 that it must have been matched by some @code{define_insn} and, if
3264 @code{reload_completed} is non-zero, is known to satisfy the constraints
3265 of that @code{define_insn}. In that case, the new insn patterns must
3266 also be insns that are matched by some @code{define_insn} and, if
3267 @code{reload_completed} is non-zero, must also satisfy the constraints
3268 of those definitions.
3270 As an example of this usage of @code{define_split}, consider the following
3271 example from @file{a29k.md}, which splits a @code{sign_extend} from
3272 @code{HImode} to @code{SImode} into a pair of shift insns:
3276 [(set (match_operand:SI 0 "gen_reg_operand" "")
3277 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
3280 (ashift:SI (match_dup 1)
3283 (ashiftrt:SI (match_dup 0)
3286 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
3289 When the combiner phase tries to split an insn pattern, it is always the
3290 case that the pattern is @emph{not} matched by any @code{define_insn}.
3291 The combiner pass first tries to split a single @code{set} expression
3292 and then the same @code{set} expression inside a @code{parallel}, but
3293 followed by a @code{clobber} of a pseudo-reg to use as a scratch
3294 register. In these cases, the combiner expects exactly two new insn
3295 patterns to be generated. It will verify that these patterns match some
3296 @code{define_insn} definitions, so you need not do this test in the
3297 @code{define_split} (of course, there is no point in writing a
3298 @code{define_split} that will never produce insns that match).
3300 Here is an example of this use of @code{define_split}, taken from
3305 [(set (match_operand:SI 0 "gen_reg_operand" "")
3306 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
3307 (match_operand:SI 2 "non_add_cint_operand" "")))]
3309 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
3310 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
3313 int low = INTVAL (operands[2]) & 0xffff;
3314 int high = (unsigned) INTVAL (operands[2]) >> 16;
3317 high++, low |= 0xffff0000;
3319 operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
3320 operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
3324 Here the predicate @code{non_add_cint_operand} matches any
3325 @code{const_int} that is @emph{not} a valid operand of a single add
3326 insn. The add with the smaller displacement is written so that it
3327 can be substituted into the address of a subsequent operation.
3329 An example that uses a scratch register, from the same file, generates
3330 an equality comparison of a register and a large constant:
3334 [(set (match_operand:CC 0 "cc_reg_operand" "")
3335 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3336 (match_operand:SI 2 "non_short_cint_operand" "")))
3337 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
3338 "find_single_use (operands[0], insn, 0)
3339 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
3340 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
3341 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
3342 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
3345 /* Get the constant we are comparing against, C, and see what it
3346 looks like sign-extended to 16 bits. Then see what constant
3347 could be XOR'ed with C to get the sign-extended value. */
3349 int c = INTVAL (operands[2]);
3350 int sextc = (c << 16) >> 16;
3351 int xorv = c ^ sextc;
3353 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
3354 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
3358 To avoid confusion, don't write a single @code{define_split} that
3359 accepts some insns that match some @code{define_insn} as well as some
3360 insns that don't. Instead, write two separate @code{define_split}
3361 definitions, one for the insns that are valid and one for the insns that
3364 @node Insn Attributes
3365 @section Instruction Attributes
3366 @cindex insn attributes
3367 @cindex instruction attributes
3369 In addition to describing the instruction supported by the target machine,
3370 the @file{md} file also defines a group of @dfn{attributes} and a set of
3371 values for each. Every generated insn is assigned a value for each attribute.
3372 One possible attribute would be the effect that the insn has on the machine's
3373 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
3374 to track the condition codes.
3377 * Defining Attributes:: Specifying attributes and their values.
3378 * Expressions:: Valid expressions for attribute values.
3379 * Tagging Insns:: Assigning attribute values to insns.
3380 * Attr Example:: An example of assigning attributes.
3381 * Insn Lengths:: Computing the length of insns.
3382 * Constant Attributes:: Defining attributes that are constant.
3383 * Delay Slots:: Defining delay slots required for a machine.
3384 * Function Units:: Specifying information for insn scheduling.
3387 @node Defining Attributes
3388 @subsection Defining Attributes and their Values
3389 @cindex defining attributes and their values
3390 @cindex attributes, defining
3393 The @code{define_attr} expression is used to define each attribute required
3394 by the target machine. It looks like:
3397 (define_attr @var{name} @var{list-of-values} @var{default})
3400 @var{name} is a string specifying the name of the attribute being defined.
3402 @var{list-of-values} is either a string that specifies a comma-separated
3403 list of values that can be assigned to the attribute, or a null string to
3404 indicate that the attribute takes numeric values.
3406 @var{default} is an attribute expression that gives the value of this
3407 attribute for insns that match patterns whose definition does not include
3408 an explicit value for this attribute. @xref{Attr Example}, for more
3409 information on the handling of defaults. @xref{Constant Attributes},
3410 for information on attributes that do not depend on any particular insn.
3413 For each defined attribute, a number of definitions are written to the
3414 @file{insn-attr.h} file. For cases where an explicit set of values is
3415 specified for an attribute, the following are defined:
3419 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
3422 An enumeral class is defined for @samp{attr_@var{name}} with
3423 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
3424 the attribute name and value are first converted to upper case.
3427 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
3428 returns the attribute value for that insn.
3431 For example, if the following is present in the @file{md} file:
3434 (define_attr "type" "branch,fp,load,store,arith" @dots{})
3438 the following lines will be written to the file @file{insn-attr.h}.
3441 #define HAVE_ATTR_type
3442 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
3443 TYPE_STORE, TYPE_ARITH@};
3444 extern enum attr_type get_attr_type ();
3447 If the attribute takes numeric values, no @code{enum} type will be
3448 defined and the function to obtain the attribute's value will return
3452 @subsection Attribute Expressions
3453 @cindex attribute expressions
3455 RTL expressions used to define attributes use the codes described above
3456 plus a few specific to attribute definitions, to be discussed below.
3457 Attribute value expressions must have one of the following forms:
3460 @cindex @code{const_int} and attributes
3461 @item (const_int @var{i})
3462 The integer @var{i} specifies the value of a numeric attribute. @var{i}
3463 must be non-negative.
3465 The value of a numeric attribute can be specified either with a
3466 @code{const_int} or as an integer represented as a string in
3467 @code{const_string}, @code{eq_attr} (see below), and @code{set_attr}
3468 (@pxref{Tagging Insns}) expressions.
3470 @cindex @code{const_string} and attributes
3471 @item (const_string @var{value})
3472 The string @var{value} specifies a constant attribute value.
3473 If @var{value} is specified as @samp{"*"}, it means that the default value of
3474 the attribute is to be used for the insn containing this expression.
3475 @samp{"*"} obviously cannot be used in the @var{default} expression
3476 of a @code{define_attr}.@refill
3478 If the attribute whose value is being specified is numeric, @var{value}
3479 must be a string containing a non-negative integer (normally
3480 @code{const_int} would be used in this case). Otherwise, it must
3481 contain one of the valid values for the attribute.
3483 @cindex @code{if_then_else} and attributes
3484 @item (if_then_else @var{test} @var{true-value} @var{false-value})
3485 @var{test} specifies an attribute test, whose format is defined below.
3486 The value of this expression is @var{true-value} if @var{test} is true,
3487 otherwise it is @var{false-value}.
3489 @cindex @code{cond} and attributes
3490 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
3491 The first operand of this expression is a vector containing an even
3492 number of expressions and consisting of pairs of @var{test} and @var{value}
3493 expressions. The value of the @code{cond} expression is that of the
3494 @var{value} corresponding to the first true @var{test} expression. If
3495 none of the @var{test} expressions are true, the value of the @code{cond}
3496 expression is that of the @var{default} expression.
3499 @var{test} expressions can have one of the following forms:
3502 @cindex @code{const_int} and attribute tests
3503 @item (const_int @var{i})
3504 This test is true if @var{i} is non-zero and false otherwise.
3506 @cindex @code{not} and attributes
3507 @cindex @code{ior} and attributes
3508 @cindex @code{and} and attributes
3509 @item (not @var{test})
3510 @itemx (ior @var{test1} @var{test2})
3511 @itemx (and @var{test1} @var{test2})
3512 These tests are true if the indicated logical function is true.
3514 @cindex @code{match_operand} and attributes
3515 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
3516 This test is true if operand @var{n} of the insn whose attribute value
3517 is being determined has mode @var{m} (this part of the test is ignored
3518 if @var{m} is @code{VOIDmode}) and the function specified by the string
3519 @var{pred} returns a non-zero value when passed operand @var{n} and mode
3520 @var{m} (this part of the test is ignored if @var{pred} is the null
3523 The @var{constraints} operand is ignored and should be the null string.
3525 @cindex @code{le} and attributes
3526 @cindex @code{leu} and attributes
3527 @cindex @code{lt} and attributes
3528 @cindex @code{gt} and attributes
3529 @cindex @code{gtu} and attributes
3530 @cindex @code{ge} and attributes
3531 @cindex @code{geu} and attributes
3532 @cindex @code{ne} and attributes
3533 @cindex @code{eq} and attributes
3534 @cindex @code{plus} and attributes
3535 @cindex @code{minus} and attributes
3536 @cindex @code{mult} and attributes
3537 @cindex @code{div} and attributes
3538 @cindex @code{mod} and attributes
3539 @cindex @code{abs} and attributes
3540 @cindex @code{neg} and attributes
3541 @cindex @code{ashift} and attributes
3542 @cindex @code{lshiftrt} and attributes
3543 @cindex @code{ashiftrt} and attributes
3544 @item (le @var{arith1} @var{arith2})
3545 @itemx (leu @var{arith1} @var{arith2})
3546 @itemx (lt @var{arith1} @var{arith2})
3547 @itemx (ltu @var{arith1} @var{arith2})
3548 @itemx (gt @var{arith1} @var{arith2})
3549 @itemx (gtu @var{arith1} @var{arith2})
3550 @itemx (ge @var{arith1} @var{arith2})
3551 @itemx (geu @var{arith1} @var{arith2})
3552 @itemx (ne @var{arith1} @var{arith2})
3553 @itemx (eq @var{arith1} @var{arith2})
3554 These tests are true if the indicated comparison of the two arithmetic
3555 expressions is true. Arithmetic expressions are formed with
3556 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
3557 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
3558 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.@refill
3561 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
3562 Lengths},for additional forms). @code{symbol_ref} is a string
3563 denoting a C expression that yields an @code{int} when evaluated by the
3564 @samp{get_attr_@dots{}} routine. It should normally be a global
3568 @item (eq_attr @var{name} @var{value})
3569 @var{name} is a string specifying the name of an attribute.
3571 @var{value} is a string that is either a valid value for attribute
3572 @var{name}, a comma-separated list of values, or @samp{!} followed by a
3573 value or list. If @var{value} does not begin with a @samp{!}, this
3574 test is true if the value of the @var{name} attribute of the current
3575 insn is in the list specified by @var{value}. If @var{value} begins
3576 with a @samp{!}, this test is true if the attribute's value is
3577 @emph{not} in the specified list.
3582 (eq_attr "type" "load,store")
3589 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
3592 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
3593 value of the compiler variable @code{which_alternative}
3594 (@pxref{Output Statement}) and the values must be small integers. For
3598 (eq_attr "alternative" "2,3")
3605 (ior (eq (symbol_ref "which_alternative") (const_int 2))
3606 (eq (symbol_ref "which_alternative") (const_int 3)))
3609 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
3610 where the value of the attribute being tested is known for all insns matching
3611 a particular pattern. This is by far the most common case.@refill
3614 @item (attr_flag @var{name})
3615 The value of an @code{attr_flag} expression is true if the flag
3616 specified by @var{name} is true for the @code{insn} currently being
3619 @var{name} is a string specifying one of a fixed set of flags to test.
3620 Test the flags @code{forward} and @code{backward} to determine the
3621 direction of a conditional branch. Test the flags @code{very_likely},
3622 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
3623 if a conditional branch is expected to be taken.
3625 If the @code{very_likely} flag is true, then the @code{likely} flag is also
3626 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
3628 This example describes a conditional branch delay slot which
3629 can be nullified for forward branches that are taken (annul-true) or
3630 for backward branches which are not taken (annul-false).
3633 (define_delay (eq_attr "type" "cbranch")
3634 [(eq_attr "in_branch_delay" "true")
3635 (and (eq_attr "in_branch_delay" "true")
3636 (attr_flag "forward"))
3637 (and (eq_attr "in_branch_delay" "true")
3638 (attr_flag "backward"))])
3641 The @code{forward} and @code{backward} flags are false if the current
3642 @code{insn} being scheduled is not a conditional branch.
3644 The @code{very_likely} and @code{likely} flags are true if the
3645 @code{insn} being scheduled is not a conditional branch.
3646 The @code{very_unlikely} and @code{unlikely} flags are false if the
3647 @code{insn} being scheduled is not a conditional branch.
3649 @code{attr_flag} is only used during delay slot scheduling and has no
3650 meaning to other passes of the compiler.
3654 @subsection Assigning Attribute Values to Insns
3655 @cindex tagging insns
3656 @cindex assigning attribute values to insns
3658 The value assigned to an attribute of an insn is primarily determined by
3659 which pattern is matched by that insn (or which @code{define_peephole}
3660 generated it). Every @code{define_insn} and @code{define_peephole} can
3661 have an optional last argument to specify the values of attributes for
3662 matching insns. The value of any attribute not specified in a particular
3663 insn is set to the default value for that attribute, as specified in its
3664 @code{define_attr}. Extensive use of default values for attributes
3665 permits the specification of the values for only one or two attributes
3666 in the definition of most insn patterns, as seen in the example in the
3667 next section.@refill
3669 The optional last argument of @code{define_insn} and
3670 @code{define_peephole} is a vector of expressions, each of which defines
3671 the value for a single attribute. The most general way of assigning an
3672 attribute's value is to use a @code{set} expression whose first operand is an
3673 @code{attr} expression giving the name of the attribute being set. The
3674 second operand of the @code{set} is an attribute expression
3675 (@pxref{Expressions}) giving the value of the attribute.@refill
3677 When the attribute value depends on the @samp{alternative} attribute
3678 (i.e., which is the applicable alternative in the constraint of the
3679 insn), the @code{set_attr_alternative} expression can be used. It
3680 allows the specification of a vector of attribute expressions, one for
3684 When the generality of arbitrary attribute expressions is not required,
3685 the simpler @code{set_attr} expression can be used, which allows
3686 specifying a string giving either a single attribute value or a list
3687 of attribute values, one for each alternative.
3689 The form of each of the above specifications is shown below. In each case,
3690 @var{name} is a string specifying the attribute to be set.
3693 @item (set_attr @var{name} @var{value-string})
3694 @var{value-string} is either a string giving the desired attribute value,
3695 or a string containing a comma-separated list giving the values for
3696 succeeding alternatives. The number of elements must match the number
3697 of alternatives in the constraint of the insn pattern.
3699 Note that it may be useful to specify @samp{*} for some alternative, in
3700 which case the attribute will assume its default value for insns matching
3703 @findex set_attr_alternative
3704 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
3705 Depending on the alternative of the insn, the value will be one of the
3706 specified values. This is a shorthand for using a @code{cond} with
3707 tests on the @samp{alternative} attribute.
3710 @item (set (attr @var{name}) @var{value})
3711 The first operand of this @code{set} must be the special RTL expression
3712 @code{attr}, whose sole operand is a string giving the name of the
3713 attribute being set. @var{value} is the value of the attribute.
3716 The following shows three different ways of representing the same
3717 attribute value specification:
3720 (set_attr "type" "load,store,arith")
3722 (set_attr_alternative "type"
3723 [(const_string "load") (const_string "store")
3724 (const_string "arith")])
3727 (cond [(eq_attr "alternative" "1") (const_string "load")
3728 (eq_attr "alternative" "2") (const_string "store")]
3729 (const_string "arith")))
3733 @findex define_asm_attributes
3734 The @code{define_asm_attributes} expression provides a mechanism to
3735 specify the attributes assigned to insns produced from an @code{asm}
3736 statement. It has the form:
3739 (define_asm_attributes [@var{attr-sets}])
3743 where @var{attr-sets} is specified the same as for both the
3744 @code{define_insn} and the @code{define_peephole} expressions.
3746 These values will typically be the ``worst case'' attribute values. For
3747 example, they might indicate that the condition code will be clobbered.
3749 A specification for a @code{length} attribute is handled specially. The
3750 way to compute the length of an @code{asm} insn is to multiply the
3751 length specified in the expression @code{define_asm_attributes} by the
3752 number of machine instructions specified in the @code{asm} statement,
3753 determined by counting the number of semicolons and newlines in the
3754 string. Therefore, the value of the @code{length} attribute specified
3755 in a @code{define_asm_attributes} should be the maximum possible length
3756 of a single machine instruction.
3759 @subsection Example of Attribute Specifications
3760 @cindex attribute specifications example
3761 @cindex attribute specifications
3763 The judicious use of defaulting is important in the efficient use of
3764 insn attributes. Typically, insns are divided into @dfn{types} and an
3765 attribute, customarily called @code{type}, is used to represent this
3766 value. This attribute is normally used only to define the default value
3767 for other attributes. An example will clarify this usage.
3769 Assume we have a RISC machine with a condition code and in which only
3770 full-word operations are performed in registers. Let us assume that we
3771 can divide all insns into loads, stores, (integer) arithmetic
3772 operations, floating point operations, and branches.
3774 Here we will concern ourselves with determining the effect of an insn on
3775 the condition code and will limit ourselves to the following possible
3776 effects: The condition code can be set unpredictably (clobbered), not
3777 be changed, be set to agree with the results of the operation, or only
3778 changed if the item previously set into the condition code has been
3781 Here is part of a sample @file{md} file for such a machine:
3784 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
3786 (define_attr "cc" "clobber,unchanged,set,change0"
3787 (cond [(eq_attr "type" "load")
3788 (const_string "change0")
3789 (eq_attr "type" "store,branch")
3790 (const_string "unchanged")
3791 (eq_attr "type" "arith")
3792 (if_then_else (match_operand:SI 0 "" "")
3793 (const_string "set")
3794 (const_string "clobber"))]
3795 (const_string "clobber")))
3798 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
3799 (match_operand:SI 1 "general_operand" "r,m,r"))]
3805 [(set_attr "type" "arith,load,store")])
3808 Note that we assume in the above example that arithmetic operations
3809 performed on quantities smaller than a machine word clobber the condition
3810 code since they will set the condition code to a value corresponding to the
3814 @subsection Computing the Length of an Insn
3815 @cindex insn lengths, computing
3816 @cindex computing the length of an insn
3818 For many machines, multiple types of branch instructions are provided, each
3819 for different length branch displacements. In most cases, the assembler
3820 will choose the correct instruction to use. However, when the assembler
3821 cannot do so, GCC can when a special attribute, the @samp{length}
3822 attribute, is defined. This attribute must be defined to have numeric
3823 values by specifying a null string in its @code{define_attr}.
3825 In the case of the @samp{length} attribute, two additional forms of
3826 arithmetic terms are allowed in test expressions:
3829 @cindex @code{match_dup} and attributes
3830 @item (match_dup @var{n})
3831 This refers to the address of operand @var{n} of the current insn, which
3832 must be a @code{label_ref}.
3834 @cindex @code{pc} and attributes
3836 This refers to the address of the @emph{current} insn. It might have
3837 been more consistent with other usage to make this the address of the
3838 @emph{next} insn but this would be confusing because the length of the
3839 current insn is to be computed.
3842 @cindex @code{addr_vec}, length of
3843 @cindex @code{addr_diff_vec}, length of
3844 For normal insns, the length will be determined by value of the
3845 @samp{length} attribute. In the case of @code{addr_vec} and
3846 @code{addr_diff_vec} insn patterns, the length is computed as
3847 the number of vectors multiplied by the size of each vector.
3849 Lengths are measured in addressable storage units (bytes).
3851 The following macros can be used to refine the length computation:
3854 @findex FIRST_INSN_ADDRESS
3855 @item FIRST_INSN_ADDRESS
3856 When the @code{length} insn attribute is used, this macro specifies the
3857 value to be assigned to the address of the first insn in a function. If
3858 not specified, 0 is used.
3860 @findex ADJUST_INSN_LENGTH
3861 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
3862 If defined, modifies the length assigned to instruction @var{insn} as a
3863 function of the context in which it is used. @var{length} is an lvalue
3864 that contains the initially computed length of the insn and should be
3865 updated with the correct length of the insn. If updating is required,
3866 @var{insn} must not be a varying-length insn.
3868 This macro will normally not be required. A case in which it is
3869 required is the ROMP. On this machine, the size of an @code{addr_vec}
3870 insn must be increased by two to compensate for the fact that alignment
3874 @findex get_attr_length
3875 The routine that returns @code{get_attr_length} (the value of the
3876 @code{length} attribute) can be used by the output routine to
3877 determine the form of the branch instruction to be written, as the
3878 example below illustrates.
3880 As an example of the specification of variable-length branches, consider
3881 the IBM 360. If we adopt the convention that a register will be set to
3882 the starting address of a function, we can jump to labels within 4k of
3883 the start using a four-byte instruction. Otherwise, we need a six-byte
3884 sequence to load the address from memory and then branch to it.
3886 On such a machine, a pattern for a branch instruction might be specified
3892 (label_ref (match_operand 0 "" "")))]
3896 return (get_attr_length (insn) == 4
3897 ? \"b %l0\" : \"l r15,=a(%l0); br r15\");
3899 [(set (attr "length") (if_then_else (lt (match_dup 0) (const_int 4096))
3904 @node Constant Attributes
3905 @subsection Constant Attributes
3906 @cindex constant attributes
3908 A special form of @code{define_attr}, where the expression for the
3909 default value is a @code{const} expression, indicates an attribute that
3910 is constant for a given run of the compiler. Constant attributes may be
3911 used to specify which variety of processor is used. For example,
3914 (define_attr "cpu" "m88100,m88110,m88000"
3916 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
3917 (symbol_ref "TARGET_88110") (const_string "m88110")]
3918 (const_string "m88000"))))
3920 (define_attr "memory" "fast,slow"
3922 (if_then_else (symbol_ref "TARGET_FAST_MEM")
3923 (const_string "fast")
3924 (const_string "slow"))))
3927 The routine generated for constant attributes has no parameters as it
3928 does not depend on any particular insn. RTL expressions used to define
3929 the value of a constant attribute may use the @code{symbol_ref} form,
3930 but may not use either the @code{match_operand} form or @code{eq_attr}
3931 forms involving insn attributes.
3934 @subsection Delay Slot Scheduling
3935 @cindex delay slots, defining
3937 The insn attribute mechanism can be used to specify the requirements for
3938 delay slots, if any, on a target machine. An instruction is said to
3939 require a @dfn{delay slot} if some instructions that are physically
3940 after the instruction are executed as if they were located before it.
3941 Classic examples are branch and call instructions, which often execute
3942 the following instruction before the branch or call is performed.
3944 On some machines, conditional branch instructions can optionally
3945 @dfn{annul} instructions in the delay slot. This means that the
3946 instruction will not be executed for certain branch outcomes. Both
3947 instructions that annul if the branch is true and instructions that
3948 annul if the branch is false are supported.
3950 Delay slot scheduling differs from instruction scheduling in that
3951 determining whether an instruction needs a delay slot is dependent only
3952 on the type of instruction being generated, not on data flow between the
3953 instructions. See the next section for a discussion of data-dependent
3954 instruction scheduling.
3956 @findex define_delay
3957 The requirement of an insn needing one or more delay slots is indicated
3958 via the @code{define_delay} expression. It has the following form:
3961 (define_delay @var{test}
3962 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
3963 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
3967 @var{test} is an attribute test that indicates whether this
3968 @code{define_delay} applies to a particular insn. If so, the number of
3969 required delay slots is determined by the length of the vector specified
3970 as the second argument. An insn placed in delay slot @var{n} must
3971 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
3972 attribute test that specifies which insns may be annulled if the branch
3973 is true. Similarly, @var{annul-false-n} specifies which insns in the
3974 delay slot may be annulled if the branch is false. If annulling is not
3975 supported for that delay slot, @code{(nil)} should be coded.@refill
3977 For example, in the common case where branch and call insns require
3978 a single delay slot, which may contain any insn other than a branch or
3979 call, the following would be placed in the @file{md} file:
3982 (define_delay (eq_attr "type" "branch,call")
3983 [(eq_attr "type" "!branch,call") (nil) (nil)])
3986 Multiple @code{define_delay} expressions may be specified. In this
3987 case, each such expression specifies different delay slot requirements
3988 and there must be no insn for which tests in two @code{define_delay}
3989 expressions are both true.
3991 For example, if we have a machine that requires one delay slot for branches
3992 but two for calls, no delay slot can contain a branch or call insn,
3993 and any valid insn in the delay slot for the branch can be annulled if the
3994 branch is true, we might represent this as follows:
3997 (define_delay (eq_attr "type" "branch")
3998 [(eq_attr "type" "!branch,call")
3999 (eq_attr "type" "!branch,call")
4002 (define_delay (eq_attr "type" "call")
4003 [(eq_attr "type" "!branch,call") (nil) (nil)
4004 (eq_attr "type" "!branch,call") (nil) (nil)])
4006 @c the above is *still* too long. --mew 4feb93
4008 @node Function Units
4009 @subsection Specifying Function Units
4010 @cindex function units, for scheduling
4012 On most RISC machines, there are instructions whose results are not
4013 available for a specific number of cycles. Common cases are instructions
4014 that load data from memory. On many machines, a pipeline stall will result
4015 if the data is referenced too soon after the load instruction.
4017 In addition, many newer microprocessors have multiple function units, usually
4018 one for integer and one for floating point, and often will incur pipeline
4019 stalls when a result that is needed is not yet ready.
4021 The descriptions in this section allow the specification of how much
4022 time must elapse between the execution of an instruction and the time
4023 when its result is used. It also allows specification of when the
4024 execution of an instruction will delay execution of similar instructions
4025 due to function unit conflicts.
4027 For the purposes of the specifications in this section, a machine is
4028 divided into @dfn{function units}, each of which execute a specific
4029 class of instructions in first-in-first-out order. Function units that
4030 accept one instruction each cycle and allow a result to be used in the
4031 succeeding instruction (usually via forwarding) need not be specified.
4032 Classic RISC microprocessors will normally have a single function unit,
4033 which we can call @samp{memory}. The newer ``superscalar'' processors
4034 will often have function units for floating point operations, usually at
4035 least a floating point adder and multiplier.
4037 @findex define_function_unit
4038 Each usage of a function units by a class of insns is specified with a
4039 @code{define_function_unit} expression, which looks like this:
4042 (define_function_unit @var{name} @var{multiplicity} @var{simultaneity}
4043 @var{test} @var{ready-delay} @var{issue-delay}
4044 [@var{conflict-list}])
4047 @var{name} is a string giving the name of the function unit.
4049 @var{multiplicity} is an integer specifying the number of identical
4050 units in the processor. If more than one unit is specified, they will
4051 be scheduled independently. Only truly independent units should be
4052 counted; a pipelined unit should be specified as a single unit. (The
4053 only common example of a machine that has multiple function units for a
4054 single instruction class that are truly independent and not pipelined
4055 are the two multiply and two increment units of the CDC 6600.)
4057 @var{simultaneity} specifies the maximum number of insns that can be
4058 executing in each instance of the function unit simultaneously or zero
4059 if the unit is pipelined and has no limit.
4061 All @code{define_function_unit} definitions referring to function unit
4062 @var{name} must have the same name and values for @var{multiplicity} and
4065 @var{test} is an attribute test that selects the insns we are describing
4066 in this definition. Note that an insn may use more than one function
4067 unit and a function unit may be specified in more than one
4068 @code{define_function_unit}.
4070 @var{ready-delay} is an integer that specifies the number of cycles
4071 after which the result of the instruction can be used without
4072 introducing any stalls.
4074 @var{issue-delay} is an integer that specifies the number of cycles
4075 after the instruction matching the @var{test} expression begins using
4076 this unit until a subsequent instruction can begin. A cost of @var{N}
4077 indicates an @var{N-1} cycle delay. A subsequent instruction may also
4078 be delayed if an earlier instruction has a longer @var{ready-delay}
4079 value. This blocking effect is computed using the @var{simultaneity},
4080 @var{ready-delay}, @var{issue-delay}, and @var{conflict-list} terms.
4081 For a normal non-pipelined function unit, @var{simultaneity} is one, the
4082 unit is taken to block for the @var{ready-delay} cycles of the executing
4083 insn, and smaller values of @var{issue-delay} are ignored.
4085 @var{conflict-list} is an optional list giving detailed conflict costs
4086 for this unit. If specified, it is a list of condition test expressions
4087 to be applied to insns chosen to execute in @var{name} following the
4088 particular insn matching @var{test} that is already executing in
4089 @var{name}. For each insn in the list, @var{issue-delay} specifies the
4090 conflict cost; for insns not in the list, the cost is zero. If not
4091 specified, @var{conflict-list} defaults to all instructions that use the
4094 Typical uses of this vector are where a floating point function unit can
4095 pipeline either single- or double-precision operations, but not both, or
4096 where a memory unit can pipeline loads, but not stores, etc.
4098 As an example, consider a classic RISC machine where the result of a
4099 load instruction is not available for two cycles (a single ``delay''
4100 instruction is required) and where only one load instruction can be executed
4101 simultaneously. This would be specified as:
4104 (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
4107 For the case of a floating point function unit that can pipeline either
4108 single or double precision, but not both, the following could be specified:
4111 (define_function_unit
4112 "fp" 1 0 (eq_attr "type" "sp_fp") 4 4 [(eq_attr "type" "dp_fp")])
4113 (define_function_unit
4114 "fp" 1 0 (eq_attr "type" "dp_fp") 4 4 [(eq_attr "type" "sp_fp")])
4117 @strong{Note:} The scheduler attempts to avoid function unit conflicts
4118 and uses all the specifications in the @code{define_function_unit}
4119 expression. It has recently come to our attention that these
4120 specifications may not allow modeling of some of the newer
4121 ``superscalar'' processors that have insns using multiple pipelined
4122 units. These insns will cause a potential conflict for the second unit
4123 used during their execution and there is no way of representing that
4124 conflict. We welcome any examples of how function unit conflicts work
4125 in such processors and suggestions for their representation.