1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
77 /* Next quantity number available for allocation. */
81 /* Information we maitain about each quantity. */
84 /* The number of refs to quantity Q. */
88 /* Insn number (counting from head of basic block)
89 where quantity Q was born. -1 if birth has not been recorded. */
93 /* Insn number (counting from head of basic block)
94 where given quantity died. Due to the way tying is done,
95 and the fact that we consider in this pass only regs that die but once,
96 a quantity can die only once. Each quantity's life span
97 is a set of consecutive insns. -1 if death has not been recorded. */
101 /* Number of words needed to hold the data in given quantity.
102 This depends on its machine mode. It is used for these purposes:
103 1. It is used in computing the relative importances of qtys,
104 which determines the order in which we look for regs for them.
105 2. It is used in rules that prevent tying several registers of
106 different sizes in a way that is geometrically impossible
107 (see combine_regs). */
111 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
115 /* The register number of one pseudo register whose reg_qty value is Q.
116 This register should be the head of the chain
117 maintained in reg_next_in_qty. */
121 /* Reg class contained in (smaller than) the preferred classes of all
122 the pseudo regs that are tied in given quantity.
123 This is the preferred class for allocating that quantity. */
125 enum reg_class min_class
;
127 /* Register class within which we allocate given qty if we can't get
128 its preferred class. */
130 enum reg_class alternate_class
;
132 /* This holds the mode of the registers that are tied to given qty,
133 or VOIDmode if registers with differing modes are tied together. */
135 enum machine_mode mode
;
137 /* the hard reg number chosen for given quantity,
138 or -1 if none was found. */
142 /* Nonzero if this quantity has been used in a SUBREG in some
143 way that is illegal. */
149 static struct qty
*qty
;
151 /* These fields are kept separately to speedup their clearing. */
153 /* We maintain two hard register sets that indicate suggested hard registers
154 for each quantity. The first, phys_copy_sugg, contains hard registers
155 that are tied to the quantity by a simple copy. The second contains all
156 hard registers that are tied to the quantity via an arithmetic operation.
158 The former register set is given priority for allocation. This tends to
159 eliminate copy insns. */
161 /* Element Q is a set of hard registers that are suggested for quantity Q by
164 static HARD_REG_SET
*qty_phys_copy_sugg
;
166 /* Element Q is a set of hard registers that are suggested for quantity Q by
169 static HARD_REG_SET
*qty_phys_sugg
;
171 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
173 static short *qty_phys_num_copy_sugg
;
175 /* Element Q is the number of suggested registers in qty_phys_sugg. */
177 static short *qty_phys_num_sugg
;
179 /* If (REG N) has been assigned a quantity number, is a register number
180 of another register assigned the same quantity number, or -1 for the
181 end of the chain. qty->first_reg point to the head of this chain. */
183 static int *reg_next_in_qty
;
185 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
187 of -1 if this register cannot be allocated by local-alloc,
188 or -2 if not known yet.
190 Note that if we see a use or death of pseudo register N with
191 reg_qty[N] == -2, register N must be local to the current block. If
192 it were used in more than one block, we would have reg_qty[N] == -1.
193 This relies on the fact that if reg_basic_block[N] is >= 0, register N
194 will not appear in any other block. We save a considerable number of
195 tests by exploiting this.
197 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
202 /* The offset (in words) of register N within its quantity.
203 This can be nonzero if register N is SImode, and has been tied
204 to a subreg of a DImode register. */
206 static char *reg_offset
;
208 /* Vector of substitutions of register numbers,
209 used to map pseudo regs into hardware regs.
210 This is set up as a result of register allocation.
211 Element N is the hard reg assigned to pseudo reg N,
212 or is -1 if no hard reg was assigned.
213 If N is a hard reg number, element N is N. */
217 /* Set of hard registers live at the current point in the scan
218 of the instructions in a basic block. */
220 static HARD_REG_SET regs_live
;
222 /* Each set of hard registers indicates registers live at a particular
223 point in the basic block. For N even, regs_live_at[N] says which
224 hard registers are needed *after* insn N/2 (i.e., they may not
225 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
227 If an object is to conflict with the inputs of insn J but not the
228 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
229 if it is to conflict with the outputs of insn J but not the inputs of
230 insn J + 1, it is said to die at index J*2 + 1. */
232 static HARD_REG_SET
*regs_live_at
;
234 /* Communicate local vars `insn_number' and `insn'
235 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
236 static int this_insn_number
;
237 static rtx this_insn
;
239 /* Used to communicate changes made by update_equiv_regs to
240 memref_referenced_p. reg_equiv_replacement is set for any REG_EQUIV note
241 found or created, so that we can keep track of what memory accesses might
242 be created later, e.g. by reload. */
244 static rtx
*reg_equiv_replacement
;
246 /* Used for communication between update_equiv_regs and no_equiv. */
247 static rtx
*reg_equiv_init_insns
;
249 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
250 static int recorded_label_ref
;
252 static void alloc_qty
PARAMS ((int, enum machine_mode
, int, int));
253 static void validate_equiv_mem_from_store
PARAMS ((rtx
, rtx
, void *));
254 static int validate_equiv_mem
PARAMS ((rtx
, rtx
, rtx
));
255 static int contains_replace_regs
PARAMS ((rtx
, char *));
256 static int memref_referenced_p
PARAMS ((rtx
, rtx
));
257 static int memref_used_between_p
PARAMS ((rtx
, rtx
, rtx
));
258 static void update_equiv_regs
PARAMS ((void));
259 static void no_equiv
PARAMS ((rtx
, rtx
, void *));
260 static void block_alloc
PARAMS ((int));
261 static int qty_sugg_compare
PARAMS ((int, int));
262 static int qty_sugg_compare_1
PARAMS ((const PTR
, const PTR
));
263 static int qty_compare
PARAMS ((int, int));
264 static int qty_compare_1
PARAMS ((const PTR
, const PTR
));
265 static int combine_regs
PARAMS ((rtx
, rtx
, int, int, rtx
, int));
266 static int reg_meets_class_p
PARAMS ((int, enum reg_class
));
267 static void update_qty_class
PARAMS ((int, int));
268 static void reg_is_set
PARAMS ((rtx
, rtx
, void *));
269 static void reg_is_born
PARAMS ((rtx
, int));
270 static void wipe_dead_reg
PARAMS ((rtx
, int));
271 static int find_free_reg
PARAMS ((enum reg_class
, enum machine_mode
,
272 int, int, int, int, int));
273 static void mark_life
PARAMS ((int, enum machine_mode
, int));
274 static void post_mark_life
PARAMS ((int, enum machine_mode
, int, int, int));
275 static int no_conflict_p
PARAMS ((rtx
, rtx
, rtx
));
276 static int requires_inout
PARAMS ((const char *));
278 /* Allocate a new quantity (new within current basic block)
279 for register number REGNO which is born at index BIRTH
280 within the block. MODE and SIZE are info on reg REGNO. */
283 alloc_qty (regno
, mode
, size
, birth
)
285 enum machine_mode mode
;
288 register int qtyno
= next_qty
++;
290 reg_qty
[regno
] = qtyno
;
291 reg_offset
[regno
] = 0;
292 reg_next_in_qty
[regno
] = -1;
294 qty
[qtyno
].first_reg
= regno
;
295 qty
[qtyno
].size
= size
;
296 qty
[qtyno
].mode
= mode
;
297 qty
[qtyno
].birth
= birth
;
298 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
299 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
300 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
301 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
302 qty
[qtyno
].changes_mode
= REG_CHANGES_MODE (regno
);
305 /* Main entry point of this file. */
313 /* We need to keep track of whether or not we recorded a LABEL_REF so
314 that we know if the jump optimizer needs to be rerun. */
315 recorded_label_ref
= 0;
317 /* Leaf functions and non-leaf functions have different needs.
318 If defined, let the machine say what kind of ordering we
320 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
321 ORDER_REGS_FOR_LOCAL_ALLOC
;
324 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
326 update_equiv_regs ();
328 /* This sets the maximum number of quantities we can have. Quantity
329 numbers start at zero and we can have one for each pseudo. */
330 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
332 /* Allocate vectors of temporary data.
333 See the declarations of these variables, above,
334 for what they mean. */
336 qty
= (struct qty
*) xmalloc (max_qty
* sizeof (struct qty
));
338 = (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
339 qty_phys_num_copy_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
340 qty_phys_sugg
= (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
341 qty_phys_num_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
343 reg_qty
= (int *) xmalloc (max_regno
* sizeof (int));
344 reg_offset
= (char *) xmalloc (max_regno
* sizeof (char));
345 reg_next_in_qty
= (int *) xmalloc (max_regno
* sizeof (int));
347 /* Allocate the reg_renumber array. */
348 allocate_reg_info (max_regno
, FALSE
, TRUE
);
350 /* Determine which pseudo-registers can be allocated by local-alloc.
351 In general, these are the registers used only in a single block and
354 We need not be concerned with which block actually uses the register
355 since we will never see it outside that block. */
357 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
359 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1)
365 /* Force loop below to initialize entire quantity array. */
368 /* Allocate each block's local registers, block by block. */
370 for (b
= 0; b
< n_basic_blocks
; b
++)
372 /* NEXT_QTY indicates which elements of the `qty_...'
373 vectors might need to be initialized because they were used
374 for the previous block; it is set to the entire array before
375 block 0. Initialize those, with explicit loop if there are few,
376 else with bzero and bcopy. Do not initialize vectors that are
377 explicit set by `alloc_qty'. */
381 for (i
= 0; i
< next_qty
; i
++)
383 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
384 qty_phys_num_copy_sugg
[i
] = 0;
385 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
386 qty_phys_num_sugg
[i
] = 0;
391 #define CLEAR(vector) \
392 bzero ((char *) (vector), (sizeof (*(vector))) * next_qty);
394 CLEAR (qty_phys_copy_sugg
);
395 CLEAR (qty_phys_num_copy_sugg
);
396 CLEAR (qty_phys_sugg
);
397 CLEAR (qty_phys_num_sugg
);
406 free (qty_phys_copy_sugg
);
407 free (qty_phys_num_copy_sugg
);
408 free (qty_phys_sugg
);
409 free (qty_phys_num_sugg
);
413 free (reg_next_in_qty
);
415 return recorded_label_ref
;
418 /* Depth of loops we are in while in update_equiv_regs. */
419 static int loop_depth
;
421 /* Used for communication between the following two functions: contains
422 a MEM that we wish to ensure remains unchanged. */
423 static rtx equiv_mem
;
425 /* Set nonzero if EQUIV_MEM is modified. */
426 static int equiv_mem_modified
;
428 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
429 Called via note_stores. */
432 validate_equiv_mem_from_store (dest
, set
, data
)
434 rtx set ATTRIBUTE_UNUSED
;
435 void *data ATTRIBUTE_UNUSED
;
437 if ((GET_CODE (dest
) == REG
438 && reg_overlap_mentioned_p (dest
, equiv_mem
))
439 || (GET_CODE (dest
) == MEM
440 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
441 equiv_mem_modified
= 1;
444 /* Verify that no store between START and the death of REG invalidates
445 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
446 by storing into an overlapping memory location, or with a non-const
449 Return 1 if MEMREF remains valid. */
452 validate_equiv_mem (start
, reg
, memref
)
461 equiv_mem_modified
= 0;
463 /* If the memory reference has side effects or is volatile, it isn't a
464 valid equivalence. */
465 if (side_effects_p (memref
))
468 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
473 if (find_reg_note (insn
, REG_DEAD
, reg
))
476 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
477 && ! CONST_CALL_P (insn
))
480 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
482 /* If a register mentioned in MEMREF is modified via an
483 auto-increment, we lose the equivalence. Do the same if one
484 dies; although we could extend the life, it doesn't seem worth
487 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
488 if ((REG_NOTE_KIND (note
) == REG_INC
489 || REG_NOTE_KIND (note
) == REG_DEAD
)
490 && GET_CODE (XEXP (note
, 0)) == REG
491 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
498 /* TRUE if X uses any registers for which reg_equiv_replace is true. */
501 contains_replace_regs (x
, reg_equiv_replace
)
503 char *reg_equiv_replace
;
507 enum rtx_code code
= GET_CODE (x
);
523 return reg_equiv_replace
[REGNO (x
)];
529 fmt
= GET_RTX_FORMAT (code
);
530 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
534 if (contains_replace_regs (XEXP (x
, i
), reg_equiv_replace
))
538 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
539 if (contains_replace_regs (XVECEXP (x
, i
, j
), reg_equiv_replace
))
547 /* TRUE if X references a memory location that would be affected by a store
551 memref_referenced_p (memref
, x
)
557 enum rtx_code code
= GET_CODE (x
);
573 return (reg_equiv_replacement
[REGNO (x
)]
574 && memref_referenced_p (memref
,
575 reg_equiv_replacement
[REGNO (x
)]));
578 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
583 /* If we are setting a MEM, it doesn't count (its address does), but any
584 other SET_DEST that has a MEM in it is referencing the MEM. */
585 if (GET_CODE (SET_DEST (x
)) == MEM
)
587 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
590 else if (memref_referenced_p (memref
, SET_DEST (x
)))
593 return memref_referenced_p (memref
, SET_SRC (x
));
599 fmt
= GET_RTX_FORMAT (code
);
600 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
604 if (memref_referenced_p (memref
, XEXP (x
, i
)))
608 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
609 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
617 /* TRUE if some insn in the range (START, END] references a memory location
618 that would be affected by a store to MEMREF. */
621 memref_used_between_p (memref
, start
, end
)
628 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
629 insn
= NEXT_INSN (insn
))
630 if (INSN_P (insn
) && memref_referenced_p (memref
, PATTERN (insn
)))
636 /* Return nonzero if the rtx X is invariant over the current function. */
638 function_invariant_p (x
)
643 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
645 if (GET_CODE (x
) == PLUS
646 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
647 && CONSTANT_P (XEXP (x
, 1)))
652 /* Find registers that are equivalent to a single value throughout the
653 compilation (either because they can be referenced in memory or are set once
654 from a single constant). Lower their priority for a register.
656 If such a register is only referenced once, try substituting its value
657 into the using insn. If it succeeds, we can eliminate the register
663 /* Set when an attempt should be made to replace a register with the
664 associated reg_equiv_replacement entry at the end of this function. */
665 char *reg_equiv_replace
;
669 reg_equiv_replace
= (char *) xcalloc (max_regno
, sizeof *reg_equiv_replace
);
670 reg_equiv_init_insns
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
671 reg_equiv_replacement
= (rtx
*) xcalloc (max_regno
, sizeof (rtx
));
673 init_alias_analysis ();
677 /* Scan the insns and find which registers have equivalences. Do this
678 in a separate scan of the insns because (due to -fcse-follow-jumps)
679 a register can be set below its use. */
680 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
687 if (GET_CODE (insn
) == NOTE
)
689 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
691 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
698 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
699 if (REG_NOTE_KIND (note
) == REG_INC
)
700 no_equiv (XEXP (note
, 0), note
, NULL
);
702 set
= single_set (insn
);
704 /* If this insn contains more (or less) than a single SET,
705 only mark all destinations as having no known equivalence. */
708 note_stores (PATTERN (insn
), no_equiv
, NULL
);
711 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
715 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
717 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
719 note_stores (part
, no_equiv
, NULL
);
723 dest
= SET_DEST (set
);
726 /* If this sets a MEM to the contents of a REG that is only used
727 in a single basic block, see if the register is always equivalent
728 to that memory location and if moving the store from INSN to the
729 insn that set REG is safe. If so, put a REG_EQUIV note on the
732 Don't add a REG_EQUIV note if the insn already has one. The existing
733 REG_EQUIV is likely more useful than the one we are adding.
735 If one of the regs in the address is marked as reg_equiv_replace,
736 then we can't add this REG_EQUIV note. The reg_equiv_replace
737 optimization may move the set of this register immediately before
738 insn, which puts it after reg_equiv_init_insns[regno], and hence
739 the mention in the REG_EQUIV note would be to an uninitialized
741 /* ????? This test isn't good enough; we might see a MEM with a use of
742 a pseudo register before we see its setting insn that will cause
743 reg_equiv_replace for that pseudo to be set.
744 Equivalences to MEMs should be made in another pass, after the
745 reg_equiv_replace information has been gathered. */
747 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
748 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
749 && REG_BASIC_BLOCK (regno
) >= 0
750 && REG_N_SETS (regno
) == 1
751 && reg_equiv_init_insns
[regno
] != 0
752 && reg_equiv_init_insns
[regno
] != const0_rtx
753 && ! find_reg_note (XEXP (reg_equiv_init_insns
[regno
], 0),
755 && ! contains_replace_regs (XEXP (dest
, 0), reg_equiv_replace
))
757 rtx init_insn
= XEXP (reg_equiv_init_insns
[regno
], 0);
758 if (validate_equiv_mem (init_insn
, src
, dest
)
759 && ! memref_used_between_p (dest
, init_insn
, insn
))
760 REG_NOTES (init_insn
)
761 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
764 /* We only handle the case of a pseudo register being set
765 once, or always to the same value. */
766 /* ??? The mn10200 port breaks if we add equivalences for
767 values that need an ADDRESS_REGS register and set them equivalent
768 to a MEM of a pseudo. The actual problem is in the over-conservative
769 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
770 calculate_needs, but we traditionally work around this problem
771 here by rejecting equivalences when the destination is in a register
772 that's likely spilled. This is fragile, of course, since the
773 preferred class of a pseudo depends on all instructions that set
776 if (GET_CODE (dest
) != REG
777 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
778 || reg_equiv_init_insns
[regno
] == const0_rtx
779 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
780 && GET_CODE (src
) == MEM
))
782 /* This might be seting a SUBREG of a pseudo, a pseudo that is
783 also set somewhere else to a constant. */
784 note_stores (set
, no_equiv
, NULL
);
788 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
790 /* cse sometimes generates function invariants, but doesn't put a
791 REG_EQUAL note on the insn. Since this note would be redundant,
792 there's no point creating it earlier than here. */
793 if (! note
&& function_invariant_p (src
))
795 = note
= gen_rtx_EXPR_LIST (REG_EQUAL
, src
, REG_NOTES (insn
));
797 if (REG_N_SETS (regno
) != 1
799 || ! function_invariant_p (XEXP (note
, 0))
800 || (reg_equiv_replacement
[regno
]
801 && ! rtx_equal_p (XEXP (note
, 0),
802 reg_equiv_replacement
[regno
]))))
804 no_equiv (dest
, set
, NULL
);
807 /* Record this insn as initializing this register. */
808 reg_equiv_init_insns
[regno
]
809 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv_init_insns
[regno
]);
811 /* If this register is known to be equal to a constant, record that
812 it is always equivalent to the constant. */
813 if (note
&& function_invariant_p (XEXP (note
, 0)))
814 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
816 /* If this insn introduces a "constant" register, decrease the priority
817 of that register. Record this insn if the register is only used once
818 more and the equivalence value is the same as our source.
820 The latter condition is checked for two reasons: First, it is an
821 indication that it may be more efficient to actually emit the insn
822 as written (if no registers are available, reload will substitute
823 the equivalence). Secondly, it avoids problems with any registers
824 dying in this insn whose death notes would be missed.
826 If we don't have a REG_EQUIV note, see if this insn is loading
827 a register used only in one basic block from a MEM. If so, and the
828 MEM remains unchanged for the life of the register, add a REG_EQUIV
831 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
833 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
834 && GET_CODE (SET_SRC (set
)) == MEM
835 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
836 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
841 int regno
= REGNO (dest
);
843 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
844 We might end up substituting the LABEL_REF for uses of the
845 pseudo here or later. That kind of transformation may turn an
846 indirect jump into a direct jump, in which case we must rerun the
847 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
848 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
849 || (GET_CODE (XEXP (note
, 0)) == CONST
850 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
851 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
853 recorded_label_ref
= 1;
855 reg_equiv_replacement
[regno
] = XEXP (note
, 0);
857 /* Don't mess with things live during setjmp. */
858 if (REG_LIVE_LENGTH (regno
) >= 0)
860 /* Note that the statement below does not affect the priority
862 REG_LIVE_LENGTH (regno
) *= 2;
865 /* If the register is referenced exactly twice, meaning it is
866 set once and used once, indicate that the reference may be
867 replaced by the equivalence we computed above. If the
868 register is only used in one basic block, this can't succeed
869 or combine would have done it.
871 It would be nice to use "loop_depth * 2" in the compare
872 below. Unfortunately, LOOP_DEPTH need not be constant within
873 a basic block so this would be too complicated.
875 This case normally occurs when a parameter is read from
876 memory and then used exactly once, not in a loop. */
878 if (REG_N_REFS (regno
) == 2
879 && REG_BASIC_BLOCK (regno
) < 0
880 && rtx_equal_p (XEXP (note
, 0), SET_SRC (set
)))
881 reg_equiv_replace
[regno
] = 1;
886 /* Now scan all regs killed in an insn to see if any of them are
887 registers only used that once. If so, see if we can replace the
888 reference with the equivalent from. If we can, delete the
889 initializing reference and this register will go away. If we
890 can't replace the reference, and the instruction is not in a
891 loop, then move the register initialization just before the use,
892 so that they are in the same basic block. */
895 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
899 /* Keep track of which basic block we are in. */
900 if (block
+ 1 < n_basic_blocks
901 && BLOCK_HEAD (block
+ 1) == insn
)
906 if (GET_CODE (insn
) == NOTE
)
908 if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
910 else if (NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
921 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
923 if (REG_NOTE_KIND (link
) == REG_DEAD
924 /* Make sure this insn still refers to the register. */
925 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
927 int regno
= REGNO (XEXP (link
, 0));
930 if (! reg_equiv_replace
[regno
])
933 /* reg_equiv_replace[REGNO] gets set only when
934 REG_N_REFS[REGNO] is 2, i.e. the register is set
935 once and used once. (If it were only set, but not used,
936 flow would have deleted the setting insns.) Hence
937 there can only be one insn in reg_equiv_init_insns. */
938 equiv_insn
= XEXP (reg_equiv_init_insns
[regno
], 0);
940 if (validate_replace_rtx (regno_reg_rtx
[regno
],
941 reg_equiv_replacement
[regno
], insn
))
943 remove_death (regno
, insn
);
944 REG_N_REFS (regno
) = 0;
945 PUT_CODE (equiv_insn
, NOTE
);
946 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
947 NOTE_SOURCE_FILE (equiv_insn
) = 0;
949 /* If we aren't in a loop, and there are no calls in
950 INSN or in the initialization of the register, then
951 move the initialization of the register to just
952 before INSN. Update the flow information. */
954 && GET_CODE (equiv_insn
) == INSN
955 && GET_CODE (insn
) == INSN
956 && REG_BASIC_BLOCK (regno
) < 0)
960 emit_insn_before (copy_rtx (PATTERN (equiv_insn
)), insn
);
961 REG_NOTES (PREV_INSN (insn
)) = REG_NOTES (equiv_insn
);
962 REG_NOTES (equiv_insn
) = 0;
964 PUT_CODE (equiv_insn
, NOTE
);
965 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
966 NOTE_SOURCE_FILE (equiv_insn
) = 0;
969 REG_BASIC_BLOCK (regno
) = 0;
971 REG_BASIC_BLOCK (regno
) = block
;
972 REG_N_CALLS_CROSSED (regno
) = 0;
973 REG_LIVE_LENGTH (regno
) = 2;
975 if (block
>= 0 && insn
== BLOCK_HEAD (block
))
976 BLOCK_HEAD (block
) = PREV_INSN (insn
);
978 for (l
= 0; l
< n_basic_blocks
; l
++)
979 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
,
987 end_alias_analysis ();
988 free (reg_equiv_replace
);
989 free (reg_equiv_init_insns
);
990 free (reg_equiv_replacement
);
993 /* Mark REG as having no known equivalence.
994 Some instructions might have been proceessed before and furnished
995 with REG_EQUIV notes for this register; these notes will have to be
997 STORE is the piece of RTL that does the non-constant / conflicting
998 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
999 but needs to be there because this function is called from note_stores. */
1001 no_equiv (reg
, store
, data
)
1002 rtx reg
, store ATTRIBUTE_UNUSED
;
1003 void *data ATTRIBUTE_UNUSED
;
1008 if (GET_CODE (reg
) != REG
)
1010 regno
= REGNO (reg
);
1011 list
= reg_equiv_init_insns
[regno
];
1012 if (list
== const0_rtx
)
1014 for (; list
; list
= XEXP (list
, 1))
1016 rtx insn
= XEXP (list
, 0);
1017 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1019 reg_equiv_init_insns
[regno
] = const0_rtx
;
1020 reg_equiv_replacement
[regno
] = NULL_RTX
;
1023 /* Allocate hard regs to the pseudo regs used only within block number B.
1024 Only the pseudos that die but once can be handled. */
1033 int insn_number
= 0;
1035 int max_uid
= get_max_uid ();
1037 int no_conflict_combined_regno
= -1;
1039 /* Count the instructions in the basic block. */
1041 insn
= BLOCK_END (b
);
1044 if (GET_CODE (insn
) != NOTE
)
1045 if (++insn_count
> max_uid
)
1047 if (insn
== BLOCK_HEAD (b
))
1049 insn
= PREV_INSN (insn
);
1052 /* +2 to leave room for a post_mark_life at the last insn and for
1053 the birth of a CLOBBER in the first insn. */
1054 regs_live_at
= (HARD_REG_SET
*) xcalloc ((2 * insn_count
+ 2),
1055 sizeof (HARD_REG_SET
));
1057 /* Initialize table of hardware registers currently live. */
1059 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1061 /* This loop scans the instructions of the basic block
1062 and assigns quantities to registers.
1063 It computes which registers to tie. */
1065 insn
= BLOCK_HEAD (b
);
1068 if (GET_CODE (insn
) != NOTE
)
1073 register rtx link
, set
;
1074 register int win
= 0;
1075 register rtx r0
, r1
= NULL_RTX
;
1076 int combined_regno
= -1;
1079 this_insn_number
= insn_number
;
1082 extract_insn (insn
);
1083 which_alternative
= -1;
1085 /* Is this insn suitable for tying two registers?
1086 If so, try doing that.
1087 Suitable insns are those with at least two operands and where
1088 operand 0 is an output that is a register that is not
1091 We can tie operand 0 with some operand that dies in this insn.
1092 First look for operands that are required to be in the same
1093 register as operand 0. If we find such, only try tying that
1094 operand or one that can be put into that operand if the
1095 operation is commutative. If we don't find an operand
1096 that is required to be in the same register as operand 0,
1097 we can tie with any operand.
1099 Subregs in place of regs are also ok.
1101 If tying is done, WIN is set nonzero. */
1104 && recog_data
.n_operands
> 1
1105 && recog_data
.constraints
[0][0] == '='
1106 && recog_data
.constraints
[0][1] != '&')
1108 /* If non-negative, is an operand that must match operand 0. */
1109 int must_match_0
= -1;
1110 /* Counts number of alternatives that require a match with
1112 int n_matching_alts
= 0;
1114 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1116 const char *p
= recog_data
.constraints
[i
];
1117 int this_match
= (requires_inout (p
));
1119 n_matching_alts
+= this_match
;
1120 if (this_match
== recog_data
.n_alternatives
)
1124 r0
= recog_data
.operand
[0];
1125 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1127 /* Skip this operand if we found an operand that
1128 must match operand 0 and this operand isn't it
1129 and can't be made to be it by commutativity. */
1131 if (must_match_0
>= 0 && i
!= must_match_0
1132 && ! (i
== must_match_0
+ 1
1133 && recog_data
.constraints
[i
-1][0] == '%')
1134 && ! (i
== must_match_0
- 1
1135 && recog_data
.constraints
[i
][0] == '%'))
1138 /* Likewise if each alternative has some operand that
1139 must match operand zero. In that case, skip any
1140 operand that doesn't list operand 0 since we know that
1141 the operand always conflicts with operand 0. We
1142 ignore commutatity in this case to keep things simple. */
1143 if (n_matching_alts
== recog_data
.n_alternatives
1144 && 0 == requires_inout (recog_data
.constraints
[i
]))
1147 r1
= recog_data
.operand
[i
];
1149 /* If the operand is an address, find a register in it.
1150 There may be more than one register, but we only try one
1152 if (recog_data
.constraints
[i
][0] == 'p')
1153 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1156 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1158 /* We have two priorities for hard register preferences.
1159 If we have a move insn or an insn whose first input
1160 can only be in the same register as the output, give
1161 priority to an equivalence found from that insn. */
1163 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1165 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1166 win
= combine_regs (r1
, r0
, may_save_copy
,
1167 insn_number
, insn
, 0);
1174 /* Recognize an insn sequence with an ultimate result
1175 which can safely overlap one of the inputs.
1176 The sequence begins with a CLOBBER of its result,
1177 and ends with an insn that copies the result to itself
1178 and has a REG_EQUAL note for an equivalent formula.
1179 That note indicates what the inputs are.
1180 The result and the input can overlap if each insn in
1181 the sequence either doesn't mention the input
1182 or has a REG_NO_CONFLICT note to inhibit the conflict.
1184 We do the combining test at the CLOBBER so that the
1185 destination register won't have had a quantity number
1186 assigned, since that would prevent combining. */
1189 && GET_CODE (PATTERN (insn
)) == CLOBBER
1190 && (r0
= XEXP (PATTERN (insn
), 0),
1191 GET_CODE (r0
) == REG
)
1192 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1193 && XEXP (link
, 0) != 0
1194 && GET_CODE (XEXP (link
, 0)) == INSN
1195 && (set
= single_set (XEXP (link
, 0))) != 0
1196 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1197 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1200 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1201 /* Check that we have such a sequence. */
1202 && no_conflict_p (insn
, r0
, r1
))
1203 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1204 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1205 && (r1
= XEXP (XEXP (note
, 0), 0),
1206 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1207 && no_conflict_p (insn
, r0
, r1
))
1208 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1210 /* Here we care if the operation to be computed is
1212 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1213 || GET_CODE (XEXP (note
, 0)) == NE
1214 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1215 && (r1
= XEXP (XEXP (note
, 0), 1),
1216 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1217 && no_conflict_p (insn
, r0
, r1
))
1218 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1220 /* If we did combine something, show the register number
1221 in question so that we know to ignore its death. */
1223 no_conflict_combined_regno
= REGNO (r1
);
1226 /* If registers were just tied, set COMBINED_REGNO
1227 to the number of the register used in this insn
1228 that was tied to the register set in this insn.
1229 This register's qty should not be "killed". */
1233 while (GET_CODE (r1
) == SUBREG
)
1234 r1
= SUBREG_REG (r1
);
1235 combined_regno
= REGNO (r1
);
1238 /* Mark the death of everything that dies in this instruction,
1239 except for anything that was just combined. */
1241 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1242 if (REG_NOTE_KIND (link
) == REG_DEAD
1243 && GET_CODE (XEXP (link
, 0)) == REG
1244 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1245 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1246 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1248 wipe_dead_reg (XEXP (link
, 0), 0);
1250 /* Allocate qty numbers for all registers local to this block
1251 that are born (set) in this instruction.
1252 A pseudo that already has a qty is not changed. */
1254 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1256 /* If anything is set in this insn and then unused, mark it as dying
1257 after this insn, so it will conflict with our outputs. This
1258 can't match with something that combined, and it doesn't matter
1259 if it did. Do this after the calls to reg_is_set since these
1260 die after, not during, the current insn. */
1262 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1263 if (REG_NOTE_KIND (link
) == REG_UNUSED
1264 && GET_CODE (XEXP (link
, 0)) == REG
)
1265 wipe_dead_reg (XEXP (link
, 0), 1);
1267 /* If this is an insn that has a REG_RETVAL note pointing at a
1268 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1269 block, so clear any register number that combined within it. */
1270 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1271 && GET_CODE (XEXP (note
, 0)) == INSN
1272 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1273 no_conflict_combined_regno
= -1;
1276 /* Set the registers live after INSN_NUMBER. Note that we never
1277 record the registers live before the block's first insn, since no
1278 pseudos we care about are live before that insn. */
1280 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1281 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1283 if (insn
== BLOCK_END (b
))
1286 insn
= NEXT_INSN (insn
);
1289 /* Now every register that is local to this basic block
1290 should have been given a quantity, or else -1 meaning ignore it.
1291 Every quantity should have a known birth and death.
1293 Order the qtys so we assign them registers in order of the
1294 number of suggested registers they need so we allocate those with
1295 the most restrictive needs first. */
1297 qty_order
= (int *) xmalloc (next_qty
* sizeof (int));
1298 for (i
= 0; i
< next_qty
; i
++)
1301 #define EXCHANGE(I1, I2) \
1302 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1307 /* Make qty_order[2] be the one to allocate last. */
1308 if (qty_sugg_compare (0, 1) > 0)
1310 if (qty_sugg_compare (1, 2) > 0)
1313 /* ... Fall through ... */
1315 /* Put the best one to allocate in qty_order[0]. */
1316 if (qty_sugg_compare (0, 1) > 0)
1319 /* ... Fall through ... */
1323 /* Nothing to do here. */
1327 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1330 /* Try to put each quantity in a suggested physical register, if it has one.
1331 This may cause registers to be allocated that otherwise wouldn't be, but
1332 this seems acceptable in local allocation (unlike global allocation). */
1333 for (i
= 0; i
< next_qty
; i
++)
1336 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1337 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1338 0, 1, qty
[q
].birth
, qty
[q
].death
);
1340 qty
[q
].phys_reg
= -1;
1343 /* Order the qtys so we assign them registers in order of
1344 decreasing length of life. Normally call qsort, but if we
1345 have only a very small number of quantities, sort them ourselves. */
1347 for (i
= 0; i
< next_qty
; i
++)
1350 #define EXCHANGE(I1, I2) \
1351 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1356 /* Make qty_order[2] be the one to allocate last. */
1357 if (qty_compare (0, 1) > 0)
1359 if (qty_compare (1, 2) > 0)
1362 /* ... Fall through ... */
1364 /* Put the best one to allocate in qty_order[0]. */
1365 if (qty_compare (0, 1) > 0)
1368 /* ... Fall through ... */
1372 /* Nothing to do here. */
1376 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1379 /* Now for each qty that is not a hardware register,
1380 look for a hardware register to put it in.
1381 First try the register class that is cheapest for this qty,
1382 if there is more than one class. */
1384 for (i
= 0; i
< next_qty
; i
++)
1387 if (qty
[q
].phys_reg
< 0)
1389 #ifdef INSN_SCHEDULING
1390 /* These values represent the adjusted lifetime of a qty so
1391 that it conflicts with qtys which appear near the start/end
1392 of this qty's lifetime.
1394 The purpose behind extending the lifetime of this qty is to
1395 discourage the register allocator from creating false
1398 The adjustment value is choosen to indicate that this qty
1399 conflicts with all the qtys in the instructions immediately
1400 before and after the lifetime of this qty.
1402 Experiments have shown that higher values tend to hurt
1403 overall code performance.
1405 If allocation using the extended lifetime fails we will try
1406 again with the qty's unadjusted lifetime. */
1407 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1408 int fake_death
= MIN (insn_number
* 2 + 1,
1409 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1412 if (N_REG_CLASSES
> 1)
1414 #ifdef INSN_SCHEDULING
1415 /* We try to avoid using hard registers allocated to qtys which
1416 are born immediately after this qty or die immediately before
1419 This optimization is only appropriate when we will run
1420 a scheduling pass after reload and we are not optimizing
1422 if (flag_schedule_insns_after_reload
1424 && !SMALL_REGISTER_CLASSES
)
1426 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1427 qty
[q
].mode
, q
, 0, 0,
1428 fake_birth
, fake_death
);
1429 if (qty
[q
].phys_reg
>= 0)
1433 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1434 qty
[q
].mode
, q
, 0, 0,
1435 qty
[q
].birth
, qty
[q
].death
);
1436 if (qty
[q
].phys_reg
>= 0)
1440 #ifdef INSN_SCHEDULING
1441 /* Similarly, avoid false dependencies. */
1442 if (flag_schedule_insns_after_reload
1444 && !SMALL_REGISTER_CLASSES
1445 && qty
[q
].alternate_class
!= NO_REGS
)
1446 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1447 qty
[q
].mode
, q
, 0, 0,
1448 fake_birth
, fake_death
);
1450 if (qty
[q
].alternate_class
!= NO_REGS
)
1451 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1452 qty
[q
].mode
, q
, 0, 0,
1453 qty
[q
].birth
, qty
[q
].death
);
1457 /* Now propagate the register assignments
1458 to the pseudo regs belonging to the qtys. */
1460 for (q
= 0; q
< next_qty
; q
++)
1461 if (qty
[q
].phys_reg
>= 0)
1463 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1464 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1468 free (regs_live_at
);
1472 /* Compare two quantities' priority for getting real registers.
1473 We give shorter-lived quantities higher priority.
1474 Quantities with more references are also preferred, as are quantities that
1475 require multiple registers. This is the identical prioritization as
1476 done by global-alloc.
1478 We used to give preference to registers with *longer* lives, but using
1479 the same algorithm in both local- and global-alloc can speed up execution
1480 of some programs by as much as a factor of three! */
1482 /* Note that the quotient will never be bigger than
1483 the value of floor_log2 times the maximum number of
1484 times a register can occur in one insn (surely less than 100).
1485 Multiplying this by 10000 can't overflow.
1486 QTY_CMP_PRI is also used by qty_sugg_compare. */
1488 #define QTY_CMP_PRI(q) \
1489 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].n_refs * qty[q].size) \
1490 / (qty[q].death - qty[q].birth)) * 10000))
1493 qty_compare (q1
, q2
)
1496 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1500 qty_compare_1 (q1p
, q2p
)
1504 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1505 register int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1510 /* If qtys are equally good, sort by qty number,
1511 so that the results of qsort leave nothing to chance. */
1515 /* Compare two quantities' priority for getting real registers. This version
1516 is called for quantities that have suggested hard registers. First priority
1517 goes to quantities that have copy preferences, then to those that have
1518 normal preferences. Within those groups, quantities with the lower
1519 number of preferences have the highest priority. Of those, we use the same
1520 algorithm as above. */
1522 #define QTY_CMP_SUGG(q) \
1523 (qty_phys_num_copy_sugg[q] \
1524 ? qty_phys_num_copy_sugg[q] \
1525 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1528 qty_sugg_compare (q1
, q2
)
1531 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1536 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1540 qty_sugg_compare_1 (q1p
, q2p
)
1544 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1545 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1550 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1554 /* If qtys are equally good, sort by qty number,
1555 so that the results of qsort leave nothing to chance. */
1562 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1563 Returns 1 if have done so, or 0 if cannot.
1565 Combining registers means marking them as having the same quantity
1566 and adjusting the offsets within the quantity if either of
1569 We don't actually combine a hard reg with a pseudo; instead
1570 we just record the hard reg as the suggestion for the pseudo's quantity.
1571 If we really combined them, we could lose if the pseudo lives
1572 across an insn that clobbers the hard reg (eg, movstr).
1574 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1575 there is no REG_DEAD note on INSN. This occurs during the processing
1576 of REG_NO_CONFLICT blocks.
1578 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1579 SETREG or if the input and output must share a register.
1580 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1582 There are elaborate checks for the validity of combining. */
1585 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1586 rtx usedreg
, setreg
;
1592 register int ureg
, sreg
;
1593 register int offset
= 0;
1597 /* Determine the numbers and sizes of registers being used. If a subreg
1598 is present that does not change the entire register, don't consider
1599 this a copy insn. */
1601 while (GET_CODE (usedreg
) == SUBREG
)
1603 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg
))) > UNITS_PER_WORD
)
1605 offset
+= SUBREG_WORD (usedreg
);
1606 usedreg
= SUBREG_REG (usedreg
);
1608 if (GET_CODE (usedreg
) != REG
)
1610 ureg
= REGNO (usedreg
);
1611 usize
= REG_SIZE (usedreg
);
1613 while (GET_CODE (setreg
) == SUBREG
)
1615 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg
))) > UNITS_PER_WORD
)
1617 offset
-= SUBREG_WORD (setreg
);
1618 setreg
= SUBREG_REG (setreg
);
1620 if (GET_CODE (setreg
) != REG
)
1622 sreg
= REGNO (setreg
);
1623 ssize
= REG_SIZE (setreg
);
1625 /* If UREG is a pseudo-register that hasn't already been assigned a
1626 quantity number, it means that it is not local to this block or dies
1627 more than once. In either event, we can't do anything with it. */
1628 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1629 /* Do not combine registers unless one fits within the other. */
1630 || (offset
> 0 && usize
+ offset
> ssize
)
1631 || (offset
< 0 && usize
+ offset
< ssize
)
1632 /* Do not combine with a smaller already-assigned object
1633 if that smaller object is already combined with something bigger. */
1634 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1635 && usize
< qty
[reg_qty
[ureg
]].size
)
1636 /* Can't combine if SREG is not a register we can allocate. */
1637 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1638 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1639 These have already been taken care of. This probably wouldn't
1640 combine anyway, but don't take any chances. */
1641 || (ureg
>= FIRST_PSEUDO_REGISTER
1642 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1643 /* Don't tie something to itself. In most cases it would make no
1644 difference, but it would screw up if the reg being tied to itself
1645 also dies in this insn. */
1647 /* Don't try to connect two different hardware registers. */
1648 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1649 /* Don't connect two different machine modes if they have different
1650 implications as to which registers may be used. */
1651 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1654 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1655 qty_phys_sugg for the pseudo instead of tying them.
1657 Return "failure" so that the lifespan of UREG is terminated here;
1658 that way the two lifespans will be disjoint and nothing will prevent
1659 the pseudo reg from being given this hard reg. */
1661 if (ureg
< FIRST_PSEUDO_REGISTER
)
1663 /* Allocate a quantity number so we have a place to put our
1665 if (reg_qty
[sreg
] == -2)
1666 reg_is_born (setreg
, 2 * insn_number
);
1668 if (reg_qty
[sreg
] >= 0)
1671 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1673 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1674 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1676 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1678 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1679 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1685 /* Similarly for SREG a hard register and UREG a pseudo register. */
1687 if (sreg
< FIRST_PSEUDO_REGISTER
)
1690 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1692 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1693 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1695 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1697 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1698 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1703 /* At this point we know that SREG and UREG are both pseudos.
1704 Do nothing if SREG already has a quantity or is a register that we
1706 if (reg_qty
[sreg
] >= -1
1707 /* If we are not going to let any regs live across calls,
1708 don't tie a call-crossing reg to a non-call-crossing reg. */
1709 || (current_function_has_nonlocal_label
1710 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1711 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1714 /* We don't already know about SREG, so tie it to UREG
1715 if this is the last use of UREG, provided the classes they want
1718 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1719 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1721 /* Add SREG to UREG's quantity. */
1722 sqty
= reg_qty
[ureg
];
1723 reg_qty
[sreg
] = sqty
;
1724 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1725 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1726 qty
[sqty
].first_reg
= sreg
;
1728 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1729 update_qty_class (sqty
, sreg
);
1731 /* Update info about quantity SQTY. */
1732 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1733 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1738 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1739 reg_offset
[i
] -= offset
;
1741 qty
[sqty
].size
= ssize
;
1742 qty
[sqty
].mode
= GET_MODE (setreg
);
1751 /* Return 1 if the preferred class of REG allows it to be tied
1752 to a quantity or register whose class is CLASS.
1753 True if REG's reg class either contains or is contained in CLASS. */
1756 reg_meets_class_p (reg
, class)
1758 enum reg_class
class;
1760 register enum reg_class rclass
= reg_preferred_class (reg
);
1761 return (reg_class_subset_p (rclass
, class)
1762 || reg_class_subset_p (class, rclass
));
1765 /* Update the class of QTYNO assuming that REG is being tied to it. */
1768 update_qty_class (qtyno
, reg
)
1772 enum reg_class rclass
= reg_preferred_class (reg
);
1773 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
1774 qty
[qtyno
].min_class
= rclass
;
1776 rclass
= reg_alternate_class (reg
);
1777 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
1778 qty
[qtyno
].alternate_class
= rclass
;
1780 if (REG_CHANGES_MODE (reg
))
1781 qty
[qtyno
].changes_mode
= 1;
1784 /* Handle something which alters the value of an rtx REG.
1786 REG is whatever is set or clobbered. SETTER is the rtx that
1787 is modifying the register.
1789 If it is not really a register, we do nothing.
1790 The file-global variables `this_insn' and `this_insn_number'
1791 carry info from `block_alloc'. */
1794 reg_is_set (reg
, setter
, data
)
1797 void *data ATTRIBUTE_UNUSED
;
1799 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
1800 a hard register. These may actually not exist any more. */
1802 if (GET_CODE (reg
) != SUBREG
1803 && GET_CODE (reg
) != REG
)
1806 /* Mark this register as being born. If it is used in a CLOBBER, mark
1807 it as being born halfway between the previous insn and this insn so that
1808 it conflicts with our inputs but not the outputs of the previous insn. */
1810 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
1813 /* Handle beginning of the life of register REG.
1814 BIRTH is the index at which this is happening. */
1817 reg_is_born (reg
, birth
)
1823 if (GET_CODE (reg
) == SUBREG
)
1824 regno
= REGNO (SUBREG_REG (reg
)) + SUBREG_WORD (reg
);
1826 regno
= REGNO (reg
);
1828 if (regno
< FIRST_PSEUDO_REGISTER
)
1830 mark_life (regno
, GET_MODE (reg
), 1);
1832 /* If the register was to have been born earlier that the present
1833 insn, mark it as live where it is actually born. */
1834 if (birth
< 2 * this_insn_number
)
1835 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
1839 if (reg_qty
[regno
] == -2)
1840 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
1842 /* If this register has a quantity number, show that it isn't dead. */
1843 if (reg_qty
[regno
] >= 0)
1844 qty
[reg_qty
[regno
]].death
= -1;
1848 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
1849 REG is an output that is dying (i.e., it is never used), otherwise it
1850 is an input (the normal case).
1851 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
1854 wipe_dead_reg (reg
, output_p
)
1858 register int regno
= REGNO (reg
);
1860 /* If this insn has multiple results,
1861 and the dead reg is used in one of the results,
1862 extend its life to after this insn,
1863 so it won't get allocated together with any other result of this insn.
1865 It is unsafe to use !single_set here since it will ignore an unused
1866 output. Just because an output is unused does not mean the compiler
1867 can assume the side effect will not occur. Consider if REG appears
1868 in the address of an output and we reload the output. If we allocate
1869 REG to the same hard register as an unused output we could set the hard
1870 register before the output reload insn. */
1871 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
1872 && multiple_sets (this_insn
))
1875 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
1877 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
1878 if (GET_CODE (set
) == SET
1879 && GET_CODE (SET_DEST (set
)) != REG
1880 && !rtx_equal_p (reg
, SET_DEST (set
))
1881 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1886 /* If this register is used in an auto-increment address, then extend its
1887 life to after this insn, so that it won't get allocated together with
1888 the result of this insn. */
1889 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
1892 if (regno
< FIRST_PSEUDO_REGISTER
)
1894 mark_life (regno
, GET_MODE (reg
), 0);
1896 /* If a hard register is dying as an output, mark it as in use at
1897 the beginning of this insn (the above statement would cause this
1900 post_mark_life (regno
, GET_MODE (reg
), 1,
1901 2 * this_insn_number
, 2 * this_insn_number
+ 1);
1904 else if (reg_qty
[regno
] >= 0)
1905 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
1908 /* Find a block of SIZE words of hard regs in reg_class CLASS
1909 that can hold something of machine-mode MODE
1910 (but actually we test only the first of the block for holding MODE)
1911 and still free between insn BORN_INDEX and insn DEAD_INDEX,
1912 and return the number of the first of them.
1913 Return -1 if such a block cannot be found.
1914 If QTYNO crosses calls, insist on a register preserved by calls,
1915 unless ACCEPT_CALL_CLOBBERED is nonzero.
1917 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
1918 register is available. If not, return -1. */
1921 find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, just_try_suggested
,
1922 born_index
, dead_index
)
1923 enum reg_class
class;
1924 enum machine_mode mode
;
1926 int accept_call_clobbered
;
1927 int just_try_suggested
;
1928 int born_index
, dead_index
;
1930 register int i
, ins
;
1932 /* Declare it register if it's a scalar. */
1935 HARD_REG_SET used
, first_used
;
1936 #ifdef ELIMINABLE_REGS
1937 static struct {int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
1940 /* Validate our parameters. */
1941 if (born_index
< 0 || born_index
> dead_index
)
1944 /* Don't let a pseudo live in a reg across a function call
1945 if we might get a nonlocal goto. */
1946 if (current_function_has_nonlocal_label
1947 && qty
[qtyno
].n_calls_crossed
> 0)
1950 if (accept_call_clobbered
)
1951 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
1952 else if (qty
[qtyno
].n_calls_crossed
== 0)
1953 COPY_HARD_REG_SET (used
, fixed_reg_set
);
1955 COPY_HARD_REG_SET (used
, call_used_reg_set
);
1957 if (accept_call_clobbered
)
1958 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
1960 for (ins
= born_index
; ins
< dead_index
; ins
++)
1961 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
1963 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
1965 /* Don't use the frame pointer reg in local-alloc even if
1966 we may omit the frame pointer, because if we do that and then we
1967 need a frame pointer, reload won't know how to move the pseudo
1968 to another hard reg. It can move only regs made by global-alloc.
1970 This is true of any register that can be eliminated. */
1971 #ifdef ELIMINABLE_REGS
1972 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
1973 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
1974 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
1975 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
1976 that it might be eliminated into. */
1977 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
1980 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
1983 #ifdef CLASS_CANNOT_CHANGE_MODE
1984 if (qty
[qtyno
].changes_mode
)
1985 IOR_HARD_REG_SET (used
,
1986 reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
]);
1989 /* Normally, the registers that can be used for the first register in
1990 a multi-register quantity are the same as those that can be used for
1991 subsequent registers. However, if just trying suggested registers,
1992 restrict our consideration to them. If there are copy-suggested
1993 register, try them. Otherwise, try the arithmetic-suggested
1995 COPY_HARD_REG_SET (first_used
, used
);
1997 if (just_try_suggested
)
1999 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2000 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2002 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2005 /* If all registers are excluded, we can't do anything. */
2006 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2008 /* If at least one would be suitable, test each hard reg. */
2010 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2012 #ifdef REG_ALLOC_ORDER
2013 int regno
= reg_alloc_order
[i
];
2017 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2018 && HARD_REGNO_MODE_OK (regno
, mode
)
2019 && (qty
[qtyno
].n_calls_crossed
== 0
2020 || accept_call_clobbered
2021 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2024 register int size1
= HARD_REGNO_NREGS (regno
, mode
);
2025 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2028 /* Mark that this register is in use between its birth and death
2030 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2033 #ifndef REG_ALLOC_ORDER
2034 /* Skip starting points we know will lose. */
2041 /* If we are just trying suggested register, we have just tried copy-
2042 suggested registers, and there are arithmetic-suggested registers,
2045 /* If it would be profitable to allocate a call-clobbered register
2046 and save and restore it around calls, do that. */
2047 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2048 && qty_phys_num_sugg
[qtyno
] != 0)
2050 /* Don't try the copy-suggested regs again. */
2051 qty_phys_num_copy_sugg
[qtyno
] = 0;
2052 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2053 born_index
, dead_index
);
2056 /* We need not check to see if the current function has nonlocal
2057 labels because we don't put any pseudos that are live over calls in
2058 registers in that case. */
2060 if (! accept_call_clobbered
2061 && flag_caller_saves
2062 && ! just_try_suggested
2063 && qty
[qtyno
].n_calls_crossed
!= 0
2064 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2065 qty
[qtyno
].n_calls_crossed
))
2067 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2069 caller_save_needed
= 1;
2075 /* Mark that REGNO with machine-mode MODE is live starting from the current
2076 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2080 mark_life (regno
, mode
, life
)
2082 enum machine_mode mode
;
2085 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2088 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2091 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2094 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2095 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2096 to insn number DEATH (exclusive). */
2099 post_mark_life (regno
, mode
, life
, birth
, death
)
2101 enum machine_mode mode
;
2102 int life
, birth
, death
;
2104 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2106 /* Declare it register if it's a scalar. */
2109 HARD_REG_SET this_reg
;
2111 CLEAR_HARD_REG_SET (this_reg
);
2113 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2116 while (birth
< death
)
2118 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2122 while (birth
< death
)
2124 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2129 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2130 is the register being clobbered, and R1 is a register being used in
2131 the equivalent expression.
2133 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2134 in which it is used, return 1.
2136 Otherwise, return 0. */
2139 no_conflict_p (insn
, r0
, r1
)
2140 rtx insn
, r0 ATTRIBUTE_UNUSED
, r1
;
2143 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2146 /* If R1 is a hard register, return 0 since we handle this case
2147 when we scan the insns that actually use it. */
2150 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2151 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2152 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2155 last
= XEXP (note
, 0);
2157 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2160 if (find_reg_note (p
, REG_DEAD
, r1
))
2163 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2164 some earlier optimization pass has inserted instructions into
2165 the sequence, and it is not safe to perform this optimization.
2166 Note that emit_no_conflict_block always ensures that this is
2167 true when these sequences are created. */
2168 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2175 /* Return the number of alternatives for which the constraint string P
2176 indicates that the operand must be equal to operand 0 and that no register
2185 int reg_allowed
= 0;
2186 int num_matching_alts
= 0;
2191 case '=': case '+': case '?':
2192 case '#': case '&': case '!':
2194 case '1': case '2': case '3': case '4': case '5':
2195 case '6': case '7': case '8': case '9':
2196 case 'm': case '<': case '>': case 'V': case 'o':
2197 case 'E': case 'F': case 'G': case 'H':
2198 case 's': case 'i': case 'n':
2199 case 'I': case 'J': case 'K': case 'L':
2200 case 'M': case 'N': case 'O': case 'P':
2202 /* These don't say anything we care about. */
2206 if (found_zero
&& ! reg_allowed
)
2207 num_matching_alts
++;
2209 found_zero
= reg_allowed
= 0;
2217 if (REG_CLASS_FROM_LETTER (c
) == NO_REGS
)
2226 if (found_zero
&& ! reg_allowed
)
2227 num_matching_alts
++;
2229 return num_matching_alts
;
2233 dump_local_alloc (file
)
2237 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2238 if (reg_renumber
[i
] != -1)
2239 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);