1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg} \
25 %{a:/usr/lib/bb_link.o}"
27 /* Provide required defaults for linker -e and -d switches. */
30 "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
32 /* Special flags to the Sun-4 assembler when using pipe for input. */
34 #define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k}"
36 /* Define macros to distinguish architectures. */
37 #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__}"
39 /* Prevent error on `-sun4' and `-target sun4' options. */
40 /* This used to translate -dalign to -malign, but that is no good
41 because it can't turn off the usual meaning of making debugging dumps. */
43 #define CC1_SPEC "%{sun4:} %{target:}"
45 /* Sparc ABI says that long double is 4 words. */
47 #define LONG_DOUBLE_TYPE_SIZE 128
49 #define PTRDIFF_TYPE "int"
50 #define SIZE_TYPE "int"
51 #define WCHAR_TYPE "short unsigned int"
52 #define WCHAR_TYPE_SIZE 16
54 /* Omit frame pointer at high optimization levels. */
56 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
60 flag_omit_frame_pointer = 1; \
64 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
65 code into the rtl. Also, if we are profiling, we cannot eliminate
66 the frame pointer (because the return address will get smashed). */
68 #define OVERRIDE_OPTIONS \
69 do { if (profile_flag || profile_block_flag) \
70 flag_omit_frame_pointer = 0, flag_pic = 0; } while (0)
72 /* These compiler options take an argument. We ignore -target for now. */
74 #define WORD_SWITCH_TAKES_ARG(STR) \
75 (!strcmp (STR, "Tdata") || !strcmp (STR, "Ttext") \
76 || !strcmp (STR, "Tbss") || !strcmp (STR, "include") \
77 || !strcmp (STR, "imacros") || !strcmp (STR, "target") \
78 || !strcmp (STR, "assert") || !strcmp (STR, "aux-info"))
80 /* Names to predefine in the preprocessor for this target machine. */
82 /* The GCC_NEW_VARARGS macro is so that old versions of gcc can compile
83 new versions, which have an incompatible va-sparc.h file. This matters
84 because gcc does "gvarargs.h" instead of <varargs.h>, and thus gets the
85 wrong varargs file when it is compiled with a different version of gcc. */
87 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__"
89 /* Print subsidiary information on the compiler version in use. */
91 #define TARGET_VERSION fprintf (stderr, " (sparc)");
93 /* Generate DBX debugging information. */
95 #define DBX_DEBUGGING_INFO
97 /* Run-time compilation parameters selecting different hardware subsets. */
99 extern int target_flags
;
101 /* Nonzero if we should generate code to use the fpu. */
102 #define TARGET_FPU (target_flags & 1)
104 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
105 use fast return insns, but lose some generality. */
106 #define TARGET_EPILOGUE (target_flags & 2)
108 /* Nonzero if we should assume that double pointers might be unaligned.
109 This can happen when linking gcc compiled code with other compilers,
110 because the ABI only guarantees 4 byte alignment. */
111 #define TARGET_UNALIGNED_DOUBLES (target_flags & 4)
113 /* Nonzero means that we should generate code for a v8 sparc. */
114 #define TARGET_V8 (target_flags & 64)
116 /* Nonzero means that we should generate code for a sparclite. */
117 #define TARGET_SPARCLITE (target_flags & 128)
119 /* Nonzero means that we should generate code using a flat register window
120 model, i.e. no save/restore instructions are generated, in the most
121 efficient manner. This code is not compatible with normal sparc code. */
122 /* This is not a user selectable option yet, because it requires changes
123 that are not yet switchable via command line arguments. */
124 #define TARGET_FRW (target_flags & 256)
126 /* Nonzero means that we should generate code using a flat register window
127 model, i.e. no save/restore instructions are generated, but which is
128 compatible with normal sparc code. This is the same as above, except
129 that the frame pointer is %l6 instead of %fp. This code is not as efficient
130 as TARGET_FRW, because it has one less allocatable register. */
131 /* This is not a user selectable option yet, because it requires changes
132 that are not yet switchable via command line arguments. */
133 #define TARGET_FRW_COMPAT (target_flags & 512)
135 /* Macro to define tables used to set the flags.
136 This is a list in braces of pairs in braces,
137 each pair being { "NAME", VALUE }
138 where VALUE is the bits to set or minus the bits to clear.
139 An empty string NAME is used to identify the default VALUE. */
141 #define TARGET_SWITCHES \
145 {"soft-float", -1}, \
147 {"no-epilogue", -2}, \
148 {"unaligned-doubles", 4}, \
149 {"no-unaligned-doubles", -4},\
152 {"sparclite", 128}, \
154 {"no-sparclite", -128}, \
155 {"no-sparclite", 1}, \
156 /* {"frw", 256}, */ \
157 /* {"no-frw", -256}, */ \
158 /* {"frw-compat", 256+512}, */ \
159 /* {"no-frw-compat", -(256+512)}, */ \
160 { "", TARGET_DEFAULT}}
162 #define TARGET_DEFAULT 3
164 /* target machine storage layout */
166 /* Define this if most significant bit is lowest numbered
167 in instructions that operate on numbered bit-fields. */
168 #define BITS_BIG_ENDIAN 1
170 /* Define this if most significant byte of a word is the lowest numbered. */
171 /* This is true on the SPARC. */
172 #define BYTES_BIG_ENDIAN 1
174 /* Define this if most significant word of a multiword number is the lowest
176 /* Doubles are stored in memory with the high order word first. This
177 matters when cross-compiling. */
178 #define WORDS_BIG_ENDIAN 1
180 /* number of bits in an addressable storage unit */
181 #define BITS_PER_UNIT 8
183 /* Width in bits of a "word", which is the contents of a machine register.
184 Note that this is not necessarily the width of data type `int';
185 if using 16-bit ints on a 68000, this would still be 32.
186 But on a machine with 16-bit registers, this would be 16. */
187 #define BITS_PER_WORD 32
188 #define MAX_BITS_PER_WORD 32
190 /* Width of a word, in units (bytes). */
191 #define UNITS_PER_WORD 4
193 /* Width in bits of a pointer.
194 See also the macro `Pmode' defined below. */
195 #define POINTER_SIZE 32
197 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
198 #define PARM_BOUNDARY 32
200 /* Boundary (in *bits*) on which stack pointer should be aligned. */
201 #define STACK_BOUNDARY 64
203 /* ALIGN FRAMES on double word boundaries */
205 #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
207 /* Allocation boundary (in *bits*) for the code of a function. */
208 #define FUNCTION_BOUNDARY 32
210 /* Alignment of field after `int : 0' in a structure. */
211 #define EMPTY_FIELD_BOUNDARY 32
213 /* Every structure's size must be a multiple of this. */
214 #define STRUCTURE_SIZE_BOUNDARY 8
216 /* A bitfield declared as `int' forces `int' alignment for the struct. */
217 #define PCC_BITFIELD_TYPE_MATTERS 1
219 /* No data type wants to be aligned rounder than this. */
220 #define BIGGEST_ALIGNMENT 64
222 /* The best alignment to use in cases where we have a choice. */
223 #define FASTEST_ALIGNMENT 64
225 /* Make strings word-aligned so strcpy from constants will be faster. */
226 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
227 ((TREE_CODE (EXP) == STRING_CST \
228 && (ALIGN) < FASTEST_ALIGNMENT) \
229 ? FASTEST_ALIGNMENT : (ALIGN))
231 /* Make arrays of chars word-aligned for the same reasons. */
232 #define DATA_ALIGNMENT(TYPE, ALIGN) \
233 (TREE_CODE (TYPE) == ARRAY_TYPE \
234 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
235 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
237 /* Set this nonzero if move instructions will actually fail to work
238 when given unaligned data. */
239 #define STRICT_ALIGNMENT 1
241 /* Things that must be doubleword aligned cannot go in the text section,
242 because the linker fails to align the text section enough!
243 Put them in the data section. */
244 #define MAX_TEXT_ALIGN 32
246 #define SELECT_SECTION(T,RELOC) \
248 if (TREE_CODE (T) == VAR_DECL) \
250 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
251 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
252 && ! (flag_pic && (RELOC))) \
257 else if (TREE_CODE (T) == CONSTRUCTOR) \
259 if (flag_pic != 0 && (RELOC) != 0) \
262 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
264 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
265 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
272 /* Use text section for a constant
273 unless we need more alignment than that offers. */
274 #define SELECT_RTX_SECTION(MODE, X) \
276 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
277 && ! (flag_pic && symbolic_operand (X))) \
283 /* Standard register usage. */
285 /* Number of actual hardware registers.
286 The hardware registers are assigned numbers for the compiler
287 from 0 to just below FIRST_PSEUDO_REGISTER.
288 All registers that the compiler knows about must be given numbers,
289 even those that are not normally considered general registers.
291 SPARC has 32 integer registers and 32 floating point registers. */
293 #define FIRST_PSEUDO_REGISTER 64
295 /* 1 for registers that have pervasive standard uses
296 and are not available for the register allocator.
297 g0 is used for the condition code and not to represent %g0, which is
298 hardwired to 0, so reg 0 is *not* fixed.
299 g1 through g4 are free to use as temporaries.
300 g5 through g7 are reserved for the operating system. */
301 #define FIXED_REGISTERS \
302 {0, 0, 0, 0, 0, 1, 1, 1, \
303 0, 0, 0, 0, 0, 0, 1, 0, \
304 0, 0, 0, 0, 0, 0, 0, 0, \
305 0, 0, 0, 0, 0, 0, 1, 1, \
307 0, 0, 0, 0, 0, 0, 0, 0, \
308 0, 0, 0, 0, 0, 0, 0, 0, \
309 0, 0, 0, 0, 0, 0, 0, 0, \
310 0, 0, 0, 0, 0, 0, 0, 0}
312 /* 1 for registers not available across function calls.
313 These must include the FIXED_REGISTERS and also any
314 registers that can be used without being saved.
315 The latter must include the registers where values are returned
316 and the register where structure-value addresses are passed.
317 Aside from that, you can include as many other registers as you like. */
318 #define CALL_USED_REGISTERS \
319 {1, 1, 1, 1, 1, 1, 1, 1, \
320 1, 1, 1, 1, 1, 1, 1, 1, \
321 0, 0, 0, 0, 0, 0, 0, 0, \
322 0, 0, 0, 0, 0, 0, 1, 1, \
324 1, 1, 1, 1, 1, 1, 1, 1, \
325 1, 1, 1, 1, 1, 1, 1, 1, \
326 1, 1, 1, 1, 1, 1, 1, 1, \
327 1, 1, 1, 1, 1, 1, 1, 1}
329 /* If !TARGET_FPU, then make the fp registers fixed so that they won't
332 #define CONDITIONAL_REGISTER_USAGE \
338 for (regno = 32; regno < 64; regno++) \
339 fixed_regs[regno] = 1; \
344 /* Return number of consecutive hard regs needed starting at reg REGNO
345 to hold something of mode MODE.
346 This is ordinarily the length in words of a value of mode MODE
347 but can be less for certain modes in special long registers.
349 On SPARC, ordinary registers hold 32 bits worth;
350 this means both integer and floating point registers.
352 We use vectors to keep this information about registers. */
354 /* How many hard registers it takes to make a register of this mode. */
355 extern int hard_regno_nregs
[];
357 #define HARD_REGNO_NREGS(REGNO, MODE) \
358 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
360 /* Value is 1 if register/mode pair is acceptable on sparc. */
361 extern int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
363 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
364 On SPARC, the cpu registers can hold any mode but the float registers
365 can only hold SFmode or DFmode. See sparc.c for how we
367 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
368 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
370 /* Value is 1 if it is a good idea to tie two pseudo registers
371 when one has mode MODE1 and one has mode MODE2.
372 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
373 for any hard reg, then this must be 0 for correct output. */
374 #define MODES_TIEABLE_P(MODE1, MODE2) \
375 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
377 /* Specify the registers used for certain standard purposes.
378 The values of these macros are register numbers. */
380 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
381 /* #define PC_REGNUM */
383 /* Register to use for pushing function arguments. */
384 #define STACK_POINTER_REGNUM 14
386 /* Actual top-of-stack address is 92 greater than the contents
387 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
388 for the ins and local registers, 4 byte for structure return address, and
389 24 bytes for the 6 register parameters. */
390 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
392 /* Base register for access to local variables of the function. */
393 #define FRAME_POINTER_REGNUM 30
396 /* Register that is used for the return address. */
397 #define RETURN_ADDR_REGNUM 15
400 /* Value should be nonzero if functions must have frame pointers.
401 Zero means the frame pointer need not be set up (and parms
402 may be accessed via the stack pointer) in functions that seem suitable.
403 This is computed in `reload', in reload1.c.
405 Used in flow.c, global.c, and reload1.c. */
406 extern int leaf_function
;
408 #define FRAME_POINTER_REQUIRED \
409 (! (leaf_function_p () && only_leaf_regs_used ()))
411 /* C statement to store the difference between the frame pointer
412 and the stack pointer values immediately after the function prologue.
414 Note, we always pretend that this is a leaf function because if
415 it's not, there's no point in trying to eliminate the
416 frame pointer. If it is a leaf function, we guessed right! */
417 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
418 ((VAR) = (TARGET_FRW ? sparc_frw_compute_frame_size (get_frame_size ()) \
419 : compute_frame_size (get_frame_size (), 1)))
421 /* Base register for access to arguments of the function. */
422 #define ARG_POINTER_REGNUM 30
424 /* Register in which static-chain is passed to a function. */
426 #define STATIC_CHAIN_REGNUM 1
428 /* Register which holds offset table for position-independent
431 #define PIC_OFFSET_TABLE_REGNUM 23
433 #define INITIALIZE_PIC initialize_pic ()
434 #define FINALIZE_PIC finalize_pic ()
436 /* Sparc ABI says that quad-precision floats and all structures are returned
438 #define RETURN_IN_MEMORY(TYPE) \
439 (TYPE_MODE (TYPE) == BLKmode || TYPE_MODE (TYPE) == TFmode)
441 /* Functions which return large structures get the address
442 to place the wanted value at offset 64 from the frame.
443 Must reserve 64 bytes for the in and local registers. */
444 /* Used only in other #defines in this file. */
445 #define STRUCT_VALUE_OFFSET 64
447 #define STRUCT_VALUE \
448 gen_rtx (MEM, Pmode, \
449 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
450 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
451 #define STRUCT_VALUE_INCOMING \
452 gen_rtx (MEM, Pmode, \
453 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
454 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
456 /* Define the classes of registers for register constraints in the
457 machine description. Also define ranges of constants.
459 One of the classes must always be named ALL_REGS and include all hard regs.
460 If there is more than one class, another class must be named NO_REGS
461 and contain no registers.
463 The name GENERAL_REGS must be the name of a class (or an alias for
464 another name such as ALL_REGS). This is the class of registers
465 that is allowed by "g" or "r" in a register constraint.
466 Also, registers outside this class are allocated only when
467 instructions express preferences for them.
469 The classes must be numbered in nondecreasing order; that is,
470 a larger-numbered class must never be contained completely
471 in a smaller-numbered class.
473 For any two classes, it is very desirable that there be another
474 class that represents their union. */
476 /* The SPARC has two kinds of registers, general and floating point. */
478 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
480 #define N_REG_CLASSES (int) LIM_REG_CLASSES
482 /* Give names of register classes as strings for dump file. */
484 #define REG_CLASS_NAMES \
485 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
487 /* Define which registers fit in which classes.
488 This is an initializer for a vector of HARD_REG_SET
489 of length N_REG_CLASSES. */
491 #if 0 && defined (__GNUC__)
492 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
494 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
497 /* The same information, inverted:
498 Return the class number of the smallest class containing
499 reg number REGNO. This could be a conditional expression
500 or could index an array. */
502 #define REGNO_REG_CLASS(REGNO) \
503 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
505 /* This is the order in which to allocate registers
508 We put %f0/%f1 last among the float registers, so as to make it more
509 likely that a pseduo-register which dies in the float return register
510 will get allocated to the float return register, thus saving a move
511 instruction at the end of the function. */
512 #define REG_ALLOC_ORDER \
513 { 8, 9, 10, 11, 12, 13, 2, 3, \
514 15, 16, 17, 18, 19, 20, 21, 22, \
515 23, 24, 25, 26, 27, 28, 29, 31, \
516 34, 35, 36, 37, 38, 39, \
517 40, 41, 42, 43, 44, 45, 46, 47, \
518 48, 49, 50, 51, 52, 53, 54, 55, \
519 56, 57, 58, 59, 60, 61, 62, 63, \
521 1, 4, 5, 6, 7, 0, 14, 30}
523 /* This is the order in which to allocate registers for
524 leaf functions. If all registers can fit in the "i" registers,
525 then we have the possibility of having a leaf function. */
526 #define REG_LEAF_ALLOC_ORDER \
527 { 2, 3, 24, 25, 26, 27, 28, 29, \
528 15, 8, 9, 10, 11, 12, 13, \
529 16, 17, 18, 19, 20, 21, 22, 23, \
530 34, 35, 36, 37, 38, 39, \
531 40, 41, 42, 43, 44, 45, 46, 47, \
532 48, 49, 50, 51, 52, 53, 54, 55, \
533 56, 57, 58, 59, 60, 61, 62, 63, \
535 1, 4, 5, 6, 7, 0, 14, 30, 31}
537 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
539 #define LEAF_REGISTERS \
540 { 1, 1, 1, 1, 1, 1, 1, 1, \
541 0, 0, 0, 0, 0, 0, 1, 0, \
542 0, 0, 0, 0, 0, 0, 0, 0, \
543 1, 1, 1, 1, 1, 1, 0, 1, \
544 1, 1, 1, 1, 1, 1, 1, 1, \
545 1, 1, 1, 1, 1, 1, 1, 1, \
546 1, 1, 1, 1, 1, 1, 1, 1, \
547 1, 1, 1, 1, 1, 1, 1, 1}
549 extern char leaf_reg_remap
[];
550 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
551 extern char leaf_reg_backmap
[];
552 #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
554 /* The class value for index registers, and the one for base regs. */
555 #define INDEX_REG_CLASS GENERAL_REGS
556 #define BASE_REG_CLASS GENERAL_REGS
558 /* Get reg_class from a letter such as appears in the machine description. */
560 #define REG_CLASS_FROM_LETTER(C) \
561 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
563 /* The letters I, J, K, L and M in a register constraint string
564 can be used to stand for particular ranges of immediate operands.
565 This macro defines what the ranges are.
566 C is the letter, and VALUE is a constant value.
567 Return 1 if VALUE is in the range specified by C.
569 For SPARC, `I' is used for the range of constants an insn
570 can actually contain.
571 `J' is used for the range which is just zero (since that is R0).
572 `K' is used for constants which can be loaded with a single sethi insn. */
574 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
576 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
577 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
578 : (C) == 'J' ? (VALUE) == 0 \
579 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
582 /* Similar, but for floating constants, and defining letters G and H.
583 Here VALUE is the CONST_DOUBLE rtx itself. */
585 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
586 ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
587 && CONST_DOUBLE_LOW (VALUE) == 0 \
588 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
591 /* Given an rtx X being reloaded into a reg required to be
592 in class CLASS, return the class of reg to actually use.
593 In general this is just CLASS; but on some machines
594 in some cases it is preferable to use a more restrictive class. */
595 /* We can't load constants into FP registers. We can't load any FP constant
596 if an 'E' constraint fails to match it. */
597 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
599 && ((CLASS) == FP_REGS \
600 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
601 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
602 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
605 /* Return the register class of a scratch register needed to load IN into
606 a register of class CLASS in MODE.
608 On the SPARC, when PIC, we need a temporary when loading some addresses
611 Also, we need a temporary when loading/storing a HImode/QImode value
612 between memory and the FPU registers. This can happen when combine puts
613 a paradoxical subreg in a float/fix conversion insn. */
615 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
616 (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS \
617 : ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode)\
618 && (GET_CODE (IN) == MEM \
619 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
620 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
622 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
623 ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode) \
624 && (GET_CODE (IN) == MEM \
625 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
626 && true_regnum (IN) == -1)) ? GENERAL_REGS : NO_REGS)
628 /* On SPARC it is not possible to directly move data between
629 GENERAL_REGS and FP_REGS. */
630 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
631 (((CLASS1) == FP_REGS && (CLASS2) == GENERAL_REGS) \
632 || ((CLASS1) == GENERAL_REGS && (CLASS2) == FP_REGS))
634 /* Return the stack location to use for secondary memory needed reloads. */
635 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
636 gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, GEN_INT (-8)))
638 /* Return the maximum number of consecutive registers
639 needed to represent mode MODE in a register of class CLASS. */
640 /* On SPARC, this is the size of MODE in words. */
641 #define CLASS_MAX_NREGS(CLASS, MODE) \
642 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
644 /* Stack layout; function entry, exit and calling. */
646 /* Define the number of register that can hold parameters.
647 These two macros are used only in other macro definitions below. */
650 /* Define this if pushing a word on the stack
651 makes the stack pointer a smaller address. */
652 #define STACK_GROWS_DOWNWARD
654 /* Define this if the nominal address of the stack frame
655 is at the high-address end of the local variables;
656 that is, each additional local variable allocated
657 goes at a more negative offset in the frame. */
658 #define FRAME_GROWS_DOWNWARD
660 /* Offset within stack frame to start allocating local variables at.
661 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
662 first local allocated. Otherwise, it is the offset to the BEGINNING
663 of the first local allocated. */
664 #define STARTING_FRAME_OFFSET (-8)
666 /* If we generate an insn to push BYTES bytes,
667 this says how many the stack pointer really advances by.
668 On SPARC, don't define this because there are no push insns. */
669 /* #define PUSH_ROUNDING(BYTES) */
671 /* Offset of first parameter from the argument pointer register value.
672 This is 64 for the ins and locals, plus 4 for the struct-return reg
673 even if this function isn't going to use it. */
674 #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
676 /* When a parameter is passed in a register, stack space is still
678 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
680 /* Keep the stack pointer constant throughout the function.
681 This is both an optimization and a necessity: longjmp
682 doesn't behave itself when the stack pointer moves within
684 #define ACCUMULATE_OUTGOING_ARGS
686 /* Value is the number of bytes of arguments automatically
687 popped when returning from a subroutine call.
688 FUNTYPE is the data type of the function (as a tree),
689 or for a library call it is an identifier node for the subroutine name.
690 SIZE is the number of bytes of arguments passed on the stack. */
692 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
694 /* Some subroutine macros specific to this machine.
695 When !TARGET_FPU, put float return values in the general registers,
696 since we don't have any fp registers. */
697 #define BASE_RETURN_VALUE_REG(MODE) \
698 (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)
699 #define BASE_OUTGOING_VALUE_REG(MODE) \
700 (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
701 : (TARGET_FRW ? 8 : 24))
702 #define BASE_PASSING_ARG_REG(MODE) (8)
703 #define BASE_INCOMING_ARG_REG(MODE) (TARGET_FRW ? 8 : 24)
705 /* Define this macro if the target machine has "register windows". This
706 C expression returns the register number as seen by the called function
707 corresponding to register number OUT as seen by the calling function.
708 Return OUT if register number OUT is not an outbound register. */
710 #define INCOMING_REGNO(OUT) \
711 ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
713 /* Define this macro if the target machine has "register windows". This
714 C expression returns the register number as seen by the calling function
715 corresponding to register number IN as seen by the called function.
716 Return IN if register number IN is not an inbound register. */
718 #define OUTGOING_REGNO(IN) \
719 ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
721 /* Define how to find the value returned by a function.
722 VALTYPE is the data type of the value (as a tree).
723 If the precise function being called is known, FUNC is its FUNCTION_DECL;
724 otherwise, FUNC is 0. */
726 /* On SPARC the value is found in the first "output" register. */
728 #define FUNCTION_VALUE(VALTYPE, FUNC) \
729 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
731 /* But the called function leaves it in the first "input" register. */
733 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
734 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
736 /* Define how to find the value returned by a library function
737 assuming the value has mode MODE. */
739 #define LIBCALL_VALUE(MODE) \
740 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
742 /* 1 if N is a possible register number for a function value
743 as seen by the caller.
744 On SPARC, the first "output" reg is used for integer values,
745 and the first floating point register is used for floating point values. */
747 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
749 /* 1 if N is a possible register number for function argument passing.
750 On SPARC, these are the "output" registers. */
752 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
754 /* Define a data type for recording info about an argument list
755 during the scan of that argument list. This data type should
756 hold all necessary information about the function itself
757 and about the args processed so far, enough to enable macros
758 such as FUNCTION_ARG to determine where the next arg should go.
760 On SPARC, this is a single integer, which is a number of words
761 of arguments scanned so far (including the invisible argument,
762 if any, which holds the structure-value-address).
763 Thus 7 or more means all following args should go on the stack. */
765 #define CUMULATIVE_ARGS int
767 #define ROUND_ADVANCE(SIZE) \
768 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
770 /* Initialize a variable CUM of type CUMULATIVE_ARGS
771 for a call to a function whose data type is FNTYPE.
772 For a library call, FNTYPE is 0.
774 On SPARC, the offset always starts at 0: the first parm reg is always
777 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
779 /* Update the data in CUM to advance over an argument
780 of mode MODE and data type TYPE.
781 (TYPE is null for libcalls where that information may not be available.) */
783 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
784 ((CUM) += ((MODE) != BLKmode \
785 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
786 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
788 /* Determine where to put an argument to a function.
789 Value is zero to push the argument on the stack,
790 or a hard register in which to store the argument.
792 MODE is the argument's machine mode.
793 TYPE is the data type of the argument (as a tree).
794 This is null for libcalls where that information may
796 CUM is a variable of type CUMULATIVE_ARGS which gives info about
797 the preceding args and about the function being called.
798 NAMED is nonzero if this argument is a named parameter
799 (otherwise it is an extra parameter matching an ellipsis). */
801 /* On SPARC the first six args are normally in registers
802 and the rest are pushed. Any arg that starts within the first 6 words
803 is at least partially passed in a register unless its data type forbids. */
805 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
806 ((CUM) < NPARM_REGS \
807 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
808 && ((TYPE)==0 || (MODE) != BLKmode \
809 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
810 ? gen_rtx (REG, (MODE), (BASE_PASSING_ARG_REG (MODE) + (CUM))) \
813 /* Define where a function finds its arguments.
814 This is different from FUNCTION_ARG because of register windows. */
816 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
817 ((CUM) < NPARM_REGS \
818 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
819 && ((TYPE)==0 || (MODE) != BLKmode \
820 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
821 ? gen_rtx (REG, (MODE), (BASE_INCOMING_ARG_REG (MODE) + (CUM))) \
824 /* For an arg passed partly in registers and partly in memory,
825 this is the number of registers used.
826 For args passed entirely in registers or entirely in memory, zero.
827 Any arg that starts in the first 6 regs but won't entirely fit in them
828 needs partial registers on the Sparc. */
830 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
831 ((CUM) < NPARM_REGS \
832 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
833 && ((TYPE)==0 || (MODE) != BLKmode \
834 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
835 && ((CUM) + ((MODE) == BLKmode \
836 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
837 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS > 0)\
838 ? (NPARM_REGS - (CUM)) \
841 /* The SPARC ABI stipulates passing struct arguments (of any size) and
842 quad-precision floats by invisible reference. */
843 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
844 ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
845 || TREE_CODE (TYPE) == UNION_TYPE)) \
848 /* Define the information needed to generate branch and scc insns. This is
849 stored from the compare operation. Note that we can't use "rtx" here
850 since it hasn't been defined! */
852 extern struct rtx_def
*sparc_compare_op0
, *sparc_compare_op1
;
854 /* Define the function that build the compare insn for scc and bcc. */
856 extern struct rtx_def
*gen_compare_reg ();
858 /* Generate the special assembly code needed to tell the assembler whatever
859 it might need to know about the return value of a function.
861 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
862 information to the assembler relating to peephole optimization (done in
865 #define ASM_DECLARE_RESULT(FILE, RESULT) \
866 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
868 /* Output the label for a function definition. */
870 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
872 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
873 ASM_OUTPUT_LABEL (FILE, NAME); \
876 /* Two views of the size of the current frame. */
877 extern int actual_fsize
;
878 extern int apparent_fsize
;
880 /* This macro generates the assembly code for function entry.
881 FILE is a stdio stream to output the code to.
882 SIZE is an int: how many units of temporary storage to allocate.
883 Refer to the array `regs_ever_live' to determine which registers
884 to save; `regs_ever_live[I]' is nonzero if register number I
885 is ever used in the function. This macro is responsible for
886 knowing which registers should not be saved even if used. */
888 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
889 of memory. If any fpu reg is used in the function, we allocate
890 such a block here, at the bottom of the frame, just in case it's needed.
892 If this function is a leaf procedure, then we may choose not
893 to do a "save" insn. The decision about whether or not
894 to do this is made in regclass.c. */
896 #define FUNCTION_PROLOGUE(FILE, SIZE) \
897 (TARGET_FRW ? sparc_frw_output_function_prologue (FILE, SIZE, leaf_function)\
898 : output_function_prologue (FILE, SIZE, leaf_function))
900 /* Output assembler code to FILE to increment profiler label # LABELNO
901 for profiling a function entry. */
903 #define FUNCTION_PROFILER(FILE, LABELNO) \
905 fputs ("\tsethi %hi(", (FILE)); \
906 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
907 fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \
908 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
909 fputs ("),%o0,%o0\n", (FILE)); \
912 /* Output assembler code to FILE to initialize this source file's
913 basic block profiling info, if that has not already been done. */
914 /* FIXME -- this does not parameterize how it generates labels (like the
915 above FUNCTION_PROFILER). Broken on Solaris-2. --gnu@cygnus.com */
917 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
918 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
919 (LABELNO), (LABELNO))
921 /* Output assembler code to FILE to increment the entry-count for
922 the BLOCKNO'th basic block in this source file. */
924 #define BLOCK_PROFILER(FILE, BLOCKNO) \
926 int blockn = (BLOCKNO); \
927 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
928 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
929 4 * blockn, 4 * blockn, 4 * blockn); \
932 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
933 the stack pointer does not matter. The value is tested only in
934 functions that have frame pointers.
935 No definition is equivalent to always zero. */
937 extern int current_function_calls_alloca
;
938 extern int current_function_outgoing_args_size
;
940 #define EXIT_IGNORE_STACK \
941 (get_frame_size () != 0 \
942 || current_function_calls_alloca || current_function_outgoing_args_size)
944 /* This macro generates the assembly code for function exit,
945 on machines that need it. If FUNCTION_EPILOGUE is not defined
946 then individual return instructions are generated for each
947 return statement. Args are same as for FUNCTION_PROLOGUE.
949 The function epilogue should not depend on the current stack pointer!
950 It should use the frame pointer only. This is mandatory because
951 of alloca; we also take advantage of it to omit stack adjustments
954 /* This declaration is needed due to traditional/ANSI
955 incompatibilities which cannot be #ifdefed away
956 because they occur inside of macros. Sigh. */
957 extern union tree_node
*current_function_decl
;
959 #define FUNCTION_EPILOGUE(FILE, SIZE) \
960 (TARGET_FRW ? sparc_frw_output_function_epilogue (FILE, SIZE, leaf_function)\
961 : output_function_epilogue (FILE, SIZE, leaf_function))
963 #define DELAY_SLOTS_FOR_EPILOGUE \
964 (TARGET_FRW ? sparc_frw_epilogue_delay_slots () : 1)
965 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
966 (TARGET_FRW ? sparc_frw_eligible_for_epilogue_delay (trial, slots_filled) \
967 : eligible_for_epilogue_delay (trial, slots_filled))
969 /* Output assembler code for a block containing the constant parts
970 of a trampoline, leaving space for the variable parts. */
972 /* On the sparc, the trampoline contains five instructions:
973 sethi #TOP_OF_FUNCTION,%g2
974 or #BOTTOM_OF_FUNCTION,%g2,%g2
975 sethi #TOP_OF_STATIC,%g1
977 or #BOTTOM_OF_STATIC,%g1,%g1 */
978 #define TRAMPOLINE_TEMPLATE(FILE) \
980 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
981 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
982 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
983 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
984 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
987 /* Length in units of the trampoline for entering a nested function. */
989 #define TRAMPOLINE_SIZE 20
991 /* Emit RTL insns to initialize the variable parts of a trampoline.
992 FNADDR is an RTX for the address of the function's pure code.
993 CXT is an RTX for the static chain value for the function.
995 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
996 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
997 (to store insns). This is a bit excessive. Perhaps a different
998 mechanism would be better here. */
1000 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1002 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
1003 size_int (10), 0, 1); \
1004 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
1005 size_int (10), 0, 1); \
1006 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1007 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1008 rtx g1_sethi = gen_rtx (HIGH, SImode, \
1009 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
1010 rtx g2_sethi = gen_rtx (HIGH, SImode, \
1011 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
1012 rtx g1_ori = gen_rtx (HIGH, SImode, \
1013 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
1014 rtx g2_ori = gen_rtx (HIGH, SImode, \
1015 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
1016 rtx tem = gen_reg_rtx (SImode); \
1017 emit_move_insn (tem, g2_sethi); \
1018 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
1019 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
1020 emit_move_insn (tem, g2_ori); \
1021 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
1022 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
1023 emit_move_insn (tem, g1_sethi); \
1024 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
1025 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
1026 emit_move_insn (tem, g1_ori); \
1027 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
1028 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
1031 /* Generate necessary RTL for __builtin_saveregs().
1032 ARGLIST is the argument list; see expr.c. */
1033 extern struct rtx_def
*sparc_builtin_saveregs ();
1034 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
1036 /* Generate RTL to flush the register windows so as to make arbitrary frames
1038 #define SETUP_FRAME_ADDRESSES() \
1039 emit_insn (gen_flush_register_windows ())
1041 /* Given an rtx for the address of a frame,
1042 return an rtx for the address of the word in the frame
1043 that holds the dynamic chain--the previous frame's address. */
1044 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1045 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 56))
1047 /* The return address isn't on the stack, it is in a register, so we can't
1048 access it from the current frame pointer. We can access it from the
1049 previous frame pointer though by reading a value from the register window
1051 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1053 /* The current return address is in %i7. The return address of anything
1054 farther back is in the register window save area at [%fp+60]. */
1055 /* ??? This ignores the fact that the actual return address is +8 for normal
1056 returns, and +12 for structure returns. */
1057 #define RETURN_ADDR_RTX(count, frame) \
1059 ? gen_rtx (REG, Pmode, 31) \
1060 : copy_to_reg (gen_rtx (MEM, Pmode, \
1061 memory_address (Pmode, plus_constant (frame, 60)))))
1063 /* Addressing modes, and classification of registers for them. */
1065 /* #define HAVE_POST_INCREMENT */
1066 /* #define HAVE_POST_DECREMENT */
1068 /* #define HAVE_PRE_DECREMENT */
1069 /* #define HAVE_PRE_INCREMENT */
1071 /* Macros to check register numbers against specific register classes. */
1073 /* These assume that REGNO is a hard or pseudo reg number.
1074 They give nonzero only if REGNO is a hard reg of the suitable class
1075 or a pseudo reg currently allocated to a suitable hard reg.
1076 Since they use reg_renumber, they are safe only once reg_renumber
1077 has been allocated, which happens in local-alloc.c. */
1079 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1080 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1081 #define REGNO_OK_FOR_BASE_P(REGNO) \
1082 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1083 #define REGNO_OK_FOR_FP_P(REGNO) \
1084 (((REGNO) ^ 0x20) < 32 \
1085 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1087 /* Now macros that check whether X is a register and also,
1088 strictly, whether it is in a specified class.
1090 These macros are specific to the SPARC, and may be used only
1091 in code for printing assembler insns and in conditions for
1092 define_optimization. */
1094 /* 1 if X is an fp register. */
1096 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1098 /* Maximum number of registers that can appear in a valid memory address. */
1100 #define MAX_REGS_PER_ADDRESS 2
1102 /* Recognize any constant value that is a valid address. */
1104 #define CONSTANT_ADDRESS_P(X) \
1105 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1106 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1107 || GET_CODE (X) == HIGH)
1109 /* Nonzero if the constant value X is a legitimate general operand.
1110 Anything can be made to work except floating point constants. */
1112 #define LEGITIMATE_CONSTANT_P(X) \
1113 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1115 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1116 and check its validity for a certain class.
1117 We have two alternate definitions for each of them.
1118 The usual definition accepts all pseudo regs; the other rejects
1119 them unless they have been allocated suitable hard regs.
1120 The symbol REG_OK_STRICT causes the latter definition to be used.
1122 Most source files want to accept pseudo regs in the hope that
1123 they will get allocated to the class that the insn wants them to be in.
1124 Source files for reload pass need to be strict.
1125 After reload, it makes no difference, since pseudo regs have
1126 been eliminated by then. */
1128 /* Optional extra constraints for this machine. Borrowed from romp.h.
1130 For the SPARC, `Q' means that this is a memory operand but not a
1131 symbolic memory operand. Note that an unassigned pseudo register
1132 is such a memory operand. Needed because reload will generate
1133 these things in insns and then not re-recognize the insns, causing
1134 constrain_operands to fail.
1136 `S' handles constraints for calls. */
1138 #ifndef REG_OK_STRICT
1140 /* Nonzero if X is a hard reg that can be used as an index
1141 or if it is a pseudo reg. */
1142 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1143 /* Nonzero if X is a hard reg that can be used as a base reg
1144 or if it is a pseudo reg. */
1145 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1147 #define EXTRA_CONSTRAINT(OP, C) \
1149 ? ((GET_CODE (OP) == MEM \
1150 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1151 && ! symbolic_memory_operand (OP, VOIDmode)) \
1152 || (reload_in_progress && GET_CODE (OP) == REG \
1153 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1155 ? (CONSTANT_P (OP) || memory_address_p (Pmode, OP)) \
1157 ? (mem_aligned_8 (OP)) \
1159 ? (register_ok_for_ldd (OP)) \
1164 /* Nonzero if X is a hard reg that can be used as an index. */
1165 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1166 /* Nonzero if X is a hard reg that can be used as a base reg. */
1167 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1169 #define EXTRA_CONSTRAINT(OP, C) \
1171 ? (GET_CODE (OP) == REG \
1172 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1173 && reg_renumber[REGNO (OP)] < 0) \
1174 : GET_CODE (OP) == MEM) \
1176 ? (CONSTANT_P (OP) \
1177 || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0) \
1178 || strict_memory_address_p (Pmode, OP)) \
1180 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, OP) \
1182 ? register_ok_for_ldd (OP) : 0)
1185 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1186 that is a valid memory address for an instruction.
1187 The MODE argument is the machine mode for the MEM expression
1188 that wants to use this address.
1190 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1191 ordinarily. This changes a bit when generating PIC.
1193 If you change this, execute "rm explow.o recog.o reload.o". */
1195 #define RTX_OK_FOR_BASE_P(X) \
1196 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1197 || (GET_CODE (X) == SUBREG \
1198 && GET_CODE (SUBREG_REG (X)) == REG \
1199 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1201 #define RTX_OK_FOR_INDEX_P(X) \
1202 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1203 || (GET_CODE (X) == SUBREG \
1204 && GET_CODE (SUBREG_REG (X)) == REG \
1205 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1207 #define RTX_OK_FOR_OFFSET_P(X) \
1208 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1210 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1211 { if (RTX_OK_FOR_BASE_P (X)) \
1213 else if (GET_CODE (X) == PLUS) \
1215 register rtx op0 = XEXP (X, 0); \
1216 register rtx op1 = XEXP (X, 1); \
1217 if (flag_pic && op0 == pic_offset_table_rtx) \
1219 if (RTX_OK_FOR_BASE_P (op1)) \
1221 else if (flag_pic == 1 \
1222 && GET_CODE (op1) != REG \
1223 && GET_CODE (op1) != LO_SUM \
1224 && GET_CODE (op1) != MEM) \
1227 else if (RTX_OK_FOR_BASE_P (op0)) \
1229 if (RTX_OK_FOR_INDEX_P (op1) \
1230 || RTX_OK_FOR_OFFSET_P (op1)) \
1233 else if (RTX_OK_FOR_BASE_P (op1)) \
1235 if (RTX_OK_FOR_INDEX_P (op0) \
1236 || RTX_OK_FOR_OFFSET_P (op0)) \
1240 else if (GET_CODE (X) == LO_SUM) \
1242 register rtx op0 = XEXP (X, 0); \
1243 register rtx op1 = XEXP (X, 1); \
1244 if (RTX_OK_FOR_BASE_P (op0) \
1245 && CONSTANT_P (op1)) \
1248 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1252 /* Try machine-dependent ways of modifying an illegitimate address
1253 to be legitimate. If we find one, return the new, valid address.
1254 This macro is used in only one place: `memory_address' in explow.c.
1256 OLDX is the address as it was before break_out_memory_refs was called.
1257 In some cases it is useful to look at this to decide what needs to be done.
1259 MODE and WIN are passed so that this macro can use
1260 GO_IF_LEGITIMATE_ADDRESS.
1262 It is always safe for this macro to do nothing. It exists to recognize
1263 opportunities to optimize the output. */
1265 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1266 extern struct rtx_def
*legitimize_pic_address ();
1267 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1268 { rtx sparc_x = (X); \
1269 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1270 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1271 force_operand (XEXP (X, 0), NULL_RTX)); \
1272 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1273 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1274 force_operand (XEXP (X, 1), NULL_RTX)); \
1275 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1276 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
1278 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1279 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1280 force_operand (XEXP (X, 1), NULL_RTX)); \
1281 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1283 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1284 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1285 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1286 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1287 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1288 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1289 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1290 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1291 || GET_CODE (X) == LABEL_REF) \
1292 (X) = gen_rtx (LO_SUM, Pmode, \
1293 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1294 if (memory_address_p (MODE, X)) \
1297 /* Go to LABEL if ADDR (a legitimate address expression)
1298 has an effect that depends on the machine mode it is used for.
1299 On the SPARC this is never true. */
1301 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1303 /* Specify the machine mode that this machine uses
1304 for the index in the tablejump instruction. */
1305 #define CASE_VECTOR_MODE SImode
1307 /* Define this if the tablejump instruction expects the table
1308 to contain offsets from the address of the table.
1309 Do not define this if the table should contain absolute addresses. */
1310 /* #define CASE_VECTOR_PC_RELATIVE */
1312 /* Specify the tree operation to be used to convert reals to integers. */
1313 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1315 /* This is the kind of divide that is easiest to do in the general case. */
1316 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1318 /* Define this as 1 if `char' should by default be signed; else as 0. */
1319 #define DEFAULT_SIGNED_CHAR 1
1321 /* Max number of bytes we can move from memory to memory
1322 in one reasonably fast instruction. */
1325 #if 0 /* Sun 4 has matherr, so this is no good. */
1326 /* This is the value of the error code EDOM for this machine,
1327 used by the sqrt instruction. */
1328 #define TARGET_EDOM 33
1330 /* This is how to refer to the variable errno. */
1331 #define GEN_ERRNO_RTX \
1332 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
1335 /* Define if normal loads of shorter-than-word items from memory clears
1336 the rest of the bigs in the register. */
1337 #define BYTE_LOADS_ZERO_EXTEND
1339 /* Nonzero if access to memory by bytes is slow and undesirable.
1340 For RISC chips, it means that access to memory by bytes is no
1341 better than access by words when possible, so grab a whole word
1342 and maybe make use of that. */
1343 #define SLOW_BYTE_ACCESS 1
1345 /* We assume that the store-condition-codes instructions store 0 for false
1346 and some other value for true. This is the value stored for true. */
1348 #define STORE_FLAG_VALUE 1
1350 /* When a prototype says `char' or `short', really pass an `int'. */
1351 #define PROMOTE_PROTOTYPES
1353 /* Define if shifts truncate the shift count
1354 which implies one can omit a sign-extension or zero-extension
1355 of a shift count. */
1356 #define SHIFT_COUNT_TRUNCATED
1358 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1359 is done just by pretending it is already truncated. */
1360 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1362 /* Specify the machine mode that pointers have.
1363 After generation of rtl, the compiler makes no further distinction
1364 between pointers and any other objects of this machine mode. */
1365 #define Pmode SImode
1367 /* Generate calls to memcpy, memcmp and memset. */
1368 #define TARGET_MEM_FUNCTIONS
1370 /* Add any extra modes needed to represent the condition code.
1372 On the Sparc, we have a "no-overflow" mode which is used when an add or
1373 subtract insn is used to set the condition code. Different branches are
1374 used in this case for some operations.
1376 We also have two modes to indicate that the relevant condition code is
1377 in the floating-point condition code register. One for comparisons which
1378 will generate an exception if the result is unordered (CCFPEmode) and
1379 one for comparisons which will never trap (CCFPmode). This really should
1380 be a separate register, but we don't want to go to 65 registers. */
1381 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1383 /* Define the names for the modes specified above. */
1384 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1386 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1387 return the mode to be used for the comparison. For floating-point,
1388 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1389 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1391 #define SELECT_CC_MODE(OP,X,Y) \
1392 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1393 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1394 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1395 ? CC_NOOVmode : CCmode))
1397 /* A function address in a call instruction
1398 is a byte address (for indexing purposes)
1399 so give the MEM rtx a byte's mode. */
1400 #define FUNCTION_MODE SImode
1402 /* Define this if addresses of constant functions
1403 shouldn't be put through pseudo regs where they can be cse'd.
1404 Desirable on machines where ordinary constants are expensive
1405 but a CALL with constant address is cheap. */
1406 #define NO_FUNCTION_CSE
1408 /* alloca should avoid clobbering the old register save area. */
1409 #define SETJMP_VIA_SAVE_AREA
1411 /* Define subroutines to call to handle multiply and divide.
1412 Use the subroutines that Sun's library provides.
1413 The `*' prevents an underscore from being prepended by the compiler. */
1415 #define DIVSI3_LIBCALL "*.div"
1416 #define UDIVSI3_LIBCALL "*.udiv"
1417 #define MODSI3_LIBCALL "*.rem"
1418 #define UMODSI3_LIBCALL "*.urem"
1419 /* .umul is a little faster than .mul. */
1420 #define MULSI3_LIBCALL "*.umul"
1422 /* Compute the cost of computing a constant rtl expression RTX
1423 whose rtx-code is CODE. The body of this macro is a portion
1424 of a switch statement. If the code is computed here,
1425 return it with a return statement. Otherwise, break from the switch. */
1427 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1429 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1437 case CONST_DOUBLE: \
1438 if (GET_MODE (RTX) == DImode) \
1439 if ((XINT (RTX, 3) == 0 \
1440 && (unsigned) XINT (RTX, 2) < 0x1000) \
1441 || (XINT (RTX, 3) == -1 \
1442 && XINT (RTX, 2) < 0 \
1443 && XINT (RTX, 2) >= -0x1000)) \
1447 /* SPARC offers addressing modes which are "as cheap as a register".
1448 See sparc.c (or gcc.texinfo) for details. */
1450 #define ADDRESS_COST(RTX) \
1451 (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1453 /* Compute extra cost of moving data between one register class
1455 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1456 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1457 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1459 /* Provide the costs of a rtl expression. This is in the body of a
1460 switch on CODE. The purpose for the cost of MULT is to encourage
1461 `synth_mult' to find a synthetic multiply when reasonable.
1463 If we need more than 12 insns to do a multiply, then go out-of-line,
1464 since the call overhead will be < 10% of the cost of the multiply. */
1466 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1468 return COSTS_N_INSNS (25); \
1473 return COSTS_N_INSNS (25); \
1474 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
1475 so that cse will favor the latter. */ \
1480 /* Conditional branches with empty delay slots have a length of two. */
1481 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1482 if (GET_CODE (INSN) == CALL_INSN \
1483 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1486 /* Control the assembler format that we output. */
1488 /* Output at beginning of assembler file. */
1490 #define ASM_FILE_START(file)
1492 /* Output to assembler file text saying following lines
1493 may contain character constants, extra white space, comments, etc. */
1495 #define ASM_APP_ON ""
1497 /* Output to assembler file text saying following lines
1498 no longer contain unusual constructs. */
1500 #define ASM_APP_OFF ""
1502 #define ASM_LONG ".word"
1503 #define ASM_SHORT ".half"
1504 #define ASM_BYTE_OP ".byte"
1506 /* Output before read-only data. */
1508 #define TEXT_SECTION_ASM_OP ".text"
1510 /* Output before writable data. */
1512 #define DATA_SECTION_ASM_OP ".data"
1514 /* How to refer to registers in assembler output.
1515 This sequence is indexed by compiler's hard-register-number (see above). */
1517 #define REGISTER_NAMES \
1518 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1519 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1520 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1521 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1522 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1523 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1524 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1525 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1527 /* Define additional names for use in asm clobbers and asm declarations.
1529 We define the fake Condition Code register as an alias for reg 0 (which
1530 is our `condition code' register), so that condition codes can easily
1531 be clobbered by an asm. No such register actually exists. Condition
1532 codes are partly stored in the PSR and partly in the FSR. */
1534 #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1536 /* How to renumber registers for dbx and gdb. */
1538 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1540 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1541 since the length can run past this up to a continuation point. */
1542 #define DBX_CONTIN_LENGTH 1500
1544 /* This is how to output a note to DBX telling it the line number
1545 to which the following sequence of instructions corresponds.
1547 This is needed for SunOS 4.0, and should not hurt for 3.2
1549 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1550 { static int sym_lineno = 1; \
1551 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1552 line, sym_lineno, sym_lineno); \
1555 /* This is how to output the definition of a user-level label named NAME,
1556 such as the label on a static function or variable NAME. */
1558 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1559 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1561 /* This is how to output a command to make the user-level label named NAME
1562 defined for reference from other files. */
1564 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1565 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1567 /* This is how to output a reference to a user-level label named NAME.
1568 `assemble_name' uses this. */
1570 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1571 fprintf (FILE, "_%s", NAME)
1573 /* This is how to output a definition of an internal numbered label where
1574 PREFIX is the class of label and NUM is the number within the class. */
1576 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1577 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1579 /* This is how to output a reference to an internal numbered label where
1580 PREFIX is the class of label and NUM is the number within the class. */
1581 /* FIXME: This should be used throughout gcc, and documented in the texinfo
1582 files. There is no reason you should have to allocate a buffer and
1583 `sprintf' to reference an internal label (as opposed to defining it). */
1585 #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
1586 fprintf (FILE, "%s%d", PREFIX, NUM)
1588 /* This is how to store into the string LABEL
1589 the symbol_ref name of an internal numbered label where
1590 PREFIX is the class of label and NUM is the number within the class.
1591 This is suitable for output with `assemble_name'. */
1593 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1594 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1596 /* This is how to output an assembler line defining a `double' constant. */
1598 /* Assemblers (both gas 1.35 and as in 4.0.3)
1599 seem to treat -0.0 as if it were 0.0.
1600 They reject 99e9999, but accept inf. */
1601 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1603 if (REAL_VALUE_ISINF (VALUE) \
1604 || REAL_VALUE_ISNAN (VALUE) \
1605 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1608 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1609 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1610 ASM_LONG, t[0], ASM_LONG, t[1]); \
1613 fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1616 /* This is how to output an assembler line defining a `float' constant. */
1618 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1620 if (REAL_VALUE_ISINF (VALUE) \
1621 || REAL_VALUE_ISNAN (VALUE) \
1622 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1625 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1626 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
1629 fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1632 /* This is how to output an assembler line defining a `long double'
1635 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1638 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
1639 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1640 ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
1643 /* This is how to output an assembler line defining an `int' constant. */
1645 #define ASM_OUTPUT_INT(FILE,VALUE) \
1646 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
1647 output_addr_const (FILE, (VALUE)), \
1648 fprintf (FILE, "\n"))
1650 /* This is how to output an assembler line defining a DImode constant. */
1651 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1652 output_double_int (FILE, VALUE)
1654 /* Likewise for `char' and `short' constants. */
1656 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1657 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
1658 output_addr_const (FILE, (VALUE)), \
1659 fprintf (FILE, "\n"))
1661 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1662 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
1663 output_addr_const (FILE, (VALUE)), \
1664 fprintf (FILE, "\n"))
1666 /* This is how to output an assembler line for a numeric constant byte. */
1668 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1669 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
1671 /* This is how to output an element of a case-vector that is absolute. */
1673 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1676 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1677 fprintf (FILE, "\t.word\t"); \
1678 assemble_name (FILE, label); \
1679 fprintf (FILE, "\n"); \
1682 /* This is how to output an element of a case-vector that is relative.
1683 (SPARC uses such vectors only when generating PIC.) */
1685 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1688 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1689 fprintf (FILE, "\t.word\t"); \
1690 assemble_name (FILE, label); \
1691 fprintf (FILE, "-1b\n"); \
1694 /* This is how to output an assembler line
1695 that says to advance the location counter
1696 to a multiple of 2**LOG bytes. */
1698 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1700 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1702 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1703 fprintf (FILE, "\t.skip %u\n", (SIZE))
1705 /* This says how to output an assembler line
1706 to define a global common symbol. */
1708 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1709 ( fputs ("\t.global ", (FILE)), \
1710 assemble_name ((FILE), (NAME)), \
1711 fputs ("\n\t.common ", (FILE)), \
1712 assemble_name ((FILE), (NAME)), \
1713 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1715 /* This says how to output an assembler line
1716 to define a local common symbol. */
1718 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1719 ( fputs ("\n\t.reserve ", (FILE)), \
1720 assemble_name ((FILE), (NAME)), \
1721 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1723 /* Store in OUTPUT a string (made with alloca) containing
1724 an assembler-name for a local static variable named NAME.
1725 LABELNO is an integer which is different for each call. */
1727 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1728 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1729 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1731 #define IDENT_ASM_OP ".ident"
1733 /* Output #ident as a .ident. */
1735 #define ASM_OUTPUT_IDENT(FILE, NAME) \
1736 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
1738 /* Define the parentheses used to group arithmetic operations
1739 in assembler code. */
1741 #define ASM_OPEN_PAREN "("
1742 #define ASM_CLOSE_PAREN ")"
1744 /* Define results of standard character escape sequences. */
1745 #define TARGET_BELL 007
1746 #define TARGET_BS 010
1747 #define TARGET_TAB 011
1748 #define TARGET_NEWLINE 012
1749 #define TARGET_VT 013
1750 #define TARGET_FF 014
1751 #define TARGET_CR 015
1753 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1754 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
1756 /* Print operand X (an rtx) in assembler syntax to file FILE.
1757 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1758 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1760 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1762 /* Print a memory address as an operand to reference that memory location. */
1764 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1765 { register rtx base, index = 0; \
1767 register rtx addr = ADDR; \
1768 if (GET_CODE (addr) == REG) \
1769 fputs (reg_names[REGNO (addr)], FILE); \
1770 else if (GET_CODE (addr) == PLUS) \
1772 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1773 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1774 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1775 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1777 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1778 fputs (reg_names[REGNO (base)], FILE); \
1780 fprintf (FILE, "%+d", offset); \
1781 else if (GET_CODE (index) == REG) \
1782 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1783 else if (GET_CODE (index) == SYMBOL_REF) \
1784 fputc ('+', FILE), output_addr_const (FILE, index); \
1787 else if (GET_CODE (addr) == MINUS \
1788 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1790 output_addr_const (FILE, XEXP (addr, 0)); \
1791 fputs ("-(", FILE); \
1792 output_addr_const (FILE, XEXP (addr, 1)); \
1793 fputs ("-.)", FILE); \
1795 else if (GET_CODE (addr) == LO_SUM) \
1797 output_operand (XEXP (addr, 0), 0); \
1798 fputs ("+%lo(", FILE); \
1799 output_address (XEXP (addr, 1)); \
1800 fputc (')', FILE); \
1802 else if (flag_pic && GET_CODE (addr) == CONST \
1803 && GET_CODE (XEXP (addr, 0)) == MINUS \
1804 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1805 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1806 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1808 addr = XEXP (addr, 0); \
1809 output_addr_const (FILE, XEXP (addr, 0)); \
1810 /* Group the args of the second CONST in parenthesis. */ \
1811 fputs ("-(", FILE); \
1812 /* Skip past the second CONST--it does nothing for us. */\
1813 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1814 /* Close the parenthesis. */ \
1815 fputc (')', FILE); \
1819 output_addr_const (FILE, addr); \
1823 /* Declare functions defined in sparc.c and used in templates. */
1825 extern char *singlemove_string ();
1826 extern char *output_move_double ();
1827 extern char *output_move_quad ();
1828 extern char *output_fp_move_double ();
1829 extern char *output_fp_move_quad ();
1830 extern char *output_block_move ();
1831 extern char *output_scc_insn ();
1832 extern char *output_cbranch ();
1833 extern char *output_return ();
1835 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1837 extern int flag_pic
;