1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
26 /* Provide required defaults for linker -e and -d switches. */
28 #define LINK_SPEC "%{!e*:-e start} -dc -dp %{static:-Bstatic} %{assert*}"
30 /* Special flags to the Sun-4 assembler when using pipe for input. */
32 #define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}"
34 /* Prevent error on `-sun4' and `-target sun4' options. */
35 /* This used to translate -dalign to -malign, but that is no good
36 because it can't turn off the usual meaning of making debugging dumps. */
38 #define CC1_SPEC "%{sun4:} %{target:}"
40 #define PTRDIFF_TYPE "int"
41 #define SIZE_TYPE "int"
42 #define WCHAR_TYPE "short unsigned int"
43 #define WCHAR_TYPE_SIZE 16
45 /* Omit frame pointer at high optimization levels. */
47 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
51 flag_omit_frame_pointer = 1; \
55 /* These compiler options take an argument. We ignore -target for now. */
57 #define WORD_SWITCH_TAKES_ARG(STR) \
58 (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \
59 || !strcmp (STR, "imacros") || !strcmp (STR, "target") \
60 || !strcmp (STR, "assert") || !strcmp (STR, "aux-info"))
62 /* Names to predefine in the preprocessor for this target machine. */
64 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix"
66 /* Print subsidiary information on the compiler version in use. */
68 #define TARGET_VERSION fprintf (stderr, " (sparc)");
70 /* Generate DBX debugging information. */
72 #define DBX_DEBUGGING_INFO
74 /* Run-time compilation parameters selecting different hardware subsets. */
76 extern int target_flags
;
78 /* Nonzero if we should generate code to use the fpu. */
79 #define TARGET_FPU (target_flags & 1)
81 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
82 use fast return insns, but lose some generality. */
83 #define TARGET_EPILOGUE (target_flags & 2)
85 /* Nonzero if we assume that all calls will fall within a 16MB
86 pc-relative range. Useful with -fomit-frame-pointer. */
87 #define TARGET_TAIL_CALL (target_flags & 8)
89 /* Nonzero means that reference doublewords as if they were guaranteed
90 to be aligned...if they aren't, too bad for the user!
91 Like -fast in Sun cc. */
92 #define TARGET_HOPE_ALIGN (target_flags & 16)
94 /* Nonzero means that make sure all doubles are on 8-byte boundaries. */
95 #define TARGET_FORCE_ALIGN (target_flags & 32)
97 /* Macro to define tables used to set the flags.
98 This is a list in braces of pairs in braces,
99 each pair being { "NAME", VALUE }
100 where VALUE is the bits to set or minus the bits to clear.
101 An empty string NAME is used to identify the default VALUE. */
103 #define TARGET_SWITCHES \
105 {"soft-float", -1}, \
107 {"no-epilogue", -2}, \
109 {"hope-align", 16}, \
110 {"force-align", 48}, \
111 { "", TARGET_DEFAULT}}
113 #define TARGET_DEFAULT 3
115 /* target machine storage layout */
117 /* Define this if most significant bit is lowest numbered
118 in instructions that operate on numbered bit-fields. */
119 #define BITS_BIG_ENDIAN 1
121 /* Define this if most significant byte of a word is the lowest numbered. */
122 /* This is true on the SPARC. */
123 #define BYTES_BIG_ENDIAN 1
125 /* Define this if most significant word of a multiword number is the lowest
127 /* Doubles are stored in memory with the high order word first. This
128 matters when cross-compiling. */
129 #define WORDS_BIG_ENDIAN 1
131 /* number of bits in an addressable storage unit */
132 #define BITS_PER_UNIT 8
134 /* Width in bits of a "word", which is the contents of a machine register.
135 Note that this is not necessarily the width of data type `int';
136 if using 16-bit ints on a 68000, this would still be 32.
137 But on a machine with 16-bit registers, this would be 16. */
138 #define BITS_PER_WORD 32
139 #define MAX_BITS_PER_WORD 32
141 /* Width of a word, in units (bytes). */
142 #define UNITS_PER_WORD 4
144 /* Width in bits of a pointer.
145 See also the macro `Pmode' defined below. */
146 #define POINTER_SIZE 32
148 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
149 #define PARM_BOUNDARY 32
151 /* Boundary (in *bits*) on which stack pointer should be aligned. */
152 #define STACK_BOUNDARY 64
154 /* Allocation boundary (in *bits*) for the code of a function. */
155 #define FUNCTION_BOUNDARY 32
157 /* Alignment of field after `int : 0' in a structure. */
158 #define EMPTY_FIELD_BOUNDARY 32
160 /* Every structure's size must be a multiple of this. */
161 #define STRUCTURE_SIZE_BOUNDARY 8
163 /* A bitfield declared as `int' forces `int' alignment for the struct. */
164 #define PCC_BITFIELD_TYPE_MATTERS 1
166 /* No data type wants to be aligned rounder than this. */
167 #define BIGGEST_ALIGNMENT 64
169 /* Make strings word-aligned so strcpy from constants will be faster. */
170 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
171 (TREE_CODE (EXP) == STRING_CST \
172 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
174 /* Make arrays of chars word-aligned for the same reasons. */
175 #define DATA_ALIGNMENT(TYPE, ALIGN) \
176 (TREE_CODE (TYPE) == ARRAY_TYPE \
177 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
178 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
180 /* Set this nonzero if move instructions will actually fail to work
181 when given unaligned data. */
182 #define STRICT_ALIGNMENT 1
184 /* Things that must be doubleword aligned cannot go in the text section,
185 because the linker fails to align the text section enough!
186 Put them in the data section. */
187 #define MAX_TEXT_ALIGN 32
189 #define SELECT_SECTION(T,RELOC) \
191 if (TREE_CODE (T) == VAR_DECL) \
193 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
194 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
195 && ! (flag_pic && (RELOC))) \
200 else if (TREE_CODE (T) == CONSTRUCTOR) \
202 if (flag_pic != 0 && (RELOC) != 0) \
205 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
207 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
208 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
215 /* Use text section for a constant
216 unless we need more alignment than that offers. */
217 #define SELECT_RTX_SECTION(MODE, X) \
219 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
220 && ! (flag_pic && symbolic_operand (X))) \
226 /* Standard register usage. */
228 /* Number of actual hardware registers.
229 The hardware registers are assigned numbers for the compiler
230 from 0 to just below FIRST_PSEUDO_REGISTER.
231 All registers that the compiler knows about must be given numbers,
232 even those that are not normally considered general registers.
234 SPARC has 32 integer registers and 32 floating point registers. */
236 #define FIRST_PSEUDO_REGISTER 64
238 /* 1 for registers that have pervasive standard uses
239 and are not available for the register allocator.
240 0 is used for the condition code and not to represent %g0, which is
241 hardwired to 0, so reg 0 is *not* fixed.
242 2 and 3 are free to use as temporaries.
243 4 through 7 are expected to become usefully defined in the future.
244 Your milage may vary. */
245 #define FIXED_REGISTERS \
246 {0, 0, 0, 0, 1, 1, 1, 1, \
247 0, 0, 0, 0, 0, 0, 1, 0, \
248 0, 0, 0, 0, 0, 0, 0, 0, \
249 0, 0, 0, 0, 0, 0, 1, 1, \
251 0, 0, 0, 0, 0, 0, 0, 0, \
252 0, 0, 0, 0, 0, 0, 0, 0, \
253 0, 0, 0, 0, 0, 0, 0, 0, \
254 0, 0, 0, 0, 0, 0, 0, 0}
256 /* 1 for registers not available across function calls.
257 These must include the FIXED_REGISTERS and also any
258 registers that can be used without being saved.
259 The latter must include the registers where values are returned
260 and the register where structure-value addresses are passed.
261 Aside from that, you can include as many other registers as you like. */
262 #define CALL_USED_REGISTERS \
263 {1, 1, 1, 1, 1, 1, 1, 1, \
264 1, 1, 1, 1, 1, 1, 1, 1, \
265 0, 0, 0, 0, 0, 0, 0, 0, \
266 0, 0, 0, 0, 0, 0, 1, 1, \
268 1, 1, 1, 1, 1, 1, 1, 1, \
269 1, 1, 1, 1, 1, 1, 1, 1, \
270 1, 1, 1, 1, 1, 1, 1, 1, \
271 1, 1, 1, 1, 1, 1, 1, 1}
273 /* Return number of consecutive hard regs needed starting at reg REGNO
274 to hold something of mode MODE.
275 This is ordinarily the length in words of a value of mode MODE
276 but can be less for certain modes in special long registers.
278 On SPARC, ordinary registers hold 32 bits worth;
279 this means both integer and floating point registers.
281 We use vectors to keep this information about registers. */
283 /* How many hard registers it takes to make a register of this mode. */
284 extern int hard_regno_nregs
[];
286 #define HARD_REGNO_NREGS(REGNO, MODE) \
287 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
289 /* Value is 1 if register/mode pair is acceptable on sparc. */
290 extern int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
292 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
293 On SPARC, the cpu registers can hold any mode but the float registers
294 can only hold SFmode or DFmode. See sparc.c for how we
296 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
297 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
299 /* Value is 1 if it is a good idea to tie two pseudo registers
300 when one has mode MODE1 and one has mode MODE2.
301 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
302 for any hard reg, then this must be 0 for correct output. */
303 #define MODES_TIEABLE_P(MODE1, MODE2) \
304 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
306 /* Specify the registers used for certain standard purposes.
307 The values of these macros are register numbers. */
309 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
310 /* #define PC_REGNUM */
312 /* Register to use for pushing function arguments. */
313 #define STACK_POINTER_REGNUM 14
315 /* Actual top-of-stack address is 92 greater than the contents
316 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
317 for the ins and local registers, 4 byte for structure return address, and
318 24 bytes for the 6 register parameters. */
319 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
321 /* Base register for access to local variables of the function. */
322 #define FRAME_POINTER_REGNUM 30
325 /* Register that is used for the return address. */
326 #define RETURN_ADDR_REGNUM 15
329 /* Value should be nonzero if functions must have frame pointers.
330 Zero means the frame pointer need not be set up (and parms
331 may be accessed via the stack pointer) in functions that seem suitable.
332 This is computed in `reload', in reload1.c.
334 Used in flow.c, global-alloc.c, and reload1.c. */
335 extern int leaf_function
;
336 extern int compute_last_arg_offset ();
338 /* Return 0 if span from stack ptr to last stack arg is too far. */
339 #define FRAME_POINTER_REQUIRED \
340 (! (leaf_function_p () && only_leaf_regs_used () \
341 && compute_last_arg_offset () < 4090))
343 /* C statement to store the difference between the frame pointer
344 and the stack pointer values immediately after the function prologue.
346 Note, we always pretend that this is a leaf function because if
347 it's not, there's no point in trying to eliminate the
348 frame pointer. If it is a leaf function, we guessed right! */
349 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
350 do { (VAR) = compute_frame_size (get_frame_size (), 1); } while (0)
352 /* Base register for access to arguments of the function. */
353 #define ARG_POINTER_REGNUM 30
355 /* Register in which static-chain is passed to a function. */
357 #define STATIC_CHAIN_REGNUM 1
359 /* Register which holds offset table for position-independent
362 #define PIC_OFFSET_TABLE_REGNUM 23
364 #define INITIALIZE_PIC initialize_pic ()
365 #define FINALIZE_PIC finalize_pic ()
367 /* Functions which return large structures get the address
368 to place the wanted value at offset 64 from the frame.
369 Must reserve 64 bytes for the in and local registers. */
370 /* Used only in other #defines in this file. */
371 #define STRUCT_VALUE_OFFSET 64
373 #define STRUCT_VALUE \
374 gen_rtx (MEM, Pmode, \
375 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
376 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
377 #define STRUCT_VALUE_INCOMING \
378 gen_rtx (MEM, Pmode, \
379 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
380 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
382 /* Define the classes of registers for register constraints in the
383 machine description. Also define ranges of constants.
385 One of the classes must always be named ALL_REGS and include all hard regs.
386 If there is more than one class, another class must be named NO_REGS
387 and contain no registers.
389 The name GENERAL_REGS must be the name of a class (or an alias for
390 another name such as ALL_REGS). This is the class of registers
391 that is allowed by "g" or "r" in a register constraint.
392 Also, registers outside this class are allocated only when
393 instructions express preferences for them.
395 The classes must be numbered in nondecreasing order; that is,
396 a larger-numbered class must never be contained completely
397 in a smaller-numbered class.
399 For any two classes, it is very desirable that there be another
400 class that represents their union. */
402 /* The SPARC has two kinds of registers, general and floating point. */
404 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
406 #define N_REG_CLASSES (int) LIM_REG_CLASSES
408 /* Give names of register classes as strings for dump file. */
410 #define REG_CLASS_NAMES \
411 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
413 /* Define which registers fit in which classes.
414 This is an initializer for a vector of HARD_REG_SET
415 of length N_REG_CLASSES. */
417 #if 0 && defined (__GNUC__)
418 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
420 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
423 /* The same information, inverted:
424 Return the class number of the smallest class containing
425 reg number REGNO. This could be a conditional expression
426 or could index an array. */
428 #define REGNO_REG_CLASS(REGNO) \
429 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
431 /* This is the order in which to allocate registers
433 #define REG_ALLOC_ORDER \
434 { 8, 9, 10, 11, 12, 13, 2, 3, \
435 15, 16, 17, 18, 19, 20, 21, 22, \
436 23, 24, 25, 26, 27, 28, 29, 31, \
437 32, 33, 34, 35, 36, 37, 38, 39, \
438 40, 41, 42, 43, 44, 45, 46, 47, \
439 48, 49, 50, 51, 52, 53, 54, 55, \
440 56, 57, 58, 59, 60, 61, 62, 63, \
441 1, 4, 5, 6, 7, 0, 14, 30}
443 /* This is the order in which to allocate registers for
444 leaf functions. If all registers can fit in the "i" registers,
445 then we have the possibility of having a leaf function. */
446 #define REG_LEAF_ALLOC_ORDER \
447 { 2, 3, 24, 25, 26, 27, 28, 29, \
448 15, 8, 9, 10, 11, 12, 13, \
449 16, 17, 18, 19, 20, 21, 22, 23, \
450 32, 33, 34, 35, 36, 37, 38, 39, \
451 40, 41, 42, 43, 44, 45, 46, 47, \
452 48, 49, 50, 51, 52, 53, 54, 55, \
453 56, 57, 58, 59, 60, 61, 62, 63, \
454 1, 4, 5, 6, 7, 0, 14, 30, 31}
456 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
458 #define LEAF_REGISTERS \
459 { 1, 1, 1, 1, 1, 1, 1, 1, \
460 0, 0, 0, 0, 0, 0, 1, 0, \
461 0, 0, 0, 0, 0, 0, 0, 0, \
462 1, 1, 1, 1, 1, 1, 0, 1, \
463 1, 1, 1, 1, 1, 1, 1, 1, \
464 1, 1, 1, 1, 1, 1, 1, 1, \
465 1, 1, 1, 1, 1, 1, 1, 1, \
466 1, 1, 1, 1, 1, 1, 1, 1}
468 extern char leaf_reg_remap
[];
469 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
470 extern char leaf_reg_backmap
[];
471 #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
473 #define REG_USED_SO_FAR(REGNO) \
474 ((REGNO) >= 24 && (REGNO) < 30 \
475 ? (regs_ever_live[24] \
476 || regs_ever_live[25] \
477 || regs_ever_live[26] \
478 || regs_ever_live[27] \
479 || regs_ever_live[28] \
480 || regs_ever_live[29]) : 0)
482 /* The class value for index registers, and the one for base regs. */
483 #define INDEX_REG_CLASS GENERAL_REGS
484 #define BASE_REG_CLASS GENERAL_REGS
486 /* Get reg_class from a letter such as appears in the machine description. */
488 #define REG_CLASS_FROM_LETTER(C) \
489 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
491 /* The letters I, J, K, L and M in a register constraint string
492 can be used to stand for particular ranges of immediate operands.
493 This macro defines what the ranges are.
494 C is the letter, and VALUE is a constant value.
495 Return 1 if VALUE is in the range specified by C.
497 For SPARC, `I' is used for the range of constants an insn
498 can actually contain.
499 `J' is used for the range which is just zero (since that is R0).
500 `K' is used for the 5-bit operand of a compare insns. */
502 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
504 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
505 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
506 : (C) == 'J' ? (VALUE) == 0 \
507 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
510 /* Similar, but for floating constants, and defining letters G and H.
511 Here VALUE is the CONST_DOUBLE rtx itself. */
513 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
514 ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
515 && CONST_DOUBLE_LOW (VALUE) == 0 \
516 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
519 /* Given an rtx X being reloaded into a reg required to be
520 in class CLASS, return the class of reg to actually use.
521 In general this is just CLASS; but on some machines
522 in some cases it is preferable to use a more restrictive class. */
523 #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
525 /* Return the register class of a scratch register needed to load IN into
526 a register of class CLASS in MODE.
528 On the SPARC, when PIC, we need a temporary when loading some addresses
531 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
532 (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS : NO_REGS)
534 /* Return the maximum number of consecutive registers
535 needed to represent mode MODE in a register of class CLASS. */
536 /* On SPARC, this is the size of MODE in words. */
537 #define CLASS_MAX_NREGS(CLASS, MODE) \
538 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
540 /* Stack layout; function entry, exit and calling. */
542 /* Define the number of register that can hold parameters.
543 These two macros are used only in other macro definitions below. */
546 /* Define this if pushing a word on the stack
547 makes the stack pointer a smaller address. */
548 #define STACK_GROWS_DOWNWARD
550 /* Define this if the nominal address of the stack frame
551 is at the high-address end of the local variables;
552 that is, each additional local variable allocated
553 goes at a more negative offset in the frame. */
554 #define FRAME_GROWS_DOWNWARD
556 /* Offset within stack frame to start allocating local variables at.
557 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
558 first local allocated. Otherwise, it is the offset to the BEGINNING
559 of the first local allocated. */
560 #define STARTING_FRAME_OFFSET (-16)
562 /* If we generate an insn to push BYTES bytes,
563 this says how many the stack pointer really advances by.
564 On SPARC, don't define this because there are no push insns. */
565 /* #define PUSH_ROUNDING(BYTES) */
567 /* Offset of first parameter from the argument pointer register value.
568 This is 64 for the ins and locals, plus 4 for the struct-return reg
569 even if this function isn't going to use it. */
570 #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
572 /* Offset from top-of-stack address to location to store the
573 function parameter if it can't go in a register.
574 Addresses for following parameters are computed relative to this one. */
575 #define FIRST_PARM_CALLER_OFFSET(FNDECL) \
576 (STRUCT_VALUE_OFFSET + UNITS_PER_WORD - STACK_POINTER_OFFSET)
578 /* When a parameter is passed in a register, stack space is still
580 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
582 /* Keep the stack pointer constant throughout the function.
583 This is both an optimization and a necessity: longjmp
584 doesn't behave itself when the stack pointer moves within
586 #define ACCUMULATE_OUTGOING_ARGS
588 /* Value is the number of bytes of arguments automatically
589 popped when returning from a subroutine call.
590 FUNTYPE is the data type of the function (as a tree),
591 or for a library call it is an identifier node for the subroutine name.
592 SIZE is the number of bytes of arguments passed on the stack. */
594 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
596 /* Some subroutine macros specific to this machine. */
597 #define BASE_RETURN_VALUE_REG(MODE) \
598 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8)
599 #define BASE_OUTGOING_VALUE_REG(MODE) \
600 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24)
601 #define BASE_PASSING_ARG_REG(MODE) (8)
602 #define BASE_INCOMING_ARG_REG(MODE) (24)
604 /* Define how to find the value returned by a function.
605 VALTYPE is the data type of the value (as a tree).
606 If the precise function being called is known, FUNC is its FUNCTION_DECL;
607 otherwise, FUNC is 0. */
609 /* On SPARC the value is found in the first "output" register. */
611 #define FUNCTION_VALUE(VALTYPE, FUNC) \
612 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
614 /* But the called function leaves it in the first "input" register. */
616 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
617 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
619 /* Define how to find the value returned by a library function
620 assuming the value has mode MODE. */
622 #define LIBCALL_VALUE(MODE) \
623 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
625 /* 1 if N is a possible register number for a function value
626 as seen by the caller.
627 On SPARC, the first "output" reg is used for integer values,
628 and the first floating point register is used for floating point values. */
630 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
632 /* 1 if N is a possible register number for function argument passing.
633 On SPARC, these are the "output" registers. */
635 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
637 /* Define a data type for recording info about an argument list
638 during the scan of that argument list. This data type should
639 hold all necessary information about the function itself
640 and about the args processed so far, enough to enable macros
641 such as FUNCTION_ARG to determine where the next arg should go.
643 On SPARC, this is a single integer, which is a number of words
644 of arguments scanned so far (including the invisible argument,
645 if any, which holds the structure-value-address).
646 Thus 7 or more means all following args should go on the stack. */
648 #define CUMULATIVE_ARGS int
650 #define ROUND_ADVANCE(SIZE) \
651 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
653 /* Round a register number up to a proper boundary for an arg of mode MODE.
654 Note that we need an odd/even pair for a two-word arg,
655 since that will become 8-byte aligned when stored in memory. */
656 #define ROUND_REG(X, MODE) \
657 (TARGET_FORCE_ALIGN && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
658 ? ((X) + ! ((X) & 1)) : (X))
660 /* Initialize a variable CUM of type CUMULATIVE_ARGS
661 for a call to a function whose data type is FNTYPE.
662 For a library call, FNTYPE is 0.
664 On SPARC, the offset always starts at 0: the first parm reg is always
667 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
669 /* Update the data in CUM to advance over an argument
670 of mode MODE and data type TYPE.
671 (TYPE is null for libcalls where that information may not be available.) */
673 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
674 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
675 + ((MODE) != BLKmode \
676 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
677 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
679 /* Determine where to put an argument to a function.
680 Value is zero to push the argument on the stack,
681 or a hard register in which to store the argument.
683 MODE is the argument's machine mode.
684 TYPE is the data type of the argument (as a tree).
685 This is null for libcalls where that information may
687 CUM is a variable of type CUMULATIVE_ARGS which gives info about
688 the preceding args and about the function being called.
689 NAMED is nonzero if this argument is a named parameter
690 (otherwise it is an extra parameter matching an ellipsis). */
692 /* On SPARC the first six args are normally in registers
693 and the rest are pushed. Any arg that starts within the first 6 words
694 is at least partially passed in a register unless its data type forbids. */
696 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
697 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
698 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
699 && ((TYPE)==0 || (MODE) != BLKmode \
700 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
701 ? gen_rtx (REG, (MODE), \
702 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
705 /* Define where a function finds its arguments.
706 This is different from FUNCTION_ARG because of register windows. */
708 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
709 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
710 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
711 && ((TYPE)==0 || (MODE) != BLKmode \
712 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
713 ? gen_rtx (REG, (MODE), \
714 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
717 /* For an arg passed partly in registers and partly in memory,
718 this is the number of registers used.
719 For args passed entirely in registers or entirely in memory, zero.
720 Any arg that starts in the first 6 regs but won't entirely fit in them
721 needs partial registers on the Sparc. */
723 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
724 ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
725 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
726 && ((TYPE)==0 || (MODE) != BLKmode \
727 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
728 && (ROUND_REG ((CUM), (MODE)) \
729 + ((MODE) == BLKmode \
730 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
731 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
732 ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
735 /* The SPARC ABI stipulates passing struct arguments (of any size)
736 by invisible reference. */
737 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
738 (TYPE && (TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE (TYPE) == UNION_TYPE))
740 /* If defined, a C expression that gives the alignment boundary, in
741 bits, of an argument with the specified mode and type. If it is
742 not defined, `PARM_BOUNDARY' is used for all arguments.
744 This definition does nothing special unless TARGET_FORCE_ALIGN;
745 in that case, it aligns each arg to the natural boundary. */
747 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
748 (! TARGET_FORCE_ALIGN \
751 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
753 : TYPE_ALIGN (TYPE)) \
754 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
756 : GET_MODE_ALIGNMENT (MODE))))
758 /* Define the information needed to generate branch and scc insns. This is
759 stored from the compare operation. Note that we can't use "rtx" here
760 since it hasn't been defined! */
762 extern struct rtx_def
*sparc_compare_op0
, *sparc_compare_op1
;
764 /* Define the function that build the compare insn for scc and bcc. */
766 extern struct rtx_def
*gen_compare_reg ();
768 /* Generate the special assembly code needed to tell the assembler whatever
769 it might need to know about the return value of a function.
771 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
772 information to the assembler relating to peephole optimization (done in
775 #define ASM_DECLARE_RESULT(FILE, RESULT) \
776 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
778 /* Output the label for a function definition. */
780 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
782 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
783 ASM_OUTPUT_LABEL (FILE, NAME); \
786 /* Two views of the size of the current frame. */
787 extern int actual_fsize
;
788 extern int apparent_fsize
;
790 /* This macro generates the assembly code for function entry.
791 FILE is a stdio stream to output the code to.
792 SIZE is an int: how many units of temporary storage to allocate.
793 Refer to the array `regs_ever_live' to determine which registers
794 to save; `regs_ever_live[I]' is nonzero if register number I
795 is ever used in the function. This macro is responsible for
796 knowing which registers should not be saved even if used. */
798 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
799 of memory. If any fpu reg is used in the function, we allocate
800 such a block here, at the bottom of the frame, just in case it's needed.
802 If this function is a leaf procedure, then we may choose not
803 to do a "save" insn. The decision about whether or not
804 to do this is made in regclass.c. */
806 #define FUNCTION_PROLOGUE(FILE, SIZE) \
807 output_function_prologue (FILE, SIZE, leaf_function)
809 /* Output assembler code to FILE to increment profiler label # LABELNO
810 for profiling a function entry. */
812 #define FUNCTION_PROFILER(FILE, LABELNO) \
813 fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
814 (LABELNO), (LABELNO))
816 /* Output assembler code to FILE to initialize this source file's
817 basic block profiling info, if that has not already been done. */
819 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
820 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
821 (LABELNO), (LABELNO))
823 /* Output assembler code to FILE to increment the entry-count for
824 the BLOCKNO'th basic block in this source file. */
826 #define BLOCK_PROFILER(FILE, BLOCKNO) \
828 int blockn = (BLOCKNO); \
829 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
830 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
831 4 * blockn, 4 * blockn, 4 * blockn); \
834 /* Output rtl to increment the entry-count for the LABELNO'th instrumented
835 arc in this source file. */
837 #define ARC_PROFILER(ARCNO, INSERT_AFTER) \
838 output_arc_profiler (ARCNO, INSERT_AFTER)
840 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
841 the stack pointer does not matter. The value is tested only in
842 functions that have frame pointers.
843 No definition is equivalent to always zero. */
845 extern int current_function_calls_alloca
;
846 extern int current_function_outgoing_args_size
;
848 #define EXIT_IGNORE_STACK \
849 (get_frame_size () != 0 \
850 || current_function_calls_alloca || current_function_outgoing_args_size)
852 /* This macro generates the assembly code for function exit,
853 on machines that need it. If FUNCTION_EPILOGUE is not defined
854 then individual return instructions are generated for each
855 return statement. Args are same as for FUNCTION_PROLOGUE.
857 The function epilogue should not depend on the current stack pointer!
858 It should use the frame pointer only. This is mandatory because
859 of alloca; we also take advantage of it to omit stack adjustments
862 /* This declaration is needed due to traditional/ANSI
863 incompatibilities which cannot be #ifdefed away
864 because they occur inside of macros. Sigh. */
865 extern union tree_node
*current_function_decl
;
867 #define FUNCTION_EPILOGUE(FILE, SIZE) \
868 output_function_epilogue (FILE, SIZE, leaf_function, 1)
870 #define DELAY_SLOTS_FOR_EPILOGUE 1
871 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
872 eligible_for_epilogue_delay (trial, slots_filled)
874 /* Output assembler code for a block containing the constant parts
875 of a trampoline, leaving space for the variable parts. */
877 /* On the sparc, the trampoline contains five instructions:
878 sethi #TOP_OF_FUNCTION,%g2
879 or #BOTTOM_OF_FUNCTION,%g2,%g2
880 sethi #TOP_OF_STATIC,%g1
882 or #BOTTOM_OF_STATIC,%g1,%g1 */
883 #define TRAMPOLINE_TEMPLATE(FILE) \
885 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
886 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
887 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
888 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
889 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
892 /* Length in units of the trampoline for entering a nested function. */
894 #define TRAMPOLINE_SIZE 20
896 /* Emit RTL insns to initialize the variable parts of a trampoline.
897 FNADDR is an RTX for the address of the function's pure code.
898 CXT is an RTX for the static chain value for the function.
900 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
901 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
902 (to store insns). This is a bit excessive. Perhaps a different
903 mechanism would be better here. */
905 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
907 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
908 size_int (10), 0, 1); \
909 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
910 size_int (10), 0, 1); \
911 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
912 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
913 rtx g1_sethi = gen_rtx (HIGH, SImode, \
914 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
915 rtx g2_sethi = gen_rtx (HIGH, SImode, \
916 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
917 rtx g1_ori = gen_rtx (HIGH, SImode, \
918 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
919 rtx g2_ori = gen_rtx (HIGH, SImode, \
920 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
921 rtx tem = gen_reg_rtx (SImode); \
922 emit_move_insn (tem, g2_sethi); \
923 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
924 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
925 emit_move_insn (tem, g2_ori); \
926 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
927 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
928 emit_move_insn (tem, g1_sethi); \
929 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
930 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
931 emit_move_insn (tem, g1_ori); \
932 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
933 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
936 /* Emit code for a call to builtin_saveregs. We must emit USE insns which
937 reference the 6 input registers. Ordinarily they are not call used
938 registers, but they are for _builtin_saveregs, so we must make this
941 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) \
942 (emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, TImode, 24))), \
943 emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, DImode, 28))), \
944 expand_call (exp, target, ignore))
946 /* Addressing modes, and classification of registers for them. */
948 /* #define HAVE_POST_INCREMENT */
949 /* #define HAVE_POST_DECREMENT */
951 /* #define HAVE_PRE_DECREMENT */
952 /* #define HAVE_PRE_INCREMENT */
954 /* Macros to check register numbers against specific register classes. */
956 /* These assume that REGNO is a hard or pseudo reg number.
957 They give nonzero only if REGNO is a hard reg of the suitable class
958 or a pseudo reg currently allocated to a suitable hard reg.
959 Since they use reg_renumber, they are safe only once reg_renumber
960 has been allocated, which happens in local-alloc.c. */
962 #define REGNO_OK_FOR_INDEX_P(REGNO) \
963 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
964 #define REGNO_OK_FOR_BASE_P(REGNO) \
965 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
966 #define REGNO_OK_FOR_FP_P(REGNO) \
967 (((REGNO) ^ 0x20) < 32 \
968 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
970 /* Now macros that check whether X is a register and also,
971 strictly, whether it is in a specified class.
973 These macros are specific to the SPARC, and may be used only
974 in code for printing assembler insns and in conditions for
975 define_optimization. */
977 /* 1 if X is an fp register. */
979 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
981 /* Maximum number of registers that can appear in a valid memory address. */
983 #define MAX_REGS_PER_ADDRESS 2
985 /* Recognize any constant value that is a valid address. */
987 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
989 /* Nonzero if the constant value X is a legitimate general operand.
990 Anything can be made to work except floating point constants. */
992 #define LEGITIMATE_CONSTANT_P(X) \
993 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
995 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
996 and check its validity for a certain class.
997 We have two alternate definitions for each of them.
998 The usual definition accepts all pseudo regs; the other rejects
999 them unless they have been allocated suitable hard regs.
1000 The symbol REG_OK_STRICT causes the latter definition to be used.
1002 Most source files want to accept pseudo regs in the hope that
1003 they will get allocated to the class that the insn wants them to be in.
1004 Source files for reload pass need to be strict.
1005 After reload, it makes no difference, since pseudo regs have
1006 been eliminated by then. */
1008 /* Optional extra constraints for this machine. Borrowed from romp.h.
1010 For the SPARC, `Q' means that this is a memory operand but not a
1011 symbolic memory operand. Note that an unassigned pseudo register
1012 is such a memory operand. Needed because reload will generate
1013 these things in insns and then not re-recognize the insns, causing
1014 constrain_operands to fail.
1016 `R' handles the LO_SUM which can be an address for `Q'.
1018 `S' handles constraints for calls. */
1020 #ifndef REG_OK_STRICT
1022 /* Nonzero if X is a hard reg that can be used as an index
1023 or if it is a pseudo reg. */
1024 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1025 /* Nonzero if X is a hard reg that can be used as a base reg
1026 or if it is a pseudo reg. */
1027 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1029 #define EXTRA_CONSTRAINT(OP, C) \
1031 ((GET_CODE (OP) == MEM \
1032 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1033 && ! symbolic_memory_operand (OP, VOIDmode))) \
1035 (GET_CODE (OP) == LO_SUM \
1036 && GET_CODE (XEXP (OP, 0)) == REG \
1037 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1039 ? CONSTANT_P (OP) || memory_address_p (Pmode, OP) : 0)))
1043 /* Nonzero if X is a hard reg that can be used as an index. */
1044 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1045 /* Nonzero if X is a hard reg that can be used as a base reg. */
1046 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1048 #define EXTRA_CONSTRAINT(OP, C) \
1050 (GET_CODE (OP) == REG ? \
1051 (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1052 && reg_renumber[REGNO (OP)] < 0) \
1053 : GET_CODE (OP) == MEM) \
1055 (GET_CODE (OP) == LO_SUM \
1056 && GET_CODE (XEXP (OP, 0)) == REG \
1057 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1059 ? (CONSTANT_P (OP) \
1060 || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\
1061 || strict_memory_address_p (Pmode, OP)) : 0)))
1064 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1065 that is a valid memory address for an instruction.
1066 The MODE argument is the machine mode for the MEM expression
1067 that wants to use this address.
1069 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1070 ordinarily. This changes a bit when generating PIC.
1072 If you change this, execute "rm explow.o recog.o reload.o". */
1074 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1075 { if (GET_CODE (X) == REG) \
1076 { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \
1077 else if (GET_CODE (X) == PLUS) \
1079 if (flag_pic && XEXP (X, 0) == pic_offset_table_rtx)\
1081 if (GET_CODE (XEXP (X, 1)) == REG \
1082 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1084 else if (flag_pic == 1 \
1085 && GET_CODE (XEXP (X, 1)) != REG \
1086 && GET_CODE (XEXP (X, 1)) != LO_SUM \
1087 && GET_CODE (XEXP (X, 1)) != MEM) \
1090 else if (GET_CODE (XEXP (X, 0)) == REG \
1091 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1093 if (GET_CODE (XEXP (X, 1)) == REG \
1094 && REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
1096 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1097 && INTVAL (XEXP (X, 1)) >= -0x1000 \
1098 && INTVAL (XEXP (X, 1)) < 0x1000) \
1101 else if (GET_CODE (XEXP (X, 1)) == REG \
1102 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1104 if (GET_CODE (XEXP (X, 0)) == REG \
1105 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1107 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1108 && INTVAL (XEXP (X, 0)) >= -0x1000 \
1109 && INTVAL (XEXP (X, 0)) < 0x1000) \
1113 else if (GET_CODE (X) == LO_SUM \
1114 && GET_CODE (XEXP (X, 0)) == REG \
1115 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1116 && CONSTANT_P (XEXP (X, 1))) \
1118 else if (GET_CODE (X) == LO_SUM \
1119 && GET_CODE (XEXP (X, 0)) == SUBREG \
1120 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG\
1121 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0)))\
1122 && CONSTANT_P (XEXP (X, 1))) \
1124 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1128 /* Try machine-dependent ways of modifying an illegitimate address
1129 to be legitimate. If we find one, return the new, valid address.
1130 This macro is used in only one place: `memory_address' in explow.c.
1132 OLDX is the address as it was before break_out_memory_refs was called.
1133 In some cases it is useful to look at this to decide what needs to be done.
1135 MODE and WIN are passed so that this macro can use
1136 GO_IF_LEGITIMATE_ADDRESS.
1138 It is always safe for this macro to do nothing. It exists to recognize
1139 opportunities to optimize the output. */
1141 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1142 extern struct rtx_def
*legitimize_pic_address ();
1143 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1144 { rtx sparc_x = (X); \
1145 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1146 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1147 force_operand (XEXP (X, 0), 0)); \
1148 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1149 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1150 force_operand (XEXP (X, 1), 0)); \
1151 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1152 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), 0),\
1154 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1155 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1156 force_operand (XEXP (X, 1), 0)); \
1157 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1159 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1160 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1161 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1162 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1163 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1164 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1165 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1166 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1167 || GET_CODE (X) == LABEL_REF) \
1168 (X) = gen_rtx (LO_SUM, Pmode, \
1169 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1170 if (memory_address_p (MODE, X)) \
1173 /* Go to LABEL if ADDR (a legitimate address expression)
1174 has an effect that depends on the machine mode it is used for.
1175 On the SPARC this is never true. */
1177 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1179 /* Specify the machine mode that this machine uses
1180 for the index in the tablejump instruction. */
1181 #define CASE_VECTOR_MODE SImode
1183 /* Define this if the tablejump instruction expects the table
1184 to contain offsets from the address of the table.
1185 Do not define this if the table should contain absolute addresses. */
1186 /* #define CASE_VECTOR_PC_RELATIVE */
1188 /* Specify the tree operation to be used to convert reals to integers. */
1189 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1191 /* This is the kind of divide that is easiest to do in the general case. */
1192 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1194 /* Define this as 1 if `char' should by default be signed; else as 0. */
1195 #define DEFAULT_SIGNED_CHAR 1
1197 /* Max number of bytes we can move from memory to memory
1198 in one reasonably fast instruction. */
1201 /* Define if normal loads of shorter-than-word items from memory clears
1202 the rest of the bigs in the register. */
1203 #define BYTE_LOADS_ZERO_EXTEND
1205 /* Nonzero if access to memory by bytes is slow and undesirable.
1206 For RISC chips, it means that access to memory by bytes is no
1207 better than access by words when possible, so grab a whole word
1208 and maybe make use of that. */
1209 #define SLOW_BYTE_ACCESS 1
1211 /* We assume that the store-condition-codes instructions store 0 for false
1212 and some other value for true. This is the value stored for true. */
1214 #define STORE_FLAG_VALUE 1
1216 /* When a prototype says `char' or `short', really pass an `int'. */
1217 #define PROMOTE_PROTOTYPES
1219 /* Define if shifts truncate the shift count
1220 which implies one can omit a sign-extension or zero-extension
1221 of a shift count. */
1222 #define SHIFT_COUNT_TRUNCATED
1224 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1225 is done just by pretending it is already truncated. */
1226 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1228 /* Specify the machine mode that pointers have.
1229 After generation of rtl, the compiler makes no further distinction
1230 between pointers and any other objects of this machine mode. */
1231 #define Pmode SImode
1233 /* Generate calls to memcpy, memcmp and memset. */
1234 #define TARGET_MEM_FUNCTIONS
1236 /* Add any extra modes needed to represent the condition code.
1238 On the Sparc, we have a "no-overflow" mode which is used when an add or
1239 subtract insn is used to set the condition code. Different branches are
1240 used in this case for some operations.
1242 We also have a mode to indicate that the relevant condition code is
1243 in the floating-point condition code. This really should be a separate
1244 register, but we don't want to go to 65 registers. */
1245 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode
1247 /* Define the names for the modes specified above. */
1248 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP"
1250 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1251 return the mode to be used for the comparison. For floating-point, CCFPmode
1252 should be used. CC_NOOVmode should be used when the first operand is a
1253 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1255 #define SELECT_CC_MODE(OP,X) \
1256 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
1257 : (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1258 ? CC_NOOVmode : CCmode)
1260 /* A function address in a call instruction
1261 is a byte address (for indexing purposes)
1262 so give the MEM rtx a byte's mode. */
1263 #define FUNCTION_MODE SImode
1265 /* Define this if addresses of constant functions
1266 shouldn't be put through pseudo regs where they can be cse'd.
1267 Desirable on machines where ordinary constants are expensive
1268 but a CALL with constant address is cheap. */
1269 #define NO_FUNCTION_CSE
1271 /* alloca should avoid clobbering the old register save area. */
1272 #define SETJMP_VIA_SAVE_AREA
1274 /* Define subroutines to call to handle multiply and divide.
1275 Use the subroutines that Sun's library provides.
1276 The `*' prevents an underscore from being prepended by the compiler. */
1278 #define DIVSI3_LIBCALL "*.div"
1279 #define UDIVSI3_LIBCALL "*.udiv"
1280 #define MODSI3_LIBCALL "*.rem"
1281 #define UMODSI3_LIBCALL "*.urem"
1282 /* .umul is a little faster than .mul. */
1283 #define MULSI3_LIBCALL "*.umul"
1285 /* Compute the cost of computing a constant rtl expression RTX
1286 whose rtx-code is CODE. The body of this macro is a portion
1287 of a switch statement. If the code is computed here,
1288 return it with a return statement. Otherwise, break from the switch. */
1290 #define CONST_COSTS(RTX,CODE) \
1292 if (INTVAL (RTX) == 0) \
1294 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1302 case CONST_DOUBLE: \
1303 if (GET_MODE (RTX) == DImode) \
1304 if ((XINT (RTX, 3) == 0 \
1305 && (unsigned) XINT (RTX, 2) < 0x1000) \
1306 || (XINT (RTX, 3) == -1 \
1307 && XINT (RTX, 2) < 0 \
1308 && XINT (RTX, 2) >= -0x1000)) \
1312 /* SPARC offers addressing modes which are "as cheap as a register".
1313 See sparc.c (or gcc.texinfo) for details. */
1315 #define ADDRESS_COST(RTX) \
1316 (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1318 /* Compute extra cost of moving data between one register class
1320 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1321 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1322 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1324 /* Provide the costs of a rtl expression. This is in the body of a
1325 switch on CODE. The purpose for the cost of MULT is to encourage
1326 `synth_mult' to find a synthetic multiply when reasonable.
1328 If we need more than 12 insns to do a multiply, then go out-of-line,
1329 since the call overhead will be < 10% of the cost of the multiply. */
1331 #define RTX_COSTS(X,CODE) \
1333 return COSTS_N_INSNS (25); \
1338 return COSTS_N_INSNS (20); \
1339 /* Make FLOAT more expensive than CONST_DOUBLE, \
1340 so that cse will favor the latter. */ \
1344 /* Conditional branches with empty delay slots have a length of two. */
1345 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1346 if (GET_CODE (INSN) == CALL_INSN \
1347 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1350 /* Control the assembler format that we output. */
1352 /* Output at beginning of assembler file. */
1354 #define ASM_FILE_START(file)
1356 /* Output to assembler file text saying following lines
1357 may contain character constants, extra white space, comments, etc. */
1359 #define ASM_APP_ON ""
1361 /* Output to assembler file text saying following lines
1362 no longer contain unusual constructs. */
1364 #define ASM_APP_OFF ""
1366 /* Output before read-only data. */
1368 #define TEXT_SECTION_ASM_OP ".text"
1370 /* Output before writable data. */
1372 #define DATA_SECTION_ASM_OP ".data"
1374 /* How to refer to registers in assembler output.
1375 This sequence is indexed by compiler's hard-register-number (see above). */
1377 #define REGISTER_NAMES \
1378 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1379 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1380 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1381 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1382 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1383 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1384 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1385 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1387 /* How to renumber registers for dbx and gdb. */
1389 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1391 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1392 since the length can run past this up to a continuation point. */
1393 #define DBX_CONTIN_LENGTH 1500
1395 /* This is how to output a note to DBX telling it the line number
1396 to which the following sequence of instructions corresponds.
1398 This is needed for SunOS 4.0, and should not hurt for 3.2
1400 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1401 { static int sym_lineno = 1; \
1402 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1403 line, sym_lineno, sym_lineno); \
1406 /* This is how to output the definition of a user-level label named NAME,
1407 such as the label on a static function or variable NAME. */
1409 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1410 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1412 /* This is how to output a command to make the user-level label named NAME
1413 defined for reference from other files. */
1415 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1416 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1418 /* This is how to output a reference to a user-level label named NAME.
1419 `assemble_name' uses this. */
1421 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1422 fprintf (FILE, "_%s", NAME)
1424 /* This is how to output an internal numbered label where
1425 PREFIX is the class of label and NUM is the number within the class. */
1427 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1428 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1430 /* This is how to store into the string LABEL
1431 the symbol_ref name of an internal numbered label where
1432 PREFIX is the class of label and NUM is the number within the class.
1433 This is suitable for output with `assemble_name'. */
1435 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1436 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1438 /* This is how to output an assembler line defining a `double' constant. */
1440 /* Assemblers (both gas 1.35 and as in 4.0.3)
1441 seem to treat -0.0 as if it were 0.0.
1442 They reject 99e9999, but accept inf. */
1443 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1445 if (REAL_VALUE_ISINF (VALUE)) \
1446 fprintf (FILE, "\t.double 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1447 else if (REAL_VALUE_ISNAN (VALUE) \
1448 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1450 union { double d; long l[2];} t; \
1452 fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t.l[0], t.l[1]); \
1455 fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1458 /* This is how to output an assembler line defining a `float' constant. */
1460 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1462 if (REAL_VALUE_ISINF (VALUE)) \
1463 fprintf (FILE, "\t.single 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1464 else if (REAL_VALUE_ISNAN (VALUE) \
1465 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1467 union { float f; long l;} t; \
1469 fprintf (FILE, "\t.word 0x%lx\n", t.l); \
1472 fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1475 /* This is how to output an assembler line defining an `int' constant. */
1477 #define ASM_OUTPUT_INT(FILE,VALUE) \
1478 ( fprintf (FILE, "\t.word "), \
1479 output_addr_const (FILE, (VALUE)), \
1480 fprintf (FILE, "\n"))
1482 /* This is how to output an assembler line defining a DImode constant. */
1483 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1484 output_double_int (FILE, VALUE)
1486 /* Likewise for `char' and `short' constants. */
1488 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1489 ( fprintf (FILE, "\t.half "), \
1490 output_addr_const (FILE, (VALUE)), \
1491 fprintf (FILE, "\n"))
1493 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1494 ( fprintf (FILE, "\t.byte "), \
1495 output_addr_const (FILE, (VALUE)), \
1496 fprintf (FILE, "\n"))
1498 /* This is how to output an assembler line for a numeric constant byte. */
1500 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1501 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1503 /* This is how to output an element of a case-vector that is absolute. */
1505 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1508 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1509 fprintf (FILE, "\t.word\t"); \
1510 assemble_name (FILE, label); \
1511 fprintf (FILE, "\n"); \
1514 /* This is how to output an element of a case-vector that is relative.
1515 (SPARC uses such vectors only when generating PIC.) */
1517 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1520 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1521 fprintf (FILE, "\t.word\t"); \
1522 assemble_name (FILE, label); \
1523 fprintf (FILE, "-1b\n"); \
1526 /* This is how to output an assembler line
1527 that says to advance the location counter
1528 to a multiple of 2**LOG bytes. */
1530 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1532 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1534 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1535 fprintf (FILE, "\t.skip %u\n", (SIZE))
1537 /* This says how to output an assembler line
1538 to define a global common symbol. */
1540 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1541 ( fputs ("\t.global ", (FILE)), \
1542 assemble_name ((FILE), (NAME)), \
1543 fputs ("\n\t.common ", (FILE)), \
1544 assemble_name ((FILE), (NAME)), \
1545 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1547 /* This says how to output an assembler line
1548 to define a local common symbol. */
1550 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1551 ( fputs ("\n\t.reserve ", (FILE)), \
1552 assemble_name ((FILE), (NAME)), \
1553 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1555 /* Store in OUTPUT a string (made with alloca) containing
1556 an assembler-name for a local static variable named NAME.
1557 LABELNO is an integer which is different for each call. */
1559 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1560 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1561 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1563 /* Define the parentheses used to group arithmetic operations
1564 in assembler code. */
1566 #define ASM_OPEN_PAREN "("
1567 #define ASM_CLOSE_PAREN ")"
1569 /* Define results of standard character escape sequences. */
1570 #define TARGET_BELL 007
1571 #define TARGET_BS 010
1572 #define TARGET_TAB 011
1573 #define TARGET_NEWLINE 012
1574 #define TARGET_VT 013
1575 #define TARGET_FF 014
1576 #define TARGET_CR 015
1578 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1579 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1581 /* Print operand X (an rtx) in assembler syntax to file FILE.
1582 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1583 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1585 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1587 /* Print a memory address as an operand to reference that memory location. */
1589 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1590 { register rtx base, index = 0; \
1592 register rtx addr = ADDR; \
1593 if (GET_CODE (addr) == REG) \
1594 fputs (reg_names[REGNO (addr)], FILE); \
1595 else if (GET_CODE (addr) == PLUS) \
1597 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1598 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1599 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1600 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1602 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1603 fputs (reg_names[REGNO (base)], FILE); \
1605 fprintf (FILE, "%+d", offset); \
1606 else if (GET_CODE (index) == REG) \
1607 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1608 else if (GET_CODE (index) == SYMBOL_REF) \
1609 fputc ('+', FILE), output_addr_const (FILE, index); \
1612 else if (GET_CODE (addr) == MINUS \
1613 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1615 output_addr_const (FILE, XEXP (addr, 0)); \
1616 fputs ("-(", FILE); \
1617 output_addr_const (FILE, XEXP (addr, 1)); \
1618 fputs ("-.)", FILE); \
1620 else if (GET_CODE (addr) == LO_SUM) \
1622 output_operand (XEXP (addr, 0), 0); \
1623 fputs ("+%lo(", FILE); \
1624 output_address (XEXP (addr, 1)); \
1625 fputc (')', FILE); \
1627 else if (flag_pic && GET_CODE (addr) == CONST \
1628 && GET_CODE (XEXP (addr, 0)) == MINUS \
1629 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1630 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1631 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1633 addr = XEXP (addr, 0); \
1634 output_addr_const (FILE, XEXP (addr, 0)); \
1635 /* Group the args of the second CONST in parenthesis. */ \
1636 fputs ("-(", FILE); \
1637 /* Skip past the second CONST--it does nothing for us. */\
1638 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1639 /* Close the parenthesis. */ \
1640 fputc (')', FILE); \
1644 output_addr_const (FILE, addr); \
1648 /* Declare functions defined in sparc.c and used in templates. */
1650 extern char *singlemove_string ();
1651 extern char *output_move_double ();
1652 extern char *output_fp_move_double ();
1653 extern char *output_block_move ();
1654 extern char *output_scc_insn ();
1655 extern char *output_cbranch ();
1656 extern char *output_return ();
1657 extern char *output_floatsisf2 ();
1658 extern char *output_floatsidf2 ();
1660 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1662 extern int flag_pic
;