1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
26 /* Provide required defaults for linker -e and -d switches. */
29 "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
31 /* Special flags to the Sun-4 assembler when using pipe for input. */
33 #define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}"
35 /* Define macros to distinguish architectures. */
36 #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mv8:-D__sparcv8__}"
38 /* Prevent error on `-sun4' and `-target sun4' options. */
39 /* This used to translate -dalign to -malign, but that is no good
40 because it can't turn off the usual meaning of making debugging dumps. */
42 #define CC1_SPEC "%{sun4:} %{target:}"
45 /* Sparc ABI says that long double is 4 words.
46 ??? This doesn't work yet. */
47 #define LONG_DOUBLE_TYPE_SIZE 128
50 #define PTRDIFF_TYPE "int"
51 #define SIZE_TYPE "int"
52 #define WCHAR_TYPE "short unsigned int"
53 #define WCHAR_TYPE_SIZE 16
55 /* Omit frame pointer at high optimization levels. */
57 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
61 flag_omit_frame_pointer = 1; \
65 /* These compiler options take an argument. We ignore -target for now. */
67 #define WORD_SWITCH_TAKES_ARG(STR) \
68 (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \
69 || !strcmp (STR, "imacros") || !strcmp (STR, "target") \
70 || !strcmp (STR, "assert") || !strcmp (STR, "aux-info"))
72 /* Names to predefine in the preprocessor for this target machine. */
74 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix"
76 /* Print subsidiary information on the compiler version in use. */
78 #define TARGET_VERSION fprintf (stderr, " (sparc)");
80 /* Generate DBX debugging information. */
82 #define DBX_DEBUGGING_INFO
84 /* Run-time compilation parameters selecting different hardware subsets. */
86 extern int target_flags
;
88 /* Nonzero if we should generate code to use the fpu. */
89 #define TARGET_FPU (target_flags & 1)
91 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
92 use fast return insns, but lose some generality. */
93 #define TARGET_EPILOGUE (target_flags & 2)
95 /* Nonzero means that reference doublewords as if they were guaranteed
96 to be aligned...if they aren't, too bad for the user!
97 Like -dalign in Sun cc. */
98 #define TARGET_HOPE_ALIGN (target_flags & 16)
100 /* Nonzero means make sure all doubles are on 8-byte boundaries.
101 This option results in a calling convention that is incompatible with
102 every other sparc compiler in the world, and thus should only ever be
103 used for experimenting. Also, varargs won't work with it, but it doesn't
104 seem worth trying to fix. */
105 #define TARGET_FORCE_ALIGN (target_flags & 32)
107 /* Nonzero means that we should generate code for a v8 sparc. */
108 #define TARGET_V8 (target_flags & 64)
110 /* Nonzero means that we should generate code for a sparclite. */
111 #define TARGET_SPARCLITE (target_flags & 128)
113 /* Macro to define tables used to set the flags.
114 This is a list in braces of pairs in braces,
115 each pair being { "NAME", VALUE }
116 where VALUE is the bits to set or minus the bits to clear.
117 An empty string NAME is used to identify the default VALUE. */
119 #define TARGET_SWITCHES \
121 {"soft-float", -1}, \
123 {"no-epilogue", -2}, \
124 {"hope-align", 16}, \
125 {"force-align", 48}, \
128 {"sparclite", 128}, \
129 {"no-sparclite", -128}, \
130 { "", TARGET_DEFAULT}}
132 #define TARGET_DEFAULT 3
134 /* target machine storage layout */
136 /* Define this if most significant bit is lowest numbered
137 in instructions that operate on numbered bit-fields. */
138 #define BITS_BIG_ENDIAN 1
140 /* Define this if most significant byte of a word is the lowest numbered. */
141 /* This is true on the SPARC. */
142 #define BYTES_BIG_ENDIAN 1
144 /* Define this if most significant word of a multiword number is the lowest
146 /* Doubles are stored in memory with the high order word first. This
147 matters when cross-compiling. */
148 #define WORDS_BIG_ENDIAN 1
150 /* number of bits in an addressable storage unit */
151 #define BITS_PER_UNIT 8
153 /* Width in bits of a "word", which is the contents of a machine register.
154 Note that this is not necessarily the width of data type `int';
155 if using 16-bit ints on a 68000, this would still be 32.
156 But on a machine with 16-bit registers, this would be 16. */
157 #define BITS_PER_WORD 32
158 #define MAX_BITS_PER_WORD 32
160 /* Width of a word, in units (bytes). */
161 #define UNITS_PER_WORD 4
163 /* Width in bits of a pointer.
164 See also the macro `Pmode' defined below. */
165 #define POINTER_SIZE 32
167 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
168 #define PARM_BOUNDARY 32
170 /* Boundary (in *bits*) on which stack pointer should be aligned. */
171 #define STACK_BOUNDARY 64
173 /* ALIGN FRAMES on double word boundaries */
175 #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
177 /* Allocation boundary (in *bits*) for the code of a function. */
178 #define FUNCTION_BOUNDARY 32
180 /* Alignment of field after `int : 0' in a structure. */
181 #define EMPTY_FIELD_BOUNDARY 32
183 /* Every structure's size must be a multiple of this. */
184 #define STRUCTURE_SIZE_BOUNDARY 8
186 /* A bitfield declared as `int' forces `int' alignment for the struct. */
187 #define PCC_BITFIELD_TYPE_MATTERS 1
189 /* No data type wants to be aligned rounder than this. */
190 #define BIGGEST_ALIGNMENT 64
192 /* The best alignment to use in cases where we have a choice. */
193 #define FASTEST_ALIGNMENT 64
195 /* Make strings word-aligned so strcpy from constants will be faster. */
196 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
197 (TREE_CODE (EXP) == STRING_CST \
198 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
200 /* Make arrays of chars word-aligned for the same reasons. */
201 #define DATA_ALIGNMENT(TYPE, ALIGN) \
202 (TREE_CODE (TYPE) == ARRAY_TYPE \
203 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
204 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
206 /* Set this nonzero if move instructions will actually fail to work
207 when given unaligned data. */
208 #define STRICT_ALIGNMENT 1
210 /* Things that must be doubleword aligned cannot go in the text section,
211 because the linker fails to align the text section enough!
212 Put them in the data section. */
213 #define MAX_TEXT_ALIGN 32
215 #define SELECT_SECTION(T,RELOC) \
217 if (TREE_CODE (T) == VAR_DECL) \
219 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
220 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
221 && ! (flag_pic && (RELOC))) \
226 else if (TREE_CODE (T) == CONSTRUCTOR) \
228 if (flag_pic != 0 && (RELOC) != 0) \
231 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
233 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
234 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
241 /* Use text section for a constant
242 unless we need more alignment than that offers. */
243 #define SELECT_RTX_SECTION(MODE, X) \
245 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
246 && ! (flag_pic && symbolic_operand (X))) \
252 /* Standard register usage. */
254 /* Number of actual hardware registers.
255 The hardware registers are assigned numbers for the compiler
256 from 0 to just below FIRST_PSEUDO_REGISTER.
257 All registers that the compiler knows about must be given numbers,
258 even those that are not normally considered general registers.
260 SPARC has 32 integer registers and 32 floating point registers. */
262 #define FIRST_PSEUDO_REGISTER 64
264 /* 1 for registers that have pervasive standard uses
265 and are not available for the register allocator.
266 0 is used for the condition code and not to represent %g0, which is
267 hardwired to 0, so reg 0 is *not* fixed.
268 g1 through g4 are free to use as temporaries.
269 g5 through g7 are reserved for the operating system. */
270 #define FIXED_REGISTERS \
271 {0, 0, 0, 0, 0, 1, 1, 1, \
272 0, 0, 0, 0, 0, 0, 1, 0, \
273 0, 0, 0, 0, 0, 0, 0, 0, \
274 0, 0, 0, 0, 0, 0, 1, 1, \
276 0, 0, 0, 0, 0, 0, 0, 0, \
277 0, 0, 0, 0, 0, 0, 0, 0, \
278 0, 0, 0, 0, 0, 0, 0, 0, \
279 0, 0, 0, 0, 0, 0, 0, 0}
281 /* 1 for registers not available across function calls.
282 These must include the FIXED_REGISTERS and also any
283 registers that can be used without being saved.
284 The latter must include the registers where values are returned
285 and the register where structure-value addresses are passed.
286 Aside from that, you can include as many other registers as you like. */
287 #define CALL_USED_REGISTERS \
288 {1, 1, 1, 1, 1, 1, 1, 1, \
289 1, 1, 1, 1, 1, 1, 1, 1, \
290 0, 0, 0, 0, 0, 0, 0, 0, \
291 0, 0, 0, 0, 0, 0, 1, 1, \
293 1, 1, 1, 1, 1, 1, 1, 1, \
294 1, 1, 1, 1, 1, 1, 1, 1, \
295 1, 1, 1, 1, 1, 1, 1, 1, \
296 1, 1, 1, 1, 1, 1, 1, 1}
298 /* Return number of consecutive hard regs needed starting at reg REGNO
299 to hold something of mode MODE.
300 This is ordinarily the length in words of a value of mode MODE
301 but can be less for certain modes in special long registers.
303 On SPARC, ordinary registers hold 32 bits worth;
304 this means both integer and floating point registers.
306 We use vectors to keep this information about registers. */
308 /* How many hard registers it takes to make a register of this mode. */
309 extern int hard_regno_nregs
[];
311 #define HARD_REGNO_NREGS(REGNO, MODE) \
312 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
314 /* Value is 1 if register/mode pair is acceptable on sparc. */
315 extern int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
317 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
318 On SPARC, the cpu registers can hold any mode but the float registers
319 can only hold SFmode or DFmode. See sparc.c for how we
321 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
322 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
324 /* Value is 1 if it is a good idea to tie two pseudo registers
325 when one has mode MODE1 and one has mode MODE2.
326 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
327 for any hard reg, then this must be 0 for correct output. */
328 #define MODES_TIEABLE_P(MODE1, MODE2) \
329 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
331 /* Specify the registers used for certain standard purposes.
332 The values of these macros are register numbers. */
334 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
335 /* #define PC_REGNUM */
337 /* Register to use for pushing function arguments. */
338 #define STACK_POINTER_REGNUM 14
340 /* Actual top-of-stack address is 92 greater than the contents
341 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
342 for the ins and local registers, 4 byte for structure return address, and
343 24 bytes for the 6 register parameters. */
344 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
346 /* Base register for access to local variables of the function. */
347 #define FRAME_POINTER_REGNUM 30
350 /* Register that is used for the return address. */
351 #define RETURN_ADDR_REGNUM 15
354 /* Value should be nonzero if functions must have frame pointers.
355 Zero means the frame pointer need not be set up (and parms
356 may be accessed via the stack pointer) in functions that seem suitable.
357 This is computed in `reload', in reload1.c.
359 Used in flow.c, global-alloc.c, and reload1.c. */
360 extern int leaf_function
;
362 #define FRAME_POINTER_REQUIRED \
363 (! (leaf_function_p () && only_leaf_regs_used ()))
365 /* C statement to store the difference between the frame pointer
366 and the stack pointer values immediately after the function prologue.
368 Note, we always pretend that this is a leaf function because if
369 it's not, there's no point in trying to eliminate the
370 frame pointer. If it is a leaf function, we guessed right! */
371 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
372 do { (VAR) = compute_frame_size (get_frame_size (), 1); } while (0)
374 /* Base register for access to arguments of the function. */
375 #define ARG_POINTER_REGNUM 30
377 /* Register in which static-chain is passed to a function. */
379 #define STATIC_CHAIN_REGNUM 1
381 /* Register which holds offset table for position-independent
384 #define PIC_OFFSET_TABLE_REGNUM 23
386 #define INITIALIZE_PIC initialize_pic ()
387 #define FINALIZE_PIC finalize_pic ()
389 /* Sparc ABI says that quad-precision floats and all structures are returned
390 in memory. We go along regarding floats, but for structures
391 we follow GCC's normal policy. Use -fpcc-struct-value
392 if you want to follow the ABI. */
393 #define RETURN_IN_MEMORY(TYPE) \
394 (TYPE_MODE (TYPE) == TFmode)
396 /* Functions which return large structures get the address
397 to place the wanted value at offset 64 from the frame.
398 Must reserve 64 bytes for the in and local registers. */
399 /* Used only in other #defines in this file. */
400 #define STRUCT_VALUE_OFFSET 64
402 #define STRUCT_VALUE \
403 gen_rtx (MEM, Pmode, \
404 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
405 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
406 #define STRUCT_VALUE_INCOMING \
407 gen_rtx (MEM, Pmode, \
408 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
409 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
411 /* Define the classes of registers for register constraints in the
412 machine description. Also define ranges of constants.
414 One of the classes must always be named ALL_REGS and include all hard regs.
415 If there is more than one class, another class must be named NO_REGS
416 and contain no registers.
418 The name GENERAL_REGS must be the name of a class (or an alias for
419 another name such as ALL_REGS). This is the class of registers
420 that is allowed by "g" or "r" in a register constraint.
421 Also, registers outside this class are allocated only when
422 instructions express preferences for them.
424 The classes must be numbered in nondecreasing order; that is,
425 a larger-numbered class must never be contained completely
426 in a smaller-numbered class.
428 For any two classes, it is very desirable that there be another
429 class that represents their union. */
431 /* The SPARC has two kinds of registers, general and floating point. */
433 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
435 #define N_REG_CLASSES (int) LIM_REG_CLASSES
437 /* Give names of register classes as strings for dump file. */
439 #define REG_CLASS_NAMES \
440 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
442 /* Define which registers fit in which classes.
443 This is an initializer for a vector of HARD_REG_SET
444 of length N_REG_CLASSES. */
446 #if 0 && defined (__GNUC__)
447 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
449 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
452 /* The same information, inverted:
453 Return the class number of the smallest class containing
454 reg number REGNO. This could be a conditional expression
455 or could index an array. */
457 #define REGNO_REG_CLASS(REGNO) \
458 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
460 /* This is the order in which to allocate registers
462 #define REG_ALLOC_ORDER \
463 { 8, 9, 10, 11, 12, 13, 2, 3, \
464 15, 16, 17, 18, 19, 20, 21, 22, \
465 23, 24, 25, 26, 27, 28, 29, 31, \
466 32, 33, 34, 35, 36, 37, 38, 39, \
467 40, 41, 42, 43, 44, 45, 46, 47, \
468 48, 49, 50, 51, 52, 53, 54, 55, \
469 56, 57, 58, 59, 60, 61, 62, 63, \
470 1, 4, 5, 6, 7, 0, 14, 30}
472 /* This is the order in which to allocate registers for
473 leaf functions. If all registers can fit in the "i" registers,
474 then we have the possibility of having a leaf function. */
475 #define REG_LEAF_ALLOC_ORDER \
476 { 2, 3, 24, 25, 26, 27, 28, 29, \
477 15, 8, 9, 10, 11, 12, 13, \
478 16, 17, 18, 19, 20, 21, 22, 23, \
479 32, 33, 34, 35, 36, 37, 38, 39, \
480 40, 41, 42, 43, 44, 45, 46, 47, \
481 48, 49, 50, 51, 52, 53, 54, 55, \
482 56, 57, 58, 59, 60, 61, 62, 63, \
483 1, 4, 5, 6, 7, 0, 14, 30, 31}
485 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
487 #define LEAF_REGISTERS \
488 { 1, 1, 1, 1, 1, 1, 1, 1, \
489 0, 0, 0, 0, 0, 0, 1, 0, \
490 0, 0, 0, 0, 0, 0, 0, 0, \
491 1, 1, 1, 1, 1, 1, 0, 1, \
492 1, 1, 1, 1, 1, 1, 1, 1, \
493 1, 1, 1, 1, 1, 1, 1, 1, \
494 1, 1, 1, 1, 1, 1, 1, 1, \
495 1, 1, 1, 1, 1, 1, 1, 1}
497 extern char leaf_reg_remap
[];
498 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
499 extern char leaf_reg_backmap
[];
500 #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
502 #define REG_USED_SO_FAR(REGNO) \
503 ((REGNO) >= 24 && (REGNO) < 30 \
504 ? (regs_ever_live[24] \
505 || regs_ever_live[25] \
506 || regs_ever_live[26] \
507 || regs_ever_live[27] \
508 || regs_ever_live[28] \
509 || regs_ever_live[29]) : 0)
511 /* The class value for index registers, and the one for base regs. */
512 #define INDEX_REG_CLASS GENERAL_REGS
513 #define BASE_REG_CLASS GENERAL_REGS
515 /* Get reg_class from a letter such as appears in the machine description. */
517 #define REG_CLASS_FROM_LETTER(C) \
518 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
520 /* The letters I, J, K, L and M in a register constraint string
521 can be used to stand for particular ranges of immediate operands.
522 This macro defines what the ranges are.
523 C is the letter, and VALUE is a constant value.
524 Return 1 if VALUE is in the range specified by C.
526 For SPARC, `I' is used for the range of constants an insn
527 can actually contain.
528 `J' is used for the range which is just zero (since that is R0).
529 `K' is used for the 5-bit operand of a compare insns. */
531 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
533 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
534 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
535 : (C) == 'J' ? (VALUE) == 0 \
536 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
539 /* Similar, but for floating constants, and defining letters G and H.
540 Here VALUE is the CONST_DOUBLE rtx itself. */
542 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
543 ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
544 && CONST_DOUBLE_LOW (VALUE) == 0 \
545 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
548 /* Given an rtx X being reloaded into a reg required to be
549 in class CLASS, return the class of reg to actually use.
550 In general this is just CLASS; but on some machines
551 in some cases it is preferable to use a more restrictive class. */
552 /* We can't load constants into FP registers. We can't load any FP constant
553 if an 'E' constraint fails to match it. */
554 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
556 && ((CLASS) == FP_REGS \
557 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
558 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
559 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
562 /* Return the register class of a scratch register needed to load IN into
563 a register of class CLASS in MODE.
565 On the SPARC, when PIC, we need a temporary when loading some addresses
568 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
569 (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS : NO_REGS)
571 /* Return the maximum number of consecutive registers
572 needed to represent mode MODE in a register of class CLASS. */
573 /* On SPARC, this is the size of MODE in words. */
574 #define CLASS_MAX_NREGS(CLASS, MODE) \
575 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
577 /* Stack layout; function entry, exit and calling. */
579 /* Define the number of register that can hold parameters.
580 These two macros are used only in other macro definitions below. */
583 /* Define this if pushing a word on the stack
584 makes the stack pointer a smaller address. */
585 #define STACK_GROWS_DOWNWARD
587 /* Define this if the nominal address of the stack frame
588 is at the high-address end of the local variables;
589 that is, each additional local variable allocated
590 goes at a more negative offset in the frame. */
591 #define FRAME_GROWS_DOWNWARD
593 /* Offset within stack frame to start allocating local variables at.
594 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
595 first local allocated. Otherwise, it is the offset to the BEGINNING
596 of the first local allocated. */
597 #define STARTING_FRAME_OFFSET (-16)
599 /* If we generate an insn to push BYTES bytes,
600 this says how many the stack pointer really advances by.
601 On SPARC, don't define this because there are no push insns. */
602 /* #define PUSH_ROUNDING(BYTES) */
604 /* Offset of first parameter from the argument pointer register value.
605 This is 64 for the ins and locals, plus 4 for the struct-return reg
606 even if this function isn't going to use it.
607 If TARGET_FORCE_ALIGN, we must reserve 4 more bytes to ensure that the
608 stack remains aligned. */
609 #define FIRST_PARM_OFFSET(FNDECL) \
610 (STRUCT_VALUE_OFFSET + UNITS_PER_WORD + (TARGET_FORCE_ALIGN ? 4 : 0))
612 /* When a parameter is passed in a register, stack space is still
614 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
616 /* Keep the stack pointer constant throughout the function.
617 This is both an optimization and a necessity: longjmp
618 doesn't behave itself when the stack pointer moves within
620 #define ACCUMULATE_OUTGOING_ARGS
622 /* Value is the number of bytes of arguments automatically
623 popped when returning from a subroutine call.
624 FUNTYPE is the data type of the function (as a tree),
625 or for a library call it is an identifier node for the subroutine name.
626 SIZE is the number of bytes of arguments passed on the stack. */
628 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
630 /* Some subroutine macros specific to this machine. */
631 #define BASE_RETURN_VALUE_REG(MODE) \
632 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8)
633 #define BASE_OUTGOING_VALUE_REG(MODE) \
634 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24)
635 #define BASE_PASSING_ARG_REG(MODE) (8)
636 #define BASE_INCOMING_ARG_REG(MODE) (24)
638 /* Define how to find the value returned by a function.
639 VALTYPE is the data type of the value (as a tree).
640 If the precise function being called is known, FUNC is its FUNCTION_DECL;
641 otherwise, FUNC is 0. */
643 /* On SPARC the value is found in the first "output" register. */
645 #define FUNCTION_VALUE(VALTYPE, FUNC) \
646 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
648 /* But the called function leaves it in the first "input" register. */
650 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
651 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
653 /* Define how to find the value returned by a library function
654 assuming the value has mode MODE. */
656 #define LIBCALL_VALUE(MODE) \
657 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
659 /* 1 if N is a possible register number for a function value
660 as seen by the caller.
661 On SPARC, the first "output" reg is used for integer values,
662 and the first floating point register is used for floating point values. */
664 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
666 /* 1 if N is a possible register number for function argument passing.
667 On SPARC, these are the "output" registers. */
669 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
671 /* Define a data type for recording info about an argument list
672 during the scan of that argument list. This data type should
673 hold all necessary information about the function itself
674 and about the args processed so far, enough to enable macros
675 such as FUNCTION_ARG to determine where the next arg should go.
677 On SPARC, this is a single integer, which is a number of words
678 of arguments scanned so far (including the invisible argument,
679 if any, which holds the structure-value-address).
680 Thus 7 or more means all following args should go on the stack. */
682 #define CUMULATIVE_ARGS int
684 #define ROUND_ADVANCE(SIZE) \
685 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
687 /* Round a register number up to a proper boundary for an arg of mode MODE.
688 Note that we need an odd/even pair for a two-word arg,
689 since that will become 8-byte aligned when stored in memory. */
690 #define ROUND_REG(X, MODE) \
691 (TARGET_FORCE_ALIGN && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
692 ? ((X) + ! ((X) & 1)) : (X))
694 /* Initialize a variable CUM of type CUMULATIVE_ARGS
695 for a call to a function whose data type is FNTYPE.
696 For a library call, FNTYPE is 0.
698 On SPARC, the offset always starts at 0: the first parm reg is always
701 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
703 /* Update the data in CUM to advance over an argument
704 of mode MODE and data type TYPE.
705 (TYPE is null for libcalls where that information may not be available.) */
707 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
708 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
709 + ((MODE) != BLKmode \
710 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
711 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
713 /* Determine where to put an argument to a function.
714 Value is zero to push the argument on the stack,
715 or a hard register in which to store the argument.
717 MODE is the argument's machine mode.
718 TYPE is the data type of the argument (as a tree).
719 This is null for libcalls where that information may
721 CUM is a variable of type CUMULATIVE_ARGS which gives info about
722 the preceding args and about the function being called.
723 NAMED is nonzero if this argument is a named parameter
724 (otherwise it is an extra parameter matching an ellipsis). */
726 /* On SPARC the first six args are normally in registers
727 and the rest are pushed. Any arg that starts within the first 6 words
728 is at least partially passed in a register unless its data type forbids. */
730 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
731 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
732 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
733 && ((TYPE)==0 || (MODE) != BLKmode \
734 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
735 ? gen_rtx (REG, (MODE), \
736 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
739 /* Define where a function finds its arguments.
740 This is different from FUNCTION_ARG because of register windows. */
742 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
743 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
744 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
745 && ((TYPE)==0 || (MODE) != BLKmode \
746 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
747 ? gen_rtx (REG, (MODE), \
748 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
751 /* For an arg passed partly in registers and partly in memory,
752 this is the number of registers used.
753 For args passed entirely in registers or entirely in memory, zero.
754 Any arg that starts in the first 6 regs but won't entirely fit in them
755 needs partial registers on the Sparc. */
757 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
758 ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
759 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
760 && ((TYPE)==0 || (MODE) != BLKmode \
761 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
762 && (ROUND_REG ((CUM), (MODE)) \
763 + ((MODE) == BLKmode \
764 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
765 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
766 ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
769 /* The SPARC ABI stipulates passing struct arguments (of any size) and
770 quad-precision floats by invisible reference. */
771 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
772 ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
773 || TREE_CODE (TYPE) == UNION_TYPE)) \
776 /* If defined, a C expression that gives the alignment boundary, in
777 bits, of an argument with the specified mode and type. If it is
778 not defined, `PARM_BOUNDARY' is used for all arguments.
780 This definition does nothing special unless TARGET_FORCE_ALIGN;
781 in that case, it aligns each arg to the natural boundary. */
783 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
784 (! TARGET_FORCE_ALIGN \
787 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
789 : TYPE_ALIGN (TYPE)) \
790 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
792 : GET_MODE_ALIGNMENT (MODE))))
794 /* Define the information needed to generate branch and scc insns. This is
795 stored from the compare operation. Note that we can't use "rtx" here
796 since it hasn't been defined! */
798 extern struct rtx_def
*sparc_compare_op0
, *sparc_compare_op1
;
800 /* Define the function that build the compare insn for scc and bcc. */
802 extern struct rtx_def
*gen_compare_reg ();
804 /* Generate the special assembly code needed to tell the assembler whatever
805 it might need to know about the return value of a function.
807 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
808 information to the assembler relating to peephole optimization (done in
811 #define ASM_DECLARE_RESULT(FILE, RESULT) \
812 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
814 /* Output the label for a function definition. */
816 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
818 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
819 ASM_OUTPUT_LABEL (FILE, NAME); \
822 /* Two views of the size of the current frame. */
823 extern int actual_fsize
;
824 extern int apparent_fsize
;
826 /* This macro generates the assembly code for function entry.
827 FILE is a stdio stream to output the code to.
828 SIZE is an int: how many units of temporary storage to allocate.
829 Refer to the array `regs_ever_live' to determine which registers
830 to save; `regs_ever_live[I]' is nonzero if register number I
831 is ever used in the function. This macro is responsible for
832 knowing which registers should not be saved even if used. */
834 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
835 of memory. If any fpu reg is used in the function, we allocate
836 such a block here, at the bottom of the frame, just in case it's needed.
838 If this function is a leaf procedure, then we may choose not
839 to do a "save" insn. The decision about whether or not
840 to do this is made in regclass.c. */
842 #define FUNCTION_PROLOGUE(FILE, SIZE) \
843 output_function_prologue (FILE, SIZE, leaf_function)
845 /* Output assembler code to FILE to increment profiler label # LABELNO
846 for profiling a function entry. */
848 #define FUNCTION_PROFILER(FILE, LABELNO) \
849 fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
850 (LABELNO), (LABELNO))
852 /* Output assembler code to FILE to initialize this source file's
853 basic block profiling info, if that has not already been done. */
855 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
856 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
857 (LABELNO), (LABELNO))
859 /* Output assembler code to FILE to increment the entry-count for
860 the BLOCKNO'th basic block in this source file. */
862 #define BLOCK_PROFILER(FILE, BLOCKNO) \
864 int blockn = (BLOCKNO); \
865 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
866 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
867 4 * blockn, 4 * blockn, 4 * blockn); \
870 /* Output rtl to increment the entry-count for the LABELNO'th instrumented
871 arc in this source file. */
873 #define ARC_PROFILER(ARCNO, INSERT_AFTER) \
874 output_arc_profiler (ARCNO, INSERT_AFTER)
876 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
877 the stack pointer does not matter. The value is tested only in
878 functions that have frame pointers.
879 No definition is equivalent to always zero. */
881 extern int current_function_calls_alloca
;
882 extern int current_function_outgoing_args_size
;
884 #define EXIT_IGNORE_STACK \
885 (get_frame_size () != 0 \
886 || current_function_calls_alloca || current_function_outgoing_args_size)
888 /* This macro generates the assembly code for function exit,
889 on machines that need it. If FUNCTION_EPILOGUE is not defined
890 then individual return instructions are generated for each
891 return statement. Args are same as for FUNCTION_PROLOGUE.
893 The function epilogue should not depend on the current stack pointer!
894 It should use the frame pointer only. This is mandatory because
895 of alloca; we also take advantage of it to omit stack adjustments
898 /* This declaration is needed due to traditional/ANSI
899 incompatibilities which cannot be #ifdefed away
900 because they occur inside of macros. Sigh. */
901 extern union tree_node
*current_function_decl
;
903 #define FUNCTION_EPILOGUE(FILE, SIZE) \
904 output_function_epilogue (FILE, SIZE, leaf_function)
906 #define DELAY_SLOTS_FOR_EPILOGUE 1
907 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
908 eligible_for_epilogue_delay (trial, slots_filled)
910 /* Output assembler code for a block containing the constant parts
911 of a trampoline, leaving space for the variable parts. */
913 /* On the sparc, the trampoline contains five instructions:
914 sethi #TOP_OF_FUNCTION,%g2
915 or #BOTTOM_OF_FUNCTION,%g2,%g2
916 sethi #TOP_OF_STATIC,%g1
918 or #BOTTOM_OF_STATIC,%g1,%g1 */
919 #define TRAMPOLINE_TEMPLATE(FILE) \
921 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
922 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
923 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
924 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
925 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
928 /* Length in units of the trampoline for entering a nested function. */
930 #define TRAMPOLINE_SIZE 20
932 /* Emit RTL insns to initialize the variable parts of a trampoline.
933 FNADDR is an RTX for the address of the function's pure code.
934 CXT is an RTX for the static chain value for the function.
936 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
937 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
938 (to store insns). This is a bit excessive. Perhaps a different
939 mechanism would be better here. */
941 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
943 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
944 size_int (10), 0, 1); \
945 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
946 size_int (10), 0, 1); \
947 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
948 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
949 rtx g1_sethi = gen_rtx (HIGH, SImode, \
950 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
951 rtx g2_sethi = gen_rtx (HIGH, SImode, \
952 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
953 rtx g1_ori = gen_rtx (HIGH, SImode, \
954 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
955 rtx g2_ori = gen_rtx (HIGH, SImode, \
956 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
957 rtx tem = gen_reg_rtx (SImode); \
958 emit_move_insn (tem, g2_sethi); \
959 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
960 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
961 emit_move_insn (tem, g2_ori); \
962 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
963 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
964 emit_move_insn (tem, g1_sethi); \
965 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
966 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
967 emit_move_insn (tem, g1_ori); \
968 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
969 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
972 /* Emit code for a call to builtin_saveregs. We must emit USE insns which
973 reference the 6 input registers. Ordinarily they are not call used
974 registers, but they are for _builtin_saveregs, so we must make this
977 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) \
978 (emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, TImode, 24))), \
979 emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, DImode, 28))), \
980 expand_call (exp, target, ignore))
982 /* Addressing modes, and classification of registers for them. */
984 /* #define HAVE_POST_INCREMENT */
985 /* #define HAVE_POST_DECREMENT */
987 /* #define HAVE_PRE_DECREMENT */
988 /* #define HAVE_PRE_INCREMENT */
990 /* Macros to check register numbers against specific register classes. */
992 /* These assume that REGNO is a hard or pseudo reg number.
993 They give nonzero only if REGNO is a hard reg of the suitable class
994 or a pseudo reg currently allocated to a suitable hard reg.
995 Since they use reg_renumber, they are safe only once reg_renumber
996 has been allocated, which happens in local-alloc.c. */
998 #define REGNO_OK_FOR_INDEX_P(REGNO) \
999 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1000 #define REGNO_OK_FOR_BASE_P(REGNO) \
1001 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1002 #define REGNO_OK_FOR_FP_P(REGNO) \
1003 (((REGNO) ^ 0x20) < 32 \
1004 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1006 /* Now macros that check whether X is a register and also,
1007 strictly, whether it is in a specified class.
1009 These macros are specific to the SPARC, and may be used only
1010 in code for printing assembler insns and in conditions for
1011 define_optimization. */
1013 /* 1 if X is an fp register. */
1015 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1017 /* Maximum number of registers that can appear in a valid memory address. */
1019 #define MAX_REGS_PER_ADDRESS 2
1021 /* Recognize any constant value that is a valid address. */
1023 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
1025 /* Nonzero if the constant value X is a legitimate general operand.
1026 Anything can be made to work except floating point constants. */
1028 #define LEGITIMATE_CONSTANT_P(X) \
1029 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1031 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1032 and check its validity for a certain class.
1033 We have two alternate definitions for each of them.
1034 The usual definition accepts all pseudo regs; the other rejects
1035 them unless they have been allocated suitable hard regs.
1036 The symbol REG_OK_STRICT causes the latter definition to be used.
1038 Most source files want to accept pseudo regs in the hope that
1039 they will get allocated to the class that the insn wants them to be in.
1040 Source files for reload pass need to be strict.
1041 After reload, it makes no difference, since pseudo regs have
1042 been eliminated by then. */
1044 /* Optional extra constraints for this machine. Borrowed from romp.h.
1046 For the SPARC, `Q' means that this is a memory operand but not a
1047 symbolic memory operand. Note that an unassigned pseudo register
1048 is such a memory operand. Needed because reload will generate
1049 these things in insns and then not re-recognize the insns, causing
1050 constrain_operands to fail.
1052 `R' handles the LO_SUM which can be an address for `Q'.
1054 `S' handles constraints for calls. */
1056 #ifndef REG_OK_STRICT
1058 /* Nonzero if X is a hard reg that can be used as an index
1059 or if it is a pseudo reg. */
1060 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1061 /* Nonzero if X is a hard reg that can be used as a base reg
1062 or if it is a pseudo reg. */
1063 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1065 #define EXTRA_CONSTRAINT(OP, C) \
1067 ? ((GET_CODE (OP) == MEM \
1068 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1069 && ! symbolic_memory_operand (OP, VOIDmode)) \
1070 || (reload_in_progress && GET_CODE (OP) == REG \
1071 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1073 ? (GET_CODE (OP) == LO_SUM \
1074 && GET_CODE (XEXP (OP, 0)) == REG \
1075 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1077 ? (CONSTANT_P (OP) || memory_address_p (Pmode, OP)) \
1082 /* Nonzero if X is a hard reg that can be used as an index. */
1083 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1084 /* Nonzero if X is a hard reg that can be used as a base reg. */
1085 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1087 #define EXTRA_CONSTRAINT(OP, C) \
1089 (GET_CODE (OP) == REG ? \
1090 (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1091 && reg_renumber[REGNO (OP)] < 0) \
1092 : GET_CODE (OP) == MEM) \
1094 (GET_CODE (OP) == LO_SUM \
1095 && GET_CODE (XEXP (OP, 0)) == REG \
1096 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1098 ? (CONSTANT_P (OP) \
1099 || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\
1100 || strict_memory_address_p (Pmode, OP)) : 0)))
1103 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1104 that is a valid memory address for an instruction.
1105 The MODE argument is the machine mode for the MEM expression
1106 that wants to use this address.
1108 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1109 ordinarily. This changes a bit when generating PIC.
1111 If you change this, execute "rm explow.o recog.o reload.o". */
1113 #define RTX_OK_FOR_BASE_P(X) \
1114 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1115 || (GET_CODE (X) == SUBREG \
1116 && GET_CODE (SUBREG_REG (X)) == REG \
1117 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1119 #define RTX_OK_FOR_INDEX_P(X) \
1120 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1121 || (GET_CODE (X) == SUBREG \
1122 && GET_CODE (SUBREG_REG (X)) == REG \
1123 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1125 #define RTX_OK_FOR_OFFSET_P(X) \
1126 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1128 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1129 { if (RTX_OK_FOR_BASE_P (X)) \
1131 else if (GET_CODE (X) == PLUS) \
1133 register rtx op0 = XEXP (X, 0); \
1134 register rtx op1 = XEXP (X, 1); \
1135 if (flag_pic && op0 == pic_offset_table_rtx) \
1137 if (RTX_OK_FOR_BASE_P (op1)) \
1139 else if (flag_pic == 1 \
1140 && GET_CODE (op1) != REG \
1141 && GET_CODE (op1) != LO_SUM \
1142 && GET_CODE (op1) != MEM) \
1145 else if (RTX_OK_FOR_BASE_P (op0)) \
1147 if (RTX_OK_FOR_INDEX_P (op1) \
1148 || RTX_OK_FOR_OFFSET_P (op1)) \
1151 else if (RTX_OK_FOR_BASE_P (op1)) \
1153 if (RTX_OK_FOR_INDEX_P (op0) \
1154 || RTX_OK_FOR_OFFSET_P (op0)) \
1158 else if (GET_CODE (X) == LO_SUM) \
1160 register rtx op0 = XEXP (X, 0); \
1161 register rtx op1 = XEXP (X, 1); \
1162 if (RTX_OK_FOR_BASE_P (op0) \
1163 && CONSTANT_P (op1)) \
1166 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1170 /* Try machine-dependent ways of modifying an illegitimate address
1171 to be legitimate. If we find one, return the new, valid address.
1172 This macro is used in only one place: `memory_address' in explow.c.
1174 OLDX is the address as it was before break_out_memory_refs was called.
1175 In some cases it is useful to look at this to decide what needs to be done.
1177 MODE and WIN are passed so that this macro can use
1178 GO_IF_LEGITIMATE_ADDRESS.
1180 It is always safe for this macro to do nothing. It exists to recognize
1181 opportunities to optimize the output. */
1183 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1184 extern struct rtx_def
*legitimize_pic_address ();
1185 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1186 { rtx sparc_x = (X); \
1187 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1188 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1189 force_operand (XEXP (X, 0), 0)); \
1190 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1191 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1192 force_operand (XEXP (X, 1), 0)); \
1193 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1194 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), 0),\
1196 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1197 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1198 force_operand (XEXP (X, 1), 0)); \
1199 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1201 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1202 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1203 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1204 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1205 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1206 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1207 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1208 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1209 || GET_CODE (X) == LABEL_REF) \
1210 (X) = gen_rtx (LO_SUM, Pmode, \
1211 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1212 if (memory_address_p (MODE, X)) \
1215 /* Go to LABEL if ADDR (a legitimate address expression)
1216 has an effect that depends on the machine mode it is used for.
1217 On the SPARC this is never true. */
1219 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1221 /* Specify the machine mode that this machine uses
1222 for the index in the tablejump instruction. */
1223 #define CASE_VECTOR_MODE SImode
1225 /* Define this if the tablejump instruction expects the table
1226 to contain offsets from the address of the table.
1227 Do not define this if the table should contain absolute addresses. */
1228 /* #define CASE_VECTOR_PC_RELATIVE */
1230 /* Specify the tree operation to be used to convert reals to integers. */
1231 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1233 /* This is the kind of divide that is easiest to do in the general case. */
1234 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1236 /* Define this as 1 if `char' should by default be signed; else as 0. */
1237 #define DEFAULT_SIGNED_CHAR 1
1239 /* Max number of bytes we can move from memory to memory
1240 in one reasonably fast instruction. */
1243 /* This is the value of the error code EDOM for this machine,
1244 used by the sqrt instruction. */
1245 #define TARGET_EDOM 33
1247 /* This is how to refer to the variable errno. */
1248 #define GEN_ERRNO_RTX \
1249 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
1251 /* Define if normal loads of shorter-than-word items from memory clears
1252 the rest of the bigs in the register. */
1253 #define BYTE_LOADS_ZERO_EXTEND
1255 /* Nonzero if access to memory by bytes is slow and undesirable.
1256 For RISC chips, it means that access to memory by bytes is no
1257 better than access by words when possible, so grab a whole word
1258 and maybe make use of that. */
1259 #define SLOW_BYTE_ACCESS 1
1261 /* We assume that the store-condition-codes instructions store 0 for false
1262 and some other value for true. This is the value stored for true. */
1264 #define STORE_FLAG_VALUE 1
1266 /* When a prototype says `char' or `short', really pass an `int'. */
1267 #define PROMOTE_PROTOTYPES
1269 /* Define if shifts truncate the shift count
1270 which implies one can omit a sign-extension or zero-extension
1271 of a shift count. */
1272 #define SHIFT_COUNT_TRUNCATED
1274 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1275 is done just by pretending it is already truncated. */
1276 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1278 /* Specify the machine mode that pointers have.
1279 After generation of rtl, the compiler makes no further distinction
1280 between pointers and any other objects of this machine mode. */
1281 #define Pmode SImode
1283 /* Generate calls to memcpy, memcmp and memset. */
1284 #define TARGET_MEM_FUNCTIONS
1286 /* Add any extra modes needed to represent the condition code.
1288 On the Sparc, we have a "no-overflow" mode which is used when an add or
1289 subtract insn is used to set the condition code. Different branches are
1290 used in this case for some operations.
1292 We also have two modes to indicate that the relevant condition code is
1293 in the floating-point condition code register. One for comparisons which
1294 will generate an exception if the result is unordered (CCFPEmode) and
1295 one for comparisons which will never trap (CCFPmode). This really should
1296 be a separate register, but we don't want to go to 65 registers. */
1297 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1299 /* Define the names for the modes specified above. */
1300 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1302 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1303 return the mode to be used for the comparison. For floating-point,
1304 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1305 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1307 #define SELECT_CC_MODE(OP,X,Y) \
1308 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1309 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1310 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1311 ? CC_NOOVmode : CCmode))
1313 /* A function address in a call instruction
1314 is a byte address (for indexing purposes)
1315 so give the MEM rtx a byte's mode. */
1316 #define FUNCTION_MODE SImode
1318 /* Define this if addresses of constant functions
1319 shouldn't be put through pseudo regs where they can be cse'd.
1320 Desirable on machines where ordinary constants are expensive
1321 but a CALL with constant address is cheap. */
1322 #define NO_FUNCTION_CSE
1324 /* alloca should avoid clobbering the old register save area. */
1325 #define SETJMP_VIA_SAVE_AREA
1327 /* Define subroutines to call to handle multiply and divide.
1328 Use the subroutines that Sun's library provides.
1329 The `*' prevents an underscore from being prepended by the compiler. */
1331 #define DIVSI3_LIBCALL "*.div"
1332 #define UDIVSI3_LIBCALL "*.udiv"
1333 #define MODSI3_LIBCALL "*.rem"
1334 #define UMODSI3_LIBCALL "*.urem"
1335 /* .umul is a little faster than .mul. */
1336 #define MULSI3_LIBCALL "*.umul"
1338 /* Compute the cost of computing a constant rtl expression RTX
1339 whose rtx-code is CODE. The body of this macro is a portion
1340 of a switch statement. If the code is computed here,
1341 return it with a return statement. Otherwise, break from the switch. */
1343 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1345 if (INTVAL (RTX) == 0) \
1347 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1355 case CONST_DOUBLE: \
1356 if (GET_MODE (RTX) == DImode) \
1357 if ((XINT (RTX, 3) == 0 \
1358 && (unsigned) XINT (RTX, 2) < 0x1000) \
1359 || (XINT (RTX, 3) == -1 \
1360 && XINT (RTX, 2) < 0 \
1361 && XINT (RTX, 2) >= -0x1000)) \
1365 /* SPARC offers addressing modes which are "as cheap as a register".
1366 See sparc.c (or gcc.texinfo) for details. */
1368 #define ADDRESS_COST(RTX) \
1369 (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1371 /* Compute extra cost of moving data between one register class
1373 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1374 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1375 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1377 /* Provide the costs of a rtl expression. This is in the body of a
1378 switch on CODE. The purpose for the cost of MULT is to encourage
1379 `synth_mult' to find a synthetic multiply when reasonable.
1381 If we need more than 12 insns to do a multiply, then go out-of-line,
1382 since the call overhead will be < 10% of the cost of the multiply. */
1384 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1386 return COSTS_N_INSNS (25); \
1391 return COSTS_N_INSNS (20); \
1392 /* Make FLOAT more expensive than CONST_DOUBLE, \
1393 so that cse will favor the latter. */ \
1397 /* Conditional branches with empty delay slots have a length of two. */
1398 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1399 if (GET_CODE (INSN) == CALL_INSN \
1400 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1403 /* Control the assembler format that we output. */
1405 /* Output at beginning of assembler file. */
1407 #define ASM_FILE_START(file)
1409 /* Output to assembler file text saying following lines
1410 may contain character constants, extra white space, comments, etc. */
1412 #define ASM_APP_ON ""
1414 /* Output to assembler file text saying following lines
1415 no longer contain unusual constructs. */
1417 #define ASM_APP_OFF ""
1419 /* Output before read-only data. */
1421 #define TEXT_SECTION_ASM_OP ".text"
1423 /* Output before writable data. */
1425 #define DATA_SECTION_ASM_OP ".data"
1427 /* How to refer to registers in assembler output.
1428 This sequence is indexed by compiler's hard-register-number (see above). */
1430 #define REGISTER_NAMES \
1431 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1432 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1433 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1434 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1435 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1436 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1437 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1438 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1440 /* Define additional names for use in asm clobbers and asm declarations.
1442 We define the fake Condition Code register as an alias for reg 0 (which
1443 is our `condition code' register), so that condition codes can easily
1444 be clobbered by an asm. No such register actually exists. Condition
1445 codes are partly stored in the PSR and partly in the FSR. */
1447 #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1449 /* How to renumber registers for dbx and gdb. */
1451 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1453 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1454 since the length can run past this up to a continuation point. */
1455 #define DBX_CONTIN_LENGTH 1500
1457 /* This is how to output a note to DBX telling it the line number
1458 to which the following sequence of instructions corresponds.
1460 This is needed for SunOS 4.0, and should not hurt for 3.2
1462 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1463 { static int sym_lineno = 1; \
1464 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1465 line, sym_lineno, sym_lineno); \
1468 /* This is how to output the definition of a user-level label named NAME,
1469 such as the label on a static function or variable NAME. */
1471 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1472 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1474 /* This is how to output a command to make the user-level label named NAME
1475 defined for reference from other files. */
1477 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1478 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1480 /* This is how to output a reference to a user-level label named NAME.
1481 `assemble_name' uses this. */
1483 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1484 fprintf (FILE, "_%s", NAME)
1486 /* This is how to output an internal numbered label where
1487 PREFIX is the class of label and NUM is the number within the class. */
1489 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1490 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1492 /* This is how to store into the string LABEL
1493 the symbol_ref name of an internal numbered label where
1494 PREFIX is the class of label and NUM is the number within the class.
1495 This is suitable for output with `assemble_name'. */
1497 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1498 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1500 /* This is how to output an assembler line defining a `double' constant. */
1502 /* Assemblers (both gas 1.35 and as in 4.0.3)
1503 seem to treat -0.0 as if it were 0.0.
1504 They reject 99e9999, but accept inf. */
1505 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1507 if (REAL_VALUE_ISINF (VALUE)) \
1508 fprintf (FILE, "\t.double 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1509 else if (REAL_VALUE_ISNAN (VALUE) \
1510 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1512 union { double d; long l[2];} t; \
1514 fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t.l[0], t.l[1]); \
1517 fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1520 /* This is how to output an assembler line defining a `float' constant. */
1522 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1524 if (REAL_VALUE_ISINF (VALUE)) \
1525 fprintf (FILE, "\t.single 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1526 else if (REAL_VALUE_ISNAN (VALUE) \
1527 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1529 union { float f; long l;} t; \
1531 fprintf (FILE, "\t.word 0x%lx\n", t.l); \
1534 fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1537 /* This is how to output an assembler line defining an `int' constant. */
1539 #define ASM_OUTPUT_INT(FILE,VALUE) \
1540 ( fprintf (FILE, "\t.word "), \
1541 output_addr_const (FILE, (VALUE)), \
1542 fprintf (FILE, "\n"))
1544 /* This is how to output an assembler line defining a DImode constant. */
1545 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1546 output_double_int (FILE, VALUE)
1548 /* Likewise for `char' and `short' constants. */
1550 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1551 ( fprintf (FILE, "\t.half "), \
1552 output_addr_const (FILE, (VALUE)), \
1553 fprintf (FILE, "\n"))
1555 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1556 ( fprintf (FILE, "\t.byte "), \
1557 output_addr_const (FILE, (VALUE)), \
1558 fprintf (FILE, "\n"))
1560 /* This is how to output an assembler line for a numeric constant byte. */
1562 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1563 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1565 /* This is how to output an element of a case-vector that is absolute. */
1567 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1570 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1571 fprintf (FILE, "\t.word\t"); \
1572 assemble_name (FILE, label); \
1573 fprintf (FILE, "\n"); \
1576 /* This is how to output an element of a case-vector that is relative.
1577 (SPARC uses such vectors only when generating PIC.) */
1579 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1582 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1583 fprintf (FILE, "\t.word\t"); \
1584 assemble_name (FILE, label); \
1585 fprintf (FILE, "-1b\n"); \
1588 /* This is how to output an assembler line
1589 that says to advance the location counter
1590 to a multiple of 2**LOG bytes. */
1592 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1594 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1596 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1597 fprintf (FILE, "\t.skip %u\n", (SIZE))
1599 /* This says how to output an assembler line
1600 to define a global common symbol. */
1602 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1603 ( fputs ("\t.global ", (FILE)), \
1604 assemble_name ((FILE), (NAME)), \
1605 fputs ("\n\t.common ", (FILE)), \
1606 assemble_name ((FILE), (NAME)), \
1607 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1609 /* This says how to output an assembler line
1610 to define a local common symbol. */
1612 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1613 ( fputs ("\n\t.reserve ", (FILE)), \
1614 assemble_name ((FILE), (NAME)), \
1615 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1617 /* Store in OUTPUT a string (made with alloca) containing
1618 an assembler-name for a local static variable named NAME.
1619 LABELNO is an integer which is different for each call. */
1621 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1622 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1623 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1625 /* Define the parentheses used to group arithmetic operations
1626 in assembler code. */
1628 #define ASM_OPEN_PAREN "("
1629 #define ASM_CLOSE_PAREN ")"
1631 /* Define results of standard character escape sequences. */
1632 #define TARGET_BELL 007
1633 #define TARGET_BS 010
1634 #define TARGET_TAB 011
1635 #define TARGET_NEWLINE 012
1636 #define TARGET_VT 013
1637 #define TARGET_FF 014
1638 #define TARGET_CR 015
1640 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1641 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' \
1644 /* Print operand X (an rtx) in assembler syntax to file FILE.
1645 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1646 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1648 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1650 /* Print a memory address as an operand to reference that memory location. */
1652 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1653 { register rtx base, index = 0; \
1655 register rtx addr = ADDR; \
1656 if (GET_CODE (addr) == REG) \
1657 fputs (reg_names[REGNO (addr)], FILE); \
1658 else if (GET_CODE (addr) == PLUS) \
1660 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1661 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1662 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1663 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1665 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1666 fputs (reg_names[REGNO (base)], FILE); \
1668 fprintf (FILE, "%+d", offset); \
1669 else if (GET_CODE (index) == REG) \
1670 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1671 else if (GET_CODE (index) == SYMBOL_REF) \
1672 fputc ('+', FILE), output_addr_const (FILE, index); \
1675 else if (GET_CODE (addr) == MINUS \
1676 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1678 output_addr_const (FILE, XEXP (addr, 0)); \
1679 fputs ("-(", FILE); \
1680 output_addr_const (FILE, XEXP (addr, 1)); \
1681 fputs ("-.)", FILE); \
1683 else if (GET_CODE (addr) == LO_SUM) \
1685 output_operand (XEXP (addr, 0), 0); \
1686 fputs ("+%lo(", FILE); \
1687 output_address (XEXP (addr, 1)); \
1688 fputc (')', FILE); \
1690 else if (flag_pic && GET_CODE (addr) == CONST \
1691 && GET_CODE (XEXP (addr, 0)) == MINUS \
1692 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1693 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1694 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1696 addr = XEXP (addr, 0); \
1697 output_addr_const (FILE, XEXP (addr, 0)); \
1698 /* Group the args of the second CONST in parenthesis. */ \
1699 fputs ("-(", FILE); \
1700 /* Skip past the second CONST--it does nothing for us. */\
1701 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1702 /* Close the parenthesis. */ \
1703 fputc (')', FILE); \
1707 output_addr_const (FILE, addr); \
1711 /* Declare functions defined in sparc.c and used in templates. */
1713 extern char *singlemove_string ();
1714 extern char *output_move_double ();
1715 extern char *output_move_quad ();
1716 extern char *output_fp_move_double ();
1717 extern char *output_fp_move_quad ();
1718 extern char *output_block_move ();
1719 extern char *output_scc_insn ();
1720 extern char *output_cbranch ();
1721 extern char *output_return ();
1722 extern char *output_floatsisf2 ();
1723 extern char *output_floatsidf2 ();
1724 extern char *output_floatsitf2 ();
1726 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1728 extern int flag_pic
;