1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
23 /* Note that some other tm.h files include this one and then override
24 many of the definitions that relate to assembler syntax. */
26 /* Sparc64 support has been added by trying to allow for a day when one
27 compiler can handle both v8 and v9. There are a few cases where this
28 isn't doable, but keep them to a minimum! Two macros are used to help out:
29 TARGET_V9 is used to select (at runtime) !v9-ness or v9-ness.
30 SPARCV9 is defined when compiling for sparc64 only.
31 In places where it is possible to choose between the two at runtime, use
32 TARGET_V9. In places where it is currently not possible to select
33 between the two at runtime use SPARCV9. Again, keep uses of SPARCV9 to a
34 minimum. No attempt is made to support both v8 and v9 in the v9 compiler.
36 If a combination v8/v9 compiler is too slow, it should always be possible
37 to #define TARGET_V9 as 0 (and potentially other v9-only options), and
40 /* What architecture we're compiling for. This must coincide with the
41 `arch_type' attribute in the .md file. The names were chosen to avoid
42 potential misunderstandings with the various 32 bit flavors (v7, v8, etc.):
43 if we used ARCH_V9 then we'd want to use something like ARCH_V8 but that
44 could be misleading and ARCH_NOTV9 sounds klunky. */
45 enum arch_type
{ ARCH_32BIT
, ARCH_64BIT
};
46 extern enum arch_type sparc_arch_type
;
48 /* Names to predefine in the preprocessor for this target machine. */
50 /* ??? The GCC_NEW_VARARGS macro is now obsolete, because gcc always uses
51 the right varags.h file when bootstrapping. */
54 #define CPP_PREDEFINES \
55 "-Dsparc -Dsun -Dunix -D__sparc_v9__ \
56 -Asystem(unix) -Asystem(bsd) -Acpu(sparc64) -Amachine(sparc64)"
58 #define CPP_PREDEFINES \
59 "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
60 -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
63 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
65 /* Provide required defaults for linker -e and -d switches. */
68 "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
70 /* Special flags to the Sun-4 assembler when using pipe for input. */
72 #define ASM_SPEC " %| %{!pg:%{!p:%{fpic:-k} %{fPIC:-k}}}"
74 /* Define macros to distinguish architectures. */
78 %{mint64:-D__INT_MAX__=9223372036854775807LL -D__LONG_MAX__=9223372036854775807LL} \
79 %{mlong64:-D__LONG_MAX__=9223372036854775807LL} \
83 %{msparclite:-D__sparclite__} \
84 %{mf930:-D__sparclite__} %{mf934:-D__sparclite__} \
85 %{mv8:-D__sparc_v8__} \
86 %{msupersparc:-D__supersparc__ -D__sparc_v8__} \
90 /* Prevent error on `-sun4' and `-target sun4' options. */
91 /* This used to translate -dalign to -malign, but that is no good
92 because it can't turn off the usual meaning of making debugging dumps. */
94 #define CC1_SPEC "%{sun4:} %{target:}"
97 #define PTRDIFF_TYPE "long long int"
98 #define SIZE_TYPE "long long unsigned int"
100 #define PTRDIFF_TYPE "int"
101 /* In 2.4 it should work to delete this.
102 #define SIZE_TYPE "int" */
105 /* ??? This should be 32 bits for v9 but what can we do? */
106 #define WCHAR_TYPE "short unsigned int"
107 #define WCHAR_TYPE_SIZE 16
108 #define MAX_WCHAR_TYPE_SIZE 16
110 /* Show we can debug even without a frame pointer. */
111 #define CAN_DEBUG_WITHOUT_FP
113 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
114 code into the rtl. Also, if we are profiling, we cannot eliminate
115 the frame pointer (because the return address will get smashed). */
117 void sparc_override_options ();
119 #define OVERRIDE_OPTIONS \
121 if (profile_flag || profile_block_flag) \
125 char *pic_string = (flag_pic == 1) ? "-fpic" : "-fPIC"; \
126 warning ("%s and profiling conflict: disabling %s", \
127 pic_string, pic_string); \
130 flag_omit_frame_pointer = 0; \
132 SUBTARGET_OVERRIDE_OPTIONS \
133 sparc_override_options (); \
136 /* This is meant to be redefined in the host dependent files */
137 #define SUBTARGET_OVERRIDE_OPTIONS
139 /* These compiler options take an argument. We ignore -target for now. */
141 #define WORD_SWITCH_TAKES_ARG(STR) \
142 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
143 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
145 /* Print subsidiary information on the compiler version in use. */
147 #define TARGET_VERSION fprintf (stderr, " (sparc)");
149 /* Generate DBX debugging information. */
151 #define DBX_DEBUGGING_INFO
153 /* Run-time compilation parameters selecting different hardware subsets. */
155 extern int target_flags
;
157 /* Nonzero if we should generate code to use the fpu. */
159 #define TARGET_FPU (target_flags & MASK_FPU)
161 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
162 use fast return insns, but lose some generality. */
163 #define MASK_EPILOGUE 2
164 #define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)
166 /* Nonzero if we should assume that double pointers might be unaligned.
167 This can happen when linking gcc compiled code with other compilers,
168 because the ABI only guarantees 4 byte alignment. */
169 #define MASK_UNALIGNED_DOUBLES 4
170 #define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)
172 /* ??? Bits 0x18 are currently unused. */
174 /* Nonzero means we should schedule code for the TMS390Z55 SuperSparc chip. */
175 #define MASK_SUPERSPARC 0x20
176 #define TARGET_SUPERSPARC (target_flags & MASK_SUPERSPARC)
178 /* Nonzero means that we should generate code for a v8 sparc. */
180 #define TARGET_V8 (target_flags & MASK_V8)
182 /* Nonzero means that we should generate code for a sparclite.
183 This enables the sparclite specific instructions, but does not affect
184 whether FPU instructions are emitted. */
185 #define MASK_SPARCLITE 0x80
186 #define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)
188 /* Nonzero means that we should generate code using a flat register window
189 model, i.e. no save/restore instructions are generated, in the most
190 efficient manner. This code is not compatible with normal sparc code. */
191 /* This is not a user selectable option yet, because it requires changes
192 that are not yet switchable via command line arguments. */
193 /* ??? This flag is deprecated and may disappear at some point. */
194 #define MASK_FRW 0x100
195 #define TARGET_FRW (target_flags & MASK_FRW)
197 /* Nonzero means that we should generate code using a flat register window
198 model, i.e. no save/restore instructions are generated, but which is
199 compatible with normal sparc code. This is the same as above, except
200 that the frame pointer is %i7 instead of %fp. */
201 /* ??? This use to be named TARGET_FRW_COMPAT. At some point TARGET_FRW will
202 go away, but until that time only use this one when necessary.
204 #define MASK_FLAT 0x200
205 #define TARGET_FLAT (target_flags & MASK_FLAT)
207 /* Nonzero means use the registers that the Sparc ABI reserves for
208 application software. This is the default for v8, but not v9. */
209 #define MASK_APP_REGS 0x400
210 #define TARGET_APP_REGS (target_flags & MASK_APP_REGS)
212 /* Option to select how quad word floating point is implemented.
213 When TARGET_HARD_QUAD is true, we use the hardware quad instructions.
214 Otherwise, we use the SPARC ABI quad library functions. */
215 #define MASK_HARD_QUAD 0x800
216 #define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)
218 /* Nonzero if we're compiling for 64 bit sparc. */
219 #define MASK_V9 0x1000
220 #define TARGET_V9 (target_flags & MASK_V9)
222 /* Nonzero if ints are 64 bits.
223 This automatically implies longs are 64 bits too.
224 This option is for v9 only. */
225 #define MASK_INT64 0x2000
226 #define TARGET_INT64 (target_flags & MASK_INT64)
228 /* Nonzero if longs are 64 bits.
229 This option is for v9 only. */
230 #define MASK_LONG64 0x4000
231 #define TARGET_LONG64 (target_flags & MASK_LONG64)
233 /* Nonzero if pointers are 64 bits.
234 This is not a user selectable option, though it may be one day -
235 so it is used to determine pointer size instead of an architecture flag. */
236 #define MASK_PTR64 0x8000
237 #define TARGET_PTR64 (target_flags & MASK_PTR64)
239 /* Nonzero if we are generating code to be tested in a 32 bit environment.
240 Hence, we assume the upper 32 bits of symbolic addresses are zero, and
241 avoid generating %uhi and %ulo terms.
242 Pointers are still 64 bits though! This option is for v9 only. */
243 /* ??? This option is deprecated. Try to use -mcode-model=medium-low. */
244 #define MASK_ENV32 0x10000
245 #define TARGET_ENV32 (target_flags & MASK_ENV32)
248 Two memory models are supported:
249 TARGET_MEDLOW: 32 bit address space, top 32 bits = 0
250 (pointers still 64 bits)
251 TARGET_MEDANY: 32 bit address space, data segment loaded anywhere
253 TARGET_FULLANY: not supported yet.
254 These options are for v9 only. All mask values are nonzero so the v8
255 compiler can assume this stuff won't interfere. */
256 #define MASK_MEDLOW 0x20000
257 #define MASK_MEDANY 0x40000
258 #define MASK_FULLANY 0x60000
259 #define MASK_CODE_MODEL (MASK_MEDLOW + MASK_MEDANY)
260 #define TARGET_MEDLOW ((target_flags & MASK_CODE_MODEL) == MASK_MEDLOW)
261 #define TARGET_MEDANY ((target_flags & MASK_CODE_MODEL) == MASK_MEDANY)
262 #define TARGET_FULLANY ((target_flags & MASK_CODE_MODEL) == MASK_FULLANY)
264 /* ??? There are hardcoded references to this reg in the .md file. */
265 #define MEDANY_BASE_REG "%g4"
267 /* Non-zero means use a stack bias of 2047. Stack offsets are obtained by
268 adding 2047 to %sp. This option is for v9 only and is the default. */
269 #define MASK_STACK_BIAS 0x80000
270 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
272 /* Macro to define tables used to set the flags.
273 This is a list in braces of pairs in braces,
274 each pair being { "NAME", VALUE }
275 where VALUE is the bits to set or minus the bits to clear.
276 An empty string NAME is used to identify the default VALUE. */
278 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
279 The Fujitsu MB86934 is the recent sparclite chip, with an fpu.
280 We use -mf930 and -mf934 options to choose which.
281 ??? These should perhaps be -mcpu= options. */
283 #define TARGET_SWITCHES \
284 { {"fpu", MASK_FPU}, \
285 {"no-fpu", -MASK_FPU}, \
286 {"hard-float", MASK_FPU}, \
287 {"soft-float", -MASK_FPU}, \
288 {"epilogue", MASK_EPILOGUE}, \
289 {"no-epilogue", -MASK_EPILOGUE}, \
290 {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \
291 {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \
292 {"supersparc", MASK_SUPERSPARC+MASK_V8}, \
293 {"cypress", -MASK_SUPERSPARC-MASK_V8}, \
295 {"no-v8", -MASK_V8}, \
296 {"sparclite", MASK_SPARCLITE}, \
297 {"no-sparclite", -MASK_SPARCLITE}, \
298 {"f930", MASK_SPARCLITE}, \
299 {"f930", -MASK_FPU}, \
300 {"f934", MASK_SPARCLITE}, \
301 {"flat", MASK_FRW+MASK_FLAT}, \
302 {"no-flat", -(MASK_FRW+MASK_FLAT)}, \
303 {"app-regs", MASK_APP_REGS}, \
304 {"no-app-regs", -MASK_APP_REGS}, \
305 {"hard-quad-float", MASK_HARD_QUAD}, \
306 {"soft-quad-float", -MASK_HARD_QUAD}, \
309 { "", TARGET_DEFAULT}}
311 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)
313 /* This is meant to be redefined in the host dependent files */
314 #define SUBTARGET_SWITCHES
316 /* ??? Until we support a combination v8/v9 compiler, the v9 specific options
317 are only defined for the v9 compiler. */
319 #define V9_SWITCHES \
320 /* {"v9", MASK_V9}, */ \
321 {"int64", MASK_INT64+MASK_LONG64}, \
322 {"int32", -MASK_INT64}, \
323 {"int32", MASK_LONG64}, \
324 {"long64", -MASK_INT64}, \
325 {"long64", MASK_LONG64}, \
326 {"long32", -(MASK_INT64+MASK_LONG64)}, \
327 /* {"ptr64", MASK_PTR64}, */ \
328 /* {"ptr32", -MASK_PTR64}, */ \
329 {"stack-bias", MASK_STACK_BIAS}, \
330 {"no-stack-bias", -MASK_STACK_BIAS},
335 /* This macro is similar to `TARGET_SWITCHES' but defines names of
336 command options that have values. Its definition is an
337 initializer with a subgrouping for each command option.
339 Each subgrouping contains a string constant, that defines the
340 fixed part of the option name, and the address of a variable.
341 The variable, type `char *', is set to the variable part of the
342 given option if the fixed part matches. The actual option name
343 is made by prepending `-m' to the specified name.
345 Here is an example which defines `-mshort-data-NUMBER'. If the
346 given option is `-mshort-data-512', the variable `m88k_short_data'
347 will be set to the string `"512"'.
349 extern char *m88k_short_data;
350 #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
352 /* For v9, two values of "code model" are currently supported.
355 32 bit address space starting at 0
358 32 bit text segment starting at 0
359 32 bit data segment(s) starting anywhere (determined at link time)
360 MEDANY_BASE_REG points to the start
363 extern char *sparc_code_model
;
365 #define TARGET_OPTIONS \
367 { "code-model=", &sparc_code_model } \
370 /* target machine storage layout */
372 /* Define for cross-compilation to a sparc target with no TFmode from a host
373 with a different float format (e.g. VAX). */
374 #define REAL_ARITHMETIC
376 /* Define this if most significant bit is lowest numbered
377 in instructions that operate on numbered bit-fields. */
378 #define BITS_BIG_ENDIAN 1
380 /* Define this if most significant byte of a word is the lowest numbered. */
381 /* This is true on the SPARC. */
382 #define BYTES_BIG_ENDIAN 1
384 /* Define this if most significant word of a multiword number is the lowest
386 /* Doubles are stored in memory with the high order word first. This
387 matters when cross-compiling. */
388 #define WORDS_BIG_ENDIAN 1
390 /* number of bits in an addressable storage unit */
391 #define BITS_PER_UNIT 8
393 /* Width in bits of a "word", which is the contents of a machine register.
394 Note that this is not necessarily the width of data type `int';
395 if using 16-bit ints on a 68000, this would still be 32.
396 But on a machine with 16-bit registers, this would be 16. */
397 #define BITS_PER_WORD (TARGET_V9 ? 64 : 32)
398 #define MAX_BITS_PER_WORD 64
400 /* Width of a word, in units (bytes). */
401 #define UNITS_PER_WORD (TARGET_V9 ? 8 : 4)
402 #define MAX_UNITS_PER_WORD 8
404 /* Now define the sizes of the C data types. */
406 #define SHORT_TYPE_SIZE 16
407 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
408 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
409 #define LONG_LONG_TYPE_SIZE 64
410 #define FLOAT_TYPE_SIZE 32
411 #define DOUBLE_TYPE_SIZE 64
413 #define MAX_INT_TYPE_SIZE 64
414 #define MAX_LONG_TYPE_SIZE 64
417 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
418 Instead, it is enabled in sol2.h, because it does work under Solaris. */
419 /* Define for support of TFmode long double and REAL_ARITHMETIC.
420 Sparc ABI says that long double is 4 words. */
421 #define LONG_DOUBLE_TYPE_SIZE 128
424 /* Width in bits of a pointer.
425 See also the macro `Pmode' defined below. */
426 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)
428 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
429 #define PARM_BOUNDARY (TARGET_V9 ? 64 : 32)
431 /* Boundary (in *bits*) on which stack pointer should be aligned. */
432 #define STACK_BOUNDARY (TARGET_V9 ? 128 : 64)
434 /* ALIGN FRAMES on double word boundaries */
436 #define SPARC_STACK_ALIGN(LOC) \
437 (TARGET_V9 ? (((LOC)+15) & ~15) : (((LOC)+7) & ~7))
439 /* Allocation boundary (in *bits*) for the code of a function. */
440 #define FUNCTION_BOUNDARY 32
442 /* Alignment of field after `int : 0' in a structure. */
443 /* ??? Should this be based on TARGET_INT64? */
444 #define EMPTY_FIELD_BOUNDARY (TARGET_V9 ? 64 : 32)
446 /* Every structure's size must be a multiple of this. */
447 #define STRUCTURE_SIZE_BOUNDARY 8
449 /* A bitfield declared as `int' forces `int' alignment for the struct. */
450 #define PCC_BITFIELD_TYPE_MATTERS 1
452 /* No data type wants to be aligned rounder than this. */
453 #define BIGGEST_ALIGNMENT (TARGET_V9 ? 128 : 64)
455 /* The best alignment to use in cases where we have a choice. */
456 #define FASTEST_ALIGNMENT 64
458 /* Make strings word-aligned so strcpy from constants will be faster. */
459 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
460 ((TREE_CODE (EXP) == STRING_CST \
461 && (ALIGN) < FASTEST_ALIGNMENT) \
462 ? FASTEST_ALIGNMENT : (ALIGN))
464 /* Make arrays of chars word-aligned for the same reasons. */
465 #define DATA_ALIGNMENT(TYPE, ALIGN) \
466 (TREE_CODE (TYPE) == ARRAY_TYPE \
467 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
468 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
470 /* Set this nonzero if move instructions will actually fail to work
471 when given unaligned data. */
472 #define STRICT_ALIGNMENT 1
474 /* Things that must be doubleword aligned cannot go in the text section,
475 because the linker fails to align the text section enough!
476 Put them in the data section. This macro is only used in this file. */
477 #define MAX_TEXT_ALIGN 32
479 /* This is defined differently for v9 in a cover file. */
480 #define SELECT_SECTION(T,RELOC) \
482 if (TREE_CODE (T) == VAR_DECL) \
484 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
485 && DECL_INITIAL (T) \
486 && (DECL_INITIAL (T) == error_mark_node \
487 || TREE_CONSTANT (DECL_INITIAL (T))) \
488 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
489 && ! (flag_pic && (RELOC))) \
494 else if (TREE_CODE (T) == CONSTRUCTOR) \
496 if (flag_pic != 0 && (RELOC) != 0) \
499 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
501 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
502 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
509 /* Use text section for a constant
510 unless we need more alignment than that offers. */
511 /* This is defined differently for v9 in a cover file. */
512 #define SELECT_RTX_SECTION(MODE, X) \
514 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
515 && ! (flag_pic && symbolic_operand (X))) \
521 /* Standard register usage. */
523 /* Number of actual hardware registers.
524 The hardware registers are assigned numbers for the compiler
525 from 0 to just below FIRST_PSEUDO_REGISTER.
526 All registers that the compiler knows about must be given numbers,
527 even those that are not normally considered general registers.
529 SPARC has 32 integer registers and 32 floating point registers.
530 64 bit SPARC has 32 additional fp regs, but the odd numbered ones are not
531 accessible. We still account for them to simplify register computations
532 (eg: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so
534 Register 0 is used as the integer condition code register. */
537 #define FIRST_PSEUDO_REGISTER 100
539 #define FIRST_PSEUDO_REGISTER 64
542 /* 1 for registers that have pervasive standard uses
543 and are not available for the register allocator.
544 g0 is used for the condition code and not to represent %g0, which is
545 hardwired to 0, so reg 0 is *not* fixed.
547 g1 is free to use as temporary.
548 g2-g4 are reserved for applications. Gcc normally uses them as
549 temporaries, but this can be disabled via the -mno-app-regs option.
550 g5 through g7 are reserved for the operating system.
552 g1 and g5 are free to use as temporaries.
553 g2-g4 are reserved for applications (the compiler will not normally use
554 them, but they can be used as temporaries with -mapp-regs).
555 g6-g7 are reserved for the operating system.
556 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must
557 currently be a fixed register until this pattern is rewritten.
558 Register 1 is also used when restoring call-preserved registers in large
562 #define FIXED_REGISTERS \
563 {0, 1, 1, 1, 1, 0, 1, 1, \
564 0, 0, 0, 0, 0, 0, 1, 0, \
565 0, 0, 0, 0, 0, 0, 0, 0, \
566 0, 0, 0, 0, 0, 0, 1, 1, \
568 0, 0, 0, 0, 0, 0, 0, 0, \
569 0, 0, 0, 0, 0, 0, 0, 0, \
570 0, 0, 0, 0, 0, 0, 0, 0, \
571 0, 0, 0, 0, 0, 0, 0, 0, \
573 0, 0, 0, 0, 0, 0, 0, 0, \
574 0, 0, 0, 0, 0, 0, 0, 0, \
575 0, 0, 0, 0, 0, 0, 0, 0, \
576 0, 0, 0, 0, 0, 0, 0, 0, \
580 #define FIXED_REGISTERS \
581 {0, 0, 0, 0, 0, 1, 1, 1, \
582 0, 0, 0, 0, 0, 0, 1, 0, \
583 0, 0, 0, 0, 0, 0, 0, 0, \
584 0, 0, 0, 0, 0, 0, 1, 1, \
586 0, 0, 0, 0, 0, 0, 0, 0, \
587 0, 0, 0, 0, 0, 0, 0, 0, \
588 0, 0, 0, 0, 0, 0, 0, 0, \
589 0, 0, 0, 0, 0, 0, 0, 0}
592 /* 1 for registers not available across function calls.
593 These must include the FIXED_REGISTERS and also any
594 registers that can be used without being saved.
595 The latter must include the registers where values are returned
596 and the register where structure-value addresses are passed.
597 Aside from that, you can include as many other registers as you like. */
600 #define CALL_USED_REGISTERS \
601 {1, 1, 1, 1, 1, 1, 1, 1, \
602 1, 1, 1, 1, 1, 1, 1, 1, \
603 0, 0, 0, 0, 0, 0, 0, 0, \
604 0, 0, 0, 0, 0, 0, 1, 1, \
606 1, 1, 1, 1, 1, 1, 1, 1, \
607 1, 1, 1, 1, 1, 1, 1, 1, \
608 0, 0, 0, 0, 0, 0, 0, 0, \
609 0, 0, 0, 0, 0, 0, 0, 0, \
611 0, 0, 0, 0, 0, 0, 0, 0, \
612 0, 0, 0, 0, 0, 0, 0, 0, \
613 1, 1, 1, 1, 1, 1, 1, 1, \
614 1, 1, 1, 1, 1, 1, 1, 1, \
618 #define CALL_USED_REGISTERS \
619 {1, 1, 1, 1, 1, 1, 1, 1, \
620 1, 1, 1, 1, 1, 1, 1, 1, \
621 0, 0, 0, 0, 0, 0, 0, 0, \
622 0, 0, 0, 0, 0, 0, 1, 1, \
624 1, 1, 1, 1, 1, 1, 1, 1, \
625 1, 1, 1, 1, 1, 1, 1, 1, \
626 1, 1, 1, 1, 1, 1, 1, 1, \
627 1, 1, 1, 1, 1, 1, 1, 1}
630 /* If !TARGET_FPU, then make the fp registers fixed so that they won't
631 be allocated. On v9, also make the fp cc regs fixed. */
633 #define CONDITIONAL_REGISTER_USAGE \
639 for (regno = 32; regno < FIRST_PSEUDO_REGISTER; regno++) \
640 fixed_regs[regno] = 1; \
642 if (! TARGET_APP_REGS) \
656 /* Let the compiler believe the frame pointer is still \
657 %fp, but output it as %i7. */ \
658 fixed_regs[31] = 1; \
659 reg_names[FRAME_POINTER_REGNUM] = "%i7"; \
660 /* ??? This is a hack to disable leaf functions. */ \
661 global_regs[7] = 1; \
663 if (profile_block_flag) \
665 /* %g1 and %g2 must be fixed, because BLOCK_PROFILER \
673 /* Return number of consecutive hard regs needed starting at reg REGNO
674 to hold something of mode MODE.
675 This is ordinarily the length in words of a value of mode MODE
676 but can be less for certain modes in special long registers.
678 On SPARC, ordinary registers hold 32 bits worth;
679 this means both integer and floating point registers.
680 On v9, integer regs hold 64 bits worth; floating point regs hold
681 32 bits worth (this includes the new fp regs as even the odd ones are
682 included in the hard register count). */
684 #define HARD_REGNO_NREGS(REGNO, MODE) \
687 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD \
688 : (GET_MODE_SIZE (MODE) + 3) / 4) \
689 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
691 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
692 See sparc.c for how we initialize this. */
693 extern int *hard_regno_mode_classes
;
694 extern int sparc_mode_class
[];
695 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
696 ((hard_regno_mode_classes[REGNO] & sparc_mode_class[MODE]) != 0)
698 /* Value is 1 if it is a good idea to tie two pseudo registers
699 when one has mode MODE1 and one has mode MODE2.
700 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
701 for any hard reg, then this must be 0 for correct output.
703 For V9: SFmode can't be combined with other float modes, because they can't
704 be allocated to the %d registers. Also, DFmode won't fit in odd %f
705 registers, but SFmode will. */
706 #define MODES_TIEABLE_P(MODE1, MODE2) \
707 ((MODE1) == (MODE2) \
708 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
710 || (GET_MODE_CLASS (MODE1) != MODE_FLOAT \
711 || (MODE1 != SFmode && MODE2 != SFmode)))))
713 /* Specify the registers used for certain standard purposes.
714 The values of these macros are register numbers. */
716 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
717 /* #define PC_REGNUM */
719 /* Register to use for pushing function arguments. */
720 #define STACK_POINTER_REGNUM 14
722 /* Actual top-of-stack address is 92/136 greater than the contents of the
723 stack pointer register for !v9/v9. That is:
724 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return
725 address, and 24 bytes for the 6 register parameters.
726 - v9: 128 bytes for the in and local registers + 8 bytes reserved. */
727 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
729 /* The stack bias (amount by which the hardware register is offset by). */
730 #define SPARC_STACK_BIAS (TARGET_STACK_BIAS ? 2047 : 0)
732 /* Base register for access to local variables of the function. */
733 #define FRAME_POINTER_REGNUM 30
736 /* Register that is used for the return address. */
737 #define RETURN_ADDR_REGNUM 15
740 /* Value should be nonzero if functions must have frame pointers.
741 Zero means the frame pointer need not be set up (and parms
742 may be accessed via the stack pointer) in functions that seem suitable.
743 This is computed in `reload', in reload1.c.
745 Used in flow.c, global.c, and reload1.c. */
746 extern int leaf_function
;
748 #define FRAME_POINTER_REQUIRED \
749 (TARGET_FRW ? (current_function_calls_alloca || current_function_varargs) \
750 : ! (leaf_function_p () && only_leaf_regs_used ()))
752 /* C statement to store the difference between the frame pointer
753 and the stack pointer values immediately after the function prologue.
755 Note, we always pretend that this is a leaf function because if
756 it's not, there's no point in trying to eliminate the
757 frame pointer. If it is a leaf function, we guessed right! */
758 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
759 ((VAR) = (TARGET_FRW ? sparc_flat_compute_frame_size (get_frame_size ()) \
760 : compute_frame_size (get_frame_size (), 1)))
762 /* Base register for access to arguments of the function. */
763 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
765 /* Register in which static-chain is passed to a function. This must
766 not be a register used by the prologue.
767 ??? v9: Since %g2 is reserved but %g5 is available, perhaps use %g5. */
768 #define STATIC_CHAIN_REGNUM 2
770 /* Register which holds offset table for position-independent
773 #define PIC_OFFSET_TABLE_REGNUM 23
775 #define INITIALIZE_PIC initialize_pic ()
776 #define FINALIZE_PIC finalize_pic ()
778 /* Sparc ABI says that quad-precision floats and all structures are returned
780 For v9, all aggregates are returned in memory. */
781 #define RETURN_IN_MEMORY(TYPE) \
782 (TYPE_MODE (TYPE) == BLKmode || (! TARGET_V9 && TYPE_MODE (TYPE) == TFmode))
784 /* Functions which return large structures get the address
785 to place the wanted value at offset 64 from the frame.
786 Must reserve 64 bytes for the in and local registers.
787 v9: Functions which return large structures get the address to place the
788 wanted value from an invisible first argument. */
789 /* Used only in other #defines in this file. */
790 #define STRUCT_VALUE_OFFSET 64
792 #define STRUCT_VALUE \
795 : gen_rtx (MEM, Pmode, \
796 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
797 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
798 #define STRUCT_VALUE_INCOMING \
801 : gen_rtx (MEM, Pmode, \
802 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
803 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET))))
805 /* Define the classes of registers for register constraints in the
806 machine description. Also define ranges of constants.
808 One of the classes must always be named ALL_REGS and include all hard regs.
809 If there is more than one class, another class must be named NO_REGS
810 and contain no registers.
812 The name GENERAL_REGS must be the name of a class (or an alias for
813 another name such as ALL_REGS). This is the class of registers
814 that is allowed by "g" or "r" in a register constraint.
815 Also, registers outside this class are allocated only when
816 instructions express preferences for them.
818 The classes must be numbered in nondecreasing order; that is,
819 a larger-numbered class must never be contained completely
820 in a smaller-numbered class.
822 For any two classes, it is very desirable that there be another
823 class that represents their union. */
825 /* The SPARC has two kinds of registers, general and floating point.
826 v9 also has 4 floating point condition code registers. Since we don't
827 have a class that is the union of FPCC_REGS with either of the others,
828 it is important that it appear first. Otherwise the compiler will die
829 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its
831 /* ??? As an experiment for v9, we treat all fp regs similarily here. */
834 enum reg_class
{ NO_REGS
, FPCC_REGS
, GENERAL_REGS
, FP_REGS
, GENERAL_OR_FP_REGS
,
835 ALL_REGS
, LIM_REG_CLASSES
};
837 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
840 #define N_REG_CLASSES (int) LIM_REG_CLASSES
842 /* Give names of register classes as strings for dump file. */
845 #define REG_CLASS_NAMES \
846 {"NO_REGS", "FPCC_REGS", "GENERAL_REGS", "FP_REGS", "GENERAL_OR_FP_REGS", \
849 #define REG_CLASS_NAMES \
850 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
853 /* Define which registers fit in which classes.
854 This is an initializer for a vector of HARD_REG_SET
855 of length N_REG_CLASSES. */
858 #define REG_CLASS_CONTENTS \
859 {{0, 0, 0, 0}, {0, 0, 0, 0xf}, {-2, 0, 0, 0}, {0, -1, -1, 0}, \
860 {-2, -1, -1, 0}, {-2, -1, -1, 0xf}}
862 #if 0 && defined (__GNUC__)
863 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
865 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
869 /* The same information, inverted:
870 Return the class number of the smallest class containing
871 reg number REGNO. This could be a conditional expression
872 or could index an array. */
875 #define REGNO_REG_CLASS(REGNO) \
876 ((REGNO) == 0 ? NO_REGS \
877 : ((REGNO) < 32 ? GENERAL_REGS \
878 : ((REGNO) < 96 ? FP_REGS \
881 #define REGNO_REG_CLASS(REGNO) \
882 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
885 /* This is the order in which to allocate registers normally.
887 We put %f0/%f1 last among the float registers, so as to make it more
888 likely that a pseudo-register which dies in the float return register
889 will get allocated to the float return register, thus saving a move
890 instruction at the end of the function.
892 On v9, the float registers are ordered a little "funny" because some
893 of them (%f16-%f47) are call-preserved. */
895 #define REG_ALLOC_ORDER \
896 { 8, 9, 10, 11, 12, 13, \
897 15, 16, 17, 18, 19, 20, 21, 22, \
898 23, 24, 25, 26, 27, 28, 29, 31, \
899 34, 35, 36, 37, 38, 39, /* %f2-%f7 */ \
900 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \
901 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \
902 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \
903 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \
904 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \
905 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \
906 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \
907 32, 33, /* %f0,%f1 */ \
908 96, 97, 98, 99, /* %fcc0-3 */ \
909 1, 5, 2, 3, 4, 6, 7, 0, 14, 30}
911 #define REG_ALLOC_ORDER \
912 { 8, 9, 10, 11, 12, 13, 2, 3, \
913 15, 16, 17, 18, 19, 20, 21, 22, \
914 23, 24, 25, 26, 27, 28, 29, 31, \
915 34, 35, 36, 37, 38, 39, \
916 40, 41, 42, 43, 44, 45, 46, 47, \
917 48, 49, 50, 51, 52, 53, 54, 55, \
918 56, 57, 58, 59, 60, 61, 62, 63, \
920 1, 4, 5, 6, 7, 0, 14, 30}
923 /* This is the order in which to allocate registers for
924 leaf functions. If all registers can fit in the "i" registers,
925 then we have the possibility of having a leaf function.
926 v9: The floating point registers are ordered a little "funny" because some
927 of them (%f16-%f47) are call-preserved. */
929 #define REG_LEAF_ALLOC_ORDER \
930 { 24, 25, 26, 27, 28, 29, \
931 15, 8, 9, 10, 11, 12, 13, \
932 16, 17, 18, 19, 20, 21, 22, 23, \
933 34, 35, 36, 37, 38, 39, \
934 40, 41, 42, 43, 44, 45, 46, 47, \
935 80, 81, 82, 83, 84, 85, 86, 87, \
936 88, 89, 90, 91, 92, 93, 94, 95, \
937 48, 49, 50, 51, 52, 53, 54, 55, \
938 56, 57, 58, 59, 60, 61, 62, 63, \
939 64, 65, 66, 67, 68, 69, 70, 71, \
940 72, 73, 74, 75, 76, 77, 78, 79, \
943 1, 5, 2, 3, 4, 6, 7, 0, 14, 30, 31}
945 #define REG_LEAF_ALLOC_ORDER \
946 { 2, 3, 24, 25, 26, 27, 28, 29, \
947 15, 8, 9, 10, 11, 12, 13, \
948 16, 17, 18, 19, 20, 21, 22, 23, \
949 34, 35, 36, 37, 38, 39, \
950 40, 41, 42, 43, 44, 45, 46, 47, \
951 48, 49, 50, 51, 52, 53, 54, 55, \
952 56, 57, 58, 59, 60, 61, 62, 63, \
954 1, 4, 5, 6, 7, 0, 14, 30, 31}
957 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
959 /* ??? %g7 is not a leaf register to effectively #undef LEAF_REGISTERS when
960 -mflat is used. Function only_leaf_regs_used will return 0 if a global
961 register is used and is not permitted in a leaf function. We make %g7
962 a global reg if -mflat and voila. Since %g7 is a system register and is
963 fixed it won't be used by gcc anyway. */
965 #define LEAF_REGISTERS \
966 { 1, 1, 1, 1, 1, 1, 1, 0, \
967 0, 0, 0, 0, 0, 0, 1, 0, \
968 0, 0, 0, 0, 0, 0, 0, 0, \
969 1, 1, 1, 1, 1, 1, 0, 1, \
970 1, 1, 1, 1, 1, 1, 1, 1, \
971 1, 1, 1, 1, 1, 1, 1, 1, \
972 1, 1, 1, 1, 1, 1, 1, 1, \
973 1, 1, 1, 1, 1, 1, 1, 1, \
974 1, 1, 1, 1, 1, 1, 1, 1, \
975 1, 1, 1, 1, 1, 1, 1, 1, \
976 1, 1, 1, 1, 1, 1, 1, 1, \
977 1, 1, 1, 1, 1, 1, 1, 1, \
980 #define LEAF_REGISTERS \
981 { 1, 1, 1, 1, 1, 1, 1, 0, \
982 0, 0, 0, 0, 0, 0, 1, 0, \
983 0, 0, 0, 0, 0, 0, 0, 0, \
984 1, 1, 1, 1, 1, 1, 0, 1, \
985 1, 1, 1, 1, 1, 1, 1, 1, \
986 1, 1, 1, 1, 1, 1, 1, 1, \
987 1, 1, 1, 1, 1, 1, 1, 1, \
988 1, 1, 1, 1, 1, 1, 1, 1}
991 extern char leaf_reg_remap
[];
992 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
994 /* The class value for index registers, and the one for base regs. */
995 #define INDEX_REG_CLASS GENERAL_REGS
996 #define BASE_REG_CLASS GENERAL_REGS
998 /* Get reg_class from a letter such as appears in the machine description. */
1001 #define REG_CLASS_FROM_LETTER(C) \
1002 ((C) == 'f' ? FP_REGS : (C) == 'c' ? FPCC_REGS : NO_REGS)
1004 #define REG_CLASS_FROM_LETTER(C) \
1005 ((C) == 'f' ? FP_REGS : NO_REGS)
1008 /* The letters I, J, K, L and M in a register constraint string
1009 can be used to stand for particular ranges of immediate operands.
1010 This macro defines what the ranges are.
1011 C is the letter, and VALUE is a constant value.
1012 Return 1 if VALUE is in the range specified by C.
1014 For SPARC, `I' is used for the range of constants an insn
1015 can actually contain.
1016 `J' is used for the range which is just zero (since that is R0).
1017 `K' is used for constants which can be loaded with a single sethi insn. */
1019 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
1021 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1022 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
1023 : (C) == 'J' ? (VALUE) == 0 \
1024 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
1027 /* Similar, but for floating constants, and defining letters G and H.
1028 Here VALUE is the CONST_DOUBLE rtx itself. */
1030 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1031 ((C) == 'G' ? fp_zero_operand (VALUE) \
1032 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
1035 /* Given an rtx X being reloaded into a reg required to be
1036 in class CLASS, return the class of reg to actually use.
1037 In general this is just CLASS; but on some machines
1038 in some cases it is preferable to use a more restrictive class. */
1039 /* We can't load constants into FP registers. We can't load any FP constant
1040 if an 'E' constraint fails to match it. */
1041 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1043 && ((CLASS) == FP_REGS \
1044 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1045 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
1046 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
1047 ? NO_REGS : (CLASS))
1049 /* Return the register class of a scratch register needed to load IN into
1050 a register of class CLASS in MODE.
1052 On the SPARC, when PIC, we need a temporary when loading some addresses
1055 Also, we need a temporary when loading/storing a HImode/QImode value
1056 between memory and the FPU registers. This can happen when combine puts
1057 a paradoxical subreg in a float/fix conversion insn. */
1059 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1060 (((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode)\
1061 && (GET_CODE (IN) == MEM \
1062 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1063 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
1065 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
1066 ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode) \
1067 && (GET_CODE (IN) == MEM \
1068 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
1069 && true_regnum (IN) == -1)) ? GENERAL_REGS : NO_REGS)
1071 /* On SPARC it is not possible to directly move data between
1072 GENERAL_REGS and FP_REGS. */
1073 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) ((CLASS1) != (CLASS2))
1075 /* Return the stack location to use for secondary memory needed reloads. */
1076 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1077 gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
1078 GEN_INT (STARTING_FRAME_OFFSET)))
1080 /* Get_secondary_mem widens it's argument to BITS_PER_WORD which loses on v9
1081 because the movsi and movsf patterns don't handle r/f moves.
1082 For v8 we copy the default definition. */
1083 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \
1085 ? (GET_MODE_BITSIZE (mode) < 32 \
1086 ? mode_for_size (32, GET_MODE_CLASS (mode), 0) \
1088 : (GET_MODE_BITSIZE (mode) < BITS_PER_WORD \
1089 ? mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0) \
1092 /* Return the maximum number of consecutive registers
1093 needed to represent mode MODE in a register of class CLASS. */
1094 /* On SPARC, this is the size of MODE in words. */
1095 #define CLASS_MAX_NREGS(CLASS, MODE) \
1096 ((CLASS) == FP_REGS ? (GET_MODE_SIZE (MODE) + 3) / 4 \
1097 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1099 /* Stack layout; function entry, exit and calling. */
1101 /* Define the number of register that can hold parameters.
1102 These two macros are used only in other macro definitions below.
1103 MODE is the mode of the argument.
1104 !v9: All args are passed in %o0-%o5.
1105 v9: Non-float args are passed in %o0-5 and float args are passed in
1107 #define NPARM_REGS(MODE) \
1108 (TARGET_V9 ? (GET_MODE_CLASS (MODE) == MODE_FLOAT ? 16 : 6) : 6)
1110 /* Define this if pushing a word on the stack
1111 makes the stack pointer a smaller address. */
1112 #define STACK_GROWS_DOWNWARD
1114 /* Define this if the nominal address of the stack frame
1115 is at the high-address end of the local variables;
1116 that is, each additional local variable allocated
1117 goes at a more negative offset in the frame. */
1118 #define FRAME_GROWS_DOWNWARD
1120 /* Offset within stack frame to start allocating local variables at.
1121 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1122 first local allocated. Otherwise, it is the offset to the BEGINNING
1123 of the first local allocated. */
1124 /* This allows space for one TFmode floating point value. */
1125 #define STARTING_FRAME_OFFSET \
1126 (TARGET_V9 ? (SPARC_STACK_BIAS - 16) \
1127 : (-SPARC_STACK_ALIGN (LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)))
1129 /* If we generate an insn to push BYTES bytes,
1130 this says how many the stack pointer really advances by.
1131 On SPARC, don't define this because there are no push insns. */
1132 /* #define PUSH_ROUNDING(BYTES) */
1134 /* Offset of first parameter from the argument pointer register value.
1135 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg
1136 even if this function isn't going to use it.
1137 v9: This is 128 for the ins and locals, plus a reserved space of 8. */
1138 #define FIRST_PARM_OFFSET(FNDECL) \
1139 (TARGET_V9 ? (SPARC_STACK_BIAS + 136) \
1140 : (STRUCT_VALUE_OFFSET + UNITS_PER_WORD))
1142 /* When a parameter is passed in a register, stack space is still
1143 allocated for it. */
1145 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS (SImode) * UNITS_PER_WORD)
1148 /* Keep the stack pointer constant throughout the function.
1149 This is both an optimization and a necessity: longjmp
1150 doesn't behave itself when the stack pointer moves within
1152 #define ACCUMULATE_OUTGOING_ARGS
1154 /* Value is the number of bytes of arguments automatically
1155 popped when returning from a subroutine call.
1156 FUNTYPE is the data type of the function (as a tree),
1157 or for a library call it is an identifier node for the subroutine name.
1158 SIZE is the number of bytes of arguments passed on the stack. */
1160 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
1162 /* Some subroutine macros specific to this machine.
1163 When !TARGET_FPU, put float return values in the general registers,
1164 since we don't have any fp registers. */
1165 #define BASE_RETURN_VALUE_REG(MODE) \
1166 (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1167 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8))
1168 #define BASE_OUTGOING_VALUE_REG(MODE) \
1169 (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1170 : TARGET_FRW ? 8 : 24) \
1171 : (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
1172 : (TARGET_FRW ? 8 : 24)))
1173 #define BASE_PASSING_ARG_REG(MODE) \
1174 (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 : 8) \
1176 #define BASE_INCOMING_ARG_REG(MODE) \
1177 (TARGET_V9 ? (TARGET_FPU && GET_MODE_CLASS (MODE) == MODE_FLOAT ? 32 \
1178 : TARGET_FRW ? 8 : 24) \
1179 : (TARGET_FRW ? 8 : 24))
1181 /* Define this macro if the target machine has "register windows". This
1182 C expression returns the register number as seen by the called function
1183 corresponding to register number OUT as seen by the calling function.
1184 Return OUT if register number OUT is not an outbound register. */
1186 #define INCOMING_REGNO(OUT) \
1187 ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
1189 /* Define this macro if the target machine has "register windows". This
1190 C expression returns the register number as seen by the calling function
1191 corresponding to register number IN as seen by the called function.
1192 Return IN if register number IN is not an inbound register. */
1194 #define OUTGOING_REGNO(IN) \
1195 ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
1197 /* Define how to find the value returned by a function.
1198 VALTYPE is the data type of the value (as a tree).
1199 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1200 otherwise, FUNC is 0. */
1202 /* On SPARC the value is found in the first "output" register. */
1204 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1205 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
1207 /* But the called function leaves it in the first "input" register. */
1209 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
1210 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
1212 /* Define how to find the value returned by a library function
1213 assuming the value has mode MODE. */
1215 #define LIBCALL_VALUE(MODE) \
1216 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
1218 /* 1 if N is a possible register number for a function value
1219 as seen by the caller.
1220 On SPARC, the first "output" reg is used for integer values,
1221 and the first floating point register is used for floating point values. */
1223 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
1225 /* Define the size of space to allocate for the return value of an
1228 #define APPLY_RESULT_SIZE 16
1230 /* 1 if N is a possible register number for function argument passing.
1231 On SPARC, these are the "output" registers. v9 also uses %f0-%f15. */
1233 #define FUNCTION_ARG_REGNO_P(N) \
1234 (TARGET_V9 ? (((N) < 14 && (N) > 7) || (N) > 31 && (N) < 48) \
1235 : ((N) < 14 && (N) > 7))
1237 /* Define a data type for recording info about an argument list
1238 during the scan of that argument list. This data type should
1239 hold all necessary information about the function itself
1240 and about the args processed so far, enough to enable macros
1241 such as FUNCTION_ARG to determine where the next arg should go.
1243 On SPARC (!v9), this is a single integer, which is a number of words
1244 of arguments scanned so far (including the invisible argument,
1245 if any, which holds the structure-value-address).
1246 Thus 7 or more means all following args should go on the stack.
1248 For v9, we record how many of each type has been passed. Different
1249 types get passed differently.
1251 - Float args are passed in %f0-15, after which they go to the stack
1252 where floats and doubles are passed 8 byte aligned and long doubles
1253 are passed 16 byte aligned.
1254 - All aggregates are passed by reference. The callee copies
1255 the structure if necessary, except if stdarg/varargs and the struct
1256 matches the ellipse in which case the caller makes a copy.
1257 - Any non-float argument might be split between memory and reg %o5.
1258 ??? I don't think this can ever happen now that structs are no
1259 longer passed in regs.
1261 For v9 return values:
1263 - For all aggregates, the caller allocates space for the return value,
1264 and passes the pointer as an implicit first argument, which is
1265 allocated like all other arguments.
1266 - The unimp instruction stuff for structure returns is gone. */
1269 enum sparc_arg_class
{ SPARC_ARG_INT
= 0, SPARC_ARG_FLOAT
= 1 };
1271 int arg_count
[2]; /* must be int! (for __builtin_args_info) */
1273 #define CUMULATIVE_ARGS struct sparc_args
1275 /* Return index into CUMULATIVE_ARGS. */
1277 #define GET_SPARC_ARG_CLASS(MODE) \
1278 (GET_MODE_CLASS (MODE) == MODE_FLOAT ? SPARC_ARG_FLOAT : SPARC_ARG_INT)
1280 /* Round a register number up to a proper boundary for an arg of mode MODE.
1281 This macro is only used in this file.
1283 The "& (0x10000 - ...)" is used to round up to the next appropriate reg. */
1285 #define ROUND_REG(CUM, MODE) \
1286 (GET_MODE_CLASS (MODE) != MODE_FLOAT \
1287 ? (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1288 : ((CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] \
1289 + GET_MODE_UNIT_SIZE (MODE) / 4 - 1) \
1290 & (0x10000 - GET_MODE_UNIT_SIZE (MODE) / 4))
1292 #define ROUND_ADVANCE(SIZE) \
1293 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1295 #else /* ! SPARCV9 */
1296 #define CUMULATIVE_ARGS int
1298 #define ROUND_REG(CUM, MODE) (CUM)
1300 #define ROUND_ADVANCE(SIZE) \
1301 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1302 #endif /* ! SPARCV9 */
1304 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1305 for a call to a function whose data type is FNTYPE.
1306 For a library call, FNTYPE is 0.
1308 On SPARC, the offset always starts at 0: the first parm reg is always
1312 extern int sparc_arg_count
,sparc_n_named_args
;
1313 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
1315 (CUM).arg_count[(int) SPARC_ARG_INT] = 0; \
1316 (CUM).arg_count[(int) SPARC_ARG_FLOAT] = 0; \
1317 sparc_arg_count = 0; \
1318 sparc_n_named_args = \
1319 ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE) \
1320 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) \
1321 + (TREE_CODE (TREE_TYPE (FNTYPE)) == RECORD_TYPE \
1322 || TREE_CODE (TREE_TYPE (FNTYPE)) == UNION_TYPE)) \
1323 /* Can't tell, treat 'em all as named. */ \
1327 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
1330 /* Update the data in CUM to advance over an argument
1331 of mode MODE and data type TYPE.
1332 (TYPE is null for libcalls where that information may not be available.) */
1335 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1337 (CUM).arg_count[(int) GET_SPARC_ARG_CLASS (MODE)] = \
1338 ROUND_REG ((CUM), (MODE)) \
1339 + (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1340 ? GET_MODE_SIZE (MODE) / 4 \
1341 : ROUND_ADVANCE ((MODE) == BLKmode \
1342 ? GET_MODE_SIZE (Pmode) \
1343 : GET_MODE_SIZE (MODE))); \
1344 sparc_arg_count++; \
1347 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1348 ((CUM) += ((MODE) != BLKmode \
1349 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
1350 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
1353 /* Return boolean indicating arg of mode MODE will be passed in a reg.
1354 This macro is only used in this file. */
1357 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1358 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS (MODE) \
1359 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1360 && ((TYPE)==0 || (MODE) != BLKmode))
1362 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1363 ((CUM) < NPARM_REGS (SImode) \
1364 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
1365 && ((TYPE)==0 || (MODE) != BLKmode \
1366 || (TYPE_ALIGN (TYPE) % PARM_BOUNDARY == 0)))
1369 /* Determine where to put an argument to a function.
1370 Value is zero to push the argument on the stack,
1371 or a hard register in which to store the argument.
1373 MODE is the argument's machine mode.
1374 TYPE is the data type of the argument (as a tree).
1375 This is null for libcalls where that information may
1377 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1378 the preceding args and about the function being called.
1379 NAMED is nonzero if this argument is a named parameter
1380 (otherwise it is an extra parameter matching an ellipsis). */
1382 /* On SPARC the first six args are normally in registers
1383 and the rest are pushed. Any arg that starts within the first 6 words
1384 is at least partially passed in a register unless its data type forbids.
1385 For v9, the first 6 int args are passed in regs and the first N
1386 float args are passed in regs (where N is such that %f0-15 are filled).
1387 The rest are pushed. Any arg that starts within the first 6 words
1388 is at least partially passed in a register unless its data type forbids. */
1390 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1391 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1392 ? gen_rtx (REG, (MODE), \
1393 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1396 /* Define where a function finds its arguments.
1397 This is different from FUNCTION_ARG because of register windows. */
1399 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
1400 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1401 ? gen_rtx (REG, (MODE), \
1402 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE))))\
1405 /* For an arg passed partly in registers and partly in memory,
1406 this is the number of registers used.
1407 For args passed entirely in registers or entirely in memory, zero.
1408 Any arg that starts in the first 6 regs but won't entirely fit in them
1409 needs partial registers on the Sparc (!v9). On v9, there are no arguments
1410 that are passed partially in registers (??? complex values?). */
1413 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1414 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \
1415 && ((CUM) + ((MODE) == BLKmode \
1416 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
1417 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS (SImode) > 0)\
1418 ? (NPARM_REGS (SImode) - (CUM)) \
1422 /* The SPARC ABI stipulates passing struct arguments (of any size) and
1423 (!v9) quad-precision floats by invisible reference.
1424 For Pascal, also pass arrays by reference. */
1425 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1426 ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
1427 || TREE_CODE (TYPE) == UNION_TYPE \
1428 || TREE_CODE (TYPE) == ARRAY_TYPE)) \
1429 || (!TARGET_V9 && MODE == TFmode))
1431 /* A C expression that indicates when it is the called function's
1432 responsibility to make copies of arguments passed by reference.
1433 If the callee can determine that the argument won't be modified, it can
1435 /* ??? We'd love to be able to use NAMED here. Unfortunately, it doesn't
1436 include the last named argument so we keep track of the args ourselves. */
1439 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
1440 (sparc_arg_count < sparc_n_named_args)
1443 /* Initialize data used by insn expanders. This is called from
1444 init_emit, once for each function, before code is generated.
1445 For v9, clear the temp slot used by float/int DImode conversions.
1446 ??? There is the 16 bytes at [%fp-16], however we'd like to delete this
1447 space at some point.
1448 ??? Use assign_stack_temp? */
1450 extern void sparc64_init_expanders ();
1451 extern struct rtx_def
*sparc64_fpconv_stack_temp ();
1453 #define INIT_EXPANDERS sparc64_init_expanders ()
1456 /* Define the information needed to generate branch and scc insns. This is
1457 stored from the compare operation. Note that we can't use "rtx" here
1458 since it hasn't been defined! */
1460 extern struct rtx_def
*sparc_compare_op0
, *sparc_compare_op1
;
1462 /* Define the function that build the compare insn for scc and bcc. */
1464 extern struct rtx_def
*gen_compare_reg ();
1466 /* This function handles all v9 scc insns */
1468 extern int gen_v9_scc ();
1470 /* ??? This is a hack until conditional move support is complete. */
1471 #define HAVE_conditional_move (TARGET_V9)
1473 /* Generate the special assembly code needed to tell the assembler whatever
1474 it might need to know about the return value of a function.
1476 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
1477 information to the assembler relating to peephole optimization (done in
1480 #define ASM_DECLARE_RESULT(FILE, RESULT) \
1481 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
1483 /* Output the label for a function definition. */
1485 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
1487 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
1488 ASM_OUTPUT_LABEL (FILE, NAME); \
1491 /* This macro generates the assembly code for function entry.
1492 FILE is a stdio stream to output the code to.
1493 SIZE is an int: how many units of temporary storage to allocate.
1494 Refer to the array `regs_ever_live' to determine which registers
1495 to save; `regs_ever_live[I]' is nonzero if register number I
1496 is ever used in the function. This macro is responsible for
1497 knowing which registers should not be saved even if used. */
1499 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
1500 of memory. If any fpu reg is used in the function, we allocate
1501 such a block here, at the bottom of the frame, just in case it's needed.
1503 If this function is a leaf procedure, then we may choose not
1504 to do a "save" insn. The decision about whether or not
1505 to do this is made in regclass.c. */
1507 #define FUNCTION_PROLOGUE(FILE, SIZE) \
1508 (TARGET_FRW ? sparc_flat_output_function_prologue (FILE, SIZE) \
1509 : output_function_prologue (FILE, SIZE, leaf_function))
1511 /* Output assembler code to FILE to increment profiler label # LABELNO
1512 for profiling a function entry. */
1514 #define FUNCTION_PROFILER(FILE, LABELNO) \
1516 fputs ("\tsethi %hi(", (FILE)); \
1517 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
1518 fputs ("),%o0\n", (FILE)); \
1519 if (TARGET_MEDANY) \
1520 fprintf (FILE, "\tadd %%o0,%s,%%o0\n", \
1522 fputs ("\tcall mcount\n\tadd %lo(", (FILE)); \
1523 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
1524 fputs ("),%o0,%o0\n", (FILE)); \
1527 /* Output assembler code to FILE to initialize this source file's
1528 basic block profiling info, if that has not already been done. */
1529 /* FIXME -- this does not parameterize how it generates labels (like the
1530 above FUNCTION_PROFILER). Broken on Solaris-2. --gnu@cygnus.com */
1532 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1534 if (TARGET_MEDANY) \
1535 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tor %%0,%%lo(LPBX0),%%o0\n\tld [%s+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%s,%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
1536 MEDANY_BASE_REG, (LABELNO), MEDANY_BASE_REG, (LABELNO)); \
1538 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
1539 (LABELNO), (LABELNO)); \
1542 /* Output assembler code to FILE to increment the entry-count for
1543 the BLOCKNO'th basic block in this source file. */
1545 #define BLOCK_PROFILER(FILE, BLOCKNO) \
1547 int blockn = (BLOCKNO); \
1548 if (TARGET_MEDANY) \
1549 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tor %%g1,%%lo(LPBX2+%d),%%g1\n\tld [%%g1+%s],%%g2\n\tadd %%g2,1,%%g2\n\tst %%g2,[%%g1+%s]\n", \
1550 4 * blockn, 4 * blockn, MEDANY_BASE_REG, MEDANY_BASE_REG); \
1552 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
1553 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
1554 4 * blockn, 4 * blockn, 4 * blockn); \
1557 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1558 the stack pointer does not matter. The value is tested only in
1559 functions that have frame pointers.
1560 No definition is equivalent to always zero. */
1562 extern int current_function_calls_alloca
;
1563 extern int current_function_outgoing_args_size
;
1565 #define EXIT_IGNORE_STACK \
1566 (get_frame_size () != 0 \
1567 || current_function_calls_alloca || current_function_outgoing_args_size)
1569 /* This macro generates the assembly code for function exit,
1570 on machines that need it. If FUNCTION_EPILOGUE is not defined
1571 then individual return instructions are generated for each
1572 return statement. Args are same as for FUNCTION_PROLOGUE.
1574 The function epilogue should not depend on the current stack pointer!
1575 It should use the frame pointer only. This is mandatory because
1576 of alloca; we also take advantage of it to omit stack adjustments
1577 before returning. */
1579 /* This declaration is needed due to traditional/ANSI
1580 incompatibilities which cannot be #ifdefed away
1581 because they occur inside of macros. Sigh. */
1582 extern union tree_node
*current_function_decl
;
1584 #define FUNCTION_EPILOGUE(FILE, SIZE) \
1585 (TARGET_FRW ? sparc_flat_output_function_epilogue (FILE, SIZE) \
1586 : output_function_epilogue (FILE, SIZE, leaf_function))
1588 #define DELAY_SLOTS_FOR_EPILOGUE \
1589 (TARGET_FRW ? sparc_flat_epilogue_delay_slots () : 1)
1590 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1591 (TARGET_FRW ? sparc_flat_eligible_for_epilogue_delay (trial, slots_filled) \
1592 : eligible_for_epilogue_delay (trial, slots_filled))
1594 /* Output assembler code for a block containing the constant parts
1595 of a trampoline, leaving space for the variable parts. */
1597 /* On the sparc, the trampoline contains five instructions:
1598 sethi #TOP_OF_FUNCTION,%g1
1599 or #BOTTOM_OF_FUNCTION,%g1,%g1
1600 sethi #TOP_OF_STATIC,%g2
1602 or #BOTTOM_OF_STATIC,%g2,%g2 */
1603 #define TRAMPOLINE_TEMPLATE(FILE) \
1605 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1606 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1607 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1608 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \
1609 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1612 /* Length in units of the trampoline for entering a nested function. */
1614 #define TRAMPOLINE_SIZE 20
1616 /* Emit RTL insns to initialize the variable parts of a trampoline.
1617 FNADDR is an RTX for the address of the function's pure code.
1618 CXT is an RTX for the static chain value for the function. */
1620 void sparc_initialize_trampoline ();
1621 void sparc64_initialize_trampoline ();
1622 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1625 sparc64_initialize_trampoline (TRAMP, FNADDR, CXT); \
1627 sparc_initialize_trampoline (TRAMP, FNADDR, CXT); \
1630 /* Generate necessary RTL for __builtin_saveregs().
1631 ARGLIST is the argument list; see expr.c. */
1632 extern struct rtx_def
*sparc_builtin_saveregs ();
1633 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
1635 /* Generate RTL to flush the register windows so as to make arbitrary frames
1637 #define SETUP_FRAME_ADDRESSES() \
1638 emit_insn (gen_flush_register_windows ())
1640 /* Given an rtx for the address of a frame,
1641 return an rtx for the address of the word in the frame
1642 that holds the dynamic chain--the previous frame's address.
1643 ??? -mflat support? */
1644 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1645 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 14 * UNITS_PER_WORD))
1647 /* The return address isn't on the stack, it is in a register, so we can't
1648 access it from the current frame pointer. We can access it from the
1649 previous frame pointer though by reading a value from the register window
1651 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1653 /* The current return address is in %i7. The return address of anything
1654 farther back is in the register window save area at [%fp+60]. */
1655 /* ??? This ignores the fact that the actual return address is +8 for normal
1656 returns, and +12 for structure returns. */
1657 #define RETURN_ADDR_RTX(count, frame) \
1659 ? gen_rtx (REG, Pmode, 31) \
1660 : copy_to_reg (gen_rtx (MEM, Pmode, \
1661 memory_address (Pmode, plus_constant (frame, 15 * UNITS_PER_WORD)))))
1663 /* Addressing modes, and classification of registers for them. */
1665 /* #define HAVE_POST_INCREMENT */
1666 /* #define HAVE_POST_DECREMENT */
1668 /* #define HAVE_PRE_DECREMENT */
1669 /* #define HAVE_PRE_INCREMENT */
1671 /* Macros to check register numbers against specific register classes. */
1673 /* These assume that REGNO is a hard or pseudo reg number.
1674 They give nonzero only if REGNO is a hard reg of the suitable class
1675 or a pseudo reg currently allocated to a suitable hard reg.
1676 Since they use reg_renumber, they are safe only once reg_renumber
1677 has been allocated, which happens in local-alloc.c. */
1679 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1680 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1681 #define REGNO_OK_FOR_BASE_P(REGNO) \
1682 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1683 #define REGNO_OK_FOR_FP_P(REGNO) \
1684 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? 64 : 32)) \
1685 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? 64 : 32)))
1686 #define REGNO_OK_FOR_CCFP_P(REGNO) \
1688 && ((unsigned) (REGNO) - 96 < 4) || ((unsigned) reg_renumber[REGNO] - 96 < 4))
1690 /* Now macros that check whether X is a register and also,
1691 strictly, whether it is in a specified class.
1693 These macros are specific to the SPARC, and may be used only
1694 in code for printing assembler insns and in conditions for
1695 define_optimization. */
1697 /* 1 if X is an fp register. */
1699 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1701 /* Maximum number of registers that can appear in a valid memory address. */
1703 #define MAX_REGS_PER_ADDRESS 2
1705 /* Recognize any constant value that is a valid address.
1706 When PIC, we do not accept an address that would require a scratch reg
1707 to load into a register. */
1709 #define CONSTANT_ADDRESS_P(X) \
1710 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1711 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1712 || (GET_CODE (X) == CONST \
1713 && ! (flag_pic && pic_address_needs_scratch (X))))
1715 /* Define this, so that when PIC, reload won't try to reload invalid
1716 addresses which require two reload registers. */
1718 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
1720 /* Nonzero if the constant value X is a legitimate general operand.
1721 Anything can be made to work except floating point constants. */
1723 #define LEGITIMATE_CONSTANT_P(X) \
1724 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1726 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1727 and check its validity for a certain class.
1728 We have two alternate definitions for each of them.
1729 The usual definition accepts all pseudo regs; the other rejects
1730 them unless they have been allocated suitable hard regs.
1731 The symbol REG_OK_STRICT causes the latter definition to be used.
1733 Most source files want to accept pseudo regs in the hope that
1734 they will get allocated to the class that the insn wants them to be in.
1735 Source files for reload pass need to be strict.
1736 After reload, it makes no difference, since pseudo regs have
1737 been eliminated by then. */
1739 /* Optional extra constraints for this machine. Borrowed from romp.h.
1741 For the SPARC, `Q' means that this is a memory operand but not a
1742 symbolic memory operand. Note that an unassigned pseudo register
1743 is such a memory operand. Needed because reload will generate
1744 these things in insns and then not re-recognize the insns, causing
1745 constrain_operands to fail.
1747 `S' handles constraints for calls. ??? So where is it? */
1749 #ifndef REG_OK_STRICT
1751 /* Nonzero if X is a hard reg that can be used as an index
1752 or if it is a pseudo reg. */
1753 #define REG_OK_FOR_INDEX_P(X) \
1754 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0)
1755 /* Nonzero if X is a hard reg that can be used as a base reg
1756 or if it is a pseudo reg. */
1757 #define REG_OK_FOR_BASE_P(X) \
1758 (((unsigned) REGNO (X)) - 32 >= (FIRST_PSEUDO_REGISTER - 32) && REGNO (X) != 0)
1760 /* 'T', 'U' are for aligned memory loads which aren't needed for v9. */
1762 #define EXTRA_CONSTRAINT(OP, C) \
1764 ? ((GET_CODE (OP) == MEM \
1765 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1766 && ! symbolic_memory_operand (OP, VOIDmode)) \
1767 || (reload_in_progress && GET_CODE (OP) == REG \
1768 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1769 : ! TARGET_V9 && (C) == 'T' \
1770 ? (mem_aligned_8 (OP)) \
1771 : ! TARGET_V9 && (C) == 'U' \
1772 ? (register_ok_for_ldd (OP)) \
1777 /* Nonzero if X is a hard reg that can be used as an index. */
1778 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1779 /* Nonzero if X is a hard reg that can be used as a base reg. */
1780 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1782 #define EXTRA_CONSTRAINT(OP, C) \
1784 ? (GET_CODE (OP) == REG \
1785 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1786 && reg_renumber[REGNO (OP)] < 0) \
1787 : GET_CODE (OP) == MEM) \
1788 : ! TARGET_V9 && (C) == 'T' \
1789 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
1790 : ! TARGET_V9 && (C) == 'U' \
1791 ? (GET_CODE (OP) == REG \
1792 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
1793 || reg_renumber[REGNO (OP)] > 0) \
1794 && register_ok_for_ldd (OP)) : 0)
1797 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1798 that is a valid memory address for an instruction.
1799 The MODE argument is the machine mode for the MEM expression
1800 that wants to use this address.
1802 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1803 ordinarily. This changes a bit when generating PIC.
1805 If you change this, execute "rm explow.o recog.o reload.o". */
1807 #define RTX_OK_FOR_BASE_P(X) \
1808 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1809 || (GET_CODE (X) == SUBREG \
1810 && GET_CODE (SUBREG_REG (X)) == REG \
1811 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1813 #define RTX_OK_FOR_INDEX_P(X) \
1814 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1815 || (GET_CODE (X) == SUBREG \
1816 && GET_CODE (SUBREG_REG (X)) == REG \
1817 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1819 #define RTX_OK_FOR_OFFSET_P(X) \
1820 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1822 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1823 { if (RTX_OK_FOR_BASE_P (X)) \
1825 else if (GET_CODE (X) == PLUS) \
1827 register rtx op0 = XEXP (X, 0); \
1828 register rtx op1 = XEXP (X, 1); \
1829 if (flag_pic && op0 == pic_offset_table_rtx) \
1831 if (RTX_OK_FOR_BASE_P (op1)) \
1833 else if (flag_pic == 1 \
1834 && GET_CODE (op1) != REG \
1835 && GET_CODE (op1) != LO_SUM \
1836 && GET_CODE (op1) != MEM \
1837 && (GET_CODE (op1) != CONST_INT \
1838 || SMALL_INT (op1))) \
1841 else if (RTX_OK_FOR_BASE_P (op0)) \
1843 if (RTX_OK_FOR_INDEX_P (op1) \
1844 || RTX_OK_FOR_OFFSET_P (op1)) \
1847 else if (RTX_OK_FOR_BASE_P (op1)) \
1849 if (RTX_OK_FOR_INDEX_P (op0) \
1850 || RTX_OK_FOR_OFFSET_P (op0)) \
1854 else if (GET_CODE (X) == LO_SUM) \
1856 register rtx op0 = XEXP (X, 0); \
1857 register rtx op1 = XEXP (X, 1); \
1858 if (RTX_OK_FOR_BASE_P (op0) \
1859 && CONSTANT_P (op1)) \
1862 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1866 /* Try machine-dependent ways of modifying an illegitimate address
1867 to be legitimate. If we find one, return the new, valid address.
1868 This macro is used in only one place: `memory_address' in explow.c.
1870 OLDX is the address as it was before break_out_memory_refs was called.
1871 In some cases it is useful to look at this to decide what needs to be done.
1873 MODE and WIN are passed so that this macro can use
1874 GO_IF_LEGITIMATE_ADDRESS.
1876 It is always safe for this macro to do nothing. It exists to recognize
1877 opportunities to optimize the output. */
1879 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1880 extern struct rtx_def
*legitimize_pic_address ();
1881 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1882 { rtx sparc_x = (X); \
1883 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1884 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1885 force_operand (XEXP (X, 0), NULL_RTX)); \
1886 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1887 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1888 force_operand (XEXP (X, 1), NULL_RTX)); \
1889 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1890 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
1892 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1893 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1894 force_operand (XEXP (X, 1), NULL_RTX)); \
1895 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1897 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
1898 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1899 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1900 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1901 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1902 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1903 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1904 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1905 || GET_CODE (X) == LABEL_REF) \
1906 (X) = gen_rtx (LO_SUM, Pmode, \
1907 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1908 if (memory_address_p (MODE, X)) \
1911 /* Go to LABEL if ADDR (a legitimate address expression)
1912 has an effect that depends on the machine mode it is used for.
1913 On the SPARC this is never true. */
1915 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1917 /* If we are referencing a function make the SYMBOL_REF special.
1918 In the Medium/Anywhere code model, %g4 points to the data segment so we
1919 must not add it to function addresses. */
1921 #define ENCODE_SECTION_INFO(DECL) \
1923 if (TARGET_MEDANY && TREE_CODE (DECL) == FUNCTION_DECL) \
1924 SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
1927 /* Specify the machine mode that this machine uses
1928 for the index in the tablejump instruction. */
1929 #define CASE_VECTOR_MODE Pmode
1931 /* Define this if the tablejump instruction expects the table
1932 to contain offsets from the address of the table.
1933 Do not define this if the table should contain absolute addresses. */
1934 /* #define CASE_VECTOR_PC_RELATIVE */
1936 /* Specify the tree operation to be used to convert reals to integers. */
1937 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1939 /* This is the kind of divide that is easiest to do in the general case. */
1940 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1942 /* Define this as 1 if `char' should by default be signed; else as 0. */
1943 #define DEFAULT_SIGNED_CHAR 1
1945 /* Max number of bytes we can move from memory to memory
1946 in one reasonably fast instruction. */
1949 #if 0 /* Sun 4 has matherr, so this is no good. */
1950 /* This is the value of the error code EDOM for this machine,
1951 used by the sqrt instruction. */
1952 #define TARGET_EDOM 33
1954 /* This is how to refer to the variable errno. */
1955 #define GEN_ERRNO_RTX \
1956 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
1959 /* Define if operations between registers always perform the operation
1960 on the full register even if a narrower mode is specified. */
1961 #define WORD_REGISTER_OPERATIONS
1963 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1964 will either zero-extend or sign-extend. The value of this macro should
1965 be the code that says which one of the two operations is implicitly
1966 done, NIL if none. */
1967 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1969 /* Nonzero if access to memory by bytes is slow and undesirable.
1970 For RISC chips, it means that access to memory by bytes is no
1971 better than access by words when possible, so grab a whole word
1972 and maybe make use of that. */
1973 #define SLOW_BYTE_ACCESS 1
1975 /* We assume that the store-condition-codes instructions store 0 for false
1976 and some other value for true. This is the value stored for true. */
1978 #define STORE_FLAG_VALUE 1
1980 /* When a prototype says `char' or `short', really pass an `int'. */
1981 #define PROMOTE_PROTOTYPES
1983 /* Define this to be nonzero if shift instructions ignore all but the low-order
1985 #define SHIFT_COUNT_TRUNCATED 1
1987 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1988 is done just by pretending it is already truncated. */
1989 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1991 /* Specify the machine mode that pointers have.
1992 After generation of rtl, the compiler makes no further distinction
1993 between pointers and any other objects of this machine mode. */
1994 #define Pmode (TARGET_PTR64 ? DImode : SImode)
1996 /* Generate calls to memcpy, memcmp and memset. */
1997 #define TARGET_MEM_FUNCTIONS
1999 /* Add any extra modes needed to represent the condition code.
2001 On the Sparc, we have a "no-overflow" mode which is used when an add or
2002 subtract insn is used to set the condition code. Different branches are
2003 used in this case for some operations.
2005 We also have two modes to indicate that the relevant condition code is
2006 in the floating-point condition code register. One for comparisons which
2007 will generate an exception if the result is unordered (CCFPEmode) and
2008 one for comparisons which will never trap (CCFPmode). This really should
2009 be a separate register, but we don't want to go to 65 registers.
2011 CCXmode and CCX_NOOVmode are only used by v9. */
2013 #define EXTRA_CC_MODES CCXmode, CC_NOOVmode, CCX_NOOVmode, CCFPmode, CCFPEmode
2015 /* Define the names for the modes specified above. */
2017 #define EXTRA_CC_NAMES "CCX", "CC_NOOV", "CCX_NOOV", "CCFP", "CCFPE"
2019 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2020 return the mode to be used for the comparison. For floating-point,
2021 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
2022 PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2023 processing is needed. */
2024 #define SELECT_CC_MODE(OP,X,Y) \
2025 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2026 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
2027 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
2028 || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \
2029 ? (TARGET_V9 && GET_MODE (X) == DImode ? CCX_NOOVmode : CC_NOOVmode) \
2030 : (TARGET_V9 && GET_MODE (X) == DImode ? CCXmode : CCmode)))
2032 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
2033 floating point inequality comparison. */
2035 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2037 /* A function address in a call instruction
2038 is a byte address (for indexing purposes)
2039 so give the MEM rtx a byte's mode. */
2040 #define FUNCTION_MODE SImode
2042 /* Define this if addresses of constant functions
2043 shouldn't be put through pseudo regs where they can be cse'd.
2044 Desirable on machines where ordinary constants are expensive
2045 but a CALL with constant address is cheap. */
2046 #define NO_FUNCTION_CSE
2048 /* alloca should avoid clobbering the old register save area. */
2049 #define SETJMP_VIA_SAVE_AREA
2051 /* Define subroutines to call to handle multiply and divide.
2052 Use the subroutines that Sun's library provides.
2053 The `*' prevents an underscore from being prepended by the compiler. */
2055 #define DIVSI3_LIBCALL "*.div"
2056 #define UDIVSI3_LIBCALL "*.udiv"
2057 #define MODSI3_LIBCALL "*.rem"
2058 #define UMODSI3_LIBCALL "*.urem"
2059 /* .umul is a little faster than .mul. */
2060 #define MULSI3_LIBCALL "*.umul"
2062 /* Define library calls for quad FP operations. These are all part of the
2064 #define ADDTF3_LIBCALL "_Q_add"
2065 #define SUBTF3_LIBCALL "_Q_sub"
2066 #define MULTF3_LIBCALL "_Q_mul"
2067 #define DIVTF3_LIBCALL "_Q_div"
2068 #define SQRTTF2_LIBCALL "_Q_sqrt"
2069 #define FLOATSITF2_LIBCALL "_Q_itoq"
2070 #define FIX_TRUNCTFSI2_LIBCALL "_Q_qtoi"
2071 #define FIXUNS_TRUNCTFSI2_LIBCALL "_Q_qtou"
2072 #define EXTENDSFTF2_LIBCALL "_Q_stoq"
2073 #define TRUNCTFSF2_LIBCALL "_Q_qtos"
2074 #define EXTENDDFTF2_LIBCALL "_Q_dtoq"
2075 #define TRUNCTFDF2_LIBCALL "_Q_qtod"
2076 #define EQTF2_LIBCALL "_Q_feq"
2077 #define NETF2_LIBCALL "_Q_fne"
2078 #define GTTF2_LIBCALL "_Q_fgt"
2079 #define GETF2_LIBCALL "_Q_fge"
2080 #define LTTF2_LIBCALL "_Q_flt"
2081 #define LETF2_LIBCALL "_Q_fle"
2083 /* Compute the cost of computing a constant rtl expression RTX
2084 whose rtx-code is CODE. The body of this macro is a portion
2085 of a switch statement. If the code is computed here,
2086 return it with a return statement. Otherwise, break from the switch. */
2088 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2090 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
2098 case CONST_DOUBLE: \
2099 if (GET_MODE (RTX) == DImode) \
2100 if ((XINT (RTX, 3) == 0 \
2101 && (unsigned) XINT (RTX, 2) < 0x1000) \
2102 || (XINT (RTX, 3) == -1 \
2103 && XINT (RTX, 2) < 0 \
2104 && XINT (RTX, 2) >= -0x1000)) \
2108 /* Compute the cost of an address. For the sparc, all valid addresses are
2110 ??? Is this true for v9? */
2112 #define ADDRESS_COST(RTX) 1
2114 /* Compute extra cost of moving data between one register class
2116 ??? v9: We ignore FPCC_REGS on the assumption they'll never be seen. */
2117 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
2118 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
2119 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
2121 /* Provide the costs of a rtl expression. This is in the body of a
2122 switch on CODE. The purpose for the cost of MULT is to encourage
2123 `synth_mult' to find a synthetic multiply when reasonable.
2125 If we need more than 12 insns to do a multiply, then go out-of-line,
2126 since the call overhead will be < 10% of the cost of the multiply. */
2128 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2130 return (TARGET_V8 || TARGET_V9) ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
2135 return COSTS_N_INSNS (25); \
2136 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
2137 so that cse will favor the latter. */ \
2142 /* Adjust the cost of dependencies. */
2143 #define ADJUST_COST(INSN,LINK,DEP,COST) \
2144 if (TARGET_SUPERSPARC) \
2145 (COST) = supersparc_adjust_cost (INSN, LINK, DEP, COST)
2147 /* Conditional branches with empty delay slots have a length of two. */
2148 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2149 if (GET_CODE (INSN) == CALL_INSN \
2150 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
2153 /* Control the assembler format that we output. */
2155 /* Output at beginning of assembler file. */
2157 #define ASM_FILE_START(file)
2159 /* Output to assembler file text saying following lines
2160 may contain character constants, extra white space, comments, etc. */
2162 #define ASM_APP_ON ""
2164 /* Output to assembler file text saying following lines
2165 no longer contain unusual constructs. */
2167 #define ASM_APP_OFF ""
2169 /* ??? Try to make the style consistent here (_OP?). */
2171 #define ASM_LONGLONG ".xword"
2172 #define ASM_LONG ".word"
2173 #define ASM_SHORT ".half"
2174 #define ASM_BYTE_OP ".byte"
2175 #define ASM_FLOAT ".single"
2176 #define ASM_DOUBLE ".double"
2177 #define ASM_LONGDOUBLE ".xxx" /* ??? Not known (or used yet). */
2179 /* Output before read-only data. */
2181 #define TEXT_SECTION_ASM_OP ".text"
2183 /* Output before writable data. */
2185 #define DATA_SECTION_ASM_OP ".data"
2187 /* How to refer to registers in assembler output.
2188 This sequence is indexed by compiler's hard-register-number (see above). */
2191 #define REGISTER_NAMES \
2192 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2193 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2194 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2195 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2196 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2197 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2198 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2199 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \
2200 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \
2201 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \
2202 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \
2203 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \
2204 "%fcc0", "%fcc1", "%fcc2", "%fcc3"}
2206 #define REGISTER_NAMES \
2207 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
2208 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
2209 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
2210 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
2211 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
2212 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
2213 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
2214 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
2217 /* Define additional names for use in asm clobbers and asm declarations.
2219 We define the fake Condition Code register as an alias for reg 0 (which
2220 is our `condition code' register), so that condition codes can easily
2221 be clobbered by an asm. No such register actually exists. Condition
2222 codes are partly stored in the PSR and partly in the FSR. */
2224 #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
2226 /* How to renumber registers for dbx and gdb. */
2228 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
2230 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
2231 since the length can run past this up to a continuation point. */
2232 #define DBX_CONTIN_LENGTH 1500
2234 /* This is how to output a note to DBX telling it the line number
2235 to which the following sequence of instructions corresponds.
2237 This is needed for SunOS 4.0, and should not hurt for 3.2
2239 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
2240 { static int sym_lineno = 1; \
2241 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
2242 line, sym_lineno, sym_lineno); \
2245 /* This is how to output the definition of a user-level label named NAME,
2246 such as the label on a static function or variable NAME. */
2248 #define ASM_OUTPUT_LABEL(FILE,NAME) \
2249 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
2251 /* This is how to output a command to make the user-level label named NAME
2252 defined for reference from other files. */
2254 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
2255 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
2257 /* This is how to output a reference to a user-level label named NAME.
2258 `assemble_name' uses this. */
2260 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2261 fprintf (FILE, "_%s", NAME)
2263 /* This is how to output a definition of an internal numbered label where
2264 PREFIX is the class of label and NUM is the number within the class. */
2266 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
2267 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
2269 /* This is how to output a reference to an internal numbered label where
2270 PREFIX is the class of label and NUM is the number within the class. */
2271 /* FIXME: This should be used throughout gcc, and documented in the texinfo
2272 files. There is no reason you should have to allocate a buffer and
2273 `sprintf' to reference an internal label (as opposed to defining it). */
2275 #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
2276 fprintf (FILE, "%s%d", PREFIX, NUM)
2278 /* This is how to store into the string LABEL
2279 the symbol_ref name of an internal numbered label where
2280 PREFIX is the class of label and NUM is the number within the class.
2281 This is suitable for output with `assemble_name'. */
2283 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2284 sprintf (LABEL, "*%s%d", PREFIX, NUM)
2286 /* This is how to output an assembler line defining a `double' constant. */
2288 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
2291 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
2292 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2293 ASM_LONG, t[0], ASM_LONG, t[1]); \
2296 /* This is how to output an assembler line defining a `float' constant. */
2298 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
2301 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
2302 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
2305 /* This is how to output an assembler line defining a `long double'
2308 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
2311 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
2312 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
2313 ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
2316 /* This is how to output an assembler line defining an `int' constant. */
2318 #define ASM_OUTPUT_INT(FILE,VALUE) \
2319 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
2320 output_addr_const (FILE, (VALUE)), \
2321 fprintf (FILE, "\n"))
2323 /* This is how to output an assembler line defining a DImode constant. */
2324 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
2325 output_double_int (FILE, VALUE)
2327 /* Likewise for `char' and `short' constants. */
2329 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
2330 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
2331 output_addr_const (FILE, (VALUE)), \
2332 fprintf (FILE, "\n"))
2334 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
2335 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
2336 output_addr_const (FILE, (VALUE)), \
2337 fprintf (FILE, "\n"))
2339 /* This is how to output an assembler line for a numeric constant byte. */
2341 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
2342 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
2344 /* This is how to output an element of a case-vector that is absolute. */
2346 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
2349 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2350 if (Pmode == SImode) \
2351 fprintf (FILE, "\t.word\t"); \
2352 else if (TARGET_ENV32) \
2353 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2355 fprintf (FILE, "\t.xword\t"); \
2356 assemble_name (FILE, label); \
2357 fprintf (FILE, "\n"); \
2360 /* This is how to output an element of a case-vector that is relative.
2361 (SPARC uses such vectors only when generating PIC.) */
2363 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
2366 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
2367 if (Pmode == SImode) \
2368 fprintf (FILE, "\t.word\t"); \
2369 else if (TARGET_ENV32) \
2370 fprintf (FILE, "\t.word\t0\n\t.word\t"); \
2372 fprintf (FILE, "\t.xword\t"); \
2373 assemble_name (FILE, label); \
2374 fprintf (FILE, "-1b\n"); \
2377 /* This is how to output an assembler line
2378 that says to advance the location counter
2379 to a multiple of 2**LOG bytes. */
2381 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2383 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
2385 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
2386 fprintf (FILE, "\t.skip %u\n", (SIZE))
2388 /* This says how to output an assembler line
2389 to define a global common symbol. */
2391 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
2392 ( fputs ("\t.common ", (FILE)), \
2393 assemble_name ((FILE), (NAME)), \
2394 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
2396 /* This says how to output an assembler line to define a local common
2399 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
2400 ( fputs ("\t.reserve ", (FILE)), \
2401 assemble_name ((FILE), (NAME)), \
2402 fprintf ((FILE), ",%u,\"bss\",%u\n", \
2403 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
2405 /* Store in OUTPUT a string (made with alloca) containing
2406 an assembler-name for a local static variable named NAME.
2407 LABELNO is an integer which is different for each call. */
2409 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2410 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2411 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2413 #define IDENT_ASM_OP ".ident"
2415 /* Output #ident as a .ident. */
2417 #define ASM_OUTPUT_IDENT(FILE, NAME) \
2418 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
2420 /* Define the parentheses used to group arithmetic operations
2421 in assembler code. */
2423 #define ASM_OPEN_PAREN "("
2424 #define ASM_CLOSE_PAREN ")"
2426 /* Define results of standard character escape sequences. */
2427 #define TARGET_BELL 007
2428 #define TARGET_BS 010
2429 #define TARGET_TAB 011
2430 #define TARGET_NEWLINE 012
2431 #define TARGET_VT 013
2432 #define TARGET_FF 014
2433 #define TARGET_CR 015
2435 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2436 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
2438 /* Print operand X (an rtx) in assembler syntax to file FILE.
2439 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2440 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2442 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2444 /* Print a memory address as an operand to reference that memory location. */
2446 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2447 { register rtx base, index = 0; \
2449 register rtx addr = ADDR; \
2450 if (GET_CODE (addr) == REG) \
2451 fputs (reg_names[REGNO (addr)], FILE); \
2452 else if (GET_CODE (addr) == PLUS) \
2454 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2455 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
2456 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2457 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
2459 base = XEXP (addr, 0), index = XEXP (addr, 1); \
2460 fputs (reg_names[REGNO (base)], FILE); \
2462 fprintf (FILE, "%+d", offset); \
2463 else if (GET_CODE (index) == REG) \
2464 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
2465 else if (GET_CODE (index) == SYMBOL_REF) \
2466 fputc ('+', FILE), output_addr_const (FILE, index); \
2469 else if (GET_CODE (addr) == MINUS \
2470 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
2472 output_addr_const (FILE, XEXP (addr, 0)); \
2473 fputs ("-(", FILE); \
2474 output_addr_const (FILE, XEXP (addr, 1)); \
2475 fputs ("-.)", FILE); \
2477 else if (GET_CODE (addr) == LO_SUM) \
2479 output_operand (XEXP (addr, 0), 0); \
2480 fputs ("+%lo(", FILE); \
2481 output_address (XEXP (addr, 1)); \
2482 fputc (')', FILE); \
2484 else if (flag_pic && GET_CODE (addr) == CONST \
2485 && GET_CODE (XEXP (addr, 0)) == MINUS \
2486 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
2487 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
2488 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
2490 addr = XEXP (addr, 0); \
2491 output_addr_const (FILE, XEXP (addr, 0)); \
2492 /* Group the args of the second CONST in parenthesis. */ \
2493 fputs ("-(", FILE); \
2494 /* Skip past the second CONST--it does nothing for us. */\
2495 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
2496 /* Close the parenthesis. */ \
2497 fputc (')', FILE); \
2501 output_addr_const (FILE, addr); \
2505 /* Declare functions defined in sparc.c and used in templates. */
2507 extern char *singlemove_string ();
2508 extern char *output_move_double ();
2509 extern char *output_move_quad ();
2510 extern char *output_fp_move_double ();
2511 extern char *output_fp_move_quad ();
2512 extern char *output_block_move ();
2513 extern char *output_scc_insn ();
2514 extern char *output_cbranch ();
2515 extern char *output_v9branch ();
2516 extern char *output_return ();
2518 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
2520 extern int flag_pic
;