1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
26 /* Provide required defaults for linker -e and -d switches. */
29 "%{nostdlib:%{!e*:-e start}} -dc -dp %{static:-Bstatic} %{assert*}"
31 /* Special flags to the Sun-4 assembler when using pipe for input. */
33 #define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}"
35 /* Prevent error on `-sun4' and `-target sun4' options. */
36 /* This used to translate -dalign to -malign, but that is no good
37 because it can't turn off the usual meaning of making debugging dumps. */
39 #define CC1_SPEC "%{sun4:} %{target:}"
41 #define PTRDIFF_TYPE "int"
42 #define SIZE_TYPE "int"
43 #define WCHAR_TYPE "short unsigned int"
44 #define WCHAR_TYPE_SIZE 16
46 /* Omit frame pointer at high optimization levels. */
48 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
52 flag_omit_frame_pointer = 1; \
56 /* These compiler options take an argument. We ignore -target for now. */
58 #define WORD_SWITCH_TAKES_ARG(STR) \
59 (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \
60 || !strcmp (STR, "imacros") || !strcmp (STR, "target") \
61 || !strcmp (STR, "assert") || !strcmp (STR, "aux-info"))
63 /* Names to predefine in the preprocessor for this target machine. */
65 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix"
67 /* Print subsidiary information on the compiler version in use. */
69 #define TARGET_VERSION fprintf (stderr, " (sparc)");
71 /* Generate DBX debugging information. */
73 #define DBX_DEBUGGING_INFO
75 /* Run-time compilation parameters selecting different hardware subsets. */
77 extern int target_flags
;
79 /* Nonzero if we should generate code to use the fpu. */
80 #define TARGET_FPU (target_flags & 1)
82 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
83 use fast return insns, but lose some generality. */
84 #define TARGET_EPILOGUE (target_flags & 2)
86 /* Nonzero if we assume that all calls will fall within a 16MB
87 pc-relative range. Useful with -fomit-frame-pointer. */
88 #define TARGET_TAIL_CALL (target_flags & 8)
90 /* Nonzero means that reference doublewords as if they were guaranteed
91 to be aligned...if they aren't, too bad for the user!
92 Like -fast in Sun cc. */
93 #define TARGET_HOPE_ALIGN (target_flags & 16)
95 /* Nonzero means that make sure all doubles are on 8-byte boundaries. */
96 #define TARGET_FORCE_ALIGN (target_flags & 32)
98 /* Macro to define tables used to set the flags.
99 This is a list in braces of pairs in braces,
100 each pair being { "NAME", VALUE }
101 where VALUE is the bits to set or minus the bits to clear.
102 An empty string NAME is used to identify the default VALUE. */
104 #define TARGET_SWITCHES \
106 {"soft-float", -1}, \
108 {"no-epilogue", -2}, \
110 {"hope-align", 16}, \
111 {"force-align", 48}, \
112 { "", TARGET_DEFAULT}}
114 #define TARGET_DEFAULT 3
116 /* target machine storage layout */
118 /* Define this if most significant bit is lowest numbered
119 in instructions that operate on numbered bit-fields. */
120 #define BITS_BIG_ENDIAN 1
122 /* Define this if most significant byte of a word is the lowest numbered. */
123 /* This is true on the SPARC. */
124 #define BYTES_BIG_ENDIAN 1
126 /* Define this if most significant word of a multiword number is the lowest
128 /* Doubles are stored in memory with the high order word first. This
129 matters when cross-compiling. */
130 #define WORDS_BIG_ENDIAN 1
132 /* number of bits in an addressable storage unit */
133 #define BITS_PER_UNIT 8
135 /* Width in bits of a "word", which is the contents of a machine register.
136 Note that this is not necessarily the width of data type `int';
137 if using 16-bit ints on a 68000, this would still be 32.
138 But on a machine with 16-bit registers, this would be 16. */
139 #define BITS_PER_WORD 32
140 #define MAX_BITS_PER_WORD 32
142 /* Width of a word, in units (bytes). */
143 #define UNITS_PER_WORD 4
145 /* Width in bits of a pointer.
146 See also the macro `Pmode' defined below. */
147 #define POINTER_SIZE 32
149 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
150 #define PARM_BOUNDARY 32
152 /* Boundary (in *bits*) on which stack pointer should be aligned. */
153 #define STACK_BOUNDARY 64
155 /* Allocation boundary (in *bits*) for the code of a function. */
156 #define FUNCTION_BOUNDARY 32
158 /* Alignment of field after `int : 0' in a structure. */
159 #define EMPTY_FIELD_BOUNDARY 32
161 /* Every structure's size must be a multiple of this. */
162 #define STRUCTURE_SIZE_BOUNDARY 8
164 /* A bitfield declared as `int' forces `int' alignment for the struct. */
165 #define PCC_BITFIELD_TYPE_MATTERS 1
167 /* No data type wants to be aligned rounder than this. */
168 #define BIGGEST_ALIGNMENT 64
170 /* Make strings word-aligned so strcpy from constants will be faster. */
171 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
172 (TREE_CODE (EXP) == STRING_CST \
173 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
175 /* Make arrays of chars word-aligned for the same reasons. */
176 #define DATA_ALIGNMENT(TYPE, ALIGN) \
177 (TREE_CODE (TYPE) == ARRAY_TYPE \
178 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
179 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
181 /* Set this nonzero if move instructions will actually fail to work
182 when given unaligned data. */
183 #define STRICT_ALIGNMENT 1
185 /* Things that must be doubleword aligned cannot go in the text section,
186 because the linker fails to align the text section enough!
187 Put them in the data section. */
188 #define MAX_TEXT_ALIGN 32
190 #define SELECT_SECTION(T,RELOC) \
192 if (TREE_CODE (T) == VAR_DECL) \
194 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
195 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
196 && ! (flag_pic && (RELOC))) \
201 else if (TREE_CODE (T) == CONSTRUCTOR) \
203 if (flag_pic != 0 && (RELOC) != 0) \
206 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
208 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
209 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
216 /* Use text section for a constant
217 unless we need more alignment than that offers. */
218 #define SELECT_RTX_SECTION(MODE, X) \
220 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
221 && ! (flag_pic && symbolic_operand (X))) \
227 /* Standard register usage. */
229 /* Number of actual hardware registers.
230 The hardware registers are assigned numbers for the compiler
231 from 0 to just below FIRST_PSEUDO_REGISTER.
232 All registers that the compiler knows about must be given numbers,
233 even those that are not normally considered general registers.
235 SPARC has 32 integer registers and 32 floating point registers. */
237 #define FIRST_PSEUDO_REGISTER 64
239 /* 1 for registers that have pervasive standard uses
240 and are not available for the register allocator.
241 0 is used for the condition code and not to represent %g0, which is
242 hardwired to 0, so reg 0 is *not* fixed.
243 2 and 3 are free to use as temporaries.
244 4 through 7 are expected to become usefully defined in the future.
245 Your milage may vary. */
246 #define FIXED_REGISTERS \
247 {0, 0, 0, 0, 1, 1, 1, 1, \
248 0, 0, 0, 0, 0, 0, 1, 0, \
249 0, 0, 0, 0, 0, 0, 0, 0, \
250 0, 0, 0, 0, 0, 0, 1, 1, \
252 0, 0, 0, 0, 0, 0, 0, 0, \
253 0, 0, 0, 0, 0, 0, 0, 0, \
254 0, 0, 0, 0, 0, 0, 0, 0, \
255 0, 0, 0, 0, 0, 0, 0, 0}
257 /* 1 for registers not available across function calls.
258 These must include the FIXED_REGISTERS and also any
259 registers that can be used without being saved.
260 The latter must include the registers where values are returned
261 and the register where structure-value addresses are passed.
262 Aside from that, you can include as many other registers as you like. */
263 #define CALL_USED_REGISTERS \
264 {1, 1, 1, 1, 1, 1, 1, 1, \
265 1, 1, 1, 1, 1, 1, 1, 1, \
266 0, 0, 0, 0, 0, 0, 0, 0, \
267 0, 0, 0, 0, 0, 0, 1, 1, \
269 1, 1, 1, 1, 1, 1, 1, 1, \
270 1, 1, 1, 1, 1, 1, 1, 1, \
271 1, 1, 1, 1, 1, 1, 1, 1, \
272 1, 1, 1, 1, 1, 1, 1, 1}
274 /* Return number of consecutive hard regs needed starting at reg REGNO
275 to hold something of mode MODE.
276 This is ordinarily the length in words of a value of mode MODE
277 but can be less for certain modes in special long registers.
279 On SPARC, ordinary registers hold 32 bits worth;
280 this means both integer and floating point registers.
282 We use vectors to keep this information about registers. */
284 /* How many hard registers it takes to make a register of this mode. */
285 extern int hard_regno_nregs
[];
287 #define HARD_REGNO_NREGS(REGNO, MODE) \
288 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
290 /* Value is 1 if register/mode pair is acceptable on sparc. */
291 extern int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
293 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
294 On SPARC, the cpu registers can hold any mode but the float registers
295 can only hold SFmode or DFmode. See sparc.c for how we
297 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
298 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
300 /* Value is 1 if it is a good idea to tie two pseudo registers
301 when one has mode MODE1 and one has mode MODE2.
302 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
303 for any hard reg, then this must be 0 for correct output. */
304 #define MODES_TIEABLE_P(MODE1, MODE2) \
305 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
307 /* Specify the registers used for certain standard purposes.
308 The values of these macros are register numbers. */
310 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
311 /* #define PC_REGNUM */
313 /* Register to use for pushing function arguments. */
314 #define STACK_POINTER_REGNUM 14
316 /* Actual top-of-stack address is 92 greater than the contents
317 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
318 for the ins and local registers, 4 byte for structure return address, and
319 24 bytes for the 6 register parameters. */
320 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
322 /* Base register for access to local variables of the function. */
323 #define FRAME_POINTER_REGNUM 30
326 /* Register that is used for the return address. */
327 #define RETURN_ADDR_REGNUM 15
330 /* Value should be nonzero if functions must have frame pointers.
331 Zero means the frame pointer need not be set up (and parms
332 may be accessed via the stack pointer) in functions that seem suitable.
333 This is computed in `reload', in reload1.c.
335 Used in flow.c, global-alloc.c, and reload1.c. */
336 extern int leaf_function
;
337 extern int compute_last_arg_offset ();
339 /* Return 0 if span from stack ptr to last stack arg is too far. */
340 #define FRAME_POINTER_REQUIRED \
341 (! (leaf_function_p () && only_leaf_regs_used () \
342 && compute_last_arg_offset () < 4090))
344 /* C statement to store the difference between the frame pointer
345 and the stack pointer values immediately after the function prologue.
347 Note, we always pretend that this is a leaf function because if
348 it's not, there's no point in trying to eliminate the
349 frame pointer. If it is a leaf function, we guessed right! */
350 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
351 do { (VAR) = compute_frame_size (get_frame_size (), 1); } while (0)
353 /* Base register for access to arguments of the function. */
354 #define ARG_POINTER_REGNUM 30
356 /* Register in which static-chain is passed to a function. */
358 #define STATIC_CHAIN_REGNUM 1
360 /* Register which holds offset table for position-independent
363 #define PIC_OFFSET_TABLE_REGNUM 23
365 #define INITIALIZE_PIC initialize_pic ()
366 #define FINALIZE_PIC finalize_pic ()
368 /* Functions which return large structures get the address
369 to place the wanted value at offset 64 from the frame.
370 Must reserve 64 bytes for the in and local registers. */
371 /* Used only in other #defines in this file. */
372 #define STRUCT_VALUE_OFFSET 64
374 #define STRUCT_VALUE \
375 gen_rtx (MEM, Pmode, \
376 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
377 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
378 #define STRUCT_VALUE_INCOMING \
379 gen_rtx (MEM, Pmode, \
380 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
381 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
383 /* Define the classes of registers for register constraints in the
384 machine description. Also define ranges of constants.
386 One of the classes must always be named ALL_REGS and include all hard regs.
387 If there is more than one class, another class must be named NO_REGS
388 and contain no registers.
390 The name GENERAL_REGS must be the name of a class (or an alias for
391 another name such as ALL_REGS). This is the class of registers
392 that is allowed by "g" or "r" in a register constraint.
393 Also, registers outside this class are allocated only when
394 instructions express preferences for them.
396 The classes must be numbered in nondecreasing order; that is,
397 a larger-numbered class must never be contained completely
398 in a smaller-numbered class.
400 For any two classes, it is very desirable that there be another
401 class that represents their union. */
403 /* The SPARC has two kinds of registers, general and floating point. */
405 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
407 #define N_REG_CLASSES (int) LIM_REG_CLASSES
409 /* Give names of register classes as strings for dump file. */
411 #define REG_CLASS_NAMES \
412 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
414 /* Define which registers fit in which classes.
415 This is an initializer for a vector of HARD_REG_SET
416 of length N_REG_CLASSES. */
418 #if 0 && defined (__GNUC__)
419 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
421 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
424 /* The same information, inverted:
425 Return the class number of the smallest class containing
426 reg number REGNO. This could be a conditional expression
427 or could index an array. */
429 #define REGNO_REG_CLASS(REGNO) \
430 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
432 /* This is the order in which to allocate registers
434 #define REG_ALLOC_ORDER \
435 { 8, 9, 10, 11, 12, 13, 2, 3, \
436 15, 16, 17, 18, 19, 20, 21, 22, \
437 23, 24, 25, 26, 27, 28, 29, 31, \
438 32, 33, 34, 35, 36, 37, 38, 39, \
439 40, 41, 42, 43, 44, 45, 46, 47, \
440 48, 49, 50, 51, 52, 53, 54, 55, \
441 56, 57, 58, 59, 60, 61, 62, 63, \
442 1, 4, 5, 6, 7, 0, 14, 30}
444 /* This is the order in which to allocate registers for
445 leaf functions. If all registers can fit in the "i" registers,
446 then we have the possibility of having a leaf function. */
447 #define REG_LEAF_ALLOC_ORDER \
448 { 2, 3, 24, 25, 26, 27, 28, 29, \
449 15, 8, 9, 10, 11, 12, 13, \
450 16, 17, 18, 19, 20, 21, 22, 23, \
451 32, 33, 34, 35, 36, 37, 38, 39, \
452 40, 41, 42, 43, 44, 45, 46, 47, \
453 48, 49, 50, 51, 52, 53, 54, 55, \
454 56, 57, 58, 59, 60, 61, 62, 63, \
455 1, 4, 5, 6, 7, 0, 14, 30, 31}
457 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
459 #define LEAF_REGISTERS \
460 { 1, 1, 1, 1, 1, 1, 1, 1, \
461 0, 0, 0, 0, 0, 0, 1, 0, \
462 0, 0, 0, 0, 0, 0, 0, 0, \
463 1, 1, 1, 1, 1, 1, 0, 1, \
464 1, 1, 1, 1, 1, 1, 1, 1, \
465 1, 1, 1, 1, 1, 1, 1, 1, \
466 1, 1, 1, 1, 1, 1, 1, 1, \
467 1, 1, 1, 1, 1, 1, 1, 1}
469 extern char leaf_reg_remap
[];
470 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
471 extern char leaf_reg_backmap
[];
472 #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
474 #define REG_USED_SO_FAR(REGNO) \
475 ((REGNO) >= 24 && (REGNO) < 30 \
476 ? (regs_ever_live[24] \
477 || regs_ever_live[25] \
478 || regs_ever_live[26] \
479 || regs_ever_live[27] \
480 || regs_ever_live[28] \
481 || regs_ever_live[29]) : 0)
483 /* The class value for index registers, and the one for base regs. */
484 #define INDEX_REG_CLASS GENERAL_REGS
485 #define BASE_REG_CLASS GENERAL_REGS
487 /* Get reg_class from a letter such as appears in the machine description. */
489 #define REG_CLASS_FROM_LETTER(C) \
490 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
492 /* The letters I, J, K, L and M in a register constraint string
493 can be used to stand for particular ranges of immediate operands.
494 This macro defines what the ranges are.
495 C is the letter, and VALUE is a constant value.
496 Return 1 if VALUE is in the range specified by C.
498 For SPARC, `I' is used for the range of constants an insn
499 can actually contain.
500 `J' is used for the range which is just zero (since that is R0).
501 `K' is used for the 5-bit operand of a compare insns. */
503 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
505 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
506 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
507 : (C) == 'J' ? (VALUE) == 0 \
508 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
511 /* Similar, but for floating constants, and defining letters G and H.
512 Here VALUE is the CONST_DOUBLE rtx itself. */
514 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
515 ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
516 && CONST_DOUBLE_LOW (VALUE) == 0 \
517 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
520 /* Given an rtx X being reloaded into a reg required to be
521 in class CLASS, return the class of reg to actually use.
522 In general this is just CLASS; but on some machines
523 in some cases it is preferable to use a more restrictive class. */
524 #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
526 /* Return the register class of a scratch register needed to load IN into
527 a register of class CLASS in MODE.
529 On the SPARC, when PIC, we need a temporary when loading some addresses
532 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
533 (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS : NO_REGS)
535 /* Return the maximum number of consecutive registers
536 needed to represent mode MODE in a register of class CLASS. */
537 /* On SPARC, this is the size of MODE in words. */
538 #define CLASS_MAX_NREGS(CLASS, MODE) \
539 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
541 /* Stack layout; function entry, exit and calling. */
543 /* Define the number of register that can hold parameters.
544 These two macros are used only in other macro definitions below. */
547 /* Define this if pushing a word on the stack
548 makes the stack pointer a smaller address. */
549 #define STACK_GROWS_DOWNWARD
551 /* Define this if the nominal address of the stack frame
552 is at the high-address end of the local variables;
553 that is, each additional local variable allocated
554 goes at a more negative offset in the frame. */
555 #define FRAME_GROWS_DOWNWARD
557 /* Offset within stack frame to start allocating local variables at.
558 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
559 first local allocated. Otherwise, it is the offset to the BEGINNING
560 of the first local allocated. */
561 #define STARTING_FRAME_OFFSET (-16)
563 /* If we generate an insn to push BYTES bytes,
564 this says how many the stack pointer really advances by.
565 On SPARC, don't define this because there are no push insns. */
566 /* #define PUSH_ROUNDING(BYTES) */
568 /* Offset of first parameter from the argument pointer register value.
569 This is 64 for the ins and locals, plus 4 for the struct-return reg
570 even if this function isn't going to use it. */
571 #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
573 /* Offset from top-of-stack address to location to store the
574 function parameter if it can't go in a register.
575 Addresses for following parameters are computed relative to this one. */
576 #define FIRST_PARM_CALLER_OFFSET(FNDECL) \
577 (STRUCT_VALUE_OFFSET + UNITS_PER_WORD - STACK_POINTER_OFFSET)
579 /* When a parameter is passed in a register, stack space is still
581 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
583 /* Keep the stack pointer constant throughout the function.
584 This is both an optimization and a necessity: longjmp
585 doesn't behave itself when the stack pointer moves within
587 #define ACCUMULATE_OUTGOING_ARGS
589 /* Value is the number of bytes of arguments automatically
590 popped when returning from a subroutine call.
591 FUNTYPE is the data type of the function (as a tree),
592 or for a library call it is an identifier node for the subroutine name.
593 SIZE is the number of bytes of arguments passed on the stack. */
595 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
597 /* Some subroutine macros specific to this machine. */
598 #define BASE_RETURN_VALUE_REG(MODE) \
599 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8)
600 #define BASE_OUTGOING_VALUE_REG(MODE) \
601 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24)
602 #define BASE_PASSING_ARG_REG(MODE) (8)
603 #define BASE_INCOMING_ARG_REG(MODE) (24)
605 /* Define how to find the value returned by a function.
606 VALTYPE is the data type of the value (as a tree).
607 If the precise function being called is known, FUNC is its FUNCTION_DECL;
608 otherwise, FUNC is 0. */
610 /* On SPARC the value is found in the first "output" register. */
612 #define FUNCTION_VALUE(VALTYPE, FUNC) \
613 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
615 /* But the called function leaves it in the first "input" register. */
617 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
618 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
620 /* Define how to find the value returned by a library function
621 assuming the value has mode MODE. */
623 #define LIBCALL_VALUE(MODE) \
624 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
626 /* 1 if N is a possible register number for a function value
627 as seen by the caller.
628 On SPARC, the first "output" reg is used for integer values,
629 and the first floating point register is used for floating point values. */
631 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
633 /* 1 if N is a possible register number for function argument passing.
634 On SPARC, these are the "output" registers. */
636 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
638 /* Define a data type for recording info about an argument list
639 during the scan of that argument list. This data type should
640 hold all necessary information about the function itself
641 and about the args processed so far, enough to enable macros
642 such as FUNCTION_ARG to determine where the next arg should go.
644 On SPARC, this is a single integer, which is a number of words
645 of arguments scanned so far (including the invisible argument,
646 if any, which holds the structure-value-address).
647 Thus 7 or more means all following args should go on the stack. */
649 #define CUMULATIVE_ARGS int
651 #define ROUND_ADVANCE(SIZE) \
652 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
654 /* Round a register number up to a proper boundary for an arg of mode MODE.
655 Note that we need an odd/even pair for a two-word arg,
656 since that will become 8-byte aligned when stored in memory. */
657 #define ROUND_REG(X, MODE) \
658 (TARGET_FORCE_ALIGN && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
659 ? ((X) + ! ((X) & 1)) : (X))
661 /* Initialize a variable CUM of type CUMULATIVE_ARGS
662 for a call to a function whose data type is FNTYPE.
663 For a library call, FNTYPE is 0.
665 On SPARC, the offset always starts at 0: the first parm reg is always
668 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
670 /* Update the data in CUM to advance over an argument
671 of mode MODE and data type TYPE.
672 (TYPE is null for libcalls where that information may not be available.) */
674 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
675 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
676 + ((MODE) != BLKmode \
677 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
678 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
680 /* Determine where to put an argument to a function.
681 Value is zero to push the argument on the stack,
682 or a hard register in which to store the argument.
684 MODE is the argument's machine mode.
685 TYPE is the data type of the argument (as a tree).
686 This is null for libcalls where that information may
688 CUM is a variable of type CUMULATIVE_ARGS which gives info about
689 the preceding args and about the function being called.
690 NAMED is nonzero if this argument is a named parameter
691 (otherwise it is an extra parameter matching an ellipsis). */
693 /* On SPARC the first six args are normally in registers
694 and the rest are pushed. Any arg that starts within the first 6 words
695 is at least partially passed in a register unless its data type forbids. */
697 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
698 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
699 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
700 && ((TYPE)==0 || (MODE) != BLKmode \
701 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
702 ? gen_rtx (REG, (MODE), \
703 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
706 /* Define where a function finds its arguments.
707 This is different from FUNCTION_ARG because of register windows. */
709 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
710 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
711 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
712 && ((TYPE)==0 || (MODE) != BLKmode \
713 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
714 ? gen_rtx (REG, (MODE), \
715 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
718 /* For an arg passed partly in registers and partly in memory,
719 this is the number of registers used.
720 For args passed entirely in registers or entirely in memory, zero.
721 Any arg that starts in the first 6 regs but won't entirely fit in them
722 needs partial registers on the Sparc. */
724 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
725 ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
726 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
727 && ((TYPE)==0 || (MODE) != BLKmode \
728 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
729 && (ROUND_REG ((CUM), (MODE)) \
730 + ((MODE) == BLKmode \
731 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
732 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
733 ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
736 /* The SPARC ABI stipulates passing struct arguments (of any size)
737 by invisible reference. */
738 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
739 (TYPE && (TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE (TYPE) == UNION_TYPE))
741 /* If defined, a C expression that gives the alignment boundary, in
742 bits, of an argument with the specified mode and type. If it is
743 not defined, `PARM_BOUNDARY' is used for all arguments.
745 This definition does nothing special unless TARGET_FORCE_ALIGN;
746 in that case, it aligns each arg to the natural boundary. */
748 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
749 (! TARGET_FORCE_ALIGN \
752 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
754 : TYPE_ALIGN (TYPE)) \
755 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
757 : GET_MODE_ALIGNMENT (MODE))))
759 /* Define the information needed to generate branch and scc insns. This is
760 stored from the compare operation. Note that we can't use "rtx" here
761 since it hasn't been defined! */
763 extern struct rtx_def
*sparc_compare_op0
, *sparc_compare_op1
;
765 /* Define the function that build the compare insn for scc and bcc. */
767 extern struct rtx_def
*gen_compare_reg ();
769 /* Generate the special assembly code needed to tell the assembler whatever
770 it might need to know about the return value of a function.
772 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
773 information to the assembler relating to peephole optimization (done in
776 #define ASM_DECLARE_RESULT(FILE, RESULT) \
777 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
779 /* Output the label for a function definition. */
781 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
783 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
784 ASM_OUTPUT_LABEL (FILE, NAME); \
787 /* Two views of the size of the current frame. */
788 extern int actual_fsize
;
789 extern int apparent_fsize
;
791 /* This macro generates the assembly code for function entry.
792 FILE is a stdio stream to output the code to.
793 SIZE is an int: how many units of temporary storage to allocate.
794 Refer to the array `regs_ever_live' to determine which registers
795 to save; `regs_ever_live[I]' is nonzero if register number I
796 is ever used in the function. This macro is responsible for
797 knowing which registers should not be saved even if used. */
799 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
800 of memory. If any fpu reg is used in the function, we allocate
801 such a block here, at the bottom of the frame, just in case it's needed.
803 If this function is a leaf procedure, then we may choose not
804 to do a "save" insn. The decision about whether or not
805 to do this is made in regclass.c. */
807 #define FUNCTION_PROLOGUE(FILE, SIZE) \
808 output_function_prologue (FILE, SIZE, leaf_function)
810 /* Output assembler code to FILE to increment profiler label # LABELNO
811 for profiling a function entry. */
813 #define FUNCTION_PROFILER(FILE, LABELNO) \
814 fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
815 (LABELNO), (LABELNO))
817 /* Output assembler code to FILE to initialize this source file's
818 basic block profiling info, if that has not already been done. */
820 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
821 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
822 (LABELNO), (LABELNO))
824 /* Output assembler code to FILE to increment the entry-count for
825 the BLOCKNO'th basic block in this source file. */
827 #define BLOCK_PROFILER(FILE, BLOCKNO) \
829 int blockn = (BLOCKNO); \
830 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
831 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
832 4 * blockn, 4 * blockn, 4 * blockn); \
835 /* Output rtl to increment the entry-count for the LABELNO'th instrumented
836 arc in this source file. */
838 #define ARC_PROFILER(ARCNO, INSERT_AFTER) \
839 output_arc_profiler (ARCNO, INSERT_AFTER)
841 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
842 the stack pointer does not matter. The value is tested only in
843 functions that have frame pointers.
844 No definition is equivalent to always zero. */
846 extern int current_function_calls_alloca
;
847 extern int current_function_outgoing_args_size
;
849 #define EXIT_IGNORE_STACK \
850 (get_frame_size () != 0 \
851 || current_function_calls_alloca || current_function_outgoing_args_size)
853 /* This macro generates the assembly code for function exit,
854 on machines that need it. If FUNCTION_EPILOGUE is not defined
855 then individual return instructions are generated for each
856 return statement. Args are same as for FUNCTION_PROLOGUE.
858 The function epilogue should not depend on the current stack pointer!
859 It should use the frame pointer only. This is mandatory because
860 of alloca; we also take advantage of it to omit stack adjustments
863 /* This declaration is needed due to traditional/ANSI
864 incompatibilities which cannot be #ifdefed away
865 because they occur inside of macros. Sigh. */
866 extern union tree_node
*current_function_decl
;
868 #define FUNCTION_EPILOGUE(FILE, SIZE) \
869 output_function_epilogue (FILE, SIZE, leaf_function, 1)
871 #define DELAY_SLOTS_FOR_EPILOGUE 1
872 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
873 eligible_for_epilogue_delay (trial, slots_filled)
875 /* Output assembler code for a block containing the constant parts
876 of a trampoline, leaving space for the variable parts. */
878 /* On the sparc, the trampoline contains five instructions:
879 sethi #TOP_OF_FUNCTION,%g2
880 or #BOTTOM_OF_FUNCTION,%g2,%g2
881 sethi #TOP_OF_STATIC,%g1
883 or #BOTTOM_OF_STATIC,%g1,%g1 */
884 #define TRAMPOLINE_TEMPLATE(FILE) \
886 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
887 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
888 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
889 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
890 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
893 /* Length in units of the trampoline for entering a nested function. */
895 #define TRAMPOLINE_SIZE 20
897 /* Emit RTL insns to initialize the variable parts of a trampoline.
898 FNADDR is an RTX for the address of the function's pure code.
899 CXT is an RTX for the static chain value for the function.
901 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
902 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
903 (to store insns). This is a bit excessive. Perhaps a different
904 mechanism would be better here. */
906 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
908 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
909 size_int (10), 0, 1); \
910 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
911 size_int (10), 0, 1); \
912 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
913 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
914 rtx g1_sethi = gen_rtx (HIGH, SImode, \
915 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
916 rtx g2_sethi = gen_rtx (HIGH, SImode, \
917 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
918 rtx g1_ori = gen_rtx (HIGH, SImode, \
919 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
920 rtx g2_ori = gen_rtx (HIGH, SImode, \
921 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
922 rtx tem = gen_reg_rtx (SImode); \
923 emit_move_insn (tem, g2_sethi); \
924 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
925 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
926 emit_move_insn (tem, g2_ori); \
927 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
928 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
929 emit_move_insn (tem, g1_sethi); \
930 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
931 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
932 emit_move_insn (tem, g1_ori); \
933 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
934 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
937 /* Emit code for a call to builtin_saveregs. We must emit USE insns which
938 reference the 6 input registers. Ordinarily they are not call used
939 registers, but they are for _builtin_saveregs, so we must make this
942 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) \
943 (emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, TImode, 24))), \
944 emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, DImode, 28))), \
945 expand_call (exp, target, ignore))
947 /* Addressing modes, and classification of registers for them. */
949 /* #define HAVE_POST_INCREMENT */
950 /* #define HAVE_POST_DECREMENT */
952 /* #define HAVE_PRE_DECREMENT */
953 /* #define HAVE_PRE_INCREMENT */
955 /* Macros to check register numbers against specific register classes. */
957 /* These assume that REGNO is a hard or pseudo reg number.
958 They give nonzero only if REGNO is a hard reg of the suitable class
959 or a pseudo reg currently allocated to a suitable hard reg.
960 Since they use reg_renumber, they are safe only once reg_renumber
961 has been allocated, which happens in local-alloc.c. */
963 #define REGNO_OK_FOR_INDEX_P(REGNO) \
964 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
965 #define REGNO_OK_FOR_BASE_P(REGNO) \
966 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
967 #define REGNO_OK_FOR_FP_P(REGNO) \
968 (((REGNO) ^ 0x20) < 32 \
969 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
971 /* Now macros that check whether X is a register and also,
972 strictly, whether it is in a specified class.
974 These macros are specific to the SPARC, and may be used only
975 in code for printing assembler insns and in conditions for
976 define_optimization. */
978 /* 1 if X is an fp register. */
980 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
982 /* Maximum number of registers that can appear in a valid memory address. */
984 #define MAX_REGS_PER_ADDRESS 2
986 /* Recognize any constant value that is a valid address. */
988 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
990 /* Nonzero if the constant value X is a legitimate general operand.
991 Anything can be made to work except floating point constants. */
993 #define LEGITIMATE_CONSTANT_P(X) \
994 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
996 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
997 and check its validity for a certain class.
998 We have two alternate definitions for each of them.
999 The usual definition accepts all pseudo regs; the other rejects
1000 them unless they have been allocated suitable hard regs.
1001 The symbol REG_OK_STRICT causes the latter definition to be used.
1003 Most source files want to accept pseudo regs in the hope that
1004 they will get allocated to the class that the insn wants them to be in.
1005 Source files for reload pass need to be strict.
1006 After reload, it makes no difference, since pseudo regs have
1007 been eliminated by then. */
1009 /* Optional extra constraints for this machine. Borrowed from romp.h.
1011 For the SPARC, `Q' means that this is a memory operand but not a
1012 symbolic memory operand. Note that an unassigned pseudo register
1013 is such a memory operand. Needed because reload will generate
1014 these things in insns and then not re-recognize the insns, causing
1015 constrain_operands to fail.
1017 `R' handles the LO_SUM which can be an address for `Q'.
1019 `S' handles constraints for calls. */
1021 #ifndef REG_OK_STRICT
1023 /* Nonzero if X is a hard reg that can be used as an index
1024 or if it is a pseudo reg. */
1025 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1026 /* Nonzero if X is a hard reg that can be used as a base reg
1027 or if it is a pseudo reg. */
1028 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1030 #define EXTRA_CONSTRAINT(OP, C) \
1032 ((GET_CODE (OP) == MEM \
1033 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1034 && ! symbolic_memory_operand (OP, VOIDmode))) \
1036 (GET_CODE (OP) == LO_SUM \
1037 && GET_CODE (XEXP (OP, 0)) == REG \
1038 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1040 ? CONSTANT_P (OP) || memory_address_p (Pmode, OP) : 0)))
1044 /* Nonzero if X is a hard reg that can be used as an index. */
1045 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1046 /* Nonzero if X is a hard reg that can be used as a base reg. */
1047 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1049 #define EXTRA_CONSTRAINT(OP, C) \
1051 (GET_CODE (OP) == REG ? \
1052 (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1053 && reg_renumber[REGNO (OP)] < 0) \
1054 : GET_CODE (OP) == MEM) \
1056 (GET_CODE (OP) == LO_SUM \
1057 && GET_CODE (XEXP (OP, 0)) == REG \
1058 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1060 ? (CONSTANT_P (OP) \
1061 || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\
1062 || strict_memory_address_p (Pmode, OP)) : 0)))
1065 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1066 that is a valid memory address for an instruction.
1067 The MODE argument is the machine mode for the MEM expression
1068 that wants to use this address.
1070 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1071 ordinarily. This changes a bit when generating PIC.
1073 If you change this, execute "rm explow.o recog.o reload.o". */
1075 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1076 { if (GET_CODE (X) == REG) \
1077 { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \
1078 else if (GET_CODE (X) == PLUS) \
1080 if (flag_pic && XEXP (X, 0) == pic_offset_table_rtx)\
1082 if (GET_CODE (XEXP (X, 1)) == REG \
1083 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1085 else if (flag_pic == 1 \
1086 && GET_CODE (XEXP (X, 1)) != REG \
1087 && GET_CODE (XEXP (X, 1)) != LO_SUM \
1088 && GET_CODE (XEXP (X, 1)) != MEM) \
1091 else if (GET_CODE (XEXP (X, 0)) == REG \
1092 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1094 if (GET_CODE (XEXP (X, 1)) == REG \
1095 && REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
1097 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1098 && INTVAL (XEXP (X, 1)) >= -0x1000 \
1099 && INTVAL (XEXP (X, 1)) < 0x1000) \
1102 else if (GET_CODE (XEXP (X, 1)) == REG \
1103 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1105 if (GET_CODE (XEXP (X, 0)) == REG \
1106 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1108 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1109 && INTVAL (XEXP (X, 0)) >= -0x1000 \
1110 && INTVAL (XEXP (X, 0)) < 0x1000) \
1114 else if (GET_CODE (X) == LO_SUM \
1115 && GET_CODE (XEXP (X, 0)) == REG \
1116 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1117 && CONSTANT_P (XEXP (X, 1))) \
1119 else if (GET_CODE (X) == LO_SUM \
1120 && GET_CODE (XEXP (X, 0)) == SUBREG \
1121 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG\
1122 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0)))\
1123 && CONSTANT_P (XEXP (X, 1))) \
1125 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1129 /* Try machine-dependent ways of modifying an illegitimate address
1130 to be legitimate. If we find one, return the new, valid address.
1131 This macro is used in only one place: `memory_address' in explow.c.
1133 OLDX is the address as it was before break_out_memory_refs was called.
1134 In some cases it is useful to look at this to decide what needs to be done.
1136 MODE and WIN are passed so that this macro can use
1137 GO_IF_LEGITIMATE_ADDRESS.
1139 It is always safe for this macro to do nothing. It exists to recognize
1140 opportunities to optimize the output. */
1142 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1143 extern struct rtx_def
*legitimize_pic_address ();
1144 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1145 { rtx sparc_x = (X); \
1146 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1147 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1148 force_operand (XEXP (X, 0), 0)); \
1149 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1150 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1151 force_operand (XEXP (X, 1), 0)); \
1152 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1153 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), 0),\
1155 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1156 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1157 force_operand (XEXP (X, 1), 0)); \
1158 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1160 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1161 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1162 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1163 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1164 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1165 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1166 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1167 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1168 || GET_CODE (X) == LABEL_REF) \
1169 (X) = gen_rtx (LO_SUM, Pmode, \
1170 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1171 if (memory_address_p (MODE, X)) \
1174 /* Go to LABEL if ADDR (a legitimate address expression)
1175 has an effect that depends on the machine mode it is used for.
1176 On the SPARC this is never true. */
1178 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1180 /* Specify the machine mode that this machine uses
1181 for the index in the tablejump instruction. */
1182 #define CASE_VECTOR_MODE SImode
1184 /* Define this if the tablejump instruction expects the table
1185 to contain offsets from the address of the table.
1186 Do not define this if the table should contain absolute addresses. */
1187 /* #define CASE_VECTOR_PC_RELATIVE */
1189 /* Specify the tree operation to be used to convert reals to integers. */
1190 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1192 /* This is the kind of divide that is easiest to do in the general case. */
1193 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1195 /* Define this as 1 if `char' should by default be signed; else as 0. */
1196 #define DEFAULT_SIGNED_CHAR 1
1198 /* Max number of bytes we can move from memory to memory
1199 in one reasonably fast instruction. */
1202 /* Define if normal loads of shorter-than-word items from memory clears
1203 the rest of the bigs in the register. */
1204 #define BYTE_LOADS_ZERO_EXTEND
1206 /* Nonzero if access to memory by bytes is slow and undesirable.
1207 For RISC chips, it means that access to memory by bytes is no
1208 better than access by words when possible, so grab a whole word
1209 and maybe make use of that. */
1210 #define SLOW_BYTE_ACCESS 1
1212 /* We assume that the store-condition-codes instructions store 0 for false
1213 and some other value for true. This is the value stored for true. */
1215 #define STORE_FLAG_VALUE 1
1217 /* When a prototype says `char' or `short', really pass an `int'. */
1218 #define PROMOTE_PROTOTYPES
1220 /* Define if shifts truncate the shift count
1221 which implies one can omit a sign-extension or zero-extension
1222 of a shift count. */
1223 #define SHIFT_COUNT_TRUNCATED
1225 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1226 is done just by pretending it is already truncated. */
1227 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1229 /* Specify the machine mode that pointers have.
1230 After generation of rtl, the compiler makes no further distinction
1231 between pointers and any other objects of this machine mode. */
1232 #define Pmode SImode
1234 /* Generate calls to memcpy, memcmp and memset. */
1235 #define TARGET_MEM_FUNCTIONS
1237 /* Add any extra modes needed to represent the condition code.
1239 On the Sparc, we have a "no-overflow" mode which is used when an add or
1240 subtract insn is used to set the condition code. Different branches are
1241 used in this case for some operations.
1243 We also have a mode to indicate that the relevant condition code is
1244 in the floating-point condition code. This really should be a separate
1245 register, but we don't want to go to 65 registers. */
1246 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode
1248 /* Define the names for the modes specified above. */
1249 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP"
1251 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1252 return the mode to be used for the comparison. For floating-point, CCFPmode
1253 should be used. CC_NOOVmode should be used when the first operand is a
1254 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1256 #define SELECT_CC_MODE(OP,X) \
1257 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
1258 : (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1259 ? CC_NOOVmode : CCmode)
1261 /* A function address in a call instruction
1262 is a byte address (for indexing purposes)
1263 so give the MEM rtx a byte's mode. */
1264 #define FUNCTION_MODE SImode
1266 /* Define this if addresses of constant functions
1267 shouldn't be put through pseudo regs where they can be cse'd.
1268 Desirable on machines where ordinary constants are expensive
1269 but a CALL with constant address is cheap. */
1270 #define NO_FUNCTION_CSE
1272 /* alloca should avoid clobbering the old register save area. */
1273 #define SETJMP_VIA_SAVE_AREA
1275 /* Define subroutines to call to handle multiply and divide.
1276 Use the subroutines that Sun's library provides.
1277 The `*' prevents an underscore from being prepended by the compiler. */
1279 #define DIVSI3_LIBCALL "*.div"
1280 #define UDIVSI3_LIBCALL "*.udiv"
1281 #define MODSI3_LIBCALL "*.rem"
1282 #define UMODSI3_LIBCALL "*.urem"
1283 /* .umul is a little faster than .mul. */
1284 #define MULSI3_LIBCALL "*.umul"
1286 /* Compute the cost of computing a constant rtl expression RTX
1287 whose rtx-code is CODE. The body of this macro is a portion
1288 of a switch statement. If the code is computed here,
1289 return it with a return statement. Otherwise, break from the switch. */
1291 #define CONST_COSTS(RTX,CODE) \
1293 if (INTVAL (RTX) == 0) \
1295 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1303 case CONST_DOUBLE: \
1304 if (GET_MODE (RTX) == DImode) \
1305 if ((XINT (RTX, 3) == 0 \
1306 && (unsigned) XINT (RTX, 2) < 0x1000) \
1307 || (XINT (RTX, 3) == -1 \
1308 && XINT (RTX, 2) < 0 \
1309 && XINT (RTX, 2) >= -0x1000)) \
1313 /* SPARC offers addressing modes which are "as cheap as a register".
1314 See sparc.c (or gcc.texinfo) for details. */
1316 #define ADDRESS_COST(RTX) \
1317 (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1319 /* Compute extra cost of moving data between one register class
1321 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1322 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1323 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1325 /* Provide the costs of a rtl expression. This is in the body of a
1326 switch on CODE. The purpose for the cost of MULT is to encourage
1327 `synth_mult' to find a synthetic multiply when reasonable.
1329 If we need more than 12 insns to do a multiply, then go out-of-line,
1330 since the call overhead will be < 10% of the cost of the multiply. */
1332 #define RTX_COSTS(X,CODE) \
1334 return COSTS_N_INSNS (25); \
1339 return COSTS_N_INSNS (20); \
1340 /* Make FLOAT more expensive than CONST_DOUBLE, \
1341 so that cse will favor the latter. */ \
1345 /* Conditional branches with empty delay slots have a length of two. */
1346 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1347 if (GET_CODE (INSN) == CALL_INSN \
1348 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1351 /* Control the assembler format that we output. */
1353 /* Output at beginning of assembler file. */
1355 #define ASM_FILE_START(file)
1357 /* Output to assembler file text saying following lines
1358 may contain character constants, extra white space, comments, etc. */
1360 #define ASM_APP_ON ""
1362 /* Output to assembler file text saying following lines
1363 no longer contain unusual constructs. */
1365 #define ASM_APP_OFF ""
1367 /* Output before read-only data. */
1369 #define TEXT_SECTION_ASM_OP ".text"
1371 /* Output before writable data. */
1373 #define DATA_SECTION_ASM_OP ".data"
1375 /* How to refer to registers in assembler output.
1376 This sequence is indexed by compiler's hard-register-number (see above). */
1378 #define REGISTER_NAMES \
1379 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1380 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1381 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1382 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1383 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1384 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1385 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1386 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1388 /* How to renumber registers for dbx and gdb. */
1390 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1392 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1393 since the length can run past this up to a continuation point. */
1394 #define DBX_CONTIN_LENGTH 1500
1396 /* This is how to output a note to DBX telling it the line number
1397 to which the following sequence of instructions corresponds.
1399 This is needed for SunOS 4.0, and should not hurt for 3.2
1401 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1402 { static int sym_lineno = 1; \
1403 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1404 line, sym_lineno, sym_lineno); \
1407 /* This is how to output the definition of a user-level label named NAME,
1408 such as the label on a static function or variable NAME. */
1410 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1411 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1413 /* This is how to output a command to make the user-level label named NAME
1414 defined for reference from other files. */
1416 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1417 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1419 /* This is how to output a reference to a user-level label named NAME.
1420 `assemble_name' uses this. */
1422 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1423 fprintf (FILE, "_%s", NAME)
1425 /* This is how to output an internal numbered label where
1426 PREFIX is the class of label and NUM is the number within the class. */
1428 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1429 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1431 /* This is how to store into the string LABEL
1432 the symbol_ref name of an internal numbered label where
1433 PREFIX is the class of label and NUM is the number within the class.
1434 This is suitable for output with `assemble_name'. */
1436 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1437 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1439 /* This is how to output an assembler line defining a `double' constant. */
1441 /* Assemblers (both gas 1.35 and as in 4.0.3)
1442 seem to treat -0.0 as if it were 0.0.
1443 They reject 99e9999, but accept inf. */
1444 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1446 if (REAL_VALUE_ISINF (VALUE)) \
1447 fprintf (FILE, "\t.double 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1448 else if (REAL_VALUE_ISNAN (VALUE) \
1449 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1451 union { double d; long l[2];} t; \
1453 fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t.l[0], t.l[1]); \
1456 fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1459 /* This is how to output an assembler line defining a `float' constant. */
1461 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1463 if (REAL_VALUE_ISINF (VALUE)) \
1464 fprintf (FILE, "\t.single 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1465 else if (REAL_VALUE_ISNAN (VALUE) \
1466 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1468 union { float f; long l;} t; \
1470 fprintf (FILE, "\t.word 0x%lx\n", t.l); \
1473 fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1476 /* This is how to output an assembler line defining an `int' constant. */
1478 #define ASM_OUTPUT_INT(FILE,VALUE) \
1479 ( fprintf (FILE, "\t.word "), \
1480 output_addr_const (FILE, (VALUE)), \
1481 fprintf (FILE, "\n"))
1483 /* This is how to output an assembler line defining a DImode constant. */
1484 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1485 output_double_int (FILE, VALUE)
1487 /* Likewise for `char' and `short' constants. */
1489 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1490 ( fprintf (FILE, "\t.half "), \
1491 output_addr_const (FILE, (VALUE)), \
1492 fprintf (FILE, "\n"))
1494 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1495 ( fprintf (FILE, "\t.byte "), \
1496 output_addr_const (FILE, (VALUE)), \
1497 fprintf (FILE, "\n"))
1499 /* This is how to output an assembler line for a numeric constant byte. */
1501 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1502 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1504 /* This is how to output an element of a case-vector that is absolute. */
1506 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1509 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1510 fprintf (FILE, "\t.word\t"); \
1511 assemble_name (FILE, label); \
1512 fprintf (FILE, "\n"); \
1515 /* This is how to output an element of a case-vector that is relative.
1516 (SPARC uses such vectors only when generating PIC.) */
1518 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1521 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1522 fprintf (FILE, "\t.word\t"); \
1523 assemble_name (FILE, label); \
1524 fprintf (FILE, "-1b\n"); \
1527 /* This is how to output an assembler line
1528 that says to advance the location counter
1529 to a multiple of 2**LOG bytes. */
1531 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1533 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1535 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1536 fprintf (FILE, "\t.skip %u\n", (SIZE))
1538 /* This says how to output an assembler line
1539 to define a global common symbol. */
1541 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1542 ( fputs ("\t.global ", (FILE)), \
1543 assemble_name ((FILE), (NAME)), \
1544 fputs ("\n\t.common ", (FILE)), \
1545 assemble_name ((FILE), (NAME)), \
1546 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1548 /* This says how to output an assembler line
1549 to define a local common symbol. */
1551 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1552 ( fputs ("\n\t.reserve ", (FILE)), \
1553 assemble_name ((FILE), (NAME)), \
1554 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1556 /* Store in OUTPUT a string (made with alloca) containing
1557 an assembler-name for a local static variable named NAME.
1558 LABELNO is an integer which is different for each call. */
1560 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1561 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1562 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1564 /* Define the parentheses used to group arithmetic operations
1565 in assembler code. */
1567 #define ASM_OPEN_PAREN "("
1568 #define ASM_CLOSE_PAREN ")"
1570 /* Define results of standard character escape sequences. */
1571 #define TARGET_BELL 007
1572 #define TARGET_BS 010
1573 #define TARGET_TAB 011
1574 #define TARGET_NEWLINE 012
1575 #define TARGET_VT 013
1576 #define TARGET_FF 014
1577 #define TARGET_CR 015
1579 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1580 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1582 /* Print operand X (an rtx) in assembler syntax to file FILE.
1583 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1584 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1586 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1588 /* Print a memory address as an operand to reference that memory location. */
1590 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1591 { register rtx base, index = 0; \
1593 register rtx addr = ADDR; \
1594 if (GET_CODE (addr) == REG) \
1595 fputs (reg_names[REGNO (addr)], FILE); \
1596 else if (GET_CODE (addr) == PLUS) \
1598 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1599 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1600 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1601 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1603 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1604 fputs (reg_names[REGNO (base)], FILE); \
1606 fprintf (FILE, "%+d", offset); \
1607 else if (GET_CODE (index) == REG) \
1608 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1609 else if (GET_CODE (index) == SYMBOL_REF) \
1610 fputc ('+', FILE), output_addr_const (FILE, index); \
1613 else if (GET_CODE (addr) == MINUS \
1614 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1616 output_addr_const (FILE, XEXP (addr, 0)); \
1617 fputs ("-(", FILE); \
1618 output_addr_const (FILE, XEXP (addr, 1)); \
1619 fputs ("-.)", FILE); \
1621 else if (GET_CODE (addr) == LO_SUM) \
1623 output_operand (XEXP (addr, 0), 0); \
1624 fputs ("+%lo(", FILE); \
1625 output_address (XEXP (addr, 1)); \
1626 fputc (')', FILE); \
1628 else if (flag_pic && GET_CODE (addr) == CONST \
1629 && GET_CODE (XEXP (addr, 0)) == MINUS \
1630 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1631 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1632 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1634 addr = XEXP (addr, 0); \
1635 output_addr_const (FILE, XEXP (addr, 0)); \
1636 /* Group the args of the second CONST in parenthesis. */ \
1637 fputs ("-(", FILE); \
1638 /* Skip past the second CONST--it does nothing for us. */\
1639 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1640 /* Close the parenthesis. */ \
1641 fputc (')', FILE); \
1645 output_addr_const (FILE, addr); \
1649 /* Declare functions defined in sparc.c and used in templates. */
1651 extern char *singlemove_string ();
1652 extern char *output_move_double ();
1653 extern char *output_fp_move_double ();
1654 extern char *output_block_move ();
1655 extern char *output_scc_insn ();
1656 extern char *output_cbranch ();
1657 extern char *output_return ();
1658 extern char *output_floatsisf2 ();
1659 extern char *output_floatsidf2 ();
1661 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1663 extern int flag_pic
;