1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
26 /* Provide required defaults for linker -e and -d switches. */
29 "%{!nostdlib:%{!e*:-e start}} -dc -dp %{static:-Bstatic} %{assert*}"
31 /* Special flags to the Sun-4 assembler when using pipe for input. */
33 #define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}"
35 /* Prevent error on `-sun4' and `-target sun4' options. */
36 /* This used to translate -dalign to -malign, but that is no good
37 because it can't turn off the usual meaning of making debugging dumps. */
39 #define CC1_SPEC "%{sun4:} %{target:}"
42 /* Sparc ABI says that long double is 4 words.
43 ??? This doesn't work yet. */
44 #define LONG_DOUBLE_TYPE_SIZE 128
47 #define PTRDIFF_TYPE "int"
48 #define SIZE_TYPE "int"
49 #define WCHAR_TYPE "short unsigned int"
50 #define WCHAR_TYPE_SIZE 16
52 /* Omit frame pointer at high optimization levels. */
54 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
58 flag_omit_frame_pointer = 1; \
62 /* These compiler options take an argument. We ignore -target for now. */
64 #define WORD_SWITCH_TAKES_ARG(STR) \
65 (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \
66 || !strcmp (STR, "imacros") || !strcmp (STR, "target") \
67 || !strcmp (STR, "assert") || !strcmp (STR, "aux-info"))
69 /* Names to predefine in the preprocessor for this target machine. */
71 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix"
73 /* Print subsidiary information on the compiler version in use. */
75 #define TARGET_VERSION fprintf (stderr, " (sparc)");
77 /* Generate DBX debugging information. */
79 #define DBX_DEBUGGING_INFO
81 /* Run-time compilation parameters selecting different hardware subsets. */
83 extern int target_flags
;
85 /* Nonzero if we should generate code to use the fpu. */
86 #define TARGET_FPU (target_flags & 1)
88 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
89 use fast return insns, but lose some generality. */
90 #define TARGET_EPILOGUE (target_flags & 2)
92 /* Nonzero means that reference doublewords as if they were guaranteed
93 to be aligned...if they aren't, too bad for the user!
94 Like -dalign in Sun cc. */
95 #define TARGET_HOPE_ALIGN (target_flags & 16)
97 /* Nonzero means make sure all doubles are on 8-byte boundaries.
98 This option results in a calling convention that is incompatible with
99 every other sparc compiler in the world, and thus should only ever be
100 used for experimenting. Also, varargs won't work with it, but it doesn't
101 seem worth trying to fix. */
102 #define TARGET_FORCE_ALIGN (target_flags & 32)
104 /* Macro to define tables used to set the flags.
105 This is a list in braces of pairs in braces,
106 each pair being { "NAME", VALUE }
107 where VALUE is the bits to set or minus the bits to clear.
108 An empty string NAME is used to identify the default VALUE. */
110 #define TARGET_SWITCHES \
112 {"soft-float", -1}, \
114 {"no-epilogue", -2}, \
115 {"hope-align", 16}, \
116 {"force-align", 48}, \
117 { "", TARGET_DEFAULT}}
119 #define TARGET_DEFAULT 3
121 /* target machine storage layout */
123 /* Define this if most significant bit is lowest numbered
124 in instructions that operate on numbered bit-fields. */
125 #define BITS_BIG_ENDIAN 1
127 /* Define this if most significant byte of a word is the lowest numbered. */
128 /* This is true on the SPARC. */
129 #define BYTES_BIG_ENDIAN 1
131 /* Define this if most significant word of a multiword number is the lowest
133 /* Doubles are stored in memory with the high order word first. This
134 matters when cross-compiling. */
135 #define WORDS_BIG_ENDIAN 1
137 /* number of bits in an addressable storage unit */
138 #define BITS_PER_UNIT 8
140 /* Width in bits of a "word", which is the contents of a machine register.
141 Note that this is not necessarily the width of data type `int';
142 if using 16-bit ints on a 68000, this would still be 32.
143 But on a machine with 16-bit registers, this would be 16. */
144 #define BITS_PER_WORD 32
145 #define MAX_BITS_PER_WORD 32
147 /* Width of a word, in units (bytes). */
148 #define UNITS_PER_WORD 4
150 /* Width in bits of a pointer.
151 See also the macro `Pmode' defined below. */
152 #define POINTER_SIZE 32
154 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
155 #define PARM_BOUNDARY 32
157 /* Boundary (in *bits*) on which stack pointer should be aligned. */
158 #define STACK_BOUNDARY 64
160 /* Allocation boundary (in *bits*) for the code of a function. */
161 #define FUNCTION_BOUNDARY 32
163 /* Alignment of field after `int : 0' in a structure. */
164 #define EMPTY_FIELD_BOUNDARY 32
166 /* Every structure's size must be a multiple of this. */
167 #define STRUCTURE_SIZE_BOUNDARY 8
169 /* A bitfield declared as `int' forces `int' alignment for the struct. */
170 #define PCC_BITFIELD_TYPE_MATTERS 1
172 /* No data type wants to be aligned rounder than this. */
173 #define BIGGEST_ALIGNMENT 64
175 /* Make strings word-aligned so strcpy from constants will be faster. */
176 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
177 (TREE_CODE (EXP) == STRING_CST \
178 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
180 /* Make arrays of chars word-aligned for the same reasons. */
181 #define DATA_ALIGNMENT(TYPE, ALIGN) \
182 (TREE_CODE (TYPE) == ARRAY_TYPE \
183 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
184 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
186 /* Set this nonzero if move instructions will actually fail to work
187 when given unaligned data. */
188 #define STRICT_ALIGNMENT 1
190 /* Things that must be doubleword aligned cannot go in the text section,
191 because the linker fails to align the text section enough!
192 Put them in the data section. */
193 #define MAX_TEXT_ALIGN 32
195 #define SELECT_SECTION(T,RELOC) \
197 if (TREE_CODE (T) == VAR_DECL) \
199 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
200 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
201 && ! (flag_pic && (RELOC))) \
206 else if (TREE_CODE (T) == CONSTRUCTOR) \
208 if (flag_pic != 0 && (RELOC) != 0) \
211 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
213 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
214 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
221 /* Use text section for a constant
222 unless we need more alignment than that offers. */
223 #define SELECT_RTX_SECTION(MODE, X) \
225 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
226 && ! (flag_pic && symbolic_operand (X))) \
232 /* Standard register usage. */
234 /* Number of actual hardware registers.
235 The hardware registers are assigned numbers for the compiler
236 from 0 to just below FIRST_PSEUDO_REGISTER.
237 All registers that the compiler knows about must be given numbers,
238 even those that are not normally considered general registers.
240 SPARC has 32 integer registers and 32 floating point registers. */
242 #define FIRST_PSEUDO_REGISTER 64
244 /* 1 for registers that have pervasive standard uses
245 and are not available for the register allocator.
246 0 is used for the condition code and not to represent %g0, which is
247 hardwired to 0, so reg 0 is *not* fixed.
248 g1 through g4 are free to use as temporaries.
249 g5 through g7 are reserved for the operating system. */
250 #define FIXED_REGISTERS \
251 {0, 0, 0, 0, 0, 1, 1, 1, \
252 0, 0, 0, 0, 0, 0, 1, 0, \
253 0, 0, 0, 0, 0, 0, 0, 0, \
254 0, 0, 0, 0, 0, 0, 1, 1, \
256 0, 0, 0, 0, 0, 0, 0, 0, \
257 0, 0, 0, 0, 0, 0, 0, 0, \
258 0, 0, 0, 0, 0, 0, 0, 0, \
259 0, 0, 0, 0, 0, 0, 0, 0}
261 /* 1 for registers not available across function calls.
262 These must include the FIXED_REGISTERS and also any
263 registers that can be used without being saved.
264 The latter must include the registers where values are returned
265 and the register where structure-value addresses are passed.
266 Aside from that, you can include as many other registers as you like. */
267 #define CALL_USED_REGISTERS \
268 {1, 1, 1, 1, 1, 1, 1, 1, \
269 1, 1, 1, 1, 1, 1, 1, 1, \
270 0, 0, 0, 0, 0, 0, 0, 0, \
271 0, 0, 0, 0, 0, 0, 1, 1, \
273 1, 1, 1, 1, 1, 1, 1, 1, \
274 1, 1, 1, 1, 1, 1, 1, 1, \
275 1, 1, 1, 1, 1, 1, 1, 1, \
276 1, 1, 1, 1, 1, 1, 1, 1}
278 /* Return number of consecutive hard regs needed starting at reg REGNO
279 to hold something of mode MODE.
280 This is ordinarily the length in words of a value of mode MODE
281 but can be less for certain modes in special long registers.
283 On SPARC, ordinary registers hold 32 bits worth;
284 this means both integer and floating point registers.
286 We use vectors to keep this information about registers. */
288 /* How many hard registers it takes to make a register of this mode. */
289 extern int hard_regno_nregs
[];
291 #define HARD_REGNO_NREGS(REGNO, MODE) \
292 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
294 /* Value is 1 if register/mode pair is acceptable on sparc. */
295 extern int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
297 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
298 On SPARC, the cpu registers can hold any mode but the float registers
299 can only hold SFmode or DFmode. See sparc.c for how we
301 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
302 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
304 /* Value is 1 if it is a good idea to tie two pseudo registers
305 when one has mode MODE1 and one has mode MODE2.
306 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
307 for any hard reg, then this must be 0 for correct output. */
308 #define MODES_TIEABLE_P(MODE1, MODE2) \
309 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
311 /* Specify the registers used for certain standard purposes.
312 The values of these macros are register numbers. */
314 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
315 /* #define PC_REGNUM */
317 /* Register to use for pushing function arguments. */
318 #define STACK_POINTER_REGNUM 14
320 /* Actual top-of-stack address is 92 greater than the contents
321 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
322 for the ins and local registers, 4 byte for structure return address, and
323 24 bytes for the 6 register parameters. */
324 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
326 /* Base register for access to local variables of the function. */
327 #define FRAME_POINTER_REGNUM 30
330 /* Register that is used for the return address. */
331 #define RETURN_ADDR_REGNUM 15
334 /* Value should be nonzero if functions must have frame pointers.
335 Zero means the frame pointer need not be set up (and parms
336 may be accessed via the stack pointer) in functions that seem suitable.
337 This is computed in `reload', in reload1.c.
339 Used in flow.c, global-alloc.c, and reload1.c. */
340 extern int leaf_function
;
342 #define FRAME_POINTER_REQUIRED \
343 (! (leaf_function_p () && only_leaf_regs_used ()))
345 /* C statement to store the difference between the frame pointer
346 and the stack pointer values immediately after the function prologue.
348 Note, we always pretend that this is a leaf function because if
349 it's not, there's no point in trying to eliminate the
350 frame pointer. If it is a leaf function, we guessed right! */
351 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
352 do { (VAR) = compute_frame_size (get_frame_size (), 1); } while (0)
354 /* Base register for access to arguments of the function. */
355 #define ARG_POINTER_REGNUM 30
357 /* Register in which static-chain is passed to a function. */
359 #define STATIC_CHAIN_REGNUM 1
361 /* Register which holds offset table for position-independent
364 #define PIC_OFFSET_TABLE_REGNUM 23
366 #define INITIALIZE_PIC initialize_pic ()
367 #define FINALIZE_PIC finalize_pic ()
369 /* Sparc ABI says that quad-precision floats and all structures are returned
371 #define RETURN_IN_MEMORY(TYPE) \
372 (TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE (TYPE) == UNION_TYPE \
373 || TYPE_MODE (TYPE) == TFmode)
375 /* Functions which return large structures get the address
376 to place the wanted value at offset 64 from the frame.
377 Must reserve 64 bytes for the in and local registers. */
378 /* Used only in other #defines in this file. */
379 #define STRUCT_VALUE_OFFSET 64
381 #define STRUCT_VALUE \
382 gen_rtx (MEM, Pmode, \
383 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
384 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
385 #define STRUCT_VALUE_INCOMING \
386 gen_rtx (MEM, Pmode, \
387 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
388 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
390 /* Define the classes of registers for register constraints in the
391 machine description. Also define ranges of constants.
393 One of the classes must always be named ALL_REGS and include all hard regs.
394 If there is more than one class, another class must be named NO_REGS
395 and contain no registers.
397 The name GENERAL_REGS must be the name of a class (or an alias for
398 another name such as ALL_REGS). This is the class of registers
399 that is allowed by "g" or "r" in a register constraint.
400 Also, registers outside this class are allocated only when
401 instructions express preferences for them.
403 The classes must be numbered in nondecreasing order; that is,
404 a larger-numbered class must never be contained completely
405 in a smaller-numbered class.
407 For any two classes, it is very desirable that there be another
408 class that represents their union. */
410 /* The SPARC has two kinds of registers, general and floating point. */
412 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
414 #define N_REG_CLASSES (int) LIM_REG_CLASSES
416 /* Give names of register classes as strings for dump file. */
418 #define REG_CLASS_NAMES \
419 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
421 /* Define which registers fit in which classes.
422 This is an initializer for a vector of HARD_REG_SET
423 of length N_REG_CLASSES. */
425 #if 0 && defined (__GNUC__)
426 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
428 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
431 /* The same information, inverted:
432 Return the class number of the smallest class containing
433 reg number REGNO. This could be a conditional expression
434 or could index an array. */
436 #define REGNO_REG_CLASS(REGNO) \
437 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
439 /* This is the order in which to allocate registers
441 #define REG_ALLOC_ORDER \
442 { 8, 9, 10, 11, 12, 13, 2, 3, \
443 15, 16, 17, 18, 19, 20, 21, 22, \
444 23, 24, 25, 26, 27, 28, 29, 31, \
445 32, 33, 34, 35, 36, 37, 38, 39, \
446 40, 41, 42, 43, 44, 45, 46, 47, \
447 48, 49, 50, 51, 52, 53, 54, 55, \
448 56, 57, 58, 59, 60, 61, 62, 63, \
449 1, 4, 5, 6, 7, 0, 14, 30}
451 /* This is the order in which to allocate registers for
452 leaf functions. If all registers can fit in the "i" registers,
453 then we have the possibility of having a leaf function. */
454 #define REG_LEAF_ALLOC_ORDER \
455 { 2, 3, 24, 25, 26, 27, 28, 29, \
456 15, 8, 9, 10, 11, 12, 13, \
457 16, 17, 18, 19, 20, 21, 22, 23, \
458 32, 33, 34, 35, 36, 37, 38, 39, \
459 40, 41, 42, 43, 44, 45, 46, 47, \
460 48, 49, 50, 51, 52, 53, 54, 55, \
461 56, 57, 58, 59, 60, 61, 62, 63, \
462 1, 4, 5, 6, 7, 0, 14, 30, 31}
464 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
466 #define LEAF_REGISTERS \
467 { 1, 1, 1, 1, 1, 1, 1, 1, \
468 0, 0, 0, 0, 0, 0, 1, 0, \
469 0, 0, 0, 0, 0, 0, 0, 0, \
470 1, 1, 1, 1, 1, 1, 0, 1, \
471 1, 1, 1, 1, 1, 1, 1, 1, \
472 1, 1, 1, 1, 1, 1, 1, 1, \
473 1, 1, 1, 1, 1, 1, 1, 1, \
474 1, 1, 1, 1, 1, 1, 1, 1}
476 extern char leaf_reg_remap
[];
477 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
478 extern char leaf_reg_backmap
[];
479 #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
481 #define REG_USED_SO_FAR(REGNO) \
482 ((REGNO) >= 24 && (REGNO) < 30 \
483 ? (regs_ever_live[24] \
484 || regs_ever_live[25] \
485 || regs_ever_live[26] \
486 || regs_ever_live[27] \
487 || regs_ever_live[28] \
488 || regs_ever_live[29]) : 0)
490 /* The class value for index registers, and the one for base regs. */
491 #define INDEX_REG_CLASS GENERAL_REGS
492 #define BASE_REG_CLASS GENERAL_REGS
494 /* Get reg_class from a letter such as appears in the machine description. */
496 #define REG_CLASS_FROM_LETTER(C) \
497 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
499 /* The letters I, J, K, L and M in a register constraint string
500 can be used to stand for particular ranges of immediate operands.
501 This macro defines what the ranges are.
502 C is the letter, and VALUE is a constant value.
503 Return 1 if VALUE is in the range specified by C.
505 For SPARC, `I' is used for the range of constants an insn
506 can actually contain.
507 `J' is used for the range which is just zero (since that is R0).
508 `K' is used for the 5-bit operand of a compare insns. */
510 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
512 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
513 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
514 : (C) == 'J' ? (VALUE) == 0 \
515 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
518 /* Similar, but for floating constants, and defining letters G and H.
519 Here VALUE is the CONST_DOUBLE rtx itself. */
521 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
522 ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
523 && CONST_DOUBLE_LOW (VALUE) == 0 \
524 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
527 /* Given an rtx X being reloaded into a reg required to be
528 in class CLASS, return the class of reg to actually use.
529 In general this is just CLASS; but on some machines
530 in some cases it is preferable to use a more restrictive class. */
531 #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
533 /* Return the register class of a scratch register needed to load IN into
534 a register of class CLASS in MODE.
536 On the SPARC, when PIC, we need a temporary when loading some addresses
539 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
540 (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS : NO_REGS)
542 /* Return the maximum number of consecutive registers
543 needed to represent mode MODE in a register of class CLASS. */
544 /* On SPARC, this is the size of MODE in words. */
545 #define CLASS_MAX_NREGS(CLASS, MODE) \
546 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
548 /* Stack layout; function entry, exit and calling. */
550 /* Define the number of register that can hold parameters.
551 These two macros are used only in other macro definitions below. */
554 /* Define this if pushing a word on the stack
555 makes the stack pointer a smaller address. */
556 #define STACK_GROWS_DOWNWARD
558 /* Define this if the nominal address of the stack frame
559 is at the high-address end of the local variables;
560 that is, each additional local variable allocated
561 goes at a more negative offset in the frame. */
562 #define FRAME_GROWS_DOWNWARD
564 /* Offset within stack frame to start allocating local variables at.
565 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
566 first local allocated. Otherwise, it is the offset to the BEGINNING
567 of the first local allocated. */
568 #define STARTING_FRAME_OFFSET (-16)
570 /* If we generate an insn to push BYTES bytes,
571 this says how many the stack pointer really advances by.
572 On SPARC, don't define this because there are no push insns. */
573 /* #define PUSH_ROUNDING(BYTES) */
575 /* Offset of first parameter from the argument pointer register value.
576 This is 64 for the ins and locals, plus 4 for the struct-return reg
577 even if this function isn't going to use it.
578 If TARGET_FORCE_ALIGN, we must reserve 4 more bytes to ensure that the
579 stack remains aligned. */
580 #define FIRST_PARM_OFFSET(FNDECL) \
581 (STRUCT_VALUE_OFFSET + UNITS_PER_WORD + (TARGET_FORCE_ALIGN ? 4 : 0))
583 /* When a parameter is passed in a register, stack space is still
585 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
587 /* Keep the stack pointer constant throughout the function.
588 This is both an optimization and a necessity: longjmp
589 doesn't behave itself when the stack pointer moves within
591 #define ACCUMULATE_OUTGOING_ARGS
593 /* Value is the number of bytes of arguments automatically
594 popped when returning from a subroutine call.
595 FUNTYPE is the data type of the function (as a tree),
596 or for a library call it is an identifier node for the subroutine name.
597 SIZE is the number of bytes of arguments passed on the stack. */
599 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
601 /* Some subroutine macros specific to this machine. */
602 #define BASE_RETURN_VALUE_REG(MODE) \
603 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8)
604 #define BASE_OUTGOING_VALUE_REG(MODE) \
605 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24)
606 #define BASE_PASSING_ARG_REG(MODE) (8)
607 #define BASE_INCOMING_ARG_REG(MODE) (24)
609 /* Define how to find the value returned by a function.
610 VALTYPE is the data type of the value (as a tree).
611 If the precise function being called is known, FUNC is its FUNCTION_DECL;
612 otherwise, FUNC is 0. */
614 /* On SPARC the value is found in the first "output" register. */
616 #define FUNCTION_VALUE(VALTYPE, FUNC) \
617 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
619 /* But the called function leaves it in the first "input" register. */
621 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
622 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
624 /* Define how to find the value returned by a library function
625 assuming the value has mode MODE. */
627 #define LIBCALL_VALUE(MODE) \
628 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
630 /* 1 if N is a possible register number for a function value
631 as seen by the caller.
632 On SPARC, the first "output" reg is used for integer values,
633 and the first floating point register is used for floating point values. */
635 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
637 /* 1 if N is a possible register number for function argument passing.
638 On SPARC, these are the "output" registers. */
640 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
642 /* Define a data type for recording info about an argument list
643 during the scan of that argument list. This data type should
644 hold all necessary information about the function itself
645 and about the args processed so far, enough to enable macros
646 such as FUNCTION_ARG to determine where the next arg should go.
648 On SPARC, this is a single integer, which is a number of words
649 of arguments scanned so far (including the invisible argument,
650 if any, which holds the structure-value-address).
651 Thus 7 or more means all following args should go on the stack. */
653 #define CUMULATIVE_ARGS int
655 #define ROUND_ADVANCE(SIZE) \
656 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
658 /* Round a register number up to a proper boundary for an arg of mode MODE.
659 Note that we need an odd/even pair for a two-word arg,
660 since that will become 8-byte aligned when stored in memory. */
661 #define ROUND_REG(X, MODE) \
662 (TARGET_FORCE_ALIGN && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
663 ? ((X) + ! ((X) & 1)) : (X))
665 /* Initialize a variable CUM of type CUMULATIVE_ARGS
666 for a call to a function whose data type is FNTYPE.
667 For a library call, FNTYPE is 0.
669 On SPARC, the offset always starts at 0: the first parm reg is always
672 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
674 /* Update the data in CUM to advance over an argument
675 of mode MODE and data type TYPE.
676 (TYPE is null for libcalls where that information may not be available.) */
678 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
679 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
680 + ((MODE) != BLKmode \
681 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
682 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
684 /* Determine where to put an argument to a function.
685 Value is zero to push the argument on the stack,
686 or a hard register in which to store the argument.
688 MODE is the argument's machine mode.
689 TYPE is the data type of the argument (as a tree).
690 This is null for libcalls where that information may
692 CUM is a variable of type CUMULATIVE_ARGS which gives info about
693 the preceding args and about the function being called.
694 NAMED is nonzero if this argument is a named parameter
695 (otherwise it is an extra parameter matching an ellipsis). */
697 /* On SPARC the first six args are normally in registers
698 and the rest are pushed. Any arg that starts within the first 6 words
699 is at least partially passed in a register unless its data type forbids. */
701 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
702 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
703 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
704 && ((TYPE)==0 || (MODE) != BLKmode \
705 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
706 ? gen_rtx (REG, (MODE), \
707 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
710 /* Define where a function finds its arguments.
711 This is different from FUNCTION_ARG because of register windows. */
713 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
714 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
715 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
716 && ((TYPE)==0 || (MODE) != BLKmode \
717 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
718 ? gen_rtx (REG, (MODE), \
719 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
722 /* For an arg passed partly in registers and partly in memory,
723 this is the number of registers used.
724 For args passed entirely in registers or entirely in memory, zero.
725 Any arg that starts in the first 6 regs but won't entirely fit in them
726 needs partial registers on the Sparc. */
728 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
729 ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
730 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
731 && ((TYPE)==0 || (MODE) != BLKmode \
732 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
733 && (ROUND_REG ((CUM), (MODE)) \
734 + ((MODE) == BLKmode \
735 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
736 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
737 ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
740 /* The SPARC ABI stipulates passing struct arguments (of any size) and
741 quad-precision floats by invisible reference. */
742 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
743 ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
744 || TREE_CODE (TYPE) == UNION_TYPE)) \
747 /* If defined, a C expression that gives the alignment boundary, in
748 bits, of an argument with the specified mode and type. If it is
749 not defined, `PARM_BOUNDARY' is used for all arguments.
751 This definition does nothing special unless TARGET_FORCE_ALIGN;
752 in that case, it aligns each arg to the natural boundary. */
754 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
755 (! TARGET_FORCE_ALIGN \
758 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
760 : TYPE_ALIGN (TYPE)) \
761 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
763 : GET_MODE_ALIGNMENT (MODE))))
765 /* Define the information needed to generate branch and scc insns. This is
766 stored from the compare operation. Note that we can't use "rtx" here
767 since it hasn't been defined! */
769 extern struct rtx_def
*sparc_compare_op0
, *sparc_compare_op1
;
771 /* Define the function that build the compare insn for scc and bcc. */
773 extern struct rtx_def
*gen_compare_reg ();
775 /* Generate the special assembly code needed to tell the assembler whatever
776 it might need to know about the return value of a function.
778 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
779 information to the assembler relating to peephole optimization (done in
782 #define ASM_DECLARE_RESULT(FILE, RESULT) \
783 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
785 /* Output the label for a function definition. */
787 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
789 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
790 ASM_OUTPUT_LABEL (FILE, NAME); \
793 /* Two views of the size of the current frame. */
794 extern int actual_fsize
;
795 extern int apparent_fsize
;
797 /* This macro generates the assembly code for function entry.
798 FILE is a stdio stream to output the code to.
799 SIZE is an int: how many units of temporary storage to allocate.
800 Refer to the array `regs_ever_live' to determine which registers
801 to save; `regs_ever_live[I]' is nonzero if register number I
802 is ever used in the function. This macro is responsible for
803 knowing which registers should not be saved even if used. */
805 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
806 of memory. If any fpu reg is used in the function, we allocate
807 such a block here, at the bottom of the frame, just in case it's needed.
809 If this function is a leaf procedure, then we may choose not
810 to do a "save" insn. The decision about whether or not
811 to do this is made in regclass.c. */
813 #define FUNCTION_PROLOGUE(FILE, SIZE) \
814 output_function_prologue (FILE, SIZE, leaf_function)
816 /* Output assembler code to FILE to increment profiler label # LABELNO
817 for profiling a function entry. */
819 #define FUNCTION_PROFILER(FILE, LABELNO) \
820 fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
821 (LABELNO), (LABELNO))
823 /* Output assembler code to FILE to initialize this source file's
824 basic block profiling info, if that has not already been done. */
826 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
827 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
828 (LABELNO), (LABELNO))
830 /* Output assembler code to FILE to increment the entry-count for
831 the BLOCKNO'th basic block in this source file. */
833 #define BLOCK_PROFILER(FILE, BLOCKNO) \
835 int blockn = (BLOCKNO); \
836 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
837 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
838 4 * blockn, 4 * blockn, 4 * blockn); \
841 /* Output rtl to increment the entry-count for the LABELNO'th instrumented
842 arc in this source file. */
844 #define ARC_PROFILER(ARCNO, INSERT_AFTER) \
845 output_arc_profiler (ARCNO, INSERT_AFTER)
847 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
848 the stack pointer does not matter. The value is tested only in
849 functions that have frame pointers.
850 No definition is equivalent to always zero. */
852 extern int current_function_calls_alloca
;
853 extern int current_function_outgoing_args_size
;
855 #define EXIT_IGNORE_STACK \
856 (get_frame_size () != 0 \
857 || current_function_calls_alloca || current_function_outgoing_args_size)
859 /* This macro generates the assembly code for function exit,
860 on machines that need it. If FUNCTION_EPILOGUE is not defined
861 then individual return instructions are generated for each
862 return statement. Args are same as for FUNCTION_PROLOGUE.
864 The function epilogue should not depend on the current stack pointer!
865 It should use the frame pointer only. This is mandatory because
866 of alloca; we also take advantage of it to omit stack adjustments
869 /* This declaration is needed due to traditional/ANSI
870 incompatibilities which cannot be #ifdefed away
871 because they occur inside of macros. Sigh. */
872 extern union tree_node
*current_function_decl
;
874 #define FUNCTION_EPILOGUE(FILE, SIZE) \
875 output_function_epilogue (FILE, SIZE, leaf_function)
877 #define DELAY_SLOTS_FOR_EPILOGUE 1
878 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
879 eligible_for_epilogue_delay (trial, slots_filled)
881 /* Output assembler code for a block containing the constant parts
882 of a trampoline, leaving space for the variable parts. */
884 /* On the sparc, the trampoline contains five instructions:
885 sethi #TOP_OF_FUNCTION,%g2
886 or #BOTTOM_OF_FUNCTION,%g2,%g2
887 sethi #TOP_OF_STATIC,%g1
889 or #BOTTOM_OF_STATIC,%g1,%g1 */
890 #define TRAMPOLINE_TEMPLATE(FILE) \
892 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
893 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
894 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
895 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
896 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
899 /* Length in units of the trampoline for entering a nested function. */
901 #define TRAMPOLINE_SIZE 20
903 /* Emit RTL insns to initialize the variable parts of a trampoline.
904 FNADDR is an RTX for the address of the function's pure code.
905 CXT is an RTX for the static chain value for the function.
907 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
908 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
909 (to store insns). This is a bit excessive. Perhaps a different
910 mechanism would be better here. */
912 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
914 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
915 size_int (10), 0, 1); \
916 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
917 size_int (10), 0, 1); \
918 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
919 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
920 rtx g1_sethi = gen_rtx (HIGH, SImode, \
921 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
922 rtx g2_sethi = gen_rtx (HIGH, SImode, \
923 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
924 rtx g1_ori = gen_rtx (HIGH, SImode, \
925 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
926 rtx g2_ori = gen_rtx (HIGH, SImode, \
927 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
928 rtx tem = gen_reg_rtx (SImode); \
929 emit_move_insn (tem, g2_sethi); \
930 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
931 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
932 emit_move_insn (tem, g2_ori); \
933 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
934 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
935 emit_move_insn (tem, g1_sethi); \
936 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
937 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
938 emit_move_insn (tem, g1_ori); \
939 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
940 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
943 /* Emit code for a call to builtin_saveregs. We must emit USE insns which
944 reference the 6 input registers. Ordinarily they are not call used
945 registers, but they are for _builtin_saveregs, so we must make this
948 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) \
949 (emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, TImode, 24))), \
950 emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, DImode, 28))), \
951 expand_call (exp, target, ignore))
953 /* Addressing modes, and classification of registers for them. */
955 /* #define HAVE_POST_INCREMENT */
956 /* #define HAVE_POST_DECREMENT */
958 /* #define HAVE_PRE_DECREMENT */
959 /* #define HAVE_PRE_INCREMENT */
961 /* Macros to check register numbers against specific register classes. */
963 /* These assume that REGNO is a hard or pseudo reg number.
964 They give nonzero only if REGNO is a hard reg of the suitable class
965 or a pseudo reg currently allocated to a suitable hard reg.
966 Since they use reg_renumber, they are safe only once reg_renumber
967 has been allocated, which happens in local-alloc.c. */
969 #define REGNO_OK_FOR_INDEX_P(REGNO) \
970 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
971 #define REGNO_OK_FOR_BASE_P(REGNO) \
972 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
973 #define REGNO_OK_FOR_FP_P(REGNO) \
974 (((REGNO) ^ 0x20) < 32 \
975 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
977 /* Now macros that check whether X is a register and also,
978 strictly, whether it is in a specified class.
980 These macros are specific to the SPARC, and may be used only
981 in code for printing assembler insns and in conditions for
982 define_optimization. */
984 /* 1 if X is an fp register. */
986 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
988 /* Maximum number of registers that can appear in a valid memory address. */
990 #define MAX_REGS_PER_ADDRESS 2
992 /* Recognize any constant value that is a valid address. */
994 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
996 /* Nonzero if the constant value X is a legitimate general operand.
997 Anything can be made to work except floating point constants. */
999 #define LEGITIMATE_CONSTANT_P(X) \
1000 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1002 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1003 and check its validity for a certain class.
1004 We have two alternate definitions for each of them.
1005 The usual definition accepts all pseudo regs; the other rejects
1006 them unless they have been allocated suitable hard regs.
1007 The symbol REG_OK_STRICT causes the latter definition to be used.
1009 Most source files want to accept pseudo regs in the hope that
1010 they will get allocated to the class that the insn wants them to be in.
1011 Source files for reload pass need to be strict.
1012 After reload, it makes no difference, since pseudo regs have
1013 been eliminated by then. */
1015 /* Optional extra constraints for this machine. Borrowed from romp.h.
1017 For the SPARC, `Q' means that this is a memory operand but not a
1018 symbolic memory operand. Note that an unassigned pseudo register
1019 is such a memory operand. Needed because reload will generate
1020 these things in insns and then not re-recognize the insns, causing
1021 constrain_operands to fail.
1023 `R' handles the LO_SUM which can be an address for `Q'.
1025 `S' handles constraints for calls. */
1027 #ifndef REG_OK_STRICT
1029 /* Nonzero if X is a hard reg that can be used as an index
1030 or if it is a pseudo reg. */
1031 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1032 /* Nonzero if X is a hard reg that can be used as a base reg
1033 or if it is a pseudo reg. */
1034 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1036 #define EXTRA_CONSTRAINT(OP, C) \
1038 ((GET_CODE (OP) == MEM \
1039 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1040 && ! symbolic_memory_operand (OP, VOIDmode))) \
1042 (GET_CODE (OP) == LO_SUM \
1043 && GET_CODE (XEXP (OP, 0)) == REG \
1044 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1046 ? CONSTANT_P (OP) || memory_address_p (Pmode, OP) : 0)))
1050 /* Nonzero if X is a hard reg that can be used as an index. */
1051 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1052 /* Nonzero if X is a hard reg that can be used as a base reg. */
1053 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1055 #define EXTRA_CONSTRAINT(OP, C) \
1057 (GET_CODE (OP) == REG ? \
1058 (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1059 && reg_renumber[REGNO (OP)] < 0) \
1060 : GET_CODE (OP) == MEM) \
1062 (GET_CODE (OP) == LO_SUM \
1063 && GET_CODE (XEXP (OP, 0)) == REG \
1064 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1066 ? (CONSTANT_P (OP) \
1067 || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\
1068 || strict_memory_address_p (Pmode, OP)) : 0)))
1071 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1072 that is a valid memory address for an instruction.
1073 The MODE argument is the machine mode for the MEM expression
1074 that wants to use this address.
1076 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1077 ordinarily. This changes a bit when generating PIC.
1079 If you change this, execute "rm explow.o recog.o reload.o". */
1081 #define RTX_OK_FOR_BASE_P(X) \
1082 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1083 || (GET_CODE (X) == SUBREG \
1084 && GET_CODE (SUBREG_REG (X)) == REG \
1085 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1087 #define RTX_OK_FOR_INDEX_P(X) \
1088 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1089 || (GET_CODE (X) == SUBREG \
1090 && GET_CODE (SUBREG_REG (X)) == REG \
1091 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1093 #define RTX_OK_FOR_OFFSET_P(X) \
1094 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1096 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1097 { if (RTX_OK_FOR_BASE_P (X)) \
1099 else if (GET_CODE (X) == PLUS) \
1101 register rtx op0 = XEXP (X, 0); \
1102 register rtx op1 = XEXP (X, 1); \
1103 if (flag_pic && op0 == pic_offset_table_rtx) \
1105 if (RTX_OK_FOR_BASE_P (op1)) \
1107 else if (flag_pic == 1 \
1108 && GET_CODE (op1) != REG \
1109 && GET_CODE (op1) != LO_SUM \
1110 && GET_CODE (op1) != MEM) \
1113 else if (RTX_OK_FOR_BASE_P (op0)) \
1115 if (RTX_OK_FOR_INDEX_P (op1) \
1116 || RTX_OK_FOR_OFFSET_P (op1)) \
1119 else if (RTX_OK_FOR_BASE_P (op1)) \
1121 if (RTX_OK_FOR_INDEX_P (op0) \
1122 || RTX_OK_FOR_OFFSET_P (op0)) \
1126 else if (GET_CODE (X) == LO_SUM) \
1128 register rtx op0 = XEXP (X, 0); \
1129 register rtx op1 = XEXP (X, 1); \
1130 if (RTX_OK_FOR_BASE_P (op0) \
1131 && CONSTANT_P (op1)) \
1134 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1138 /* Try machine-dependent ways of modifying an illegitimate address
1139 to be legitimate. If we find one, return the new, valid address.
1140 This macro is used in only one place: `memory_address' in explow.c.
1142 OLDX is the address as it was before break_out_memory_refs was called.
1143 In some cases it is useful to look at this to decide what needs to be done.
1145 MODE and WIN are passed so that this macro can use
1146 GO_IF_LEGITIMATE_ADDRESS.
1148 It is always safe for this macro to do nothing. It exists to recognize
1149 opportunities to optimize the output. */
1151 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1152 extern struct rtx_def
*legitimize_pic_address ();
1153 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1154 { rtx sparc_x = (X); \
1155 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1156 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1157 force_operand (XEXP (X, 0), 0)); \
1158 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1159 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1160 force_operand (XEXP (X, 1), 0)); \
1161 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1162 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), 0),\
1164 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1165 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1166 force_operand (XEXP (X, 1), 0)); \
1167 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1169 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1170 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1171 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1172 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1173 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1174 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1175 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1176 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1177 || GET_CODE (X) == LABEL_REF) \
1178 (X) = gen_rtx (LO_SUM, Pmode, \
1179 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1180 if (memory_address_p (MODE, X)) \
1183 /* Go to LABEL if ADDR (a legitimate address expression)
1184 has an effect that depends on the machine mode it is used for.
1185 On the SPARC this is never true. */
1187 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1189 /* Specify the machine mode that this machine uses
1190 for the index in the tablejump instruction. */
1191 #define CASE_VECTOR_MODE SImode
1193 /* Define this if the tablejump instruction expects the table
1194 to contain offsets from the address of the table.
1195 Do not define this if the table should contain absolute addresses. */
1196 /* #define CASE_VECTOR_PC_RELATIVE */
1198 /* Specify the tree operation to be used to convert reals to integers. */
1199 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1201 /* This is the kind of divide that is easiest to do in the general case. */
1202 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1204 /* Define this as 1 if `char' should by default be signed; else as 0. */
1205 #define DEFAULT_SIGNED_CHAR 1
1207 /* Max number of bytes we can move from memory to memory
1208 in one reasonably fast instruction. */
1211 /* Define if normal loads of shorter-than-word items from memory clears
1212 the rest of the bigs in the register. */
1213 #define BYTE_LOADS_ZERO_EXTEND
1215 /* Nonzero if access to memory by bytes is slow and undesirable.
1216 For RISC chips, it means that access to memory by bytes is no
1217 better than access by words when possible, so grab a whole word
1218 and maybe make use of that. */
1219 #define SLOW_BYTE_ACCESS 1
1221 /* We assume that the store-condition-codes instructions store 0 for false
1222 and some other value for true. This is the value stored for true. */
1224 #define STORE_FLAG_VALUE 1
1226 /* When a prototype says `char' or `short', really pass an `int'. */
1227 #define PROMOTE_PROTOTYPES
1229 /* Define if shifts truncate the shift count
1230 which implies one can omit a sign-extension or zero-extension
1231 of a shift count. */
1232 #define SHIFT_COUNT_TRUNCATED
1234 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1235 is done just by pretending it is already truncated. */
1236 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1238 /* Specify the machine mode that pointers have.
1239 After generation of rtl, the compiler makes no further distinction
1240 between pointers and any other objects of this machine mode. */
1241 #define Pmode SImode
1243 /* Generate calls to memcpy, memcmp and memset. */
1244 #define TARGET_MEM_FUNCTIONS
1246 /* Add any extra modes needed to represent the condition code.
1248 On the Sparc, we have a "no-overflow" mode which is used when an add or
1249 subtract insn is used to set the condition code. Different branches are
1250 used in this case for some operations.
1252 We also have two modes to indicate that the relevant condition code is
1253 in the floating-point condition code register. One for comparisons which
1254 will generate an exception if the result is unordered (CCFPEmode) and
1255 one for comparisons which will never trap (CCFPmode). This really should
1256 be a separate register, but we don't want to go to 65 registers. */
1257 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1259 /* Define the names for the modes specified above. */
1260 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1262 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1263 return the mode to be used for the comparison. For floating-point,
1264 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1265 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1267 #define SELECT_CC_MODE(OP,X) \
1268 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1269 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1270 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1271 ? CC_NOOVmode : CCmode))
1273 /* A function address in a call instruction
1274 is a byte address (for indexing purposes)
1275 so give the MEM rtx a byte's mode. */
1276 #define FUNCTION_MODE SImode
1278 /* Define this if addresses of constant functions
1279 shouldn't be put through pseudo regs where they can be cse'd.
1280 Desirable on machines where ordinary constants are expensive
1281 but a CALL with constant address is cheap. */
1282 #define NO_FUNCTION_CSE
1284 /* alloca should avoid clobbering the old register save area. */
1285 #define SETJMP_VIA_SAVE_AREA
1287 /* Define subroutines to call to handle multiply and divide.
1288 Use the subroutines that Sun's library provides.
1289 The `*' prevents an underscore from being prepended by the compiler. */
1291 #define DIVSI3_LIBCALL "*.div"
1292 #define UDIVSI3_LIBCALL "*.udiv"
1293 #define MODSI3_LIBCALL "*.rem"
1294 #define UMODSI3_LIBCALL "*.urem"
1295 /* .umul is a little faster than .mul. */
1296 #define MULSI3_LIBCALL "*.umul"
1298 /* Compute the cost of computing a constant rtl expression RTX
1299 whose rtx-code is CODE. The body of this macro is a portion
1300 of a switch statement. If the code is computed here,
1301 return it with a return statement. Otherwise, break from the switch. */
1303 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1305 if (INTVAL (RTX) == 0) \
1307 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1315 case CONST_DOUBLE: \
1316 if (GET_MODE (RTX) == DImode) \
1317 if ((XINT (RTX, 3) == 0 \
1318 && (unsigned) XINT (RTX, 2) < 0x1000) \
1319 || (XINT (RTX, 3) == -1 \
1320 && XINT (RTX, 2) < 0 \
1321 && XINT (RTX, 2) >= -0x1000)) \
1325 /* SPARC offers addressing modes which are "as cheap as a register".
1326 See sparc.c (or gcc.texinfo) for details. */
1328 #define ADDRESS_COST(RTX) \
1329 (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1331 /* Compute extra cost of moving data between one register class
1333 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1334 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1335 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1337 /* Provide the costs of a rtl expression. This is in the body of a
1338 switch on CODE. The purpose for the cost of MULT is to encourage
1339 `synth_mult' to find a synthetic multiply when reasonable.
1341 If we need more than 12 insns to do a multiply, then go out-of-line,
1342 since the call overhead will be < 10% of the cost of the multiply. */
1344 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1346 return COSTS_N_INSNS (25); \
1351 return COSTS_N_INSNS (20); \
1352 /* Make FLOAT more expensive than CONST_DOUBLE, \
1353 so that cse will favor the latter. */ \
1357 /* Conditional branches with empty delay slots have a length of two. */
1358 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1359 if (GET_CODE (INSN) == CALL_INSN \
1360 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1363 /* Control the assembler format that we output. */
1365 /* Output at beginning of assembler file. */
1367 #define ASM_FILE_START(file)
1369 /* Output to assembler file text saying following lines
1370 may contain character constants, extra white space, comments, etc. */
1372 #define ASM_APP_ON ""
1374 /* Output to assembler file text saying following lines
1375 no longer contain unusual constructs. */
1377 #define ASM_APP_OFF ""
1379 /* Output before read-only data. */
1381 #define TEXT_SECTION_ASM_OP ".text"
1383 /* Output before writable data. */
1385 #define DATA_SECTION_ASM_OP ".data"
1387 /* How to refer to registers in assembler output.
1388 This sequence is indexed by compiler's hard-register-number (see above). */
1390 #define REGISTER_NAMES \
1391 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1392 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1393 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1394 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1395 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1396 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1397 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1398 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1400 /* Define additional names for use in asm clobbers and asm declarations.
1402 We define the fake Condition Code register as an alias for reg 0 (which
1403 is our `condition code' register), so that condition codes can easily
1404 be clobbered by an asm. No such register actually exists. Condition
1405 codes are partly stored in the PSR and partly in the FSR. */
1407 #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1409 /* How to renumber registers for dbx and gdb. */
1411 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1413 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1414 since the length can run past this up to a continuation point. */
1415 #define DBX_CONTIN_LENGTH 1500
1417 /* This is how to output a note to DBX telling it the line number
1418 to which the following sequence of instructions corresponds.
1420 This is needed for SunOS 4.0, and should not hurt for 3.2
1422 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1423 { static int sym_lineno = 1; \
1424 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1425 line, sym_lineno, sym_lineno); \
1428 /* This is how to output the definition of a user-level label named NAME,
1429 such as the label on a static function or variable NAME. */
1431 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1432 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1434 /* This is how to output a command to make the user-level label named NAME
1435 defined for reference from other files. */
1437 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1438 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1440 /* This is how to output a reference to a user-level label named NAME.
1441 `assemble_name' uses this. */
1443 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1444 fprintf (FILE, "_%s", NAME)
1446 /* This is how to output an internal numbered label where
1447 PREFIX is the class of label and NUM is the number within the class. */
1449 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1450 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1452 /* This is how to store into the string LABEL
1453 the symbol_ref name of an internal numbered label where
1454 PREFIX is the class of label and NUM is the number within the class.
1455 This is suitable for output with `assemble_name'. */
1457 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1458 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1460 /* This is how to output an assembler line defining a `double' constant. */
1462 /* Assemblers (both gas 1.35 and as in 4.0.3)
1463 seem to treat -0.0 as if it were 0.0.
1464 They reject 99e9999, but accept inf. */
1465 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1467 if (REAL_VALUE_ISINF (VALUE)) \
1468 fprintf (FILE, "\t.double 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1469 else if (REAL_VALUE_ISNAN (VALUE) \
1470 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1472 union { double d; long l[2];} t; \
1474 fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t.l[0], t.l[1]); \
1477 fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1480 /* This is how to output an assembler line defining a `float' constant. */
1482 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1484 if (REAL_VALUE_ISINF (VALUE)) \
1485 fprintf (FILE, "\t.single 0r%sinf\n", (VALUE) > 0 ? "" : "-"); \
1486 else if (REAL_VALUE_ISNAN (VALUE) \
1487 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1489 union { float f; long l;} t; \
1491 fprintf (FILE, "\t.word 0x%lx\n", t.l); \
1494 fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1497 /* This is how to output an assembler line defining an `int' constant. */
1499 #define ASM_OUTPUT_INT(FILE,VALUE) \
1500 ( fprintf (FILE, "\t.word "), \
1501 output_addr_const (FILE, (VALUE)), \
1502 fprintf (FILE, "\n"))
1504 /* This is how to output an assembler line defining a DImode constant. */
1505 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1506 output_double_int (FILE, VALUE)
1508 /* Likewise for `char' and `short' constants. */
1510 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1511 ( fprintf (FILE, "\t.half "), \
1512 output_addr_const (FILE, (VALUE)), \
1513 fprintf (FILE, "\n"))
1515 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1516 ( fprintf (FILE, "\t.byte "), \
1517 output_addr_const (FILE, (VALUE)), \
1518 fprintf (FILE, "\n"))
1520 /* This is how to output an assembler line for a numeric constant byte. */
1522 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1523 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1525 /* This is how to output an element of a case-vector that is absolute. */
1527 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1530 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1531 fprintf (FILE, "\t.word\t"); \
1532 assemble_name (FILE, label); \
1533 fprintf (FILE, "\n"); \
1536 /* This is how to output an element of a case-vector that is relative.
1537 (SPARC uses such vectors only when generating PIC.) */
1539 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1542 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1543 fprintf (FILE, "\t.word\t"); \
1544 assemble_name (FILE, label); \
1545 fprintf (FILE, "-1b\n"); \
1548 /* This is how to output an assembler line
1549 that says to advance the location counter
1550 to a multiple of 2**LOG bytes. */
1552 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1554 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1556 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1557 fprintf (FILE, "\t.skip %u\n", (SIZE))
1559 /* This says how to output an assembler line
1560 to define a global common symbol. */
1562 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1563 ( fputs ("\t.global ", (FILE)), \
1564 assemble_name ((FILE), (NAME)), \
1565 fputs ("\n\t.common ", (FILE)), \
1566 assemble_name ((FILE), (NAME)), \
1567 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1569 /* This says how to output an assembler line
1570 to define a local common symbol. */
1572 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1573 ( fputs ("\n\t.reserve ", (FILE)), \
1574 assemble_name ((FILE), (NAME)), \
1575 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1577 /* Store in OUTPUT a string (made with alloca) containing
1578 an assembler-name for a local static variable named NAME.
1579 LABELNO is an integer which is different for each call. */
1581 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1582 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1583 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1585 /* Define the parentheses used to group arithmetic operations
1586 in assembler code. */
1588 #define ASM_OPEN_PAREN "("
1589 #define ASM_CLOSE_PAREN ")"
1591 /* Define results of standard character escape sequences. */
1592 #define TARGET_BELL 007
1593 #define TARGET_BS 010
1594 #define TARGET_TAB 011
1595 #define TARGET_NEWLINE 012
1596 #define TARGET_VT 013
1597 #define TARGET_FF 014
1598 #define TARGET_CR 015
1600 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1601 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1603 /* Print operand X (an rtx) in assembler syntax to file FILE.
1604 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1605 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1607 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1609 /* Print a memory address as an operand to reference that memory location. */
1611 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1612 { register rtx base, index = 0; \
1614 register rtx addr = ADDR; \
1615 if (GET_CODE (addr) == REG) \
1616 fputs (reg_names[REGNO (addr)], FILE); \
1617 else if (GET_CODE (addr) == PLUS) \
1619 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1620 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1621 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1622 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1624 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1625 fputs (reg_names[REGNO (base)], FILE); \
1627 fprintf (FILE, "%+d", offset); \
1628 else if (GET_CODE (index) == REG) \
1629 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1630 else if (GET_CODE (index) == SYMBOL_REF) \
1631 fputc ('+', FILE), output_addr_const (FILE, index); \
1634 else if (GET_CODE (addr) == MINUS \
1635 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1637 output_addr_const (FILE, XEXP (addr, 0)); \
1638 fputs ("-(", FILE); \
1639 output_addr_const (FILE, XEXP (addr, 1)); \
1640 fputs ("-.)", FILE); \
1642 else if (GET_CODE (addr) == LO_SUM) \
1644 output_operand (XEXP (addr, 0), 0); \
1645 fputs ("+%lo(", FILE); \
1646 output_address (XEXP (addr, 1)); \
1647 fputc (')', FILE); \
1649 else if (flag_pic && GET_CODE (addr) == CONST \
1650 && GET_CODE (XEXP (addr, 0)) == MINUS \
1651 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1652 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1653 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1655 addr = XEXP (addr, 0); \
1656 output_addr_const (FILE, XEXP (addr, 0)); \
1657 /* Group the args of the second CONST in parenthesis. */ \
1658 fputs ("-(", FILE); \
1659 /* Skip past the second CONST--it does nothing for us. */\
1660 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1661 /* Close the parenthesis. */ \
1662 fputc (')', FILE); \
1666 output_addr_const (FILE, addr); \
1670 /* Declare functions defined in sparc.c and used in templates. */
1672 extern char *singlemove_string ();
1673 extern char *output_move_double ();
1674 extern char *output_move_quad ();
1675 extern char *output_fp_move_double ();
1676 extern char *output_fp_move_quad ();
1677 extern char *output_block_move ();
1678 extern char *output_scc_insn ();
1679 extern char *output_cbranch ();
1680 extern char *output_return ();
1681 extern char *output_floatsisf2 ();
1682 extern char *output_floatsidf2 ();
1683 extern char *output_floatsitf2 ();
1685 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1687 extern int flag_pic
;