1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
26 /* Provide required defaults for linker -e and -d switches. */
29 "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
31 /* Special flags to the Sun-4 assembler when using pipe for input. */
33 #define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}"
35 /* Define macros to distinguish architectures. */
36 #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mv8:-D__sparc_v8__}"
38 /* Prevent error on `-sun4' and `-target sun4' options. */
39 /* This used to translate -dalign to -malign, but that is no good
40 because it can't turn off the usual meaning of making debugging dumps. */
42 #define CC1_SPEC "%{sun4:} %{target:}"
45 /* Sparc ABI says that long double is 4 words.
46 ??? This doesn't work yet. */
47 #define LONG_DOUBLE_TYPE_SIZE 128
50 #define PTRDIFF_TYPE "int"
51 #define SIZE_TYPE "int"
52 #define WCHAR_TYPE "short unsigned int"
53 #define WCHAR_TYPE_SIZE 16
55 /* Omit frame pointer at high optimization levels. */
57 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
61 flag_omit_frame_pointer = 1; \
65 /* These compiler options take an argument. We ignore -target for now. */
67 #define WORD_SWITCH_TAKES_ARG(STR) \
68 (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \
69 || !strcmp (STR, "imacros") || !strcmp (STR, "target") \
70 || !strcmp (STR, "assert") || !strcmp (STR, "aux-info"))
72 /* Names to predefine in the preprocessor for this target machine. */
74 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix"
76 /* Print subsidiary information on the compiler version in use. */
78 #define TARGET_VERSION fprintf (stderr, " (sparc)");
80 /* Generate DBX debugging information. */
82 #define DBX_DEBUGGING_INFO
84 /* Run-time compilation parameters selecting different hardware subsets. */
86 extern int target_flags
;
88 /* Nonzero if we should generate code to use the fpu. */
89 #define TARGET_FPU (target_flags & 1)
91 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
92 use fast return insns, but lose some generality. */
93 #define TARGET_EPILOGUE (target_flags & 2)
95 /* Nonzero means that reference doublewords as if they were guaranteed
96 to be aligned...if they aren't, too bad for the user!
97 Like -dalign in Sun cc. */
98 #define TARGET_HOPE_ALIGN (target_flags & 16)
100 /* Nonzero means make sure all doubles are on 8-byte boundaries.
101 This option results in a calling convention that is incompatible with
102 every other sparc compiler in the world, and thus should only ever be
103 used for experimenting. Also, varargs won't work with it, but it doesn't
104 seem worth trying to fix. */
105 #define TARGET_FORCE_ALIGN (target_flags & 32)
107 /* Nonzero means that we should generate code for a v8 sparc. */
108 #define TARGET_V8 (target_flags & 64)
110 /* Nonzero means that we should generate code for a sparclite. */
111 #define TARGET_SPARCLITE (target_flags & 128)
113 /* Macro to define tables used to set the flags.
114 This is a list in braces of pairs in braces,
115 each pair being { "NAME", VALUE }
116 where VALUE is the bits to set or minus the bits to clear.
117 An empty string NAME is used to identify the default VALUE. */
119 #define TARGET_SWITCHES \
121 {"soft-float", -1}, \
123 {"no-epilogue", -2}, \
124 {"hope-align", 16}, \
125 {"force-align", 48}, \
128 {"sparclite", 128}, \
129 {"no-sparclite", -128}, \
130 { "", TARGET_DEFAULT}}
132 #define TARGET_DEFAULT 3
134 /* target machine storage layout */
136 /* Define this if most significant bit is lowest numbered
137 in instructions that operate on numbered bit-fields. */
138 #define BITS_BIG_ENDIAN 1
140 /* Define this if most significant byte of a word is the lowest numbered. */
141 /* This is true on the SPARC. */
142 #define BYTES_BIG_ENDIAN 1
144 /* Define this if most significant word of a multiword number is the lowest
146 /* Doubles are stored in memory with the high order word first. This
147 matters when cross-compiling. */
148 #define WORDS_BIG_ENDIAN 1
150 /* number of bits in an addressable storage unit */
151 #define BITS_PER_UNIT 8
153 /* Width in bits of a "word", which is the contents of a machine register.
154 Note that this is not necessarily the width of data type `int';
155 if using 16-bit ints on a 68000, this would still be 32.
156 But on a machine with 16-bit registers, this would be 16. */
157 #define BITS_PER_WORD 32
158 #define MAX_BITS_PER_WORD 32
160 /* Width of a word, in units (bytes). */
161 #define UNITS_PER_WORD 4
163 /* Width in bits of a pointer.
164 See also the macro `Pmode' defined below. */
165 #define POINTER_SIZE 32
167 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
168 #define PARM_BOUNDARY 32
170 /* Boundary (in *bits*) on which stack pointer should be aligned. */
171 #define STACK_BOUNDARY 64
173 /* ALIGN FRAMES on double word boundaries */
175 #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
177 /* Allocation boundary (in *bits*) for the code of a function. */
178 #define FUNCTION_BOUNDARY 32
180 /* Alignment of field after `int : 0' in a structure. */
181 #define EMPTY_FIELD_BOUNDARY 32
183 /* Every structure's size must be a multiple of this. */
184 #define STRUCTURE_SIZE_BOUNDARY 8
186 /* A bitfield declared as `int' forces `int' alignment for the struct. */
187 #define PCC_BITFIELD_TYPE_MATTERS 1
189 /* No data type wants to be aligned rounder than this. */
190 #define BIGGEST_ALIGNMENT 64
192 /* The best alignment to use in cases where we have a choice. */
193 #define FASTEST_ALIGNMENT 64
195 /* Make strings word-aligned so strcpy from constants will be faster. */
196 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
197 ((TREE_CODE (EXP) == STRING_CST \
198 && (ALIGN) < FASTEST_ALIGNMENT) \
199 ? FASTEST_ALIGNMENT : (ALIGN))
201 /* Make arrays of chars word-aligned for the same reasons. */
202 #define DATA_ALIGNMENT(TYPE, ALIGN) \
203 (TREE_CODE (TYPE) == ARRAY_TYPE \
204 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
205 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
207 /* Set this nonzero if move instructions will actually fail to work
208 when given unaligned data. */
209 #define STRICT_ALIGNMENT 1
211 /* Things that must be doubleword aligned cannot go in the text section,
212 because the linker fails to align the text section enough!
213 Put them in the data section. */
214 #define MAX_TEXT_ALIGN 32
216 #define SELECT_SECTION(T,RELOC) \
218 if (TREE_CODE (T) == VAR_DECL) \
220 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
221 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
222 && ! (flag_pic && (RELOC))) \
227 else if (TREE_CODE (T) == CONSTRUCTOR) \
229 if (flag_pic != 0 && (RELOC) != 0) \
232 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
234 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
235 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
242 /* Use text section for a constant
243 unless we need more alignment than that offers. */
244 #define SELECT_RTX_SECTION(MODE, X) \
246 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
247 && ! (flag_pic && symbolic_operand (X))) \
253 /* Standard register usage. */
255 /* Number of actual hardware registers.
256 The hardware registers are assigned numbers for the compiler
257 from 0 to just below FIRST_PSEUDO_REGISTER.
258 All registers that the compiler knows about must be given numbers,
259 even those that are not normally considered general registers.
261 SPARC has 32 integer registers and 32 floating point registers. */
263 #define FIRST_PSEUDO_REGISTER 64
265 /* 1 for registers that have pervasive standard uses
266 and are not available for the register allocator.
267 0 is used for the condition code and not to represent %g0, which is
268 hardwired to 0, so reg 0 is *not* fixed.
269 g1 through g4 are free to use as temporaries.
270 g5 through g7 are reserved for the operating system. */
271 #define FIXED_REGISTERS \
272 {0, 0, 0, 0, 0, 1, 1, 1, \
273 0, 0, 0, 0, 0, 0, 1, 0, \
274 0, 0, 0, 0, 0, 0, 0, 0, \
275 0, 0, 0, 0, 0, 0, 1, 1, \
277 0, 0, 0, 0, 0, 0, 0, 0, \
278 0, 0, 0, 0, 0, 0, 0, 0, \
279 0, 0, 0, 0, 0, 0, 0, 0, \
280 0, 0, 0, 0, 0, 0, 0, 0}
282 /* 1 for registers not available across function calls.
283 These must include the FIXED_REGISTERS and also any
284 registers that can be used without being saved.
285 The latter must include the registers where values are returned
286 and the register where structure-value addresses are passed.
287 Aside from that, you can include as many other registers as you like. */
288 #define CALL_USED_REGISTERS \
289 {1, 1, 1, 1, 1, 1, 1, 1, \
290 1, 1, 1, 1, 1, 1, 1, 1, \
291 0, 0, 0, 0, 0, 0, 0, 0, \
292 0, 0, 0, 0, 0, 0, 1, 1, \
294 1, 1, 1, 1, 1, 1, 1, 1, \
295 1, 1, 1, 1, 1, 1, 1, 1, \
296 1, 1, 1, 1, 1, 1, 1, 1, \
297 1, 1, 1, 1, 1, 1, 1, 1}
299 /* Return number of consecutive hard regs needed starting at reg REGNO
300 to hold something of mode MODE.
301 This is ordinarily the length in words of a value of mode MODE
302 but can be less for certain modes in special long registers.
304 On SPARC, ordinary registers hold 32 bits worth;
305 this means both integer and floating point registers.
307 We use vectors to keep this information about registers. */
309 /* How many hard registers it takes to make a register of this mode. */
310 extern int hard_regno_nregs
[];
312 #define HARD_REGNO_NREGS(REGNO, MODE) \
313 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
315 /* Value is 1 if register/mode pair is acceptable on sparc. */
316 extern int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
318 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
319 On SPARC, the cpu registers can hold any mode but the float registers
320 can only hold SFmode or DFmode. See sparc.c for how we
322 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
323 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
325 /* Value is 1 if it is a good idea to tie two pseudo registers
326 when one has mode MODE1 and one has mode MODE2.
327 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
328 for any hard reg, then this must be 0 for correct output. */
329 #define MODES_TIEABLE_P(MODE1, MODE2) \
330 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
332 /* Specify the registers used for certain standard purposes.
333 The values of these macros are register numbers. */
335 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
336 /* #define PC_REGNUM */
338 /* Register to use for pushing function arguments. */
339 #define STACK_POINTER_REGNUM 14
341 /* Actual top-of-stack address is 92 greater than the contents
342 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
343 for the ins and local registers, 4 byte for structure return address, and
344 24 bytes for the 6 register parameters. */
345 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
347 /* Base register for access to local variables of the function. */
348 #define FRAME_POINTER_REGNUM 30
351 /* Register that is used for the return address. */
352 #define RETURN_ADDR_REGNUM 15
355 /* Value should be nonzero if functions must have frame pointers.
356 Zero means the frame pointer need not be set up (and parms
357 may be accessed via the stack pointer) in functions that seem suitable.
358 This is computed in `reload', in reload1.c.
360 Used in flow.c, global-alloc.c, and reload1.c. */
361 extern int leaf_function
;
363 #define FRAME_POINTER_REQUIRED \
364 (! (leaf_function_p () && only_leaf_regs_used ()))
366 /* C statement to store the difference between the frame pointer
367 and the stack pointer values immediately after the function prologue.
369 Note, we always pretend that this is a leaf function because if
370 it's not, there's no point in trying to eliminate the
371 frame pointer. If it is a leaf function, we guessed right! */
372 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
373 do { (VAR) = compute_frame_size (get_frame_size (), 1); } while (0)
375 /* Base register for access to arguments of the function. */
376 #define ARG_POINTER_REGNUM 30
378 /* Register in which static-chain is passed to a function. */
380 #define STATIC_CHAIN_REGNUM 1
382 /* Register which holds offset table for position-independent
385 #define PIC_OFFSET_TABLE_REGNUM 23
387 #define INITIALIZE_PIC initialize_pic ()
388 #define FINALIZE_PIC finalize_pic ()
390 /* Sparc ABI says that quad-precision floats and all structures are returned
391 in memory. We go along regarding floats, but for structures
392 we follow GCC's normal policy. Use -fpcc-struct-value
393 if you want to follow the ABI. */
394 #define RETURN_IN_MEMORY(TYPE) \
395 (TYPE_MODE (TYPE) == TFmode)
397 /* Functions which return large structures get the address
398 to place the wanted value at offset 64 from the frame.
399 Must reserve 64 bytes for the in and local registers. */
400 /* Used only in other #defines in this file. */
401 #define STRUCT_VALUE_OFFSET 64
403 #define STRUCT_VALUE \
404 gen_rtx (MEM, Pmode, \
405 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
406 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
407 #define STRUCT_VALUE_INCOMING \
408 gen_rtx (MEM, Pmode, \
409 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
410 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
412 /* Define the classes of registers for register constraints in the
413 machine description. Also define ranges of constants.
415 One of the classes must always be named ALL_REGS and include all hard regs.
416 If there is more than one class, another class must be named NO_REGS
417 and contain no registers.
419 The name GENERAL_REGS must be the name of a class (or an alias for
420 another name such as ALL_REGS). This is the class of registers
421 that is allowed by "g" or "r" in a register constraint.
422 Also, registers outside this class are allocated only when
423 instructions express preferences for them.
425 The classes must be numbered in nondecreasing order; that is,
426 a larger-numbered class must never be contained completely
427 in a smaller-numbered class.
429 For any two classes, it is very desirable that there be another
430 class that represents their union. */
432 /* The SPARC has two kinds of registers, general and floating point. */
434 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
436 #define N_REG_CLASSES (int) LIM_REG_CLASSES
438 /* Give names of register classes as strings for dump file. */
440 #define REG_CLASS_NAMES \
441 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
443 /* Define which registers fit in which classes.
444 This is an initializer for a vector of HARD_REG_SET
445 of length N_REG_CLASSES. */
447 #if 0 && defined (__GNUC__)
448 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
450 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
453 /* The same information, inverted:
454 Return the class number of the smallest class containing
455 reg number REGNO. This could be a conditional expression
456 or could index an array. */
458 #define REGNO_REG_CLASS(REGNO) \
459 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
461 /* This is the order in which to allocate registers
463 #define REG_ALLOC_ORDER \
464 { 8, 9, 10, 11, 12, 13, 2, 3, \
465 15, 16, 17, 18, 19, 20, 21, 22, \
466 23, 24, 25, 26, 27, 28, 29, 31, \
467 32, 33, 34, 35, 36, 37, 38, 39, \
468 40, 41, 42, 43, 44, 45, 46, 47, \
469 48, 49, 50, 51, 52, 53, 54, 55, \
470 56, 57, 58, 59, 60, 61, 62, 63, \
471 1, 4, 5, 6, 7, 0, 14, 30}
473 /* This is the order in which to allocate registers for
474 leaf functions. If all registers can fit in the "i" registers,
475 then we have the possibility of having a leaf function. */
476 #define REG_LEAF_ALLOC_ORDER \
477 { 2, 3, 24, 25, 26, 27, 28, 29, \
478 15, 8, 9, 10, 11, 12, 13, \
479 16, 17, 18, 19, 20, 21, 22, 23, \
480 32, 33, 34, 35, 36, 37, 38, 39, \
481 40, 41, 42, 43, 44, 45, 46, 47, \
482 48, 49, 50, 51, 52, 53, 54, 55, \
483 56, 57, 58, 59, 60, 61, 62, 63, \
484 1, 4, 5, 6, 7, 0, 14, 30, 31}
486 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
488 #define LEAF_REGISTERS \
489 { 1, 1, 1, 1, 1, 1, 1, 1, \
490 0, 0, 0, 0, 0, 0, 1, 0, \
491 0, 0, 0, 0, 0, 0, 0, 0, \
492 1, 1, 1, 1, 1, 1, 0, 1, \
493 1, 1, 1, 1, 1, 1, 1, 1, \
494 1, 1, 1, 1, 1, 1, 1, 1, \
495 1, 1, 1, 1, 1, 1, 1, 1, \
496 1, 1, 1, 1, 1, 1, 1, 1}
498 extern char leaf_reg_remap
[];
499 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
500 extern char leaf_reg_backmap
[];
501 #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
503 #define REG_USED_SO_FAR(REGNO) \
504 ((REGNO) >= 24 && (REGNO) < 30 \
505 ? (regs_ever_live[24] \
506 || regs_ever_live[25] \
507 || regs_ever_live[26] \
508 || regs_ever_live[27] \
509 || regs_ever_live[28] \
510 || regs_ever_live[29]) : 0)
512 /* The class value for index registers, and the one for base regs. */
513 #define INDEX_REG_CLASS GENERAL_REGS
514 #define BASE_REG_CLASS GENERAL_REGS
516 /* Get reg_class from a letter such as appears in the machine description. */
518 #define REG_CLASS_FROM_LETTER(C) \
519 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
521 /* The letters I, J, K, L and M in a register constraint string
522 can be used to stand for particular ranges of immediate operands.
523 This macro defines what the ranges are.
524 C is the letter, and VALUE is a constant value.
525 Return 1 if VALUE is in the range specified by C.
527 For SPARC, `I' is used for the range of constants an insn
528 can actually contain.
529 `J' is used for the range which is just zero (since that is R0).
530 `K' is used for the 5-bit operand of a compare insns. */
532 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
534 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
535 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
536 : (C) == 'J' ? (VALUE) == 0 \
537 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
540 /* Similar, but for floating constants, and defining letters G and H.
541 Here VALUE is the CONST_DOUBLE rtx itself. */
543 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
544 ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
545 && CONST_DOUBLE_LOW (VALUE) == 0 \
546 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
549 /* Given an rtx X being reloaded into a reg required to be
550 in class CLASS, return the class of reg to actually use.
551 In general this is just CLASS; but on some machines
552 in some cases it is preferable to use a more restrictive class. */
553 /* We can't load constants into FP registers. We can't load any FP constant
554 if an 'E' constraint fails to match it. */
555 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
557 && ((CLASS) == FP_REGS \
558 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
559 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
560 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
563 /* Return the register class of a scratch register needed to load IN into
564 a register of class CLASS in MODE.
566 On the SPARC, when PIC, we need a temporary when loading some addresses
569 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
570 (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS : NO_REGS)
572 /* On SPARC it is not possible to directly move data between
573 GENERAL_REGS and FP_REGS. */
574 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
575 ((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
576 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS))
579 /* Return the maximum number of consecutive registers
580 needed to represent mode MODE in a register of class CLASS. */
581 /* On SPARC, this is the size of MODE in words. */
582 #define CLASS_MAX_NREGS(CLASS, MODE) \
583 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
585 /* Stack layout; function entry, exit and calling. */
587 /* Define the number of register that can hold parameters.
588 These two macros are used only in other macro definitions below. */
591 /* Define this if pushing a word on the stack
592 makes the stack pointer a smaller address. */
593 #define STACK_GROWS_DOWNWARD
595 /* Define this if the nominal address of the stack frame
596 is at the high-address end of the local variables;
597 that is, each additional local variable allocated
598 goes at a more negative offset in the frame. */
599 #define FRAME_GROWS_DOWNWARD
601 /* Offset within stack frame to start allocating local variables at.
602 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
603 first local allocated. Otherwise, it is the offset to the BEGINNING
604 of the first local allocated. */
605 #define STARTING_FRAME_OFFSET (-16)
607 /* If we generate an insn to push BYTES bytes,
608 this says how many the stack pointer really advances by.
609 On SPARC, don't define this because there are no push insns. */
610 /* #define PUSH_ROUNDING(BYTES) */
612 /* Offset of first parameter from the argument pointer register value.
613 This is 64 for the ins and locals, plus 4 for the struct-return reg
614 even if this function isn't going to use it.
615 If TARGET_FORCE_ALIGN, we must reserve 4 more bytes to ensure that the
616 stack remains aligned. */
617 #define FIRST_PARM_OFFSET(FNDECL) \
618 (STRUCT_VALUE_OFFSET + UNITS_PER_WORD + (TARGET_FORCE_ALIGN ? 4 : 0))
620 /* When a parameter is passed in a register, stack space is still
622 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
624 /* Keep the stack pointer constant throughout the function.
625 This is both an optimization and a necessity: longjmp
626 doesn't behave itself when the stack pointer moves within
628 #define ACCUMULATE_OUTGOING_ARGS
630 /* Value is the number of bytes of arguments automatically
631 popped when returning from a subroutine call.
632 FUNTYPE is the data type of the function (as a tree),
633 or for a library call it is an identifier node for the subroutine name.
634 SIZE is the number of bytes of arguments passed on the stack. */
636 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
638 /* Some subroutine macros specific to this machine. */
639 #define BASE_RETURN_VALUE_REG(MODE) \
640 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8)
641 #define BASE_OUTGOING_VALUE_REG(MODE) \
642 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24)
643 #define BASE_PASSING_ARG_REG(MODE) (8)
644 #define BASE_INCOMING_ARG_REG(MODE) (24)
646 /* Define how to find the value returned by a function.
647 VALTYPE is the data type of the value (as a tree).
648 If the precise function being called is known, FUNC is its FUNCTION_DECL;
649 otherwise, FUNC is 0. */
651 /* On SPARC the value is found in the first "output" register. */
653 #define FUNCTION_VALUE(VALTYPE, FUNC) \
654 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
656 /* But the called function leaves it in the first "input" register. */
658 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
659 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
661 /* Define how to find the value returned by a library function
662 assuming the value has mode MODE. */
664 #define LIBCALL_VALUE(MODE) \
665 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
667 /* 1 if N is a possible register number for a function value
668 as seen by the caller.
669 On SPARC, the first "output" reg is used for integer values,
670 and the first floating point register is used for floating point values. */
672 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
674 /* 1 if N is a possible register number for function argument passing.
675 On SPARC, these are the "output" registers. */
677 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
679 /* Define a data type for recording info about an argument list
680 during the scan of that argument list. This data type should
681 hold all necessary information about the function itself
682 and about the args processed so far, enough to enable macros
683 such as FUNCTION_ARG to determine where the next arg should go.
685 On SPARC, this is a single integer, which is a number of words
686 of arguments scanned so far (including the invisible argument,
687 if any, which holds the structure-value-address).
688 Thus 7 or more means all following args should go on the stack. */
690 #define CUMULATIVE_ARGS int
692 #define ROUND_ADVANCE(SIZE) \
693 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
695 /* Round a register number up to a proper boundary for an arg of mode MODE.
696 Note that we need an odd/even pair for a two-word arg,
697 since that will become 8-byte aligned when stored in memory. */
698 #define ROUND_REG(X, MODE) \
699 (TARGET_FORCE_ALIGN && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
700 ? ((X) + ! ((X) & 1)) : (X))
702 /* Initialize a variable CUM of type CUMULATIVE_ARGS
703 for a call to a function whose data type is FNTYPE.
704 For a library call, FNTYPE is 0.
706 On SPARC, the offset always starts at 0: the first parm reg is always
709 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
711 /* Update the data in CUM to advance over an argument
712 of mode MODE and data type TYPE.
713 (TYPE is null for libcalls where that information may not be available.) */
715 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
716 ((CUM) = (ROUND_REG ((CUM), (MODE)) \
717 + ((MODE) != BLKmode \
718 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
719 : ROUND_ADVANCE (int_size_in_bytes (TYPE)))))
721 /* Determine where to put an argument to a function.
722 Value is zero to push the argument on the stack,
723 or a hard register in which to store the argument.
725 MODE is the argument's machine mode.
726 TYPE is the data type of the argument (as a tree).
727 This is null for libcalls where that information may
729 CUM is a variable of type CUMULATIVE_ARGS which gives info about
730 the preceding args and about the function being called.
731 NAMED is nonzero if this argument is a named parameter
732 (otherwise it is an extra parameter matching an ellipsis). */
734 /* On SPARC the first six args are normally in registers
735 and the rest are pushed. Any arg that starts within the first 6 words
736 is at least partially passed in a register unless its data type forbids. */
738 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
739 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
740 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
741 && ((TYPE)==0 || (MODE) != BLKmode \
742 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
743 ? gen_rtx (REG, (MODE), \
744 (BASE_PASSING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
747 /* Define where a function finds its arguments.
748 This is different from FUNCTION_ARG because of register windows. */
750 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
751 (ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
752 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
753 && ((TYPE)==0 || (MODE) != BLKmode \
754 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
755 ? gen_rtx (REG, (MODE), \
756 (BASE_INCOMING_ARG_REG (MODE) + ROUND_REG ((CUM), (MODE)))) \
759 /* For an arg passed partly in registers and partly in memory,
760 this is the number of registers used.
761 For args passed entirely in registers or entirely in memory, zero.
762 Any arg that starts in the first 6 regs but won't entirely fit in them
763 needs partial registers on the Sparc. */
765 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
766 ((ROUND_REG ((CUM), (MODE)) < NPARM_REGS \
767 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
768 && ((TYPE)==0 || (MODE) != BLKmode \
769 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
770 && (ROUND_REG ((CUM), (MODE)) \
771 + ((MODE) == BLKmode \
772 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
773 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
774 ? (NPARM_REGS - ROUND_REG ((CUM), (MODE))) \
777 /* The SPARC ABI stipulates passing struct arguments (of any size) and
778 quad-precision floats by invisible reference. */
779 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
780 ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
781 || TREE_CODE (TYPE) == UNION_TYPE)) \
784 /* If defined, a C expression that gives the alignment boundary, in
785 bits, of an argument with the specified mode and type. If it is
786 not defined, `PARM_BOUNDARY' is used for all arguments.
788 This definition does nothing special unless TARGET_FORCE_ALIGN;
789 in that case, it aligns each arg to the natural boundary. */
791 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
792 (! TARGET_FORCE_ALIGN \
795 ? (TYPE_ALIGN (TYPE) <= PARM_BOUNDARY \
797 : TYPE_ALIGN (TYPE)) \
798 : (GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY \
800 : GET_MODE_ALIGNMENT (MODE))))
802 /* Define the information needed to generate branch and scc insns. This is
803 stored from the compare operation. Note that we can't use "rtx" here
804 since it hasn't been defined! */
806 extern struct rtx_def
*sparc_compare_op0
, *sparc_compare_op1
;
808 /* Define the function that build the compare insn for scc and bcc. */
810 extern struct rtx_def
*gen_compare_reg ();
812 /* Generate the special assembly code needed to tell the assembler whatever
813 it might need to know about the return value of a function.
815 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
816 information to the assembler relating to peephole optimization (done in
819 #define ASM_DECLARE_RESULT(FILE, RESULT) \
820 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
822 /* Output the label for a function definition. */
824 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
826 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
827 ASM_OUTPUT_LABEL (FILE, NAME); \
830 /* Two views of the size of the current frame. */
831 extern int actual_fsize
;
832 extern int apparent_fsize
;
834 /* This macro generates the assembly code for function entry.
835 FILE is a stdio stream to output the code to.
836 SIZE is an int: how many units of temporary storage to allocate.
837 Refer to the array `regs_ever_live' to determine which registers
838 to save; `regs_ever_live[I]' is nonzero if register number I
839 is ever used in the function. This macro is responsible for
840 knowing which registers should not be saved even if used. */
842 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
843 of memory. If any fpu reg is used in the function, we allocate
844 such a block here, at the bottom of the frame, just in case it's needed.
846 If this function is a leaf procedure, then we may choose not
847 to do a "save" insn. The decision about whether or not
848 to do this is made in regclass.c. */
850 #define FUNCTION_PROLOGUE(FILE, SIZE) \
851 output_function_prologue (FILE, SIZE, leaf_function)
853 /* Output assembler code to FILE to increment profiler label # LABELNO
854 for profiling a function entry. */
856 #define FUNCTION_PROFILER(FILE, LABELNO) \
858 fputs ("\tsethi %hi(", (FILE)); \
859 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
860 fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \
861 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
862 fputs ("),%o0,%o0\n", (FILE)); \
865 /* Output assembler code to FILE to initialize this source file's
866 basic block profiling info, if that has not already been done. */
867 /* FIXME -- this does not parameterize how it generates labels (like the
868 above FUNCTION_PROFILER). Broken on Solaris-2. --gnu@cygnus.com */
870 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
871 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
872 (LABELNO), (LABELNO))
874 /* Output assembler code to FILE to increment the entry-count for
875 the BLOCKNO'th basic block in this source file. */
877 #define BLOCK_PROFILER(FILE, BLOCKNO) \
879 int blockn = (BLOCKNO); \
880 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
881 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
882 4 * blockn, 4 * blockn, 4 * blockn); \
885 /* Output rtl to increment the entry-count for the LABELNO'th instrumented
886 arc in this source file. */
888 #define ARC_PROFILER(ARCNO, INSERT_AFTER) \
889 output_arc_profiler (ARCNO, INSERT_AFTER)
891 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
892 the stack pointer does not matter. The value is tested only in
893 functions that have frame pointers.
894 No definition is equivalent to always zero. */
896 extern int current_function_calls_alloca
;
897 extern int current_function_outgoing_args_size
;
899 #define EXIT_IGNORE_STACK \
900 (get_frame_size () != 0 \
901 || current_function_calls_alloca || current_function_outgoing_args_size)
903 /* This macro generates the assembly code for function exit,
904 on machines that need it. If FUNCTION_EPILOGUE is not defined
905 then individual return instructions are generated for each
906 return statement. Args are same as for FUNCTION_PROLOGUE.
908 The function epilogue should not depend on the current stack pointer!
909 It should use the frame pointer only. This is mandatory because
910 of alloca; we also take advantage of it to omit stack adjustments
913 /* This declaration is needed due to traditional/ANSI
914 incompatibilities which cannot be #ifdefed away
915 because they occur inside of macros. Sigh. */
916 extern union tree_node
*current_function_decl
;
918 #define FUNCTION_EPILOGUE(FILE, SIZE) \
919 output_function_epilogue (FILE, SIZE, leaf_function)
921 #define DELAY_SLOTS_FOR_EPILOGUE 1
922 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
923 eligible_for_epilogue_delay (trial, slots_filled)
925 /* Output assembler code for a block containing the constant parts
926 of a trampoline, leaving space for the variable parts. */
928 /* On the sparc, the trampoline contains five instructions:
929 sethi #TOP_OF_FUNCTION,%g2
930 or #BOTTOM_OF_FUNCTION,%g2,%g2
931 sethi #TOP_OF_STATIC,%g1
933 or #BOTTOM_OF_STATIC,%g1,%g1 */
934 #define TRAMPOLINE_TEMPLATE(FILE) \
936 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
937 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
938 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
939 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
940 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
943 /* Length in units of the trampoline for entering a nested function. */
945 #define TRAMPOLINE_SIZE 20
947 /* Emit RTL insns to initialize the variable parts of a trampoline.
948 FNADDR is an RTX for the address of the function's pure code.
949 CXT is an RTX for the static chain value for the function.
951 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
952 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
953 (to store insns). This is a bit excessive. Perhaps a different
954 mechanism would be better here. */
956 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
958 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
959 size_int (10), 0, 1); \
960 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
961 size_int (10), 0, 1); \
962 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
963 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
964 rtx g1_sethi = gen_rtx (HIGH, SImode, \
965 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
966 rtx g2_sethi = gen_rtx (HIGH, SImode, \
967 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
968 rtx g1_ori = gen_rtx (HIGH, SImode, \
969 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
970 rtx g2_ori = gen_rtx (HIGH, SImode, \
971 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
972 rtx tem = gen_reg_rtx (SImode); \
973 emit_move_insn (tem, g2_sethi); \
974 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
975 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
976 emit_move_insn (tem, g2_ori); \
977 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
978 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
979 emit_move_insn (tem, g1_sethi); \
980 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
981 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
982 emit_move_insn (tem, g1_ori); \
983 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
984 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
987 /* Emit code for a call to builtin_saveregs. We must emit USE insns which
988 reference the 6 input registers. Ordinarily they are not call used
989 registers, but they are for _builtin_saveregs, so we must make this
992 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) \
993 (emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, TImode, 24))), \
994 emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, DImode, 28))), \
995 expand_call (exp, target, ignore))
997 /* Addressing modes, and classification of registers for them. */
999 /* #define HAVE_POST_INCREMENT */
1000 /* #define HAVE_POST_DECREMENT */
1002 /* #define HAVE_PRE_DECREMENT */
1003 /* #define HAVE_PRE_INCREMENT */
1005 /* Macros to check register numbers against specific register classes. */
1007 /* These assume that REGNO is a hard or pseudo reg number.
1008 They give nonzero only if REGNO is a hard reg of the suitable class
1009 or a pseudo reg currently allocated to a suitable hard reg.
1010 Since they use reg_renumber, they are safe only once reg_renumber
1011 has been allocated, which happens in local-alloc.c. */
1013 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1014 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1015 #define REGNO_OK_FOR_BASE_P(REGNO) \
1016 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1017 #define REGNO_OK_FOR_FP_P(REGNO) \
1018 (((REGNO) ^ 0x20) < 32 \
1019 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1021 /* Now macros that check whether X is a register and also,
1022 strictly, whether it is in a specified class.
1024 These macros are specific to the SPARC, and may be used only
1025 in code for printing assembler insns and in conditions for
1026 define_optimization. */
1028 /* 1 if X is an fp register. */
1030 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1032 /* Maximum number of registers that can appear in a valid memory address. */
1034 #define MAX_REGS_PER_ADDRESS 2
1036 /* Recognize any constant value that is a valid address. */
1038 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
1040 /* Nonzero if the constant value X is a legitimate general operand.
1041 Anything can be made to work except floating point constants. */
1043 #define LEGITIMATE_CONSTANT_P(X) \
1044 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1046 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1047 and check its validity for a certain class.
1048 We have two alternate definitions for each of them.
1049 The usual definition accepts all pseudo regs; the other rejects
1050 them unless they have been allocated suitable hard regs.
1051 The symbol REG_OK_STRICT causes the latter definition to be used.
1053 Most source files want to accept pseudo regs in the hope that
1054 they will get allocated to the class that the insn wants them to be in.
1055 Source files for reload pass need to be strict.
1056 After reload, it makes no difference, since pseudo regs have
1057 been eliminated by then. */
1059 /* Optional extra constraints for this machine. Borrowed from romp.h.
1061 For the SPARC, `Q' means that this is a memory operand but not a
1062 symbolic memory operand. Note that an unassigned pseudo register
1063 is such a memory operand. Needed because reload will generate
1064 these things in insns and then not re-recognize the insns, causing
1065 constrain_operands to fail.
1067 `R' handles the LO_SUM which can be an address for `Q'.
1069 `S' handles constraints for calls. */
1071 #ifndef REG_OK_STRICT
1073 /* Nonzero if X is a hard reg that can be used as an index
1074 or if it is a pseudo reg. */
1075 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1076 /* Nonzero if X is a hard reg that can be used as a base reg
1077 or if it is a pseudo reg. */
1078 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1080 #define EXTRA_CONSTRAINT(OP, C) \
1082 ? ((GET_CODE (OP) == MEM \
1083 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1084 && ! symbolic_memory_operand (OP, VOIDmode)) \
1085 || (reload_in_progress && GET_CODE (OP) == REG \
1086 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1088 ? (GET_CODE (OP) == LO_SUM \
1089 && GET_CODE (XEXP (OP, 0)) == REG \
1090 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1092 ? (CONSTANT_P (OP) || memory_address_p (Pmode, OP)) \
1094 ? (mem_aligned_8 (OP)) \
1096 ? (register_ok_for_ldd (OP)) \
1101 /* Nonzero if X is a hard reg that can be used as an index. */
1102 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1103 /* Nonzero if X is a hard reg that can be used as a base reg. */
1104 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1106 #define EXTRA_CONSTRAINT(OP, C) \
1108 (GET_CODE (OP) == REG ? \
1109 (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1110 && reg_renumber[REGNO (OP)] < 0) \
1111 : GET_CODE (OP) == MEM) \
1113 (GET_CODE (OP) == LO_SUM \
1114 && GET_CODE (XEXP (OP, 0)) == REG \
1115 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1117 ? (CONSTANT_P (OP) \
1118 || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\
1119 || strict_memory_address_p (Pmode, OP)) \
1121 mem_aligned_8 (OP) && strict_memory_address_p (Pmode, OP) \
1123 register_ok_for_ldd (OP) : 0)))))
1126 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1127 that is a valid memory address for an instruction.
1128 The MODE argument is the machine mode for the MEM expression
1129 that wants to use this address.
1131 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1132 ordinarily. This changes a bit when generating PIC.
1134 If you change this, execute "rm explow.o recog.o reload.o". */
1136 #define RTX_OK_FOR_BASE_P(X) \
1137 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1138 || (GET_CODE (X) == SUBREG \
1139 && GET_CODE (SUBREG_REG (X)) == REG \
1140 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1142 #define RTX_OK_FOR_INDEX_P(X) \
1143 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1144 || (GET_CODE (X) == SUBREG \
1145 && GET_CODE (SUBREG_REG (X)) == REG \
1146 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1148 #define RTX_OK_FOR_OFFSET_P(X) \
1149 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1151 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1152 { if (RTX_OK_FOR_BASE_P (X)) \
1154 else if (GET_CODE (X) == PLUS) \
1156 register rtx op0 = XEXP (X, 0); \
1157 register rtx op1 = XEXP (X, 1); \
1158 if (flag_pic && op0 == pic_offset_table_rtx) \
1160 if (RTX_OK_FOR_BASE_P (op1)) \
1162 else if (flag_pic == 1 \
1163 && GET_CODE (op1) != REG \
1164 && GET_CODE (op1) != LO_SUM \
1165 && GET_CODE (op1) != MEM) \
1168 else if (RTX_OK_FOR_BASE_P (op0)) \
1170 if (RTX_OK_FOR_INDEX_P (op1) \
1171 || RTX_OK_FOR_OFFSET_P (op1)) \
1174 else if (RTX_OK_FOR_BASE_P (op1)) \
1176 if (RTX_OK_FOR_INDEX_P (op0) \
1177 || RTX_OK_FOR_OFFSET_P (op0)) \
1181 else if (GET_CODE (X) == LO_SUM) \
1183 register rtx op0 = XEXP (X, 0); \
1184 register rtx op1 = XEXP (X, 1); \
1185 if (RTX_OK_FOR_BASE_P (op0) \
1186 && CONSTANT_P (op1)) \
1189 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1193 /* Try machine-dependent ways of modifying an illegitimate address
1194 to be legitimate. If we find one, return the new, valid address.
1195 This macro is used in only one place: `memory_address' in explow.c.
1197 OLDX is the address as it was before break_out_memory_refs was called.
1198 In some cases it is useful to look at this to decide what needs to be done.
1200 MODE and WIN are passed so that this macro can use
1201 GO_IF_LEGITIMATE_ADDRESS.
1203 It is always safe for this macro to do nothing. It exists to recognize
1204 opportunities to optimize the output. */
1206 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1207 extern struct rtx_def
*legitimize_pic_address ();
1208 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1209 { rtx sparc_x = (X); \
1210 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1211 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1212 force_operand (XEXP (X, 0), 0)); \
1213 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1214 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1215 force_operand (XEXP (X, 1), 0)); \
1216 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1217 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), 0),\
1219 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1220 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1221 force_operand (XEXP (X, 1), 0)); \
1222 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1224 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1225 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1226 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1227 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1228 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1229 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1230 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1231 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1232 || GET_CODE (X) == LABEL_REF) \
1233 (X) = gen_rtx (LO_SUM, Pmode, \
1234 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1235 if (memory_address_p (MODE, X)) \
1238 /* Go to LABEL if ADDR (a legitimate address expression)
1239 has an effect that depends on the machine mode it is used for.
1240 On the SPARC this is never true. */
1242 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1244 /* Specify the machine mode that this machine uses
1245 for the index in the tablejump instruction. */
1246 #define CASE_VECTOR_MODE SImode
1248 /* Define this if the tablejump instruction expects the table
1249 to contain offsets from the address of the table.
1250 Do not define this if the table should contain absolute addresses. */
1251 /* #define CASE_VECTOR_PC_RELATIVE */
1253 /* Specify the tree operation to be used to convert reals to integers. */
1254 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1256 /* This is the kind of divide that is easiest to do in the general case. */
1257 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1259 /* Define this as 1 if `char' should by default be signed; else as 0. */
1260 #define DEFAULT_SIGNED_CHAR 1
1262 /* Max number of bytes we can move from memory to memory
1263 in one reasonably fast instruction. */
1266 /* This is the value of the error code EDOM for this machine,
1267 used by the sqrt instruction. */
1268 #define TARGET_EDOM 33
1270 /* This is how to refer to the variable errno. */
1271 #define GEN_ERRNO_RTX \
1272 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
1274 /* Define if normal loads of shorter-than-word items from memory clears
1275 the rest of the bigs in the register. */
1276 #define BYTE_LOADS_ZERO_EXTEND
1278 /* Nonzero if access to memory by bytes is slow and undesirable.
1279 For RISC chips, it means that access to memory by bytes is no
1280 better than access by words when possible, so grab a whole word
1281 and maybe make use of that. */
1282 #define SLOW_BYTE_ACCESS 1
1284 /* We assume that the store-condition-codes instructions store 0 for false
1285 and some other value for true. This is the value stored for true. */
1287 #define STORE_FLAG_VALUE 1
1289 /* When a prototype says `char' or `short', really pass an `int'. */
1290 #define PROMOTE_PROTOTYPES
1292 /* Define if shifts truncate the shift count
1293 which implies one can omit a sign-extension or zero-extension
1294 of a shift count. */
1295 #define SHIFT_COUNT_TRUNCATED
1297 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1298 is done just by pretending it is already truncated. */
1299 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1301 /* Specify the machine mode that pointers have.
1302 After generation of rtl, the compiler makes no further distinction
1303 between pointers and any other objects of this machine mode. */
1304 #define Pmode SImode
1306 /* Generate calls to memcpy, memcmp and memset. */
1307 #define TARGET_MEM_FUNCTIONS
1309 /* Add any extra modes needed to represent the condition code.
1311 On the Sparc, we have a "no-overflow" mode which is used when an add or
1312 subtract insn is used to set the condition code. Different branches are
1313 used in this case for some operations.
1315 We also have two modes to indicate that the relevant condition code is
1316 in the floating-point condition code register. One for comparisons which
1317 will generate an exception if the result is unordered (CCFPEmode) and
1318 one for comparisons which will never trap (CCFPmode). This really should
1319 be a separate register, but we don't want to go to 65 registers. */
1320 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1322 /* Define the names for the modes specified above. */
1323 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1325 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1326 return the mode to be used for the comparison. For floating-point,
1327 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1328 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1330 #define SELECT_CC_MODE(OP,X,Y) \
1331 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1332 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1333 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1334 ? CC_NOOVmode : CCmode))
1336 /* A function address in a call instruction
1337 is a byte address (for indexing purposes)
1338 so give the MEM rtx a byte's mode. */
1339 #define FUNCTION_MODE SImode
1341 /* Define this if addresses of constant functions
1342 shouldn't be put through pseudo regs where they can be cse'd.
1343 Desirable on machines where ordinary constants are expensive
1344 but a CALL with constant address is cheap. */
1345 #define NO_FUNCTION_CSE
1347 /* alloca should avoid clobbering the old register save area. */
1348 #define SETJMP_VIA_SAVE_AREA
1350 /* Define subroutines to call to handle multiply and divide.
1351 Use the subroutines that Sun's library provides.
1352 The `*' prevents an underscore from being prepended by the compiler. */
1354 #define DIVSI3_LIBCALL "*.div"
1355 #define UDIVSI3_LIBCALL "*.udiv"
1356 #define MODSI3_LIBCALL "*.rem"
1357 #define UMODSI3_LIBCALL "*.urem"
1358 /* .umul is a little faster than .mul. */
1359 #define MULSI3_LIBCALL "*.umul"
1361 /* Compute the cost of computing a constant rtl expression RTX
1362 whose rtx-code is CODE. The body of this macro is a portion
1363 of a switch statement. If the code is computed here,
1364 return it with a return statement. Otherwise, break from the switch. */
1366 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1368 if (INTVAL (RTX) == 0) \
1370 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1378 case CONST_DOUBLE: \
1379 if (GET_MODE (RTX) == DImode) \
1380 if ((XINT (RTX, 3) == 0 \
1381 && (unsigned) XINT (RTX, 2) < 0x1000) \
1382 || (XINT (RTX, 3) == -1 \
1383 && XINT (RTX, 2) < 0 \
1384 && XINT (RTX, 2) >= -0x1000)) \
1388 /* SPARC offers addressing modes which are "as cheap as a register".
1389 See sparc.c (or gcc.texinfo) for details. */
1391 #define ADDRESS_COST(RTX) \
1392 (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1394 /* Compute extra cost of moving data between one register class
1396 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1397 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1398 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1400 /* Provide the costs of a rtl expression. This is in the body of a
1401 switch on CODE. The purpose for the cost of MULT is to encourage
1402 `synth_mult' to find a synthetic multiply when reasonable.
1404 If we need more than 12 insns to do a multiply, then go out-of-line,
1405 since the call overhead will be < 10% of the cost of the multiply. */
1407 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1409 return COSTS_N_INSNS (25); \
1414 return COSTS_N_INSNS (20); \
1415 /* Make FLOAT more expensive than CONST_DOUBLE, \
1416 so that cse will favor the latter. */ \
1420 /* Conditional branches with empty delay slots have a length of two. */
1421 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1422 if (GET_CODE (INSN) == CALL_INSN \
1423 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1426 /* Control the assembler format that we output. */
1428 /* Output at beginning of assembler file. */
1430 #define ASM_FILE_START(file)
1432 /* Output to assembler file text saying following lines
1433 may contain character constants, extra white space, comments, etc. */
1435 #define ASM_APP_ON ""
1437 /* Output to assembler file text saying following lines
1438 no longer contain unusual constructs. */
1440 #define ASM_APP_OFF ""
1442 #define ASM_LONG ".word"
1443 #define ASM_SHORT ".half"
1444 #define ASM_BYTE_OP ".byte"
1446 /* Output before read-only data. */
1448 #define TEXT_SECTION_ASM_OP ".text"
1450 /* Output before writable data. */
1452 #define DATA_SECTION_ASM_OP ".data"
1454 /* How to refer to registers in assembler output.
1455 This sequence is indexed by compiler's hard-register-number (see above). */
1457 #define REGISTER_NAMES \
1458 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1459 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1460 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1461 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1462 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1463 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1464 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1465 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1467 /* Define additional names for use in asm clobbers and asm declarations.
1469 We define the fake Condition Code register as an alias for reg 0 (which
1470 is our `condition code' register), so that condition codes can easily
1471 be clobbered by an asm. No such register actually exists. Condition
1472 codes are partly stored in the PSR and partly in the FSR. */
1474 #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1476 /* How to renumber registers for dbx and gdb. */
1478 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1480 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1481 since the length can run past this up to a continuation point. */
1482 #define DBX_CONTIN_LENGTH 1500
1484 /* This is how to output a note to DBX telling it the line number
1485 to which the following sequence of instructions corresponds.
1487 This is needed for SunOS 4.0, and should not hurt for 3.2
1489 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1490 { static int sym_lineno = 1; \
1491 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1492 line, sym_lineno, sym_lineno); \
1495 /* This is how to output the definition of a user-level label named NAME,
1496 such as the label on a static function or variable NAME. */
1498 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1499 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1501 /* This is how to output a command to make the user-level label named NAME
1502 defined for reference from other files. */
1504 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1505 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1507 /* This is how to output a reference to a user-level label named NAME.
1508 `assemble_name' uses this. */
1510 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1511 fprintf (FILE, "_%s", NAME)
1513 /* This is how to output a definition of an internal numbered label where
1514 PREFIX is the class of label and NUM is the number within the class. */
1516 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1517 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1519 /* This is how to output a reference to an internal numbered label where
1520 PREFIX is the class of label and NUM is the number within the class. */
1521 /* FIXME: This should be used throughout gcc, and documented in the texinfo
1522 files. There is no reason you should have to allocate a buffer and
1523 `sprintf' to reference an internal label (as opposed to defining it). */
1525 #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
1526 fprintf (FILE, "%s%d", PREFIX, NUM)
1528 /* This is how to store into the string LABEL
1529 the symbol_ref name of an internal numbered label where
1530 PREFIX is the class of label and NUM is the number within the class.
1531 This is suitable for output with `assemble_name'. */
1533 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1534 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1536 /* This is how to output an assembler line defining a `double' constant. */
1538 /* Assemblers (both gas 1.35 and as in 4.0.3)
1539 seem to treat -0.0 as if it were 0.0.
1540 They reject 99e9999, but accept inf. */
1541 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1543 if (REAL_VALUE_ISINF (VALUE) \
1544 || REAL_VALUE_ISNAN (VALUE) \
1545 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1548 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1549 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1550 ASM_LONG, t[0], ASM_LONG, t[1]); \
1553 fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1556 /* This is how to output an assembler line defining a `float' constant. */
1558 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1560 if (REAL_VALUE_ISINF (VALUE) \
1561 || REAL_VALUE_ISNAN (VALUE) \
1562 || REAL_VALUE_MINUS_ZERO (VALUE)) \
1565 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1566 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
1569 fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1572 /* This is how to output an assembler line defining an `int' constant. */
1574 #define ASM_OUTPUT_INT(FILE,VALUE) \
1575 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
1576 output_addr_const (FILE, (VALUE)), \
1577 fprintf (FILE, "\n"))
1579 /* This is how to output an assembler line defining a DImode constant. */
1580 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1581 output_double_int (FILE, VALUE)
1583 /* Likewise for `char' and `short' constants. */
1585 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1586 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
1587 output_addr_const (FILE, (VALUE)), \
1588 fprintf (FILE, "\n"))
1590 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1591 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
1592 output_addr_const (FILE, (VALUE)), \
1593 fprintf (FILE, "\n"))
1595 /* This is how to output an assembler line for a numeric constant byte. */
1597 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1598 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
1600 /* This is how to output an element of a case-vector that is absolute. */
1602 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1605 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1606 fprintf (FILE, "\t.word\t"); \
1607 assemble_name (FILE, label); \
1608 fprintf (FILE, "\n"); \
1611 /* This is how to output an element of a case-vector that is relative.
1612 (SPARC uses such vectors only when generating PIC.) */
1614 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1617 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1618 fprintf (FILE, "\t.word\t"); \
1619 assemble_name (FILE, label); \
1620 fprintf (FILE, "-1b\n"); \
1623 /* This is how to output an assembler line
1624 that says to advance the location counter
1625 to a multiple of 2**LOG bytes. */
1627 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1629 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1631 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1632 fprintf (FILE, "\t.skip %u\n", (SIZE))
1634 /* This says how to output an assembler line
1635 to define a global common symbol. */
1637 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1638 ( fputs ("\t.global ", (FILE)), \
1639 assemble_name ((FILE), (NAME)), \
1640 fputs ("\n\t.common ", (FILE)), \
1641 assemble_name ((FILE), (NAME)), \
1642 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1644 /* This says how to output an assembler line
1645 to define a local common symbol. */
1647 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1648 ( fputs ("\n\t.reserve ", (FILE)), \
1649 assemble_name ((FILE), (NAME)), \
1650 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1652 /* Store in OUTPUT a string (made with alloca) containing
1653 an assembler-name for a local static variable named NAME.
1654 LABELNO is an integer which is different for each call. */
1656 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1657 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1658 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1660 /* Define the parentheses used to group arithmetic operations
1661 in assembler code. */
1663 #define ASM_OPEN_PAREN "("
1664 #define ASM_CLOSE_PAREN ")"
1666 /* Define results of standard character escape sequences. */
1667 #define TARGET_BELL 007
1668 #define TARGET_BS 010
1669 #define TARGET_TAB 011
1670 #define TARGET_NEWLINE 012
1671 #define TARGET_VT 013
1672 #define TARGET_FF 014
1673 #define TARGET_CR 015
1675 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1676 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' \
1679 /* Print operand X (an rtx) in assembler syntax to file FILE.
1680 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1681 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1683 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1685 /* Print a memory address as an operand to reference that memory location. */
1687 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1688 { register rtx base, index = 0; \
1690 register rtx addr = ADDR; \
1691 if (GET_CODE (addr) == REG) \
1692 fputs (reg_names[REGNO (addr)], FILE); \
1693 else if (GET_CODE (addr) == PLUS) \
1695 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1696 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1697 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1698 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1700 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1701 fputs (reg_names[REGNO (base)], FILE); \
1703 fprintf (FILE, "%+d", offset); \
1704 else if (GET_CODE (index) == REG) \
1705 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1706 else if (GET_CODE (index) == SYMBOL_REF) \
1707 fputc ('+', FILE), output_addr_const (FILE, index); \
1710 else if (GET_CODE (addr) == MINUS \
1711 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1713 output_addr_const (FILE, XEXP (addr, 0)); \
1714 fputs ("-(", FILE); \
1715 output_addr_const (FILE, XEXP (addr, 1)); \
1716 fputs ("-.)", FILE); \
1718 else if (GET_CODE (addr) == LO_SUM) \
1720 output_operand (XEXP (addr, 0), 0); \
1721 fputs ("+%lo(", FILE); \
1722 output_address (XEXP (addr, 1)); \
1723 fputc (')', FILE); \
1725 else if (flag_pic && GET_CODE (addr) == CONST \
1726 && GET_CODE (XEXP (addr, 0)) == MINUS \
1727 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1728 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1729 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1731 addr = XEXP (addr, 0); \
1732 output_addr_const (FILE, XEXP (addr, 0)); \
1733 /* Group the args of the second CONST in parenthesis. */ \
1734 fputs ("-(", FILE); \
1735 /* Skip past the second CONST--it does nothing for us. */\
1736 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1737 /* Close the parenthesis. */ \
1738 fputc (')', FILE); \
1742 output_addr_const (FILE, addr); \
1746 /* Declare functions defined in sparc.c and used in templates. */
1748 extern char *singlemove_string ();
1749 extern char *output_move_double ();
1750 extern char *output_move_quad ();
1751 extern char *output_fp_move_double ();
1752 extern char *output_fp_move_quad ();
1753 extern char *output_block_move ();
1754 extern char *output_scc_insn ();
1755 extern char *output_cbranch ();
1756 extern char *output_return ();
1758 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1760 extern int flag_pic
;