1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg}"
26 /* Provide required defaults for linker -e and -d switches.
27 Also, it is hard to debug with shared libraries,
28 so don't use them if going to debug. */
30 #define LINK_SPEC "%{!e*:-e start} -dc -dp %{static:-Bstatic} %{assert*}"
32 /* Special flags to the Sun-4 assembler when using pipe for input. */
34 #define ASM_SPEC " %{pipe:-} %{fpic:-k} %{fPIC:-k}"
36 /* Prevent error on `-dalign', `-sun4' and `-target sun4' options. */
37 /* Also, make it easy to specify interesting optimization options. */
39 #define CC1_SPEC "%{dalign:-malign} %{sun4:} %{target:}"
41 #define PTRDIFF_TYPE "int"
42 #define SIZE_TYPE "int"
43 #define WCHAR_TYPE "short unsigned int"
44 #define WCHAR_TYPE_SIZE 16
46 /* Omit frame pointer and enable caller-saves at high optimization levels. */
48 #define OPTIMIZATION_OPTIONS(OPTIMIZE) \
52 flag_omit_frame_pointer = 1; \
53 flag_caller_saves = 1; \
57 /* These compiler options take an argument. We ignore -target for now. */
59 #define WORD_SWITCH_TAKES_ARG(STR) \
60 (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \
61 || !strcmp (STR, "imacros") || !strcmp (STR, "target") \
62 || !strcmp (STR, "assert"))
64 /* Names to predefine in the preprocessor for this target machine. */
66 #define CPP_PREDEFINES "-Dsparc -Dsun -Dunix"
68 /* Print subsidiary information on the compiler version in use. */
70 #define TARGET_VERSION fprintf (stderr, " (sparc)");
72 /* Generate DBX debugging information. */
74 #define DBX_DEBUGGING_INFO
76 /* Run-time compilation parameters selecting different hardware subsets. */
78 extern int target_flags
;
80 /* Nonzero if we should generate code to use the fpu. */
81 #define TARGET_FPU (target_flags & 1)
83 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
84 use fast return insns, but lose some generality. */
85 #define TARGET_EPILOGUE (target_flags & 2)
87 /* Nonzero if we assume that all calls will fall within a 16MB
88 pc-relative range. Useful with -fomit-frame-pointer. */
89 #define TARGET_TAIL_CALL (target_flags & 8)
91 /* Nonzero means that references to doublewords are guaranteed
92 aligned...if not, its a bug in the users program! */
93 #define TARGET_ALIGN (target_flags & 16)
95 /* Macro to define tables used to set the flags.
96 This is a list in braces of pairs in braces,
97 each pair being { "NAME", VALUE }
98 where VALUE is the bits to set or minus the bits to clear.
99 An empty string NAME is used to identify the default VALUE. */
101 #define TARGET_SWITCHES \
103 {"soft-float", -1}, \
105 {"no-epilogue", -2}, \
108 { "", TARGET_DEFAULT}}
110 #define TARGET_DEFAULT 3
112 /* target machine storage layout */
114 /* Define this if most significant bit is lowest numbered
115 in instructions that operate on numbered bit-fields. */
116 #define BITS_BIG_ENDIAN 1
118 /* Define this if most significant byte of a word is the lowest numbered. */
119 /* This is true on the SPARC. */
120 #define BYTES_BIG_ENDIAN 1
122 /* Define this if most significant word of a multiword number is the lowest
124 /* Doubles are stored in memory with the high order word first. This
125 matters when cross-compiling. */
126 #define WORDS_BIG_ENDIAN 1
128 /* number of bits in an addressible storage unit */
129 #define BITS_PER_UNIT 8
131 /* Width in bits of a "word", which is the contents of a machine register.
132 Note that this is not necessarily the width of data type `int';
133 if using 16-bit ints on a 68000, this would still be 32.
134 But on a machine with 16-bit registers, this would be 16. */
135 #define BITS_PER_WORD 32
136 #define MAX_BITS_PER_WORD 32
138 /* Width of a word, in units (bytes). */
139 #define UNITS_PER_WORD 4
141 /* Width in bits of a pointer.
142 See also the macro `Pmode' defined below. */
143 #define POINTER_SIZE 32
145 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
146 #define PARM_BOUNDARY 32
148 /* Boundary (in *bits*) on which stack pointer should be aligned. */
149 #define STACK_BOUNDARY 64
151 /* Allocation boundary (in *bits*) for the code of a function. */
152 #define FUNCTION_BOUNDARY 32
154 /* Alignment of field after `int : 0' in a structure. */
155 #define EMPTY_FIELD_BOUNDARY 32
157 /* Every structure's size must be a multiple of this. */
158 #define STRUCTURE_SIZE_BOUNDARY 8
160 /* A bitfield declared as `int' forces `int' alignment for the struct. */
161 #define PCC_BITFIELD_TYPE_MATTERS 1
163 /* No data type wants to be aligned rounder than this. */
164 #define BIGGEST_ALIGNMENT 64
166 /* Make strings word-aligned so strcpy from constants will be faster. */
167 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
168 (TREE_CODE (EXP) == STRING_CST \
169 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
171 /* Make arrays of chars word-aligned for the same reasons. */
172 #define DATA_ALIGNMENT(TYPE, ALIGN) \
173 (TREE_CODE (TYPE) == ARRAY_TYPE \
174 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
175 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
177 /* Define this if move instructions will actually fail to work
178 when given unaligned data. */
179 #define STRICT_ALIGNMENT
181 /* Things that must be doubleword aligned cannot go in the text section,
182 because the linker fails to align the text section enough!
183 Put them in the data section. */
184 #define MAX_TEXT_ALIGN 32
186 #define SELECT_SECTION(T,RELOC) \
188 if (TREE_CODE (T) == VAR_DECL) \
190 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
191 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
192 && ! (flag_pic && (RELOC))) \
197 else if (TREE_CODE (T) == CONSTRUCTOR) \
199 if (flag_pic != 0 && (RELOC) != 0) \
202 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
204 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
205 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
212 /* Use text section for a constant
213 unless we need more alignment than that offers. */
214 #define SELECT_RTX_SECTION(MODE, X) \
216 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
217 && ! (flag_pic && symbolic_operand (X))) \
223 /* Standard register usage. */
225 /* Number of actual hardware registers.
226 The hardware registers are assigned numbers for the compiler
227 from 0 to just below FIRST_PSEUDO_REGISTER.
228 All registers that the compiler knows about must be given numbers,
229 even those that are not normally considered general registers.
231 SPARC has 32 integer registers and 32 floating point registers. */
233 #define FIRST_PSEUDO_REGISTER 64
235 /* 1 for registers that have pervasive standard uses
236 and are not available for the register allocator.
237 0 is used for the condition code and not to represent %g0, which is
238 hardwired to 0, so reg 0 is *not* fixed.
239 2 and 3 are free to use as temporaries.
240 4 through 7 are expected to become usefully defined in the future.
241 Your milage may vary. */
242 #define FIXED_REGISTERS \
243 {0, 0, 0, 0, 1, 1, 1, 1, \
244 0, 0, 0, 0, 0, 0, 1, 0, \
245 0, 0, 0, 0, 0, 0, 0, 0, \
246 0, 0, 0, 0, 0, 0, 1, 1, \
248 0, 0, 0, 0, 0, 0, 0, 0, \
249 0, 0, 0, 0, 0, 0, 0, 0, \
250 0, 0, 0, 0, 0, 0, 0, 0, \
251 0, 0, 0, 0, 0, 0, 0, 0}
253 /* 1 for registers not available across function calls.
254 These must include the FIXED_REGISTERS and also any
255 registers that can be used without being saved.
256 The latter must include the registers where values are returned
257 and the register where structure-value addresses are passed.
258 Aside from that, you can include as many other registers as you like. */
259 #define CALL_USED_REGISTERS \
260 {1, 1, 1, 1, 1, 1, 1, 1, \
261 1, 1, 1, 1, 1, 1, 1, 1, \
262 0, 0, 0, 0, 0, 0, 0, 0, \
263 0, 0, 0, 0, 0, 0, 1, 1, \
265 1, 1, 1, 1, 1, 1, 1, 1, \
266 1, 1, 1, 1, 1, 1, 1, 1, \
267 1, 1, 1, 1, 1, 1, 1, 1, \
268 1, 1, 1, 1, 1, 1, 1, 1}
270 /* Return number of consecutive hard regs needed starting at reg REGNO
271 to hold something of mode MODE.
272 This is ordinarily the length in words of a value of mode MODE
273 but can be less for certain modes in special long registers.
275 On SPARC, ordinary registers hold 32 bits worth;
276 this means both integer and floating point registers.
278 We use vectors to keep this information about registers. */
280 /* How many hard registers it takes to make a register of this mode. */
281 extern int hard_regno_nregs
[];
283 #define HARD_REGNO_NREGS(REGNO, MODE) \
284 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
286 /* Value is 1 if register/mode pair is acceptable on sparc. */
287 extern int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
289 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
290 On SPARC, the cpu registers can hold any mode but the float registers
291 can only hold SFmode or DFmode. See sparc.c for how we
293 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
294 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
296 /* Value is 1 if it is a good idea to tie two pseudo registers
297 when one has mode MODE1 and one has mode MODE2.
298 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
299 for any hard reg, then this must be 0 for correct output. */
300 #define MODES_TIEABLE_P(MODE1, MODE2) \
301 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
303 /* Specify the registers used for certain standard purposes.
304 The values of these macros are register numbers. */
306 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
307 /* #define PC_REGNUM */
309 /* Register to use for pushing function arguments. */
310 #define STACK_POINTER_REGNUM 14
312 /* Actual top-of-stack address is 92 greater than the contents
313 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
314 for the ins and local registers, 4 byte for structure return address, and
315 24 bytes for the 6 register parameters. */
316 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
318 /* Base register for access to local variables of the function. */
319 #define FRAME_POINTER_REGNUM 30
322 /* Register that is used for the return address. */
323 #define RETURN_ADDR_REGNUM 15
326 /* Value should be nonzero if functions must have frame pointers.
327 Zero means the frame pointer need not be set up (and parms
328 may be accessed via the stack pointer) in functions that seem suitable.
329 This is computed in `reload', in reload1.c.
331 Used in flow.c, global-alloc.c, and reload1.c. */
332 extern int leaf_function
;
334 #define FRAME_POINTER_REQUIRED \
335 (! (leaf_function_p () && only_leaf_regs_used ()))
337 /* C statement to store the difference between the frame pointer
338 and the stack pointer values immediately after the function prologue.
340 Note, we always pretend that this is a leaf function because if
341 it's not, there's no point in trying to eliminate the
342 frame pointer. If it is a leaf function, we guessed right! */
343 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
344 do { (VAR) = compute_frame_size (get_frame_size (), 1); } while (0)
346 /* Base register for access to arguments of the function. */
347 #define ARG_POINTER_REGNUM 30
349 /* Register in which static-chain is passed to a function. */
351 #define STATIC_CHAIN_REGNUM 1
353 /* Register which holds offset table for position-independent
356 #define PIC_OFFSET_TABLE_REGNUM 23
358 #define INITIALIZE_PIC initialize_pic ()
359 #define FINALIZE_PIC finalize_pic ()
361 /* Functions which return large structures get the address
362 to place the wanted value at offset 64 from the frame.
363 Must reserve 64 bytes for the in and local registers. */
364 /* Used only in other #defines in this file. */
365 #define STRUCT_VALUE_OFFSET 64
367 #define STRUCT_VALUE \
368 gen_rtx (MEM, Pmode, \
369 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
370 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
371 #define STRUCT_VALUE_INCOMING \
372 gen_rtx (MEM, Pmode, \
373 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
374 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
376 /* Define the classes of registers for register constraints in the
377 machine description. Also define ranges of constants.
379 One of the classes must always be named ALL_REGS and include all hard regs.
380 If there is more than one class, another class must be named NO_REGS
381 and contain no registers.
383 The name GENERAL_REGS must be the name of a class (or an alias for
384 another name such as ALL_REGS). This is the class of registers
385 that is allowed by "g" or "r" in a register constraint.
386 Also, registers outside this class are allocated only when
387 instructions express preferences for them.
389 The classes must be numbered in nondecreasing order; that is,
390 a larger-numbered class must never be contained completely
391 in a smaller-numbered class.
393 For any two classes, it is very desirable that there be another
394 class that represents their union. */
396 /* The SPARC has two kinds of registers, general and floating point. */
398 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
400 #define N_REG_CLASSES (int) LIM_REG_CLASSES
402 /* Give names of register classes as strings for dump file. */
404 #define REG_CLASS_NAMES \
405 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
407 /* Define which registers fit in which classes.
408 This is an initializer for a vector of HARD_REG_SET
409 of length N_REG_CLASSES. */
411 #if 0 && defined (__GNUC__)
412 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
414 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
417 /* The same information, inverted:
418 Return the class number of the smallest class containing
419 reg number REGNO. This could be a conditional expression
420 or could index an array. */
422 #define REGNO_REG_CLASS(REGNO) \
423 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
425 /* This is the order in which to allocate registers
427 #define REG_ALLOC_ORDER \
428 { 8, 9, 10, 11, 12, 13, 2, 15, \
429 16, 17, 18, 19, 20, 21, 22, 23, \
430 24, 25, 26, 27, 28, 29, 3, 31, \
431 32, 33, 34, 35, 36, 37, 38, 39, \
432 40, 41, 42, 43, 44, 45, 46, 47, \
433 48, 49, 50, 51, 52, 53, 54, 55, \
434 56, 57, 58, 59, 60, 61, 62, 63, \
435 1, 4, 5, 6, 7, 0, 14, 30};
437 /* This is the order in which to allocate registers for
438 leaf functions. If all registers can fit in the "i" registers,
439 then we have the possibility of having a leaf function. */
440 #define REG_LEAF_ALLOC_ORDER \
441 { 2, 3, 24, 25, 26, 27, 28, 29, \
442 15, 8, 9, 10, 11, 12, 13, \
443 16, 17, 18, 19, 20, 21, 22, 23, \
444 32, 33, 34, 35, 36, 37, 38, 39, \
445 40, 41, 42, 43, 44, 45, 46, 47, \
446 48, 49, 50, 51, 52, 53, 54, 55, \
447 56, 57, 58, 59, 60, 61, 62, 63, \
448 1, 4, 5, 6, 7, 0, 14, 30, 31};
450 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
452 #define LEAF_REGISTERS \
453 { 1, 1, 1, 1, 1, 1, 1, 1, \
454 0, 0, 0, 0, 0, 0, 1, 0, \
455 0, 0, 0, 0, 0, 0, 0, 0, \
456 1, 1, 1, 1, 1, 1, 0, 1, \
457 1, 1, 1, 1, 1, 1, 1, 1, \
458 1, 1, 1, 1, 1, 1, 1, 1, \
459 1, 1, 1, 1, 1, 1, 1, 1, \
460 1, 1, 1, 1, 1, 1, 1, 1};
462 extern char leaf_reg_remap
[];
463 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
464 extern char leaf_reg_backmap
[];
465 #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
467 #define REG_USED_SO_FAR(REGNO) \
468 ((REGNO) >= 24 && (REGNO) < 30 \
469 ? (regs_ever_live[24] \
470 || regs_ever_live[25] \
471 || regs_ever_live[26] \
472 || regs_ever_live[27] \
473 || regs_ever_live[28] \
474 || regs_ever_live[29]) : 0)
476 /* The class value for index registers, and the one for base regs. */
477 #define INDEX_REG_CLASS GENERAL_REGS
478 #define BASE_REG_CLASS GENERAL_REGS
480 /* Get reg_class from a letter such as appears in the machine description. */
482 #define REG_CLASS_FROM_LETTER(C) \
483 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
485 /* The letters I, J, K, L and M in a register constraint string
486 can be used to stand for particular ranges of immediate operands.
487 This macro defines what the ranges are.
488 C is the letter, and VALUE is a constant value.
489 Return 1 if VALUE is in the range specified by C.
491 For SPARC, `I' is used for the range of constants an insn
492 can actually contain.
493 `J' is used for the range which is just zero (since that is R0).
494 `K' is used for the 5-bit operand of a compare insns. */
496 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
498 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
499 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
500 : (C) == 'J' ? (VALUE) == 0 \
501 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
504 /* Similar, but for floating constants, and defining letters G and H.
505 Here VALUE is the CONST_DOUBLE rtx itself. */
507 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
508 ((C) == 'G' ? CONST_DOUBLE_HIGH (VALUE) == 0 \
509 && CONST_DOUBLE_LOW (VALUE) == 0 \
510 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
513 /* Given an rtx X being reloaded into a reg required to be
514 in class CLASS, return the class of reg to actually use.
515 In general this is just CLASS; but on some machines
516 in some cases it is preferable to use a more restrictive class. */
517 #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
519 /* Return the register class of a scratch register needed to load IN into
520 a register of class CLASS in MODE.
522 On the SPARC, when PIC, we need a temporary when loading some addresses
525 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
526 (flag_pic && pic_address_needs_scratch (IN) ? GENERAL_REGS : NO_REGS)
528 /* Return the maximum number of consecutive registers
529 needed to represent mode MODE in a register of class CLASS. */
530 /* On SPARC, this is the size of MODE in words. */
531 #define CLASS_MAX_NREGS(CLASS, MODE) \
532 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
534 /* Stack layout; function entry, exit and calling. */
536 /* Define the number of register that can hold parameters.
537 These two macros are used only in other macro definitions below. */
540 /* Define this if pushing a word on the stack
541 makes the stack pointer a smaller address. */
542 #define STACK_GROWS_DOWNWARD
544 /* Define this if the nominal address of the stack frame
545 is at the high-address end of the local variables;
546 that is, each additional local variable allocated
547 goes at a more negative offset in the frame. */
548 #define FRAME_GROWS_DOWNWARD
550 /* Offset within stack frame to start allocating local variables at.
551 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
552 first local allocated. Otherwise, it is the offset to the BEGINNING
553 of the first local allocated. */
554 #define STARTING_FRAME_OFFSET (-16)
556 /* If we generate an insn to push BYTES bytes,
557 this says how many the stack pointer really advances by.
558 On SPARC, don't define this because there are no push insns. */
559 /* #define PUSH_ROUNDING(BYTES) */
561 /* Offset of first parameter from the argument pointer register value.
562 This is 64 for the ins and locals, plus 4 for the struct-return reg
563 even if this function isn't going to use it. */
564 #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
566 /* Offset from top-of-stack address to location to store the
567 function parameter if it can't go in a register.
568 Addresses for following parameters are computed relative to this one. */
569 #define FIRST_PARM_CALLER_OFFSET(FNDECL) \
570 (STRUCT_VALUE_OFFSET + UNITS_PER_WORD - STACK_POINTER_OFFSET)
572 /* When a parameter is passed in a register, stack space is still
574 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
576 /* Keep the stack pointer constant throughout the function.
577 This is both an optimization and a neccessity: longjmp
578 doesn't behave itself when the stack pointer moves within
580 #define ACCUMULATE_OUTGOING_ARGS
582 /* Value is the number of bytes of arguments automatically
583 popped when returning from a subroutine call.
584 FUNTYPE is the data type of the function (as a tree),
585 or for a library call it is an identifier node for the subroutine name.
586 SIZE is the number of bytes of arguments passed on the stack. */
588 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
590 /* Some subroutine macros specific to this machine. */
591 #define BASE_RETURN_VALUE_REG(MODE) \
592 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 8)
593 #define BASE_OUTGOING_VALUE_REG(MODE) \
594 ((MODE) == SFmode || (MODE) == DFmode ? 32 : 24)
595 #define BASE_PASSING_ARG_REG(MODE) (8)
596 #define BASE_INCOMING_ARG_REG(MODE) (24)
598 /* Define how to find the value returned by a function.
599 VALTYPE is the data type of the value (as a tree).
600 If the precise function being called is known, FUNC is its FUNCTION_DECL;
601 otherwise, FUNC is 0. */
603 /* On SPARC the value is found in the first "output" register. */
605 #define FUNCTION_VALUE(VALTYPE, FUNC) \
606 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
608 /* But the called function leaves it in the first "input" register. */
610 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
611 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
613 /* Define how to find the value returned by a library function
614 assuming the value has mode MODE. */
616 #define LIBCALL_VALUE(MODE) \
617 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
619 /* 1 if N is a possible register number for a function value
620 as seen by the caller.
621 On SPARC, the first "output" reg is used for integer values,
622 and the first floating point register is used for floating point values. */
624 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
626 /* 1 if N is a possible register number for function argument passing.
627 On SPARC, these are the "output" registers. */
629 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
631 /* Define a data type for recording info about an argument list
632 during the scan of that argument list. This data type should
633 hold all necessary information about the function itself
634 and about the args processed so far, enough to enable macros
635 such as FUNCTION_ARG to determine where the next arg should go.
637 On SPARC, this is a single integer, which is a number of words
638 of arguments scanned so far (including the invisible argument,
639 if any, which holds the structure-value-address).
640 Thus 7 or more means all following args should go on the stack. */
642 #define CUMULATIVE_ARGS int
644 #define ROUND_ADVANCE(SIZE) \
645 ((SIZE + UNITS_PER_WORD - 1)/UNITS_PER_WORD)
647 /* Initialize a variable CUM of type CUMULATIVE_ARGS
648 for a call to a function whose data type is FNTYPE.
649 For a library call, FNTYPE is 0.
651 On SPARC, the offset always starts at 0: the first parm reg is always
654 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
656 /* Update the data in CUM to advance over an argument
657 of mode MODE and data type TYPE.
658 (TYPE is null for libcalls where that information may not be available.) */
660 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
661 ((CUM) += ((MODE) != BLKmode \
662 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
663 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
665 /* Determine where to put an argument to a function.
666 Value is zero to push the argument on the stack,
667 or a hard register in which to store the argument.
669 MODE is the argument's machine mode.
670 TYPE is the data type of the argument (as a tree).
671 This is null for libcalls where that information may
673 CUM is a variable of type CUMULATIVE_ARGS which gives info about
674 the preceding args and about the function being called.
675 NAMED is nonzero if this argument is a named parameter
676 (otherwise it is an extra parameter matching an ellipsis). */
678 /* On SPARC the first six args are normally in registers
679 and the rest are pushed. Any arg that starts within the first 6 words
680 is at least partially passed in a register unless its data type forbids. */
682 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
683 ((CUM) < NPARM_REGS \
684 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
685 && ((TYPE)==0 || (MODE) != BLKmode || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
686 ? gen_rtx (REG, (MODE), BASE_PASSING_ARG_REG (MODE) + (CUM)) : 0)
688 /* Define where a function finds its arguments.
689 This is different from FUNCTION_ARG because of register windows. */
691 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
692 ((CUM) < NPARM_REGS \
693 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
694 && ((MODE) != BLKmode || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
695 ? gen_rtx (REG, (MODE), BASE_INCOMING_ARG_REG (MODE) + (CUM)) : 0)
697 /* For an arg passed partly in registers and partly in memory,
698 this is the number of registers used.
699 For args passed entirely in registers or entirely in memory, zero.
700 Any arg that starts in the first 6 regs but won't entirely fit in them
701 needs partial registers on the Sparc. */
703 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
704 (((CUM) < NPARM_REGS \
705 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
706 && ((TYPE)==0 || (MODE) != BLKmode || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0))\
708 + ((MODE) == BLKmode \
709 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
710 : ROUND_ADVANCE (GET_MODE_SIZE (MODE)))) - NPARM_REGS > 0) \
711 ? (NPARM_REGS - (CUM)) \
714 /* The SPARC ABI stipulates passing struct arguments (of any size)
715 by invisible reference. */
716 /* Must pass by reference if this is a structure/union type, and this is not
717 target gnu or the address of this structure is needed somewhere. */
718 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
719 (TYPE && (TREE_CODE (TYPE) == RECORD_TYPE || TREE_CODE (TYPE) == UNION_TYPE))
721 /* Define the information needed to generate branch and scc insns. This is
722 stored from the compare operation. Note that we can't use "rtx" here
723 since it hasn't been defined! */
725 extern struct rtx_def
*sparc_compare_op0
, *sparc_compare_op1
;
727 /* Define the function that build the compare insn for scc and bcc. */
729 extern struct rtx_def
*gen_compare_reg ();
731 /* Output the label for a function definition. */
733 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
735 extern tree double_type_node, float_type_node; \
736 if (TREE_TYPE (DECL) == float_type_node) \
737 fprintf (FILE, "\t.proc 6\n"); \
738 else if (TREE_TYPE (DECL) == double_type_node) \
739 fprintf (FILE, "\t.proc 7\n"); \
740 else if (TREE_TYPE (DECL) == void_type_node) \
741 fprintf (FILE, "\t.proc 0\n"); \
742 else fprintf (FILE, "\t.proc 1\n"); \
743 ASM_OUTPUT_LABEL (FILE, NAME); \
746 /* Two views of the size of the current frame. */
747 extern int actual_fsize
;
748 extern int apparent_fsize
;
750 /* This macro generates the assembly code for function entry.
751 FILE is a stdio stream to output the code to.
752 SIZE is an int: how many units of temporary storage to allocate.
753 Refer to the array `regs_ever_live' to determine which registers
754 to save; `regs_ever_live[I]' is nonzero if register number I
755 is ever used in the function. This macro is responsible for
756 knowing which registers should not be saved even if used. */
758 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
759 of memory. If any fpu reg is used in the function, we allocate
760 such a block here, at the bottom of the frame, just in case it's needed.
762 If this function is a leaf procedure, then we may choose not
763 to do a "save" insn. The decision about whether or not
764 to do this is made in regclass.c. */
766 #define FUNCTION_PROLOGUE(FILE, SIZE) \
767 output_function_prologue (FILE, SIZE, leaf_function)
769 /* Output assembler code to FILE to increment profiler label # LABELNO
770 for profiling a function entry. */
772 #define FUNCTION_PROFILER(FILE, LABELNO) \
773 fprintf (FILE, "\tsethi %%hi(LP%d),%%o0\n\tcall mcount\n\tor %%lo(LP%d),%%o0,%%o0\n", \
774 (LABELNO), (LABELNO))
776 /* Output assembler code to FILE to initialize this source file's
777 basic block profiling info, if that has not already been done. */
779 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
780 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
781 (LABELNO), (LABELNO))
783 /* Output assembler code to FILE to increment the entry-count for
784 the BLOCKNO'th basic block in this source file. */
786 #define BLOCK_PROFILER(FILE, BLOCKNO) \
788 int blockn = (BLOCKNO); \
789 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
790 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
791 4 * blockn, 4 * blockn, 4 * blockn); \
794 /* Output rtl to increment the entry-count for the LABELNO'th instrumented
795 arc in this source file. */
797 #define ARC_PROFILER(ARCNO, INSERT_AFTER) \
798 output_arc_profiler (ARCNO, INSERT_AFTER)
800 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
801 the stack pointer does not matter. The value is tested only in
802 functions that have frame pointers.
803 No definition is equivalent to always zero. */
805 extern int current_function_calls_alloca
;
806 extern int current_function_outgoing_args_size
;
808 #define EXIT_IGNORE_STACK \
809 (get_frame_size () != 0 \
810 || current_function_calls_alloca || current_function_outgoing_args_size)
812 /* This macro generates the assembly code for function exit,
813 on machines that need it. If FUNCTION_EPILOGUE is not defined
814 then individual return instructions are generated for each
815 return statement. Args are same as for FUNCTION_PROLOGUE.
817 The function epilogue should not depend on the current stack pointer!
818 It should use the frame pointer only. This is mandatory because
819 of alloca; we also take advantage of it to omit stack adjustments
822 /* This declaration is needed due to traditional/ANSI
823 incompatibilities which cannot be #ifdefed away
824 because they occur inside of macros. Sigh. */
825 extern union tree_node
*current_function_decl
;
827 #define FUNCTION_EPILOGUE(FILE, SIZE) \
828 output_function_epilogue (FILE, SIZE, leaf_function, 1)
830 #define DELAY_SLOTS_FOR_EPILOGUE 1
831 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
832 eligible_for_epilogue_delay (trial, slots_filled)
834 /* Output assembler code for a block containing the constant parts
835 of a trampoline, leaving space for the variable parts. */
837 /* On the sparc, the trampoline contains five instructions:
838 sethi #TOP_OF_FUNCTION,%g2
839 or #BOTTOM_OF_FUNCTION,%g2,%g2
840 sethi #TOP_OF_STATIC,%g1
842 or #BOTTOM_OF_STATIC,%g1,%g1 */
843 #define TRAMPOLINE_TEMPLATE(FILE) \
845 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
846 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
847 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
848 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C08000)); \
849 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
852 /* Length in units of the trampoline for entering a nested function. */
854 #define TRAMPOLINE_SIZE 20
856 /* Emit RTL insns to initialize the variable parts of a trampoline.
857 FNADDR is an RTX for the address of the function's pure code.
858 CXT is an RTX for the static chain value for the function.
860 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
861 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
862 (to store insns). This is a bit excessive. Perhaps a different
863 mechanism would be better here. */
865 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
867 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
868 size_int (10), 0, 1); \
869 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
870 size_int (10), 0, 1); \
871 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
872 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
873 rtx g1_sethi = gen_rtx (HIGH, SImode, \
874 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
875 rtx g2_sethi = gen_rtx (HIGH, SImode, \
876 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
877 rtx g1_ori = gen_rtx (HIGH, SImode, \
878 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
879 rtx g2_ori = gen_rtx (HIGH, SImode, \
880 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
881 rtx tem = gen_reg_rtx (SImode); \
882 emit_move_insn (tem, g2_sethi); \
883 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
884 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
885 emit_move_insn (tem, g2_ori); \
886 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
887 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
888 emit_move_insn (tem, g1_sethi); \
889 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
890 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
891 emit_move_insn (tem, g1_ori); \
892 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
893 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
896 /* Emit code for a call to builtin_saveregs. We must emit USE insns which
897 reference the 6 input registers. Ordinarily they are not call used
898 registers, but they are for _builtin_saveregs, so we must make this
901 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) \
902 (emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, TImode, 24))), \
903 emit_insn (gen_rtx (USE, VOIDmode, gen_rtx (REG, DImode, 28))), \
904 expand_call (exp, target, ignore))
906 /* Addressing modes, and classification of registers for them. */
908 /* #define HAVE_POST_INCREMENT */
909 /* #define HAVE_POST_DECREMENT */
911 /* #define HAVE_PRE_DECREMENT */
912 /* #define HAVE_PRE_INCREMENT */
914 /* Macros to check register numbers against specific register classes. */
916 /* These assume that REGNO is a hard or pseudo reg number.
917 They give nonzero only if REGNO is a hard reg of the suitable class
918 or a pseudo reg currently allocated to a suitable hard reg.
919 Since they use reg_renumber, they are safe only once reg_renumber
920 has been allocated, which happens in local-alloc.c. */
922 #define REGNO_OK_FOR_INDEX_P(REGNO) \
923 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
924 #define REGNO_OK_FOR_BASE_P(REGNO) \
925 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
926 #define REGNO_OK_FOR_FP_P(REGNO) \
927 (((REGNO) ^ 0x20) < 32 \
928 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
930 /* Now macros that check whether X is a register and also,
931 strictly, whether it is in a specified class.
933 These macros are specific to the SPARC, and may be used only
934 in code for printing assembler insns and in conditions for
935 define_optimization. */
937 /* 1 if X is an fp register. */
939 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
941 /* Maximum number of registers that can appear in a valid memory address. */
943 #define MAX_REGS_PER_ADDRESS 2
945 /* Recognize any constant value that is a valid address. */
947 #define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X))
949 /* Nonzero if the constant value X is a legitimate general operand.
950 Anything can be made to work except floating point constants. */
952 #define LEGITIMATE_CONSTANT_P(X) \
953 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
955 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
956 and check its validity for a certain class.
957 We have two alternate definitions for each of them.
958 The usual definition accepts all pseudo regs; the other rejects
959 them unless they have been allocated suitable hard regs.
960 The symbol REG_OK_STRICT causes the latter definition to be used.
962 Most source files want to accept pseudo regs in the hope that
963 they will get allocated to the class that the insn wants them to be in.
964 Source files for reload pass need to be strict.
965 After reload, it makes no difference, since pseudo regs have
966 been eliminated by then. */
968 /* Optional extra constraints for this machine. Borrowed from romp.h.
970 For the SPARC, `Q' means that this is a memory operand but not a
971 symbolic memory operand. Note that an unassigned pseudo register
972 is such a memory operand. Needed because reload will generate
973 these things in insns and then not re-recognize the insns, causing
974 constrain_operands to fail.
976 `R' handles the LO_SUM which can be an address for `Q'.
978 `S' handles constraints for calls. */
980 #ifndef REG_OK_STRICT
982 /* Nonzero if X is a hard reg that can be used as an index
983 or if it is a pseudo reg. */
984 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
985 /* Nonzero if X is a hard reg that can be used as a base reg
986 or if it is a pseudo reg. */
987 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
989 #define EXTRA_CONSTRAINT(OP, C) \
991 ((GET_CODE (OP) == MEM \
992 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
993 && ! symbolic_memory_operand (OP, VOIDmode))) \
995 (GET_CODE (OP) == LO_SUM \
996 && GET_CODE (XEXP (OP, 0)) == REG \
997 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
999 ? CONSTANT_P (OP) || memory_address_p (Pmode, OP) : 0)))
1003 /* Nonzero if X is a hard reg that can be used as an index. */
1004 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1005 /* Nonzero if X is a hard reg that can be used as a base reg. */
1006 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1008 #define EXTRA_CONSTRAINT(OP, C) \
1010 (GET_CODE (OP) == REG ? \
1011 (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1012 && reg_renumber[REGNO (OP)] < 0) \
1013 : GET_CODE (OP) == MEM) \
1015 (GET_CODE (OP) == LO_SUM \
1016 && GET_CODE (XEXP (OP, 0)) == REG \
1017 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1019 ? (CONSTANT_P (OP) \
1020 || (GET_CODE (OP) == REG && reg_renumber[REGNO (OP)] > 0)\
1021 || strict_memory_address_p (Pmode, OP)) : 0)))
1024 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1025 that is a valid memory address for an instruction.
1026 The MODE argument is the machine mode for the MEM expression
1027 that wants to use this address.
1029 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1030 ordinarily. This changes a bit when generating PIC.
1032 If you change this, execute "rm explow.o recog.o reload.o". */
1034 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1035 { if (GET_CODE (X) == REG) \
1036 { if (REG_OK_FOR_BASE_P (X)) goto ADDR; } \
1037 else if (GET_CODE (X) == PLUS) \
1039 if (flag_pic && XEXP (X, 0) == pic_offset_table_rtx)\
1041 if (GET_CODE (XEXP (X, 1)) == REG \
1042 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1044 else if (flag_pic == 1 \
1045 && GET_CODE (XEXP (X, 1)) != REG \
1046 && GET_CODE (XEXP (X, 1)) != LO_SUM \
1047 && GET_CODE (XEXP (X, 1)) != MEM) \
1050 else if (GET_CODE (XEXP (X, 0)) == REG \
1051 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1053 if (GET_CODE (XEXP (X, 1)) == REG \
1054 && REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
1056 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1057 && INTVAL (XEXP (X, 1)) >= -0x1000 \
1058 && INTVAL (XEXP (X, 1)) < 0x1000) \
1061 else if (GET_CODE (XEXP (X, 1)) == REG \
1062 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1064 if (GET_CODE (XEXP (X, 0)) == REG \
1065 && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
1067 if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1068 && INTVAL (XEXP (X, 0)) >= -0x1000 \
1069 && INTVAL (XEXP (X, 0)) < 0x1000) \
1073 else if (GET_CODE (X) == LO_SUM \
1074 && GET_CODE (XEXP (X, 0)) == REG \
1075 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1076 && CONSTANT_P (XEXP (X, 1))) \
1078 else if (GET_CODE (X) == LO_SUM \
1079 && GET_CODE (XEXP (X, 0)) == SUBREG \
1080 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG\
1081 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0)))\
1082 && CONSTANT_P (XEXP (X, 1))) \
1084 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1088 /* Try machine-dependent ways of modifying an illegitimate address
1089 to be legitimate. If we find one, return the new, valid address.
1090 This macro is used in only one place: `memory_address' in explow.c.
1092 OLDX is the address as it was before break_out_memory_refs was called.
1093 In some cases it is useful to look at this to decide what needs to be done.
1095 MODE and WIN are passed so that this macro can use
1096 GO_IF_LEGITIMATE_ADDRESS.
1098 It is always safe for this macro to do nothing. It exists to recognize
1099 opportunities to optimize the output. */
1101 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1102 extern struct rtx_def
*legitimize_pic_address ();
1103 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1104 { rtx sparc_x = (X); \
1105 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1106 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1107 force_operand (XEXP (X, 0), 0)); \
1108 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1109 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1110 force_operand (XEXP (X, 1), 0)); \
1111 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1112 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), 0),\
1114 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1115 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1116 force_operand (XEXP (X, 1), 0)); \
1117 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1119 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0, 0); \
1120 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1121 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1122 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1123 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1124 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1125 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1126 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1127 || GET_CODE (X) == LABEL_REF) \
1128 (X) = gen_rtx (LO_SUM, Pmode, \
1129 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1130 if (memory_address_p (MODE, X)) \
1133 /* Go to LABEL if ADDR (a legitimate address expression)
1134 has an effect that depends on the machine mode it is used for.
1135 On the SPARC this is never true. */
1137 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1139 /* Specify the machine mode that this machine uses
1140 for the index in the tablejump instruction. */
1141 #define CASE_VECTOR_MODE SImode
1143 /* Define this if the tablejump instruction expects the table
1144 to contain offsets from the address of the table.
1145 Do not define this if the table should contain absolute addresses. */
1146 /* #define CASE_VECTOR_PC_RELATIVE */
1148 /* Specify the tree operation to be used to convert reals to integers. */
1149 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1151 /* This is the kind of divide that is easiest to do in the general case. */
1152 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1154 /* Define this as 1 if `char' should by default be signed; else as 0. */
1155 #define DEFAULT_SIGNED_CHAR 1
1157 /* Max number of bytes we can move from memory to memory
1158 in one reasonably fast instruction. */
1161 /* Define if normal loads of shorter-than-word items from memory clears
1162 the rest of the bigs in the register. */
1163 #define BYTE_LOADS_ZERO_EXTEND
1165 /* Nonzero if access to memory by bytes is slow and undesirable.
1166 For RISC chips, it means that access to memory by bytes is no
1167 better than access by words when possible, so grab a whole word
1168 and maybe make use of that. */
1169 #define SLOW_BYTE_ACCESS 1
1171 /* We assume that the store-condition-codes instructions store 0 for false
1172 and some other value for true. This is the value stored for true. */
1174 #define STORE_FLAG_VALUE 1
1176 /* When a prototype says `char' or `short', really pass an `int'. */
1177 #define PROMOTE_PROTOTYPES
1179 /* Define if shifts truncate the shift count
1180 which implies one can omit a sign-extension or zero-extension
1181 of a shift count. */
1182 #define SHIFT_COUNT_TRUNCATED
1184 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1185 is done just by pretending it is already truncated. */
1186 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1188 /* Specify the machine mode that pointers have.
1189 After generation of rtl, the compiler makes no further distinction
1190 between pointers and any other objects of this machine mode. */
1191 #define Pmode SImode
1193 /* Add any extra modes needed to represent the condition code.
1195 On the Sparc, we have a "no-overflow" mode which is used when an add or
1196 subtract insn is used to set the condition code. Different branches are
1197 used in this case for some operations.
1199 We also have a mode to indicate that the relevant condition code is
1200 in the floating-point condition code. This really should be a separate
1201 register, but we don't want to go to 65 registers. */
1202 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode
1204 /* Define the names for the modes specified above. */
1205 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP"
1207 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1208 return the mode to be used for the comparison. For floating-point, CCFPmode
1209 should be used. CC_NOOVmode should be used when the first operand is a
1210 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1212 #define SELECT_CC_MODE(OP,X) \
1213 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
1214 : (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS || GET_CODE (X) == NEG) \
1215 ? CC_NOOVmode : CCmode)
1217 /* A function address in a call instruction
1218 is a byte address (for indexing purposes)
1219 so give the MEM rtx a byte's mode. */
1220 #define FUNCTION_MODE SImode
1222 /* Define this if addresses of constant functions
1223 shouldn't be put through pseudo regs where they can be cse'd.
1224 Desirable on machines where ordinary constants are expensive
1225 but a CALL with constant address is cheap. */
1226 #define NO_FUNCTION_CSE
1228 /* alloca should avoid clobbering the old register save area. */
1229 #define SETJMP_VIA_SAVE_AREA
1231 /* Define subroutines to call to handle multiply and divide.
1232 Use the subroutines that Sun's library provides.
1233 The `*' prevents an underscore from being prepended by the compiler. */
1235 #define DIVSI3_LIBCALL "*.div"
1236 #define UDIVSI3_LIBCALL "*.udiv"
1237 #define MODSI3_LIBCALL "*.rem"
1238 #define UMODSI3_LIBCALL "*.urem"
1239 /* .umul is a little faster than .mul. */
1240 #define MULSI3_LIBCALL "*.umul"
1242 /* Compute the cost of computing a constant rtl expression RTX
1243 whose rtx-code is CODE. The body of this macro is a portion
1244 of a switch statement. If the code is computed here,
1245 return it with a return statement. Otherwise, break from the switch. */
1247 #define CONST_COSTS(RTX,CODE) \
1249 if (INTVAL (RTX) == 0) \
1251 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1259 case CONST_DOUBLE: \
1260 if (GET_MODE (RTX) == DImode) \
1261 if ((XINT (RTX, 3) == 0 \
1262 && (unsigned) XINT (RTX, 2) < 0x1000) \
1263 || (XINT (RTX, 3) == -1 \
1264 && XINT (RTX, 2) < 0 \
1265 && XINT (RTX, 2) >= -0x1000)) \
1269 /* SPARC offers addressing modes which are "as cheap as a register".
1270 See sparc.c (or gcc.texinfo) for details. */
1272 #define ADDRESS_COST(RTX) \
1273 (GET_CODE (RTX) == REG ? 1 : sparc_address_cost (RTX))
1275 /* Compute extra cost of moving data between one register class
1277 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1278 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1279 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1281 /* Provide the costs of a rtl expression. This is in the body of a
1282 switch on CODE. The purpose for the cost of MULT is to encourage
1283 `synth_mult' to find a synthetic multiply when reasonable.
1285 If we need more than 12 insns to do a multiply, then go out-of-line,
1286 since the call overhead will be < 10% of the cost of the multiply. */
1288 #define RTX_COSTS(X,CODE) \
1290 return COSTS_N_INSNS (25); \
1295 return COSTS_N_INSNS (20); \
1296 /* Make FLOAT more expensive than CONST_DOUBLE, \
1297 so that cse will favor the latter. */ \
1301 /* Conditional branches with empty delay slots have a length of two. */
1302 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1303 if (GET_CODE (INSN) == CALL_INSN \
1304 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1307 /* Control the assembler format that we output. */
1309 /* Output at beginning of assembler file. */
1311 #define ASM_FILE_START(file)
1313 /* Output to assembler file text saying following lines
1314 may contain character constants, extra white space, comments, etc. */
1316 #define ASM_APP_ON ""
1318 /* Output to assembler file text saying following lines
1319 no longer contain unusual constructs. */
1321 #define ASM_APP_OFF ""
1323 /* Output before read-only data. */
1325 #define TEXT_SECTION_ASM_OP ".text"
1327 /* Output before writable data. */
1329 #define DATA_SECTION_ASM_OP ".data"
1331 /* How to refer to registers in assembler output.
1332 This sequence is indexed by compiler's hard-register-number (see above). */
1334 #define REGISTER_NAMES \
1335 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1336 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1337 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1338 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1339 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1340 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1341 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1342 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1344 /* How to renumber registers for dbx and gdb. */
1346 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1348 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1349 since the length can run past this up to a continuation point. */
1350 #define DBX_CONTIN_LENGTH 1500
1352 /* This is how to output a note to DBX telling it the line number
1353 to which the following sequence of instructions corresponds.
1355 This is needed for SunOS 4.0, and should not hurt for 3.2
1357 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1358 { static int sym_lineno = 1; \
1359 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1360 line, sym_lineno, sym_lineno); \
1363 /* This is how to output the definition of a user-level label named NAME,
1364 such as the label on a static function or variable NAME. */
1366 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1367 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1369 /* This is how to output a command to make the user-level label named NAME
1370 defined for reference from other files. */
1372 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1373 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1375 /* This is how to output a reference to a user-level label named NAME.
1376 `assemble_name' uses this. */
1378 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1379 fprintf (FILE, "_%s", NAME)
1381 /* This is how to output an internal numbered label where
1382 PREFIX is the class of label and NUM is the number within the class. */
1384 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1385 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1387 /* This is how to store into the string LABEL
1388 the symbol_ref name of an internal numbered label where
1389 PREFIX is the class of label and NUM is the number within the class.
1390 This is suitable for output with `assemble_name'. */
1392 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1393 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1395 /* This is how to output an assembler line defining a `double' constant. */
1397 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1399 if (REAL_VALUE_ISINF (VALUE)) \
1400 fprintf (FILE, "\t.double 0r%s99e999\n", (VALUE) > 0 ? "" : "-"); \
1401 else if (isnan (VALUE)) \
1403 union { double d; long l[2];} t; \
1405 fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", t.l[0], t.l[1]); \
1408 fprintf (FILE, "\t.double 0r%.17g\n", VALUE); \
1411 /* This is how to output an assembler line defining a `float' constant. */
1413 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1415 if (REAL_VALUE_ISINF (VALUE)) \
1416 fprintf (FILE, "\t.single 0r%s99e999\n", (VALUE) > 0 ? "" : "-"); \
1417 else if (isnan (VALUE)) \
1419 union { float f; long l;} t; \
1421 fprintf (FILE, "\t.word 0x%lx\n", t.l); \
1424 fprintf (FILE, "\t.single 0r%.9g\n", VALUE); \
1427 /* This is how to output an assembler line defining an `int' constant. */
1429 #define ASM_OUTPUT_INT(FILE,VALUE) \
1430 ( fprintf (FILE, "\t.word "), \
1431 output_addr_const (FILE, (VALUE)), \
1432 fprintf (FILE, "\n"))
1434 /* This is how to output an assembler line defining a DImode constant. */
1435 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1436 output_double_int (FILE, VALUE)
1438 /* Likewise for `char' and `short' constants. */
1440 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1441 ( fprintf (FILE, "\t.half "), \
1442 output_addr_const (FILE, (VALUE)), \
1443 fprintf (FILE, "\n"))
1445 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1446 ( fprintf (FILE, "\t.byte "), \
1447 output_addr_const (FILE, (VALUE)), \
1448 fprintf (FILE, "\n"))
1450 /* This is how to output an assembler line for a numeric constant byte. */
1452 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1453 fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1455 /* This is how to output an element of a case-vector that is absolute. */
1457 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1458 fprintf (FILE, "\t.word L%d\n", VALUE)
1460 /* This is how to output an element of a case-vector that is relative.
1461 (SPARC uses such vectors only when generating PIC.) */
1463 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1464 fprintf (FILE, "\t.word L%d-1b\n", VALUE)
1466 /* This is how to output an assembler line
1467 that says to advance the location counter
1468 to a multiple of 2**LOG bytes. */
1470 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1472 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1474 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1475 fprintf (FILE, "\t.skip %u\n", (SIZE))
1477 /* This says how to output an assembler line
1478 to define a global common symbol. */
1480 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1481 ( fputs ("\t.global ", (FILE)), \
1482 assemble_name ((FILE), (NAME)), \
1483 fputs ("\n\t.common ", (FILE)), \
1484 assemble_name ((FILE), (NAME)), \
1485 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1487 /* This says how to output an assembler line
1488 to define a local common symbol. */
1490 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1491 ( fputs ("\n\t.reserve ", (FILE)), \
1492 assemble_name ((FILE), (NAME)), \
1493 fprintf ((FILE), ",%u,\"bss\"\n", (ROUNDED)))
1495 /* Store in OUTPUT a string (made with alloca) containing
1496 an assembler-name for a local static variable named NAME.
1497 LABELNO is an integer which is different for each call. */
1499 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1500 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1501 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1503 /* Define the parentheses used to group arithmetic operations
1504 in assembler code. */
1506 #define ASM_OPEN_PAREN "("
1507 #define ASM_CLOSE_PAREN ")"
1509 /* Define results of standard character escape sequences. */
1510 #define TARGET_BELL 007
1511 #define TARGET_BS 010
1512 #define TARGET_TAB 011
1513 #define TARGET_NEWLINE 012
1514 #define TARGET_VT 013
1515 #define TARGET_FF 014
1516 #define TARGET_CR 015
1518 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1519 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1521 /* Print operand X (an rtx) in assembler syntax to file FILE.
1522 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1523 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1525 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1527 /* Print a memory address as an operand to reference that memory location. */
1529 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1530 { register rtx base, index = 0; \
1532 register rtx addr = ADDR; \
1533 if (GET_CODE (addr) == REG) \
1534 fputs (reg_names[REGNO (addr)], FILE); \
1535 else if (GET_CODE (addr) == PLUS) \
1537 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1538 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1539 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1540 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1542 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1543 fputs (reg_names[REGNO (base)], FILE); \
1545 fprintf (FILE, "%+d", offset); \
1546 else if (GET_CODE (index) == REG) \
1547 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1548 else if (GET_CODE (index) == SYMBOL_REF) \
1549 fputc ('+', FILE), output_addr_const (FILE, index); \
1552 else if (GET_CODE (addr) == MINUS \
1553 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1555 output_addr_const (FILE, XEXP (addr, 0)); \
1556 fputs ("-(", FILE); \
1557 output_addr_const (FILE, XEXP (addr, 1)); \
1558 fputs ("-.)", FILE); \
1560 else if (GET_CODE (addr) == LO_SUM) \
1562 output_operand (XEXP (addr, 0), 0); \
1563 fputs ("+%lo(", FILE); \
1564 output_address (XEXP (addr, 1)); \
1565 fputc (')', FILE); \
1567 else if (flag_pic && GET_CODE (addr) == CONST \
1568 && GET_CODE (XEXP (addr, 0)) == MINUS \
1569 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1570 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1571 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1573 addr = XEXP (addr, 0); \
1574 output_addr_const (FILE, XEXP (addr, 0)); \
1575 /* Group the args of the second CONST in parenthesis. */ \
1576 fputs ("-(", FILE); \
1577 /* Skip past the second CONST--it does nothing for us. */\
1578 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1579 /* Close the parenthesis. */ \
1580 fputc (')', FILE); \
1584 output_addr_const (FILE, addr); \
1588 /* Declare functions defined in sparc.c and used in templates. */
1590 extern char *singlemove_string ();
1591 extern char *output_move_double ();
1592 extern char *output_fp_move_double ();
1593 extern char *output_block_move ();
1594 extern char *output_scc_insn ();
1595 extern char *output_cbranch ();
1596 extern char *output_return ();
1597 extern char *output_floatsisf2 ();
1598 extern char *output_floatsidf2 ();
1600 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1602 extern int flag_pic
;