1 /* Definitions of target machine for GNU compiler, for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1994 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* Note that some other tm.h files include this one and then override
22 many of the definitions that relate to assembler syntax. */
24 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} %{g:-lg} \
25 %{a:/usr/lib/bb_link.o}"
27 /* Provide required defaults for linker -e and -d switches. */
30 "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}"
32 /* Special flags to the Sun-4 assembler when using pipe for input. */
34 #define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k}"
36 /* Define macros to distinguish architectures. */
37 #define CPP_SPEC "%{msparclite:-D__sparclite__} %{mf930:-D__sparclite__} \
38 %{mf934:-D__sparclite__} %{mv8:-D__sparc_v8__}"
40 /* Prevent error on `-sun4' and `-target sun4' options. */
41 /* This used to translate -dalign to -malign, but that is no good
42 because it can't turn off the usual meaning of making debugging dumps. */
44 #define CC1_SPEC "%{sun4:} %{target:}"
46 #define PTRDIFF_TYPE "int"
47 /* In 2.4 it should work to delete this.
48 #define SIZE_TYPE "int" */
49 #define WCHAR_TYPE "short unsigned int"
50 #define WCHAR_TYPE_SIZE 16
52 /* Show we can debug even without a frame pointer. */
53 #define CAN_DEBUG_WITHOUT_FP
55 /* To make profiling work with -f{pic,PIC}, we need to emit the profiling
56 code into the rtl. Also, if we are profiling, we cannot eliminate
57 the frame pointer (because the return address will get smashed). */
59 #define OVERRIDE_OPTIONS \
61 if (profile_flag || profile_block_flag) \
62 flag_omit_frame_pointer = 0, flag_pic = 0; \
63 SUBTARGET_OVERRIDE_OPTIONS \
66 /* This is meant to be redefined in the host dependent files */
67 #define SUBTARGET_OVERRIDE_OPTIONS
69 /* These compiler options take an argument. We ignore -target for now. */
71 #define WORD_SWITCH_TAKES_ARG(STR) \
72 (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) \
73 || !strcmp (STR, "target") || !strcmp (STR, "assert"))
75 /* Names to predefine in the preprocessor for this target machine. */
77 /* The GCC_NEW_VARARGS macro is so that old versions of gcc can compile
78 new versions, which have an incompatible va-sparc.h file. This matters
79 because gcc does "gvarargs.h" instead of <varargs.h>, and thus gets the
80 wrong varargs file when it is compiled with a different version of gcc. */
82 #define CPP_PREDEFINES \
83 "-Dsparc -Dsun -Dunix -D__GCC_NEW_VARARGS__ \
84 -Asystem(unix) -Asystem(bsd) -Acpu(sparc) -Amachine(sparc)"
86 /* Print subsidiary information on the compiler version in use. */
88 #define TARGET_VERSION fprintf (stderr, " (sparc)");
90 /* Generate DBX debugging information. */
92 #define DBX_DEBUGGING_INFO
94 /* Run-time compilation parameters selecting different hardware subsets. */
96 extern int target_flags
;
98 /* Nonzero if we should generate code to use the fpu. */
99 #define TARGET_FPU (target_flags & 1)
101 /* Nonzero if we should use FUNCTION_EPILOGUE. Otherwise, we
102 use fast return insns, but lose some generality. */
103 #define TARGET_EPILOGUE (target_flags & 2)
105 /* Nonzero if we should assume that double pointers might be unaligned.
106 This can happen when linking gcc compiled code with other compilers,
107 because the ABI only guarantees 4 byte alignment. */
108 #define TARGET_UNALIGNED_DOUBLES (target_flags & 4)
110 /* Nonzero means that we should generate code for a v8 sparc. */
111 #define TARGET_V8 (target_flags & 64)
113 /* Nonzero means that we should generate code for a sparclite.
114 This enables the sparclite specific instructions, but does not affect
115 whether FPU instructions are emitted. */
116 #define TARGET_SPARCLITE (target_flags & 128)
118 /* Nonzero means that we should generate code using a flat register window
119 model, i.e. no save/restore instructions are generated, in the most
120 efficient manner. This code is not compatible with normal sparc code. */
121 /* This is not a user selectable option yet, because it requires changes
122 that are not yet switchable via command line arguments. */
123 #define TARGET_FRW (target_flags & 256)
125 /* Nonzero means that we should generate code using a flat register window
126 model, i.e. no save/restore instructions are generated, but which is
127 compatible with normal sparc code. This is the same as above, except
128 that the frame pointer is %l6 instead of %fp. This code is not as efficient
129 as TARGET_FRW, because it has one less allocatable register. */
130 /* This is not a user selectable option yet, because it requires changes
131 that are not yet switchable via command line arguments. */
132 #define TARGET_FRW_COMPAT (target_flags & 512)
134 /* Nonzero means use the registers that the Sparc ABI reserves for
135 application software. This is the default. */
136 #define TARGET_APP_REGS (target_flags & 1024)
138 /* Macro to define tables used to set the flags.
139 This is a list in braces of pairs in braces,
140 each pair being { "NAME", VALUE }
141 where VALUE is the bits to set or minus the bits to clear.
142 An empty string NAME is used to identify the default VALUE. */
144 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
145 The Fujitsu MB86934 is the recent sparclite chip, with an fup.
146 We use -mf930 and -mf934 options to choose which.
147 ??? These should perhaps be -mcpu= options. */
149 #define TARGET_SWITCHES \
153 {"soft-float", -1}, \
155 {"no-epilogue", -2}, \
156 {"unaligned-doubles", 4}, \
157 {"no-unaligned-doubles", -4},\
160 {"sparclite", 128}, \
161 {"no-sparclite", -128}, \
162 /* {"frw", 256}, */ \
163 /* {"no-frw", -256}, */ \
164 /* {"frw-compat", 256+512}, */ \
165 /* {"no-frw-compat", -(256+512)}, */ \
169 {"app-regs", 1024}, \
170 {"no-app-regs", -1024}, \
172 { "", TARGET_DEFAULT}}
174 #define TARGET_DEFAULT 1024+3
176 /* This is meant to be redefined in the host dependent files */
177 #define SUBTARGET_SWITCHES
179 /* target machine storage layout */
182 /* ??? This does not work in SunOS 4.x, so it is not enabled here.
183 Instead, it is enabled in sol2.h, because it does work under Solaris. */
184 /* Define for support of TFmode long double and REAL_ARITHMETIC.
185 Sparc ABI says that long double is 4 words. */
186 #define LONG_DOUBLE_TYPE_SIZE 128
189 /* Define for cross-compilation to a sparc target with no TFmode from a host
190 with a different float format (e.g. VAX). */
191 #define REAL_ARITHMETIC
193 /* Define this if most significant bit is lowest numbered
194 in instructions that operate on numbered bit-fields. */
195 #define BITS_BIG_ENDIAN 1
197 /* Define this if most significant byte of a word is the lowest numbered. */
198 /* This is true on the SPARC. */
199 #define BYTES_BIG_ENDIAN 1
201 /* Define this if most significant word of a multiword number is the lowest
203 /* Doubles are stored in memory with the high order word first. This
204 matters when cross-compiling. */
205 #define WORDS_BIG_ENDIAN 1
207 /* number of bits in an addressable storage unit */
208 #define BITS_PER_UNIT 8
210 /* Width in bits of a "word", which is the contents of a machine register.
211 Note that this is not necessarily the width of data type `int';
212 if using 16-bit ints on a 68000, this would still be 32.
213 But on a machine with 16-bit registers, this would be 16. */
214 #define BITS_PER_WORD 32
215 #define MAX_BITS_PER_WORD 32
217 /* Width of a word, in units (bytes). */
218 #define UNITS_PER_WORD 4
220 /* Width in bits of a pointer.
221 See also the macro `Pmode' defined below. */
222 #define POINTER_SIZE 32
224 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
225 #define PARM_BOUNDARY 32
227 /* Boundary (in *bits*) on which stack pointer should be aligned. */
228 #define STACK_BOUNDARY 64
230 /* ALIGN FRAMES on double word boundaries */
232 #define SPARC_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
234 /* Allocation boundary (in *bits*) for the code of a function. */
235 #define FUNCTION_BOUNDARY 32
237 /* Alignment of field after `int : 0' in a structure. */
238 #define EMPTY_FIELD_BOUNDARY 32
240 /* Every structure's size must be a multiple of this. */
241 #define STRUCTURE_SIZE_BOUNDARY 8
243 /* A bitfield declared as `int' forces `int' alignment for the struct. */
244 #define PCC_BITFIELD_TYPE_MATTERS 1
246 /* No data type wants to be aligned rounder than this. */
247 #define BIGGEST_ALIGNMENT 64
249 /* The best alignment to use in cases where we have a choice. */
250 #define FASTEST_ALIGNMENT 64
252 /* Make strings word-aligned so strcpy from constants will be faster. */
253 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
254 ((TREE_CODE (EXP) == STRING_CST \
255 && (ALIGN) < FASTEST_ALIGNMENT) \
256 ? FASTEST_ALIGNMENT : (ALIGN))
258 /* Make arrays of chars word-aligned for the same reasons. */
259 #define DATA_ALIGNMENT(TYPE, ALIGN) \
260 (TREE_CODE (TYPE) == ARRAY_TYPE \
261 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
262 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
264 /* Set this nonzero if move instructions will actually fail to work
265 when given unaligned data. */
266 #define STRICT_ALIGNMENT 1
268 /* Things that must be doubleword aligned cannot go in the text section,
269 because the linker fails to align the text section enough!
270 Put them in the data section. */
271 #define MAX_TEXT_ALIGN 32
273 #define SELECT_SECTION(T,RELOC) \
275 if (TREE_CODE (T) == VAR_DECL) \
277 if (TREE_READONLY (T) && ! TREE_SIDE_EFFECTS (T) \
278 && DECL_ALIGN (T) <= MAX_TEXT_ALIGN \
279 && ! (flag_pic && (RELOC))) \
284 else if (TREE_CODE (T) == CONSTRUCTOR) \
286 if (flag_pic != 0 && (RELOC) != 0) \
289 else if (*tree_code_type[(int) TREE_CODE (T)] == 'c') \
291 if ((TREE_CODE (T) == STRING_CST && flag_writable_strings) \
292 || TYPE_ALIGN (TREE_TYPE (T)) > MAX_TEXT_ALIGN) \
299 /* Use text section for a constant
300 unless we need more alignment than that offers. */
301 #define SELECT_RTX_SECTION(MODE, X) \
303 if (GET_MODE_BITSIZE (MODE) <= MAX_TEXT_ALIGN \
304 && ! (flag_pic && symbolic_operand (X))) \
310 /* Standard register usage. */
312 /* Number of actual hardware registers.
313 The hardware registers are assigned numbers for the compiler
314 from 0 to just below FIRST_PSEUDO_REGISTER.
315 All registers that the compiler knows about must be given numbers,
316 even those that are not normally considered general registers.
318 SPARC has 32 integer registers and 32 floating point registers. */
320 #define FIRST_PSEUDO_REGISTER 64
322 /* 1 for registers that have pervasive standard uses
323 and are not available for the register allocator.
324 g0 is used for the condition code and not to represent %g0, which is
325 hardwired to 0, so reg 0 is *not* fixed.
326 g1 is free to use as temporary.
327 g2-g4 are reserved for applications. Gcc normally uses them as
328 temporaries, but this can be disabled via the -mno-app-regs option.
329 g5 through g7 are reserved for the operating system. */
330 #define FIXED_REGISTERS \
331 {0, 0, 0, 0, 0, 1, 1, 1, \
332 0, 0, 0, 0, 0, 0, 1, 0, \
333 0, 0, 0, 0, 0, 0, 0, 0, \
334 0, 0, 0, 0, 0, 0, 1, 1, \
336 0, 0, 0, 0, 0, 0, 0, 0, \
337 0, 0, 0, 0, 0, 0, 0, 0, \
338 0, 0, 0, 0, 0, 0, 0, 0, \
339 0, 0, 0, 0, 0, 0, 0, 0}
341 /* 1 for registers not available across function calls.
342 These must include the FIXED_REGISTERS and also any
343 registers that can be used without being saved.
344 The latter must include the registers where values are returned
345 and the register where structure-value addresses are passed.
346 Aside from that, you can include as many other registers as you like. */
347 #define CALL_USED_REGISTERS \
348 {1, 1, 1, 1, 1, 1, 1, 1, \
349 1, 1, 1, 1, 1, 1, 1, 1, \
350 0, 0, 0, 0, 0, 0, 0, 0, \
351 0, 0, 0, 0, 0, 0, 1, 1, \
353 1, 1, 1, 1, 1, 1, 1, 1, \
354 1, 1, 1, 1, 1, 1, 1, 1, \
355 1, 1, 1, 1, 1, 1, 1, 1, \
356 1, 1, 1, 1, 1, 1, 1, 1}
358 /* If !TARGET_FPU, then make the fp registers fixed so that they won't
361 #define CONDITIONAL_REGISTER_USAGE \
367 for (regno = 32; regno < 64; regno++) \
368 fixed_regs[regno] = 1; \
370 if (! TARGET_APP_REGS) \
379 /* Return number of consecutive hard regs needed starting at reg REGNO
380 to hold something of mode MODE.
381 This is ordinarily the length in words of a value of mode MODE
382 but can be less for certain modes in special long registers.
384 On SPARC, ordinary registers hold 32 bits worth;
385 this means both integer and floating point registers.
387 We use vectors to keep this information about registers. */
389 /* How many hard registers it takes to make a register of this mode. */
390 extern int hard_regno_nregs
[];
392 #define HARD_REGNO_NREGS(REGNO, MODE) \
393 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
395 /* Value is 1 if register/mode pair is acceptable on sparc. */
396 extern int hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
];
398 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
399 On SPARC, the cpu registers can hold any mode but the float registers
400 can only hold SFmode or DFmode. See sparc.c for how we
402 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
403 ((hard_regno_mode_ok[REGNO] & (1<<(int)(MODE))) != 0)
405 /* Value is 1 if it is a good idea to tie two pseudo registers
406 when one has mode MODE1 and one has mode MODE2.
407 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
408 for any hard reg, then this must be 0 for correct output. */
409 #define MODES_TIEABLE_P(MODE1, MODE2) \
410 ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
412 /* Specify the registers used for certain standard purposes.
413 The values of these macros are register numbers. */
415 /* SPARC pc isn't overloaded on a register that the compiler knows about. */
416 /* #define PC_REGNUM */
418 /* Register to use for pushing function arguments. */
419 #define STACK_POINTER_REGNUM 14
421 /* Actual top-of-stack address is 92 greater than the contents
422 of the stack pointer register. 92 = 68 + 24. 64 bytes reserving space
423 for the ins and local registers, 4 byte for structure return address, and
424 24 bytes for the 6 register parameters. */
425 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(0)
427 /* Base register for access to local variables of the function. */
428 #define FRAME_POINTER_REGNUM 30
431 /* Register that is used for the return address. */
432 #define RETURN_ADDR_REGNUM 15
435 /* Value should be nonzero if functions must have frame pointers.
436 Zero means the frame pointer need not be set up (and parms
437 may be accessed via the stack pointer) in functions that seem suitable.
438 This is computed in `reload', in reload1.c.
440 Used in flow.c, global.c, and reload1.c. */
441 extern int leaf_function
;
443 #define FRAME_POINTER_REQUIRED \
444 (! (leaf_function_p () && only_leaf_regs_used ()))
446 /* C statement to store the difference between the frame pointer
447 and the stack pointer values immediately after the function prologue.
449 Note, we always pretend that this is a leaf function because if
450 it's not, there's no point in trying to eliminate the
451 frame pointer. If it is a leaf function, we guessed right! */
452 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
453 ((VAR) = (TARGET_FRW ? sparc_frw_compute_frame_size (get_frame_size ()) \
454 : compute_frame_size (get_frame_size (), 1)))
456 /* Base register for access to arguments of the function. */
457 #define ARG_POINTER_REGNUM 30
459 /* Register in which static-chain is passed to a function. This must
460 not be a register used by the prologue. */
461 #define STATIC_CHAIN_REGNUM 2
463 /* Register which holds offset table for position-independent
466 #define PIC_OFFSET_TABLE_REGNUM 23
468 #define INITIALIZE_PIC initialize_pic ()
469 #define FINALIZE_PIC finalize_pic ()
471 /* Sparc ABI says that quad-precision floats and all structures are returned
473 #define RETURN_IN_MEMORY(TYPE) \
474 (TYPE_MODE (TYPE) == BLKmode || TYPE_MODE (TYPE) == TFmode)
476 /* Functions which return large structures get the address
477 to place the wanted value at offset 64 from the frame.
478 Must reserve 64 bytes for the in and local registers. */
479 /* Used only in other #defines in this file. */
480 #define STRUCT_VALUE_OFFSET 64
482 #define STRUCT_VALUE \
483 gen_rtx (MEM, Pmode, \
484 gen_rtx (PLUS, Pmode, stack_pointer_rtx, \
485 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
486 #define STRUCT_VALUE_INCOMING \
487 gen_rtx (MEM, Pmode, \
488 gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
489 gen_rtx (CONST_INT, VOIDmode, STRUCT_VALUE_OFFSET)))
491 /* Define the classes of registers for register constraints in the
492 machine description. Also define ranges of constants.
494 One of the classes must always be named ALL_REGS and include all hard regs.
495 If there is more than one class, another class must be named NO_REGS
496 and contain no registers.
498 The name GENERAL_REGS must be the name of a class (or an alias for
499 another name such as ALL_REGS). This is the class of registers
500 that is allowed by "g" or "r" in a register constraint.
501 Also, registers outside this class are allocated only when
502 instructions express preferences for them.
504 The classes must be numbered in nondecreasing order; that is,
505 a larger-numbered class must never be contained completely
506 in a smaller-numbered class.
508 For any two classes, it is very desirable that there be another
509 class that represents their union. */
511 /* The SPARC has two kinds of registers, general and floating point. */
513 enum reg_class
{ NO_REGS
, GENERAL_REGS
, FP_REGS
, ALL_REGS
, LIM_REG_CLASSES
};
515 #define N_REG_CLASSES (int) LIM_REG_CLASSES
517 /* Give names of register classes as strings for dump file. */
519 #define REG_CLASS_NAMES \
520 {"NO_REGS", "GENERAL_REGS", "FP_REGS", "ALL_REGS" }
522 /* Define which registers fit in which classes.
523 This is an initializer for a vector of HARD_REG_SET
524 of length N_REG_CLASSES. */
526 #if 0 && defined (__GNUC__)
527 #define REG_CLASS_CONTENTS {0LL, 0xfffffffeLL, 0xffffffff00000000LL, 0xfffffffffffffffeLL}
529 #define REG_CLASS_CONTENTS {{0, 0}, {-2, 0}, {0, -1}, {-2, -1}}
532 /* The same information, inverted:
533 Return the class number of the smallest class containing
534 reg number REGNO. This could be a conditional expression
535 or could index an array. */
537 #define REGNO_REG_CLASS(REGNO) \
538 ((REGNO) >= 32 ? FP_REGS : (REGNO) == 0 ? NO_REGS : GENERAL_REGS)
540 /* This is the order in which to allocate registers
543 We put %f0/%f1 last among the float registers, so as to make it more
544 likely that a pseudo-register which dies in the float return register
545 will get allocated to the float return register, thus saving a move
546 instruction at the end of the function. */
547 #define REG_ALLOC_ORDER \
548 { 8, 9, 10, 11, 12, 13, 2, 3, \
549 15, 16, 17, 18, 19, 20, 21, 22, \
550 23, 24, 25, 26, 27, 28, 29, 31, \
551 34, 35, 36, 37, 38, 39, \
552 40, 41, 42, 43, 44, 45, 46, 47, \
553 48, 49, 50, 51, 52, 53, 54, 55, \
554 56, 57, 58, 59, 60, 61, 62, 63, \
556 1, 4, 5, 6, 7, 0, 14, 30}
558 /* This is the order in which to allocate registers for
559 leaf functions. If all registers can fit in the "i" registers,
560 then we have the possibility of having a leaf function. */
561 #define REG_LEAF_ALLOC_ORDER \
562 { 2, 3, 24, 25, 26, 27, 28, 29, \
563 15, 8, 9, 10, 11, 12, 13, \
564 16, 17, 18, 19, 20, 21, 22, 23, \
565 34, 35, 36, 37, 38, 39, \
566 40, 41, 42, 43, 44, 45, 46, 47, \
567 48, 49, 50, 51, 52, 53, 54, 55, \
568 56, 57, 58, 59, 60, 61, 62, 63, \
570 1, 4, 5, 6, 7, 0, 14, 30, 31}
572 #define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc ()
574 #define LEAF_REGISTERS \
575 { 1, 1, 1, 1, 1, 1, 1, 1, \
576 0, 0, 0, 0, 0, 0, 1, 0, \
577 0, 0, 0, 0, 0, 0, 0, 0, \
578 1, 1, 1, 1, 1, 1, 0, 1, \
579 1, 1, 1, 1, 1, 1, 1, 1, \
580 1, 1, 1, 1, 1, 1, 1, 1, \
581 1, 1, 1, 1, 1, 1, 1, 1, \
582 1, 1, 1, 1, 1, 1, 1, 1}
584 extern char leaf_reg_remap
[];
585 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO])
586 extern char leaf_reg_backmap
[];
587 #define LEAF_REG_BACKMAP(REGNO) (leaf_reg_backmap[REGNO])
589 /* The class value for index registers, and the one for base regs. */
590 #define INDEX_REG_CLASS GENERAL_REGS
591 #define BASE_REG_CLASS GENERAL_REGS
593 /* Get reg_class from a letter such as appears in the machine description. */
595 #define REG_CLASS_FROM_LETTER(C) \
596 ((C) == 'f' ? FP_REGS : (C) == 'r' ? GENERAL_REGS : NO_REGS)
598 /* The letters I, J, K, L and M in a register constraint string
599 can be used to stand for particular ranges of immediate operands.
600 This macro defines what the ranges are.
601 C is the letter, and VALUE is a constant value.
602 Return 1 if VALUE is in the range specified by C.
604 For SPARC, `I' is used for the range of constants an insn
605 can actually contain.
606 `J' is used for the range which is just zero (since that is R0).
607 `K' is used for constants which can be loaded with a single sethi insn. */
609 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x1000) < 0x2000)
611 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
612 ((C) == 'I' ? (unsigned) ((VALUE) + 0x1000) < 0x2000 \
613 : (C) == 'J' ? (VALUE) == 0 \
614 : (C) == 'K' ? ((VALUE) & 0x3ff) == 0 \
617 /* Similar, but for floating constants, and defining letters G and H.
618 Here VALUE is the CONST_DOUBLE rtx itself. */
620 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
621 ((C) == 'G' ? fp_zero_operand (VALUE) \
622 : (C) == 'H' ? arith_double_operand (VALUE, DImode) \
625 /* Given an rtx X being reloaded into a reg required to be
626 in class CLASS, return the class of reg to actually use.
627 In general this is just CLASS; but on some machines
628 in some cases it is preferable to use a more restrictive class. */
629 /* We can't load constants into FP registers. We can't load any FP constant
630 if an 'E' constraint fails to match it. */
631 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
633 && ((CLASS) == FP_REGS \
634 || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
635 && (HOST_FLOAT_FORMAT != IEEE_FLOAT_FORMAT \
636 || HOST_BITS_PER_INT != BITS_PER_WORD))) \
639 /* Return the register class of a scratch register needed to load IN into
640 a register of class CLASS in MODE.
642 On the SPARC, when PIC, we need a temporary when loading some addresses
645 Also, we need a temporary when loading/storing a HImode/QImode value
646 between memory and the FPU registers. This can happen when combine puts
647 a paradoxical subreg in a float/fix conversion insn. */
649 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
650 (((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode)\
651 && (GET_CODE (IN) == MEM \
652 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
653 && true_regnum (IN) == -1))) ? GENERAL_REGS : NO_REGS)
655 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
656 ((CLASS) == FP_REGS && ((MODE) == HImode || (MODE) == QImode) \
657 && (GET_CODE (IN) == MEM \
658 || ((GET_CODE (IN) == REG || GET_CODE (IN) == SUBREG) \
659 && true_regnum (IN) == -1)) ? GENERAL_REGS : NO_REGS)
661 /* On SPARC it is not possible to directly move data between
662 GENERAL_REGS and FP_REGS. */
663 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
664 (((CLASS1) == FP_REGS && (CLASS2) == GENERAL_REGS) \
665 || ((CLASS1) == GENERAL_REGS && (CLASS2) == FP_REGS))
667 /* Return the stack location to use for secondary memory needed reloads. */
668 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
669 gen_rtx (MEM, MODE, gen_rtx (PLUS, Pmode, frame_pointer_rtx, \
670 GEN_INT (STARTING_FRAME_OFFSET)))
672 /* Return the maximum number of consecutive registers
673 needed to represent mode MODE in a register of class CLASS. */
674 /* On SPARC, this is the size of MODE in words. */
675 #define CLASS_MAX_NREGS(CLASS, MODE) \
676 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
678 /* Stack layout; function entry, exit and calling. */
680 /* Define the number of register that can hold parameters.
681 These two macros are used only in other macro definitions below. */
684 /* Define this if pushing a word on the stack
685 makes the stack pointer a smaller address. */
686 #define STACK_GROWS_DOWNWARD
688 /* Define this if the nominal address of the stack frame
689 is at the high-address end of the local variables;
690 that is, each additional local variable allocated
691 goes at a more negative offset in the frame. */
692 #define FRAME_GROWS_DOWNWARD
694 /* Offset within stack frame to start allocating local variables at.
695 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
696 first local allocated. Otherwise, it is the offset to the BEGINNING
697 of the first local allocated. */
698 /* This is 16 to allow space for one TFmode floating point value. */
699 #define STARTING_FRAME_OFFSET (-16)
701 /* If we generate an insn to push BYTES bytes,
702 this says how many the stack pointer really advances by.
703 On SPARC, don't define this because there are no push insns. */
704 /* #define PUSH_ROUNDING(BYTES) */
706 /* Offset of first parameter from the argument pointer register value.
707 This is 64 for the ins and locals, plus 4 for the struct-return reg
708 even if this function isn't going to use it. */
709 #define FIRST_PARM_OFFSET(FNDECL) (STRUCT_VALUE_OFFSET + UNITS_PER_WORD)
711 /* When a parameter is passed in a register, stack space is still
713 #define REG_PARM_STACK_SPACE(DECL) (NPARM_REGS * UNITS_PER_WORD)
715 /* Keep the stack pointer constant throughout the function.
716 This is both an optimization and a necessity: longjmp
717 doesn't behave itself when the stack pointer moves within
719 #define ACCUMULATE_OUTGOING_ARGS
721 /* Value is the number of bytes of arguments automatically
722 popped when returning from a subroutine call.
723 FUNTYPE is the data type of the function (as a tree),
724 or for a library call it is an identifier node for the subroutine name.
725 SIZE is the number of bytes of arguments passed on the stack. */
727 #define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0
729 /* Some subroutine macros specific to this machine.
730 When !TARGET_FPU, put float return values in the general registers,
731 since we don't have any fp registers. */
732 #define BASE_RETURN_VALUE_REG(MODE) \
733 (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 : 8)
734 #define BASE_OUTGOING_VALUE_REG(MODE) \
735 (((MODE) == SFmode || (MODE) == DFmode) && TARGET_FPU ? 32 \
736 : (TARGET_FRW ? 8 : 24))
737 #define BASE_PASSING_ARG_REG(MODE) (8)
738 #define BASE_INCOMING_ARG_REG(MODE) (TARGET_FRW ? 8 : 24)
740 /* Define this macro if the target machine has "register windows". This
741 C expression returns the register number as seen by the called function
742 corresponding to register number OUT as seen by the calling function.
743 Return OUT if register number OUT is not an outbound register. */
745 #define INCOMING_REGNO(OUT) \
746 ((TARGET_FRW || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16)
748 /* Define this macro if the target machine has "register windows". This
749 C expression returns the register number as seen by the calling function
750 corresponding to register number IN as seen by the called function.
751 Return IN if register number IN is not an inbound register. */
753 #define OUTGOING_REGNO(IN) \
754 ((TARGET_FRW || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16)
756 /* Define how to find the value returned by a function.
757 VALTYPE is the data type of the value (as a tree).
758 If the precise function being called is known, FUNC is its FUNCTION_DECL;
759 otherwise, FUNC is 0. */
761 /* On SPARC the value is found in the first "output" register. */
763 #define FUNCTION_VALUE(VALTYPE, FUNC) \
764 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG (TYPE_MODE (VALTYPE)))
766 /* But the called function leaves it in the first "input" register. */
768 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
769 gen_rtx (REG, TYPE_MODE (VALTYPE), BASE_OUTGOING_VALUE_REG (TYPE_MODE (VALTYPE)))
771 /* Define how to find the value returned by a library function
772 assuming the value has mode MODE. */
774 #define LIBCALL_VALUE(MODE) \
775 gen_rtx (REG, MODE, BASE_RETURN_VALUE_REG (MODE))
777 /* 1 if N is a possible register number for a function value
778 as seen by the caller.
779 On SPARC, the first "output" reg is used for integer values,
780 and the first floating point register is used for floating point values. */
782 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 8 || (N) == 32)
784 /* Define the size of space to allocate for the return value of an
787 #define APPLY_RESULT_SIZE 16
789 /* 1 if N is a possible register number for function argument passing.
790 On SPARC, these are the "output" registers. */
792 #define FUNCTION_ARG_REGNO_P(N) ((N) < 14 && (N) > 7)
794 /* Define a data type for recording info about an argument list
795 during the scan of that argument list. This data type should
796 hold all necessary information about the function itself
797 and about the args processed so far, enough to enable macros
798 such as FUNCTION_ARG to determine where the next arg should go.
800 On SPARC, this is a single integer, which is a number of words
801 of arguments scanned so far (including the invisible argument,
802 if any, which holds the structure-value-address).
803 Thus 7 or more means all following args should go on the stack. */
805 #define CUMULATIVE_ARGS int
807 #define ROUND_ADVANCE(SIZE) \
808 ((SIZE + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
810 /* Initialize a variable CUM of type CUMULATIVE_ARGS
811 for a call to a function whose data type is FNTYPE.
812 For a library call, FNTYPE is 0.
814 On SPARC, the offset always starts at 0: the first parm reg is always
817 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0)
819 /* Update the data in CUM to advance over an argument
820 of mode MODE and data type TYPE.
821 (TYPE is null for libcalls where that information may not be available.) */
823 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
824 ((CUM) += ((MODE) != BLKmode \
825 ? ROUND_ADVANCE (GET_MODE_SIZE (MODE)) \
826 : ROUND_ADVANCE (int_size_in_bytes (TYPE))))
828 /* Determine where to put an argument to a function.
829 Value is zero to push the argument on the stack,
830 or a hard register in which to store the argument.
832 MODE is the argument's machine mode.
833 TYPE is the data type of the argument (as a tree).
834 This is null for libcalls where that information may
836 CUM is a variable of type CUMULATIVE_ARGS which gives info about
837 the preceding args and about the function being called.
838 NAMED is nonzero if this argument is a named parameter
839 (otherwise it is an extra parameter matching an ellipsis). */
841 /* On SPARC the first six args are normally in registers
842 and the rest are pushed. Any arg that starts within the first 6 words
843 is at least partially passed in a register unless its data type forbids. */
845 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
846 ((CUM) < NPARM_REGS \
847 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
848 && ((TYPE)==0 || (MODE) != BLKmode \
849 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
850 ? gen_rtx (REG, (MODE), (BASE_PASSING_ARG_REG (MODE) + (CUM))) \
853 /* Define where a function finds its arguments.
854 This is different from FUNCTION_ARG because of register windows. */
856 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
857 ((CUM) < NPARM_REGS \
858 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
859 && ((TYPE)==0 || (MODE) != BLKmode \
860 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
861 ? gen_rtx (REG, (MODE), (BASE_INCOMING_ARG_REG (MODE) + (CUM))) \
864 /* For an arg passed partly in registers and partly in memory,
865 this is the number of registers used.
866 For args passed entirely in registers or entirely in memory, zero.
867 Any arg that starts in the first 6 regs but won't entirely fit in them
868 needs partial registers on the Sparc. */
870 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
871 ((CUM) < NPARM_REGS \
872 && ((TYPE)==0 || ! TREE_ADDRESSABLE ((tree)(TYPE))) \
873 && ((TYPE)==0 || (MODE) != BLKmode \
874 || (TYPE_ALIGN ((TYPE)) % PARM_BOUNDARY == 0)) \
875 && ((CUM) + ((MODE) == BLKmode \
876 ? ROUND_ADVANCE (int_size_in_bytes (TYPE)) \
877 : ROUND_ADVANCE (GET_MODE_SIZE (MODE))) - NPARM_REGS > 0)\
878 ? (NPARM_REGS - (CUM)) \
881 /* The SPARC ABI stipulates passing struct arguments (of any size) and
882 quad-precision floats by invisible reference.
883 For Pascal, also pass arrays by reference. */
884 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
885 ((TYPE && (TREE_CODE (TYPE) == RECORD_TYPE \
886 || TREE_CODE (TYPE) == UNION_TYPE \
887 || TREE_CODE (TYPE) == ARRAY_TYPE)) \
890 /* Define the information needed to generate branch and scc insns. This is
891 stored from the compare operation. Note that we can't use "rtx" here
892 since it hasn't been defined! */
894 extern struct rtx_def
*sparc_compare_op0
, *sparc_compare_op1
;
896 /* Define the function that build the compare insn for scc and bcc. */
898 extern struct rtx_def
*gen_compare_reg ();
900 /* Generate the special assembly code needed to tell the assembler whatever
901 it might need to know about the return value of a function.
903 For Sparc assemblers, we need to output a .proc pseudo-op which conveys
904 information to the assembler relating to peephole optimization (done in
907 #define ASM_DECLARE_RESULT(FILE, RESULT) \
908 fprintf ((FILE), "\t.proc\t0%o\n", sparc_type_code (TREE_TYPE (RESULT)))
910 /* Output the label for a function definition. */
912 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
914 ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
915 ASM_OUTPUT_LABEL (FILE, NAME); \
918 /* This macro generates the assembly code for function entry.
919 FILE is a stdio stream to output the code to.
920 SIZE is an int: how many units of temporary storage to allocate.
921 Refer to the array `regs_ever_live' to determine which registers
922 to save; `regs_ever_live[I]' is nonzero if register number I
923 is ever used in the function. This macro is responsible for
924 knowing which registers should not be saved even if used. */
926 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
927 of memory. If any fpu reg is used in the function, we allocate
928 such a block here, at the bottom of the frame, just in case it's needed.
930 If this function is a leaf procedure, then we may choose not
931 to do a "save" insn. The decision about whether or not
932 to do this is made in regclass.c. */
934 #define FUNCTION_PROLOGUE(FILE, SIZE) \
935 (TARGET_FRW ? sparc_frw_output_function_prologue (FILE, SIZE, leaf_function)\
936 : output_function_prologue (FILE, SIZE, leaf_function))
938 /* Output assembler code to FILE to increment profiler label # LABELNO
939 for profiling a function entry. */
941 #define FUNCTION_PROFILER(FILE, LABELNO) \
943 fputs ("\tsethi %hi(", (FILE)); \
944 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
945 fputs ("),%o0\n\tcall mcount\n\tor %lo(", (FILE)); \
946 ASM_OUTPUT_INTERNAL_LABELREF (FILE, "LP", LABELNO); \
947 fputs ("),%o0,%o0\n", (FILE)); \
950 /* Output assembler code to FILE to initialize this source file's
951 basic block profiling info, if that has not already been done. */
952 /* FIXME -- this does not parameterize how it generates labels (like the
953 above FUNCTION_PROFILER). Broken on Solaris-2. --gnu@cygnus.com */
955 #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
956 fprintf (FILE, "\tsethi %%hi(LPBX0),%%o0\n\tld [%%lo(LPBX0)+%%o0],%%o1\n\ttst %%o1\n\tbne LPY%d\n\tadd %%o0,%%lo(LPBX0),%%o0\n\tcall ___bb_init_func\n\tnop\nLPY%d:\n", \
957 (LABELNO), (LABELNO))
959 /* Output assembler code to FILE to increment the entry-count for
960 the BLOCKNO'th basic block in this source file. */
962 #define BLOCK_PROFILER(FILE, BLOCKNO) \
964 int blockn = (BLOCKNO); \
965 fprintf (FILE, "\tsethi %%hi(LPBX2+%d),%%g1\n\tld [%%lo(LPBX2+%d)+%%g1],%%g2\n\
966 \tadd %%g2,1,%%g2\n\tst %%g2,[%%lo(LPBX2+%d)+%%g1]\n", \
967 4 * blockn, 4 * blockn, 4 * blockn); \
970 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
971 the stack pointer does not matter. The value is tested only in
972 functions that have frame pointers.
973 No definition is equivalent to always zero. */
975 extern int current_function_calls_alloca
;
976 extern int current_function_outgoing_args_size
;
978 #define EXIT_IGNORE_STACK \
979 (get_frame_size () != 0 \
980 || current_function_calls_alloca || current_function_outgoing_args_size)
982 /* This macro generates the assembly code for function exit,
983 on machines that need it. If FUNCTION_EPILOGUE is not defined
984 then individual return instructions are generated for each
985 return statement. Args are same as for FUNCTION_PROLOGUE.
987 The function epilogue should not depend on the current stack pointer!
988 It should use the frame pointer only. This is mandatory because
989 of alloca; we also take advantage of it to omit stack adjustments
992 /* This declaration is needed due to traditional/ANSI
993 incompatibilities which cannot be #ifdefed away
994 because they occur inside of macros. Sigh. */
995 extern union tree_node
*current_function_decl
;
997 #define FUNCTION_EPILOGUE(FILE, SIZE) \
998 (TARGET_FRW ? sparc_frw_output_function_epilogue (FILE, SIZE, leaf_function)\
999 : output_function_epilogue (FILE, SIZE, leaf_function))
1001 #define DELAY_SLOTS_FOR_EPILOGUE \
1002 (TARGET_FRW ? sparc_frw_epilogue_delay_slots () : 1)
1003 #define ELIGIBLE_FOR_EPILOGUE_DELAY(trial, slots_filled) \
1004 (TARGET_FRW ? sparc_frw_eligible_for_epilogue_delay (trial, slots_filled) \
1005 : eligible_for_epilogue_delay (trial, slots_filled))
1007 /* Output assembler code for a block containing the constant parts
1008 of a trampoline, leaving space for the variable parts. */
1010 /* On the sparc, the trampoline contains five instructions:
1011 sethi #TOP_OF_FUNCTION,%g1
1012 or #BOTTOM_OF_FUNCTION,%g1,%g1
1013 sethi #TOP_OF_STATIC,%g2
1015 or #BOTTOM_OF_STATIC,%g2,%g2 */
1016 #define TRAMPOLINE_TEMPLATE(FILE) \
1018 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1019 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1020 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1021 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x81C04000)); \
1022 ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1025 /* Length in units of the trampoline for entering a nested function. */
1027 #define TRAMPOLINE_SIZE 20
1029 /* Emit RTL insns to initialize the variable parts of a trampoline.
1030 FNADDR is an RTX for the address of the function's pure code.
1031 CXT is an RTX for the static chain value for the function.
1033 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
1034 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
1035 (to store insns). This is a bit excessive. Perhaps a different
1036 mechanism would be better here.
1038 Emit 3 FLUSH instructions (UNSPEC_VOLATILE 2) to synchonize the data
1039 and instruction caches. */
1041 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1043 rtx high_cxt = expand_shift (RSHIFT_EXPR, SImode, CXT, \
1044 size_int (10), 0, 1); \
1045 rtx high_fn = expand_shift (RSHIFT_EXPR, SImode, FNADDR, \
1046 size_int (10), 0, 1); \
1047 rtx low_cxt = expand_and (CXT, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1048 rtx low_fn = expand_and (FNADDR, gen_rtx (CONST_INT, VOIDmode, 0x3ff), 0); \
1049 rtx g1_sethi = gen_rtx (HIGH, SImode, \
1050 gen_rtx (CONST_INT, VOIDmode, 0x03000000)); \
1051 rtx g2_sethi = gen_rtx (HIGH, SImode, \
1052 gen_rtx (CONST_INT, VOIDmode, 0x05000000)); \
1053 rtx g1_ori = gen_rtx (HIGH, SImode, \
1054 gen_rtx (CONST_INT, VOIDmode, 0x82106000)); \
1055 rtx g2_ori = gen_rtx (HIGH, SImode, \
1056 gen_rtx (CONST_INT, VOIDmode, 0x8410A000)); \
1057 rtx tem = gen_reg_rtx (SImode); \
1058 emit_move_insn (tem, g1_sethi); \
1059 emit_insn (gen_iorsi3 (high_fn, high_fn, tem)); \
1060 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 0)), high_fn);\
1061 emit_move_insn (tem, g1_ori); \
1062 emit_insn (gen_iorsi3 (low_fn, low_fn, tem)); \
1063 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), low_fn);\
1064 emit_move_insn (tem, g2_sethi); \
1065 emit_insn (gen_iorsi3 (high_cxt, high_cxt, tem)); \
1066 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 8)), high_cxt);\
1067 emit_move_insn (tem, g2_ori); \
1068 emit_insn (gen_iorsi3 (low_cxt, low_cxt, tem)); \
1069 emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 16)), low_cxt);\
1070 emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1071 gen_rtvec (1, plus_constant (TRAMP, 0)), \
1073 emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1074 gen_rtvec (1, plus_constant (TRAMP, 8)), \
1076 emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode, \
1077 gen_rtvec (1, plus_constant (TRAMP, 16)), \
1081 /* Generate necessary RTL for __builtin_saveregs().
1082 ARGLIST is the argument list; see expr.c. */
1083 extern struct rtx_def
*sparc_builtin_saveregs ();
1084 #define EXPAND_BUILTIN_SAVEREGS(ARGLIST) sparc_builtin_saveregs (ARGLIST)
1086 /* Generate RTL to flush the register windows so as to make arbitrary frames
1088 #define SETUP_FRAME_ADDRESSES() \
1089 emit_insn (gen_flush_register_windows ())
1091 /* Given an rtx for the address of a frame,
1092 return an rtx for the address of the word in the frame
1093 that holds the dynamic chain--the previous frame's address. */
1094 #define DYNAMIC_CHAIN_ADDRESS(frame) \
1095 gen_rtx (PLUS, Pmode, frame, gen_rtx (CONST_INT, VOIDmode, 56))
1097 /* The return address isn't on the stack, it is in a register, so we can't
1098 access it from the current frame pointer. We can access it from the
1099 previous frame pointer though by reading a value from the register window
1101 #define RETURN_ADDR_IN_PREVIOUS_FRAME
1103 /* The current return address is in %i7. The return address of anything
1104 farther back is in the register window save area at [%fp+60]. */
1105 /* ??? This ignores the fact that the actual return address is +8 for normal
1106 returns, and +12 for structure returns. */
1107 #define RETURN_ADDR_RTX(count, frame) \
1109 ? gen_rtx (REG, Pmode, 31) \
1110 : copy_to_reg (gen_rtx (MEM, Pmode, \
1111 memory_address (Pmode, plus_constant (frame, 60)))))
1113 /* Addressing modes, and classification of registers for them. */
1115 /* #define HAVE_POST_INCREMENT */
1116 /* #define HAVE_POST_DECREMENT */
1118 /* #define HAVE_PRE_DECREMENT */
1119 /* #define HAVE_PRE_INCREMENT */
1121 /* Macros to check register numbers against specific register classes. */
1123 /* These assume that REGNO is a hard or pseudo reg number.
1124 They give nonzero only if REGNO is a hard reg of the suitable class
1125 or a pseudo reg currently allocated to a suitable hard reg.
1126 Since they use reg_renumber, they are safe only once reg_renumber
1127 has been allocated, which happens in local-alloc.c. */
1129 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1130 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1131 #define REGNO_OK_FOR_BASE_P(REGNO) \
1132 (((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) && (REGNO) != 0)
1133 #define REGNO_OK_FOR_FP_P(REGNO) \
1134 (((REGNO) ^ 0x20) < 32 \
1135 || (((REGNO) != 0) && (unsigned) (reg_renumber[REGNO] ^ 0x20) < 32))
1137 /* Now macros that check whether X is a register and also,
1138 strictly, whether it is in a specified class.
1140 These macros are specific to the SPARC, and may be used only
1141 in code for printing assembler insns and in conditions for
1142 define_optimization. */
1144 /* 1 if X is an fp register. */
1146 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1148 /* Maximum number of registers that can appear in a valid memory address. */
1150 #define MAX_REGS_PER_ADDRESS 2
1152 /* Recognize any constant value that is a valid address.
1153 When PIC, we do not accept an address that would require a scratch reg
1154 to load into a register. */
1156 #define CONSTANT_ADDRESS_P(X) \
1157 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1158 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
1159 || (GET_CODE (X) == CONST \
1160 && ! (flag_pic && pic_address_needs_scratch (X))))
1162 /* Define this, so that when PIC, reload won't try to reload invalid
1163 addresses which require two reload registers. */
1165 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
1167 /* Nonzero if the constant value X is a legitimate general operand.
1168 Anything can be made to work except floating point constants. */
1170 #define LEGITIMATE_CONSTANT_P(X) \
1171 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode)
1173 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1174 and check its validity for a certain class.
1175 We have two alternate definitions for each of them.
1176 The usual definition accepts all pseudo regs; the other rejects
1177 them unless they have been allocated suitable hard regs.
1178 The symbol REG_OK_STRICT causes the latter definition to be used.
1180 Most source files want to accept pseudo regs in the hope that
1181 they will get allocated to the class that the insn wants them to be in.
1182 Source files for reload pass need to be strict.
1183 After reload, it makes no difference, since pseudo regs have
1184 been eliminated by then. */
1186 /* Optional extra constraints for this machine. Borrowed from romp.h.
1188 For the SPARC, `Q' means that this is a memory operand but not a
1189 symbolic memory operand. Note that an unassigned pseudo register
1190 is such a memory operand. Needed because reload will generate
1191 these things in insns and then not re-recognize the insns, causing
1192 constrain_operands to fail.
1194 `S' handles constraints for calls. */
1196 #ifndef REG_OK_STRICT
1198 /* Nonzero if X is a hard reg that can be used as an index
1199 or if it is a pseudo reg. */
1200 #define REG_OK_FOR_INDEX_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1201 /* Nonzero if X is a hard reg that can be used as a base reg
1202 or if it is a pseudo reg. */
1203 #define REG_OK_FOR_BASE_P(X) (((unsigned) REGNO (X)) - 32 >= 32 && REGNO (X) != 0)
1205 #define EXTRA_CONSTRAINT(OP, C) \
1207 ? ((GET_CODE (OP) == MEM \
1208 && memory_address_p (GET_MODE (OP), XEXP (OP, 0)) \
1209 && ! symbolic_memory_operand (OP, VOIDmode)) \
1210 || (reload_in_progress && GET_CODE (OP) == REG \
1211 && REGNO (OP) >= FIRST_PSEUDO_REGISTER)) \
1213 ? (mem_aligned_8 (OP)) \
1215 ? (register_ok_for_ldd (OP)) \
1220 /* Nonzero if X is a hard reg that can be used as an index. */
1221 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1222 /* Nonzero if X is a hard reg that can be used as a base reg. */
1223 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1225 #define EXTRA_CONSTRAINT(OP, C) \
1227 ? (GET_CODE (OP) == REG \
1228 ? (REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1229 && reg_renumber[REGNO (OP)] < 0) \
1230 : GET_CODE (OP) == MEM) \
1232 ? mem_aligned_8 (OP) && strict_memory_address_p (Pmode, XEXP (OP, 0)) \
1234 ? (GET_CODE (OP) == REG \
1235 && (REGNO (OP) < FIRST_PSEUDO_REGISTER \
1236 || reg_renumber[REGNO (OP)] > 0) \
1237 && register_ok_for_ldd (OP)) : 0)
1240 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1241 that is a valid memory address for an instruction.
1242 The MODE argument is the machine mode for the MEM expression
1243 that wants to use this address.
1245 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
1246 ordinarily. This changes a bit when generating PIC.
1248 If you change this, execute "rm explow.o recog.o reload.o". */
1250 #define RTX_OK_FOR_BASE_P(X) \
1251 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1252 || (GET_CODE (X) == SUBREG \
1253 && GET_CODE (SUBREG_REG (X)) == REG \
1254 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
1256 #define RTX_OK_FOR_INDEX_P(X) \
1257 ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1258 || (GET_CODE (X) == SUBREG \
1259 && GET_CODE (SUBREG_REG (X)) == REG \
1260 && REG_OK_FOR_INDEX_P (SUBREG_REG (X))))
1262 #define RTX_OK_FOR_OFFSET_P(X) \
1263 (GET_CODE (X) == CONST_INT && INTVAL (X) >= -0x1000 && INTVAL (X) < 0x1000)
1265 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1266 { if (RTX_OK_FOR_BASE_P (X)) \
1268 else if (GET_CODE (X) == PLUS) \
1270 register rtx op0 = XEXP (X, 0); \
1271 register rtx op1 = XEXP (X, 1); \
1272 if (flag_pic && op0 == pic_offset_table_rtx) \
1274 if (RTX_OK_FOR_BASE_P (op1)) \
1276 else if (flag_pic == 1 \
1277 && GET_CODE (op1) != REG \
1278 && GET_CODE (op1) != LO_SUM \
1279 && GET_CODE (op1) != MEM \
1280 && (GET_CODE (op1) != CONST_INT \
1281 || SMALL_INT (op1))) \
1284 else if (RTX_OK_FOR_BASE_P (op0)) \
1286 if (RTX_OK_FOR_INDEX_P (op1) \
1287 || RTX_OK_FOR_OFFSET_P (op1)) \
1290 else if (RTX_OK_FOR_BASE_P (op1)) \
1292 if (RTX_OK_FOR_INDEX_P (op0) \
1293 || RTX_OK_FOR_OFFSET_P (op0)) \
1297 else if (GET_CODE (X) == LO_SUM) \
1299 register rtx op0 = XEXP (X, 0); \
1300 register rtx op1 = XEXP (X, 1); \
1301 if (RTX_OK_FOR_BASE_P (op0) \
1302 && CONSTANT_P (op1)) \
1305 else if (GET_CODE (X) == CONST_INT && SMALL_INT (X)) \
1309 /* Try machine-dependent ways of modifying an illegitimate address
1310 to be legitimate. If we find one, return the new, valid address.
1311 This macro is used in only one place: `memory_address' in explow.c.
1313 OLDX is the address as it was before break_out_memory_refs was called.
1314 In some cases it is useful to look at this to decide what needs to be done.
1316 MODE and WIN are passed so that this macro can use
1317 GO_IF_LEGITIMATE_ADDRESS.
1319 It is always safe for this macro to do nothing. It exists to recognize
1320 opportunities to optimize the output. */
1322 /* On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
1323 extern struct rtx_def
*legitimize_pic_address ();
1324 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1325 { rtx sparc_x = (X); \
1326 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \
1327 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1328 force_operand (XEXP (X, 0), NULL_RTX)); \
1329 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == MULT) \
1330 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1331 force_operand (XEXP (X, 1), NULL_RTX)); \
1332 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == PLUS) \
1333 (X) = gen_rtx (PLUS, Pmode, force_operand (XEXP (X, 0), NULL_RTX),\
1335 if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 1)) == PLUS) \
1336 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1337 force_operand (XEXP (X, 1), NULL_RTX)); \
1338 if (sparc_x != (X) && memory_address_p (MODE, X)) \
1340 if (flag_pic) (X) = legitimize_pic_address (X, MODE, 0); \
1341 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 1))) \
1342 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 0), \
1343 copy_to_mode_reg (Pmode, XEXP (X, 1))); \
1344 else if (GET_CODE (X) == PLUS && CONSTANT_ADDRESS_P (XEXP (X, 0))) \
1345 (X) = gen_rtx (PLUS, Pmode, XEXP (X, 1), \
1346 copy_to_mode_reg (Pmode, XEXP (X, 0))); \
1347 else if (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST \
1348 || GET_CODE (X) == LABEL_REF) \
1349 (X) = gen_rtx (LO_SUM, Pmode, \
1350 copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode, X)), X); \
1351 if (memory_address_p (MODE, X)) \
1354 /* Go to LABEL if ADDR (a legitimate address expression)
1355 has an effect that depends on the machine mode it is used for.
1356 On the SPARC this is never true. */
1358 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1360 /* Specify the machine mode that this machine uses
1361 for the index in the tablejump instruction. */
1362 #define CASE_VECTOR_MODE SImode
1364 /* Define this if the tablejump instruction expects the table
1365 to contain offsets from the address of the table.
1366 Do not define this if the table should contain absolute addresses. */
1367 /* #define CASE_VECTOR_PC_RELATIVE */
1369 /* Specify the tree operation to be used to convert reals to integers. */
1370 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1372 /* This is the kind of divide that is easiest to do in the general case. */
1373 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1375 /* Define this as 1 if `char' should by default be signed; else as 0. */
1376 #define DEFAULT_SIGNED_CHAR 1
1378 /* Max number of bytes we can move from memory to memory
1379 in one reasonably fast instruction. */
1382 #if 0 /* Sun 4 has matherr, so this is no good. */
1383 /* This is the value of the error code EDOM for this machine,
1384 used by the sqrt instruction. */
1385 #define TARGET_EDOM 33
1387 /* This is how to refer to the variable errno. */
1388 #define GEN_ERRNO_RTX \
1389 gen_rtx (MEM, SImode, gen_rtx (SYMBOL_REF, Pmode, "errno"))
1392 /* Define if operations between registers always perform the operation
1393 on the full register even if a narrower mode is specified. */
1394 #define WORD_REGISTER_OPERATIONS
1396 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1397 will either zero-extend or sign-extend. The value of this macro should
1398 be the code that says which one of the two operations is implicitly
1399 done, NIL if none. */
1400 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1402 /* Nonzero if access to memory by bytes is slow and undesirable.
1403 For RISC chips, it means that access to memory by bytes is no
1404 better than access by words when possible, so grab a whole word
1405 and maybe make use of that. */
1406 #define SLOW_BYTE_ACCESS 1
1408 /* We assume that the store-condition-codes instructions store 0 for false
1409 and some other value for true. This is the value stored for true. */
1411 #define STORE_FLAG_VALUE 1
1413 /* When a prototype says `char' or `short', really pass an `int'. */
1414 #define PROMOTE_PROTOTYPES
1416 /* Define this to be nonzero if shift instructions ignore all but the low-order
1418 #define SHIFT_COUNT_TRUNCATED 1
1420 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1421 is done just by pretending it is already truncated. */
1422 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1424 /* Specify the machine mode that pointers have.
1425 After generation of rtl, the compiler makes no further distinction
1426 between pointers and any other objects of this machine mode. */
1427 #define Pmode SImode
1429 /* Generate calls to memcpy, memcmp and memset. */
1430 #define TARGET_MEM_FUNCTIONS
1432 /* Add any extra modes needed to represent the condition code.
1434 On the Sparc, we have a "no-overflow" mode which is used when an add or
1435 subtract insn is used to set the condition code. Different branches are
1436 used in this case for some operations.
1438 We also have two modes to indicate that the relevant condition code is
1439 in the floating-point condition code register. One for comparisons which
1440 will generate an exception if the result is unordered (CCFPEmode) and
1441 one for comparisons which will never trap (CCFPmode). This really should
1442 be a separate register, but we don't want to go to 65 registers. */
1443 #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode, CCFPEmode
1445 /* Define the names for the modes specified above. */
1446 #define EXTRA_CC_NAMES "CC_NOOV", "CCFP", "CCFPE"
1448 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1449 return the mode to be used for the comparison. For floating-point,
1450 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand is a
1451 PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
1452 processing is needed. */
1453 #define SELECT_CC_MODE(OP,X,Y) \
1454 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1455 ? ((OP == EQ || OP == NE) ? CCFPmode : CCFPEmode) \
1456 : ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1457 || GET_CODE (X) == NEG || GET_CODE (X) == ASHIFT) \
1458 ? CC_NOOVmode : CCmode))
1460 /* Return non-zero if SELECT_CC_MODE will never return MODE for a
1461 floating point inequality comparison. */
1463 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
1465 /* A function address in a call instruction
1466 is a byte address (for indexing purposes)
1467 so give the MEM rtx a byte's mode. */
1468 #define FUNCTION_MODE SImode
1470 /* Define this if addresses of constant functions
1471 shouldn't be put through pseudo regs where they can be cse'd.
1472 Desirable on machines where ordinary constants are expensive
1473 but a CALL with constant address is cheap. */
1474 #define NO_FUNCTION_CSE
1476 /* alloca should avoid clobbering the old register save area. */
1477 #define SETJMP_VIA_SAVE_AREA
1479 /* Define subroutines to call to handle multiply and divide.
1480 Use the subroutines that Sun's library provides.
1481 The `*' prevents an underscore from being prepended by the compiler. */
1483 #define DIVSI3_LIBCALL "*.div"
1484 #define UDIVSI3_LIBCALL "*.udiv"
1485 #define MODSI3_LIBCALL "*.rem"
1486 #define UMODSI3_LIBCALL "*.urem"
1487 /* .umul is a little faster than .mul. */
1488 #define MULSI3_LIBCALL "*.umul"
1490 /* Compute the cost of computing a constant rtl expression RTX
1491 whose rtx-code is CODE. The body of this macro is a portion
1492 of a switch statement. If the code is computed here,
1493 return it with a return statement. Otherwise, break from the switch. */
1495 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1497 if (INTVAL (RTX) < 0x1000 && INTVAL (RTX) >= -0x1000) \
1505 case CONST_DOUBLE: \
1506 if (GET_MODE (RTX) == DImode) \
1507 if ((XINT (RTX, 3) == 0 \
1508 && (unsigned) XINT (RTX, 2) < 0x1000) \
1509 || (XINT (RTX, 3) == -1 \
1510 && XINT (RTX, 2) < 0 \
1511 && XINT (RTX, 2) >= -0x1000)) \
1515 /* Compute the cost of an address. For the sparc, all valid addresses are
1518 #define ADDRESS_COST(RTX) 1
1520 /* Compute extra cost of moving data between one register class
1522 #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
1523 (((CLASS1 == FP_REGS && CLASS2 == GENERAL_REGS) \
1524 || (CLASS1 == GENERAL_REGS && CLASS2 == FP_REGS)) ? 6 : 2)
1526 /* Provide the costs of a rtl expression. This is in the body of a
1527 switch on CODE. The purpose for the cost of MULT is to encourage
1528 `synth_mult' to find a synthetic multiply when reasonable.
1530 If we need more than 12 insns to do a multiply, then go out-of-line,
1531 since the call overhead will be < 10% of the cost of the multiply. */
1533 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1535 return TARGET_V8 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25); \
1540 return COSTS_N_INSNS (25); \
1541 /* Make FLOAT and FIX more expensive than CONST_DOUBLE,\
1542 so that cse will favor the latter. */ \
1547 /* Conditional branches with empty delay slots have a length of two. */
1548 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1549 if (GET_CODE (INSN) == CALL_INSN \
1550 || (GET_CODE (INSN) == JUMP_INSN && ! simplejump_p (insn))) \
1553 /* Control the assembler format that we output. */
1555 /* Output at beginning of assembler file. */
1557 #define ASM_FILE_START(file)
1559 /* Output to assembler file text saying following lines
1560 may contain character constants, extra white space, comments, etc. */
1562 #define ASM_APP_ON ""
1564 /* Output to assembler file text saying following lines
1565 no longer contain unusual constructs. */
1567 #define ASM_APP_OFF ""
1569 #define ASM_LONG ".word"
1570 #define ASM_SHORT ".half"
1571 #define ASM_BYTE_OP ".byte"
1573 /* Output before read-only data. */
1575 #define TEXT_SECTION_ASM_OP ".text"
1577 /* Output before writable data. */
1579 #define DATA_SECTION_ASM_OP ".data"
1581 /* How to refer to registers in assembler output.
1582 This sequence is indexed by compiler's hard-register-number (see above). */
1584 #define REGISTER_NAMES \
1585 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \
1586 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \
1587 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \
1588 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \
1589 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \
1590 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \
1591 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \
1592 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31"}
1594 /* Define additional names for use in asm clobbers and asm declarations.
1596 We define the fake Condition Code register as an alias for reg 0 (which
1597 is our `condition code' register), so that condition codes can easily
1598 be clobbered by an asm. No such register actually exists. Condition
1599 codes are partly stored in the PSR and partly in the FSR. */
1601 #define ADDITIONAL_REGISTER_NAMES {"ccr", 0, "cc", 0}
1603 /* How to renumber registers for dbx and gdb. */
1605 #define DBX_REGISTER_NUMBER(REGNO) (REGNO)
1607 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1608 since the length can run past this up to a continuation point. */
1609 #define DBX_CONTIN_LENGTH 1500
1611 /* This is how to output a note to DBX telling it the line number
1612 to which the following sequence of instructions corresponds.
1614 This is needed for SunOS 4.0, and should not hurt for 3.2
1616 #define ASM_OUTPUT_SOURCE_LINE(file, line) \
1617 { static int sym_lineno = 1; \
1618 fprintf (file, ".stabn 68,0,%d,LM%d\nLM%d:\n", \
1619 line, sym_lineno, sym_lineno); \
1622 /* This is how to output the definition of a user-level label named NAME,
1623 such as the label on a static function or variable NAME. */
1625 #define ASM_OUTPUT_LABEL(FILE,NAME) \
1626 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1628 /* This is how to output a command to make the user-level label named NAME
1629 defined for reference from other files. */
1631 #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1632 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
1634 /* This is how to output a reference to a user-level label named NAME.
1635 `assemble_name' uses this. */
1637 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1638 fprintf (FILE, "_%s", NAME)
1640 /* This is how to output a definition of an internal numbered label where
1641 PREFIX is the class of label and NUM is the number within the class. */
1643 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1644 fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1646 /* This is how to output a reference to an internal numbered label where
1647 PREFIX is the class of label and NUM is the number within the class. */
1648 /* FIXME: This should be used throughout gcc, and documented in the texinfo
1649 files. There is no reason you should have to allocate a buffer and
1650 `sprintf' to reference an internal label (as opposed to defining it). */
1652 #define ASM_OUTPUT_INTERNAL_LABELREF(FILE,PREFIX,NUM) \
1653 fprintf (FILE, "%s%d", PREFIX, NUM)
1655 /* This is how to store into the string LABEL
1656 the symbol_ref name of an internal numbered label where
1657 PREFIX is the class of label and NUM is the number within the class.
1658 This is suitable for output with `assemble_name'. */
1660 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1661 sprintf (LABEL, "*%s%d", PREFIX, NUM)
1663 /* This is how to output an assembler line defining a `double' constant. */
1665 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1668 REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), t); \
1669 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1670 ASM_LONG, t[0], ASM_LONG, t[1]); \
1673 /* This is how to output an assembler line defining a `float' constant. */
1675 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1678 REAL_VALUE_TO_TARGET_SINGLE ((VALUE), t); \
1679 fprintf (FILE, "\t%s\t0x%lx\n", ASM_LONG, t); \
1682 /* This is how to output an assembler line defining a `long double'
1685 #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \
1688 REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), t); \
1689 fprintf (FILE, "\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n\t%s\t0x%lx\n", \
1690 ASM_LONG, t[0], ASM_LONG, t[1], ASM_LONG, t[2], ASM_LONG, t[3]); \
1693 /* This is how to output an assembler line defining an `int' constant. */
1695 #define ASM_OUTPUT_INT(FILE,VALUE) \
1696 ( fprintf (FILE, "\t%s\t", ASM_LONG), \
1697 output_addr_const (FILE, (VALUE)), \
1698 fprintf (FILE, "\n"))
1700 /* This is how to output an assembler line defining a DImode constant. */
1701 #define ASM_OUTPUT_DOUBLE_INT(FILE,VALUE) \
1702 output_double_int (FILE, VALUE)
1704 /* Likewise for `char' and `short' constants. */
1706 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1707 ( fprintf (FILE, "\t%s\t", ASM_SHORT), \
1708 output_addr_const (FILE, (VALUE)), \
1709 fprintf (FILE, "\n"))
1711 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1712 ( fprintf (FILE, "\t%s\t", ASM_BYTE_OP), \
1713 output_addr_const (FILE, (VALUE)), \
1714 fprintf (FILE, "\n"))
1716 /* This is how to output an assembler line for a numeric constant byte. */
1718 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1719 fprintf (FILE, "\t%s\t0x%x\n", ASM_BYTE_OP, (VALUE))
1721 /* This is how to output an element of a case-vector that is absolute. */
1723 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1726 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1727 fprintf (FILE, "\t.word\t"); \
1728 assemble_name (FILE, label); \
1729 fprintf (FILE, "\n"); \
1732 /* This is how to output an element of a case-vector that is relative.
1733 (SPARC uses such vectors only when generating PIC.) */
1735 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1738 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \
1739 fprintf (FILE, "\t.word\t"); \
1740 assemble_name (FILE, label); \
1741 fprintf (FILE, "-1b\n"); \
1744 /* This is how to output an assembler line
1745 that says to advance the location counter
1746 to a multiple of 2**LOG bytes. */
1748 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1750 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1752 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1753 fprintf (FILE, "\t.skip %u\n", (SIZE))
1755 /* This says how to output an assembler line
1756 to define a global common symbol. */
1758 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1759 ( fputs ("\t.common ", (FILE)), \
1760 assemble_name ((FILE), (NAME)), \
1761 fprintf ((FILE), ",%u,\"bss\"\n", (SIZE)))
1763 /* This says how to output an assembler line to define a local common
1766 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1767 ( fputs ("\t.reserve ", (FILE)), \
1768 assemble_name ((FILE), (NAME)), \
1769 fprintf ((FILE), ",%u,\"bss\",%u\n", \
1770 (SIZE), ((ALIGNED) / BITS_PER_UNIT)))
1772 /* Store in OUTPUT a string (made with alloca) containing
1773 an assembler-name for a local static variable named NAME.
1774 LABELNO is an integer which is different for each call. */
1776 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1777 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1778 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1780 #define IDENT_ASM_OP ".ident"
1782 /* Output #ident as a .ident. */
1784 #define ASM_OUTPUT_IDENT(FILE, NAME) \
1785 fprintf (FILE, "\t%s\t\"%s\"\n", IDENT_ASM_OP, NAME);
1787 /* Define the parentheses used to group arithmetic operations
1788 in assembler code. */
1790 #define ASM_OPEN_PAREN "("
1791 #define ASM_CLOSE_PAREN ")"
1793 /* Define results of standard character escape sequences. */
1794 #define TARGET_BELL 007
1795 #define TARGET_BS 010
1796 #define TARGET_TAB 011
1797 #define TARGET_NEWLINE 012
1798 #define TARGET_VT 013
1799 #define TARGET_FF 014
1800 #define TARGET_CR 015
1802 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1803 ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(')
1805 /* Print operand X (an rtx) in assembler syntax to file FILE.
1806 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1807 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1809 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1811 /* Print a memory address as an operand to reference that memory location. */
1813 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1814 { register rtx base, index = 0; \
1816 register rtx addr = ADDR; \
1817 if (GET_CODE (addr) == REG) \
1818 fputs (reg_names[REGNO (addr)], FILE); \
1819 else if (GET_CODE (addr) == PLUS) \
1821 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1822 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);\
1823 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1824 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);\
1826 base = XEXP (addr, 0), index = XEXP (addr, 1); \
1827 fputs (reg_names[REGNO (base)], FILE); \
1829 fprintf (FILE, "%+d", offset); \
1830 else if (GET_CODE (index) == REG) \
1831 fprintf (FILE, "+%s", reg_names[REGNO (index)]); \
1832 else if (GET_CODE (index) == SYMBOL_REF) \
1833 fputc ('+', FILE), output_addr_const (FILE, index); \
1836 else if (GET_CODE (addr) == MINUS \
1837 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) \
1839 output_addr_const (FILE, XEXP (addr, 0)); \
1840 fputs ("-(", FILE); \
1841 output_addr_const (FILE, XEXP (addr, 1)); \
1842 fputs ("-.)", FILE); \
1844 else if (GET_CODE (addr) == LO_SUM) \
1846 output_operand (XEXP (addr, 0), 0); \
1847 fputs ("+%lo(", FILE); \
1848 output_address (XEXP (addr, 1)); \
1849 fputc (')', FILE); \
1851 else if (flag_pic && GET_CODE (addr) == CONST \
1852 && GET_CODE (XEXP (addr, 0)) == MINUS \
1853 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST \
1854 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS \
1855 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) \
1857 addr = XEXP (addr, 0); \
1858 output_addr_const (FILE, XEXP (addr, 0)); \
1859 /* Group the args of the second CONST in parenthesis. */ \
1860 fputs ("-(", FILE); \
1861 /* Skip past the second CONST--it does nothing for us. */\
1862 output_addr_const (FILE, XEXP (XEXP (addr, 1), 0)); \
1863 /* Close the parenthesis. */ \
1864 fputc (')', FILE); \
1868 output_addr_const (FILE, addr); \
1872 /* Declare functions defined in sparc.c and used in templates. */
1874 extern char *singlemove_string ();
1875 extern char *output_move_double ();
1876 extern char *output_move_quad ();
1877 extern char *output_fp_move_double ();
1878 extern char *output_fp_move_quad ();
1879 extern char *output_block_move ();
1880 extern char *output_scc_insn ();
1881 extern char *output_cbranch ();
1882 extern char *output_return ();
1884 /* Defined in flags.h, but insn-emit.c does not include flags.h. */
1886 extern int flag_pic
;