1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-96, 1997 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
40 /* 1 if the caller has placed an "unimp" insn immediately after the call.
41 This is used in v8 code when calling a function that returns a structure.
42 v9 doesn't have this. Be careful to have this test be the same as that
45 #define SKIP_CALLERS_UNIMP_P \
46 (!TARGET_ARCH64 && current_function_returns_struct \
47 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
48 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
51 /* Global variables for machine-dependent things. */
53 /* Size of frame. Need to know this to emit return insns from leaf procedures.
54 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
55 reload pass. This is important as the value is later used in insn
56 scheduling (to see what can go in a delay slot).
57 APPARENT_FSIZE is the size of the stack less the register save area and less
58 the outgoing argument area. It is used when saving call preserved regs. */
59 static int apparent_fsize
;
60 static int actual_fsize
;
62 /* Save the operands last given to a compare for use when we
63 generate a scc or bcc insn. */
65 rtx sparc_compare_op0
, sparc_compare_op1
;
67 /* We may need an epilogue if we spill too many registers.
68 If this is non-zero, then we branch here for the epilogue. */
69 static rtx leaf_label
;
73 /* Vector to say how input registers are mapped to output
74 registers. FRAME_POINTER_REGNUM cannot be remapped by
75 this function to eliminate it. You must use -fomit-frame-pointer
77 char leaf_reg_remap
[] =
78 { 0, 1, 2, 3, 4, 5, 6, 7,
79 -1, -1, -1, -1, -1, -1, 14, -1,
80 -1, -1, -1, -1, -1, -1, -1, -1,
81 8, 9, 10, 11, 12, 13, -1, 15,
83 32, 33, 34, 35, 36, 37, 38, 39,
84 40, 41, 42, 43, 44, 45, 46, 47,
85 48, 49, 50, 51, 52, 53, 54, 55,
86 56, 57, 58, 59, 60, 61, 62, 63,
87 64, 65, 66, 67, 68, 69, 70, 71,
88 72, 73, 74, 75, 76, 77, 78, 79,
89 80, 81, 82, 83, 84, 85, 86, 87,
90 88, 89, 90, 91, 92, 93, 94, 95,
95 /* Name of where we pretend to think the frame pointer points.
96 Normally, this is "%fp", but if we are in a leaf procedure,
97 this is "%sp+something". We record "something" separately as it may be
98 too big for reg+constant addressing. */
100 static char *frame_base_name
;
101 static int frame_base_offset
;
103 static rtx pic_setup_code
PROTO((void));
104 static rtx find_addr_reg
PROTO((rtx
));
105 static void sparc_init_modes
PROTO((void));
106 static int save_regs
PROTO((FILE *, int, int, char *,
108 static int restore_regs
PROTO((FILE *, int, int, char *, int, int));
109 static void build_big_number
PROTO((FILE *, int, char *));
110 static function_arg_slotno
PROTO((const CUMULATIVE_ARGS
*,
111 enum machine_mode
, tree
, int, int,
114 #ifdef DWARF2_DEBUGGING_INFO
115 extern char *dwarf2out_cfi_label ();
118 /* Option handling. */
120 /* Code model option as passed by user. */
121 char *sparc_cmodel_string
;
123 enum cmodel sparc_cmodel
;
125 /* Record alignment options as passed by user. */
126 char *sparc_align_loops_string
;
127 char *sparc_align_jumps_string
;
128 char *sparc_align_funcs_string
;
130 /* Parsed values, as a power of two. */
131 int sparc_align_loops
;
132 int sparc_align_jumps
;
133 int sparc_align_funcs
;
135 struct sparc_cpu_select sparc_select
[] =
137 /* switch name, tune arch */
138 { (char *)0, "default", 1, 1 },
139 { (char *)0, "-mcpu=", 1, 1 },
140 { (char *)0, "-mtune=", 1, 0 },
144 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
145 enum processor_type sparc_cpu
;
147 /* Validate and override various options, and do some machine dependent
151 sparc_override_options ()
153 static struct code_model
{
158 { "medlow", CM_MEDLOW
},
159 { "medmid", CM_MEDMID
},
160 { "medany", CM_MEDANY
},
161 { "embmedany", CM_EMBMEDANY
},
164 struct code_model
*cmodel
;
165 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
166 static struct cpu_default
{
170 /* There must be one entry here for each TARGET_CPU value. */
171 { TARGET_CPU_sparc
, "cypress" },
172 { TARGET_CPU_sparclet
, "tsc701" },
173 { TARGET_CPU_sparclite
, "f930" },
174 { TARGET_CPU_v8
, "v8" },
175 { TARGET_CPU_supersparc
, "supersparc" },
176 { TARGET_CPU_v9
, "v9" },
177 { TARGET_CPU_ultrasparc
, "ultrasparc" },
180 struct cpu_default
*def
;
181 /* Table of values for -m{cpu,tune}=. */
182 static struct cpu_table
{
184 enum processor_type processor
;
188 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
189 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
190 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
191 /* TI TMS390Z55 supersparc */
192 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
193 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
194 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
195 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
196 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
197 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
198 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
200 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
201 /* "v8plus" is what Sun calls Solaris2.5 running on UltraSPARC's. */
202 { "v8plus", PROCESSOR_V8PLUS
, MASK_ISA
, MASK_V9
},
203 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
205 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
},
208 struct cpu_table
*cpu
;
209 struct sparc_cpu_select
*sel
;
212 #ifndef SPARC_BI_ARCH
213 /* Check for unsupported architecture size. */
214 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
216 error ("%s is not supported by this configuration",
217 DEFAULT_ARCH32_P
? "-m64" : "-m32");
221 /* Code model selection. */
222 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
223 if (sparc_cmodel_string
!= NULL
)
227 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
228 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
230 if (cmodel
->name
== NULL
)
231 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
233 sparc_cmodel
= cmodel
->value
;
236 error ("-mcmodel= is not supported on 32 bit systems");
239 fpu
= TARGET_FPU
; /* save current -mfpu status */
241 /* Set the default CPU. */
242 for (def
= &cpu_default
[0]; def
->name
; ++def
)
243 if (def
->cpu
== TARGET_CPU_DEFAULT
)
247 sparc_select
[0].string
= def
->name
;
249 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
253 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
254 if (! strcmp (sel
->string
, cpu
->name
))
257 sparc_cpu
= cpu
->processor
;
261 target_flags
&= ~cpu
->disable
;
262 target_flags
|= cpu
->enable
;
268 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
272 /* If -mfpu or -mno-fpu was explicitly used, don't override with
273 the processor default. */
275 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
277 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
278 if (TARGET_V9
&& TARGET_ARCH32
)
279 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
281 /* Validate -malign-loops= value, or provide default. */
282 if (sparc_align_loops_string
)
284 sparc_align_loops
= exact_log2 (atoi (sparc_align_loops_string
));
285 if (sparc_align_loops
< 2 || sparc_align_loops
> 7)
286 fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
287 sparc_align_loops_string
);
291 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
292 its 0. This sounds a bit kludgey. */
293 sparc_align_loops
= 0;
296 /* Validate -malign-jumps= value, or provide default. */
297 if (sparc_align_jumps_string
)
299 sparc_align_jumps
= exact_log2 (atoi (sparc_align_jumps_string
));
300 if (sparc_align_jumps
< 2 || sparc_align_loops
> 7)
301 fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
302 sparc_align_jumps_string
);
306 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
307 its 0. This sounds a bit kludgey. */
308 sparc_align_jumps
= 0;
311 /* Validate -malign-functions= value, or provide default. */
312 if (sparc_align_funcs_string
)
314 sparc_align_funcs
= exact_log2 (atoi (sparc_align_funcs_string
));
315 if (sparc_align_funcs
< 2 || sparc_align_loops
> 7)
316 fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
317 sparc_align_funcs_string
);
320 sparc_align_funcs
= DEFAULT_SPARC_ALIGN_FUNCS
;
322 /* Do various machine dependent initializations. */
326 /* Float conversions (v9 only).
328 The floating point registers cannot hold DImode values because SUBREG's
329 on them get the wrong register. "(subreg:SI (reg:DI M int-reg) 0)" is the
330 same as "(subreg:SI (reg:DI N float-reg) 1)", but gcc doesn't know how to
331 turn the "0" to a "1". Therefore, we must explicitly do the conversions
332 to/from int/fp regs. `sparc64_fpconv_stack_slot' is the address of an
333 8 byte stack slot used during the transfer.
334 ??? I could have used [%fp-16] but I didn't want to add yet another
335 dependence on this. */
336 /* ??? Can we use assign_stack_temp here? */
338 static rtx fpconv_stack_temp
;
340 /* Called once for each function. */
343 sparc_init_expanders ()
345 fpconv_stack_temp
= NULL_RTX
;
348 /* Assign a stack temp for fp/int DImode conversions. */
351 sparc64_fpconv_stack_temp ()
353 if (fpconv_stack_temp
== NULL_RTX
)
355 assign_stack_local (DImode
, GET_MODE_SIZE (DImode
), 0);
357 return fpconv_stack_temp
;
360 /* Miscellaneous utilities. */
362 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
363 or branch on register contents instructions. */
369 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
370 || code
== LE
|| code
== GT
);
373 /* Operand constraints. */
375 /* Return non-zero only if OP is a register of mode MODE,
376 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
377 %g0 may contain anything. */
380 reg_or_0_operand (op
, mode
)
382 enum machine_mode mode
;
384 if (register_operand (op
, mode
))
388 if (op
== const0_rtx
)
390 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
391 && CONST_DOUBLE_HIGH (op
) == 0
392 && CONST_DOUBLE_LOW (op
) == 0)
394 if (GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
395 && GET_CODE (op
) == CONST_DOUBLE
396 && fp_zero_operand (op
))
401 /* Nonzero if OP is a floating point value with value 0.0. */
409 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
410 return (REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
));
413 /* Nonzero if OP is an integer register. */
416 intreg_operand (op
, mode
)
418 enum machine_mode mode
;
420 return (register_operand (op
, SImode
)
421 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
424 /* Nonzero if OP is a floating point condition code register. */
427 fcc_reg_operand (op
, mode
)
429 enum machine_mode mode
;
431 /* This can happen when recog is called from combine. Op may be a MEM.
432 Fail instead of calling abort in this case. */
433 if (GET_CODE (op
) != REG
)
436 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
439 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
442 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
443 if (reg_renumber
== 0)
444 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
445 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
447 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
451 /* Nonzero if OP is an integer or floating point condition code register. */
454 icc_or_fcc_reg_operand (op
, mode
)
456 enum machine_mode mode
;
458 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
460 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
463 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
468 return fcc_reg_operand (op
, mode
);
471 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
473 restore_operand (op
, mode
)
475 enum machine_mode mode
;
477 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
478 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
481 /* Call insn on SPARC can take a PC-relative constant address, or any regular
485 call_operand (op
, mode
)
487 enum machine_mode mode
;
489 if (GET_CODE (op
) != MEM
)
492 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
496 call_operand_address (op
, mode
)
498 enum machine_mode mode
;
500 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
503 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
504 reference and a constant. */
507 symbolic_operand (op
, mode
)
509 enum machine_mode mode
;
511 switch (GET_CODE (op
))
519 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
520 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
521 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
523 /* ??? This clause seems to be irrelevant. */
525 return GET_MODE (op
) == mode
;
532 /* Return truth value of statement that OP is a symbolic memory
533 operand of mode MODE. */
536 symbolic_memory_operand (op
, mode
)
538 enum machine_mode mode
;
540 if (GET_CODE (op
) == SUBREG
)
541 op
= SUBREG_REG (op
);
542 if (GET_CODE (op
) != MEM
)
545 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
546 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
549 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
552 label_ref_operand (op
, mode
)
554 enum machine_mode mode
;
556 if (GET_CODE (op
) != LABEL_REF
)
558 if (GET_MODE (op
) != mode
)
563 /* Return 1 if the operand is an argument used in generating pic references
564 in either the medium/low or medium/anywhere code models of sparc64. */
567 sp64_medium_pic_operand (op
, mode
)
569 enum machine_mode mode
;
571 /* Check for (const (minus (symbol_ref:GOT)
572 (const (minus (label) (pc))))). */
573 if (GET_CODE (op
) != CONST
)
576 if (GET_CODE (op
) != MINUS
)
578 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
580 /* ??? Ensure symbol is GOT. */
581 if (GET_CODE (XEXP (op
, 1)) != CONST
)
583 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
588 /* Return 1 if the operand is a data segment reference. This includes
589 the readonly data segment, or in other words anything but the text segment.
590 This is needed in the medium/anywhere code model on v9. These values
591 are accessed with EMBMEDANY_BASE_REG. */
594 data_segment_operand (op
, mode
)
596 enum machine_mode mode
;
598 switch (GET_CODE (op
))
601 return ! SYMBOL_REF_FLAG (op
);
603 /* Assume canonical format of symbol + constant.
606 return data_segment_operand (XEXP (op
, 0));
612 /* Return 1 if the operand is a text segment reference.
613 This is needed in the medium/anywhere code model on v9. */
616 text_segment_operand (op
, mode
)
618 enum machine_mode mode
;
620 switch (GET_CODE (op
))
625 return SYMBOL_REF_FLAG (op
);
627 /* Assume canonical format of symbol + constant.
630 return text_segment_operand (XEXP (op
, 0));
636 /* Return 1 if the operand is either a register or a memory operand that is
640 reg_or_nonsymb_mem_operand (op
, mode
)
642 enum machine_mode mode
;
644 if (register_operand (op
, mode
))
647 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
654 sparc_operand (op
, mode
)
656 enum machine_mode mode
;
658 if (register_operand (op
, mode
))
660 if (GET_CODE (op
) == CONST_INT
)
661 return SMALL_INT (op
);
662 if (GET_MODE (op
) != mode
)
664 if (GET_CODE (op
) == SUBREG
)
665 op
= SUBREG_REG (op
);
666 if (GET_CODE (op
) != MEM
)
670 if (GET_CODE (op
) == LO_SUM
)
671 return (GET_CODE (XEXP (op
, 0)) == REG
672 && symbolic_operand (XEXP (op
, 1), Pmode
));
673 return memory_address_p (mode
, op
);
677 move_operand (op
, mode
)
679 enum machine_mode mode
;
681 if (mode
== DImode
&& arith_double_operand (op
, mode
))
683 if (register_operand (op
, mode
))
685 if (GET_CODE (op
) == CONST_INT
)
686 return SMALL_INT (op
) || SPARC_SETHI_P (INTVAL (op
));
688 if (GET_MODE (op
) != mode
)
690 if (GET_CODE (op
) == SUBREG
)
691 op
= SUBREG_REG (op
);
692 if (GET_CODE (op
) != MEM
)
695 if (GET_CODE (op
) == LO_SUM
)
696 return (register_operand (XEXP (op
, 0), Pmode
)
697 && CONSTANT_P (XEXP (op
, 1)));
698 return memory_address_p (mode
, op
);
702 splittable_symbolic_memory_operand (op
, mode
)
704 enum machine_mode mode
;
706 if (GET_CODE (op
) != MEM
)
708 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
714 splittable_immediate_memory_operand (op
, mode
)
716 enum machine_mode mode
;
718 if (GET_CODE (op
) != MEM
)
720 if (! immediate_operand (XEXP (op
, 0), Pmode
))
725 /* Return truth value of whether OP is EQ or NE. */
730 enum machine_mode mode
;
732 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
735 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
736 or LTU for non-floating-point. We handle those specially. */
739 normal_comp_operator (op
, mode
)
741 enum machine_mode mode
;
743 enum rtx_code code
= GET_CODE (op
);
745 if (GET_RTX_CLASS (code
) != '<')
748 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
749 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
752 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
755 /* Return 1 if this is a comparison operator. This allows the use of
756 MATCH_OPERATOR to recognize all the branch insns. */
759 noov_compare_op (op
, mode
)
761 enum machine_mode mode
;
763 enum rtx_code code
= GET_CODE (op
);
765 if (GET_RTX_CLASS (code
) != '<')
768 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
)
769 /* These are the only branches which work with CC_NOOVmode. */
770 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
774 /* Nonzero if OP is a comparison operator suitable for use in v9
775 conditional move or branch on register contents instructions. */
778 v9_regcmp_op (op
, mode
)
780 enum machine_mode mode
;
782 enum rtx_code code
= GET_CODE (op
);
784 if (GET_RTX_CLASS (code
) != '<')
787 return v9_regcmp_p (code
);
790 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
795 enum machine_mode mode
;
797 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
800 /* Return nonzero if OP is an operator of mode MODE which can set
801 the condition codes explicitly. We do not include PLUS and MINUS
802 because these require CC_NOOVmode, which we handle explicitly. */
805 cc_arithop (op
, mode
)
807 enum machine_mode mode
;
809 if (GET_CODE (op
) == AND
810 || GET_CODE (op
) == IOR
811 || GET_CODE (op
) == XOR
)
817 /* Return nonzero if OP is an operator of mode MODE which can bitwise
818 complement its second operand and set the condition codes explicitly. */
821 cc_arithopn (op
, mode
)
823 enum machine_mode mode
;
825 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
826 and (xor ... (not ...)) to (not (xor ...)). */
827 return (GET_CODE (op
) == AND
828 || GET_CODE (op
) == IOR
);
831 /* Return true if OP is a register, or is a CONST_INT that can fit in a
832 signed 13 bit immediate field. This is an acceptable SImode operand for
833 most 3 address instructions. */
836 arith_operand (op
, mode
)
838 enum machine_mode mode
;
840 return (register_operand (op
, mode
)
841 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
)));
844 /* Return true if OP is a register, or is a CONST_INT that can fit in a
845 signed 11 bit immediate field. This is an acceptable SImode operand for
846 the movcc instructions. */
849 arith11_operand (op
, mode
)
851 enum machine_mode mode
;
853 return (register_operand (op
, mode
)
854 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
857 /* Return true if OP is a register, or is a CONST_INT that can fit in a
858 signed 10 bit immediate field. This is an acceptable SImode operand for
859 the movrcc instructions. */
862 arith10_operand (op
, mode
)
864 enum machine_mode mode
;
866 return (register_operand (op
, mode
)
867 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
870 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
871 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
873 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
874 can fit in a 13 bit immediate field. This is an acceptable DImode operand
875 for most 3 address instructions. */
878 arith_double_operand (op
, mode
)
880 enum machine_mode mode
;
882 return (register_operand (op
, mode
)
883 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
885 && GET_CODE (op
) == CONST_DOUBLE
886 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
887 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
889 && GET_CODE (op
) == CONST_DOUBLE
890 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
891 && ((CONST_DOUBLE_HIGH (op
) == -1
892 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
893 || (CONST_DOUBLE_HIGH (op
) == 0
894 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
897 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
898 can fit in an 11 bit immediate field. This is an acceptable DImode
899 operand for the movcc instructions. */
900 /* ??? Replace with arith11_operand? */
903 arith11_double_operand (op
, mode
)
905 enum machine_mode mode
;
907 return (register_operand (op
, mode
)
908 || (GET_CODE (op
) == CONST_DOUBLE
909 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
910 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
911 && ((CONST_DOUBLE_HIGH (op
) == -1
912 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
913 || (CONST_DOUBLE_HIGH (op
) == 0
914 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
915 || (GET_CODE (op
) == CONST_INT
916 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
917 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
920 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
921 can fit in an 10 bit immediate field. This is an acceptable DImode
922 operand for the movrcc instructions. */
923 /* ??? Replace with arith10_operand? */
926 arith10_double_operand (op
, mode
)
928 enum machine_mode mode
;
930 return (register_operand (op
, mode
)
931 || (GET_CODE (op
) == CONST_DOUBLE
932 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
933 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
934 && ((CONST_DOUBLE_HIGH (op
) == -1
935 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
936 || (CONST_DOUBLE_HIGH (op
) == 0
937 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
938 || (GET_CODE (op
) == CONST_INT
939 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
940 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
943 /* Return truth value of whether OP is a integer which fits the
944 range constraining immediate operands in most three-address insns,
945 which have a 13 bit immediate field. */
950 enum machine_mode mode
;
952 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
955 /* Recognize operand values for the umul instruction. That instruction sign
956 extends immediate values just like all other sparc instructions, but
957 interprets the extended result as an unsigned number. */
960 uns_small_int (op
, mode
)
962 enum machine_mode mode
;
964 #if HOST_BITS_PER_WIDE_INT > 32
965 /* All allowed constants will fit a CONST_INT. */
966 return (GET_CODE (op
) == CONST_INT
967 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
968 || (INTVAL (op
) >= 0xFFFFF000 && INTVAL (op
) < 0x100000000L
)));
970 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
971 || (GET_CODE (op
) == CONST_DOUBLE
972 && CONST_DOUBLE_HIGH (op
) == 0
973 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
978 uns_arith_operand (op
, mode
)
980 enum machine_mode mode
;
982 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
985 /* Return truth value of statement that OP is a call-clobbered register. */
987 clobbered_register (op
, mode
)
989 enum machine_mode mode
;
991 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
994 /* X and Y are two things to compare using CODE. Emit the compare insn and
995 return the rtx for the cc reg in the proper mode. */
998 gen_compare_reg (code
, x
, y
)
1002 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
1005 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
1006 fcc regs (cse can't tell they're really call clobbered regs and will
1007 remove a duplicate comparison even if there is an intervening function
1008 call - it will then try to reload the cc reg via an int reg which is why
1009 we need the movcc patterns). It is possible to provide the movcc
1010 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
1011 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
1012 to tell cse that CCFPE mode registers (even pseudos) are call
1015 /* ??? This is an experiment. Rather than making changes to cse which may
1016 or may not be easy/clean, we do our own cse. This is possible because
1017 we will generate hard registers. Cse knows they're call clobbered (it
1018 doesn't know the same thing about pseudos). If we guess wrong, no big
1019 deal, but if we win, great! */
1021 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1022 #if 1 /* experiment */
1025 /* We cycle through the registers to ensure they're all exercised. */
1026 static int next_fcc_reg
= 0;
1027 /* Previous x,y for each fcc reg. */
1028 static rtx prev_args
[4][2];
1030 /* Scan prev_args for x,y. */
1031 for (reg
= 0; reg
< 4; reg
++)
1032 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
1037 prev_args
[reg
][0] = x
;
1038 prev_args
[reg
][1] = y
;
1039 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
1041 cc_reg
= gen_rtx (REG
, mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
1044 cc_reg
= gen_reg_rtx (mode
);
1045 #endif /* ! experiment */
1046 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1047 cc_reg
= gen_rtx (REG
, mode
, SPARC_FCC_REG
);
1049 cc_reg
= gen_rtx (REG
, mode
, SPARC_ICC_REG
);
1051 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
1052 gen_rtx (COMPARE
, mode
, x
, y
)));
1057 /* This function is used for v9 only.
1058 CODE is the code for an Scc's comparison.
1059 OPERANDS[0] is the target of the Scc insn.
1060 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
1061 been generated yet).
1063 This function is needed to turn
1066 (gt (reg:CCX 100 %icc)
1070 (gt:DI (reg:CCX 100 %icc)
1073 IE: The instruction recognizer needs to see the mode of the comparison to
1074 find the right instruction. We could use "gt:DI" right in the
1075 define_expand, but leaving it out allows us to handle DI, SI, etc.
1077 We refer to the global sparc compare operands sparc_compare_op0 and
1078 sparc_compare_op1. */
1081 gen_v9_scc (compare_code
, operands
)
1082 enum rtx_code compare_code
;
1083 register rtx
*operands
;
1088 && (GET_MODE (sparc_compare_op0
) == DImode
1089 || GET_MODE (operands
[0]) == DImode
))
1092 /* Handle the case where operands[0] == sparc_compare_op0.
1093 We "early clobber" the result. */
1094 if (REGNO (operands
[0]) == REGNO (sparc_compare_op0
))
1096 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
1097 emit_move_insn (op0
, sparc_compare_op0
);
1100 op0
= sparc_compare_op0
;
1101 /* For consistency in the following. */
1102 op1
= sparc_compare_op1
;
1104 /* Try to use the movrCC insns. */
1106 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
1107 && op1
== const0_rtx
1108 && v9_regcmp_p (compare_code
))
1110 /* Special case for op0 != 0. This can be done with one instruction if
1111 operands[0] == sparc_compare_op0. We don't assume they are equal
1114 if (compare_code
== NE
1115 && GET_MODE (operands
[0]) == DImode
1116 && GET_MODE (op0
) == DImode
)
1118 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0], op0
));
1119 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0],
1120 gen_rtx (IF_THEN_ELSE
, DImode
,
1121 gen_rtx (compare_code
, DImode
,
1128 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0], const0_rtx
));
1129 if (GET_MODE (op0
) != DImode
)
1131 temp
= gen_reg_rtx (DImode
);
1132 convert_move (temp
, op0
, 0);
1136 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0],
1137 gen_rtx (IF_THEN_ELSE
, GET_MODE (operands
[0]),
1138 gen_rtx (compare_code
, DImode
,
1146 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
1148 switch (GET_MODE (operands
[1]))
1158 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0], const0_rtx
));
1159 emit_insn (gen_rtx (SET
, VOIDmode
, operands
[0],
1160 gen_rtx (IF_THEN_ELSE
, GET_MODE (operands
[0]),
1161 gen_rtx (compare_code
,
1162 GET_MODE (operands
[1]),
1163 operands
[1], const0_rtx
),
1164 const1_rtx
, operands
[0])));
1169 /* Emit a conditional jump insn for the v9 architecture using comparison code
1170 CODE and jump target LABEL.
1171 This function exists to take advantage of the v9 brxx insns. */
1174 emit_v9_brxx_insn (code
, op0
, label
)
1178 emit_jump_insn (gen_rtx (SET
, VOIDmode
,
1180 gen_rtx (IF_THEN_ELSE
, VOIDmode
,
1181 gen_rtx (code
, GET_MODE (op0
),
1183 gen_rtx (LABEL_REF
, VOIDmode
, label
),
1187 /* Return nonzero if a return peephole merging return with
1188 setting of output register is ok. */
1190 leaf_return_peephole_ok ()
1192 return (actual_fsize
== 0);
1195 /* Return nonzero if TRIAL can go into the function epilogue's
1196 delay slot. SLOT is the slot we are trying to fill. */
1199 eligible_for_epilogue_delay (trial
, slot
)
1208 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
1211 if (get_attr_length (trial
) != 1)
1214 /* If %g0 is live, there are lots of things we can't handle.
1215 Rather than trying to find them all now, let's punt and only
1216 optimize things as necessary. */
1220 /* In the case of a true leaf function, anything can go into the delay slot.
1221 A delay slot only exists however if the frame size is zero, otherwise
1222 we will put an insn to adjust the stack after the return. */
1225 if (leaf_return_peephole_ok ())
1226 return ((get_attr_in_uncond_branch_delay (trial
)
1227 == IN_BRANCH_DELAY_TRUE
));
1231 /* If only trivial `restore' insns work, nothing can go in the
1233 else if (TARGET_BROKEN_SAVERESTORE
)
1236 pat
= PATTERN (trial
);
1238 /* Otherwise, only operations which can be done in tandem with
1239 a `restore' insn can go into the delay slot. */
1240 if (GET_CODE (SET_DEST (pat
)) != REG
1241 || REGNO (SET_DEST (pat
)) >= 32
1242 || REGNO (SET_DEST (pat
)) < 24)
1245 /* The set of insns matched here must agree precisely with the set of
1246 patterns paired with a RETURN in sparc.md. */
1248 src
= SET_SRC (pat
);
1250 /* This matches "*return_[qhs]". */
1251 if (arith_operand (src
, GET_MODE (src
)))
1252 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
1254 /* This matches "*return_di". */
1255 else if (arith_double_operand (src
, GET_MODE (src
)))
1256 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
1258 /* This matches "*return_sf_no_fpu". */
1259 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
1260 && register_operand (src
, SFmode
))
1263 /* This matches "*return_addsi". */
1264 else if (GET_CODE (src
) == PLUS
1265 && arith_operand (XEXP (src
, 0), SImode
)
1266 && arith_operand (XEXP (src
, 1), SImode
)
1267 && (register_operand (XEXP (src
, 0), SImode
)
1268 || register_operand (XEXP (src
, 1), SImode
)))
1271 /* This matches "*return_adddi". */
1272 else if (GET_CODE (src
) == PLUS
1273 && arith_double_operand (XEXP (src
, 0), DImode
)
1274 && arith_double_operand (XEXP (src
, 1), DImode
)
1275 && (register_operand (XEXP (src
, 0), DImode
)
1276 || register_operand (XEXP (src
, 1), DImode
)))
1279 /* This matches "*return_subsi". */
1280 else if (GET_CODE (src
) == MINUS
1281 && register_operand (XEXP (src
, 0), SImode
)
1282 && small_int (XEXP (src
, 1), VOIDmode
)
1283 && INTVAL (XEXP (src
, 1)) != -4096)
1290 short_branch (uid1
, uid2
)
1293 unsigned int delta
= insn_addresses
[uid1
] - insn_addresses
[uid2
];
1294 if (delta
+ 1024 < 2048)
1296 /* warning ("long branch, distance %d", delta); */
1300 /* Return non-zero if REG is not used after INSN.
1301 We assume REG is a reload reg, and therefore does
1302 not live past labels or calls or jumps. */
1304 reg_unused_after (reg
, insn
)
1308 enum rtx_code code
, prev_code
= UNKNOWN
;
1310 while (insn
= NEXT_INSN (insn
))
1312 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
1315 code
= GET_CODE (insn
);
1316 if (GET_CODE (insn
) == CODE_LABEL
)
1319 if (GET_RTX_CLASS (code
) == 'i')
1321 rtx set
= single_set (insn
);
1322 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
1325 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1327 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
1335 /* The table we use to reference PIC data. */
1336 static rtx global_offset_table
;
1338 /* Ensure that we are not using patterns that are not OK with PIC. */
1347 if (GET_CODE (recog_operand
[i
]) == SYMBOL_REF
1348 || (GET_CODE (recog_operand
[i
]) == CONST
1349 && ! (GET_CODE (XEXP (recog_operand
[i
], 0)) == MINUS
1350 && (XEXP (XEXP (recog_operand
[i
], 0), 0)
1351 == global_offset_table
)
1352 && (GET_CODE (XEXP (XEXP (recog_operand
[i
], 0), 1))
1361 /* Return true if X is an address which needs a temporary register when
1362 reloaded while generating PIC code. */
1365 pic_address_needs_scratch (x
)
1368 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1369 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1370 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1371 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1372 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1378 /* Legitimize PIC addresses. If the address is already position-independent,
1379 we return ORIG. Newly generated position-independent addresses go into a
1380 reg. This is REG if non zero, otherwise we allocate register(s) as
1384 legitimize_pic_address (orig
, mode
, reg
)
1386 enum machine_mode mode
;
1389 if (GET_CODE (orig
) == SYMBOL_REF
)
1391 rtx pic_ref
, address
;
1396 if (reload_in_progress
|| reload_completed
)
1399 reg
= gen_reg_rtx (Pmode
);
1404 /* If not during reload, allocate another temp reg here for loading
1405 in the address, so that these instructions can be optimized
1407 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
1408 ? reg
: gen_reg_rtx (Pmode
));
1410 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
1411 won't get confused into thinking that these two instructions
1412 are loading in the true address of the symbol. If in the
1413 future a PIC rtx exists, that should be used instead. */
1414 emit_insn (gen_pic_sethi_si (temp_reg
, orig
));
1415 emit_insn (gen_pic_lo_sum_si (temp_reg
, temp_reg
, orig
));
1422 pic_ref
= gen_rtx (MEM
, Pmode
,
1423 gen_rtx (PLUS
, Pmode
,
1424 pic_offset_table_rtx
, address
));
1425 current_function_uses_pic_offset_table
= 1;
1426 RTX_UNCHANGING_P (pic_ref
) = 1;
1427 insn
= emit_move_insn (reg
, pic_ref
);
1428 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1430 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_EQUAL
, orig
,
1434 else if (GET_CODE (orig
) == CONST
)
1438 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1439 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1444 if (reload_in_progress
|| reload_completed
)
1447 reg
= gen_reg_rtx (Pmode
);
1450 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1452 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1453 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1454 base
== reg
? 0 : reg
);
1459 if (GET_CODE (offset
) == CONST_INT
)
1461 if (SMALL_INT (offset
))
1462 return plus_constant_for_output (base
, INTVAL (offset
));
1463 else if (! reload_in_progress
&& ! reload_completed
)
1464 offset
= force_reg (Pmode
, offset
);
1466 /* If we reach here, then something is seriously wrong. */
1469 return gen_rtx (PLUS
, Pmode
, base
, offset
);
1471 else if (GET_CODE (orig
) == LABEL_REF
)
1472 /* ??? Why do we do this? */
1473 current_function_uses_pic_offset_table
= 1;
1478 /* Set up PIC-specific rtl. This should not cause any insns
1486 /* Return the RTX for insns to set the PIC register. */
1497 l1
= gen_label_rtx ();
1499 pic_pc_rtx
= gen_rtx (CONST
, Pmode
,
1500 gen_rtx (MINUS
, Pmode
,
1501 global_offset_table
,
1502 gen_rtx (CONST
, Pmode
,
1503 gen_rtx (MINUS
, Pmode
,
1508 /* sparc64: the RDPC instruction doesn't pair, and puts 4 bubbles in the
1509 pipe to boot. So don't use it here, especially when we're
1510 doing a save anyway because of %l7. */
1512 l2
= gen_label_rtx ();
1515 /* Iff we are doing delay branch optimization, slot the sethi up
1516 here so that it will fill the delay slot of the call. */
1517 if (flag_delayed_branch
)
1518 emit_insn (gen_rtx (SET
, VOIDmode
, pic_offset_table_rtx
,
1519 gen_rtx (HIGH
, Pmode
, pic_pc_rtx
)));
1521 /* Note that we pun calls and jumps here! */
1522 emit_jump_insn (gen_get_pc_via_call (l2
, l1
));
1526 if (!flag_delayed_branch
)
1527 emit_insn (gen_rtx (SET
, VOIDmode
, pic_offset_table_rtx
,
1528 gen_rtx (HIGH
, Pmode
, pic_pc_rtx
)));
1530 emit_insn (gen_rtx (SET
, VOIDmode
,
1531 pic_offset_table_rtx
,
1532 gen_rtx (LO_SUM
, Pmode
,
1533 pic_offset_table_rtx
, pic_pc_rtx
)));
1534 emit_insn (gen_rtx (SET
, VOIDmode
,
1535 pic_offset_table_rtx
,
1536 gen_rtx (PLUS
, Pmode
,
1537 pic_offset_table_rtx
,
1538 gen_rtx (REG
, Pmode
, 15))));
1540 /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */
1541 LABEL_PRESERVE_P (l1
) = 1;
1542 LABEL_PRESERVE_P (l2
) = 1;
1544 seq
= gen_sequence ();
1550 /* Emit special PIC prologues and epilogues. */
1555 /* Labels to get the PC in the prologue of this function. */
1556 int orig_flag_pic
= flag_pic
;
1559 if (current_function_uses_pic_offset_table
== 0)
1565 /* Initialize every time through, since we can't easily
1566 know this to be permanent. */
1567 global_offset_table
= gen_rtx (SYMBOL_REF
, Pmode
, "_GLOBAL_OFFSET_TABLE_");
1570 emit_insn_after (pic_setup_code (), get_insns ());
1572 /* Insert the code in each nonlocal goto receiver. */
1573 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1574 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
1575 && XINT (PATTERN (insn
), 1) == 4)
1576 emit_insn_after (pic_setup_code (), insn
);
1578 flag_pic
= orig_flag_pic
;
1580 /* Need to emit this whether or not we obey regdecls,
1581 since setjmp/longjmp can cause life info to screw up.
1582 ??? In the case where we don't obey regdecls, this is not sufficient
1583 since we may not fall out the bottom. */
1584 emit_insn (gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
));
1587 /* Emit insns to move operands[1] into operands[0].
1589 Return 1 if we have written out everything that needs to be done to
1590 do the move. Otherwise, return 0 and the caller will emit the move
1594 emit_move_sequence (operands
, mode
)
1596 enum machine_mode mode
;
1598 register rtx operand0
= operands
[0];
1599 register rtx operand1
= operands
[1];
1601 if (CONSTANT_P (operand1
) && flag_pic
1602 && pic_address_needs_scratch (operand1
))
1603 operands
[1] = operand1
= legitimize_pic_address (operand1
, mode
, 0);
1605 /* Handle most common case first: storing into a register. */
1606 if (register_operand (operand0
, mode
))
1608 if (register_operand (operand1
, mode
)
1609 || (GET_CODE (operand1
) == CONST_INT
&& SMALL_INT (operand1
))
1610 || (GET_CODE (operand1
) == CONST_DOUBLE
1611 && arith_double_operand (operand1
, DImode
))
1612 || (GET_CODE (operand1
) == HIGH
&& GET_MODE (operand1
) != DImode
)
1613 /* Only `general_operands' can come here, so MEM is ok. */
1614 || GET_CODE (operand1
) == MEM
)
1616 /* Run this case quickly. */
1617 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
1621 else if (GET_CODE (operand0
) == MEM
)
1623 if (register_operand (operand1
, mode
)
1624 || (operand1
== const0_rtx
&& ! TARGET_LIVE_G0
))
1626 /* Run this case quickly. */
1627 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
1630 if (! reload_in_progress
)
1632 operands
[0] = validize_mem (operand0
);
1633 operands
[1] = operand1
= force_reg (mode
, operand1
);
1637 if (GET_CODE (operand1
) == LABEL_REF
1638 && mode
== SImode
&& flag_pic
)
1642 emit_insn (gen_move_pic_label_si (operand0
, operand1
));
1645 /* Non-pic LABEL_REF's in sparc64 are expensive to do the normal way,
1646 so always use special code. */
1647 else if (GET_CODE (operand1
) == LABEL_REF
1650 if (! TARGET_ARCH64
)
1652 emit_insn (gen_move_label_di (operand0
, operand1
));
1655 /* DImode HIGH values in sparc64 need a clobber added. */
1656 else if (TARGET_ARCH64
1657 && GET_CODE (operand1
) == HIGH
&& GET_MODE (operand1
) == DImode
)
1659 emit_insn (gen_sethi_di_sp64 (operand0
, XEXP (operand1
, 0)));
1662 /* Simplify the source if we need to. */
1663 else if (GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
1665 if (flag_pic
&& symbolic_operand (operand1
, mode
))
1667 rtx temp_reg
= reload_in_progress
? operand0
: 0;
1669 operands
[1] = legitimize_pic_address (operand1
, mode
, temp_reg
);
1671 else if (GET_CODE (operand1
) == CONST_INT
1672 ? (! SMALL_INT (operand1
)
1673 && ! SPARC_SETHI_P (INTVAL (operand1
)))
1674 : GET_CODE (operand1
) == CONST_DOUBLE
1675 ? ! arith_double_operand (operand1
, DImode
)
1678 /* For DImode values, temp must be operand0 because of the way
1679 HI and LO_SUM work. The LO_SUM operator only copies half of
1680 the LSW from the dest of the HI operator. If the LO_SUM dest is
1681 not the same as the HI dest, then the MSW of the LO_SUM dest will
1684 ??? The real problem here is that the ...(HI:DImode pattern emits
1685 multiple instructions, and the ...(LO_SUM:DImode pattern emits
1686 one instruction. This fails, because the compiler assumes that
1687 LO_SUM copies all bits of the first operand to its dest. Better
1688 would be to have the HI pattern emit one instruction and the
1689 LO_SUM pattern multiple instructions. Even better would be
1690 to use four rtl insns. */
1691 rtx temp
= ((reload_in_progress
|| mode
== DImode
)
1692 ? operand0
: gen_reg_rtx (mode
));
1694 if (TARGET_ARCH64
&& mode
== DImode
)
1695 emit_insn (gen_sethi_di_sp64 (temp
, operand1
));
1697 emit_insn (gen_rtx (SET
, VOIDmode
, temp
,
1698 gen_rtx (HIGH
, mode
, operand1
)));
1700 if (GET_CODE (operand1
) == CONST_INT
)
1701 operand1
= GEN_INT (INTVAL (operand1
) & 0xffffffff);
1702 else if (GET_CODE (operand1
) == CONST_DOUBLE
)
1703 operand1
= GEN_INT (CONST_DOUBLE_LOW (operand1
) & 0xffffffff);
1704 operands
[1] = gen_rtx (LO_SUM
, mode
, temp
, operand1
);
1708 /* Now have insn-emit do whatever it normally does. */
1712 /* Return the best assembler insn template
1713 for moving operands[1] into operands[0] as a 4 byte quantity.
1715 This isn't intended to be very smart. It is up to the caller to
1716 choose the best way to do things.
1718 Note that OPERANDS may be modified to suit the returned string. */
1721 singlemove_string (operands
)
1724 if (GET_CODE (operands
[0]) == MEM
)
1726 if (GET_CODE (operands
[1]) != MEM
)
1731 else if (GET_CODE (operands
[1]) == MEM
)
1733 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1738 /* Must be SFmode, otherwise this doesn't make sense. */
1739 if (GET_MODE (operands
[1]) != SFmode
)
1742 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1743 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1744 operands
[1] = GEN_INT (i
);
1746 if (CONST_OK_FOR_LETTER_P (i
, 'I'))
1748 else if ((i
& 0x000003FF) != 0)
1749 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1751 return "sethi %%hi(%a1),%0";
1753 else if (GET_CODE (operands
[1]) == CONST_INT
1754 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands
[1]), 'I'))
1756 HOST_WIDE_INT i
= INTVAL (operands
[1]);
1758 /* If all low order 10 bits are clear, then we only need a single
1759 sethi insn to load the constant. */
1760 /* FIXME: Use SETHI_P. */
1761 if ((i
& 0x000003FF) != 0)
1762 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1764 return "sethi %%hi(%a1),%0";
1766 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1770 /* Return the best assembler insn template
1771 for moving operands[1] into operands[0] as an 8 byte quantity.
1773 This isn't intended to be very smart. It is up to the caller to
1774 choose the best way to do things.
1776 Note that OPERANDS may be modified to suit the returned string. */
1779 doublemove_string (operands
)
1782 rtx op0
= operands
[0], op1
= operands
[1];
1784 if (GET_CODE (op0
) == MEM
)
1786 if (GET_CODE (op1
) == REG
)
1790 return TARGET_ARCH64
? "stx %1,%0" : "std %1,%0";
1793 && (op1
== const0_rtx
1794 || (GET_MODE (op1
) != VOIDmode
1795 && op1
== CONST0_RTX (GET_MODE (op1
)))))
1796 return "stx %r1,%0";
1799 else if (GET_CODE (op1
) == MEM
)
1801 if (GET_CODE (op0
) != REG
)
1805 return TARGET_ARCH64
? "ldx %1,%0" : "ldd %1,%0";
1807 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1809 /* ??? Unfinished, and maybe not needed. */
1812 else if (GET_CODE (operands
[1]) == CONST_INT
1813 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands
[1]), 'I'))
1815 /* ??? Unfinished, and maybe not needed. */
1818 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1822 /* Return non-zero if it is OK to assume that the given memory operand is
1823 aligned at least to a 8-byte boundary. This should only be called
1824 for memory accesses whose size is 8 bytes or larger. */
1832 register rtx offset
;
1834 if (GET_CODE (mem
) != MEM
)
1835 return 0; /* It's gotta be a MEM! */
1837 addr
= XEXP (mem
, 0);
1839 /* Now that all misaligned double parms are copied on function entry,
1840 we can assume any 64-bit object is 64-bit aligned except those which
1841 are at unaligned offsets from the stack or frame pointer. If the
1842 TARGET_UNALIGNED_DOUBLES switch is given, we do not make this
1845 /* See what register we use in the address. */
1847 if (GET_CODE (addr
) == PLUS
)
1849 if (GET_CODE (XEXP (addr
, 0)) == REG
1850 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
1852 base
= XEXP (addr
, 0);
1853 offset
= XEXP (addr
, 1);
1856 else if (GET_CODE (addr
) == REG
)
1859 offset
= const0_rtx
;
1862 /* If it's the stack or frame pointer, check offset alignment.
1863 We can have improper alignment in the function entry code. */
1865 && (REGNO (base
) == FRAME_POINTER_REGNUM
1866 || REGNO (base
) == STACK_POINTER_REGNUM
))
1868 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & 0x7) == 0)
1871 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
1872 is true, in which case we can only assume that an access is aligned if
1873 it is to a constant address, or the address involves a LO_SUM.
1875 We used to assume an address was aligned if MEM_IN_STRUCT_P was true.
1876 That assumption was deleted so that gcc generated code can be used with
1877 memory allocators that only guarantee 4 byte alignment. */
1878 else if (! TARGET_UNALIGNED_DOUBLES
|| CONSTANT_P (addr
)
1879 || GET_CODE (addr
) == LO_SUM
)
1882 /* An obviously unaligned address. */
1886 enum optype
{ REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
};
1888 /* Output assembler code to perform a doubleword move insn
1889 with operands OPERANDS. This is very similar to the following
1890 output_move_quad function. */
1893 output_move_double (operands
)
1896 register rtx op0
= operands
[0];
1897 register rtx op1
= operands
[1];
1898 register enum optype optype0
;
1899 register enum optype optype1
;
1903 int highest_first
= 0;
1904 int no_addreg1_decrement
= 0;
1906 /* First classify both operands. */
1910 else if (offsettable_memref_p (op0
))
1912 else if (GET_CODE (op0
) == MEM
)
1919 else if (CONSTANT_P (op1
))
1921 else if (offsettable_memref_p (op1
))
1923 else if (GET_CODE (op1
) == MEM
)
1928 /* Check for the cases that the operand constraints are not
1929 supposed to allow to happen. Abort if we get one,
1930 because generating code for these cases is painful. */
1932 if (optype0
== RNDOP
|| optype1
== RNDOP
1933 || (optype0
== MEM
&& optype1
== MEM
))
1936 /* If an operand is an unoffsettable memory ref, find a register
1937 we can increment temporarily to make it refer to the second word. */
1939 if (optype0
== MEMOP
)
1940 addreg0
= find_addr_reg (XEXP (op0
, 0));
1942 if (optype1
== MEMOP
)
1943 addreg1
= find_addr_reg (XEXP (op1
, 0));
1945 /* Ok, we can do one word at a time.
1946 Set up in LATEHALF the operands to use for the
1947 high-numbered (least significant) word and in some cases alter the
1948 operands in OPERANDS to be suitable for the low-numbered word. */
1950 if (optype0
== REGOP
)
1951 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 1);
1952 else if (optype0
== OFFSOP
)
1953 latehalf
[0] = adj_offsettable_operand (op0
, 4);
1957 if (optype1
== REGOP
)
1958 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 1);
1959 else if (optype1
== OFFSOP
)
1960 latehalf
[1] = adj_offsettable_operand (op1
, 4);
1961 else if (optype1
== CNSTOP
)
1965 if (arith_double_operand (op1
, DImode
))
1967 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
,
1968 CONST_DOUBLE_LOW (op1
));
1973 /* The only way to handle CONST_DOUBLEs or other 64 bit
1974 constants here is to use a temporary, such as is done
1975 for the V9 DImode sethi insn pattern. This is not
1976 a practical solution, so abort if we reach here.
1977 The md file should always force such constants to
1983 split_double (op1
, &operands
[1], &latehalf
[1]);
1988 /* Easy case: try moving both words at once. Check for moving between
1989 an even/odd register pair and a memory location. */
1990 if ((optype0
== REGOP
&& optype1
!= REGOP
&& optype1
!= CNSTOP
1991 && (TARGET_ARCH64
|| (REGNO (op0
) & 1) == 0))
1992 || (optype0
!= REGOP
&& optype0
!= CNSTOP
&& optype1
== REGOP
1993 && (TARGET_ARCH64
|| (REGNO (op1
) & 1) == 0)))
1995 register rtx mem
,reg
;
1997 if (optype0
== REGOP
)
1998 mem
= op1
, reg
= op0
;
2000 mem
= op0
, reg
= op1
;
2002 /* In v9, ldd can be used for word aligned addresses, so technically
2003 some of this logic is unneeded. We still avoid ldd if the address
2004 is obviously unaligned though. */
2006 if (mem_aligned_8 (mem
)
2007 /* If this is a floating point register higher than %f31,
2008 then we *must* use an aligned load, since `ld' will not accept
2009 the register number. */
2010 || (TARGET_V9
&& REGNO (reg
) >= 64))
2012 if (FP_REG_P (reg
) || ! TARGET_ARCH64
)
2013 return (mem
== op1
? "ldd %1,%0" : "std %1,%0");
2015 return (mem
== op1
? "ldx %1,%0" : "stx %1,%0");
2021 if (optype0
== REGOP
&& optype1
== REGOP
)
2024 return "fmovd %1,%0";
2030 /* If the first move would clobber the source of the second one,
2031 do them in the other order. */
2033 /* Overlapping registers. */
2034 if (optype0
== REGOP
&& optype1
== REGOP
2035 && REGNO (op0
) == REGNO (latehalf
[1]))
2038 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2039 /* Do low-numbered word. */
2040 return singlemove_string (operands
);
2042 /* Loading into a register which overlaps a register used in the address. */
2043 else if (optype0
== REGOP
&& optype1
!= REGOP
2044 && reg_overlap_mentioned_p (op0
, op1
))
2046 /* If both halves of dest are used in the src memory address,
2047 add the two regs and put them in the low reg (op0).
2048 Then it works to load latehalf first. */
2049 if (reg_mentioned_p (op0
, XEXP (op1
, 0))
2050 && reg_mentioned_p (latehalf
[0], XEXP (op1
, 0)))
2053 xops
[0] = latehalf
[0];
2055 output_asm_insn ("add %1,%0,%1", xops
);
2056 operands
[1] = gen_rtx (MEM
, DImode
, op0
);
2057 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
2061 /* Only one register in the dest is used in the src memory address,
2062 and this is the first register of the dest, so we want to do
2063 the late half first here also. */
2064 else if (! reg_mentioned_p (latehalf
[0], XEXP (op1
, 0)))
2066 /* Only one register in the dest is used in the src memory address,
2067 and this is the second register of the dest, so we want to do
2068 the late half last. If addreg1 is set, and addreg1 is the same
2069 register as latehalf, then we must suppress the trailing decrement,
2070 because it would clobber the value just loaded. */
2071 else if (addreg1
&& reg_mentioned_p (addreg1
, latehalf
[0]))
2072 no_addreg1_decrement
= 1;
2075 /* Normal case: do the two words, low-numbered first.
2076 Overlap case (highest_first set): do high-numbered word first. */
2078 if (! highest_first
)
2079 output_asm_insn (singlemove_string (operands
), operands
);
2081 /* Make any unoffsettable addresses point at high-numbered word. */
2083 output_asm_insn ("add %0,0x4,%0", &addreg0
);
2085 output_asm_insn ("add %0,0x4,%0", &addreg1
);
2088 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2090 /* Undo the adds we just did. */
2092 output_asm_insn ("add %0,-0x4,%0", &addreg0
);
2093 if (addreg1
&& ! no_addreg1_decrement
)
2094 output_asm_insn ("add %0,-0x4,%0", &addreg1
);
2097 output_asm_insn (singlemove_string (operands
), operands
);
2102 /* Output assembler code to perform a quadword move insn
2103 with operands OPERANDS. This is very similar to the preceding
2104 output_move_double function. */
2107 output_move_quad (operands
)
2110 register rtx op0
= operands
[0];
2111 register rtx op1
= operands
[1];
2112 register enum optype optype0
;
2113 register enum optype optype1
;
2118 /* First classify both operands. */
2122 else if (offsettable_memref_p (op0
))
2124 else if (GET_CODE (op0
) == MEM
)
2131 else if (CONSTANT_P (op1
))
2133 else if (offsettable_memref_p (op1
))
2135 else if (GET_CODE (op1
) == MEM
)
2140 /* Check for the cases that the operand constraints are not
2141 supposed to allow to happen. Abort if we get one,
2142 because generating code for these cases is painful. */
2144 if (optype0
== RNDOP
|| optype1
== RNDOP
2145 || (optype0
== MEM
&& optype1
== MEM
))
2148 /* If an operand is an unoffsettable memory ref, find a register
2149 we can increment temporarily to make it refer to the later words. */
2151 if (optype0
== MEMOP
)
2152 addreg0
= find_addr_reg (XEXP (op0
, 0));
2154 if (optype1
== MEMOP
)
2155 addreg1
= find_addr_reg (XEXP (op1
, 0));
2157 /* Ok, we can do one word at a time.
2158 Set up in wordpart the operands to use for each word of the arguments. */
2160 if (optype0
== REGOP
)
2162 wordpart
[0][0] = gen_rtx (REG
, word_mode
, REGNO (op0
) + 0);
2163 wordpart
[1][0] = gen_rtx (REG
, word_mode
, REGNO (op0
) + 1);
2166 wordpart
[2][0] = gen_rtx (REG
, word_mode
, REGNO (op0
) + 2);
2167 wordpart
[3][0] = gen_rtx (REG
, word_mode
, REGNO (op0
) + 3);
2170 else if (optype0
== OFFSOP
)
2172 wordpart
[0][0] = adj_offsettable_operand (op0
, 0);
2175 wordpart
[1][0] = adj_offsettable_operand (op0
, 4);
2176 wordpart
[2][0] = adj_offsettable_operand (op0
, 8);
2177 wordpart
[3][0] = adj_offsettable_operand (op0
, 12);
2180 wordpart
[1][0] = adj_offsettable_operand (op0
, 8);
2184 wordpart
[0][0] = op0
;
2185 wordpart
[1][0] = op0
;
2186 wordpart
[2][0] = op0
;
2187 wordpart
[3][0] = op0
;
2190 if (optype1
== REGOP
)
2192 wordpart
[0][1] = gen_rtx (REG
, word_mode
, REGNO (op1
) + 0);
2193 wordpart
[1][1] = gen_rtx (REG
, word_mode
, REGNO (op1
) + 1);
2196 wordpart
[2][1] = gen_rtx (REG
, word_mode
, REGNO (op1
) + 2);
2197 wordpart
[3][1] = gen_rtx (REG
, word_mode
, REGNO (op1
) + 3);
2200 else if (optype1
== OFFSOP
)
2202 wordpart
[0][1] = adj_offsettable_operand (op1
, 0);
2205 wordpart
[1][1] = adj_offsettable_operand (op1
, 4);
2206 wordpart
[2][1] = adj_offsettable_operand (op1
, 8);
2207 wordpart
[3][1] = adj_offsettable_operand (op1
, 12);
2210 wordpart
[1][1] = adj_offsettable_operand (op1
, 8);
2212 else if (optype1
== CNSTOP
)
2217 /* This only works for TFmode floating point constants. */
2218 if (GET_CODE (op1
) != CONST_DOUBLE
|| GET_MODE (op1
) != TFmode
)
2221 REAL_VALUE_FROM_CONST_DOUBLE (r
, op1
);
2222 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2224 wordpart
[0][1] = GEN_INT (l
[0]);
2225 wordpart
[1][1] = GEN_INT (l
[1]);
2226 wordpart
[2][1] = GEN_INT (l
[2]);
2227 wordpart
[3][1] = GEN_INT (l
[3]);
2231 wordpart
[0][1] = op1
;
2232 wordpart
[1][1] = op1
;
2233 wordpart
[2][1] = op1
;
2234 wordpart
[3][1] = op1
;
2237 /* Easy case: try moving the quad as two pairs. Check for moving between
2238 an even/odd register pair and a memory location.
2239 Also handle new v9 fp regs here. */
2240 /* ??? Should also handle the case of non-offsettable addresses here.
2241 We can at least do the first pair as a ldd/std, and then do the third
2242 and fourth words individually. */
2243 if ((optype0
== REGOP
&& optype1
== OFFSOP
&& (REGNO (op0
) & 1) == 0)
2244 || (optype0
== OFFSOP
&& optype1
== REGOP
&& (REGNO (op1
) & 1) == 0))
2248 if (optype0
== REGOP
)
2249 mem
= op1
, reg
= op0
;
2251 mem
= op0
, reg
= op1
;
2253 if (mem_aligned_8 (mem
)
2254 /* If this is a floating point register higher than %f31,
2255 then we *must* use an aligned load, since `ld' will not accept
2256 the register number. */
2257 || (TARGET_V9
&& REGNO (reg
) >= SPARC_FIRST_V9_FP_REG
))
2259 if (TARGET_V9
&& FP_REG_P (reg
) && TARGET_HARD_QUAD
)
2261 if ((REGNO (reg
) & 3) != 0)
2263 /* ??? Can `mem' have an inappropriate alignment here? */
2264 return (mem
== op1
? "ldq %1,%0" : "stq %1,%0");
2266 operands
[2] = adj_offsettable_operand (mem
, 8);
2267 /* ??? In arch64 case, shouldn't we use ldd/std for fp regs. */
2269 return TARGET_ARCH64
? "ldx %1,%0;ldx %2,%R0" : "ldd %1,%0;ldd %2,%S0";
2271 return TARGET_ARCH64
? "stx %1,%0;stx %R1,%2" : "std %1,%0;std %S1,%2";
2275 /* If the first move would clobber the source of the second one,
2276 do them in the other order. */
2278 /* Overlapping registers? */
2281 if (optype0
== REGOP
&& optype1
== REGOP
2282 && (REGNO (op0
) == REGNO (wordpart
[1][3])
2283 || REGNO (op0
) == REGNO (wordpart
[1][2])
2284 || REGNO (op0
) == REGNO (wordpart
[1][1])))
2286 /* Do fourth word. */
2287 output_asm_insn (singlemove_string (wordpart
[3]), wordpart
[3]);
2288 /* Do the third word. */
2289 output_asm_insn (singlemove_string (wordpart
[2]), wordpart
[2]);
2290 /* Do the second word. */
2291 output_asm_insn (singlemove_string (wordpart
[1]), wordpart
[1]);
2292 /* Do lowest-numbered word. */
2293 output_asm_insn (singlemove_string (wordpart
[0]), wordpart
[0]);
2297 else /* TARGET_ARCH64 */
2299 if (optype0
== REGOP
&& optype1
== REGOP
2300 && REGNO (op0
) == REGNO (wordpart
[1][1]))
2302 output_asm_insn ("mov %1,%0", wordpart
[1]);
2303 output_asm_insn ("mov %1,%0", wordpart
[0]);
2308 /* Loading into a register which overlaps a register used in the address. */
2309 if (optype0
== REGOP
&& optype1
!= REGOP
2310 && reg_overlap_mentioned_p (op0
, op1
))
2312 /* ??? Not implemented yet. This is a bit complicated, because we
2313 must load which ever part overlaps the address last. If the address
2314 is a double-reg address, then there are two parts which need to
2315 be done last, which is impossible. We would need a scratch register
2320 /* Normal case: move the words in lowest to highest address order. */
2324 output_asm_insn (singlemove_string (wordpart
[0]), wordpart
[0]);
2326 /* Make any unoffsettable addresses point at the second word. */
2328 output_asm_insn ("add %0,0x4,%0", &addreg0
);
2330 output_asm_insn ("add %0,0x4,%0", &addreg1
);
2332 /* Do the second word. */
2333 output_asm_insn (singlemove_string (wordpart
[1]), wordpart
[1]);
2335 /* Make any unoffsettable addresses point at the third word. */
2337 output_asm_insn ("add %0,0x4,%0", &addreg0
);
2339 output_asm_insn ("add %0,0x4,%0", &addreg1
);
2341 /* Do the third word. */
2342 output_asm_insn (singlemove_string (wordpart
[2]), wordpart
[2]);
2344 /* Make any unoffsettable addresses point at the fourth word. */
2346 output_asm_insn ("add %0,0x4,%0", &addreg0
);
2348 output_asm_insn ("add %0,0x4,%0", &addreg1
);
2350 /* Do the fourth word. */
2351 output_asm_insn (singlemove_string (wordpart
[3]), wordpart
[3]);
2353 /* Undo the adds we just did. */
2355 output_asm_insn ("add %0,-0xc,%0", &addreg0
);
2357 output_asm_insn ("add %0,-0xc,%0", &addreg1
);
2359 else /* TARGET_ARCH64 */
2361 output_asm_insn (doublemove_string (wordpart
[0]), wordpart
[0]);
2363 /* Make any unoffsettable addresses point at the second word. */
2365 output_asm_insn ("add %0,0x8,%0", &addreg0
);
2367 output_asm_insn ("add %0,0x8,%0", &addreg1
);
2369 /* Do the second word. */
2370 output_asm_insn (doublemove_string (wordpart
[1]), wordpart
[1]);
2372 /* Undo the adds we just did. */
2374 output_asm_insn ("add %0,-0x8,%0", &addreg0
);
2376 output_asm_insn ("add %0,-0x8,%0", &addreg1
);
2382 /* Output assembler code to perform a doubleword move insn with operands
2383 OPERANDS, one of which must be a floating point register. */
2386 output_fp_move_double (operands
)
2389 if (FP_REG_P (operands
[0]))
2391 if (FP_REG_P (operands
[1]))
2394 return "fmovd %1,%0";
2396 return "fmovs %1,%0\n\tfmovs %R1,%R0";
2398 else if (GET_CODE (operands
[1]) == REG
)
2401 return output_move_double (operands
);
2403 else if (FP_REG_P (operands
[1]))
2405 if (GET_CODE (operands
[0]) == REG
)
2408 return output_move_double (operands
);
2413 /* Output assembler code to perform a quadword move insn with operands
2414 OPERANDS, one of which must be a floating point register. */
2417 output_fp_move_quad (operands
)
2420 register rtx op0
= operands
[0];
2421 register rtx op1
= operands
[1];
2427 if (TARGET_V9
&& TARGET_HARD_QUAD
)
2428 return "fmovq %1,%0";
2430 return "fmovd %1,%0\n\tfmovd %S1,%S0";
2432 return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0";
2434 else if (GET_CODE (op1
) == REG
)
2437 return output_move_quad (operands
);
2439 else if (FP_REG_P (op1
))
2441 if (GET_CODE (op0
) == REG
)
2444 return output_move_quad (operands
);
2450 /* Return a REG that occurs in ADDR with coefficient 1.
2451 ADDR can be effectively incremented by incrementing REG. */
2454 find_addr_reg (addr
)
2457 while (GET_CODE (addr
) == PLUS
)
2459 /* We absolutely can not fudge the frame pointer here, because the
2460 frame pointer must always be 8 byte aligned. It also confuses
2462 if (GET_CODE (XEXP (addr
, 0)) == REG
2463 && REGNO (XEXP (addr
, 0)) != FRAME_POINTER_REGNUM
)
2464 addr
= XEXP (addr
, 0);
2465 else if (GET_CODE (XEXP (addr
, 1)) == REG
2466 && REGNO (XEXP (addr
, 1)) != FRAME_POINTER_REGNUM
)
2467 addr
= XEXP (addr
, 1);
2468 else if (CONSTANT_P (XEXP (addr
, 0)))
2469 addr
= XEXP (addr
, 1);
2470 else if (CONSTANT_P (XEXP (addr
, 1)))
2471 addr
= XEXP (addr
, 0);
2475 if (GET_CODE (addr
) == REG
)
2480 #if 0 /* not currently used */
2483 output_sized_memop (opname
, mode
, signedp
)
2485 enum machine_mode mode
;
2488 static char *ld_size_suffix_u
[] = { "ub", "uh", "", "?", "d" };
2489 static char *ld_size_suffix_s
[] = { "sb", "sh", "", "?", "d" };
2490 static char *st_size_suffix
[] = { "b", "h", "", "?", "d" };
2491 char **opnametab
, *modename
;
2493 if (opname
[0] == 'l')
2495 opnametab
= ld_size_suffix_s
;
2497 opnametab
= ld_size_suffix_u
;
2499 opnametab
= st_size_suffix
;
2500 modename
= opnametab
[GET_MODE_SIZE (mode
) >> 1];
2502 fprintf (asm_out_file
, "\t%s%s", opname
, modename
);
2506 output_move_with_extension (operands
)
2509 if (GET_MODE (operands
[2]) == HImode
)
2510 output_asm_insn ("sll %2,0x10,%0", operands
);
2511 else if (GET_MODE (operands
[2]) == QImode
)
2512 output_asm_insn ("sll %2,0x18,%0", operands
);
2516 #endif /* not currently used */
2519 /* ??? These are only used by the movstrsi pattern, but we get better code
2520 in general without that, because emit_block_move can do just as good a
2521 job as this function does when alignment and size are known. When they
2522 aren't known, a call to strcpy may be faster anyways, because it is
2523 likely to be carefully crafted assembly language code, and below we just
2524 do a byte-wise copy.
2526 Also, emit_block_move expands into multiple read/write RTL insns, which
2527 can then be optimized, whereas our movstrsi pattern can not be optimized
2530 /* Load the address specified by OPERANDS[3] into the register
2531 specified by OPERANDS[0].
2533 OPERANDS[3] may be the result of a sum, hence it could either be:
2538 (3) REG + REG + CONST_INT
2539 (4) REG + REG (special case of 3).
2541 Note that (3) is not a legitimate address.
2542 All cases are handled here. */
2545 output_load_address (operands
)
2550 if (CONSTANT_P (operands
[3]))
2552 output_asm_insn ("set %3,%0", operands
);
2556 if (REG_P (operands
[3]))
2558 if (REGNO (operands
[0]) != REGNO (operands
[3]))
2559 output_asm_insn ("mov %3,%0", operands
);
2563 if (GET_CODE (operands
[3]) != PLUS
)
2566 base
= XEXP (operands
[3], 0);
2567 offset
= XEXP (operands
[3], 1);
2569 if (GET_CODE (base
) == CONST_INT
)
2576 if (GET_CODE (offset
) != CONST_INT
)
2578 /* Operand is (PLUS (REG) (REG)). */
2580 offset
= const0_rtx
;
2586 operands
[7] = offset
;
2587 if (SMALL_INT (offset
))
2588 output_asm_insn ("add %6,%7,%0", operands
);
2590 output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands
);
2592 else if (GET_CODE (base
) == PLUS
)
2594 operands
[6] = XEXP (base
, 0);
2595 operands
[7] = XEXP (base
, 1);
2596 operands
[8] = offset
;
2598 if (SMALL_INT (offset
))
2599 output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands
);
2601 output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands
);
2607 /* Output code to place a size count SIZE in register REG.
2608 ALIGN is the size of the unit of transfer.
2610 Because block moves are pipelined, we don't include the
2611 first element in the transfer of SIZE to REG. */
2614 output_size_for_block_move (size
, reg
, align
)
2621 xoperands
[1] = size
;
2622 xoperands
[2] = align
;
2623 if (GET_CODE (size
) == REG
)
2624 output_asm_insn ("sub %1,%2,%0", xoperands
);
2628 = gen_rtx (CONST_INT
, VOIDmode
, INTVAL (size
) - INTVAL (align
));
2629 output_asm_insn ("set %1,%0", xoperands
);
2633 /* Emit code to perform a block move.
2635 OPERANDS[0] is the destination.
2636 OPERANDS[1] is the source.
2637 OPERANDS[2] is the size.
2638 OPERANDS[3] is the alignment safe to use.
2639 OPERANDS[4] is a register we can safely clobber as a temp. */
2642 output_block_move (operands
)
2645 /* A vector for our computed operands. Note that load_output_address
2646 makes use of (and can clobber) up to the 8th element of this vector. */
2649 static int movstrsi_label
= 0;
2651 rtx temp1
= operands
[4];
2652 rtx sizertx
= operands
[2];
2653 rtx alignrtx
= operands
[3];
2654 int align
= INTVAL (alignrtx
);
2655 char label3
[30], label5
[30];
2657 xoperands
[0] = operands
[0];
2658 xoperands
[1] = operands
[1];
2659 xoperands
[2] = temp1
;
2661 /* We can't move more than this many bytes at a time because we have only
2662 one register, %g1, to move them through. */
2663 if (align
> UNITS_PER_WORD
)
2665 align
= UNITS_PER_WORD
;
2666 alignrtx
= gen_rtx (CONST_INT
, VOIDmode
, UNITS_PER_WORD
);
2669 /* We consider 8 ld/st pairs, for a total of 16 inline insns to be
2670 reasonable here. (Actually will emit a maximum of 18 inline insns for
2671 the case of size == 31 and align == 4). */
2673 if (GET_CODE (sizertx
) == CONST_INT
&& (INTVAL (sizertx
) / align
) <= 8
2674 && memory_address_p (QImode
, plus_constant_for_output (xoperands
[0],
2676 && memory_address_p (QImode
, plus_constant_for_output (xoperands
[1],
2679 int size
= INTVAL (sizertx
);
2682 /* We will store different integers into this particular RTX. */
2683 xoperands
[2] = rtx_alloc (CONST_INT
);
2684 PUT_MODE (xoperands
[2], VOIDmode
);
2686 /* This case is currently not handled. Abort instead of generating
2688 if (align
> UNITS_PER_WORD
)
2691 if (TARGET_ARCH64
&& align
>= 8)
2693 for (i
= (size
>> 3) - 1; i
>= 0; i
--)
2695 INTVAL (xoperands
[2]) = (i
<< 3) + offset
;
2696 output_asm_insn ("ldx [%a1+%2],%%g1\n\tstx %%g1,[%a0+%2]",
2699 offset
+= (size
& ~0x7);
2707 for (i
= (size
>> 2) - 1; i
>= 0; i
--)
2709 INTVAL (xoperands
[2]) = (i
<< 2) + offset
;
2710 output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]",
2713 offset
+= (size
& ~0x3);
2721 for (i
= (size
>> 1) - 1; i
>= 0; i
--)
2723 INTVAL (xoperands
[2]) = (i
<< 1) + offset
;
2724 output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]",
2727 offset
+= (size
& ~0x1);
2735 for (i
= size
- 1; i
>= 0; i
--)
2737 INTVAL (xoperands
[2]) = i
+ offset
;
2738 output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]",
2744 /* We should never reach here. */
2748 /* If the size isn't known to be a multiple of the alignment,
2749 we have to do it in smaller pieces. If we could determine that
2750 the size was a multiple of 2 (or whatever), we could be smarter
2752 if (GET_CODE (sizertx
) != CONST_INT
)
2756 int size
= INTVAL (sizertx
);
2757 while (size
% align
)
2761 if (align
!= INTVAL (alignrtx
))
2762 alignrtx
= gen_rtx (CONST_INT
, VOIDmode
, align
);
2764 xoperands
[3] = gen_rtx (CONST_INT
, VOIDmode
, movstrsi_label
++);
2765 xoperands
[4] = gen_rtx (CONST_INT
, VOIDmode
, align
);
2766 xoperands
[5] = gen_rtx (CONST_INT
, VOIDmode
, movstrsi_label
++);
2768 ASM_GENERATE_INTERNAL_LABEL (label3
, "Lm", INTVAL (xoperands
[3]));
2769 ASM_GENERATE_INTERNAL_LABEL (label5
, "Lm", INTVAL (xoperands
[5]));
2771 /* This is the size of the transfer. Emit code to decrement the size
2772 value by ALIGN, and store the result in the temp1 register. */
2773 output_size_for_block_move (sizertx
, temp1
, alignrtx
);
2775 /* Must handle the case when the size is zero or negative, so the first thing
2776 we do is compare the size against zero, and only copy bytes if it is
2777 zero or greater. Note that we have already subtracted off the alignment
2778 once, so we must copy 1 alignment worth of bytes if the size is zero
2781 The SUN assembler complains about labels in branch delay slots, so we
2782 do this before outputting the load address, so that there will always
2783 be a harmless insn between the branch here and the next label emitted
2789 sprintf (pattern
, "cmp %%2,0\n\tbl %s", &label5
[1]);
2790 output_asm_insn (pattern
, xoperands
);
2793 zoperands
[0] = operands
[0];
2794 zoperands
[3] = plus_constant_for_output (operands
[0], align
);
2795 output_load_address (zoperands
);
2797 /* ??? This might be much faster if the loops below were preconditioned
2800 That is, at run time, copy enough bytes one at a time to ensure that the
2801 target and source addresses are aligned to the the largest possible
2802 alignment. Then use a preconditioned unrolled loop to copy say 16
2803 bytes at a time. Then copy bytes one at a time until finish the rest. */
2805 /* Output the first label separately, so that it is spaced properly. */
2807 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "Lm", INTVAL (xoperands
[3]));
2811 register char *ld_suffix
= ((align
== 1) ? "ub" : (align
== 2) ? "uh"
2812 : (align
== 8 && TARGET_ARCH64
) ? "x" : "");
2813 register char *st_suffix
= ((align
== 1) ? "b" : (align
== 2) ? "h"
2814 : (align
== 8 && TARGET_ARCH64
) ? "x" : "");
2816 sprintf (pattern
, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix
, &label3
[1], st_suffix
, &label5
[1]);
2817 output_asm_insn (pattern
, xoperands
);
2824 /* Output reasonable peephole for set-on-condition-code insns.
2825 Note that these insns assume a particular way of defining
2826 labels. Therefore, *both* sparc.h and this function must
2827 be changed if a new syntax is needed. */
2830 output_scc_insn (operands
, insn
)
2834 static char string
[100];
2835 rtx label
= 0, next
= insn
;
2838 /* Try doing a jump optimization which jump.c can't do for us
2839 because we did not expose that setcc works by using branches.
2841 If this scc insn is followed by an unconditional branch, then have
2842 the jump insn emitted here jump to that location, instead of to
2843 the end of the scc sequence as usual. */
2847 if (GET_CODE (next
) == CODE_LABEL
)
2849 next
= NEXT_INSN (next
);
2853 while (GET_CODE (next
) == NOTE
|| GET_CODE (next
) == CODE_LABEL
);
2855 /* If we are in a sequence, and the following insn is a sequence also,
2856 then just following the current insn's next field will take us to the
2857 first insn of the next sequence, which is the wrong place. We don't
2858 want to optimize with a branch that has had its delay slot filled.
2859 Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next
2860 which fails only if NEXT is such a branch. */
2862 if (next
&& GET_CODE (next
) == JUMP_INSN
&& simplejump_p (next
)
2863 && (! final_sequence
|| NEXT_INSN (PREV_INSN (next
)) == next
))
2864 label
= JUMP_LABEL (next
);
2865 /* If not optimizing, jump label fields are not set. To be safe, always
2866 check here to whether label is still zero. */
2869 label
= gen_label_rtx ();
2873 LABEL_NUSES (label
) += 1;
2875 /* operands[3] is an unused slot. */
2876 operands
[3] = label
;
2878 /* If we are in a delay slot, assume it is the delay slot of an fpcc
2879 insn since our type isn't allowed anywhere else. */
2881 /* ??? Fpcc instructions no longer have delay slots, so this code is
2882 probably obsolete. */
2884 /* The fastest way to emit code for this is an annulled branch followed
2885 by two move insns. This will take two cycles if the branch is taken,
2886 and three cycles if the branch is not taken.
2888 However, if we are in the delay slot of another branch, this won't work,
2889 because we can't put a branch in the delay slot of another branch.
2890 The above sequence would effectively take 3 or 4 cycles respectively
2891 since a no op would have be inserted between the two branches.
2892 In this case, we want to emit a move, annulled branch, and then the
2893 second move. This sequence always takes 3 cycles, and hence is faster
2894 when we are in a branch delay slot. */
2898 strcpy (string
, "mov 0,%0\n\t");
2899 strcat (string
, output_cbranch (operands
[2], 3, 0, 1, 0));
2900 strcat (string
, "\n\tmov 1,%0");
2904 strcpy (string
, output_cbranch (operands
[2], 3, 0, 1, 0));
2905 strcat (string
, "\n\tmov 1,%0\n\tmov 0,%0");
2909 strcat (string
, "\n%l3:");
2914 /* Vectors to keep interesting information about registers where it can easily
2915 be got. We use to use the actual mode value as the bit number, but there
2916 are more than 32 modes now. Instead we use two tables: one indexed by
2917 hard register number, and one indexed by mode. */
2919 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2920 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2921 mapped into one sparc_mode_class mode. */
2923 enum sparc_mode_class
{
2924 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
2925 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
2929 /* Modes for single-word and smaller quantities. */
2930 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2932 /* Modes for double-word and smaller quantities. */
2933 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2935 /* Modes for quad-word and smaller quantities. */
2936 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2938 /* Modes for single-float quantities. We must allow any single word or
2939 smaller quantity. This is because the fix/float conversion instructions
2940 take integer inputs/outputs from the float registers. */
2941 #define SF_MODES (S_MODES)
2943 /* Modes for double-float and smaller quantities. */
2944 #define DF_MODES (S_MODES | D_MODES)
2946 /* ??? Sparc64 fp regs cannot hold DImode values. */
2947 #define DF_MODES64 (SF_MODES | (1 << (int) DF_MODE) /* | (1 << (int) D_MODE)*/)
2949 /* Modes for double-float only quantities. */
2950 /* ??? Sparc64 fp regs cannot hold DImode values.
2951 See fix_truncsfdi2. */
2952 #define DF_ONLY_MODES ((1 << (int) DF_MODE) /*| (1 << (int) D_MODE)*/)
2954 /* Modes for double-float and larger quantities. */
2955 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2957 /* Modes for quad-float only quantities. */
2958 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2960 /* Modes for quad-float and smaller quantities. */
2961 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2963 /* ??? Sparc64 fp regs cannot hold DImode values.
2964 See fix_truncsfdi2. */
2965 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2967 /* Modes for condition codes. */
2968 #define CC_MODES (1 << (int) CC_MODE)
2969 #define CCFP_MODES (1 << (int) CCFP_MODE)
2971 /* Value is 1 if register/mode pair is acceptable on sparc.
2972 The funny mixture of D and T modes is because integer operations
2973 do not specially operate on tetra quantities, so non-quad-aligned
2974 registers can hold quadword quantities (except %o4 and %i4 because
2975 they cross fixed registers). */
2977 /* This points to either the 32 bit or the 64 bit version. */
2978 int *hard_regno_mode_classes
;
2980 static int hard_32bit_mode_classes
[] = {
2981 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2982 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
2983 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2984 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
2986 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2987 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2988 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2989 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2991 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2992 and none can hold SFmode/SImode values. */
2993 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2994 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2995 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2996 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2999 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3005 static int hard_64bit_mode_classes
[] = {
3006 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3007 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3008 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3009 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3011 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
3012 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
3013 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
3014 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
3016 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3017 and none can hold SFmode/SImode values. */
3018 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
3019 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
3020 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
3021 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
3024 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3030 int sparc_mode_class
[NUM_MACHINE_MODES
];
3032 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3039 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3041 switch (GET_MODE_CLASS (i
))
3044 case MODE_PARTIAL_INT
:
3045 case MODE_COMPLEX_INT
:
3046 if (GET_MODE_SIZE (i
) <= 4)
3047 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3048 else if (GET_MODE_SIZE (i
) == 8)
3049 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3050 else if (GET_MODE_SIZE (i
) == 16)
3051 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3052 else if (GET_MODE_SIZE (i
) == 32)
3053 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3055 sparc_mode_class
[i
] = 0;
3058 case MODE_COMPLEX_FLOAT
:
3059 if (GET_MODE_SIZE (i
) <= 4)
3060 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3061 else if (GET_MODE_SIZE (i
) == 8)
3062 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3063 else if (GET_MODE_SIZE (i
) == 16)
3064 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3065 else if (GET_MODE_SIZE (i
) == 32)
3066 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3068 sparc_mode_class
[i
] = 0;
3072 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3073 we must explicitly check for them here. */
3074 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3075 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3076 else if (i
== (int) CCmode
|| i
== (int) CC_NOOVmode
3077 || i
== (int) CCXmode
|| i
== (int) CCX_NOOVmode
)
3078 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3080 sparc_mode_class
[i
] = 0;
3086 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3088 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3090 /* Initialize the array used by REGNO_REG_CLASS. */
3091 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3094 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3096 sparc_regno_reg_class
[i
] = FP_REGS
;
3098 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3100 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3102 sparc_regno_reg_class
[i
] = NO_REGS
;
3106 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3107 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3108 v9 int regs as it simplifies the code. */
3111 save_regs (file
, low
, high
, base
, offset
, n_regs
, real_offset
)
3121 if (TARGET_ARCH64
&& high
<= 32)
3123 for (i
= low
; i
< high
; i
++)
3125 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3127 fprintf (file
, "\tstx %s,[%s+%d]\n",
3128 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3129 if (dwarf2out_do_frame ())
3130 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3137 for (i
= low
; i
< high
; i
+= 2)
3139 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3140 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3142 fprintf (file
, "\tstd %s,[%s+%d]\n",
3143 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3144 if (dwarf2out_do_frame ())
3146 char *l
= dwarf2out_cfi_label ();
3147 dwarf2out_reg_save (l
, i
, real_offset
+ 4 * n_regs
);
3148 dwarf2out_reg_save (l
, i
+1, real_offset
+ 4 * n_regs
+ 4);
3154 fprintf (file
, "\tst %s,[%s+%d]\n",
3155 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3156 if (dwarf2out_do_frame ())
3157 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3160 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3162 fprintf (file
, "\tst %s,[%s+%d]\n",
3163 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4);
3164 if (dwarf2out_do_frame ())
3165 dwarf2out_reg_save ("", i
+ 1, real_offset
+ 4 * n_regs
+ 4);
3173 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3175 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3176 v9 int regs as it simplifies the code. */
3179 restore_regs (file
, low
, high
, base
, offset
, n_regs
)
3188 if (TARGET_ARCH64
&& high
<= 32)
3190 for (i
= low
; i
< high
; i
++)
3192 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3193 fprintf (file
, "\tldx [%s+%d], %s\n",
3194 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3200 for (i
= low
; i
< high
; i
+= 2)
3202 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3203 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3204 fprintf (file
, "\tldd [%s+%d], %s\n",
3205 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3208 fprintf (file
, "\tld [%s+%d],%s\n",
3209 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3211 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3212 fprintf (file
, "\tld [%s+%d],%s\n",
3213 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
3220 /* Static variables we want to share between prologue and epilogue. */
3222 /* Number of live general or floating point registers needed to be saved
3223 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
3224 static int num_gfregs
;
3226 /* Compute the frame size required by the function. This function is called
3227 during the reload pass and also by output_function_prologue(). */
3230 compute_frame_size (size
, leaf_function
)
3235 int outgoing_args_size
= (current_function_outgoing_args_size
3236 + REG_PARM_STACK_SPACE (current_function_decl
));
3238 if (TARGET_EPILOGUE
)
3240 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3241 even to v9 int regs to be consistent with save_regs/restore_regs. */
3245 for (i
= 0; i
< 8; i
++)
3246 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3251 for (i
= 0; i
< 8; i
+= 2)
3252 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3253 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3257 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3258 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3259 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3263 /* Set up values for use in `function_epilogue'. */
3264 num_gfregs
= n_regs
;
3266 if (leaf_function
&& n_regs
== 0
3267 && size
== 0 && current_function_outgoing_args_size
== 0)
3269 actual_fsize
= apparent_fsize
= 0;
3273 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3274 The stack bias (if any) is taken out to undo its effects. */
3275 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ SPARC_STACK_BIAS
+ 7) & -8;
3276 apparent_fsize
+= n_regs
* 4;
3277 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3280 /* Make sure nothing can clobber our register windows.
3281 If a SAVE must be done, or there is a stack-local variable,
3282 the register window area must be allocated.
3283 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3284 if (leaf_function
== 0 || size
> 0)
3285 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
3287 return SPARC_STACK_ALIGN (actual_fsize
);
3290 /* Build a (32 bit) big number in a register. */
3291 /* ??? We may be able to use the set macro here too. */
3294 build_big_number (file
, num
, reg
)
3299 if (num
>= 0 || ! TARGET_ARCH64
)
3301 fprintf (file
, "\tsethi %%hi(%d),%s\n", num
, reg
);
3302 if ((num
& 0x3ff) != 0)
3303 fprintf (file
, "\tor %s,%%lo(%d),%s\n", reg
, num
, reg
);
3305 else /* num < 0 && TARGET_ARCH64 */
3307 /* Sethi does not sign extend, so we must use a little trickery
3308 to use it for negative numbers. Invert the constant before
3309 loading it in, then use xor immediate to invert the loaded bits
3310 (along with the upper 32 bits) to the desired constant. This
3311 works because the sethi and immediate fields overlap. */
3314 int low
= -0x400 + (asize
& 0x3FF);
3316 fprintf (file
, "\tsethi %%hi(%d),%s\n\txor %s,%d,%s\n",
3317 inv
, reg
, reg
, low
, reg
);
3321 /* Output code for the function prologue. */
3324 output_function_prologue (file
, size
, leaf_function
)
3329 /* Need to use actual_fsize, since we are also allocating
3330 space for our callee (and our own register save area). */
3331 actual_fsize
= compute_frame_size (size
, leaf_function
);
3335 frame_base_name
= "%sp";
3336 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3340 frame_base_name
= "%fp";
3341 frame_base_offset
= SPARC_STACK_BIAS
;
3344 /* This is only for the human reader. */
3345 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
3347 if (actual_fsize
== 0)
3349 else if (! leaf_function
&& ! TARGET_BROKEN_SAVERESTORE
)
3351 if (actual_fsize
<= 4096)
3352 fprintf (file
, "\tsave %%sp,-%d,%%sp\n", actual_fsize
);
3353 else if (actual_fsize
<= 8192)
3355 fprintf (file
, "\tsave %%sp,-4096,%%sp\n");
3356 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
- 4096);
3360 build_big_number (file
, -actual_fsize
, "%g1");
3361 fprintf (file
, "\tsave %%sp,%%g1,%%sp\n");
3364 else if (! leaf_function
&& TARGET_BROKEN_SAVERESTORE
)
3366 /* We assume the environment will properly handle or otherwise avoid
3367 trouble associated with an interrupt occurring after the `save' or
3368 trap occurring during it. */
3369 fprintf (file
, "\tsave\n");
3371 if (actual_fsize
<= 4096)
3372 fprintf (file
, "\tadd %%fp,-%d,%%sp\n", actual_fsize
);
3373 else if (actual_fsize
<= 8192)
3375 fprintf (file
, "\tadd %%fp,-4096,%%sp\n");
3376 fprintf (file
, "\tadd %%fp,-%d,%%sp\n", actual_fsize
- 4096);
3380 build_big_number (file
, -actual_fsize
, "%g1");
3381 fprintf (file
, "\tadd %%fp,%%g1,%%sp\n");
3384 else /* leaf function */
3386 if (actual_fsize
<= 4096)
3387 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
);
3388 else if (actual_fsize
<= 8192)
3390 fprintf (file
, "\tadd %%sp,-4096,%%sp\n");
3391 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
- 4096);
3395 build_big_number (file
, -actual_fsize
, "%g1");
3396 fprintf (file
, "\tadd %%sp,%%g1,%%sp\n");
3400 if (dwarf2out_do_frame () && actual_fsize
)
3402 char *label
= dwarf2out_cfi_label ();
3404 /* The canonical frame address refers to the top of the frame. */
3405 dwarf2out_def_cfa (label
, (leaf_function
? STACK_POINTER_REGNUM
3406 : FRAME_POINTER_REGNUM
),
3409 if (! leaf_function
)
3411 /* Note the register window save. This tells the unwinder that
3412 it needs to restore the window registers from the previous
3413 frame's window save area at 0(cfa). */
3414 dwarf2out_window_save (label
);
3416 /* The return address (-8) is now in %i7. */
3417 dwarf2out_return_reg (label
, 31);
3421 /* If doing anything with PIC, do it now. */
3423 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
3425 /* Call saved registers are saved just above the outgoing argument area. */
3428 int offset
, real_offset
, n_regs
;
3431 real_offset
= -apparent_fsize
;
3432 offset
= -apparent_fsize
+ frame_base_offset
;
3433 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
3435 /* ??? This might be optimized a little as %g1 might already have a
3436 value close enough that a single add insn will do. */
3437 /* ??? Although, all of this is probably only a temporary fix
3438 because if %g1 can hold a function result, then
3439 output_function_epilogue will lose (the result will get
3441 build_big_number (file
, offset
, "%g1");
3442 fprintf (file
, "\tadd %s,%%g1,%%g1\n", frame_base_name
);
3448 base
= frame_base_name
;
3451 if (TARGET_EPILOGUE
&& ! leaf_function
)
3452 /* ??? Originally saved regs 0-15 here. */
3453 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3454 else if (leaf_function
)
3455 /* ??? Originally saved regs 0-31 here. */
3456 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3457 if (TARGET_EPILOGUE
)
3458 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
,
3463 if (leaf_function
&& actual_fsize
!= 0)
3465 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3466 if (! TARGET_EPILOGUE
)
3467 leaf_label
= gen_label_rtx ();
3471 /* Output code for the function epilogue. */
3474 output_function_epilogue (file
, size
, leaf_function
)
3483 emit_label_after (leaf_label
, get_last_insn ());
3484 final_scan_insn (get_last_insn (), file
, 0, 0, 1);
3487 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3488 else if (profile_block_flag
== 2)
3490 FUNCTION_BLOCK_PROFILER_EXIT(file
);
3494 /* Restore any call saved registers. */
3500 offset
= -apparent_fsize
+ frame_base_offset
;
3501 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
3503 build_big_number (file
, offset
, "%g1");
3504 fprintf (file
, "\tadd %s,%%g1,%%g1\n", frame_base_name
);
3510 base
= frame_base_name
;
3513 if (TARGET_EPILOGUE
&& ! leaf_function
)
3514 /* ??? Originally saved regs 0-15 here. */
3515 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3516 else if (leaf_function
)
3517 /* ??? Originally saved regs 0-31 here. */
3518 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3519 if (TARGET_EPILOGUE
)
3520 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
3523 /* Work out how to skip the caller's unimp instruction if required. */
3525 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp %o7+12" : "retl");
3527 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp %i7+12" : "ret");
3529 if (TARGET_EPILOGUE
|| leaf_label
)
3531 int old_target_epilogue
= TARGET_EPILOGUE
;
3532 target_flags
&= ~old_target_epilogue
;
3534 if (! leaf_function
)
3536 /* If we wound up with things in our delay slot, flush them here. */
3537 if (current_function_epilogue_delay_list
)
3539 rtx insn
= emit_jump_insn_after (gen_rtx (RETURN
, VOIDmode
),
3541 PATTERN (insn
) = gen_rtx (PARALLEL
, VOIDmode
,
3543 PATTERN (XEXP (current_function_epilogue_delay_list
, 0)),
3545 final_scan_insn (insn
, file
, 1, 0, 1);
3548 fprintf (file
, "\t%s\n\trestore\n", ret
);
3550 /* All of the following cases are for leaf functions. */
3551 else if (current_function_epilogue_delay_list
)
3553 /* eligible_for_epilogue_delay_slot ensures that if this is a
3554 leaf function, then we will only have insn in the delay slot
3555 if the frame size is zero, thus no adjust for the stack is
3557 if (actual_fsize
!= 0)
3559 fprintf (file
, "\t%s\n", ret
);
3560 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
3563 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3564 avoid generating confusing assembly language output. */
3565 else if (actual_fsize
== 0)
3566 fprintf (file
, "\t%s\n\tnop\n", ret
);
3567 else if (actual_fsize
<= 4096)
3568 fprintf (file
, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret
, actual_fsize
);
3569 else if (actual_fsize
<= 8192)
3570 fprintf (file
, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n",
3571 ret
, actual_fsize
- 4096);
3572 else if ((actual_fsize
& 0x3ff) == 0)
3573 fprintf (file
, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3576 fprintf (file
, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3577 actual_fsize
, actual_fsize
, ret
);
3578 target_flags
|= old_target_epilogue
;
3582 /* Functions for handling argument passing.
3584 For v8 the first six args are normally in registers and the rest are
3585 pushed. Any arg that starts within the first 6 words is at least
3586 partially passed in a register unless its data type forbids.
3588 For v9, the argument registers are laid out as an array of 16 elements
3589 and arguments are added sequentially. The first 6 int args and up to the
3590 first 16 fp args (depending on size) are passed in regs.
3592 Slot Stack Integral Float Float in structure Double Long Double
3593 ---- ----- -------- ----- ------------------ ------ -----------
3594 15 [SP+248] %f31 %f30,%f31 %d30
3595 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3596 13 [SP+232] %f27 %f26,%f27 %d26
3597 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3598 11 [SP+216] %f23 %f22,%f23 %d22
3599 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3600 9 [SP+200] %f19 %f18,%f19 %d18
3601 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3602 7 [SP+184] %f15 %f14,%f15 %d14
3603 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3604 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3605 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3606 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3607 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3608 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3609 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3611 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3613 Integral arguments are always passed as 64 bit quantities appropriately
3616 Passing of floating point values is handled as follows.
3617 If a prototype is in scope:
3618 If the value is in a named argument (i.e. not a stdarg function or a
3619 value not part of the `...') then the value is passed in the appropriate
3621 If the value is part of the `...' and is passed in one of the first 6
3622 slots then the value is passed in the appropriate int reg.
3623 If the value is part of the `...' and is not passed in one of the first 6
3624 slots then the value is passed in memory.
3625 If a prototype is not in scope:
3626 If the value is one of the first 6 arguments the value is passed in the
3627 appropriate integer reg and the appropriate fp reg.
3628 If the value is not one of the first 6 arguments the value is passed in
3629 the appropriate fp reg and in memory.
3632 /* Maximum number of int regs for args. */
3633 #define SPARC_INT_ARG_MAX 6
3634 /* Maximum number of fp regs for args. */
3635 #define SPARC_FP_ARG_MAX 16
3637 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3639 /* Handle the INIT_CUMULATIVE_ARGS macro.
3640 Initialize a variable CUM of type CUMULATIVE_ARGS
3641 for a call to a function whose data type is FNTYPE.
3642 For a library call, FNTYPE is 0. */
3645 init_cumulative_args (cum
, fntype
, libname
, indirect
)
3646 CUMULATIVE_ARGS
*cum
;
3647 tree fntype
, libname
;
3651 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
3652 cum
->libcall_p
= fntype
== 0;
3655 /* Compute the slot number to pass an argument in.
3656 Returns the slot number or -1 if passing on the stack.
3658 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3659 the preceding args and about the function being called.
3660 MODE is the argument's machine mode.
3661 TYPE is the data type of the argument (as a tree).
3662 This is null for libcalls where that information may
3664 NAMED is nonzero if this argument is a named parameter
3665 (otherwise it is an extra parameter matching an ellipsis).
3666 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3667 *PREGNO records the register number to use if scalar type.
3668 *PPADDING records the amount of padding needed in words. */
3671 function_arg_slotno (cum
, mode
, type
, named
, incoming_p
, pregno
, ppadding
)
3672 const CUMULATIVE_ARGS
*cum
;
3673 enum machine_mode mode
;
3680 int regbase
= (incoming_p
3681 ? SPARC_INCOMING_INT_ARG_FIRST
3682 : SPARC_OUTGOING_INT_ARG_FIRST
);
3683 int slotno
= cum
->words
;
3688 if (type
!= 0 && TREE_ADDRESSABLE (type
))
3691 && type
!= 0 && mode
== BLKmode
3692 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
3698 /* MODE is VOIDmode when generating the actual call.
3702 case QImode
: case CQImode
:
3703 case HImode
: case CHImode
:
3704 case SImode
: case CSImode
:
3705 case DImode
: case CDImode
:
3706 if (slotno
>= SPARC_INT_ARG_MAX
)
3708 regno
= regbase
+ slotno
;
3711 case SFmode
: case SCmode
:
3712 case DFmode
: case DCmode
:
3713 case TFmode
: case TCmode
:
3716 if (slotno
>= SPARC_INT_ARG_MAX
)
3718 regno
= regbase
+ slotno
;
3722 if ((mode
== TFmode
|| mode
== TCmode
)
3723 && (slotno
& 1) != 0)
3724 slotno
++, *ppadding
= 1;
3725 if (TARGET_FPU
&& named
)
3727 if (slotno
>= SPARC_FP_ARG_MAX
)
3729 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
3735 if (slotno
>= SPARC_INT_ARG_MAX
)
3737 regno
= regbase
+ slotno
;
3743 /* For sparc64, objects requiring 16 byte alignment get it. */
3746 if (type
&& TYPE_ALIGN (type
) == 128 && (slotno
& 1) != 0)
3747 slotno
++, *ppadding
= 1;
3751 || type
&& TREE_CODE (type
) == UNION_TYPE
)
3753 if (slotno
>= SPARC_INT_ARG_MAX
)
3755 regno
= regbase
+ slotno
;
3760 int intregs_p
= 0, fpregs_p
= 0;
3761 /* The ABI obviously doesn't specify how packed
3762 structures are passed. These are defined to be passed
3763 in int regs if possible, otherwise memory. */
3766 /* First see what kinds of registers we need. */
3767 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3769 if (TREE_CODE (field
) == FIELD_DECL
)
3771 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3776 if (DECL_PACKED (field
))
3780 if (packed_p
|| !named
)
3781 fpregs_p
= 0, intregs_p
= 1;
3783 /* If all arg slots are filled, then must pass on stack. */
3784 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
3786 /* If there are only int args and all int arg slots are filled,
3787 then must pass on stack. */
3788 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
3790 /* Note that even if all int arg slots are filled, fp members may
3791 still be passed in regs if such regs are available.
3792 *PREGNO isn't set because there may be more than one, it's up
3793 to the caller to compute them. */
3806 /* Handle the FUNCTION_ARG macro.
3807 Determine where to put an argument to a function.
3808 Value is zero to push the argument on the stack,
3809 or a hard register in which to store the argument.
3811 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3812 the preceding args and about the function being called.
3813 MODE is the argument's machine mode.
3814 TYPE is the data type of the argument (as a tree).
3815 This is null for libcalls where that information may
3817 NAMED is nonzero if this argument is a named parameter
3818 (otherwise it is an extra parameter matching an ellipsis).
3819 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
3822 function_arg (cum
, mode
, type
, named
, incoming_p
)
3823 const CUMULATIVE_ARGS
*cum
;
3824 enum machine_mode mode
;
3829 int regbase
= (incoming_p
3830 ? SPARC_INCOMING_INT_ARG_FIRST
3831 : SPARC_OUTGOING_INT_ARG_FIRST
);
3832 int slotno
, regno
, padding
;
3835 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
3843 reg
= gen_rtx (REG
, mode
, regno
);
3847 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3848 but also have the slot allocated for them.
3849 If no prototype is in scope fp values in register slots get passed
3850 in two places, either fp regs and int regs or fp regs and memory. */
3851 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3852 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3853 && SPARC_FP_REG_P (regno
))
3855 reg
= gen_rtx (REG
, mode
, regno
);
3856 if (cum
->prototype_p
|| cum
->libcall_p
)
3858 /* "* 2" because fp reg numbers are recorded in 4 byte
3860 /* ??? This will cause the value to be passed in the fp reg and
3861 in the stack. When a prototype exists we want to pass the
3862 value in the reg but reserve space on the stack. That's an
3863 optimization, and is deferred [for a bit]. */
3864 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
3865 return gen_rtx (PARALLEL
, mode
,
3867 gen_rtx (EXPR_LIST
, VOIDmode
,
3868 NULL_RTX
, const0_rtx
),
3869 gen_rtx (EXPR_LIST
, VOIDmode
,
3876 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
3878 int regbase
= (incoming_p
3879 ? SPARC_INCOMING_INT_ARG_FIRST
3880 : SPARC_OUTGOING_INT_ARG_FIRST
);
3881 int intreg
= regbase
+ (regno
- SPARC_FP_ARG_FIRST
) / 2;
3882 return gen_rtx (PARALLEL
, mode
,
3884 gen_rtx (EXPR_LIST
, VOIDmode
,
3886 gen_rtx (EXPR_LIST
, VOIDmode
,
3887 gen_rtx (REG
, mode
, intreg
),
3891 return gen_rtx (PARALLEL
, mode
,
3893 gen_rtx (EXPR_LIST
, VOIDmode
,
3894 NULL_RTX
, const0_rtx
),
3895 gen_rtx (EXPR_LIST
, VOIDmode
,
3899 else if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
3901 /* Structures up to 16 bytes in size are passed in arg slots on the
3902 stack and are promoted to registers where possible. */
3907 /* Starting bit position of a sequence of integer fields, counted from
3908 msb of left most byte, -1 if last field wasn't an int. */
3909 /* ??? This isn't entirely necessary, some simplification
3911 int start_int_bitpos
;
3912 /* Current bitpos in struct, counted from msb of left most byte. */
3913 int bitpos
, this_slotno
;
3914 /* The ABI obviously doesn't specify how packed
3915 structures are passed. These are defined to be passed
3916 in int regs if possible, otherwise memory. */
3919 if (int_size_in_bytes (type
) > 16)
3920 abort (); /* shouldn't get here */
3922 /* We need to compute how many registers are needed so we can allocate
3923 the PARALLEL but before we can do that we need to know whether there
3924 are any packed fields. If there are, int regs are used regardless of
3925 whether there are fp values present. */
3926 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3928 if (TREE_CODE (field
) == FIELD_DECL
3929 && DECL_PACKED (field
))
3936 /* Compute how many registers we need. */
3938 start_int_bitpos
= -1;
3939 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3941 bitpos
= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
));
3942 this_slotno
= slotno
+ bitpos
/ BITS_PER_WORD
;
3943 if (TREE_CODE (field
) == FIELD_DECL
)
3945 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3950 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3951 If it wasn't true we wouldn't be here. */
3953 start_int_bitpos
= -1;
3955 else if (this_slotno
< SPARC_INT_ARG_MAX
)
3957 if (start_int_bitpos
== -1)
3960 start_int_bitpos
= bitpos
;
3964 if (bitpos
% BITS_PER_WORD
== 0)
3973 ret
= gen_rtx (PARALLEL
, BLKmode
, rtvec_alloc (nregs
+ 1));
3975 /* ??? This causes the entire struct to be passed in memory.
3976 This isn't necessary, but is left for later. */
3977 XVECEXP (ret
, 0, 0) = gen_rtx (EXPR_LIST
, VOIDmode
, NULL_RTX
,
3980 /* Fill in the entries. */
3981 start_int_bitpos
= -1;
3982 for (i
= 1, field
= TYPE_FIELDS (type
);
3984 field
= TREE_CHAIN (field
))
3986 bitpos
= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
));
3987 this_slotno
= slotno
+ bitpos
/ BITS_PER_WORD
;
3988 if (TREE_CODE (field
) == FIELD_DECL
)
3990 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3995 reg
= gen_rtx (REG
, DECL_MODE (field
),
3996 (SPARC_FP_ARG_FIRST
+ this_slotno
* 2
3997 + (DECL_MODE (field
) == SFmode
3998 && (bitpos
& 32) != 0)));
3999 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
4000 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4002 start_int_bitpos
= -1;
4006 if (this_slotno
< SPARC_INT_ARG_MAX
4007 && (start_int_bitpos
== -1
4008 || bitpos
% BITS_PER_WORD
== 0))
4010 enum machine_mode mode
;
4012 /* If this is the trailing part of a word, only load
4013 that much into the register. Otherwise load the
4014 whole register. Note that in the latter case we may
4015 pick up unwanted bits. It's not a problem at the
4016 moment but may wish to revisit. */
4017 if (bitpos
% BITS_PER_WORD
!= 0)
4018 mode
= mode_for_size (BITS_PER_WORD
- bitpos
% BITS_PER_WORD
,
4023 regno
= regbase
+ this_slotno
;
4024 reg
= gen_rtx (REG
, mode
, regno
);
4025 XVECEXP (ret
, 0, i
) = gen_rtx (EXPR_LIST
, VOIDmode
, reg
,
4026 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4028 if (start_int_bitpos
== -1)
4029 start_int_bitpos
= bitpos
;
4039 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
4041 enum machine_mode mode
;
4042 int bytes
= int_size_in_bytes (type
);
4047 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
4048 reg
= gen_rtx (REG
, mode
, regno
);
4052 /* Scalar or complex int. */
4053 reg
= gen_rtx (REG
, mode
, regno
);
4059 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4060 For an arg passed partly in registers and partly in memory,
4061 this is the number of registers used.
4062 For args passed entirely in registers or entirely in memory, zero.
4064 Any arg that starts in the first 6 regs but won't entirely fit in them
4065 needs partial registers on v8. On v9, structures with integer
4066 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4067 values that begin in the last fp reg [where "last fp reg" varies with the
4068 mode] will be split between that reg and memory. */
4071 function_arg_partial_nregs (cum
, mode
, type
, named
)
4072 const CUMULATIVE_ARGS
*cum
;
4073 enum machine_mode mode
;
4077 int slotno
, regno
, padding
;
4079 /* We pass 0 for incoming_p here, it doesn't matter. */
4080 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
4087 if ((slotno
+ (mode
== BLKmode
4088 ? ROUND_ADVANCE (int_size_in_bytes (type
))
4089 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
4090 > NPARM_REGS (SImode
))
4091 return NPARM_REGS (SImode
) - slotno
;
4096 if (type
&& AGGREGATE_TYPE_P (type
))
4098 int size
= int_size_in_bytes (type
);
4099 int align
= TYPE_ALIGN (type
);
4102 slotno
+= slotno
& 1;
4103 if (size
> 8 && size
<= 16
4104 && slotno
== SPARC_INT_ARG_MAX
- 1)
4107 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
4108 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4111 if (GET_MODE_ALIGNMENT (mode
) == 128)
4113 slotno
+= slotno
& 1;
4114 if (slotno
== SPARC_INT_ARG_MAX
- 2)
4119 if (slotno
== SPARC_INT_ARG_MAX
- 1)
4123 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4125 if (GET_MODE_ALIGNMENT (mode
) == 128)
4126 slotno
+= slotno
& 1;
4127 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
4135 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4136 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4137 quad-precision floats by invisible reference.
4138 v9: aggregates greater than 16 bytes are passed by reference.
4139 For Pascal, also pass arrays by reference. */
4142 function_arg_pass_by_reference (cum
, mode
, type
, named
)
4143 const CUMULATIVE_ARGS
*cum
;
4144 enum machine_mode mode
;
4150 return (type
&& AGGREGATE_TYPE_P (type
)
4151 || mode
== TFmode
|| mode
== TCmode
);
4155 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
4156 || (type
&& AGGREGATE_TYPE_P (type
)
4157 && int_size_in_bytes (type
) > 16));
4161 /* Handle the FUNCTION_ARG_ADVANCE macro.
4162 Update the data in CUM to advance over an argument
4163 of mode MODE and data type TYPE.
4164 TYPE is null for libcalls where that information may not be available. */
4167 function_arg_advance (cum
, mode
, type
, named
)
4168 CUMULATIVE_ARGS
*cum
;
4169 enum machine_mode mode
;
4173 int slotno
, regno
, padding
;
4175 /* We pass 0 for incoming_p here, it doesn't matter. */
4176 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
4178 /* If register required leading padding, add it. */
4180 cum
->words
+= padding
;
4184 cum
->words
+= (mode
!= BLKmode
4185 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
4186 : ROUND_ADVANCE (int_size_in_bytes (type
)));
4190 if (type
&& AGGREGATE_TYPE_P (type
))
4192 int size
= int_size_in_bytes (type
);
4196 else if (size
<= 16)
4198 else /* passed by reference */
4201 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
4205 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4207 cum
->words
+= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4211 cum
->words
+= (mode
!= BLKmode
4212 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
4213 : ROUND_ADVANCE (int_size_in_bytes (type
)));
4218 /* Handle the FUNCTION_ARG_PADDING macro.
4219 For the 64 bit ABI structs are always stored left shifted in their
4223 function_arg_padding (mode
, type
)
4224 enum machine_mode mode
;
4227 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
4230 /* This is the default definition. */
4231 return (! BYTES_BIG_ENDIAN
4234 ? (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
4235 && int_size_in_bytes (type
) < (PARM_BOUNDARY
/ BITS_PER_UNIT
))
4236 : GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
4237 ? downward
: upward
));
4240 /* Do what is necessary for `va_start'. The argument is ignored.
4242 We look at the current function to determine if stdarg or varargs
4243 is used and return the address of the first unnamed parameter. */
4246 sparc_builtin_saveregs (arglist
)
4249 tree fntype
= TREE_TYPE (current_function_decl
);
4250 int stdarg
= (TYPE_ARG_TYPES (fntype
) != 0
4251 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4252 != void_type_node
));
4253 int first_reg
= current_function_args_info
.words
;
4257 for (regno
= first_reg
; regno
< NPARM_REGS (word_mode
); regno
++)
4258 emit_move_insn (gen_rtx (MEM
, word_mode
,
4259 gen_rtx (PLUS
, Pmode
,
4261 GEN_INT (STACK_POINTER_OFFSET
4262 + UNITS_PER_WORD
* regno
))),
4263 gen_rtx (REG
, word_mode
,
4264 BASE_INCOMING_ARG_REG (word_mode
) + regno
));
4266 address
= gen_rtx (PLUS
, Pmode
,
4268 GEN_INT (STACK_POINTER_OFFSET
4269 + UNITS_PER_WORD
* first_reg
));
4271 if (flag_check_memory_usage
4272 && first_reg
< NPARM_REGS (word_mode
))
4273 emit_library_call (chkr_set_right_libfunc
, 1, VOIDmode
, 3,
4275 GEN_INT (UNITS_PER_WORD
4276 * (NPARM_REGS (word_mode
) - first_reg
)),
4277 TYPE_MODE (sizetype
), GEN_INT (MEMORY_USE_RW
),
4278 TYPE_MODE (integer_type_node
));
4283 /* Return the string to output a conditional branch to LABEL, which is
4284 the operand number of the label. OP is the conditional expression.
4285 XEXP (OP, 0) is assumed to be a condition code register (integer or
4286 floating point) and its mode specifies what kind of comparison we made.
4288 REVERSED is non-zero if we should reverse the sense of the comparison.
4290 ANNUL is non-zero if we should generate an annulling branch.
4292 NOOP is non-zero if we have to follow this branch by a noop. */
4295 output_cbranch (op
, label
, reversed
, annul
, noop
)
4298 int reversed
, annul
, noop
;
4300 static char string
[20];
4301 enum rtx_code code
= GET_CODE (op
);
4302 rtx cc_reg
= XEXP (op
, 0);
4303 enum machine_mode mode
= GET_MODE (cc_reg
);
4304 static char v8_labelno
[] = " %lX";
4305 static char v9_icc_labelno
[] = " %%icc,%lX";
4306 static char v9_xcc_labelno
[] = " %%xcc,%lX";
4307 static char v9_fcc_labelno
[] = " %%fccX,%lY";
4311 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4312 Because there is currently no concept of pre-delay slots, we can fix
4313 this only by always emitting a nop before a floating point branch. */
4315 if ((mode
== CCFPmode
|| mode
== CCFPEmode
) && ! TARGET_V9
)
4316 strcpy (string
, "nop\n\t");
4320 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4322 && ((mode
!= CCFPmode
&& mode
!= CCFPEmode
) || code
== EQ
|| code
== NE
))
4323 code
= reverse_condition (code
), reversed
= 0;
4325 /* Start by writing the branch condition. */
4329 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4330 strcat (string
, "fbne");
4332 strcpy (string
, "bne");
4336 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4337 strcat (string
, "fbe");
4339 strcpy (string
, "be");
4343 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4346 strcat (string
, "fbul");
4348 strcat (string
, "fbge");
4350 else if (mode
== CC_NOOVmode
)
4351 strcpy (string
, "bpos");
4353 strcpy (string
, "bge");
4357 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4360 strcat (string
, "fbule");
4362 strcat (string
, "fbg");
4365 strcpy (string
, "bg");
4369 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4372 strcat (string
, "fbug");
4374 strcat (string
, "fble");
4377 strcpy (string
, "ble");
4381 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4384 strcat (string
, "fbuge");
4386 strcat (string
, "fbl");
4388 else if (mode
== CC_NOOVmode
)
4389 strcpy (string
, "bneg");
4391 strcpy (string
, "bl");
4395 strcpy (string
, "bgeu");
4399 strcpy (string
, "bgu");
4403 strcpy (string
, "bleu");
4407 strcpy (string
, "blu");
4411 /* Now add the annulling, the label, and a possible noop. */
4413 strcat (string
, ",a");
4415 /* ??? If v9, optional prediction bit ",pt" or ",pf" goes here. */
4420 labelno
= v8_labelno
;
4425 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4428 labelno
= v9_fcc_labelno
;
4429 /* Set the char indicating the number of the fcc reg to use. */
4430 labelno
[6] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
4432 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
4433 labelno
= v9_xcc_labelno
;
4435 labelno
= v9_icc_labelno
;
4437 /* Set the char indicating the number of the operand containing the
4439 labelno
[labeloff
] = label
+ '0';
4440 strcat (string
, labelno
);
4443 strcat (string
, "\n\tnop");
4448 /* Return the string to output a conditional branch to LABEL, testing
4449 register REG. LABEL is the operand number of the label; REG is the
4450 operand number of the reg. OP is the conditional expression. The mode
4451 of REG says what kind of comparison we made.
4453 REVERSED is non-zero if we should reverse the sense of the comparison.
4455 ANNUL is non-zero if we should generate an annulling branch.
4457 NOOP is non-zero if we have to follow this branch by a noop. */
4460 output_v9branch (op
, reg
, label
, reversed
, annul
, noop
)
4463 int reversed
, annul
, noop
;
4465 static char string
[20];
4466 enum rtx_code code
= GET_CODE (op
);
4467 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
4468 static char labelno
[] = " %X,%lX";
4470 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4472 code
= reverse_condition (code
), reversed
= 0;
4474 /* Only 64 bit versions of these instructions exist. */
4478 /* Start by writing the branch condition. */
4483 strcpy (string
, "brnz");
4487 strcpy (string
, "brz");
4491 strcpy (string
, "brgez");
4495 strcpy (string
, "brlz");
4499 strcpy (string
, "brlez");
4503 strcpy (string
, "brgz");
4510 /* Now add the annulling, reg, label, and nop. */
4512 strcat (string
, ",a");
4514 /* ??? Optional prediction bit ",pt" or ",pf" goes here. */
4516 labelno
[2] = reg
+ '0';
4517 labelno
[6] = label
+ '0';
4518 strcat (string
, labelno
);
4521 strcat (string
, "\n\tnop");
4526 /* Output assembler code to return from a function. */
4528 /* ??? v9: Update to use the new `return' instruction. Also, add patterns to
4529 md file for the `return' instruction. */
4532 output_return (operands
)
4537 operands
[0] = leaf_label
;
4540 else if (leaf_function
)
4542 /* If we didn't allocate a frame pointer for the current function,
4543 the stack pointer might have been adjusted. Output code to
4546 operands
[0] = gen_rtx (CONST_INT
, VOIDmode
, actual_fsize
);
4548 /* Use sub of negated value in first two cases instead of add to
4549 allow actual_fsize == 4096. */
4551 if (actual_fsize
<= 4096)
4553 if (SKIP_CALLERS_UNIMP_P
)
4554 return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp";
4556 return "retl\n\tsub %%sp,-%0,%%sp";
4558 else if (actual_fsize
<= 8192)
4560 operands
[0] = gen_rtx (CONST_INT
, VOIDmode
, actual_fsize
- 4096);
4561 if (SKIP_CALLERS_UNIMP_P
)
4562 return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp";
4564 return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp";
4566 else if (SKIP_CALLERS_UNIMP_P
)
4568 if ((actual_fsize
& 0x3ff) != 0)
4569 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
4571 return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
4575 if ((actual_fsize
& 0x3ff) != 0)
4576 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4578 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4583 if (SKIP_CALLERS_UNIMP_P
)
4584 return "jmp %%i7+12\n\trestore";
4586 return "ret\n\trestore";
4590 /* Leaf functions and non-leaf functions have different needs. */
4593 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
4596 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
4598 static int *reg_alloc_orders
[] = {
4599 reg_leaf_alloc_order
,
4600 reg_nonleaf_alloc_order
};
4603 order_regs_for_local_alloc ()
4605 static int last_order_nonleaf
= 1;
4607 if (regs_ever_live
[15] != last_order_nonleaf
)
4609 last_order_nonleaf
= !last_order_nonleaf
;
4610 bcopy ((char *) reg_alloc_orders
[last_order_nonleaf
],
4611 (char *) reg_alloc_order
, FIRST_PSEUDO_REGISTER
* sizeof (int));
4615 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4616 This makes them candidates for using ldd and std insns.
4618 Note reg1 and reg2 *must* be hard registers. To be sure we will
4619 abort if we are passed pseudo registers. */
4622 registers_ok_for_ldd_peep (reg1
, reg2
)
4625 /* We might have been passed a SUBREG. */
4626 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
4629 if (REGNO (reg1
) % 2 != 0)
4632 return (REGNO (reg1
) == REGNO (reg2
) - 1);
4635 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4638 This can only happen when addr1 and addr2 are consecutive memory
4639 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4640 64 bit boundary (addr1 % 8 == 0).
4642 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4643 registers are assumed to *never* be properly aligned and are
4646 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4647 need only check that the offset for addr1 % 8 == 0. */
4650 addrs_ok_for_ldd_peep (addr1
, addr2
)
4655 /* Extract a register number and offset (if used) from the first addr. */
4656 if (GET_CODE (addr1
) == PLUS
)
4658 /* If not a REG, return zero. */
4659 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
4663 reg1
= REGNO (XEXP (addr1
, 0));
4664 /* The offset must be constant! */
4665 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
4667 offset1
= INTVAL (XEXP (addr1
, 1));
4670 else if (GET_CODE (addr1
) != REG
)
4674 reg1
= REGNO (addr1
);
4675 /* This was a simple (mem (reg)) expression. Offset is 0. */
4679 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4680 if (GET_CODE (addr2
) != PLUS
)
4683 if (GET_CODE (XEXP (addr2
, 0)) != REG
4684 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
4687 /* Only %fp and %sp are allowed. Additionally both addresses must
4688 use the same register. */
4689 if (reg1
!= FRAME_POINTER_REGNUM
&& reg1
!= STACK_POINTER_REGNUM
)
4692 if (reg1
!= REGNO (XEXP (addr2
, 0)))
4695 /* The first offset must be evenly divisible by 8 to ensure the
4696 address is 64 bit aligned. */
4697 if (offset1
% 8 != 0)
4700 /* The offset for the second addr must be 4 more than the first addr. */
4701 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
4704 /* All the tests passed. addr1 and addr2 are valid for ldd and std
4709 /* Return 1 if reg is a pseudo, or is the first register in
4710 a hard register pair. This makes it a candidate for use in
4711 ldd and std insns. */
4714 register_ok_for_ldd (reg
)
4717 /* We might have been passed a SUBREG. */
4718 if (GET_CODE (reg
) != REG
)
4721 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
4722 return (REGNO (reg
) % 2 == 0);
4727 /* Print operand X (an rtx) in assembler syntax to file FILE.
4728 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4729 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4732 print_operand (file
, x
, code
)
4740 /* Output a 'nop' if there's nothing for the delay slot. */
4741 if (dbr_sequence_length () == 0)
4742 fputs ("\n\tnop", file
);
4745 /* Output an annul flag if there's nothing for the delay slot and we
4746 are optimizing. This is always used with '(' below. */
4747 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
4748 this is a dbx bug. So, we only do this when optimizing. */
4749 if (dbr_sequence_length () == 0 && optimize
)
4753 /* Output a 'nop' if there's nothing for the delay slot and we are
4754 not optimizing. This is always used with '*' above. */
4755 if (dbr_sequence_length () == 0 && ! optimize
)
4756 fputs ("\n\tnop", file
);
4759 /* Output the Embedded Medium/Anywhere code model base register. */
4760 fputs (EMBMEDANY_BASE_REG
, file
);
4763 /* Print out what we are using as the frame pointer. This might
4764 be %fp, or might be %sp+offset. */
4765 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
4766 fprintf (file
, "%s+%d", frame_base_name
, frame_base_offset
);
4769 /* Adjust the operand to take into account a RESTORE operation. */
4770 if (GET_CODE (x
) != REG
)
4771 output_operand_lossage ("Invalid %%Y operand");
4772 else if (REGNO (x
) < 8)
4773 fputs (reg_names
[REGNO (x
)], file
);
4774 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
4775 fputs (reg_names
[REGNO (x
)-16], file
);
4777 output_operand_lossage ("Invalid %%Y operand");
4780 /* Print out the low order register name of a register pair. */
4781 if (WORDS_BIG_ENDIAN
)
4782 fputs (reg_names
[REGNO (x
)+1], file
);
4784 fputs (reg_names
[REGNO (x
)], file
);
4787 /* Print out the high order register name of a register pair. */
4788 if (WORDS_BIG_ENDIAN
)
4789 fputs (reg_names
[REGNO (x
)], file
);
4791 fputs (reg_names
[REGNO (x
)+1], file
);
4794 /* Print out the second register name of a register pair or quad.
4795 I.e., R (%o0) => %o1. */
4796 fputs (reg_names
[REGNO (x
)+1], file
);
4799 /* Print out the third register name of a register quad.
4800 I.e., S (%o0) => %o2. */
4801 fputs (reg_names
[REGNO (x
)+2], file
);
4804 /* Print out the fourth register name of a register quad.
4805 I.e., T (%o0) => %o3. */
4806 fputs (reg_names
[REGNO (x
)+3], file
);
4809 /* Print a condition code register. */
4810 if (REGNO (x
) == SPARC_ICC_REG
)
4812 /* We don't handle CC[X]_NOOVmode because they're not supposed
4814 if (GET_MODE (x
) == CCmode
)
4815 fputs ("%icc", file
);
4816 else if (GET_MODE (x
) == CCXmode
)
4817 fputs ("%xcc", file
);
4822 /* %fccN register */
4823 fputs (reg_names
[REGNO (x
)], file
);
4826 /* Print the operand's address only. */
4827 output_address (XEXP (x
, 0));
4830 /* In this case we need a register. Use %g0 if the
4831 operand is const0_rtx. */
4833 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
4835 fputs ("%g0", file
);
4842 switch (GET_CODE (x
))
4844 case IOR
: fputs ("or", file
); break;
4845 case AND
: fputs ("and", file
); break;
4846 case XOR
: fputs ("xor", file
); break;
4847 default: output_operand_lossage ("Invalid %%A operand");
4852 switch (GET_CODE (x
))
4854 case IOR
: fputs ("orn", file
); break;
4855 case AND
: fputs ("andn", file
); break;
4856 case XOR
: fputs ("xnor", file
); break;
4857 default: output_operand_lossage ("Invalid %%B operand");
4861 /* These are used by the conditional move instructions. */
4865 enum rtx_code rc
= (code
== 'c'
4866 ? reverse_condition (GET_CODE (x
))
4870 case NE
: fputs ("ne", file
); break;
4871 case EQ
: fputs ("e", file
); break;
4872 case GE
: fputs ("ge", file
); break;
4873 case GT
: fputs ("g", file
); break;
4874 case LE
: fputs ("le", file
); break;
4875 case LT
: fputs ("l", file
); break;
4876 case GEU
: fputs ("geu", file
); break;
4877 case GTU
: fputs ("gu", file
); break;
4878 case LEU
: fputs ("leu", file
); break;
4879 case LTU
: fputs ("lu", file
); break;
4880 default: output_operand_lossage (code
== 'c'
4881 ? "Invalid %%c operand"
4882 : "Invalid %%C operand");
4887 /* These are used by the movr instruction pattern. */
4891 enum rtx_code rc
= (code
== 'd'
4892 ? reverse_condition (GET_CODE (x
))
4896 case NE
: fputs ("ne", file
); break;
4897 case EQ
: fputs ("e", file
); break;
4898 case GE
: fputs ("gez", file
); break;
4899 case LT
: fputs ("lz", file
); break;
4900 case LE
: fputs ("lez", file
); break;
4901 case GT
: fputs ("gz", file
); break;
4902 default: output_operand_lossage (code
== 'd'
4903 ? "Invalid %%d operand"
4904 : "Invalid %%D operand");
4911 /* Print a sign-extended character. */
4912 int i
= INTVAL (x
) & 0xff;
4915 fprintf (file
, "%d", i
);
4920 /* Operand must be a MEM; write its address. */
4921 if (GET_CODE (x
) != MEM
)
4922 output_operand_lossage ("Invalid %%f operand");
4923 output_address (XEXP (x
, 0));
4927 /* Do nothing special. */
4931 /* Undocumented flag. */
4932 output_operand_lossage ("invalid operand output code");
4935 if (GET_CODE (x
) == REG
)
4936 fputs (reg_names
[REGNO (x
)], file
);
4937 else if (GET_CODE (x
) == MEM
)
4940 /* Poor Sun assembler doesn't understand absolute addressing. */
4941 if (CONSTANT_P (XEXP (x
, 0))
4942 && ! TARGET_LIVE_G0
)
4943 fputs ("%g0+", file
);
4944 output_address (XEXP (x
, 0));
4947 else if (GET_CODE (x
) == HIGH
)
4949 fputs ("%hi(", file
);
4950 output_addr_const (file
, XEXP (x
, 0));
4953 else if (GET_CODE (x
) == LO_SUM
)
4955 print_operand (file
, XEXP (x
, 0), 0);
4956 fputs ("+%lo(", file
);
4957 output_addr_const (file
, XEXP (x
, 1));
4960 else if (GET_CODE (x
) == CONST_DOUBLE
4961 && (GET_MODE (x
) == VOIDmode
4962 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
4964 if (CONST_DOUBLE_HIGH (x
) == 0)
4965 fprintf (file
, "%u", CONST_DOUBLE_LOW (x
));
4966 else if (CONST_DOUBLE_HIGH (x
) == -1
4967 && CONST_DOUBLE_LOW (x
) < 0)
4968 fprintf (file
, "%d", CONST_DOUBLE_LOW (x
));
4970 output_operand_lossage ("long long constant not a valid immediate operand");
4972 else if (GET_CODE (x
) == CONST_DOUBLE
)
4973 output_operand_lossage ("floating point constant not a valid immediate operand");
4974 else { output_addr_const (file
, x
); }
4977 /* This function outputs assembler code for VALUE to FILE, where VALUE is
4978 a 64 bit (DImode) value. */
4980 /* ??? If there is a 64 bit counterpart to .word that the assembler
4981 understands, then using that would simply this code greatly. */
4982 /* ??? We only output .xword's for symbols and only then in environments
4983 where the assembler can handle them. */
4986 output_double_int (file
, value
)
4990 if (GET_CODE (value
) == CONST_INT
)
4992 /* ??? This has endianness issues. */
4993 #if HOST_BITS_PER_WIDE_INT == 64
4994 HOST_WIDE_INT xword
= INTVAL (value
);
4995 HOST_WIDE_INT high
, low
;
4997 high
= (xword
>> 32) & 0xffffffff;
4998 low
= xword
& 0xffffffff;
4999 ASM_OUTPUT_INT (file
, gen_rtx (CONST_INT
, VOIDmode
, high
));
5000 ASM_OUTPUT_INT (file
, gen_rtx (CONST_INT
, VOIDmode
, low
));
5002 if (INTVAL (value
) < 0)
5003 ASM_OUTPUT_INT (file
, constm1_rtx
);
5005 ASM_OUTPUT_INT (file
, const0_rtx
);
5006 ASM_OUTPUT_INT (file
, value
);
5009 else if (GET_CODE (value
) == CONST_DOUBLE
)
5011 ASM_OUTPUT_INT (file
, gen_rtx (CONST_INT
, VOIDmode
,
5012 CONST_DOUBLE_HIGH (value
)));
5013 ASM_OUTPUT_INT (file
, gen_rtx (CONST_INT
, VOIDmode
,
5014 CONST_DOUBLE_LOW (value
)));
5016 else if (GET_CODE (value
) == SYMBOL_REF
5017 || GET_CODE (value
) == CONST
5018 || GET_CODE (value
) == PLUS
5019 || (TARGET_ARCH64
&&
5020 (GET_CODE (value
) == LABEL_REF
5021 || GET_CODE (value
) == CODE_LABEL
5022 || GET_CODE (value
) == MINUS
)))
5024 if (!TARGET_V9
|| TARGET_CM_MEDLOW
)
5026 ASM_OUTPUT_INT (file
, const0_rtx
);
5027 ASM_OUTPUT_INT (file
, value
);
5031 fprintf (file
, "\t%s\t", ASM_LONGLONG
);
5032 output_addr_const (file
, value
);
5033 fprintf (file
, "\n");
5040 /* Return the value of a code used in the .proc pseudo-op that says
5041 what kind of result this function returns. For non-C types, we pick
5042 the closest C type. */
5044 #ifndef CHAR_TYPE_SIZE
5045 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5048 #ifndef SHORT_TYPE_SIZE
5049 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5052 #ifndef INT_TYPE_SIZE
5053 #define INT_TYPE_SIZE BITS_PER_WORD
5056 #ifndef LONG_TYPE_SIZE
5057 #define LONG_TYPE_SIZE BITS_PER_WORD
5060 #ifndef LONG_LONG_TYPE_SIZE
5061 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5064 #ifndef FLOAT_TYPE_SIZE
5065 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5068 #ifndef DOUBLE_TYPE_SIZE
5069 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5072 #ifndef LONG_DOUBLE_TYPE_SIZE
5073 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5077 sparc_type_code (type
)
5080 register unsigned long qualifiers
= 0;
5081 register unsigned shift
= 6;
5083 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5084 setting more, since some assemblers will give an error for this. Also,
5085 we must be careful to avoid shifts of 32 bits or more to avoid getting
5086 unpredictable results. */
5090 switch (TREE_CODE (type
))
5097 qualifiers
|= (3 << shift
);
5099 type
= TREE_TYPE (type
);
5105 qualifiers
|= (2 << shift
);
5107 type
= TREE_TYPE (type
);
5111 case REFERENCE_TYPE
:
5114 qualifiers
|= (1 << shift
);
5116 type
= TREE_TYPE (type
);
5120 return (qualifiers
| 8);
5123 case QUAL_UNION_TYPE
:
5124 return (qualifiers
| 9);
5127 return (qualifiers
| 10);
5130 return (qualifiers
| 16);
5133 /* If this is a range type, consider it to be the underlying
5135 if (TREE_TYPE (type
) != 0)
5137 type
= TREE_TYPE (type
);
5141 /* Carefully distinguish all the standard types of C,
5142 without messing up if the language is not C. We do this by
5143 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5144 look at both the names and the above fields, but that's redundant.
5145 Any type whose size is between two C types will be considered
5146 to be the wider of the two types. Also, we do not have a
5147 special code to use for "long long", so anything wider than
5148 long is treated the same. Note that we can't distinguish
5149 between "int" and "long" in this code if they are the same
5150 size, but that's fine, since neither can the assembler. */
5152 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
5153 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
5155 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
5156 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
5158 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
5159 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
5162 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
5165 /* Carefully distinguish all the standard types of C,
5166 without messing up if the language is not C. */
5168 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
5169 return (qualifiers
| 6);
5172 return (qualifiers
| 7);
5174 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
5175 /* ??? We need to distinguish between double and float complex types,
5176 but I don't know how yet because I can't reach this code from
5177 existing front-ends. */
5178 return (qualifiers
| 7); /* Who knows? */
5180 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
5181 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
5182 case FILE_TYPE
: /* GNU Pascal FILE type. */
5183 case SET_TYPE
: /* GNU Pascal SET type. */
5184 case LANG_TYPE
: /* ? */
5188 abort (); /* Not a type! */
5193 /* Nested function support. */
5195 /* Emit RTL insns to initialize the variable parts of a trampoline.
5196 FNADDR is an RTX for the address of the function's pure code.
5197 CXT is an RTX for the static chain value for the function.
5199 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5200 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5201 (to store insns). This is a bit excessive. Perhaps a different
5202 mechanism would be better here.
5204 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5207 sparc_initialize_trampoline (tramp
, fnaddr
, cxt
)
5208 rtx tramp
, fnaddr
, cxt
;
5210 rtx high_cxt
= expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
5211 size_int (10), 0, 1);
5212 rtx high_fn
= expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
5213 size_int (10), 0, 1);
5214 rtx low_cxt
= expand_and (cxt
, gen_rtx (CONST_INT
, VOIDmode
, 0x3ff), 0);
5215 rtx low_fn
= expand_and (fnaddr
, gen_rtx (CONST_INT
, VOIDmode
, 0x3ff), 0);
5216 rtx g1_sethi
= gen_rtx (HIGH
, SImode
,
5217 gen_rtx (CONST_INT
, VOIDmode
, 0x03000000));
5218 rtx g2_sethi
= gen_rtx (HIGH
, SImode
,
5219 gen_rtx (CONST_INT
, VOIDmode
, 0x05000000));
5220 rtx g1_ori
= gen_rtx (HIGH
, SImode
,
5221 gen_rtx (CONST_INT
, VOIDmode
, 0x82106000));
5222 rtx g2_ori
= gen_rtx (HIGH
, SImode
,
5223 gen_rtx (CONST_INT
, VOIDmode
, 0x8410A000));
5224 rtx tem
= gen_reg_rtx (SImode
);
5225 emit_move_insn (tem
, g1_sethi
);
5226 emit_insn (gen_iorsi3 (high_fn
, high_fn
, tem
));
5227 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 0)), high_fn
);
5228 emit_move_insn (tem
, g1_ori
);
5229 emit_insn (gen_iorsi3 (low_fn
, low_fn
, tem
));
5230 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 4)), low_fn
);
5231 emit_move_insn (tem
, g2_sethi
);
5232 emit_insn (gen_iorsi3 (high_cxt
, high_cxt
, tem
));
5233 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 8)), high_cxt
);
5234 emit_move_insn (tem
, g2_ori
);
5235 emit_insn (gen_iorsi3 (low_cxt
, low_cxt
, tem
));
5236 emit_move_insn (gen_rtx (MEM
, SImode
, plus_constant (tramp
, 16)), low_cxt
);
5237 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, SImode
, tramp
))));
5238 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, SImode
,
5239 plus_constant (tramp
, 8)))));
5240 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, SImode
,
5241 plus_constant (tramp
, 16)))));
5244 /* The 64 bit version is simpler because it makes more sense to load the
5245 values as "immediate" data out of the trampoline. It's also easier since
5246 we can read the PC without clobbering a register. */
5249 sparc64_initialize_trampoline (tramp
, fnaddr
, cxt
)
5250 rtx tramp
, fnaddr
, cxt
;
5252 emit_move_insn (gen_rtx (MEM
, DImode
, plus_constant (tramp
, 24)), cxt
);
5253 emit_move_insn (gen_rtx (MEM
, DImode
, plus_constant (tramp
, 32)), fnaddr
);
5254 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, DImode
, tramp
))));
5255 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, DImode
,
5256 plus_constant (tramp
, 8)))));
5257 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, DImode
,
5258 plus_constant (tramp
, 16)))));
5259 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, DImode
,
5260 plus_constant (tramp
, 24)))));
5261 emit_insn (gen_flush (validize_mem (gen_rtx (MEM
, DImode
,
5262 plus_constant (tramp
, 32)))));
5265 /* Subroutines to support a flat (single) register window calling
5268 /* Single-register window sparc stack frames look like:
5270 Before call After call
5271 +-----------------------+ +-----------------------+
5273 mem | caller's temps. | | caller's temps. |
5275 +-----------------------+ +-----------------------+
5277 | arguments on stack. | | arguments on stack. |
5279 +-----------------------+FP+92->+-----------------------+
5280 | 6 words to save | | 6 words to save |
5281 | arguments passed | | arguments passed |
5282 | in registers, even | | in registers, even |
5283 | if not passed. | | if not passed. |
5284 SP+68->+-----------------------+FP+68->+-----------------------+
5285 | 1 word struct addr | | 1 word struct addr |
5286 +-----------------------+FP+64->+-----------------------+
5288 | 16 word reg save area | | 16 word reg save area |
5290 SP->+-----------------------+ FP->+-----------------------+
5292 | fp/alu reg moves |
5293 FP-16->+-----------------------+
5297 +-----------------------+
5299 | fp register save |
5301 +-----------------------+
5303 | gp register save |
5305 +-----------------------+
5307 | alloca allocations |
5309 +-----------------------+
5311 | arguments on stack |
5313 SP+92->+-----------------------+
5315 | arguments passed |
5316 | in registers, even |
5317 low | if not passed. |
5318 memory SP+68->+-----------------------+
5319 | 1 word struct addr |
5320 SP+64->+-----------------------+
5322 I 16 word reg save area |
5324 SP->+-----------------------+ */
5326 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5327 save masks, and offsets for the current function. */
5329 struct sparc_frame_info
5331 unsigned long total_size
; /* # bytes that the entire frame takes up. */
5332 unsigned long var_size
; /* # bytes that variables take up. */
5333 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
5334 unsigned long extra_size
; /* # bytes of extra gunk. */
5335 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
5336 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
5337 unsigned long gmask
; /* Mask of saved gp registers. */
5338 unsigned long fmask
; /* Mask of saved fp registers. */
5339 unsigned long reg_offset
; /* Offset from new sp to store regs. */
5340 int initialized
; /* Nonzero if frame size already calculated. */
5343 /* Current frame information calculated by sparc_flat_compute_frame_size. */
5344 struct sparc_frame_info current_frame_info
;
5346 /* Zero structure to initialize current_frame_info. */
5347 struct sparc_frame_info zero_frame_info
;
5349 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
5351 #define RETURN_ADDR_REGNUM 15
5352 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5353 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5355 #define MUST_SAVE_REGISTER(regno) \
5356 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5357 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
5358 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
5360 /* Return the bytes needed to compute the frame pointer from the current
5364 sparc_flat_compute_frame_size (size
)
5365 int size
; /* # of var. bytes allocated. */
5368 unsigned long total_size
; /* # bytes that the entire frame takes up. */
5369 unsigned long var_size
; /* # bytes that variables take up. */
5370 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
5371 unsigned long extra_size
; /* # extra bytes. */
5372 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
5373 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
5374 unsigned long gmask
; /* Mask of saved gp registers. */
5375 unsigned long fmask
; /* Mask of saved fp registers. */
5376 unsigned long reg_offset
; /* Offset to register save area. */
5377 int need_aligned_p
; /* 1 if need the save area 8 byte aligned. */
5379 /* This is the size of the 16 word reg save area, 1 word struct addr
5380 area, and 4 word fp/alu register copy area. */
5381 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
5383 /* Also include the size needed for the 6 parameter registers. */
5384 args_size
= current_function_outgoing_args_size
+ 24;
5385 total_size
= var_size
+ args_size
+ extra_size
;
5393 /* Calculate space needed for gp registers. */
5394 for (regno
= 1; regno
<= 31; regno
++)
5396 if (MUST_SAVE_REGISTER (regno
))
5398 /* If we need to save two regs in a row, ensure there's room to bump
5399 up the address to align it to a doubleword boundary. */
5400 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
5402 if (gp_reg_size
% 8 != 0)
5404 gp_reg_size
+= 2 * UNITS_PER_WORD
;
5405 gmask
|= 3 << regno
;
5411 gp_reg_size
+= UNITS_PER_WORD
;
5412 gmask
|= 1 << regno
;
5417 /* Calculate space needed for fp registers. */
5418 for (regno
= 32; regno
<= 63; regno
++)
5420 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
5422 fp_reg_size
+= UNITS_PER_WORD
;
5423 fmask
|= 1 << (regno
- 32);
5430 reg_offset
= FIRST_PARM_OFFSET(0) + args_size
;
5431 /* Ensure save area is 8 byte aligned if we need it. */
5433 if (need_aligned_p
&& n
!= 0)
5435 total_size
+= 8 - n
;
5436 reg_offset
+= 8 - n
;
5438 total_size
+= gp_reg_size
+ fp_reg_size
;
5441 /* ??? This looks a little suspicious. Clarify. */
5442 if (total_size
== extra_size
)
5443 total_size
= extra_size
= 0;
5445 total_size
= SPARC_STACK_ALIGN (total_size
);
5447 /* Save other computed information. */
5448 current_frame_info
.total_size
= total_size
;
5449 current_frame_info
.var_size
= var_size
;
5450 current_frame_info
.args_size
= args_size
;
5451 current_frame_info
.extra_size
= extra_size
;
5452 current_frame_info
.gp_reg_size
= gp_reg_size
;
5453 current_frame_info
.fp_reg_size
= fp_reg_size
;
5454 current_frame_info
.gmask
= gmask
;
5455 current_frame_info
.fmask
= fmask
;
5456 current_frame_info
.reg_offset
= reg_offset
;
5457 current_frame_info
.initialized
= reload_completed
;
5459 /* Ok, we're done. */
5463 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5466 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5467 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5468 [BASE_REG+OFFSET] will always be a valid address.
5470 WORD_OP is either "st" for save, "ld" for restore.
5471 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
5474 sparc_flat_save_restore (file
, base_reg
, offset
, gmask
, fmask
, word_op
,
5475 doubleword_op
, base_offset
)
5478 unsigned int offset
;
5479 unsigned long gmask
;
5480 unsigned long fmask
;
5482 char *doubleword_op
;
5483 unsigned long base_offset
;
5487 if (gmask
== 0 && fmask
== 0)
5490 /* Save registers starting from high to low. We've already saved the
5491 previous frame pointer and previous return address for the debugger's
5492 sake. The debugger allows us to not need a nop in the epilog if at least
5493 one register is reloaded in addition to return address. */
5497 for (regno
= 1; regno
<= 31; regno
++)
5499 if ((gmask
& (1L << regno
)) != 0)
5501 if ((regno
& 0x1) == 0 && ((gmask
& (1L << (regno
+1))) != 0))
5503 /* We can save two registers in a row. If we're not at a
5504 double word boundary, move to one.
5505 sparc_flat_compute_frame_size ensures there's room to do
5507 if (offset
% 8 != 0)
5508 offset
+= UNITS_PER_WORD
;
5510 if (word_op
[0] == 's')
5512 fprintf (file
, "\t%s %s,[%s+%d]\n",
5513 doubleword_op
, reg_names
[regno
],
5515 if (dwarf2out_do_frame ())
5517 char *l
= dwarf2out_cfi_label ();
5518 dwarf2out_reg_save (l
, regno
, offset
+ base_offset
);
5520 (l
, regno
+1, offset
+base_offset
+ UNITS_PER_WORD
);
5524 fprintf (file
, "\t%s [%s+%d],%s\n",
5525 doubleword_op
, base_reg
, offset
,
5528 offset
+= 2 * UNITS_PER_WORD
;
5533 if (word_op
[0] == 's')
5535 fprintf (file
, "\t%s %s,[%s+%d]\n",
5536 word_op
, reg_names
[regno
],
5538 if (dwarf2out_do_frame ())
5539 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
5542 fprintf (file
, "\t%s [%s+%d],%s\n",
5543 word_op
, base_reg
, offset
, reg_names
[regno
]);
5545 offset
+= UNITS_PER_WORD
;
5553 for (regno
= 32; regno
<= 63; regno
++)
5555 if ((fmask
& (1L << (regno
- 32))) != 0)
5557 if (word_op
[0] == 's')
5559 fprintf (file
, "\t%s %s,[%s+%d]\n",
5560 word_op
, reg_names
[regno
],
5562 if (dwarf2out_do_frame ())
5563 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
5566 fprintf (file
, "\t%s [%s+%d],%s\n",
5567 word_op
, base_reg
, offset
, reg_names
[regno
]);
5569 offset
+= UNITS_PER_WORD
;
5575 /* Set up the stack and frame (if desired) for the function. */
5578 sparc_flat_output_function_prologue (file
, size
)
5582 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5583 unsigned long gmask
= current_frame_info
.gmask
;
5585 /* This is only for the human reader. */
5586 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
5587 fprintf (file
, "\t%s# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5589 current_frame_info
.var_size
,
5590 current_frame_info
.gp_reg_size
/ 4,
5591 current_frame_info
.fp_reg_size
/ 4,
5592 current_function_outgoing_args_size
,
5593 current_frame_info
.extra_size
);
5595 size
= SPARC_STACK_ALIGN (size
);
5596 size
= (! current_frame_info
.initialized
5597 ? sparc_flat_compute_frame_size (size
)
5598 : current_frame_info
.total_size
);
5600 /* These cases shouldn't happen. Catch them now. */
5601 if (size
== 0 && (gmask
|| current_frame_info
.fmask
))
5604 /* Allocate our stack frame by decrementing %sp.
5605 At present, the only algorithm gdb can use to determine if this is a
5606 flat frame is if we always set %i7 if we set %sp. This can be optimized
5607 in the future by putting in some sort of debugging information that says
5608 this is a `flat' function. However, there is still the case of debugging
5609 code without such debugging information (including cases where most fns
5610 have such info, but there is one that doesn't). So, always do this now
5611 so we don't get a lot of code out there that gdb can't handle.
5612 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5613 distinguish us from a non-flat function but there won't (and shouldn't)
5614 be any differences anyway. The return pc is saved (if necessary) right
5615 after %i7 so gdb won't have to look too far to find it. */
5618 unsigned int reg_offset
= current_frame_info
.reg_offset
;
5619 char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
5620 char *t1_str
= "%g1";
5622 /* Things get a little tricky if local variables take up more than ~4096
5623 bytes and outgoing arguments take up more than ~4096 bytes. When that
5624 happens, the register save area can't be accessed from either end of
5625 the frame. Handle this by decrementing %sp to the start of the gp
5626 register save area, save the regs, update %i7, and then set %sp to its
5627 final value. Given that we only have one scratch register to play
5628 with it is the cheapest solution, and it helps gdb out as it won't
5629 slow down recognition of flat functions.
5630 Don't change the order of insns emitted here without checking with
5631 the gdb folk first. */
5633 /* Is the entire register save area offsettable from %sp? */
5634 if (reg_offset
< 4096 - 64 * UNITS_PER_WORD
)
5638 fprintf (file
, "\tadd %s,%d,%s\n",
5639 sp_str
, -size
, sp_str
);
5640 if (gmask
& FRAME_POINTER_MASK
)
5642 fprintf (file
, "\tst %s,[%s+%d]\n",
5643 fp_str
, sp_str
, reg_offset
);
5644 fprintf (file
, "\tsub %s,%d,%s\t%s# set up frame pointer\n",
5645 sp_str
, -size
, fp_str
, ASM_COMMENT_START
);
5651 fprintf (file
, "\tset %d,%s\n\tsub %s,%s,%s\n",
5652 size
, t1_str
, sp_str
, t1_str
, sp_str
);
5653 if (gmask
& FRAME_POINTER_MASK
)
5655 fprintf (file
, "\tst %s,[%s+%d]\n",
5656 fp_str
, sp_str
, reg_offset
);
5657 fprintf (file
, "\tadd %s,%s,%s\t%s# set up frame pointer\n",
5658 sp_str
, t1_str
, fp_str
, ASM_COMMENT_START
);
5662 if (dwarf2out_do_frame ())
5664 char *l
= dwarf2out_cfi_label ();
5665 if (gmask
& FRAME_POINTER_MASK
)
5667 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
,
5668 reg_offset
- 4 - size
);
5669 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, 0);
5672 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size
);
5674 if (gmask
& RETURN_ADDR_MASK
)
5676 fprintf (file
, "\tst %s,[%s+%d]\n",
5677 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, reg_offset
);
5678 if (dwarf2out_do_frame ())
5679 dwarf2out_return_save ("", reg_offset
- size
);
5682 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
5683 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
5684 current_frame_info
.fmask
,
5685 "st", "std", -size
);
5689 /* Subtract %sp in two steps, but make sure there is always a
5690 64 byte register save area, and %sp is properly aligned. */
5691 /* Amount to decrement %sp by, the first time. */
5692 unsigned int size1
= ((size
- reg_offset
+ 64) + 15) & -16;
5693 /* Offset to register save area from %sp. */
5694 unsigned int offset
= size1
- (size
- reg_offset
);
5698 fprintf (file
, "\tadd %s,%d,%s\n",
5699 sp_str
, -size1
, sp_str
);
5700 if (gmask
& FRAME_POINTER_MASK
)
5702 fprintf (file
, "\tst %s,[%s+%d]\n\tsub %s,%d,%s\t%s# set up frame pointer\n",
5703 fp_str
, sp_str
, offset
, sp_str
, -size1
, fp_str
,
5710 fprintf (file
, "\tset %d,%s\n\tsub %s,%s,%s\n",
5711 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
5712 if (gmask
& FRAME_POINTER_MASK
)
5714 fprintf (file
, "\tst %s,[%s+%d]\n\tadd %s,%s,%s\t%s# set up frame pointer\n",
5715 fp_str
, sp_str
, offset
, sp_str
, t1_str
, fp_str
,
5720 if (dwarf2out_do_frame ())
5722 char *l
= dwarf2out_cfi_label ();
5723 if (gmask
& FRAME_POINTER_MASK
)
5725 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
,
5726 offset
- 4 - size1
);
5727 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, 0);
5730 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size1
);
5732 if (gmask
& RETURN_ADDR_MASK
)
5734 fprintf (file
, "\tst %s,[%s+%d]\n",
5735 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, offset
);
5736 if (dwarf2out_do_frame ())
5737 /* offset - size1 == reg_offset - size
5738 if reg_offset were updated above like offset. */
5739 dwarf2out_return_save ("", offset
- size1
);
5742 sparc_flat_save_restore (file
, sp_str
, offset
,
5743 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
5744 current_frame_info
.fmask
,
5745 "st", "std", -size1
);
5746 fprintf (file
, "\tset %d,%s\n\tsub %s,%s,%s\n",
5747 size
- size1
, t1_str
, sp_str
, t1_str
, sp_str
);
5748 if (dwarf2out_do_frame ())
5749 if (! (gmask
& FRAME_POINTER_MASK
))
5750 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, size
);
5754 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
5757 /* Do any necessary cleanup after a function to restore stack, frame,
5761 sparc_flat_output_function_epilogue (file
, size
)
5765 rtx epilogue_delay
= current_function_epilogue_delay_list
;
5766 int noepilogue
= FALSE
;
5768 /* This is only for the human reader. */
5769 fprintf (file
, "\t%s#EPILOGUE#\n", ASM_COMMENT_START
);
5771 /* The epilogue does not depend on any registers, but the stack
5772 registers, so we assume that if we have 1 pending nop, it can be
5773 ignored, and 2 it must be filled (2 nops occur for integer
5774 multiply and divide). */
5776 size
= SPARC_STACK_ALIGN (size
);
5777 size
= (!current_frame_info
.initialized
5778 ? sparc_flat_compute_frame_size (size
)
5779 : current_frame_info
.total_size
);
5781 if (size
== 0 && epilogue_delay
== 0)
5783 rtx insn
= get_last_insn ();
5785 /* If the last insn was a BARRIER, we don't have to write any code
5786 because a jump (aka return) was put there. */
5787 if (GET_CODE (insn
) == NOTE
)
5788 insn
= prev_nonnote_insn (insn
);
5789 if (insn
&& GET_CODE (insn
) == BARRIER
)
5795 unsigned int reg_offset
= current_frame_info
.reg_offset
;
5797 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5798 char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
5799 char *t1_str
= "%g1";
5801 /* In the reload sequence, we don't need to fill the load delay
5802 slots for most of the loads, also see if we can fill the final
5803 delay slot if not otherwise filled by the reload sequence. */
5806 fprintf (file
, "\tset %d,%s\n", size
, t1_str
);
5808 if (frame_pointer_needed
)
5811 fprintf (file
,"\tsub %s,%s,%s\t\t%s# sp not trusted here\n",
5812 fp_str
, t1_str
, sp_str
, ASM_COMMENT_START
);
5814 fprintf (file
,"\tsub %s,%d,%s\t\t%s# sp not trusted here\n",
5815 fp_str
, size
, sp_str
, ASM_COMMENT_START
);
5818 /* Is the entire register save area offsettable from %sp? */
5819 if (reg_offset
< 4096 - 64 * UNITS_PER_WORD
)
5825 /* Restore %sp in two steps, but make sure there is always a
5826 64 byte register save area, and %sp is properly aligned. */
5827 /* Amount to increment %sp by, the first time. */
5828 size1
= ((reg_offset
- 64 - 16) + 15) & -16;
5829 /* Offset to register save area from %sp. */
5830 reg_offset
= size1
- reg_offset
;
5832 fprintf (file
, "\tset %d,%s\n\tadd %s,%s,%s\n",
5833 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
5836 /* We must restore the frame pointer and return address reg first
5837 because they are treated specially by the prologue output code. */
5838 if (current_frame_info
.gmask
& FRAME_POINTER_MASK
)
5840 fprintf (file
, "\tld [%s+%d],%s\n",
5841 sp_str
, reg_offset
, fp_str
);
5844 if (current_frame_info
.gmask
& RETURN_ADDR_MASK
)
5846 fprintf (file
, "\tld [%s+%d],%s\n",
5847 sp_str
, reg_offset
, reg_names
[RETURN_ADDR_REGNUM
]);
5851 /* Restore any remaining saved registers. */
5852 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
5853 current_frame_info
.gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
5854 current_frame_info
.fmask
,
5857 /* If we had to increment %sp in two steps, record it so the second
5858 restoration in the epilogue finishes up. */
5863 fprintf (file
, "\tset %d,%s\n",
5867 if (current_function_returns_struct
)
5868 fprintf (file
, "\tjmp %%o7+12\n");
5870 fprintf (file
, "\tretl\n");
5872 /* If the only register saved is the return address, we need a
5873 nop, unless we have an instruction to put into it. Otherwise
5874 we don't since reloading multiple registers doesn't reference
5875 the register being loaded. */
5881 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
5884 else if (size
> 4095)
5885 fprintf (file
, "\tadd %s,%s,%s\n", sp_str
, t1_str
, sp_str
);
5888 fprintf (file
, "\tadd %s,%d,%s\n", sp_str
, size
, sp_str
);
5891 fprintf (file
, "\tnop\n");
5894 /* Reset state info for each function. */
5895 current_frame_info
= zero_frame_info
;
5898 /* Define the number of delay slots needed for the function epilogue.
5900 On the sparc, we need a slot if either no stack has been allocated,
5901 or the only register saved is the return register. */
5904 sparc_flat_epilogue_delay_slots ()
5906 if (!current_frame_info
.initialized
)
5907 (void) sparc_flat_compute_frame_size (get_frame_size ());
5909 if (current_frame_info
.total_size
== 0)
5915 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
5916 Any single length instruction which doesn't reference the stack or frame
5920 sparc_flat_eligible_for_epilogue_delay (trial
, slot
)
5924 rtx pat
= PATTERN (trial
);
5926 if (get_attr_length (trial
) != 1)
5929 /* If %g0 is live, there are lots of things we can't handle.
5930 Rather than trying to find them all now, let's punt and only
5931 optimize things as necessary. */
5935 if (! reg_mentioned_p (stack_pointer_rtx
, pat
)
5936 && ! reg_mentioned_p (frame_pointer_rtx
, pat
))
5942 /* Adjust the cost of a scheduling dependency. Return the new cost of
5943 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5946 supersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
5952 enum attr_type insn_type
;
5954 if (! recog_memoized (insn
))
5957 insn_type
= get_attr_type (insn
);
5959 if (REG_NOTE_KIND (link
) == 0)
5961 /* Data dependency; DEP_INSN writes a register that INSN reads some
5964 /* if a load, then the dependence must be on the memory address;
5965 add an extra 'cycle'. Note that the cost could be two cycles
5966 if the reg was written late in an instruction group; we can't tell
5968 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
5971 /* Get the delay only if the address of the store is the dependence. */
5972 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
5974 rtx pat
= PATTERN(insn
);
5975 rtx dep_pat
= PATTERN (dep_insn
);
5977 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
5978 return cost
; /* This shouldn't happen! */
5980 /* The dependency between the two instructions was on the data that
5981 is being stored. Assume that this implies that the address of the
5982 store is not dependent. */
5983 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
5986 return cost
+ 3; /* An approximation. */
5989 /* A shift instruction cannot receive its data from an instruction
5990 in the same cycle; add a one cycle penalty. */
5991 if (insn_type
== TYPE_SHIFT
)
5992 return cost
+ 3; /* Split before cascade into shift. */
5996 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
5997 INSN writes some cycles later. */
5999 /* These are only significant for the fpu unit; writing a fp reg before
6000 the fpu has finished with it stalls the processor. */
6002 /* Reusing an integer register causes no problems. */
6003 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)