1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
37 /* Global variables for machine-dependent things. */
39 /* Save the operands last given to a compare for use when we
40 generate a scc or bcc insn. */
42 rtx sparc_compare_op0
, sparc_compare_op1
;
44 /* We may need an epilogue if we spill too many registers.
45 If this is non-zero, then we branch here for the epilogue. */
46 static rtx leaf_label
;
50 /* Vector to say how input registers are mapped to output
51 registers. FRAME_POINTER_REGNUM cannot be remapped by
52 this function to eliminate it. You must use -fomit-frame-pointer
54 char leaf_reg_remap
[] =
55 { 0, 1, 2, 3, 4, 5, 6, 7,
56 -1, -1, -1, -1, -1, -1, 14, -1,
57 -1, -1, -1, -1, -1, -1, -1, -1,
58 8, 9, 10, 11, 12, 13, -1, 15,
60 32, 33, 34, 35, 36, 37, 38, 39,
61 40, 41, 42, 43, 44, 45, 46, 47,
62 48, 49, 50, 51, 52, 53, 54, 55,
63 56, 57, 58, 59, 60, 61, 62, 63};
65 char leaf_reg_backmap
[] =
66 { 0, 1, 2, 3, 4, 5, 6, 7,
67 24, 25, 26, 27, 28, 29, 14, 31,
68 -1, -1, -1, -1, -1, -1, -1, -1,
69 -1, -1, -1, -1, -1, -1, -1, -1,
71 32, 33, 34, 35, 36, 37, 38, 39,
72 40, 41, 42, 43, 44, 45, 46, 47,
73 48, 49, 50, 51, 52, 53, 54, 55,
74 56, 57, 58, 59, 60, 61, 62, 63};
77 /* Global variables set by FUNCTION_PROLOGUE. */
78 /* Size of frame. Need to know this to emit return insns from
83 /* Name of where we pretend to think the frame pointer points.
84 Normally, this is "%fp", but if we are in a leaf procedure,
85 this is "%sp+something". */
86 char *frame_base_name
;
88 static rtx
find_addr_reg ();
90 /* Return non-zero only if OP is a register of mode MODE,
93 reg_or_0_operand (op
, mode
)
95 enum machine_mode mode
;
97 if (op
== const0_rtx
|| register_operand (op
, mode
))
99 if (GET_CODE (op
) == CONST_DOUBLE
100 && CONST_DOUBLE_HIGH (op
) == 0
101 && CONST_DOUBLE_LOW (op
) == 0)
106 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
108 restore_operand (op
, mode
)
110 enum machine_mode mode
;
112 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
113 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
116 /* PC-relative call insn on SPARC is independent of `memory_operand'. */
119 call_operand (op
, mode
)
121 enum machine_mode mode
;
123 if (GET_CODE (op
) != MEM
)
126 return (REG_P (op
) || CONSTANT_P (op
));
130 call_operand_address (op
, mode
)
132 enum machine_mode mode
;
134 return (REG_P (op
) || CONSTANT_P (op
));
137 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
138 reference and a constant. */
141 symbolic_operand (op
, mode
)
143 enum machine_mode mode
;
145 switch (GET_CODE (op
))
153 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
154 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
155 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
157 /* This clause seems to be irrelevant. */
159 return GET_MODE (op
) == mode
;
166 /* Return truth value of statement that OP is a symbolic memory
167 operand of mode MODE. */
170 symbolic_memory_operand (op
, mode
)
172 enum machine_mode mode
;
174 if (GET_CODE (op
) == SUBREG
)
175 op
= SUBREG_REG (op
);
176 if (GET_CODE (op
) != MEM
)
179 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
180 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
183 /* Return 1 if the operand is either a register or a memory operand that is
187 reg_or_nonsymb_mem_operand (op
, mode
)
189 enum machine_mode mode
;
191 if (register_operand (op
, mode
))
194 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
201 sparc_operand (op
, mode
)
203 enum machine_mode mode
;
205 if (register_operand (op
, mode
))
207 if (GET_CODE (op
) == CONST_INT
)
208 return SMALL_INT (op
);
209 if (GET_MODE (op
) != mode
)
211 if (GET_CODE (op
) == SUBREG
)
212 op
= SUBREG_REG (op
);
213 if (GET_CODE (op
) != MEM
)
217 if (GET_CODE (op
) == LO_SUM
)
218 return (GET_CODE (XEXP (op
, 0)) == REG
219 && symbolic_operand (XEXP (op
, 1), Pmode
));
220 return memory_address_p (mode
, op
);
224 move_operand (op
, mode
)
226 enum machine_mode mode
;
228 if (mode
== DImode
&& arith_double_operand (op
, mode
))
230 if (register_operand (op
, mode
))
232 if (GET_CODE (op
) == CONST_INT
)
233 return (SMALL_INT (op
) || (INTVAL (op
) & 0x3ff) == 0);
235 if (GET_MODE (op
) != mode
)
237 if (GET_CODE (op
) == SUBREG
)
238 op
= SUBREG_REG (op
);
239 if (GET_CODE (op
) != MEM
)
242 if (GET_CODE (op
) == LO_SUM
)
243 return (register_operand (XEXP (op
, 0), Pmode
)
244 && CONSTANT_P (XEXP (op
, 1)));
245 return memory_address_p (mode
, op
);
249 move_pic_label (op
, mode
)
251 enum machine_mode mode
;
253 /* Special case for PIC. */
254 if (flag_pic
&& GET_CODE (op
) == LABEL_REF
)
259 /* The rtx for the global offset table which is a special form
260 that *is* a position independent symbolic constant. */
263 /* Ensure that we are not using patterns that are not OK with PIC. */
272 if (GET_CODE (recog_operand
[i
]) == SYMBOL_REF
273 || (GET_CODE (recog_operand
[i
]) == CONST
274 && ! rtx_equal_p (pic_pc_rtx
, recog_operand
[i
])))
282 /* Return true if X is an address which needs a temporary register when
283 reloaded while generating PIC code. */
286 pic_address_needs_scratch (x
)
289 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
290 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
291 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
292 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
293 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
302 enum machine_mode mode
;
304 if (GET_CODE (op
) == MEM
)
305 return (mode
== VOIDmode
|| mode
== GET_MODE (op
));
309 /* Return truth value of whether OP is EQ or NE. */
314 enum machine_mode mode
;
316 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
319 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
320 or LTU for non-floating-point. We handle those specially. */
323 normal_comp_operator (op
, mode
)
325 enum machine_mode mode
;
327 enum rtx_code code
= GET_CODE (op
);
329 if (GET_RTX_CLASS (code
) != '<')
332 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
333 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
336 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
339 /* Return 1 if this is a comparison operator. This allows the use of
340 MATCH_OPERATOR to recognize all the branch insns. */
343 noov_compare_op (op
, mode
)
345 enum machine_mode mode
;
347 enum rtx_code code
= GET_CODE (op
);
349 if (GET_RTX_CLASS (code
) != '<')
352 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
)
353 /* These are the only branches which work with CC_NOOVmode. */
354 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
358 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
363 enum machine_mode mode
;
365 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
368 /* Return nonzero if OP is an operator of mode MODE which can set
369 the condition codes explicitly. We do not include PLUS and MINUS
370 because these require CC_NOOVmode, which we handle explicitly. */
373 cc_arithop (op
, mode
)
375 enum machine_mode mode
;
377 if (GET_CODE (op
) == AND
378 || GET_CODE (op
) == IOR
379 || GET_CODE (op
) == XOR
)
385 /* Return nonzero if OP is an operator of mode MODE which can bitwise
386 complement its second operand and set the condition codes explicitly. */
389 cc_arithopn (op
, mode
)
391 enum machine_mode mode
;
393 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
394 and (xor ... (not ...)) to (not (xor ...)). */
395 return (GET_CODE (op
) == AND
396 || GET_CODE (op
) == IOR
);
399 /* Return truth value of whether OP can be used as an operands in a three
400 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
403 arith_operand (op
, mode
)
405 enum machine_mode mode
;
407 return (register_operand (op
, mode
)
408 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
)));
411 /* Return truth value of whether OP is a register or a CONST_DOUBLE. */
414 arith_double_operand (op
, mode
)
416 enum machine_mode mode
;
418 return (register_operand (op
, mode
)
419 || (GET_CODE (op
) == CONST_DOUBLE
420 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
421 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
422 && ((CONST_DOUBLE_HIGH (op
) == -1
423 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
424 || (CONST_DOUBLE_HIGH (op
) == 0
425 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0)))
426 || (GET_CODE (op
) == CONST_INT
427 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
428 && (unsigned) (INTVAL (op
) + 0x1000) < 0x2000));
431 /* Return truth value of whether OP is a integer which fits the
432 range constraining immediate operands in three-address insns. */
437 enum machine_mode mode
;
439 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
442 /* Return truth value of statement that OP is a call-clobbered register. */
444 clobbered_register (op
, mode
)
446 enum machine_mode mode
;
448 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
451 /* X and Y are two things to compare using CODE. Emit the compare insn and
452 return the rtx for register 0 in the proper mode. */
455 gen_compare_reg (code
, x
, y
)
459 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
460 rtx cc_reg
= gen_rtx (REG
, mode
, 0);
462 emit_insn (gen_rtx (SET
, VOIDmode
, cc_reg
,
463 gen_rtx (COMPARE
, mode
, x
, y
)));
468 /* Return nonzero if a return peephole merging return with
469 setting of output register is ok. */
471 leaf_return_peephole_ok ()
473 return (actual_fsize
== 0);
476 /* Return nonzero if TRIAL can go into the function epilogue's
477 delay slot. SLOT is the slot we are trying to fill. */
480 eligible_for_epilogue_delay (trial
, slot
)
484 static char *this_function_name
;
489 if (GET_CODE (trial
) != INSN
490 || GET_CODE (PATTERN (trial
)) != SET
)
492 if (get_attr_length (trial
) != 1)
495 /* In the case of a true leaf function, anything can go into the delay slot.
496 A delay slot only exists however if the frame size is zero, otherwise
497 we will put an insn to adjust the stack after the return. */
500 if (leaf_return_peephole_ok ())
501 return (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
);
505 /* Otherwise, only operations which can be done in tandem with
506 a `restore' insn can go into the delay slot. */
507 pat
= PATTERN (trial
);
508 if (GET_CODE (SET_DEST (pat
)) != REG
509 || REGNO (SET_DEST (pat
)) == 0
510 || REGNO (SET_DEST (pat
)) >= 32
511 || REGNO (SET_DEST (pat
)) < 24)
515 if (arith_operand (src
, GET_MODE (src
)))
516 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
517 if (arith_double_operand (src
, GET_MODE (src
)))
518 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
519 if (GET_CODE (src
) == PLUS
)
521 if (register_operand (XEXP (src
, 0), SImode
)
522 && arith_operand (XEXP (src
, 1), SImode
))
524 if (register_operand (XEXP (src
, 1), SImode
)
525 && arith_operand (XEXP (src
, 0), SImode
))
527 if (register_operand (XEXP (src
, 0), DImode
)
528 && arith_double_operand (XEXP (src
, 1), DImode
))
530 if (register_operand (XEXP (src
, 1), DImode
)
531 && arith_double_operand (XEXP (src
, 0), DImode
))
534 if (GET_CODE (src
) == MINUS
535 && register_operand (XEXP (src
, 0), SImode
)
536 && small_int (XEXP (src
, 1), VOIDmode
))
538 if (GET_CODE (src
) == MINUS
539 && register_operand (XEXP (src
, 0), DImode
)
540 && !register_operand (XEXP (src
, 1), DImode
)
541 && arith_double_operand (XEXP (src
, 1), DImode
))
547 short_branch (uid1
, uid2
)
550 unsigned int delta
= insn_addresses
[uid1
] - insn_addresses
[uid2
];
551 if (delta
+ 1024 < 2048)
553 /* warning ("long branch, distance %d", delta); */
557 /* Return non-zero if REG is not used after INSN.
558 We assume REG is a reload reg, and therefore does
559 not live past labels or calls or jumps. */
561 reg_unused_after (reg
, insn
)
565 enum rtx_code code
, prev_code
= UNKNOWN
;
567 while (insn
= NEXT_INSN (insn
))
569 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
572 code
= GET_CODE (insn
);
573 if (GET_CODE (insn
) == CODE_LABEL
)
576 if (GET_RTX_CLASS (code
) == 'i')
578 rtx set
= single_set (insn
);
579 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
582 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
584 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
592 /* Legitimize PIC addresses. If the address is already position-independent,
593 we return ORIG. Newly generated position-independent addresses go into a
594 reg. This is REG if non zero, otherwise we allocate register(s) as
595 necessary. If this is called during reload, and we need a second temp
596 register, then we use SCRATCH, which is provided via the
597 SECONDARY_INPUT_RELOAD_CLASS mechanism. */
600 legitimize_pic_address (orig
, mode
, reg
, scratch
)
602 enum machine_mode mode
;
605 if (GET_CODE (orig
) == SYMBOL_REF
)
607 rtx pic_ref
, address
;
612 if (reload_in_progress
|| reload_completed
)
615 reg
= gen_reg_rtx (Pmode
);
620 /* If not during reload, allocate another temp reg here for loading
621 in the address, so that these instructions can be optimized
623 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
624 ? reg
: gen_reg_rtx (Pmode
));
626 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
627 won't get confused into thinking that these two instructions
628 are loading in the true address of the symbol. If in the
629 future a PIC rtx exists, that should be used instead. */
630 emit_insn (gen_rtx (SET
, VOIDmode
, temp_reg
,
631 gen_rtx (HIGH
, Pmode
,
632 gen_rtx (UNSPEC
, Pmode
,
635 emit_insn (gen_rtx (SET
, VOIDmode
, temp_reg
,
636 gen_rtx (LO_SUM
, Pmode
, temp_reg
,
637 gen_rtx (UNSPEC
, Pmode
,
645 pic_ref
= gen_rtx (MEM
, Pmode
,
646 gen_rtx (PLUS
, Pmode
,
647 pic_offset_table_rtx
, address
));
648 current_function_uses_pic_offset_table
= 1;
649 RTX_UNCHANGING_P (pic_ref
) = 1;
650 insn
= emit_move_insn (reg
, pic_ref
);
651 /* Put a REG_EQUAL note on this insn, so that it can be optimized
653 REG_NOTES (insn
) = gen_rtx (EXPR_LIST
, REG_EQUAL
, orig
,
657 else if (GET_CODE (orig
) == CONST
)
661 if (GET_CODE (XEXP (orig
, 0)) == PLUS
662 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
667 if (reload_in_progress
|| reload_completed
)
670 reg
= gen_reg_rtx (Pmode
);
673 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
675 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
,
677 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
678 base
== reg
? 0 : reg
, 0);
683 if (GET_CODE (offset
) == CONST_INT
)
685 if (SMALL_INT (offset
))
686 return plus_constant_for_output (base
, INTVAL (offset
));
687 else if (! reload_in_progress
&& ! reload_completed
)
688 offset
= force_reg (Pmode
, offset
);
689 /* We can't create any new registers during reload, so use the
690 SCRATCH reg provided by the reload_insi pattern. */
693 emit_move_insn (scratch
, offset
);
697 /* If we reach here, then the SECONDARY_INPUT_RELOAD_CLASS
698 macro needs to be adjusted so that a scratch reg is provided
702 return gen_rtx (PLUS
, Pmode
, base
, offset
);
704 else if (GET_CODE (orig
) == LABEL_REF
)
705 current_function_uses_pic_offset_table
= 1;
710 /* Set up PIC-specific rtl. This should not cause any insns
718 /* Emit special PIC prologues and epilogues. */
723 /* The table we use to reference PIC data. */
724 rtx global_offset_table
;
725 /* Labels to get the PC in the prologue of this function. */
728 int orig_flag_pic
= flag_pic
;
730 if (current_function_uses_pic_offset_table
== 0)
737 l1
= gen_label_rtx ();
738 l2
= gen_label_rtx ();
743 /* Note that we pun calls and jumps here! */
744 emit_jump_insn (gen_rtx (PARALLEL
, VOIDmode
,
746 gen_rtx (SET
, VOIDmode
, pc_rtx
, gen_rtx (LABEL_REF
, VOIDmode
, l2
)),
747 gen_rtx (SET
, VOIDmode
, gen_rtx (REG
, SImode
, 15), gen_rtx (LABEL_REF
, VOIDmode
, l2
)))));
750 /* Initialize every time through, since we can't easily
751 know this to be permanent. */
752 global_offset_table
= gen_rtx (SYMBOL_REF
, Pmode
, "*__GLOBAL_OFFSET_TABLE_");
753 pic_pc_rtx
= gen_rtx (CONST
, Pmode
,
754 gen_rtx (MINUS
, Pmode
,
756 gen_rtx (CONST
, Pmode
,
757 gen_rtx (MINUS
, Pmode
,
758 gen_rtx (LABEL_REF
, VOIDmode
, l1
),
761 emit_insn (gen_rtx (SET
, VOIDmode
, pic_offset_table_rtx
,
762 gen_rtx (HIGH
, Pmode
, pic_pc_rtx
)));
763 emit_insn (gen_rtx (SET
, VOIDmode
,
764 pic_offset_table_rtx
,
765 gen_rtx (LO_SUM
, Pmode
,
766 pic_offset_table_rtx
, pic_pc_rtx
)));
767 emit_insn (gen_rtx (SET
, VOIDmode
,
768 pic_offset_table_rtx
,
769 gen_rtx (PLUS
, Pmode
,
770 pic_offset_table_rtx
, gen_rtx (REG
, Pmode
, 15))));
771 /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */
772 LABEL_PRESERVE_P (l1
) = 1;
773 LABEL_PRESERVE_P (l2
) = 1;
774 flag_pic
= orig_flag_pic
;
776 seq
= gen_sequence ();
778 emit_insn_after (seq
, get_insns ());
780 /* Need to emit this whether or not we obey regdecls,
781 since setjmp/longjmp can cause life info to screw up. */
782 emit_insn (gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
));
785 /* For the SPARC, REG and REG+CONST is cost 0, REG+REG is cost 1,
786 and addresses involving symbolic constants are cost 2.
788 We make REG+REG slightly more expensive because it might keep
789 a register live for longer than we might like.
791 PIC addresses are very expensive.
793 It is no coincidence that this has the same structure
794 as GO_IF_LEGITIMATE_ADDRESS. */
796 sparc_address_cost (X
)
800 /* Handled before calling here. */
801 if (GET_CODE (X
) == REG
)
804 if (GET_CODE (X
) == PLUS
)
806 if (GET_CODE (XEXP (X
, 0)) == REG
807 && GET_CODE (XEXP (X
, 1)) == REG
)
811 else if (GET_CODE (X
) == LO_SUM
)
813 else if (GET_CODE (X
) == HIGH
)
818 /* Emit insns to move operands[1] into operands[0].
820 Return 1 if we have written out everything that needs to be done to
821 do the move. Otherwise, return 0 and the caller will emit the move
824 SCRATCH_REG if non zero can be used as a scratch register for the move
825 operation. It is provided by a SECONDARY_RELOAD_* macro if needed. */
828 emit_move_sequence (operands
, mode
, scratch_reg
)
830 enum machine_mode mode
;
833 register rtx operand0
= operands
[0];
834 register rtx operand1
= operands
[1];
836 /* Handle most common case first: storing into a register. */
837 if (register_operand (operand0
, mode
))
839 if (register_operand (operand1
, mode
)
840 || (GET_CODE (operand1
) == CONST_INT
&& SMALL_INT (operand1
))
841 || (GET_CODE (operand1
) == CONST_DOUBLE
842 && arith_double_operand (operand1
, DImode
))
843 || (GET_CODE (operand1
) == HIGH
&& GET_MODE (operand1
) != DImode
)
844 /* Only `general_operands' can come here, so MEM is ok. */
845 || GET_CODE (operand1
) == MEM
)
847 /* Run this case quickly. */
848 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
852 else if (GET_CODE (operand0
) == MEM
)
854 if (register_operand (operand1
, mode
) || operand1
== const0_rtx
)
856 /* Run this case quickly. */
857 emit_insn (gen_rtx (SET
, VOIDmode
, operand0
, operand1
));
860 if (! reload_in_progress
)
862 operands
[0] = validize_mem (operand0
);
863 operands
[1] = operand1
= force_reg (mode
, operand1
);
867 /* Simplify the source if we need to. Must handle DImode HIGH operators
868 here because such a move needs a clobber added. */
869 if ((GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
870 || (GET_CODE (operand1
) == HIGH
&& GET_MODE (operand1
) == DImode
))
872 if (flag_pic
&& symbolic_operand (operand1
, mode
))
874 rtx temp_reg
= reload_in_progress
? operand0
: 0;
876 operands
[1] = legitimize_pic_address (operand1
, mode
, temp_reg
,
879 else if (GET_CODE (operand1
) == CONST_INT
880 ? (! SMALL_INT (operand1
)
881 && (INTVAL (operand1
) & 0x3ff) != 0)
882 : (GET_CODE (operand1
) == CONST_DOUBLE
883 ? ! arith_double_operand (operand1
, DImode
)
886 /* For DImode values, temp must be operand0 because of the way
887 HI and LO_SUM work. The LO_SUM operator only copies half of
888 the LSW from the dest of the HI operator. If the LO_SUM dest is
889 not the same as the HI dest, then the MSW of the LO_SUM dest will
892 ??? The real problem here is that the ...(HI:DImode pattern emits
893 multiple instructions, and the ...(LO_SUM:DImode pattern emits
894 one instruction. This fails, because the compiler assumes that
895 LO_SUM copies all bits of the first operand to its dest. Better
896 would be to have the HI pattern emit one instruction and the
897 LO_SUM pattern multiple instructions. Even better would be
898 to use four rtl insns. */
899 rtx temp
= ((reload_in_progress
|| mode
== DImode
)
900 ? operand0
: gen_reg_rtx (mode
));
902 emit_insn (gen_rtx (SET
, VOIDmode
, temp
,
903 gen_rtx (HIGH
, mode
, operand1
)));
904 operands
[1] = gen_rtx (LO_SUM
, mode
, temp
, operand1
);
908 if (GET_CODE (operand1
) == LABEL_REF
&& flag_pic
)
910 /* The procedure for doing this involves using a call instruction to
911 get the pc into o7. We need to indicate this explicitly because
912 the tablejump pattern assumes that it can use this value also. */
913 emit_insn (gen_rtx (PARALLEL
, VOIDmode
,
915 gen_rtx (SET
, VOIDmode
, operand0
,
917 gen_rtx (SET
, VOIDmode
,
918 gen_rtx (REG
, mode
, 15),
923 /* Now have insn-emit do whatever it normally does. */
927 /* Return the best assembler insn template
928 for moving operands[1] into operands[0] as a fullword. */
931 singlemove_string (operands
)
934 if (GET_CODE (operands
[0]) == MEM
)
936 if (GET_CODE (operands
[1]) != MEM
)
941 else if (GET_CODE (operands
[1]) == MEM
)
943 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
946 union real_extract u
;
947 union float_extract
{ float f
; int i
; } v
;
949 /* Must be SFmode, otherwise this doesn't make sense. */
950 if (GET_MODE (operands
[1]) != SFmode
)
953 bcopy (&CONST_DOUBLE_LOW (operands
[1]), &u
, sizeof u
);
954 v
.f
= REAL_VALUE_TRUNCATE (SFmode
, u
.d
);
957 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
);
959 if (CONST_OK_FOR_LETTER_P (i
, 'I'))
961 else if ((i
& 0x000003FF) != 0)
962 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
964 return "sethi %%hi(%a1),%0";
966 else if (GET_CODE (operands
[1]) == CONST_INT
967 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands
[1]), 'I'))
969 int i
= INTVAL (operands
[1]);
971 /* If all low order 10 bits are clear, then we only need a single
972 sethi insn to load the constant. */
973 if ((i
& 0x000003FF) != 0)
974 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
976 return "sethi %%hi(%a1),%0";
978 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
982 /* Return non-zero if it is OK to assume that the given memory operand is
983 aligned at least to a 8-byte boundary. This should only be called
984 for memory accesses whose size is 8 bytes or larger. */
994 if (GET_CODE (mem
) != MEM
)
995 abort (); /* It's gotta be a MEM! */
997 addr
= XEXP (mem
, 0);
1000 /* Now that all misaligned double parms are copied on function entry,
1001 we can assume any 64-bit object is 64-bit aligned. */
1003 /* See what register we use in the address. */
1005 if (GET_CODE (addr
) == PLUS
)
1007 if (GET_CODE (XEXP (addr
, 0)) == REG
1008 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
1010 base
= XEXP (addr
, 0);
1011 offset
= XEXP (addr
, 1);
1014 else if (GET_CODE (addr
) == REG
)
1017 offset
= const0_rtx
;
1020 /* If it's the stack or frame pointer, check offset alignment.
1021 We can have improper alignment in the function entry code. */
1023 && (REGNO (base
) == FRAME_POINTER_REGNUM
1024 || REGNO (base
) == STACK_POINTER_REGNUM
))
1026 if ((INTVAL (offset
) & 0x7) == 0)
1030 /* Anything else, we know is properly aligned. */
1033 /* If the operand is known to have been allocated in static storage, then
1034 it must be aligned. */
1036 if (CONSTANT_P (addr
) || GET_CODE (addr
) == LO_SUM
)
1040 if (GET_CODE (addr
) == PLUS
)
1042 if (GET_CODE (XEXP (addr
, 0)) == REG
1043 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
1045 base
= XEXP (addr
, 0);
1046 offset
= XEXP (addr
, 1);
1049 else if (GET_CODE (addr
) == REG
)
1052 offset
= const0_rtx
;
1055 /* Trust round enough offsets from the stack or frame pointer.
1056 If TARGET_HOPE_ALIGN, trust round enough offset from any register.
1057 If it is obviously unaligned, don't ever return true. */
1059 && (REGNO (base
) == FRAME_POINTER_REGNUM
1060 || REGNO (base
) == STACK_POINTER_REGNUM
1061 || TARGET_HOPE_ALIGN
))
1063 if ((INTVAL (offset
) & 0x7) == 0)
1066 /* Otherwise, we can assume that an access is aligned if it is to an
1067 aggregate. Also, if TARGET_HOPE_ALIGN, then assume everything that isn't
1068 obviously unaligned is aligned. */
1069 else if (MEM_IN_STRUCT_P (mem
) || TARGET_HOPE_ALIGN
)
1073 /* An obviously unaligned address. */
1077 enum optype
{ REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
};
1079 /* Output assembler code to perform a doubleword move insn
1080 with operands OPERANDS. This is very similar to the following
1081 output_move_quad function. */
1084 output_move_double (operands
)
1087 register rtx op0
= operands
[0];
1088 register rtx op1
= operands
[1];
1089 register enum optype optype0
;
1090 register enum optype optype1
;
1095 /* First classify both operands. */
1099 else if (offsettable_memref_p (op0
))
1101 else if (GET_CODE (op0
) == MEM
)
1108 else if (CONSTANT_P (op1
))
1110 else if (offsettable_memref_p (op1
))
1112 else if (GET_CODE (op1
) == MEM
)
1117 /* Check for the cases that the operand constraints are not
1118 supposed to allow to happen. Abort if we get one,
1119 because generating code for these cases is painful. */
1121 if (optype0
== RNDOP
|| optype1
== RNDOP
1122 || (optype0
== MEM
&& optype1
== MEM
))
1125 /* If an operand is an unoffsettable memory ref, find a register
1126 we can increment temporarily to make it refer to the second word. */
1128 if (optype0
== MEMOP
)
1129 addreg0
= find_addr_reg (XEXP (op0
, 0));
1131 if (optype1
== MEMOP
)
1132 addreg1
= find_addr_reg (XEXP (op1
, 0));
1134 /* Ok, we can do one word at a time.
1135 Set up in LATEHALF the operands to use for the
1136 high-numbered (least significant) word and in some cases alter the
1137 operands in OPERANDS to be suitable for the low-numbered word. */
1139 if (optype0
== REGOP
)
1140 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 1);
1141 else if (optype0
== OFFSOP
)
1142 latehalf
[0] = adj_offsettable_operand (op0
, 4);
1146 if (optype1
== REGOP
)
1147 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 1);
1148 else if (optype1
== OFFSOP
)
1149 latehalf
[1] = adj_offsettable_operand (op1
, 4);
1150 else if (optype1
== CNSTOP
)
1151 split_double (op1
, &operands
[1], &latehalf
[1]);
1155 /* Easy case: try moving both words at once. Check for moving between
1156 an even/odd register pair and a memory location. */
1157 if ((optype0
== REGOP
&& optype1
!= REGOP
&& optype1
!= CNSTOP
1158 && (REGNO (op0
) & 1) == 0)
1159 || (optype0
!= REGOP
&& optype0
!= CNSTOP
&& optype1
== REGOP
1160 && (REGNO (op1
) & 1) == 0))
1164 if (optype0
== REGOP
)
1169 if (mem_aligned_8 (mem
))
1170 return (mem
== op1
? "ldd %1,%0" : "std %1,%0");
1173 /* If the first move would clobber the source of the second one,
1174 do them in the other order. */
1176 /* Overlapping registers. */
1177 if (optype0
== REGOP
&& optype1
== REGOP
1178 && REGNO (op0
) == REGNO (latehalf
[1]))
1181 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1182 /* Do low-numbered word. */
1183 return singlemove_string (operands
);
1185 /* Loading into a register which overlaps a register used in the address. */
1186 else if (optype0
== REGOP
&& optype1
!= REGOP
1187 && reg_overlap_mentioned_p (op0
, op1
))
1189 /* ??? This fails if the address is a double register address, each
1190 of which is clobbered by operand 0. */
1191 /* Do the late half first. */
1192 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1194 return singlemove_string (operands
);
1197 /* Normal case: do the two words, low-numbered first. */
1199 output_asm_insn (singlemove_string (operands
), operands
);
1201 /* Make any unoffsettable addresses point at high-numbered word. */
1203 output_asm_insn ("add %0,0x4,%0", &addreg0
);
1205 output_asm_insn ("add %0,0x4,%0", &addreg1
);
1208 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1210 /* Undo the adds we just did. */
1212 output_asm_insn ("add %0,-0x4,%0", &addreg0
);
1214 output_asm_insn ("add %0,-0x4,%0", &addreg1
);
1219 /* Output assembler code to perform a quadword move insn
1220 with operands OPERANDS. This is very similar to the preceding
1221 output_move_double function. */
1224 output_move_quad (operands
)
1227 register rtx op0
= operands
[0];
1228 register rtx op1
= operands
[1];
1229 register enum optype optype0
;
1230 register enum optype optype1
;
1235 /* First classify both operands. */
1239 else if (offsettable_memref_p (op0
))
1241 else if (GET_CODE (op0
) == MEM
)
1248 else if (CONSTANT_P (op1
))
1250 else if (offsettable_memref_p (op1
))
1252 else if (GET_CODE (op1
) == MEM
)
1257 /* Check for the cases that the operand constraints are not
1258 supposed to allow to happen. Abort if we get one,
1259 because generating code for these cases is painful. */
1261 if (optype0
== RNDOP
|| optype1
== RNDOP
1262 || (optype0
== MEM
&& optype1
== MEM
))
1265 /* If an operand is an unoffsettable memory ref, find a register
1266 we can increment temporarily to make it refer to the later words. */
1268 if (optype0
== MEMOP
)
1269 addreg0
= find_addr_reg (XEXP (op0
, 0));
1271 if (optype1
== MEMOP
)
1272 addreg1
= find_addr_reg (XEXP (op1
, 0));
1274 /* Ok, we can do one word at a time.
1275 Set up in wordpart the operands to use for each word of the arguments. */
1277 if (optype0
== REGOP
)
1279 wordpart
[0][0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 0);
1280 wordpart
[1][0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 1);
1281 wordpart
[2][0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 2);
1282 wordpart
[3][0] = gen_rtx (REG
, SImode
, REGNO (op0
) + 3);
1284 else if (optype0
== OFFSOP
)
1286 wordpart
[0][0] = adj_offsettable_operand (op0
, 0);
1287 wordpart
[1][0] = adj_offsettable_operand (op0
, 4);
1288 wordpart
[2][0] = adj_offsettable_operand (op0
, 8);
1289 wordpart
[3][0] = adj_offsettable_operand (op0
, 12);
1293 wordpart
[0][0] = op0
;
1294 wordpart
[1][0] = op0
;
1295 wordpart
[2][0] = op0
;
1296 wordpart
[3][0] = op0
;
1299 if (optype1
== REGOP
)
1301 wordpart
[0][1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 0);
1302 wordpart
[1][1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 1);
1303 wordpart
[2][1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 2);
1304 wordpart
[3][1] = gen_rtx (REG
, SImode
, REGNO (op1
) + 3);
1306 else if (optype1
== OFFSOP
)
1308 wordpart
[0][1] = adj_offsettable_operand (op1
, 0);
1309 wordpart
[1][1] = adj_offsettable_operand (op1
, 4);
1310 wordpart
[2][1] = adj_offsettable_operand (op1
, 8);
1311 wordpart
[3][1] = adj_offsettable_operand (op1
, 12);
1313 else if (optype1
== CNSTOP
)
1315 /* This case isn't implemented yet, because there is no internal
1316 representation for quad-word constants, and there is no split_quad
1319 split_quad (op1
, &wordpart
[0][1], &wordpart
[1][1],
1320 &wordpart
[2][1], &wordpart
[3][1]);
1327 wordpart
[0][1] = op1
;
1328 wordpart
[1][1] = op1
;
1329 wordpart
[2][1] = op1
;
1330 wordpart
[3][1] = op1
;
1333 /* Easy case: try moving the quad as two pairs. Check for moving between
1334 an even/odd register pair and a memory location. */
1335 /* ??? Should also handle the case of non-offsettable addresses here.
1336 We can at least do the first pair as a ldd/std, and then do the third
1337 and fourth words individually. */
1338 if ((optype0
== REGOP
&& optype1
== OFFSOP
&& (REGNO (op0
) & 1) == 0)
1339 || (optype0
== OFFSOP
&& optype1
== REGOP
&& (REGNO (op1
) & 1) == 0))
1343 if (optype0
== REGOP
)
1348 if (mem_aligned_8 (mem
))
1350 operands
[2] = adj_offsettable_operand (mem
, 8);
1352 return "ldd %1,%0;ldd %2,%S0";
1354 return "std %1,%0;std %S1,%2";
1358 /* If the first move would clobber the source of the second one,
1359 do them in the other order. */
1361 /* Overlapping registers. */
1362 if (optype0
== REGOP
&& optype1
== REGOP
1363 && (REGNO (op0
) == REGNO (wordpart
[1][3])
1364 || REGNO (op0
) == REGNO (wordpart
[1][2])
1365 || REGNO (op0
) == REGNO (wordpart
[1][1])))
1367 /* Do fourth word. */
1368 output_asm_insn (singlemove_string (wordpart
[3]), wordpart
[3]);
1369 /* Do the third word. */
1370 output_asm_insn (singlemove_string (wordpart
[2]), wordpart
[2]);
1371 /* Do the second word. */
1372 output_asm_insn (singlemove_string (wordpart
[1]), wordpart
[1]);
1373 /* Do lowest-numbered word. */
1374 return singlemove_string (wordpart
[0]);
1376 /* Loading into a register which overlaps a register used in the address. */
1377 if (optype0
== REGOP
&& optype1
!= REGOP
1378 && reg_overlap_mentioned_p (op0
, op1
))
1380 /* ??? Not implemented yet. This is a bit complicated, because we
1381 must load which ever part overlaps the address last. If the address
1382 is a double-reg address, then there are two parts which need to
1383 be done last, which is impossible. We would need a scratch register
1388 /* Normal case: move the four words in lowest to higest address order. */
1390 output_asm_insn (singlemove_string (wordpart
[0]), wordpart
[0]);
1392 /* Make any unoffsettable addresses point at the second word. */
1394 output_asm_insn ("add %0,0x4,%0", &addreg0
);
1396 output_asm_insn ("add %0,0x4,%0", &addreg1
);
1398 /* Do the second word. */
1399 output_asm_insn (singlemove_string (wordpart
[1]), wordpart
[1]);
1401 /* Make any unoffsettable addresses point at the third word. */
1403 output_asm_insn ("add %0,0x4,%0", &addreg0
);
1405 output_asm_insn ("add %0,0x4,%0", &addreg1
);
1407 /* Do the third word. */
1408 output_asm_insn (singlemove_string (wordpart
[2]), wordpart
[2]);
1410 /* Make any unoffsettable addresses point at the fourth word. */
1412 output_asm_insn ("add %0,0x4,%0", &addreg0
);
1414 output_asm_insn ("add %0,0x4,%0", &addreg1
);
1416 /* Do the fourth word. */
1417 output_asm_insn (singlemove_string (wordpart
[3]), wordpart
[3]);
1419 /* Undo the adds we just did. */
1421 output_asm_insn ("add %0,-0xc,%0", &addreg0
);
1423 output_asm_insn ("add %0,-0xc,%0", &addreg1
);
1428 /* Output assembler code to perform a doubleword move insn with operands
1429 OPERANDS, one of which must be a floating point register. */
1432 output_fp_move_double (operands
)
1437 if (FP_REG_P (operands
[0]))
1439 if (FP_REG_P (operands
[1]))
1440 return "fmovs %1,%0\n\tfmovs %R1,%R0";
1441 else if (GET_CODE (operands
[1]) == REG
)
1443 if ((REGNO (operands
[1]) & 1) == 0)
1444 return "std %1,[%@-8]\n\tldd [%@-8],%0";
1446 return "st %R1,[%@-4]\n\tst %1,[%@-8]\n\tldd [%@-8],%0";
1449 return output_move_double (operands
);
1451 else if (FP_REG_P (operands
[1]))
1453 if (GET_CODE (operands
[0]) == REG
)
1455 if ((REGNO (operands
[0]) & 1) == 0)
1456 return "std %1,[%@-8]\n\tldd [%@-8],%0";
1458 return "std %1,[%@-8]\n\tld [%@-4],%R0\n\tld [%@-8],%0";
1461 return output_move_double (operands
);
1466 /* Output assembler code to perform a quadword move insn with operands
1467 OPERANDS, one of which must be a floating point register. */
1470 output_fp_move_quad (operands
)
1473 register rtx op0
= operands
[0];
1474 register rtx op1
= operands
[1];
1480 return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0";
1481 if (GET_CODE (op1
) == REG
)
1483 if ((REGNO (op1
) & 1) == 0)
1484 return "std %1,[%@-8]\n\tldd [%@-8],%0\n\tstd %S1,[%@-8]\n\tldd [%@-8],%S0";
1486 return "st %R1,[%@-4]\n\tst %1,[%@-8]\n\tldd [%@-8],%0\n\tst %T1,[%@-4]\n\tst %S1,[%@-8]\n\tldd [%@-8],%S0";
1489 return output_move_quad (operands
);
1491 else if (FP_REG_P (op1
))
1493 if (GET_CODE (op0
) == REG
)
1495 if ((REGNO (op0
) & 1) == 0)
1496 return "std %1,[%@-8]\n\tldd [%@-8],%0\n\tstd %S1,[%@-8]\n\tldd [%@-8],%S0";
1498 return "std %S1,[%@-8]\n\tld [%@-4],%T0\n\tld [%@-8],%S0\n\tstd %1,[%@-8]\n\tld [%@-4],%R0\n\tld [%@-8],%0";
1501 return output_move_quad (operands
);
1507 /* Return a REG that occurs in ADDR with coefficient 1.
1508 ADDR can be effectively incremented by incrementing REG. */
1511 find_addr_reg (addr
)
1514 while (GET_CODE (addr
) == PLUS
)
1516 /* We absolutely can not fudge the frame pointer here, because the
1517 frame pointer must always be 8 byte aligned. It also confuses
1519 if (GET_CODE (XEXP (addr
, 0)) == REG
1520 && REGNO (XEXP (addr
, 0)) != FRAME_POINTER_REGNUM
)
1521 addr
= XEXP (addr
, 0);
1522 else if (GET_CODE (XEXP (addr
, 1)) == REG
1523 && REGNO (XEXP (addr
, 1)) != FRAME_POINTER_REGNUM
)
1524 addr
= XEXP (addr
, 1);
1525 else if (CONSTANT_P (XEXP (addr
, 0)))
1526 addr
= XEXP (addr
, 1);
1527 else if (CONSTANT_P (XEXP (addr
, 1)))
1528 addr
= XEXP (addr
, 0);
1532 if (GET_CODE (addr
) == REG
)
1538 output_sized_memop (opname
, mode
, signedp
)
1540 enum machine_mode mode
;
1543 static char *ld_size_suffix_u
[] = { "ub", "uh", "", "?", "d" };
1544 static char *ld_size_suffix_s
[] = { "sb", "sh", "", "?", "d" };
1545 static char *st_size_suffix
[] = { "b", "h", "", "?", "d" };
1546 char **opnametab
, *modename
;
1548 if (opname
[0] == 'l')
1550 opnametab
= ld_size_suffix_s
;
1552 opnametab
= ld_size_suffix_u
;
1554 opnametab
= st_size_suffix
;
1555 modename
= opnametab
[GET_MODE_SIZE (mode
) >> 1];
1557 fprintf (asm_out_file
, "\t%s%s", opname
, modename
);
1561 output_move_with_extension (operands
)
1564 if (GET_MODE (operands
[2]) == HImode
)
1565 output_asm_insn ("sll %2,0x10,%0", operands
);
1566 else if (GET_MODE (operands
[2]) == QImode
)
1567 output_asm_insn ("sll %2,0x18,%0", operands
);
1572 /* Load the address specified by OPERANDS[3] into the register
1573 specified by OPERANDS[0].
1575 OPERANDS[3] may be the result of a sum, hence it could either be:
1580 (3) REG + REG + CONST_INT
1581 (4) REG + REG (special case of 3).
1583 Note that (3) is not a legitimate address.
1584 All cases are handled here. */
1587 output_load_address (operands
)
1592 if (CONSTANT_P (operands
[3]))
1594 output_asm_insn ("set %3,%0", operands
);
1598 if (REG_P (operands
[3]))
1600 if (REGNO (operands
[0]) != REGNO (operands
[3]))
1601 output_asm_insn ("mov %3,%0", operands
);
1605 if (GET_CODE (operands
[3]) != PLUS
)
1608 base
= XEXP (operands
[3], 0);
1609 offset
= XEXP (operands
[3], 1);
1611 if (GET_CODE (base
) == CONST_INT
)
1618 if (GET_CODE (offset
) != CONST_INT
)
1620 /* Operand is (PLUS (REG) (REG)). */
1622 offset
= const0_rtx
;
1628 operands
[7] = offset
;
1629 if (SMALL_INT (offset
))
1630 output_asm_insn ("add %6,%7,%0", operands
);
1632 output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands
);
1634 else if (GET_CODE (base
) == PLUS
)
1636 operands
[6] = XEXP (base
, 0);
1637 operands
[7] = XEXP (base
, 1);
1638 operands
[8] = offset
;
1640 if (SMALL_INT (offset
))
1641 output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands
);
1643 output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands
);
1649 /* Output code to place a size count SIZE in register REG.
1650 ALIGN is the size of the unit of transfer.
1652 Because block moves are pipelined, we don't include the
1653 first element in the transfer of SIZE to REG. */
1656 output_size_for_block_move (size
, reg
, align
)
1663 xoperands
[1] = size
;
1664 xoperands
[2] = align
;
1665 if (GET_CODE (size
) == REG
)
1666 output_asm_insn ("sub %1,%2,%0", xoperands
);
1670 = gen_rtx (CONST_INT
, VOIDmode
, INTVAL (size
) - INTVAL (align
));
1671 output_asm_insn ("set %1,%0", xoperands
);
1675 /* Emit code to perform a block move.
1677 OPERANDS[0] is the destination.
1678 OPERANDS[1] is the source.
1679 OPERANDS[2] is the size.
1680 OPERANDS[3] is the alignment safe to use.
1681 OPERANDS[4] is a register we can safely clobber as a temp. */
1684 output_block_move (operands
)
1687 /* A vector for our computed operands. Note that load_output_address
1688 makes use of (and can clobber) up to the 8th element of this vector. */
1691 static int movstrsi_label
= 0;
1693 rtx temp1
= operands
[4];
1694 rtx sizertx
= operands
[2];
1695 rtx alignrtx
= operands
[3];
1696 int align
= INTVAL (alignrtx
);
1697 char label3
[30], label5
[30];
1699 xoperands
[0] = operands
[0];
1700 xoperands
[1] = operands
[1];
1701 xoperands
[2] = temp1
;
1703 /* We can't move more than this many bytes at a time because we have only
1704 one register, %g1, to move them through. */
1705 if (align
> UNITS_PER_WORD
)
1707 align
= UNITS_PER_WORD
;
1708 alignrtx
= gen_rtx (CONST_INT
, VOIDmode
, UNITS_PER_WORD
);
1711 /* We consider 8 ld/st pairs, for a total of 16 inline insns to be
1712 reasonable here. (Actually will emit a maximum of 18 inline insns for
1713 the case of size == 31 and align == 4). */
1715 if (GET_CODE (sizertx
) == CONST_INT
&& (INTVAL (sizertx
) / align
) <= 8
1716 && memory_address_p (QImode
, plus_constant_for_output (xoperands
[0],
1718 && memory_address_p (QImode
, plus_constant_for_output (xoperands
[1],
1721 int size
= INTVAL (sizertx
);
1724 /* We will store different integers into this particular RTX. */
1725 xoperands
[2] = rtx_alloc (CONST_INT
);
1726 PUT_MODE (xoperands
[2], VOIDmode
);
1728 /* This case is currently not handled. Abort instead of generating
1735 for (i
= (size
>> 2) - 1; i
>= 0; i
--)
1737 INTVAL (xoperands
[2]) = (i
<< 2) + offset
;
1738 output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]",
1741 offset
+= (size
& ~0x3);
1749 for (i
= (size
>> 1) - 1; i
>= 0; i
--)
1751 INTVAL (xoperands
[2]) = (i
<< 1) + offset
;
1752 output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]",
1755 offset
+= (size
& ~0x1);
1763 for (i
= size
- 1; i
>= 0; i
--)
1765 INTVAL (xoperands
[2]) = i
+ offset
;
1766 output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]",
1772 /* We should never reach here. */
1776 /* If the size isn't known to be a multiple of the alignment,
1777 we have to do it in smaller pieces. If we could determine that
1778 the size was a multiple of 2 (or whatever), we could be smarter
1780 if (GET_CODE (sizertx
) != CONST_INT
)
1784 int size
= INTVAL (sizertx
);
1785 while (size
% align
)
1789 if (align
!= INTVAL (alignrtx
))
1790 alignrtx
= gen_rtx (CONST_INT
, VOIDmode
, align
);
1792 xoperands
[3] = gen_rtx (CONST_INT
, VOIDmode
, movstrsi_label
++);
1793 xoperands
[4] = gen_rtx (CONST_INT
, VOIDmode
, align
);
1794 xoperands
[5] = gen_rtx (CONST_INT
, VOIDmode
, movstrsi_label
++);
1796 ASM_GENERATE_INTERNAL_LABEL (label3
, "Lm", INTVAL (xoperands
[3]));
1797 ASM_GENERATE_INTERNAL_LABEL (label5
, "Lm", INTVAL (xoperands
[5]));
1799 /* This is the size of the transfer. Emit code to decrement the size
1800 value by ALIGN, and store the result in the temp1 register. */
1801 output_size_for_block_move (sizertx
, temp1
, alignrtx
);
1803 /* Must handle the case when the size is zero or negative, so the first thing
1804 we do is compare the size against zero, and only copy bytes if it is
1805 zero or greater. Note that we have already subtracted off the alignment
1806 once, so we must copy 1 alignment worth of bytes if the size is zero
1809 The SUN assembler complains about labels in branch delay slots, so we
1810 do this before outputting the load address, so that there will always
1811 be a harmless insn between the branch here and the next label emitted
1817 sprintf (pattern
, "cmp %%2,0\n\tbl %s", &label5
[1]);
1818 output_asm_insn (pattern
, xoperands
);
1821 zoperands
[0] = operands
[0];
1822 zoperands
[3] = plus_constant_for_output (operands
[0], align
);
1823 output_load_address (zoperands
);
1825 /* ??? This might be much faster if the loops below were preconditioned
1828 That is, at run time, copy enough bytes one at a time to ensure that the
1829 target and source addresses are aligned to the the largest possible
1830 alignment. Then use a preconditioned unrolled loop to copy say 16
1831 bytes at a time. Then copy bytes one at a time until finish the rest. */
1833 /* Output the first label separately, so that it is spaced properly. */
1835 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "Lm", INTVAL (xoperands
[3]));
1839 register char *ld_suffix
= (align
== 1) ? "ub" : (align
== 2) ? "uh" : "";
1840 register char *st_suffix
= (align
== 1) ? "b" : (align
== 2) ? "h" : "";
1842 sprintf (pattern
, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix
, &label3
[1], st_suffix
, &label5
[1]);
1843 output_asm_insn (pattern
, xoperands
);
1849 /* Output reasonable peephole for set-on-condition-code insns.
1850 Note that these insns assume a particular way of defining
1851 labels. Therefore, *both* sparc.h and this function must
1852 be changed if a new syntax is needed. */
1855 output_scc_insn (operands
, insn
)
1859 static char string
[100];
1860 rtx label
= 0, next
= insn
;
1863 /* Try doing a jump optimization which jump.c can't do for us
1864 because we did not expose that setcc works by using branches.
1866 If this scc insn is followed by an unconditional branch, then have
1867 the jump insn emitted here jump to that location, instead of to
1868 the end of the scc sequence as usual. */
1872 if (GET_CODE (next
) == CODE_LABEL
)
1874 next
= NEXT_INSN (next
);
1878 while (GET_CODE (next
) == NOTE
|| GET_CODE (next
) == CODE_LABEL
);
1880 /* If we are in a sequence, and the following insn is a sequence also,
1881 then just following the current insn's next field will take us to the
1882 first insn of the next sequence, which is the wrong place. We don't
1883 want to optimize with a branch that has had its delay slot filled.
1884 Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next
1885 which fails only if NEXT is such a branch. */
1887 if (next
&& GET_CODE (next
) == JUMP_INSN
&& simplejump_p (next
)
1888 && (! final_sequence
|| NEXT_INSN (PREV_INSN (next
)) == next
))
1889 label
= JUMP_LABEL (next
);
1890 /* If not optimizing, jump label fields are not set. To be safe, always
1891 check here to whether label is still zero. */
1894 label
= gen_label_rtx ();
1898 LABEL_NUSES (label
) += 1;
1900 operands
[2] = label
;
1902 /* If we are in a delay slot, assume it is the delay slot of an fpcc
1903 insn since our type isn't allowed anywhere else. */
1905 /* ??? Fpcc instructions no longer have delay slots, so this code is
1906 probably obsolete. */
1908 /* The fastest way to emit code for this is an annulled branch followed
1909 by two move insns. This will take two cycles if the branch is taken,
1910 and three cycles if the branch is not taken.
1912 However, if we are in the delay slot of another branch, this won't work,
1913 because we can't put a branch in the delay slot of another branch.
1914 The above sequence would effectively take 3 or 4 cycles respectively
1915 since a no op would have be inserted between the two branches.
1916 In this case, we want to emit a move, annulled branch, and then the
1917 second move. This sequence always takes 3 cycles, and hence is faster
1918 when we are in a branch delay slot. */
1922 strcpy (string
, "mov 0,%0\n\t");
1923 strcat (string
, output_cbranch (operands
[1], 2, 0, 1, 0));
1924 strcat (string
, "\n\tmov 1,%0");
1928 strcpy (string
, output_cbranch (operands
[1], 2, 0, 1, 0));
1929 strcat (string
, "\n\tmov 1,%0\n\tmov 0,%0");
1933 strcat (string
, "\n%l2:");
1938 /* Vectors to keep interesting information about registers where
1939 it can easily be got. */
1941 /* Modes for condition codes. */
1943 ((1 << (int) CCmode) | (1 << (int) CC_NOOVmode) \
1944 | (1 << (int) CCFPmode) | (1 << (int) CCFPEmode))
1946 /* Modes for single-word (and smaller) quantities. */
1949 & ~ ((1 << (int) DImode) | (1 << (int) TImode) \
1950 | (1 << (int) DFmode) | (1 << (int) TFmode)))
1952 /* Modes for double-word (and smaller) quantities. */
1955 & ~ ((1 << (int) TImode) | (1 << (int) TFmode)))
1957 /* Modes for quad-word quantities. */
1958 #define T_MODES (~C_MODES)
1960 /* Modes for single-float quantities. */
1961 #define SF_MODES ((1 << (int) SFmode))
1963 /* Modes for double-float quantities. */
1964 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1966 /* Modes for quad-float quantities. */
1967 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1969 /* Value is 1 if register/mode pair is acceptable on sparc.
1970 The funny mixture of D and T modes is because integer operations
1971 do not specially operate on tetra quantities, so non-quad-aligned
1972 registers can hold quadword quantities (except %o4 and %i4 because
1973 they cross fixed registers. */
1975 int hard_regno_mode_ok
[] = {
1976 C_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1977 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
1978 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
1979 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
1981 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
1982 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
1983 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
1984 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
};
1990 save_regs (file
, low
, high
, base
, offset
, n_fregs
)
1999 for (i
= low
; i
< high
; i
+= 2)
2001 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2002 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2003 fprintf (file
, "\tstd %s,[%s+%d]\n",
2004 reg_names
[i
], base
, offset
+ 4 * n_fregs
),
2007 fprintf (file
, "\tst %s,[%s+%d]\n",
2008 reg_names
[i
], base
, offset
+ 4 * n_fregs
),
2010 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2011 fprintf (file
, "\tst %s,[%s+%d]\n",
2012 reg_names
[i
+1], base
, offset
+ 4 * n_fregs
),
2022 restore_regs (file
, low
, high
, base
, offset
, n_fregs
)
2030 for (i
= low
; i
< high
; i
+= 2)
2032 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
2033 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2034 fprintf (file
, "\tldd [%s+%d], %s\n",
2035 base
, offset
+ 4 * n_fregs
, reg_names
[i
]),
2038 fprintf (file
, "\tld [%s+%d],%s\n",
2039 base
, offset
+ 4 * n_fregs
, reg_names
[i
]),
2041 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
2042 fprintf (file
, "\tld [%s+%d],%s\n",
2043 base
, offset
+ 4 * n_fregs
, reg_names
[i
+1]),
2049 /* Static variables we want to share between prologue and epilogue. */
2051 /* Number of live floating point registers needed to be saved. */
2052 static int num_fregs
;
2054 /* Nonzero if any floating point register was ever used. */
2055 static int fregs_ever_live
;
2058 compute_frame_size (size
, leaf_function
)
2062 int fregs_ever_live
= 0;
2064 int outgoing_args_size
= (current_function_outgoing_args_size
2065 + REG_PARM_STACK_SPACE (current_function_decl
));
2067 apparent_fsize
= ((size
) + 7 - STARTING_FRAME_OFFSET
) & -8;
2068 for (i
= 32; i
< FIRST_PSEUDO_REGISTER
; i
+= 2)
2069 fregs_ever_live
|= regs_ever_live
[i
]|regs_ever_live
[i
+1];
2071 if (TARGET_EPILOGUE
&& fregs_ever_live
)
2073 for (i
= 32; i
< FIRST_PSEUDO_REGISTER
; i
+= 2)
2074 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
2075 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
2079 /* Set up values for use in `function_epilogue'. */
2080 num_fregs
= n_fregs
;
2082 apparent_fsize
+= (outgoing_args_size
+7) & -8;
2083 if (leaf_function
&& n_fregs
== 0
2084 && apparent_fsize
== (REG_PARM_STACK_SPACE (current_function_decl
)
2085 - STARTING_FRAME_OFFSET
))
2088 actual_fsize
= apparent_fsize
+ n_fregs
*4;
2090 /* Make sure nothing can clobber our register windows.
2091 If a SAVE must be done, or there is a stack-local variable,
2092 the register window area must be allocated. */
2093 if (leaf_function
== 0 || size
> 0)
2094 actual_fsize
+= (16 * UNITS_PER_WORD
)+8;
2096 return actual_fsize
;
2099 /* Output code for the function prologue. */
2102 output_function_prologue (file
, size
, leaf_function
)
2108 frame_base_name
= "%sp+80";
2110 frame_base_name
= "%fp";
2112 /* Need to use actual_fsize, since we are also allocating
2113 space for our callee (and our own register save area). */
2114 actual_fsize
= compute_frame_size (size
, leaf_function
);
2116 fprintf (file
, "\t!#PROLOGUE# 0\n");
2117 if (actual_fsize
== 0)
2119 else if (actual_fsize
<= 4096)
2121 if (! leaf_function
)
2122 fprintf (file
, "\tsave %%sp,-%d,%%sp\n", actual_fsize
);
2124 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
);
2126 else if (actual_fsize
<= 8192)
2128 /* For frames in the range 4097..8192, we can use just two insns. */
2129 if (! leaf_function
)
2131 fprintf (file
, "\tsave %%sp,-4096,%%sp\n");
2132 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
- 4096);
2136 fprintf (file
, "\tadd %%sp,-4096,%%sp\n");
2137 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
- 4096);
2142 if (! leaf_function
)
2144 fprintf (file
, "\tsethi %%hi(-%d),%%g1\n", actual_fsize
);
2145 if ((actual_fsize
& 0x3ff) != 0)
2146 fprintf (file
, "\tor %%g1,%%lo(-%d),%%g1\n", actual_fsize
);
2147 fprintf (file
, "\tsave %%sp,%%g1,%%sp\n");
2151 fprintf (file
, "\tsethi %%hi(-%d),%%g1\n", actual_fsize
);
2152 if ((actual_fsize
& 0x3ff) != 0)
2153 fprintf (file
, "\tor %%g1,%%lo(-%d),%%g1\n", actual_fsize
);
2154 fprintf (file
, "\tadd %%sp,%%g1,%%sp\n");
2158 /* If doing anything with PIC, do it now. */
2160 fprintf (file
, "\t!#PROLOGUE# 1\n");
2162 /* Figure out where to save any special registers. */
2165 int offset
, n_fregs
= num_fregs
;
2167 if (! leaf_function
)
2168 offset
= -apparent_fsize
;
2172 if (TARGET_EPILOGUE
&& ! leaf_function
)
2173 n_fregs
= save_regs (file
, 0, 16, frame_base_name
, offset
, 0);
2174 else if (leaf_function
)
2175 n_fregs
= save_regs (file
, 0, 32, frame_base_name
, offset
, 0);
2176 if (TARGET_EPILOGUE
)
2177 save_regs (file
, 32, FIRST_PSEUDO_REGISTER
,
2178 frame_base_name
, offset
, n_fregs
);
2181 if (regs_ever_live
[62])
2182 fprintf (file
, "\tst %s,[%s-16]\n\tst %s,[%s-12]\n",
2183 reg_names
[0], frame_base_name
,
2184 reg_names
[0], frame_base_name
);
2187 if (leaf_function
&& actual_fsize
!= 0)
2189 /* warning ("leaf procedure with frame size %d", actual_fsize); */
2190 if (! TARGET_EPILOGUE
)
2191 leaf_label
= gen_label_rtx ();
2195 /* Output code for the function epilogue. */
2198 output_function_epilogue (file
, size
, leaf_function
)
2208 emit_label_after (leaf_label
, get_last_insn ());
2209 final_scan_insn (get_last_insn (), file
, 0, 0, 1);
2214 int offset
, n_fregs
= num_fregs
;
2216 if (! leaf_function
)
2217 offset
= -apparent_fsize
;
2221 if (TARGET_EPILOGUE
&& ! leaf_function
)
2222 n_fregs
= restore_regs (file
, 0, 16, frame_base_name
, offset
, 0);
2223 else if (leaf_function
)
2224 n_fregs
= restore_regs (file
, 0, 32, frame_base_name
, offset
, 0);
2225 if (TARGET_EPILOGUE
)
2226 restore_regs (file
, 32, FIRST_PSEUDO_REGISTER
,
2227 frame_base_name
, offset
, n_fregs
);
2230 /* Work out how to skip the caller's unimp instruction if required. */
2232 ret
= (current_function_returns_struct
? "jmp %o7+12" : "retl");
2234 ret
= (current_function_returns_struct
? "jmp %i7+12" : "ret");
2236 if (TARGET_EPILOGUE
|| leaf_label
)
2238 int old_target_epilogue
= TARGET_EPILOGUE
;
2239 target_flags
&= ~old_target_epilogue
;
2241 if (! leaf_function
)
2243 /* If we wound up with things in our delay slot, flush them here. */
2244 if (current_function_epilogue_delay_list
)
2246 rtx insn
= emit_jump_insn_after (gen_rtx (RETURN
, VOIDmode
),
2248 PATTERN (insn
) = gen_rtx (PARALLEL
, VOIDmode
,
2250 PATTERN (XEXP (current_function_epilogue_delay_list
, 0)),
2252 final_scan_insn (insn
, file
, 1, 0, 1);
2255 fprintf (file
, "\t%s\n\trestore\n", ret
);
2257 /* All of the following cases are for leaf functions. */
2258 else if (current_function_epilogue_delay_list
)
2260 /* eligible_for_epilogue_delay_slot ensures that if this is a
2261 leaf function, then we will only have insn in the delay slot
2262 if the frame size is zero, thus no adjust for the stack is
2264 if (actual_fsize
!= 0)
2266 fprintf (file
, "\t%s\n", ret
);
2267 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
2270 else if (actual_fsize
<= 4096)
2271 fprintf (file
, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret
, actual_fsize
);
2272 else if (actual_fsize
<= 8192)
2273 fprintf (file
, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n",
2274 ret
, actual_fsize
- 4096);
2275 else if ((actual_fsize
& 0x3ff) == 0)
2276 fprintf (file
, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
2279 fprintf (file
, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
2280 actual_fsize
, actual_fsize
, ret
);
2281 target_flags
|= old_target_epilogue
;
2285 /* Return the string to output a conditional branch to LABEL, which is
2286 the operand number of the label. OP is the conditional expression. The
2287 mode of register 0 says what kind of comparison we made.
2289 REVERSED is non-zero if we should reverse the sense of the comparison.
2291 ANNUL is non-zero if we should generate an annulling branch.
2293 NOOP is non-zero if we have to follow this branch by a noop. */
2296 output_cbranch (op
, label
, reversed
, annul
, noop
)
2299 int reversed
, annul
, noop
;
2301 static char string
[20];
2302 enum rtx_code code
= GET_CODE (op
);
2303 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
2304 static char labelno
[] = " %lX";
2306 /* ??? FP branches can not be preceded by another floating point insn.
2307 Because there is currently no concept of pre-delay slots, we can fix
2308 this only by always emitting a nop before a floating point branch. */
2310 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
2311 strcpy (string
, "nop\n\t");
2313 /* If not floating-point or if EQ or NE, we can just reverse the code. */
2315 && ((mode
!= CCFPmode
&& mode
!= CCFPEmode
) || code
== EQ
|| code
== NE
))
2316 code
= reverse_condition (code
), reversed
= 0;
2318 /* Start by writing the branch condition. */
2322 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
2323 strcat (string
, "fbne");
2325 strcpy (string
, "bne");
2329 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
2330 strcat (string
, "fbe");
2332 strcpy (string
, "be");
2336 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
2339 strcat (string
, "fbul");
2341 strcat (string
, "fbge");
2343 else if (mode
== CC_NOOVmode
)
2344 strcpy (string
, "bpos");
2346 strcpy (string
, "bge");
2350 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
2353 strcat (string
, "fbule");
2355 strcat (string
, "fbg");
2358 strcpy (string
, "bg");
2362 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
2365 strcat (string
, "fbug");
2367 strcat (string
, "fble");
2370 strcpy (string
, "ble");
2374 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
2377 strcat (string
, "fbuge");
2379 strcat (string
, "fbl");
2381 else if (mode
== CC_NOOVmode
)
2382 strcpy (string
, "bneg");
2384 strcpy (string
, "bl");
2388 strcpy (string
, "bgeu");
2392 strcpy (string
, "bgu");
2396 strcpy (string
, "bleu");
2400 strcpy (string
, "blu");
2404 /* Now add the annulling, the label, and a possible noop. */
2406 strcat (string
, ",a");
2408 labelno
[3] = label
+ '0';
2409 strcat (string
, labelno
);
2412 strcat (string
, "\n\tnop");
2417 /* Output assembler code to return from a function. */
2420 output_return (operands
)
2425 operands
[0] = leaf_label
;
2428 else if (leaf_function
)
2430 /* If we didn't allocate a frame pointer for the current function,
2431 the stack pointer might have been adjusted. Output code to
2434 operands
[0] = gen_rtx (CONST_INT
, VOIDmode
, actual_fsize
);
2436 /* Use sub of negated value in first two cases instead of add to
2437 allow actual_fsize == 4096. */
2439 if (actual_fsize
<= 4096)
2441 if (current_function_returns_struct
)
2442 return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp";
2444 return "retl\n\tsub %%sp,-%0,%%sp";
2446 else if (actual_fsize
<= 8192)
2448 operands
[0] = gen_rtx (CONST_INT
, VOIDmode
, actual_fsize
- 4096);
2449 if (current_function_returns_struct
)
2450 return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp";
2452 return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp";
2454 else if (current_function_returns_struct
)
2456 if ((actual_fsize
& 0x3ff) != 0)
2457 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
2459 return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
2463 if ((actual_fsize
& 0x3ff) != 0)
2464 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
2466 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
2471 if (current_function_returns_struct
)
2472 return "jmp %%i7+12\n\trestore";
2474 return "ret\n\trestore";
2478 /* Output assembler code for a SImode to SFmode conversion. */
2481 output_floatsisf2 (operands
)
2484 if (GET_CODE (operands
[1]) == MEM
)
2485 return "ld %1,%0\n\tfitos %0,%0";
2486 else if (FP_REG_P (operands
[1]))
2487 return "fitos %1,%0";
2488 return "st %r1,[%%fp-4]\n\tld [%%fp-4],%0\n\tfitos %0,%0";
2491 /* Output assembler code for a SImode to DFmode conversion. */
2494 output_floatsidf2 (operands
)
2497 if (GET_CODE (operands
[1]) == MEM
)
2498 return "ld %1,%0\n\tfitod %0,%0";
2499 else if (FP_REG_P (operands
[1]))
2500 return "fitod %1,%0";
2501 return "st %r1,[%%fp-4]\n\tld [%%fp-4],%0\n\tfitod %0,%0";
2504 /* Output assembler code for a SImode to TFmode conversion. */
2507 output_floatsitf2 (operands
)
2510 if (GET_CODE (operands
[1]) == MEM
)
2511 return "ld %1,%0\n\tfitoq %0,%0";
2512 else if (FP_REG_P (operands
[1]))
2513 return "fitoq %1,%0";
2514 return "st %r1,[%%fp-4]\n\tld [%%fp-4],%0\n\tfitoq %0,%0";
2517 /* Leaf functions and non-leaf functions have different needs. */
2520 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
2523 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
2525 static int *reg_alloc_orders
[] = {
2526 reg_leaf_alloc_order
,
2527 reg_nonleaf_alloc_order
};
2530 order_regs_for_local_alloc ()
2532 static int last_order_nonleaf
= 1;
2534 if (regs_ever_live
[15] != last_order_nonleaf
)
2536 last_order_nonleaf
= !last_order_nonleaf
;
2537 bcopy (reg_alloc_orders
[last_order_nonleaf
], reg_alloc_order
,
2538 FIRST_PSEUDO_REGISTER
* sizeof (int));
2542 /* Machine dependent routines for the branch probability, arc profiling
2545 /* The label used by the arc profiling code. */
2547 static rtx profiler_label
;
2550 init_arc_profiler ()
2552 /* Generate and save a copy of this so it can be shared. */
2553 profiler_label
= gen_rtx (SYMBOL_REF
, Pmode
, "*LPBX2");
2557 output_arc_profiler (arcno
, insert_after
)
2561 rtx profiler_target_addr
2562 = gen_rtx (CONST
, Pmode
,
2563 gen_rtx (PLUS
, Pmode
, profiler_label
,
2564 gen_rtx (CONST_INT
, VOIDmode
, 4 * arcno
)));
2565 register rtx profiler_reg
= gen_reg_rtx (SImode
);
2566 register rtx address_reg
= gen_reg_rtx (Pmode
);
2569 insert_after
= emit_insn_after (gen_rtx (SET
, VOIDmode
, address_reg
,
2570 gen_rtx (HIGH
, Pmode
,
2571 profiler_target_addr
)),
2574 mem_ref
= gen_rtx (MEM
, SImode
, gen_rtx (LO_SUM
, Pmode
, address_reg
,
2575 profiler_target_addr
));
2576 insert_after
= emit_insn_after (gen_rtx (SET
, VOIDmode
, profiler_reg
,
2580 insert_after
= emit_insn_after (gen_rtx (SET
, VOIDmode
, profiler_reg
,
2581 gen_rtx (PLUS
, SImode
, profiler_reg
,
2585 /* This is the same rtx as above, but it is not legal to share this rtx. */
2586 mem_ref
= gen_rtx (MEM
, SImode
, gen_rtx (LO_SUM
, Pmode
, address_reg
,
2587 profiler_target_addr
));
2588 emit_insn_after (gen_rtx (SET
, VOIDmode
, mem_ref
, profiler_reg
),
2592 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
2593 This makes them candidates for using ldd and std insns.
2595 Note reg1 and reg2 *must* be hard registers. To be sure we will
2596 abort if we are passed pseudo registers. */
2599 registers_ok_for_ldd (reg1
, reg2
)
2603 /* We might have been passed a SUBREG. */
2604 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
2607 /* Should never happen. */
2608 if (REGNO (reg1
) > FIRST_PSEUDO_REGISTER
2609 || REGNO (reg2
) > FIRST_PSEUDO_REGISTER
)
2612 if (REGNO (reg1
) % 2 != 0)
2615 return (REGNO (reg1
) == REGNO (reg2
) - 1);
2619 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
2622 This can only happen when addr1 and addr2 are consecutive memory
2623 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
2624 64 bit boundary (addr1 % 8 == 0).
2626 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
2627 registers are assumed to *never* be properly aligned and are
2630 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
2631 need only check that the offset for addr1 % 8 == 0. */
2634 memory_ok_for_ldd (addr1
, addr2
)
2639 /* Extract a register number and offset (if used) from the first addr. */
2640 if (GET_CODE (addr1
) == PLUS
)
2642 /* If not a REG, return zero. */
2643 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
2647 reg1
= REGNO (XEXP (addr1
, 0));
2648 /* The offset must be constant! */
2649 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
2651 offset1
= INTVAL (XEXP (addr1
, 1));
2654 else if (GET_CODE (addr1
) != REG
)
2658 reg1
= REGNO (addr1
);
2659 /* This was a simple (mem (reg)) expression. Offset is 0. */
2663 /* Make sure the second address is a (mem (plus (reg) (const_int). */
2664 if (GET_CODE (addr2
) != PLUS
)
2667 if (GET_CODE (XEXP (addr2
, 0)) != REG
2668 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
2671 /* Only %fp and %sp are allowed. Additionally both addresses must
2672 use the same register. */
2673 if (reg1
!= FRAME_POINTER_REGNUM
&& reg1
!= STACK_POINTER_REGNUM
)
2676 if (reg1
!= REGNO (XEXP (addr2
, 0)))
2679 /* The first offset must be evenly divisible by 8 to ensure the
2680 address is 64 bit aligned. */
2681 if (offset1
% 8 != 0)
2684 /* The offset for the second addr must be 4 more than the first addr. */
2685 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
2688 /* All the tests passed. addr1 and addr2 are valid for ldd and std
2693 /* Print operand X (an rtx) in assembler syntax to file FILE.
2694 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2695 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2698 print_operand (file
, x
, code
)
2706 /* Output a 'nop' if there's nothing for the delay slot. */
2707 if (dbr_sequence_length () == 0)
2708 fputs ("\n\tnop", file
);
2711 /* Output an annul flag if there's nothing for the delay slot and we
2712 are optimizing. This is always used with '(' below. */
2713 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
2714 this is a dbx bug. So, we only do this when optimizing. */
2715 if (dbr_sequence_length () == 0 && optimize
)
2719 /* Output a 'nop' if there's nothing for the delay slot and we are
2720 not optimizing. This is always used with '*' above. */
2721 if (dbr_sequence_length () == 0 && ! optimize
)
2722 fputs ("\n\tnop", file
);
2725 /* Adjust the operand to take into account a RESTORE operation. */
2726 if (GET_CODE (x
) != REG
)
2729 fputs (reg_names
[REGNO (x
)], file
);
2730 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
2731 fputs (reg_names
[REGNO (x
)-16], file
);
2736 /* Print out what we are using as the frame pointer. This might
2737 be %fp, or might be %sp+offset. */
2738 fputs (frame_base_name
, file
);
2741 /* Print out the second register name of a register pair or quad.
2742 I.e., R (%o0) => %o1. */
2743 fputs (reg_names
[REGNO (x
)+1], file
);
2746 /* Print out the third register name of a register quad.
2747 I.e., S (%o0) => %o2. */
2748 fputs (reg_names
[REGNO (x
)+2], file
);
2751 /* Print out the fourth register name of a register quad.
2752 I.e., T (%o0) => %o3. */
2753 fputs (reg_names
[REGNO (x
)+3], file
);
2756 /* Print the operand's address only. */
2757 output_address (XEXP (x
, 0));
2760 /* In this case we need a register. Use %g0 if the
2761 operand is const0_rtx. */
2763 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
2765 fputs ("%g0", file
);
2772 switch (GET_CODE (x
))
2774 case IOR
: fputs ("or", file
); break;
2775 case AND
: fputs ("and", file
); break;
2776 case XOR
: fputs ("xor", file
); break;
2782 switch (GET_CODE (x
))
2784 case IOR
: fputs ("orn", file
); break;
2785 case AND
: fputs ("andn", file
); break;
2786 case XOR
: fputs ("xnor", file
); break;
2793 /* Print a sign-extended character. */
2794 int i
= INTVAL (x
) & 0xff;
2797 fprintf (file
, "%d", i
);
2802 /* Do nothing special. */
2806 /* Undocumented flag. */
2810 if (GET_CODE (x
) == REG
)
2811 fputs (reg_names
[REGNO (x
)], file
);
2812 else if (GET_CODE (x
) == MEM
)
2815 if (CONSTANT_P (XEXP (x
, 0)))
2816 /* Poor Sun assembler doesn't understand absolute addressing. */
2817 fputs ("%g0+", file
);
2818 output_address (XEXP (x
, 0));
2821 else if (GET_CODE (x
) == HIGH
)
2823 fputs ("%hi(", file
);
2824 output_addr_const (file
, XEXP (x
, 0));
2827 else if (GET_CODE (x
) == LO_SUM
)
2829 print_operand (file
, XEXP (x
, 0), 0);
2830 fputs ("+%lo(", file
);
2831 output_addr_const (file
, XEXP (x
, 1));
2834 else if (GET_CODE (x
) == CONST_DOUBLE
)
2836 if (CONST_DOUBLE_HIGH (x
) == 0)
2837 fprintf (file
, "%u", CONST_DOUBLE_LOW (x
));
2838 else if (CONST_DOUBLE_HIGH (x
) == -1
2839 && CONST_DOUBLE_LOW (x
) < 0)
2840 fprintf (file
, "%d", CONST_DOUBLE_LOW (x
));
2844 else { output_addr_const (file
, x
); }
2847 /* This function outputs assembler code for VALUE to FILE, where VALUE is
2848 a 64 bit (DImode) value. */
2850 /* ??? If there is a 64 bit counterpart to .word that the assembler
2851 understands, then using that would simply this code greatly. */
2854 output_double_int (file
, value
)
2858 if (GET_CODE (value
) == CONST_INT
)
2860 if (INTVAL (value
) < 0)
2861 ASM_OUTPUT_INT (file
, constm1_rtx
);
2863 ASM_OUTPUT_INT (file
, const0_rtx
);
2864 ASM_OUTPUT_INT (file
, value
);
2866 else if (GET_CODE (value
) == CONST_DOUBLE
)
2868 ASM_OUTPUT_INT (file
, gen_rtx (CONST_INT
, VOIDmode
,
2869 CONST_DOUBLE_HIGH (value
)));
2870 ASM_OUTPUT_INT (file
, gen_rtx (CONST_INT
, VOIDmode
,
2871 CONST_DOUBLE_LOW (value
)));
2873 else if (GET_CODE (value
) == SYMBOL_REF
2874 || GET_CODE (value
) == CONST
2875 || GET_CODE (value
) == PLUS
)
2877 /* Addresses are only 32 bits. */
2878 ASM_OUTPUT_INT (file
, const0_rtx
);
2879 ASM_OUTPUT_INT (file
, value
);
2885 #ifndef CHAR_TYPE_SIZE
2886 #define CHAR_TYPE_SIZE BITS_PER_UNIT
2889 #ifndef SHORT_TYPE_SIZE
2890 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
2893 #ifndef INT_TYPE_SIZE
2894 #define INT_TYPE_SIZE BITS_PER_WORD
2897 #ifndef LONG_TYPE_SIZE
2898 #define LONG_TYPE_SIZE BITS_PER_WORD
2901 #ifndef LONG_LONG_TYPE_SIZE
2902 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
2905 #ifndef FLOAT_TYPE_SIZE
2906 #define FLOAT_TYPE_SIZE BITS_PER_WORD
2909 #ifndef DOUBLE_TYPE_SIZE
2910 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
2913 #ifndef LONG_DOUBLE_TYPE_SIZE
2914 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
2918 sparc_type_code (type
)
2921 register unsigned long qualifiers
= 0;
2922 register unsigned shift
= 6;
2926 switch (TREE_CODE (type
))
2932 qualifiers
|= (3 << shift
);
2934 type
= TREE_TYPE (type
);
2939 qualifiers
|= (2 << shift
);
2941 type
= TREE_TYPE (type
);
2945 case REFERENCE_TYPE
:
2947 qualifiers
|= (1 << shift
);
2949 type
= TREE_TYPE (type
);
2953 return (qualifiers
| 8);
2956 return (qualifiers
| 9);
2959 return (qualifiers
| 10);
2962 return (qualifiers
| 16);
2965 /* Carefully distinguish all the standard types of C,
2966 without messing up if the language is not C.
2967 Note that we check only for the names that contain spaces;
2968 other names might occur by coincidence in other languages. */
2969 if (TYPE_NAME (type
) != 0
2970 && TREE_CODE (TYPE_NAME (type
)) == TYPE_DECL
2971 && DECL_NAME (TYPE_NAME (type
)) != 0
2972 && TREE_CODE (DECL_NAME (TYPE_NAME (type
))) == IDENTIFIER_NODE
)
2974 char *name
= IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type
)));
2976 if (!strcmp (name
, "unsigned char"))
2977 return (qualifiers
| 12);
2978 if (!strcmp (name
, "signed char"))
2979 return (qualifiers
| 2);
2980 if (!strcmp (name
, "unsigned int"))
2981 return (qualifiers
| 14);
2982 if (!strcmp (name
, "short int"))
2983 return (qualifiers
| 3);
2984 if (!strcmp (name
, "short unsigned int"))
2985 return (qualifiers
| 13);
2986 if (!strcmp (name
, "long int"))
2987 return (qualifiers
| 5);
2988 if (!strcmp (name
, "long unsigned int"))
2989 return (qualifiers
| 15);
2990 if (!strcmp (name
, "long long int"))
2991 return (qualifiers
| 5); /* Who knows? */
2992 if (!strcmp (name
, "long long unsigned int"))
2993 return (qualifiers
| 15); /* Who knows? */
2996 /* Most integer types will be sorted out above, however, for the
2997 sake of special `array index' integer types, the following code
2998 is also provided. */
3000 if (TYPE_PRECISION (type
) == INT_TYPE_SIZE
)
3001 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
3003 if (TYPE_PRECISION (type
) == LONG_TYPE_SIZE
)
3004 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
3006 if (TYPE_PRECISION (type
) == LONG_LONG_TYPE_SIZE
)
3007 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
3009 if (TYPE_PRECISION (type
) == SHORT_TYPE_SIZE
)
3010 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
3012 if (TYPE_PRECISION (type
) == CHAR_TYPE_SIZE
)
3013 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
3018 /* Carefully distinguish all the standard types of C,
3019 without messing up if the language is not C. */
3020 if (TYPE_NAME (type
) != 0
3021 && TREE_CODE (TYPE_NAME (type
)) == TYPE_DECL
3022 && DECL_NAME (TYPE_NAME (type
)) != 0
3023 && TREE_CODE (DECL_NAME (TYPE_NAME (type
))) == IDENTIFIER_NODE
)
3025 char *name
= IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type
)));
3027 if (!strcmp (name
, "long double"))
3028 return (qualifiers
| 7); /* Who knows? */
3031 if (TYPE_PRECISION (type
) == DOUBLE_TYPE_SIZE
)
3032 return (qualifiers
| 7);
3033 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
3034 return (qualifiers
| 6);
3035 if (TYPE_PRECISION (type
) == LONG_DOUBLE_TYPE_SIZE
)
3036 return (qualifiers
| 7); /* Who knows? */
3039 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
3040 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
3041 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
3042 case FILE_TYPE
: /* GNU Pascal FILE type. */
3043 case STRING_TYPE
: /* GNU Fortran STRING type. */
3044 case LANG_TYPE
: /* ? */
3048 abort (); /* Not a type! */
3053 #ifdef HANDLE_PRAGMA
3055 /* Handle a pragma directive. HANDLE_PRAGMA conspires to parse the
3056 input following #pragma into tokens based on yylex. TOKEN is the
3057 current token, and STRING is its printable form. */
3060 handle_pragma_token (string
, token
)
3064 static enum pragma_state
3073 } state
= ps_start
, type
;
3081 if (type
== ps_weak
)
3083 if (state
== ps_name
|| state
== ps_value
)
3085 fprintf (asm_out_file
, "\t%s\t", WEAK_ASM_OP
);
3086 ASM_OUTPUT_LABELREF (asm_out_file
, name
);
3087 fputc ('\n', asm_out_file
);
3088 if (state
== ps_value
)
3090 fputc ('\t', asm_out_file
);
3091 ASM_OUTPUT_LABELREF (asm_out_file
, name
);
3092 fputs (" = ", asm_out_file
);
3093 ASM_OUTPUT_LABELREF (asm_out_file
, value
);
3094 fputc ('\n', asm_out_file
);
3097 else if (! (state
== ps_done
|| state
== ps_start
))
3098 warning ("ignoring malformed #pragma weak symbol [=value]");
3100 #endif /* WEAK_ASM_OP */
3102 type
= state
= ps_start
;
3109 if (token
&& TREE_CODE (token
) == IDENTIFIER_NODE
)
3112 if (strcmp (IDENTIFIER_POINTER (token
), "weak") == 0)
3113 type
= state
= ps_weak
;
3116 type
= state
= ps_done
;
3119 type
= state
= ps_done
;
3124 if (token
&& TREE_CODE (token
) == IDENTIFIER_NODE
)
3126 name
= IDENTIFIER_POINTER (token
);
3134 state
= (strcmp (string
, "=") ? ps_bad
: ps_equals
);
3138 if (token
&& TREE_CODE (token
) == IDENTIFIER_NODE
)
3140 value
= IDENTIFIER_POINTER (token
);
3150 #endif /* WEAK_ASM_OP */
3160 #endif /* HANDLE_PRAGMA */
3162 /* Subroutines to support a flat (single) register window calling
3165 /* Single-register window sparc stack frames look like:
3167 Before call After call
3168 +-----------------------+ +-----------------------+
3171 | caller's temps. | | caller's temps. |
3173 +-----------------------+ +-----------------------+
3175 | arguments on stack. | | arguments on stack. |
3177 +-----------------------+ +-----------------------+
3178 | 6 words to save | | 6 words to save |
3179 | arguments passed | | arguments passed |
3180 | in registers, even | | in registers, even |
3181 SP+68->| if not passed. |FP+68->| if not passed. |
3182 +-----------------------+ +-----------------------+
3183 | 1 word struct addr |FP+64->| 1 word struct addr |
3184 +-----------------------+ +-----------------------+
3186 | 16 word reg save area | | 16 word reg save area |
3188 +-----------------------+ +-----------------------+
3190 FP-16->| fp/alu reg moves |
3191 +-----------------------+
3195 +-----------------------+
3197 | fp register save |
3199 +-----------------------+
3201 | gp register save |
3203 +-----------------------+
3205 | alloca allocations |
3207 +-----------------------+
3209 | arguments on stack |
3211 +-----------------------+
3213 | arguments passed |
3214 | in registers, even |
3215 low SP+68->| if not passed. |
3216 memory +-----------------------+
3217 SP+64->| 1 word struct addr |
3218 +-----------------------+
3220 I 16 word reg save area |
3222 +-----------------------+ */
3224 /* Structure to be filled in by sparc_frw_compute_frame_size with register
3225 save masks, and offsets for the current function. */
3227 struct sparc_frame_info
3229 unsigned long total_size
; /* # bytes that the entire frame takes up. */
3230 unsigned long var_size
; /* # bytes that variables take up. */
3231 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
3232 unsigned long extra_size
; /* # bytes of extra gunk. */
3233 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
3234 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
3235 unsigned long mask
; /* Mask of saved gp registers. */
3236 unsigned long fmask
; /* Mask of saved fp registers. */
3237 unsigned long gp_sp_offset
; /* Offset from new sp to store gp regs. */
3238 unsigned long fp_sp_offset
; /* Offset from new sp to store fp regs. */
3239 int initialized
; /* Nonzero if frame size already calculated. */
3242 /* Current frame information calculated by sparc_frw_compute_frame_size. */
3243 struct sparc_frame_info current_frame_info
;
3245 /* Zero structure to initialize current_frame_info. */
3246 struct sparc_frame_info zero_frame_info
;
3248 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
3250 #define MUST_SAVE_REGISTER(regno) \
3251 ((regs_ever_live[regno] && !call_used_regs[regno]) \
3252 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
3253 || (regno == 15 && regs_ever_live[15]))
3255 #ifndef SPARC_STACK_ALIGN
3256 #define STACK_BYTES (STACK_BOUNDARY / 8)
3257 #define SPARC_STACK_ALIGN(X) (((X) + STACK_BYTES - 1) & -STACK_BYTES)
3260 /* Return the bytes needed to compute the frame pointer from the current
3264 sparc_frw_compute_frame_size (size
)
3265 int size
; /* # of var. bytes allocated. */
3268 unsigned long total_size
; /* # bytes that the entire frame takes up. */
3269 unsigned long var_size
; /* # bytes that variables take up. */
3270 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
3271 unsigned long extra_size
; /* # extra bytes. */
3272 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
3273 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
3274 unsigned long mask
; /* Mask of saved gp registers. */
3275 unsigned long fmask
; /* Mask of saved fp registers. */
3277 /* This is the size of the 16 word reg save area, 1 word struct addr
3278 area, and 4 word fp/alu register copy area. */
3279 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
3281 /* Also include the size needed for the 6 parameter registers. */
3282 args_size
= current_function_outgoing_args_size
+ 24;
3283 total_size
= var_size
+ args_size
+ extra_size
;
3289 /* Calculate space needed for gp registers. */
3290 for (regno
= 1; regno
<= 31; regno
++)
3292 if (MUST_SAVE_REGISTER (regno
))
3294 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
3296 if (gp_reg_size
% 8 != 0)
3297 gp_reg_size
+= UNITS_PER_WORD
;
3298 gp_reg_size
+= 2 * UNITS_PER_WORD
;
3304 gp_reg_size
+= UNITS_PER_WORD
;
3309 /* Add extra word in case we have to align the space to a double word
3311 if (gp_reg_size
!= 0)
3312 gp_reg_size
+= UNITS_PER_WORD
;
3314 /* Calculate space needed for fp registers. */
3315 for (regno
= 32; regno
<= 63; regno
++)
3317 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
3319 fp_reg_size
+= UNITS_PER_WORD
;
3320 fmask
|= 1 << (regno
- 32);
3324 total_size
+= gp_reg_size
+ fp_reg_size
;
3326 if (total_size
== extra_size
)
3327 total_size
= extra_size
= 0;
3329 total_size
= SPARC_STACK_ALIGN (total_size
);
3331 /* Save other computed information. */
3332 current_frame_info
.total_size
= total_size
;
3333 current_frame_info
.var_size
= var_size
;
3334 current_frame_info
.args_size
= args_size
;
3335 current_frame_info
.extra_size
= extra_size
;
3336 current_frame_info
.gp_reg_size
= gp_reg_size
;
3337 current_frame_info
.fp_reg_size
= fp_reg_size
;
3338 current_frame_info
.mask
= mask
;
3339 current_frame_info
.fmask
= fmask
;
3340 current_frame_info
.initialized
= reload_completed
;
3344 unsigned long offset
= args_size
;
3346 offset
+= FIRST_PARM_OFFSET(0);
3347 current_frame_info
.gp_sp_offset
= offset
;
3352 unsigned long offset
= args_size
+ gp_reg_size
;
3354 offset
+= FIRST_PARM_OFFSET(0);
3355 current_frame_info
.fp_sp_offset
= offset
;
3358 /* Ok, we're done. */
3362 /* Common code to save/restore registers. */
3365 sparc_frw_save_restore (file
, word_op
, doubleword_op
)
3366 FILE *file
; /* Stream to write to. */
3367 char *word_op
; /* Operation to do for one word. */
3368 char *doubleword_op
; /* Operation to do for doubleword. */
3371 unsigned long mask
= current_frame_info
.mask
;
3372 unsigned long fmask
= current_frame_info
.fmask
;
3373 unsigned long gp_offset
;
3374 unsigned long fp_offset
;
3375 unsigned long max_offset
;
3378 if (mask
== 0 && fmask
== 0)
3381 base_reg
= reg_names
[STACK_POINTER_REGNUM
];
3382 gp_offset
= current_frame_info
.gp_sp_offset
;
3383 fp_offset
= current_frame_info
.fp_sp_offset
;
3384 max_offset
= (gp_offset
> fp_offset
) ? gp_offset
: fp_offset
;
3386 /* Deal with calling functions with a large structure. */
3387 if (max_offset
>= 4096)
3390 fprintf (file
, "\tset %ld,%s\n", max_offset
, temp
);
3391 fprintf (file
, "\tadd %s,%s,%s\n", temp
, base_reg
, temp
);
3393 gp_offset
= max_offset
- gp_offset
;
3394 fp_offset
= max_offset
- fp_offset
;
3397 /* Save registers starting from high to low. The debuggers prefer
3398 at least the return register be stored at func+4, and also it
3399 allows us not to need a nop in the epilog if at least one
3400 register is reloaded in addition to return address. */
3402 if (mask
|| frame_pointer_needed
)
3404 for (regno
= 1; regno
<= 31; regno
++)
3406 if ((mask
& (1L << regno
)) != 0
3407 || (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
))
3409 if ((regno
& 0x1) == 0 && ((mask
& (1L << regno
+1)) != 0))
3411 if (gp_offset
% 8 != 0)
3412 gp_offset
+= UNITS_PER_WORD
;
3414 if (word_op
[0] == 's')
3415 fprintf (file
, "\t%s %s,[%s+%d]\n",
3416 doubleword_op
, reg_names
[regno
],
3417 base_reg
, gp_offset
);
3419 fprintf (file
, "\t%s [%s+%d],%s\n",
3420 doubleword_op
, base_reg
, gp_offset
,
3423 gp_offset
+= 2 * UNITS_PER_WORD
;
3428 if (word_op
[0] == 's')
3429 fprintf (file
, "\t%s %s,[%s+%d]\n",
3430 word_op
, reg_names
[regno
],
3431 base_reg
, gp_offset
);
3433 fprintf (file
, "\t%s [%s+%d],%s\n",
3434 word_op
, base_reg
, gp_offset
, reg_names
[regno
]);
3436 gp_offset
+= UNITS_PER_WORD
;
3444 for (regno
= 32; regno
<= 63; regno
++)
3446 if ((fmask
& (1L << (regno
- 32))) != 0)
3448 if (word_op
[0] == 's')
3449 fprintf (file
, "\t%s %s,[%s+%d]\n",
3450 word_op
, reg_names
[regno
],
3451 base_reg
, gp_offset
);
3453 fprintf (file
, "\t%s [%s+%d],%s\n",
3454 word_op
, base_reg
, gp_offset
, reg_names
[regno
]);
3456 fp_offset
+= UNITS_PER_WORD
;
3462 /* Set up the stack and frame (if desired) for the function. */
3465 sparc_frw_output_function_prologue (file
, size
, ignored
)
3469 extern char call_used_regs
[];
3472 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
3474 = (!frame_pointer_needed
) ? "%sp+64" : reg_names
[FRAME_POINTER_REGNUM
];
3476 fprintf (file
, "\t!#PROLOGUE# 0\n");
3478 size
= SPARC_STACK_ALIGN (size
);
3479 tsize
= (! current_frame_info
.initialized
3480 ? sparc_frw_compute_frame_size (size
)
3481 : current_frame_info
.total_size
);
3487 "\tsub %s,%d,%s\t\t!# vars= %d, regs= %d/%d, args = %d, extra= %d\n",
3488 sp_str
, tsize
, sp_str
, current_frame_info
.var_size
,
3489 current_frame_info
.gp_reg_size
/ 4,
3490 current_frame_info
.fp_reg_size
/ 8,
3491 current_function_outgoing_args_size
,
3492 current_frame_info
.extra_size
);
3495 "\tset %d,%s\n\tsub\t%s,%s,%s\t\t!# vars= %d, regs= %d/%d, args = %d, sfo= %d\n",
3496 tsize
, "%g1", sp_str
, "%g1",
3497 sp_str
, current_frame_info
.var_size
,
3498 current_frame_info
.gp_reg_size
/ 4,
3499 current_frame_info
.fp_reg_size
/ 8,
3500 current_function_outgoing_args_size
,
3501 current_frame_info
.extra_size
);
3504 sparc_frw_save_restore (file
, "st", "std");
3506 if (frame_pointer_needed
)
3509 fprintf (file
, "\tadd %s,%d,%s\t!# set up frame pointer\n", sp_str
,
3510 tsize
, frame_base_name
);
3512 fprintf (file
, "\tadd %s,%s,%s\t!# set up frame pointer\n", sp_str
,
3513 "%g1", frame_base_name
);
3517 /* Do any necessary cleanup after a function to restore stack, frame,
3521 sparc_frw_output_function_epilogue (file
, size
, ignored1
, ignored2
)
3525 extern FILE *asm_out_data_file
, *asm_out_file
;
3526 extern char call_used_regs
[];
3527 extern int frame_pointer_needed
;
3529 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
3530 char *t1_str
= "%g1";
3531 rtx epilogue_delay
= current_function_epilogue_delay_list
;
3532 int noepilogue
= FALSE
;
3533 int load_nop
= FALSE
;
3536 /* The epilogue does not depend on any registers, but the stack
3537 registers, so we assume that if we have 1 pending nop, it can be
3538 ignored, and 2 it must be filled (2 nops occur for integer
3539 multiply and divide). */
3541 size
= SPARC_STACK_ALIGN (size
);
3542 tsize
= (!current_frame_info
.initialized
3543 ? sparc_frw_compute_frame_size (size
)
3544 : current_frame_info
.total_size
);
3546 if (tsize
== 0 && epilogue_delay
== 0)
3548 rtx insn
= get_last_insn ();
3550 /* If the last insn was a BARRIER, we don't have to write any code
3551 because a jump (aka return) was put there. */
3552 if (GET_CODE (insn
) == NOTE
)
3553 insn
= prev_nonnote_insn (insn
);
3554 if (insn
&& GET_CODE (insn
) == BARRIER
)
3560 /* In the reload sequence, we don't need to fill the load delay
3561 slots for most of the loads, also see if we can fill the final
3562 delay slot if not otherwise filled by the reload sequence. */
3565 fprintf (file
, "\tset %d,%s\n", tsize
, t1_str
);
3567 if (frame_pointer_needed
)
3569 char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
3571 fprintf (file
,"\tsub %s,%s,%s\t\t!# sp not trusted here\n",
3572 fp_str
, t1_str
, sp_str
);
3574 fprintf (file
,"\tsub %s,%d,%s\t\t!# sp not trusted here\n",
3575 fp_str
, tsize
, sp_str
);
3578 sparc_frw_save_restore (file
, "ld", "ldd");
3580 load_only_r15
= (current_frame_info
.mask
== (1 << 15)
3581 && current_frame_info
.fmask
== 0);
3583 if (current_function_returns_struct
)
3584 fprintf (file
, "\tjmp %%o7+12\n");
3586 fprintf (file
, "\tretl\n");
3588 /* If the only register saved is the return address, we need a
3589 nop, unless we have an instruction to put into it. Otherwise
3590 we don't since reloading multiple registers doesn't reference
3591 the register being loaded. */
3597 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
3600 else if (tsize
> 4095)
3601 fprintf (file
, "\tadd %s,%s,%s\n", sp_str
, t1_str
, sp_str
);
3604 fprintf (file
, "\tadd %s,%d,%s\n", sp_str
, tsize
, sp_str
);
3607 fprintf (file
, "\tnop\n");
3610 /* Reset state info for each function. */
3611 current_frame_info
= zero_frame_info
;
3614 /* Define the number of delay slots needed for the function epilogue.
3616 On the sparc, we need a slot if either no stack has been allocated,
3617 or the only register saved is the return register. */
3620 sparc_frw_epilogue_delay_slots ()
3622 if (!current_frame_info
.initialized
)
3623 (void) sparc_frw_compute_frame_size (get_frame_size ());
3625 if (current_frame_info
.total_size
== 0)
3628 if (current_frame_info
.mask
== (1 << 15) && current_frame_info
.fmask
== 0)
3634 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
3635 Any single length instruction which doesn't reference the stack or frame
3639 sparc_frw_eligible_for_epilogue_delay (trial
, slot
)
3643 if (get_attr_length (trial
) == 1
3644 && ! reg_mentioned_p (stack_pointer_rtx
, PATTERN (trial
))
3645 && ! reg_mentioned_p (frame_pointer_rtx
, PATTERN (trial
)))