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[gcc.git] / gcc / config / sparc / sparc.c
1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4
5 This file is part of GNU CC.
6
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20
21 #include <stdio.h>
22 #include "config.h"
23 #include "tree.h"
24 #include "rtl.h"
25 #include "regs.h"
26 #include "hard-reg-set.h"
27 #include "real.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
31 #include "output.h"
32 #include "insn-attr.h"
33 #include "flags.h"
34 #include "expr.h"
35 #include "recog.h"
36
37 /* Global variables for machine-dependent things. */
38
39 /* Save the operands last given to a compare for use when we
40 generate a scc or bcc insn. */
41
42 rtx sparc_compare_op0, sparc_compare_op1;
43
44 /* We may need an epilogue if we spill too many registers.
45 If this is non-zero, then we branch here for the epilogue. */
46 static rtx leaf_label;
47
48 #ifdef LEAF_REGISTERS
49
50 /* Vector to say how input registers are mapped to output
51 registers. FRAME_POINTER_REGNUM cannot be remapped by
52 this function to eliminate it. You must use -fomit-frame-pointer
53 to get that. */
54 char leaf_reg_remap[] =
55 { 0, 1, 2, 3, 4, 5, 6, 7,
56 -1, -1, -1, -1, -1, -1, 14, -1,
57 -1, -1, -1, -1, -1, -1, -1, -1,
58 8, 9, 10, 11, 12, 13, -1, 15,
59
60 32, 33, 34, 35, 36, 37, 38, 39,
61 40, 41, 42, 43, 44, 45, 46, 47,
62 48, 49, 50, 51, 52, 53, 54, 55,
63 56, 57, 58, 59, 60, 61, 62, 63};
64
65 char leaf_reg_backmap[] =
66 { 0, 1, 2, 3, 4, 5, 6, 7,
67 24, 25, 26, 27, 28, 29, 14, 31,
68 -1, -1, -1, -1, -1, -1, -1, -1,
69 -1, -1, -1, -1, -1, -1, -1, -1,
70
71 32, 33, 34, 35, 36, 37, 38, 39,
72 40, 41, 42, 43, 44, 45, 46, 47,
73 48, 49, 50, 51, 52, 53, 54, 55,
74 56, 57, 58, 59, 60, 61, 62, 63};
75 #endif
76
77 /* Global variables set by FUNCTION_PROLOGUE. */
78 /* Size of frame. Need to know this to emit return insns from
79 leaf procedures. */
80 int apparent_fsize;
81 int actual_fsize;
82
83 /* Name of where we pretend to think the frame pointer points.
84 Normally, this is "%fp", but if we are in a leaf procedure,
85 this is "%sp+something". */
86 char *frame_base_name;
87
88 static rtx find_addr_reg ();
89
90 /* Return non-zero only if OP is a register of mode MODE,
91 or const0_rtx. */
92 int
93 reg_or_0_operand (op, mode)
94 rtx op;
95 enum machine_mode mode;
96 {
97 if (op == const0_rtx || register_operand (op, mode))
98 return 1;
99 if (GET_CODE (op) == CONST_DOUBLE
100 && CONST_DOUBLE_HIGH (op) == 0
101 && CONST_DOUBLE_LOW (op) == 0)
102 return 1;
103 return 0;
104 }
105
106 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
107 int
108 restore_operand (op, mode)
109 rtx op;
110 enum machine_mode mode;
111 {
112 return (GET_CODE (op) == REG && GET_MODE (op) == mode
113 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
114 }
115
116 /* Call insn on SPARC can take a PC-relative constant address, or any regular
117 memory address. */
118
119 int
120 call_operand (op, mode)
121 rtx op;
122 enum machine_mode mode;
123 {
124 if (GET_CODE (op) != MEM)
125 abort ();
126 op = XEXP (op, 0);
127 return (CONSTANT_P (op) || memory_address_p (Pmode, op));
128 }
129
130 int
131 call_operand_address (op, mode)
132 rtx op;
133 enum machine_mode mode;
134 {
135 return (CONSTANT_P (op) || memory_address_p (Pmode, op));
136 }
137
138 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
139 reference and a constant. */
140
141 int
142 symbolic_operand (op, mode)
143 register rtx op;
144 enum machine_mode mode;
145 {
146 switch (GET_CODE (op))
147 {
148 case SYMBOL_REF:
149 case LABEL_REF:
150 return 1;
151
152 case CONST:
153 op = XEXP (op, 0);
154 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
155 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
156 && GET_CODE (XEXP (op, 1)) == CONST_INT);
157
158 /* ??? This clause seems to be irrelevant. */
159 case CONST_DOUBLE:
160 return GET_MODE (op) == mode;
161
162 default:
163 return 0;
164 }
165 }
166
167 /* Return truth value of statement that OP is a symbolic memory
168 operand of mode MODE. */
169
170 int
171 symbolic_memory_operand (op, mode)
172 rtx op;
173 enum machine_mode mode;
174 {
175 if (GET_CODE (op) == SUBREG)
176 op = SUBREG_REG (op);
177 if (GET_CODE (op) != MEM)
178 return 0;
179 op = XEXP (op, 0);
180 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
181 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
182 }
183
184 /* Return 1 if the operand is either a register or a memory operand that is
185 not symbolic. */
186
187 int
188 reg_or_nonsymb_mem_operand (op, mode)
189 register rtx op;
190 enum machine_mode mode;
191 {
192 if (register_operand (op, mode))
193 return 1;
194
195 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
196 return 1;
197
198 return 0;
199 }
200
201 int
202 sparc_operand (op, mode)
203 rtx op;
204 enum machine_mode mode;
205 {
206 if (register_operand (op, mode))
207 return 1;
208 if (GET_CODE (op) == CONST_INT)
209 return SMALL_INT (op);
210 if (GET_MODE (op) != mode)
211 return 0;
212 if (GET_CODE (op) == SUBREG)
213 op = SUBREG_REG (op);
214 if (GET_CODE (op) != MEM)
215 return 0;
216
217 op = XEXP (op, 0);
218 if (GET_CODE (op) == LO_SUM)
219 return (GET_CODE (XEXP (op, 0)) == REG
220 && symbolic_operand (XEXP (op, 1), Pmode));
221 return memory_address_p (mode, op);
222 }
223
224 int
225 move_operand (op, mode)
226 rtx op;
227 enum machine_mode mode;
228 {
229 if (mode == DImode && arith_double_operand (op, mode))
230 return 1;
231 if (register_operand (op, mode))
232 return 1;
233 if (GET_CODE (op) == CONST_INT)
234 return (SMALL_INT (op) || (INTVAL (op) & 0x3ff) == 0);
235
236 if (GET_MODE (op) != mode)
237 return 0;
238 if (GET_CODE (op) == SUBREG)
239 op = SUBREG_REG (op);
240 if (GET_CODE (op) != MEM)
241 return 0;
242 op = XEXP (op, 0);
243 if (GET_CODE (op) == LO_SUM)
244 return (register_operand (XEXP (op, 0), Pmode)
245 && CONSTANT_P (XEXP (op, 1)));
246 return memory_address_p (mode, op);
247 }
248
249 int
250 move_pic_label (op, mode)
251 rtx op;
252 enum machine_mode mode;
253 {
254 /* Special case for PIC. */
255 if (flag_pic && GET_CODE (op) == LABEL_REF)
256 return 1;
257 return 0;
258 }
259 \f
260 /* The rtx for the global offset table which is a special form
261 that *is* a position independent symbolic constant. */
262 rtx pic_pc_rtx;
263
264 /* Ensure that we are not using patterns that are not OK with PIC. */
265
266 int
267 check_pic (i)
268 int i;
269 {
270 switch (flag_pic)
271 {
272 case 1:
273 if (GET_CODE (recog_operand[i]) == SYMBOL_REF
274 || (GET_CODE (recog_operand[i]) == CONST
275 && ! rtx_equal_p (pic_pc_rtx, recog_operand[i])))
276 abort ();
277 case 2:
278 default:
279 return 1;
280 }
281 }
282
283 /* Return true if X is an address which needs a temporary register when
284 reloaded while generating PIC code. */
285
286 int
287 pic_address_needs_scratch (x)
288 rtx x;
289 {
290 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
291 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
292 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
293 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
294 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
295 return 1;
296
297 return 0;
298 }
299
300 int
301 memop (op, mode)
302 rtx op;
303 enum machine_mode mode;
304 {
305 if (GET_CODE (op) == MEM)
306 return (mode == VOIDmode || mode == GET_MODE (op));
307 return 0;
308 }
309
310 /* Return truth value of whether OP is EQ or NE. */
311
312 int
313 eq_or_neq (op, mode)
314 rtx op;
315 enum machine_mode mode;
316 {
317 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
318 }
319
320 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
321 or LTU for non-floating-point. We handle those specially. */
322
323 int
324 normal_comp_operator (op, mode)
325 rtx op;
326 enum machine_mode mode;
327 {
328 enum rtx_code code = GET_CODE (op);
329
330 if (GET_RTX_CLASS (code) != '<')
331 return 0;
332
333 if (GET_MODE (XEXP (op, 0)) == CCFPmode
334 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
335 return 1;
336
337 return (code != NE && code != EQ && code != GEU && code != LTU);
338 }
339
340 /* Return 1 if this is a comparison operator. This allows the use of
341 MATCH_OPERATOR to recognize all the branch insns. */
342
343 int
344 noov_compare_op (op, mode)
345 register rtx op;
346 enum machine_mode mode;
347 {
348 enum rtx_code code = GET_CODE (op);
349
350 if (GET_RTX_CLASS (code) != '<')
351 return 0;
352
353 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode)
354 /* These are the only branches which work with CC_NOOVmode. */
355 return (code == EQ || code == NE || code == GE || code == LT);
356 return 1;
357 }
358
359 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
360
361 int
362 extend_op (op, mode)
363 rtx op;
364 enum machine_mode mode;
365 {
366 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
367 }
368
369 /* Return nonzero if OP is an operator of mode MODE which can set
370 the condition codes explicitly. We do not include PLUS and MINUS
371 because these require CC_NOOVmode, which we handle explicitly. */
372
373 int
374 cc_arithop (op, mode)
375 rtx op;
376 enum machine_mode mode;
377 {
378 if (GET_CODE (op) == AND
379 || GET_CODE (op) == IOR
380 || GET_CODE (op) == XOR)
381 return 1;
382
383 return 0;
384 }
385
386 /* Return nonzero if OP is an operator of mode MODE which can bitwise
387 complement its second operand and set the condition codes explicitly. */
388
389 int
390 cc_arithopn (op, mode)
391 rtx op;
392 enum machine_mode mode;
393 {
394 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
395 and (xor ... (not ...)) to (not (xor ...)). */
396 return (GET_CODE (op) == AND
397 || GET_CODE (op) == IOR);
398 }
399 \f
400 /* Return true if OP is a register, or is a CONST_INT that can fit in a 13
401 bit immediate field. This is an acceptable SImode operand for most 3
402 address instructions. */
403
404 int
405 arith_operand (op, mode)
406 rtx op;
407 enum machine_mode mode;
408 {
409 return (register_operand (op, mode)
410 || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
411 }
412
413 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
414 can fit in a 13 bit immediate field. This is an acceptable DImode operand
415 for most 3 address instructions. */
416
417 int
418 arith_double_operand (op, mode)
419 rtx op;
420 enum machine_mode mode;
421 {
422 return (register_operand (op, mode)
423 || (GET_CODE (op) == CONST_DOUBLE
424 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
425 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
426 && ((CONST_DOUBLE_HIGH (op) == -1
427 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
428 || (CONST_DOUBLE_HIGH (op) == 0
429 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0)))
430 || (GET_CODE (op) == CONST_INT
431 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
432 && (unsigned) (INTVAL (op) + 0x1000) < 0x2000));
433 }
434
435 /* Return truth value of whether OP is a integer which fits the
436 range constraining immediate operands in most three-address insns,
437 which have a 13 bit immediate field. */
438
439 int
440 small_int (op, mode)
441 rtx op;
442 enum machine_mode mode;
443 {
444 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
445 }
446
447 /* Return truth value of statement that OP is a call-clobbered register. */
448 int
449 clobbered_register (op, mode)
450 rtx op;
451 enum machine_mode mode;
452 {
453 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
454 }
455 \f
456 /* X and Y are two things to compare using CODE. Emit the compare insn and
457 return the rtx for register 0 in the proper mode. */
458
459 rtx
460 gen_compare_reg (code, x, y)
461 enum rtx_code code;
462 rtx x, y;
463 {
464 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
465 rtx cc_reg = gen_rtx (REG, mode, 0);
466
467 emit_insn (gen_rtx (SET, VOIDmode, cc_reg,
468 gen_rtx (COMPARE, mode, x, y)));
469
470 return cc_reg;
471 }
472 \f
473 /* Return nonzero if a return peephole merging return with
474 setting of output register is ok. */
475 int
476 leaf_return_peephole_ok ()
477 {
478 return (actual_fsize == 0);
479 }
480
481 /* Return nonzero if TRIAL can go into the function epilogue's
482 delay slot. SLOT is the slot we are trying to fill. */
483
484 int
485 eligible_for_epilogue_delay (trial, slot)
486 rtx trial;
487 int slot;
488 {
489 rtx pat, src;
490
491 if (slot >= 1)
492 return 0;
493 if (GET_CODE (trial) != INSN
494 || GET_CODE (PATTERN (trial)) != SET)
495 return 0;
496 if (get_attr_length (trial) != 1)
497 return 0;
498
499 /* In the case of a true leaf function, anything can go into the delay slot.
500 A delay slot only exists however if the frame size is zero, otherwise
501 we will put an insn to adjust the stack after the return. */
502 if (leaf_function)
503 {
504 if (leaf_return_peephole_ok ())
505 return (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE);
506 return 0;
507 }
508
509 /* Otherwise, only operations which can be done in tandem with
510 a `restore' insn can go into the delay slot. */
511 pat = PATTERN (trial);
512 if (GET_CODE (SET_DEST (pat)) != REG
513 || REGNO (SET_DEST (pat)) == 0
514 || REGNO (SET_DEST (pat)) >= 32
515 || REGNO (SET_DEST (pat)) < 24)
516 return 0;
517
518 src = SET_SRC (pat);
519 if (arith_operand (src, GET_MODE (src)))
520 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
521 if (arith_double_operand (src, GET_MODE (src)))
522 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
523 if (GET_CODE (src) == PLUS)
524 {
525 if (register_operand (XEXP (src, 0), SImode)
526 && arith_operand (XEXP (src, 1), SImode))
527 return 1;
528 if (register_operand (XEXP (src, 1), SImode)
529 && arith_operand (XEXP (src, 0), SImode))
530 return 1;
531 if (register_operand (XEXP (src, 0), DImode)
532 && arith_double_operand (XEXP (src, 1), DImode))
533 return 1;
534 if (register_operand (XEXP (src, 1), DImode)
535 && arith_double_operand (XEXP (src, 0), DImode))
536 return 1;
537 }
538 if (GET_CODE (src) == MINUS
539 && register_operand (XEXP (src, 0), SImode)
540 && small_int (XEXP (src, 1), VOIDmode))
541 return 1;
542 if (GET_CODE (src) == MINUS
543 && register_operand (XEXP (src, 0), DImode)
544 && !register_operand (XEXP (src, 1), DImode)
545 && arith_double_operand (XEXP (src, 1), DImode))
546 return 1;
547 return 0;
548 }
549
550 int
551 short_branch (uid1, uid2)
552 int uid1, uid2;
553 {
554 unsigned int delta = insn_addresses[uid1] - insn_addresses[uid2];
555 if (delta + 1024 < 2048)
556 return 1;
557 /* warning ("long branch, distance %d", delta); */
558 return 0;
559 }
560
561 /* Return non-zero if REG is not used after INSN.
562 We assume REG is a reload reg, and therefore does
563 not live past labels or calls or jumps. */
564 int
565 reg_unused_after (reg, insn)
566 rtx reg;
567 rtx insn;
568 {
569 enum rtx_code code, prev_code = UNKNOWN;
570
571 while (insn = NEXT_INSN (insn))
572 {
573 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
574 return 1;
575
576 code = GET_CODE (insn);
577 if (GET_CODE (insn) == CODE_LABEL)
578 return 1;
579
580 if (GET_RTX_CLASS (code) == 'i')
581 {
582 rtx set = single_set (insn);
583 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
584 if (set && in_src)
585 return 0;
586 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
587 return 1;
588 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
589 return 0;
590 }
591 prev_code = code;
592 }
593 return 1;
594 }
595 \f
596 /* Legitimize PIC addresses. If the address is already position-independent,
597 we return ORIG. Newly generated position-independent addresses go into a
598 reg. This is REG if non zero, otherwise we allocate register(s) as
599 necessary. If this is called during reload, and we need a second temp
600 register, then we use SCRATCH, which is provided via the
601 SECONDARY_INPUT_RELOAD_CLASS mechanism. */
602
603 rtx
604 legitimize_pic_address (orig, mode, reg, scratch)
605 rtx orig;
606 enum machine_mode mode;
607 rtx reg, scratch;
608 {
609 if (GET_CODE (orig) == SYMBOL_REF)
610 {
611 rtx pic_ref, address;
612 rtx insn;
613
614 if (reg == 0)
615 {
616 if (reload_in_progress || reload_completed)
617 abort ();
618 else
619 reg = gen_reg_rtx (Pmode);
620 }
621
622 if (flag_pic == 2)
623 {
624 /* If not during reload, allocate another temp reg here for loading
625 in the address, so that these instructions can be optimized
626 properly. */
627 rtx temp_reg = ((reload_in_progress || reload_completed)
628 ? reg : gen_reg_rtx (Pmode));
629
630 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
631 won't get confused into thinking that these two instructions
632 are loading in the true address of the symbol. If in the
633 future a PIC rtx exists, that should be used instead. */
634 emit_insn (gen_rtx (SET, VOIDmode, temp_reg,
635 gen_rtx (HIGH, Pmode,
636 gen_rtx (UNSPEC, Pmode,
637 gen_rtvec (1, orig),
638 0))));
639 emit_insn (gen_rtx (SET, VOIDmode, temp_reg,
640 gen_rtx (LO_SUM, Pmode, temp_reg,
641 gen_rtx (UNSPEC, Pmode,
642 gen_rtvec (1, orig),
643 0))));
644 address = temp_reg;
645 }
646 else
647 address = orig;
648
649 pic_ref = gen_rtx (MEM, Pmode,
650 gen_rtx (PLUS, Pmode,
651 pic_offset_table_rtx, address));
652 current_function_uses_pic_offset_table = 1;
653 RTX_UNCHANGING_P (pic_ref) = 1;
654 insn = emit_move_insn (reg, pic_ref);
655 /* Put a REG_EQUAL note on this insn, so that it can be optimized
656 by loop. */
657 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_EQUAL, orig,
658 REG_NOTES (insn));
659 return reg;
660 }
661 else if (GET_CODE (orig) == CONST)
662 {
663 rtx base, offset;
664
665 if (GET_CODE (XEXP (orig, 0)) == PLUS
666 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
667 return orig;
668
669 if (reg == 0)
670 {
671 if (reload_in_progress || reload_completed)
672 abort ();
673 else
674 reg = gen_reg_rtx (Pmode);
675 }
676
677 if (GET_CODE (XEXP (orig, 0)) == PLUS)
678 {
679 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode,
680 reg, 0);
681 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
682 base == reg ? 0 : reg, 0);
683 }
684 else
685 abort ();
686
687 if (GET_CODE (offset) == CONST_INT)
688 {
689 if (SMALL_INT (offset))
690 return plus_constant_for_output (base, INTVAL (offset));
691 else if (! reload_in_progress && ! reload_completed)
692 offset = force_reg (Pmode, offset);
693 /* We can't create any new registers during reload, so use the
694 SCRATCH reg provided by the reload_insi pattern. */
695 else if (scratch)
696 {
697 emit_move_insn (scratch, offset);
698 offset = scratch;
699 }
700 else
701 /* If we reach here, then the SECONDARY_INPUT_RELOAD_CLASS
702 macro needs to be adjusted so that a scratch reg is provided
703 for this address. */
704 abort ();
705 }
706 return gen_rtx (PLUS, Pmode, base, offset);
707 }
708 else if (GET_CODE (orig) == LABEL_REF)
709 current_function_uses_pic_offset_table = 1;
710
711 return orig;
712 }
713
714 /* Set up PIC-specific rtl. This should not cause any insns
715 to be emitted. */
716
717 void
718 initialize_pic ()
719 {
720 }
721
722 /* Emit special PIC prologues and epilogues. */
723
724 void
725 finalize_pic ()
726 {
727 /* The table we use to reference PIC data. */
728 rtx global_offset_table;
729 /* Labels to get the PC in the prologue of this function. */
730 rtx l1, l2;
731 rtx seq;
732 int orig_flag_pic = flag_pic;
733
734 if (current_function_uses_pic_offset_table == 0)
735 return;
736
737 if (! flag_pic)
738 abort ();
739
740 flag_pic = 0;
741 l1 = gen_label_rtx ();
742 l2 = gen_label_rtx ();
743
744 start_sequence ();
745
746 emit_label (l1);
747 /* Note that we pun calls and jumps here! */
748 emit_jump_insn (gen_rtx (PARALLEL, VOIDmode,
749 gen_rtvec (2,
750 gen_rtx (SET, VOIDmode, pc_rtx, gen_rtx (LABEL_REF, VOIDmode, l2)),
751 gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 15), gen_rtx (LABEL_REF, VOIDmode, l2)))));
752 emit_label (l2);
753
754 /* Initialize every time through, since we can't easily
755 know this to be permanent. */
756 global_offset_table = gen_rtx (SYMBOL_REF, Pmode, "_GLOBAL_OFFSET_TABLE_");
757 pic_pc_rtx = gen_rtx (CONST, Pmode,
758 gen_rtx (MINUS, Pmode,
759 global_offset_table,
760 gen_rtx (CONST, Pmode,
761 gen_rtx (MINUS, Pmode,
762 gen_rtx (LABEL_REF, VOIDmode, l1),
763 pc_rtx))));
764
765 emit_insn (gen_rtx (SET, VOIDmode, pic_offset_table_rtx,
766 gen_rtx (HIGH, Pmode, pic_pc_rtx)));
767 emit_insn (gen_rtx (SET, VOIDmode,
768 pic_offset_table_rtx,
769 gen_rtx (LO_SUM, Pmode,
770 pic_offset_table_rtx, pic_pc_rtx)));
771 emit_insn (gen_rtx (SET, VOIDmode,
772 pic_offset_table_rtx,
773 gen_rtx (PLUS, Pmode,
774 pic_offset_table_rtx, gen_rtx (REG, Pmode, 15))));
775 /* emit_insn (gen_rtx (ASM_INPUT, VOIDmode, "!#PROLOGUE# 1")); */
776 LABEL_PRESERVE_P (l1) = 1;
777 LABEL_PRESERVE_P (l2) = 1;
778 flag_pic = orig_flag_pic;
779
780 seq = gen_sequence ();
781 end_sequence ();
782 emit_insn_after (seq, get_insns ());
783
784 /* Need to emit this whether or not we obey regdecls,
785 since setjmp/longjmp can cause life info to screw up. */
786 emit_insn (gen_rtx (USE, VOIDmode, pic_offset_table_rtx));
787 }
788 \f
789 /* For the SPARC, REG and REG+CONST is cost 0, REG+REG is cost 1,
790 and addresses involving symbolic constants are cost 2.
791
792 We make REG+REG slightly more expensive because it might keep
793 a register live for longer than we might like.
794
795 PIC addresses are very expensive.
796
797 It is no coincidence that this has the same structure
798 as GO_IF_LEGITIMATE_ADDRESS. */
799 int
800 sparc_address_cost (X)
801 rtx X;
802 {
803 #if 0
804 /* Handled before calling here. */
805 if (GET_CODE (X) == REG)
806 { return 1; }
807 #endif
808 if (GET_CODE (X) == PLUS)
809 {
810 if (GET_CODE (XEXP (X, 0)) == REG
811 && GET_CODE (XEXP (X, 1)) == REG)
812 return 2;
813 return 1;
814 }
815 else if (GET_CODE (X) == LO_SUM)
816 return 1;
817 else if (GET_CODE (X) == HIGH)
818 return 2;
819 return 4;
820 }
821 \f
822 /* Emit insns to move operands[1] into operands[0].
823
824 Return 1 if we have written out everything that needs to be done to
825 do the move. Otherwise, return 0 and the caller will emit the move
826 normally.
827
828 SCRATCH_REG if non zero can be used as a scratch register for the move
829 operation. It is provided by a SECONDARY_RELOAD_* macro if needed. */
830
831 int
832 emit_move_sequence (operands, mode, scratch_reg)
833 rtx *operands;
834 enum machine_mode mode;
835 rtx scratch_reg;
836 {
837 register rtx operand0 = operands[0];
838 register rtx operand1 = operands[1];
839
840 /* Handle most common case first: storing into a register. */
841 if (register_operand (operand0, mode))
842 {
843 if (register_operand (operand1, mode)
844 || (GET_CODE (operand1) == CONST_INT && SMALL_INT (operand1))
845 || (GET_CODE (operand1) == CONST_DOUBLE
846 && arith_double_operand (operand1, DImode))
847 || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) != DImode)
848 /* Only `general_operands' can come here, so MEM is ok. */
849 || GET_CODE (operand1) == MEM)
850 {
851 /* Run this case quickly. */
852 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
853 return 1;
854 }
855 }
856 else if (GET_CODE (operand0) == MEM)
857 {
858 if (register_operand (operand1, mode) || operand1 == const0_rtx)
859 {
860 /* Run this case quickly. */
861 emit_insn (gen_rtx (SET, VOIDmode, operand0, operand1));
862 return 1;
863 }
864 if (! reload_in_progress)
865 {
866 operands[0] = validize_mem (operand0);
867 operands[1] = operand1 = force_reg (mode, operand1);
868 }
869 }
870
871 /* Simplify the source if we need to. Must handle DImode HIGH operators
872 here because such a move needs a clobber added. */
873 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
874 || (GET_CODE (operand1) == HIGH && GET_MODE (operand1) == DImode))
875 {
876 if (flag_pic && symbolic_operand (operand1, mode))
877 {
878 rtx temp_reg = reload_in_progress ? operand0 : 0;
879
880 operands[1] = legitimize_pic_address (operand1, mode, temp_reg,
881 scratch_reg);
882 }
883 else if (GET_CODE (operand1) == CONST_INT
884 ? (! SMALL_INT (operand1)
885 && (INTVAL (operand1) & 0x3ff) != 0)
886 : (GET_CODE (operand1) == CONST_DOUBLE
887 ? ! arith_double_operand (operand1, DImode)
888 : 1))
889 {
890 /* For DImode values, temp must be operand0 because of the way
891 HI and LO_SUM work. The LO_SUM operator only copies half of
892 the LSW from the dest of the HI operator. If the LO_SUM dest is
893 not the same as the HI dest, then the MSW of the LO_SUM dest will
894 never be set.
895
896 ??? The real problem here is that the ...(HI:DImode pattern emits
897 multiple instructions, and the ...(LO_SUM:DImode pattern emits
898 one instruction. This fails, because the compiler assumes that
899 LO_SUM copies all bits of the first operand to its dest. Better
900 would be to have the HI pattern emit one instruction and the
901 LO_SUM pattern multiple instructions. Even better would be
902 to use four rtl insns. */
903 rtx temp = ((reload_in_progress || mode == DImode)
904 ? operand0 : gen_reg_rtx (mode));
905
906 emit_insn (gen_rtx (SET, VOIDmode, temp,
907 gen_rtx (HIGH, mode, operand1)));
908 operands[1] = gen_rtx (LO_SUM, mode, temp, operand1);
909 }
910 }
911
912 if (GET_CODE (operand1) == LABEL_REF && flag_pic)
913 {
914 /* The procedure for doing this involves using a call instruction to
915 get the pc into o7. We need to indicate this explicitly because
916 the tablejump pattern assumes that it can use this value also. */
917 emit_insn (gen_rtx (PARALLEL, VOIDmode,
918 gen_rtvec (2,
919 gen_rtx (SET, VOIDmode, operand0,
920 operand1),
921 gen_rtx (SET, VOIDmode,
922 gen_rtx (REG, mode, 15),
923 pc_rtx))));
924 return 1;
925 }
926
927 /* Now have insn-emit do whatever it normally does. */
928 return 0;
929 }
930 \f
931 /* Return the best assembler insn template
932 for moving operands[1] into operands[0] as a fullword. */
933
934 char *
935 singlemove_string (operands)
936 rtx *operands;
937 {
938 if (GET_CODE (operands[0]) == MEM)
939 {
940 if (GET_CODE (operands[1]) != MEM)
941 return "st %r1,%0";
942 else
943 abort ();
944 }
945 else if (GET_CODE (operands[1]) == MEM)
946 return "ld %1,%0";
947 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
948 {
949 REAL_VALUE_TYPE r;
950 long i;
951
952 /* Must be SFmode, otherwise this doesn't make sense. */
953 if (GET_MODE (operands[1]) != SFmode)
954 abort ();
955
956 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
957 REAL_VALUE_TO_TARGET_SINGLE (r, i);
958 operands[1] = gen_rtx (CONST_INT, VOIDmode, i);
959
960 if (CONST_OK_FOR_LETTER_P (i, 'I'))
961 return "mov %1,%0";
962 else if ((i & 0x000003FF) != 0)
963 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
964 else
965 return "sethi %%hi(%a1),%0";
966 }
967 else if (GET_CODE (operands[1]) == CONST_INT
968 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I'))
969 {
970 int i = INTVAL (operands[1]);
971
972 /* If all low order 10 bits are clear, then we only need a single
973 sethi insn to load the constant. */
974 if ((i & 0x000003FF) != 0)
975 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
976 else
977 return "sethi %%hi(%a1),%0";
978 }
979 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
980 return "mov %1,%0";
981 }
982 \f
983 /* Return non-zero if it is OK to assume that the given memory operand is
984 aligned at least to a 8-byte boundary. This should only be called
985 for memory accesses whose size is 8 bytes or larger. */
986
987 int
988 mem_aligned_8 (mem)
989 register rtx mem;
990 {
991 register rtx addr;
992 register rtx base;
993 register rtx offset;
994
995 if (GET_CODE (mem) != MEM)
996 return 0; /* It's gotta be a MEM! */
997
998 addr = XEXP (mem, 0);
999
1000 /* Now that all misaligned double parms are copied on function entry,
1001 we can assume any 64-bit object is 64-bit aligned except those which
1002 are at unaligned offsets from the stack or frame pointer. If the
1003 TARGET_UNALIGNED_DOUBLES switch is given, we do not make this
1004 assumption. */
1005
1006 /* See what register we use in the address. */
1007 base = 0;
1008 if (GET_CODE (addr) == PLUS)
1009 {
1010 if (GET_CODE (XEXP (addr, 0)) == REG
1011 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
1012 {
1013 base = XEXP (addr, 0);
1014 offset = XEXP (addr, 1);
1015 }
1016 }
1017 else if (GET_CODE (addr) == REG)
1018 {
1019 base = addr;
1020 offset = const0_rtx;
1021 }
1022
1023 /* If it's the stack or frame pointer, check offset alignment.
1024 We can have improper alignment in the function entry code. */
1025 if (base
1026 && (REGNO (base) == FRAME_POINTER_REGNUM
1027 || REGNO (base) == STACK_POINTER_REGNUM))
1028 {
1029 if ((INTVAL (offset) & 0x7) == 0)
1030 return 1;
1031 }
1032 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
1033 is true, in which case we can only assume that an access is aligned if
1034 it is to an aggregate, it is to a constant address, or the address
1035 involves a LO_SUM. */
1036 else if (! TARGET_UNALIGNED_DOUBLES || MEM_IN_STRUCT_P (mem)
1037 || CONSTANT_P (addr) || GET_CODE (addr) == LO_SUM)
1038 return 1;
1039
1040 /* An obviously unaligned address. */
1041 return 0;
1042 }
1043
1044 enum optype { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP };
1045
1046 /* Output assembler code to perform a doubleword move insn
1047 with operands OPERANDS. This is very similar to the following
1048 output_move_quad function. */
1049
1050 char *
1051 output_move_double (operands)
1052 rtx *operands;
1053 {
1054 register rtx op0 = operands[0];
1055 register rtx op1 = operands[1];
1056 register enum optype optype0;
1057 register enum optype optype1;
1058 rtx latehalf[2];
1059 rtx addreg0 = 0;
1060 rtx addreg1 = 0;
1061 int highest_first = 0;
1062 int no_addreg1_decrement = 0;
1063
1064 /* First classify both operands. */
1065
1066 if (REG_P (op0))
1067 optype0 = REGOP;
1068 else if (offsettable_memref_p (op0))
1069 optype0 = OFFSOP;
1070 else if (GET_CODE (op0) == MEM)
1071 optype0 = MEMOP;
1072 else
1073 optype0 = RNDOP;
1074
1075 if (REG_P (op1))
1076 optype1 = REGOP;
1077 else if (CONSTANT_P (op1))
1078 optype1 = CNSTOP;
1079 else if (offsettable_memref_p (op1))
1080 optype1 = OFFSOP;
1081 else if (GET_CODE (op1) == MEM)
1082 optype1 = MEMOP;
1083 else
1084 optype1 = RNDOP;
1085
1086 /* Check for the cases that the operand constraints are not
1087 supposed to allow to happen. Abort if we get one,
1088 because generating code for these cases is painful. */
1089
1090 if (optype0 == RNDOP || optype1 == RNDOP
1091 || (optype0 == MEM && optype1 == MEM))
1092 abort ();
1093
1094 /* If an operand is an unoffsettable memory ref, find a register
1095 we can increment temporarily to make it refer to the second word. */
1096
1097 if (optype0 == MEMOP)
1098 addreg0 = find_addr_reg (XEXP (op0, 0));
1099
1100 if (optype1 == MEMOP)
1101 addreg1 = find_addr_reg (XEXP (op1, 0));
1102
1103 /* Ok, we can do one word at a time.
1104 Set up in LATEHALF the operands to use for the
1105 high-numbered (least significant) word and in some cases alter the
1106 operands in OPERANDS to be suitable for the low-numbered word. */
1107
1108 if (optype0 == REGOP)
1109 latehalf[0] = gen_rtx (REG, SImode, REGNO (op0) + 1);
1110 else if (optype0 == OFFSOP)
1111 latehalf[0] = adj_offsettable_operand (op0, 4);
1112 else
1113 latehalf[0] = op0;
1114
1115 if (optype1 == REGOP)
1116 latehalf[1] = gen_rtx (REG, SImode, REGNO (op1) + 1);
1117 else if (optype1 == OFFSOP)
1118 latehalf[1] = adj_offsettable_operand (op1, 4);
1119 else if (optype1 == CNSTOP)
1120 split_double (op1, &operands[1], &latehalf[1]);
1121 else
1122 latehalf[1] = op1;
1123
1124 /* Easy case: try moving both words at once. Check for moving between
1125 an even/odd register pair and a memory location. */
1126 if ((optype0 == REGOP && optype1 != REGOP && optype1 != CNSTOP
1127 && (REGNO (op0) & 1) == 0)
1128 || (optype0 != REGOP && optype0 != CNSTOP && optype1 == REGOP
1129 && (REGNO (op1) & 1) == 0))
1130 {
1131 register rtx mem;
1132
1133 if (optype0 == REGOP)
1134 mem = op1;
1135 else
1136 mem = op0;
1137
1138 if (mem_aligned_8 (mem))
1139 return (mem == op1 ? "ldd %1,%0" : "std %1,%0");
1140 }
1141
1142 /* If the first move would clobber the source of the second one,
1143 do them in the other order. */
1144
1145 /* Overlapping registers. */
1146 if (optype0 == REGOP && optype1 == REGOP
1147 && REGNO (op0) == REGNO (latehalf[1]))
1148 {
1149 /* Do that word. */
1150 output_asm_insn (singlemove_string (latehalf), latehalf);
1151 /* Do low-numbered word. */
1152 return singlemove_string (operands);
1153 }
1154 /* Loading into a register which overlaps a register used in the address. */
1155 else if (optype0 == REGOP && optype1 != REGOP
1156 && reg_overlap_mentioned_p (op0, op1))
1157 {
1158 /* If both halves of dest are used in the src memory address,
1159 add the two regs and put them in the low reg (op0).
1160 Then it works to load latehalf first. */
1161 if (reg_mentioned_p (op0, XEXP (op1, 0))
1162 && reg_mentioned_p (latehalf[0], XEXP (op1, 0)))
1163 {
1164 rtx xops[2];
1165 xops[0] = latehalf[0];
1166 xops[1] = op0;
1167 output_asm_insn ("add %1,%0,%1", xops);
1168 operands[1] = gen_rtx (MEM, DImode, op0);
1169 latehalf[1] = adj_offsettable_operand (operands[1], 4);
1170 addreg1 = 0;
1171 highest_first = 1;
1172 }
1173 /* Only one register in the dest is used in the src memory address,
1174 and this is the first register of the dest, so we want to do
1175 the late half first here also. */
1176 else if (! reg_mentioned_p (latehalf[0], XEXP (op1, 0)))
1177 highest_first = 1;
1178 /* Only one register in the dest is used in the src memory address,
1179 and this is the second register of the dest, so we want to do
1180 the late half last. If addreg1 is set, and addreg1 is the same
1181 register as latehalf, then we must suppress the trailing decrement,
1182 because it would clobber the value just loaded. */
1183 else if (addreg1 && reg_mentioned_p (addreg1, latehalf[0]))
1184 no_addreg1_decrement = 1;
1185 }
1186
1187 /* Normal case: do the two words, low-numbered first.
1188 Overlap case (highest_first set): do high-numbered word first. */
1189
1190 if (! highest_first)
1191 output_asm_insn (singlemove_string (operands), operands);
1192
1193 /* Make any unoffsettable addresses point at high-numbered word. */
1194 if (addreg0)
1195 output_asm_insn ("add %0,0x4,%0", &addreg0);
1196 if (addreg1)
1197 output_asm_insn ("add %0,0x4,%0", &addreg1);
1198
1199 /* Do that word. */
1200 output_asm_insn (singlemove_string (latehalf), latehalf);
1201
1202 /* Undo the adds we just did. */
1203 if (addreg0)
1204 output_asm_insn ("add %0,-0x4,%0", &addreg0);
1205 if (addreg1 && ! no_addreg1_decrement)
1206 output_asm_insn ("add %0,-0x4,%0", &addreg1);
1207
1208 if (highest_first)
1209 output_asm_insn (singlemove_string (operands), operands);
1210
1211 return "";
1212 }
1213
1214 /* Output assembler code to perform a quadword move insn
1215 with operands OPERANDS. This is very similar to the preceding
1216 output_move_double function. */
1217
1218 char *
1219 output_move_quad (operands)
1220 rtx *operands;
1221 {
1222 register rtx op0 = operands[0];
1223 register rtx op1 = operands[1];
1224 register enum optype optype0;
1225 register enum optype optype1;
1226 rtx wordpart[4][2];
1227 rtx addreg0 = 0;
1228 rtx addreg1 = 0;
1229
1230 /* First classify both operands. */
1231
1232 if (REG_P (op0))
1233 optype0 = REGOP;
1234 else if (offsettable_memref_p (op0))
1235 optype0 = OFFSOP;
1236 else if (GET_CODE (op0) == MEM)
1237 optype0 = MEMOP;
1238 else
1239 optype0 = RNDOP;
1240
1241 if (REG_P (op1))
1242 optype1 = REGOP;
1243 else if (CONSTANT_P (op1))
1244 optype1 = CNSTOP;
1245 else if (offsettable_memref_p (op1))
1246 optype1 = OFFSOP;
1247 else if (GET_CODE (op1) == MEM)
1248 optype1 = MEMOP;
1249 else
1250 optype1 = RNDOP;
1251
1252 /* Check for the cases that the operand constraints are not
1253 supposed to allow to happen. Abort if we get one,
1254 because generating code for these cases is painful. */
1255
1256 if (optype0 == RNDOP || optype1 == RNDOP
1257 || (optype0 == MEM && optype1 == MEM))
1258 abort ();
1259
1260 /* If an operand is an unoffsettable memory ref, find a register
1261 we can increment temporarily to make it refer to the later words. */
1262
1263 if (optype0 == MEMOP)
1264 addreg0 = find_addr_reg (XEXP (op0, 0));
1265
1266 if (optype1 == MEMOP)
1267 addreg1 = find_addr_reg (XEXP (op1, 0));
1268
1269 /* Ok, we can do one word at a time.
1270 Set up in wordpart the operands to use for each word of the arguments. */
1271
1272 if (optype0 == REGOP)
1273 {
1274 wordpart[0][0] = gen_rtx (REG, SImode, REGNO (op0) + 0);
1275 wordpart[1][0] = gen_rtx (REG, SImode, REGNO (op0) + 1);
1276 wordpart[2][0] = gen_rtx (REG, SImode, REGNO (op0) + 2);
1277 wordpart[3][0] = gen_rtx (REG, SImode, REGNO (op0) + 3);
1278 }
1279 else if (optype0 == OFFSOP)
1280 {
1281 wordpart[0][0] = adj_offsettable_operand (op0, 0);
1282 wordpart[1][0] = adj_offsettable_operand (op0, 4);
1283 wordpart[2][0] = adj_offsettable_operand (op0, 8);
1284 wordpart[3][0] = adj_offsettable_operand (op0, 12);
1285 }
1286 else
1287 {
1288 wordpart[0][0] = op0;
1289 wordpart[1][0] = op0;
1290 wordpart[2][0] = op0;
1291 wordpart[3][0] = op0;
1292 }
1293
1294 if (optype1 == REGOP)
1295 {
1296 wordpart[0][1] = gen_rtx (REG, SImode, REGNO (op1) + 0);
1297 wordpart[1][1] = gen_rtx (REG, SImode, REGNO (op1) + 1);
1298 wordpart[2][1] = gen_rtx (REG, SImode, REGNO (op1) + 2);
1299 wordpart[3][1] = gen_rtx (REG, SImode, REGNO (op1) + 3);
1300 }
1301 else if (optype1 == OFFSOP)
1302 {
1303 wordpart[0][1] = adj_offsettable_operand (op1, 0);
1304 wordpart[1][1] = adj_offsettable_operand (op1, 4);
1305 wordpart[2][1] = adj_offsettable_operand (op1, 8);
1306 wordpart[3][1] = adj_offsettable_operand (op1, 12);
1307 }
1308 else if (optype1 == CNSTOP)
1309 {
1310 REAL_VALUE_TYPE r;
1311 long l[4];
1312
1313 /* This only works for TFmode floating point constants. */
1314 if (GET_CODE (op1) != CONST_DOUBLE || GET_MODE (op1) != TFmode)
1315 abort ();
1316
1317 REAL_VALUE_FROM_CONST_DOUBLE (r, op1);
1318 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l);
1319
1320 wordpart[0][1] = GEN_INT (l[0]);
1321 wordpart[1][1] = GEN_INT (l[1]);
1322 wordpart[2][1] = GEN_INT (l[2]);
1323 wordpart[3][1] = GEN_INT (l[3]);
1324 }
1325 else
1326 {
1327 wordpart[0][1] = op1;
1328 wordpart[1][1] = op1;
1329 wordpart[2][1] = op1;
1330 wordpart[3][1] = op1;
1331 }
1332
1333 /* Easy case: try moving the quad as two pairs. Check for moving between
1334 an even/odd register pair and a memory location. */
1335 /* ??? Should also handle the case of non-offsettable addresses here.
1336 We can at least do the first pair as a ldd/std, and then do the third
1337 and fourth words individually. */
1338 if ((optype0 == REGOP && optype1 == OFFSOP && (REGNO (op0) & 1) == 0)
1339 || (optype0 == OFFSOP && optype1 == REGOP && (REGNO (op1) & 1) == 0))
1340 {
1341 rtx mem;
1342
1343 if (optype0 == REGOP)
1344 mem = op1;
1345 else
1346 mem = op0;
1347
1348 if (mem_aligned_8 (mem))
1349 {
1350 operands[2] = adj_offsettable_operand (mem, 8);
1351 if (mem == op1)
1352 return "ldd %1,%0;ldd %2,%S0";
1353 else
1354 return "std %1,%0;std %S1,%2";
1355 }
1356 }
1357
1358 /* If the first move would clobber the source of the second one,
1359 do them in the other order. */
1360
1361 /* Overlapping registers. */
1362 if (optype0 == REGOP && optype1 == REGOP
1363 && (REGNO (op0) == REGNO (wordpart[1][3])
1364 || REGNO (op0) == REGNO (wordpart[1][2])
1365 || REGNO (op0) == REGNO (wordpart[1][1])))
1366 {
1367 /* Do fourth word. */
1368 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
1369 /* Do the third word. */
1370 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
1371 /* Do the second word. */
1372 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
1373 /* Do lowest-numbered word. */
1374 return singlemove_string (wordpart[0]);
1375 }
1376 /* Loading into a register which overlaps a register used in the address. */
1377 if (optype0 == REGOP && optype1 != REGOP
1378 && reg_overlap_mentioned_p (op0, op1))
1379 {
1380 /* ??? Not implemented yet. This is a bit complicated, because we
1381 must load which ever part overlaps the address last. If the address
1382 is a double-reg address, then there are two parts which need to
1383 be done last, which is impossible. We would need a scratch register
1384 in that case. */
1385 abort ();
1386 }
1387
1388 /* Normal case: move the four words in lowest to higest address order. */
1389
1390 output_asm_insn (singlemove_string (wordpart[0]), wordpart[0]);
1391
1392 /* Make any unoffsettable addresses point at the second word. */
1393 if (addreg0)
1394 output_asm_insn ("add %0,0x4,%0", &addreg0);
1395 if (addreg1)
1396 output_asm_insn ("add %0,0x4,%0", &addreg1);
1397
1398 /* Do the second word. */
1399 output_asm_insn (singlemove_string (wordpart[1]), wordpart[1]);
1400
1401 /* Make any unoffsettable addresses point at the third word. */
1402 if (addreg0)
1403 output_asm_insn ("add %0,0x4,%0", &addreg0);
1404 if (addreg1)
1405 output_asm_insn ("add %0,0x4,%0", &addreg1);
1406
1407 /* Do the third word. */
1408 output_asm_insn (singlemove_string (wordpart[2]), wordpart[2]);
1409
1410 /* Make any unoffsettable addresses point at the fourth word. */
1411 if (addreg0)
1412 output_asm_insn ("add %0,0x4,%0", &addreg0);
1413 if (addreg1)
1414 output_asm_insn ("add %0,0x4,%0", &addreg1);
1415
1416 /* Do the fourth word. */
1417 output_asm_insn (singlemove_string (wordpart[3]), wordpart[3]);
1418
1419 /* Undo the adds we just did. */
1420 if (addreg0)
1421 output_asm_insn ("add %0,-0xc,%0", &addreg0);
1422 if (addreg1)
1423 output_asm_insn ("add %0,-0xc,%0", &addreg1);
1424
1425 return "";
1426 }
1427 \f
1428 /* Output assembler code to perform a doubleword move insn with operands
1429 OPERANDS, one of which must be a floating point register. */
1430
1431 char *
1432 output_fp_move_double (operands)
1433 rtx *operands;
1434 {
1435 if (FP_REG_P (operands[0]))
1436 {
1437 if (FP_REG_P (operands[1]))
1438 return "fmovs %1,%0\n\tfmovs %R1,%R0";
1439 else if (GET_CODE (operands[1]) == REG)
1440 abort ();
1441 else
1442 return output_move_double (operands);
1443 }
1444 else if (FP_REG_P (operands[1]))
1445 {
1446 if (GET_CODE (operands[0]) == REG)
1447 abort ();
1448 else
1449 return output_move_double (operands);
1450 }
1451 else abort ();
1452 }
1453
1454 /* Output assembler code to perform a quadword move insn with operands
1455 OPERANDS, one of which must be a floating point register. */
1456
1457 char *
1458 output_fp_move_quad (operands)
1459 rtx *operands;
1460 {
1461 register rtx op0 = operands[0];
1462 register rtx op1 = operands[1];
1463
1464 if (FP_REG_P (op0))
1465 {
1466 if (FP_REG_P (op1))
1467 return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0";
1468 else if (GET_CODE (op1) == REG)
1469 abort ();
1470 else
1471 return output_move_quad (operands);
1472 }
1473 else if (FP_REG_P (op1))
1474 {
1475 if (GET_CODE (op0) == REG)
1476 abort ();
1477 else
1478 return output_move_quad (operands);
1479 }
1480 else
1481 abort ();
1482 }
1483 \f
1484 /* Return a REG that occurs in ADDR with coefficient 1.
1485 ADDR can be effectively incremented by incrementing REG. */
1486
1487 static rtx
1488 find_addr_reg (addr)
1489 rtx addr;
1490 {
1491 while (GET_CODE (addr) == PLUS)
1492 {
1493 /* We absolutely can not fudge the frame pointer here, because the
1494 frame pointer must always be 8 byte aligned. It also confuses
1495 debuggers. */
1496 if (GET_CODE (XEXP (addr, 0)) == REG
1497 && REGNO (XEXP (addr, 0)) != FRAME_POINTER_REGNUM)
1498 addr = XEXP (addr, 0);
1499 else if (GET_CODE (XEXP (addr, 1)) == REG
1500 && REGNO (XEXP (addr, 1)) != FRAME_POINTER_REGNUM)
1501 addr = XEXP (addr, 1);
1502 else if (CONSTANT_P (XEXP (addr, 0)))
1503 addr = XEXP (addr, 1);
1504 else if (CONSTANT_P (XEXP (addr, 1)))
1505 addr = XEXP (addr, 0);
1506 else
1507 abort ();
1508 }
1509 if (GET_CODE (addr) == REG)
1510 return addr;
1511 abort ();
1512 }
1513
1514 void
1515 output_sized_memop (opname, mode, signedp)
1516 char *opname;
1517 enum machine_mode mode;
1518 int signedp;
1519 {
1520 static char *ld_size_suffix_u[] = { "ub", "uh", "", "?", "d" };
1521 static char *ld_size_suffix_s[] = { "sb", "sh", "", "?", "d" };
1522 static char *st_size_suffix[] = { "b", "h", "", "?", "d" };
1523 char **opnametab, *modename;
1524
1525 if (opname[0] == 'l')
1526 if (signedp)
1527 opnametab = ld_size_suffix_s;
1528 else
1529 opnametab = ld_size_suffix_u;
1530 else
1531 opnametab = st_size_suffix;
1532 modename = opnametab[GET_MODE_SIZE (mode) >> 1];
1533
1534 fprintf (asm_out_file, "\t%s%s", opname, modename);
1535 }
1536 \f
1537 void
1538 output_move_with_extension (operands)
1539 rtx *operands;
1540 {
1541 if (GET_MODE (operands[2]) == HImode)
1542 output_asm_insn ("sll %2,0x10,%0", operands);
1543 else if (GET_MODE (operands[2]) == QImode)
1544 output_asm_insn ("sll %2,0x18,%0", operands);
1545 else
1546 abort ();
1547 }
1548 \f
1549 #if 0
1550 /* ??? These are only used by the movstrsi pattern, but we get better code
1551 in general without that, because emit_block_move can do just as good a
1552 job as this function does when alignment and size are known. When they
1553 aren't known, a call to strcpy may be faster anyways, because it is
1554 likely to be carefully crafted assembly language code, and below we just
1555 do a byte-wise copy.
1556
1557 Also, emit_block_move expands into multiple read/write RTL insns, which
1558 can then be optimized, whereas our movstrsi pattern can not be optimized
1559 at all. */
1560
1561 /* Load the address specified by OPERANDS[3] into the register
1562 specified by OPERANDS[0].
1563
1564 OPERANDS[3] may be the result of a sum, hence it could either be:
1565
1566 (1) CONST
1567 (2) REG
1568 (2) REG + CONST_INT
1569 (3) REG + REG + CONST_INT
1570 (4) REG + REG (special case of 3).
1571
1572 Note that (3) is not a legitimate address.
1573 All cases are handled here. */
1574
1575 void
1576 output_load_address (operands)
1577 rtx *operands;
1578 {
1579 rtx base, offset;
1580
1581 if (CONSTANT_P (operands[3]))
1582 {
1583 output_asm_insn ("set %3,%0", operands);
1584 return;
1585 }
1586
1587 if (REG_P (operands[3]))
1588 {
1589 if (REGNO (operands[0]) != REGNO (operands[3]))
1590 output_asm_insn ("mov %3,%0", operands);
1591 return;
1592 }
1593
1594 if (GET_CODE (operands[3]) != PLUS)
1595 abort ();
1596
1597 base = XEXP (operands[3], 0);
1598 offset = XEXP (operands[3], 1);
1599
1600 if (GET_CODE (base) == CONST_INT)
1601 {
1602 rtx tmp = base;
1603 base = offset;
1604 offset = tmp;
1605 }
1606
1607 if (GET_CODE (offset) != CONST_INT)
1608 {
1609 /* Operand is (PLUS (REG) (REG)). */
1610 base = operands[3];
1611 offset = const0_rtx;
1612 }
1613
1614 if (REG_P (base))
1615 {
1616 operands[6] = base;
1617 operands[7] = offset;
1618 if (SMALL_INT (offset))
1619 output_asm_insn ("add %6,%7,%0", operands);
1620 else
1621 output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands);
1622 }
1623 else if (GET_CODE (base) == PLUS)
1624 {
1625 operands[6] = XEXP (base, 0);
1626 operands[7] = XEXP (base, 1);
1627 operands[8] = offset;
1628
1629 if (SMALL_INT (offset))
1630 output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands);
1631 else
1632 output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands);
1633 }
1634 else
1635 abort ();
1636 }
1637
1638 /* Output code to place a size count SIZE in register REG.
1639 ALIGN is the size of the unit of transfer.
1640
1641 Because block moves are pipelined, we don't include the
1642 first element in the transfer of SIZE to REG. */
1643
1644 static void
1645 output_size_for_block_move (size, reg, align)
1646 rtx size, reg;
1647 rtx align;
1648 {
1649 rtx xoperands[3];
1650
1651 xoperands[0] = reg;
1652 xoperands[1] = size;
1653 xoperands[2] = align;
1654 if (GET_CODE (size) == REG)
1655 output_asm_insn ("sub %1,%2,%0", xoperands);
1656 else
1657 {
1658 xoperands[1]
1659 = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align));
1660 output_asm_insn ("set %1,%0", xoperands);
1661 }
1662 }
1663
1664 /* Emit code to perform a block move.
1665
1666 OPERANDS[0] is the destination.
1667 OPERANDS[1] is the source.
1668 OPERANDS[2] is the size.
1669 OPERANDS[3] is the alignment safe to use.
1670 OPERANDS[4] is a register we can safely clobber as a temp. */
1671
1672 char *
1673 output_block_move (operands)
1674 rtx *operands;
1675 {
1676 /* A vector for our computed operands. Note that load_output_address
1677 makes use of (and can clobber) up to the 8th element of this vector. */
1678 rtx xoperands[10];
1679 rtx zoperands[10];
1680 static int movstrsi_label = 0;
1681 int i;
1682 rtx temp1 = operands[4];
1683 rtx sizertx = operands[2];
1684 rtx alignrtx = operands[3];
1685 int align = INTVAL (alignrtx);
1686 char label3[30], label5[30];
1687
1688 xoperands[0] = operands[0];
1689 xoperands[1] = operands[1];
1690 xoperands[2] = temp1;
1691
1692 /* We can't move more than this many bytes at a time because we have only
1693 one register, %g1, to move them through. */
1694 if (align > UNITS_PER_WORD)
1695 {
1696 align = UNITS_PER_WORD;
1697 alignrtx = gen_rtx (CONST_INT, VOIDmode, UNITS_PER_WORD);
1698 }
1699
1700 /* We consider 8 ld/st pairs, for a total of 16 inline insns to be
1701 reasonable here. (Actually will emit a maximum of 18 inline insns for
1702 the case of size == 31 and align == 4). */
1703
1704 if (GET_CODE (sizertx) == CONST_INT && (INTVAL (sizertx) / align) <= 8
1705 && memory_address_p (QImode, plus_constant_for_output (xoperands[0],
1706 INTVAL (sizertx)))
1707 && memory_address_p (QImode, plus_constant_for_output (xoperands[1],
1708 INTVAL (sizertx))))
1709 {
1710 int size = INTVAL (sizertx);
1711 int offset = 0;
1712
1713 /* We will store different integers into this particular RTX. */
1714 xoperands[2] = rtx_alloc (CONST_INT);
1715 PUT_MODE (xoperands[2], VOIDmode);
1716
1717 /* This case is currently not handled. Abort instead of generating
1718 bad code. */
1719 if (align > 4)
1720 abort ();
1721
1722 if (align >= 4)
1723 {
1724 for (i = (size >> 2) - 1; i >= 0; i--)
1725 {
1726 INTVAL (xoperands[2]) = (i << 2) + offset;
1727 output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]",
1728 xoperands);
1729 }
1730 offset += (size & ~0x3);
1731 size = size & 0x3;
1732 if (size == 0)
1733 return "";
1734 }
1735
1736 if (align >= 2)
1737 {
1738 for (i = (size >> 1) - 1; i >= 0; i--)
1739 {
1740 INTVAL (xoperands[2]) = (i << 1) + offset;
1741 output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]",
1742 xoperands);
1743 }
1744 offset += (size & ~0x1);
1745 size = size & 0x1;
1746 if (size == 0)
1747 return "";
1748 }
1749
1750 if (align >= 1)
1751 {
1752 for (i = size - 1; i >= 0; i--)
1753 {
1754 INTVAL (xoperands[2]) = i + offset;
1755 output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]",
1756 xoperands);
1757 }
1758 return "";
1759 }
1760
1761 /* We should never reach here. */
1762 abort ();
1763 }
1764
1765 /* If the size isn't known to be a multiple of the alignment,
1766 we have to do it in smaller pieces. If we could determine that
1767 the size was a multiple of 2 (or whatever), we could be smarter
1768 about this. */
1769 if (GET_CODE (sizertx) != CONST_INT)
1770 align = 1;
1771 else
1772 {
1773 int size = INTVAL (sizertx);
1774 while (size % align)
1775 align >>= 1;
1776 }
1777
1778 if (align != INTVAL (alignrtx))
1779 alignrtx = gen_rtx (CONST_INT, VOIDmode, align);
1780
1781 xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
1782 xoperands[4] = gen_rtx (CONST_INT, VOIDmode, align);
1783 xoperands[5] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
1784
1785 ASM_GENERATE_INTERNAL_LABEL (label3, "Lm", INTVAL (xoperands[3]));
1786 ASM_GENERATE_INTERNAL_LABEL (label5, "Lm", INTVAL (xoperands[5]));
1787
1788 /* This is the size of the transfer. Emit code to decrement the size
1789 value by ALIGN, and store the result in the temp1 register. */
1790 output_size_for_block_move (sizertx, temp1, alignrtx);
1791
1792 /* Must handle the case when the size is zero or negative, so the first thing
1793 we do is compare the size against zero, and only copy bytes if it is
1794 zero or greater. Note that we have already subtracted off the alignment
1795 once, so we must copy 1 alignment worth of bytes if the size is zero
1796 here.
1797
1798 The SUN assembler complains about labels in branch delay slots, so we
1799 do this before outputting the load address, so that there will always
1800 be a harmless insn between the branch here and the next label emitted
1801 below. */
1802
1803 {
1804 char pattern[100];
1805
1806 sprintf (pattern, "cmp %%2,0\n\tbl %s", &label5[1]);
1807 output_asm_insn (pattern, xoperands);
1808 }
1809
1810 zoperands[0] = operands[0];
1811 zoperands[3] = plus_constant_for_output (operands[0], align);
1812 output_load_address (zoperands);
1813
1814 /* ??? This might be much faster if the loops below were preconditioned
1815 and unrolled.
1816
1817 That is, at run time, copy enough bytes one at a time to ensure that the
1818 target and source addresses are aligned to the the largest possible
1819 alignment. Then use a preconditioned unrolled loop to copy say 16
1820 bytes at a time. Then copy bytes one at a time until finish the rest. */
1821
1822 /* Output the first label separately, so that it is spaced properly. */
1823
1824 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "Lm", INTVAL (xoperands[3]));
1825
1826 {
1827 char pattern[200];
1828 register char *ld_suffix = (align == 1) ? "ub" : (align == 2) ? "uh" : "";
1829 register char *st_suffix = (align == 1) ? "b" : (align == 2) ? "h" : "";
1830
1831 sprintf (pattern, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix, &label3[1], st_suffix, &label5[1]);
1832 output_asm_insn (pattern, xoperands);
1833 }
1834
1835 return "";
1836 }
1837 #endif
1838 \f
1839 /* Output reasonable peephole for set-on-condition-code insns.
1840 Note that these insns assume a particular way of defining
1841 labels. Therefore, *both* sparc.h and this function must
1842 be changed if a new syntax is needed. */
1843
1844 char *
1845 output_scc_insn (operands, insn)
1846 rtx operands[];
1847 rtx insn;
1848 {
1849 static char string[100];
1850 rtx label = 0, next = insn;
1851 int need_label = 0;
1852
1853 /* Try doing a jump optimization which jump.c can't do for us
1854 because we did not expose that setcc works by using branches.
1855
1856 If this scc insn is followed by an unconditional branch, then have
1857 the jump insn emitted here jump to that location, instead of to
1858 the end of the scc sequence as usual. */
1859
1860 do
1861 {
1862 if (GET_CODE (next) == CODE_LABEL)
1863 label = next;
1864 next = NEXT_INSN (next);
1865 if (next == 0)
1866 break;
1867 }
1868 while (GET_CODE (next) == NOTE || GET_CODE (next) == CODE_LABEL);
1869
1870 /* If we are in a sequence, and the following insn is a sequence also,
1871 then just following the current insn's next field will take us to the
1872 first insn of the next sequence, which is the wrong place. We don't
1873 want to optimize with a branch that has had its delay slot filled.
1874 Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next
1875 which fails only if NEXT is such a branch. */
1876
1877 if (next && GET_CODE (next) == JUMP_INSN && simplejump_p (next)
1878 && (! final_sequence || NEXT_INSN (PREV_INSN (next)) == next))
1879 label = JUMP_LABEL (next);
1880 /* If not optimizing, jump label fields are not set. To be safe, always
1881 check here to whether label is still zero. */
1882 if (label == 0)
1883 {
1884 label = gen_label_rtx ();
1885 need_label = 1;
1886 }
1887
1888 LABEL_NUSES (label) += 1;
1889
1890 operands[2] = label;
1891
1892 /* If we are in a delay slot, assume it is the delay slot of an fpcc
1893 insn since our type isn't allowed anywhere else. */
1894
1895 /* ??? Fpcc instructions no longer have delay slots, so this code is
1896 probably obsolete. */
1897
1898 /* The fastest way to emit code for this is an annulled branch followed
1899 by two move insns. This will take two cycles if the branch is taken,
1900 and three cycles if the branch is not taken.
1901
1902 However, if we are in the delay slot of another branch, this won't work,
1903 because we can't put a branch in the delay slot of another branch.
1904 The above sequence would effectively take 3 or 4 cycles respectively
1905 since a no op would have be inserted between the two branches.
1906 In this case, we want to emit a move, annulled branch, and then the
1907 second move. This sequence always takes 3 cycles, and hence is faster
1908 when we are in a branch delay slot. */
1909
1910 if (final_sequence)
1911 {
1912 strcpy (string, "mov 0,%0\n\t");
1913 strcat (string, output_cbranch (operands[1], 2, 0, 1, 0));
1914 strcat (string, "\n\tmov 1,%0");
1915 }
1916 else
1917 {
1918 strcpy (string, output_cbranch (operands[1], 2, 0, 1, 0));
1919 strcat (string, "\n\tmov 1,%0\n\tmov 0,%0");
1920 }
1921
1922 if (need_label)
1923 strcat (string, "\n%l2:");
1924
1925 return string;
1926 }
1927 \f
1928 /* Vectors to keep interesting information about registers where
1929 it can easily be got. */
1930
1931 /* Modes for condition codes. */
1932 #define C_MODES \
1933 ((1 << (int) CCmode) | (1 << (int) CC_NOOVmode) \
1934 | (1 << (int) CCFPmode) | (1 << (int) CCFPEmode))
1935
1936 /* Modes for single-word (and smaller) quantities. */
1937 #define S_MODES \
1938 ((1 << (int) QImode) | (1 << (int) HImode) | (1 << (int) SImode) \
1939 | (1 << (int) QFmode) | (1 << (int) HFmode) | (1 << (int) SFmode) \
1940 | (1 << (int) CQImode) | (1 << (int) CHImode))
1941
1942 /* Modes for double-word (and smaller) quantities. */
1943 #define D_MODES \
1944 (S_MODES | (1 << (int) DImode) | (1 << (int) DFmode) \
1945 | (1 << (int) CSImode) | (1 << (int) SCmode))
1946
1947 /* Modes for quad-word quantities. */
1948 #define T_MODES \
1949 (D_MODES | (1 << (int) TImode) | (1 << (int) TFmode) \
1950 | (1 << (int) DCmode) | (1 << (int) CDImode))
1951
1952 /* Modes for single-float quantities. We must allow any single word or
1953 smaller quantity. This is because the fix/float conversion instructions
1954 take integer inputs/outputs from the float registers. */
1955 #define SF_MODES (S_MODES)
1956
1957 /* Modes for double-float quantities. */
1958 #define DF_MODES (SF_MODES | (1 << (int) DFmode) | (1 << (int) SCmode))
1959
1960 /* Modes for quad-float quantities. */
1961 #define TF_MODES (DF_MODES | (1 << (int) TFmode) | (1 << (int) DCmode))
1962
1963 /* Value is 1 if register/mode pair is acceptable on sparc.
1964 The funny mixture of D and T modes is because integer operations
1965 do not specially operate on tetra quantities, so non-quad-aligned
1966 registers can hold quadword quantities (except %o4 and %i4 because
1967 they cross fixed registers. */
1968
1969 int hard_regno_mode_ok[] = {
1970 C_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1971 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
1972 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
1973 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
1974
1975 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
1976 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
1977 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
1978 TF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES};
1979 \f
1980 #ifdef __GNUC__
1981 inline
1982 #endif
1983 static int
1984 save_regs (file, low, high, base, offset, n_fregs)
1985 FILE *file;
1986 int low, high;
1987 char *base;
1988 int offset;
1989 int n_fregs;
1990 {
1991 int i;
1992
1993 for (i = low; i < high; i += 2)
1994 {
1995 if (regs_ever_live[i] && ! call_used_regs[i])
1996 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
1997 fprintf (file, "\tstd %s,[%s+%d]\n",
1998 reg_names[i], base, offset + 4 * n_fregs),
1999 n_fregs += 2;
2000 else
2001 fprintf (file, "\tst %s,[%s+%d]\n",
2002 reg_names[i], base, offset + 4 * n_fregs),
2003 n_fregs += 2;
2004 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2005 fprintf (file, "\tst %s,[%s+%d]\n",
2006 reg_names[i+1], base, offset + 4 * n_fregs),
2007 n_fregs += 2;
2008 }
2009 return n_fregs;
2010 }
2011
2012 #ifdef __GNUC__
2013 inline
2014 #endif
2015 static int
2016 restore_regs (file, low, high, base, offset, n_fregs)
2017 FILE *file;
2018 int low, high;
2019 char *base;
2020 int offset;
2021 {
2022 int i;
2023
2024 for (i = low; i < high; i += 2)
2025 {
2026 if (regs_ever_live[i] && ! call_used_regs[i])
2027 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2028 fprintf (file, "\tldd [%s+%d], %s\n",
2029 base, offset + 4 * n_fregs, reg_names[i]),
2030 n_fregs += 2;
2031 else
2032 fprintf (file, "\tld [%s+%d],%s\n",
2033 base, offset + 4 * n_fregs, reg_names[i]),
2034 n_fregs += 2;
2035 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
2036 fprintf (file, "\tld [%s+%d],%s\n",
2037 base, offset + 4 * n_fregs, reg_names[i+1]),
2038 n_fregs += 2;
2039 }
2040 return n_fregs;
2041 }
2042
2043 /* Static variables we want to share between prologue and epilogue. */
2044
2045 /* Number of live floating point registers needed to be saved. */
2046 static int num_fregs;
2047
2048 int
2049 compute_frame_size (size, leaf_function)
2050 int size;
2051 int leaf_function;
2052 {
2053 int fregs_ever_live = 0;
2054 int n_fregs = 0, i;
2055 int outgoing_args_size = (current_function_outgoing_args_size
2056 + REG_PARM_STACK_SPACE (current_function_decl));
2057
2058 apparent_fsize = ((size) + 7 - STARTING_FRAME_OFFSET) & -8;
2059 for (i = 32; i < FIRST_PSEUDO_REGISTER; i += 2)
2060 fregs_ever_live |= regs_ever_live[i]|regs_ever_live[i+1];
2061
2062 if (TARGET_EPILOGUE && fregs_ever_live)
2063 {
2064 for (i = 32; i < FIRST_PSEUDO_REGISTER; i += 2)
2065 if ((regs_ever_live[i] && ! call_used_regs[i])
2066 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
2067 n_fregs += 2;
2068 }
2069
2070 /* Set up values for use in `function_epilogue'. */
2071 num_fregs = n_fregs;
2072
2073 apparent_fsize += (outgoing_args_size+7) & -8;
2074 if (leaf_function && n_fregs == 0
2075 && apparent_fsize == (REG_PARM_STACK_SPACE (current_function_decl)
2076 - STARTING_FRAME_OFFSET))
2077 apparent_fsize = 0;
2078
2079 actual_fsize = apparent_fsize + n_fregs*4;
2080
2081 /* Make sure nothing can clobber our register windows.
2082 If a SAVE must be done, or there is a stack-local variable,
2083 the register window area must be allocated. */
2084 if (leaf_function == 0 || size > 0)
2085 actual_fsize += (16 * UNITS_PER_WORD)+8;
2086
2087 return actual_fsize;
2088 }
2089
2090 /* Output code for the function prologue. */
2091
2092 void
2093 output_function_prologue (file, size, leaf_function)
2094 FILE *file;
2095 int size;
2096 int leaf_function;
2097 {
2098 /* ??? This should be %sp+actual_fsize for a leaf function. I think it
2099 works only because it is never used. */
2100 if (leaf_function)
2101 frame_base_name = "%sp+80";
2102 else
2103 frame_base_name = "%fp";
2104
2105 /* Need to use actual_fsize, since we are also allocating
2106 space for our callee (and our own register save area). */
2107 actual_fsize = compute_frame_size (size, leaf_function);
2108
2109 fprintf (file, "\t!#PROLOGUE# 0\n");
2110 if (actual_fsize == 0)
2111 /* do nothing. */ ;
2112 else if (actual_fsize <= 4096)
2113 {
2114 if (! leaf_function)
2115 fprintf (file, "\tsave %%sp,-%d,%%sp\n", actual_fsize);
2116 else
2117 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize);
2118 }
2119 else if (actual_fsize <= 8192)
2120 {
2121 /* For frames in the range 4097..8192, we can use just two insns. */
2122 if (! leaf_function)
2123 {
2124 fprintf (file, "\tsave %%sp,-4096,%%sp\n");
2125 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
2126 }
2127 else
2128 {
2129 fprintf (file, "\tadd %%sp,-4096,%%sp\n");
2130 fprintf (file, "\tadd %%sp,-%d,%%sp\n", actual_fsize - 4096);
2131 }
2132 }
2133 else
2134 {
2135 if (! leaf_function)
2136 {
2137 fprintf (file, "\tsethi %%hi(-%d),%%g1\n", actual_fsize);
2138 if ((actual_fsize & 0x3ff) != 0)
2139 fprintf (file, "\tor %%g1,%%lo(-%d),%%g1\n", actual_fsize);
2140 fprintf (file, "\tsave %%sp,%%g1,%%sp\n");
2141 }
2142 else
2143 {
2144 fprintf (file, "\tsethi %%hi(-%d),%%g1\n", actual_fsize);
2145 if ((actual_fsize & 0x3ff) != 0)
2146 fprintf (file, "\tor %%g1,%%lo(-%d),%%g1\n", actual_fsize);
2147 fprintf (file, "\tadd %%sp,%%g1,%%sp\n");
2148 }
2149 }
2150
2151 /* If doing anything with PIC, do it now. */
2152 if (! flag_pic)
2153 fprintf (file, "\t!#PROLOGUE# 1\n");
2154
2155 /* Figure out where to save any special registers. */
2156 if (num_fregs)
2157 {
2158 int offset, n_fregs = num_fregs;
2159
2160 /* ??? This should always be -apparent_fsize. */
2161 if (! leaf_function)
2162 offset = -apparent_fsize;
2163 else
2164 offset = 0;
2165
2166 if (TARGET_EPILOGUE && ! leaf_function)
2167 n_fregs = save_regs (file, 0, 16, frame_base_name, offset, 0);
2168 else if (leaf_function)
2169 n_fregs = save_regs (file, 0, 32, frame_base_name, offset, 0);
2170 if (TARGET_EPILOGUE)
2171 save_regs (file, 32, FIRST_PSEUDO_REGISTER,
2172 frame_base_name, offset, n_fregs);
2173 }
2174
2175 leaf_label = 0;
2176 if (leaf_function && actual_fsize != 0)
2177 {
2178 /* warning ("leaf procedure with frame size %d", actual_fsize); */
2179 if (! TARGET_EPILOGUE)
2180 leaf_label = gen_label_rtx ();
2181 }
2182 }
2183
2184 /* Output code for the function epilogue. */
2185
2186 void
2187 output_function_epilogue (file, size, leaf_function)
2188 FILE *file;
2189 int size;
2190 int leaf_function;
2191 {
2192 char *ret;
2193
2194 if (leaf_label)
2195 {
2196 emit_label_after (leaf_label, get_last_insn ());
2197 final_scan_insn (get_last_insn (), file, 0, 0, 1);
2198 }
2199
2200 if (num_fregs)
2201 {
2202 int offset, n_fregs = num_fregs;
2203
2204 /* ??? This should always be -apparent_fsize. */
2205 if (! leaf_function)
2206 offset = -apparent_fsize;
2207 else
2208 offset = 0;
2209
2210 if (TARGET_EPILOGUE && ! leaf_function)
2211 n_fregs = restore_regs (file, 0, 16, frame_base_name, offset, 0);
2212 else if (leaf_function)
2213 n_fregs = restore_regs (file, 0, 32, frame_base_name, offset, 0);
2214 if (TARGET_EPILOGUE)
2215 restore_regs (file, 32, FIRST_PSEUDO_REGISTER,
2216 frame_base_name, offset, n_fregs);
2217 }
2218
2219 /* Work out how to skip the caller's unimp instruction if required. */
2220 if (leaf_function)
2221 ret = (current_function_returns_struct ? "jmp %o7+12" : "retl");
2222 else
2223 ret = (current_function_returns_struct ? "jmp %i7+12" : "ret");
2224
2225 if (TARGET_EPILOGUE || leaf_label)
2226 {
2227 int old_target_epilogue = TARGET_EPILOGUE;
2228 target_flags &= ~old_target_epilogue;
2229
2230 if (! leaf_function)
2231 {
2232 /* If we wound up with things in our delay slot, flush them here. */
2233 if (current_function_epilogue_delay_list)
2234 {
2235 rtx insn = emit_jump_insn_after (gen_rtx (RETURN, VOIDmode),
2236 get_last_insn ());
2237 PATTERN (insn) = gen_rtx (PARALLEL, VOIDmode,
2238 gen_rtvec (2,
2239 PATTERN (XEXP (current_function_epilogue_delay_list, 0)),
2240 PATTERN (insn)));
2241 final_scan_insn (insn, file, 1, 0, 1);
2242 }
2243 else
2244 fprintf (file, "\t%s\n\trestore\n", ret);
2245 }
2246 /* All of the following cases are for leaf functions. */
2247 else if (current_function_epilogue_delay_list)
2248 {
2249 /* eligible_for_epilogue_delay_slot ensures that if this is a
2250 leaf function, then we will only have insn in the delay slot
2251 if the frame size is zero, thus no adjust for the stack is
2252 needed here. */
2253 if (actual_fsize != 0)
2254 abort ();
2255 fprintf (file, "\t%s\n", ret);
2256 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
2257 file, 1, 0, 1);
2258 }
2259 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
2260 avoid generating confusing assembly language output. */
2261 else if (actual_fsize == 0)
2262 fprintf (file, "\t%s\n\tnop\n", ret);
2263 else if (actual_fsize <= 4096)
2264 fprintf (file, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret, actual_fsize);
2265 else if (actual_fsize <= 8192)
2266 fprintf (file, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n",
2267 ret, actual_fsize - 4096);
2268 else if ((actual_fsize & 0x3ff) == 0)
2269 fprintf (file, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
2270 actual_fsize, ret);
2271 else
2272 fprintf (file, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
2273 actual_fsize, actual_fsize, ret);
2274 target_flags |= old_target_epilogue;
2275 }
2276 }
2277
2278 /* Do what is necessary for `va_start'. The argument is ignored;
2279 We look at the current function to determine if stdarg or varargs
2280 is used and return the address of the first unnamed parameter. */
2281
2282 rtx
2283 sparc_builtin_saveregs (arglist)
2284 tree arglist;
2285 {
2286 tree fntype = TREE_TYPE (current_function_decl);
2287 int stdarg = (TYPE_ARG_TYPES (fntype) != 0
2288 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
2289 != void_type_node));
2290 int first_reg = current_function_args_info;
2291 rtx address;
2292 int regno;
2293
2294 #if 0 /* This code seemed to have no effect except to make
2295 varargs not work right when va_list wasn't the first arg. */
2296 if (! stdarg)
2297 first_reg = 0;
2298 #endif
2299
2300 for (regno = first_reg; regno < NPARM_REGS; regno++)
2301 emit_move_insn (gen_rtx (MEM, word_mode,
2302 gen_rtx (PLUS, Pmode,
2303 frame_pointer_rtx,
2304 GEN_INT (STACK_POINTER_OFFSET
2305 + UNITS_PER_WORD * regno))),
2306 gen_rtx (REG, word_mode, BASE_INCOMING_ARG_REG (word_mode)
2307 + regno));
2308
2309 address = gen_rtx (PLUS, Pmode,
2310 frame_pointer_rtx,
2311 GEN_INT (STACK_POINTER_OFFSET
2312 + UNITS_PER_WORD * first_reg));
2313
2314 return address;
2315 }
2316 \f
2317 /* Return the string to output a conditional branch to LABEL, which is
2318 the operand number of the label. OP is the conditional expression. The
2319 mode of register 0 says what kind of comparison we made.
2320
2321 REVERSED is non-zero if we should reverse the sense of the comparison.
2322
2323 ANNUL is non-zero if we should generate an annulling branch.
2324
2325 NOOP is non-zero if we have to follow this branch by a noop. */
2326
2327 char *
2328 output_cbranch (op, label, reversed, annul, noop)
2329 rtx op;
2330 int label;
2331 int reversed, annul, noop;
2332 {
2333 static char string[20];
2334 enum rtx_code code = GET_CODE (op);
2335 enum machine_mode mode = GET_MODE (XEXP (op, 0));
2336 static char labelno[] = " %lX";
2337
2338 /* ??? FP branches can not be preceded by another floating point insn.
2339 Because there is currently no concept of pre-delay slots, we can fix
2340 this only by always emitting a nop before a floating point branch. */
2341
2342 if (mode == CCFPmode || mode == CCFPEmode)
2343 strcpy (string, "nop\n\t");
2344
2345 /* If not floating-point or if EQ or NE, we can just reverse the code. */
2346 if (reversed
2347 && ((mode != CCFPmode && mode != CCFPEmode) || code == EQ || code == NE))
2348 code = reverse_condition (code), reversed = 0;
2349
2350 /* Start by writing the branch condition. */
2351 switch (code)
2352 {
2353 case NE:
2354 if (mode == CCFPmode || mode == CCFPEmode)
2355 strcat (string, "fbne");
2356 else
2357 strcpy (string, "bne");
2358 break;
2359
2360 case EQ:
2361 if (mode == CCFPmode || mode == CCFPEmode)
2362 strcat (string, "fbe");
2363 else
2364 strcpy (string, "be");
2365 break;
2366
2367 case GE:
2368 if (mode == CCFPmode || mode == CCFPEmode)
2369 {
2370 if (reversed)
2371 strcat (string, "fbul");
2372 else
2373 strcat (string, "fbge");
2374 }
2375 else if (mode == CC_NOOVmode)
2376 strcpy (string, "bpos");
2377 else
2378 strcpy (string, "bge");
2379 break;
2380
2381 case GT:
2382 if (mode == CCFPmode || mode == CCFPEmode)
2383 {
2384 if (reversed)
2385 strcat (string, "fbule");
2386 else
2387 strcat (string, "fbg");
2388 }
2389 else
2390 strcpy (string, "bg");
2391 break;
2392
2393 case LE:
2394 if (mode == CCFPmode || mode == CCFPEmode)
2395 {
2396 if (reversed)
2397 strcat (string, "fbug");
2398 else
2399 strcat (string, "fble");
2400 }
2401 else
2402 strcpy (string, "ble");
2403 break;
2404
2405 case LT:
2406 if (mode == CCFPmode || mode == CCFPEmode)
2407 {
2408 if (reversed)
2409 strcat (string, "fbuge");
2410 else
2411 strcat (string, "fbl");
2412 }
2413 else if (mode == CC_NOOVmode)
2414 strcpy (string, "bneg");
2415 else
2416 strcpy (string, "bl");
2417 break;
2418
2419 case GEU:
2420 strcpy (string, "bgeu");
2421 break;
2422
2423 case GTU:
2424 strcpy (string, "bgu");
2425 break;
2426
2427 case LEU:
2428 strcpy (string, "bleu");
2429 break;
2430
2431 case LTU:
2432 strcpy (string, "blu");
2433 break;
2434 }
2435
2436 /* Now add the annulling, the label, and a possible noop. */
2437 if (annul)
2438 strcat (string, ",a");
2439
2440 labelno[3] = label + '0';
2441 strcat (string, labelno);
2442
2443 if (noop)
2444 strcat (string, "\n\tnop");
2445
2446 return string;
2447 }
2448
2449 /* Output assembler code to return from a function. */
2450
2451 char *
2452 output_return (operands)
2453 rtx *operands;
2454 {
2455 if (leaf_label)
2456 {
2457 operands[0] = leaf_label;
2458 return "b,a %l0";
2459 }
2460 else if (leaf_function)
2461 {
2462 /* If we didn't allocate a frame pointer for the current function,
2463 the stack pointer might have been adjusted. Output code to
2464 restore it now. */
2465
2466 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize);
2467
2468 /* Use sub of negated value in first two cases instead of add to
2469 allow actual_fsize == 4096. */
2470
2471 if (actual_fsize <= 4096)
2472 {
2473 if (current_function_returns_struct)
2474 return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp";
2475 else
2476 return "retl\n\tsub %%sp,-%0,%%sp";
2477 }
2478 else if (actual_fsize <= 8192)
2479 {
2480 operands[0] = gen_rtx (CONST_INT, VOIDmode, actual_fsize - 4096);
2481 if (current_function_returns_struct)
2482 return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp";
2483 else
2484 return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp";
2485 }
2486 else if (current_function_returns_struct)
2487 {
2488 if ((actual_fsize & 0x3ff) != 0)
2489 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
2490 else
2491 return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
2492 }
2493 else
2494 {
2495 if ((actual_fsize & 0x3ff) != 0)
2496 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
2497 else
2498 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
2499 }
2500 }
2501 else
2502 {
2503 if (current_function_returns_struct)
2504 return "jmp %%i7+12\n\trestore";
2505 else
2506 return "ret\n\trestore";
2507 }
2508 }
2509 \f
2510 /* Leaf functions and non-leaf functions have different needs. */
2511
2512 static int
2513 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
2514
2515 static int
2516 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
2517
2518 static int *reg_alloc_orders[] = {
2519 reg_leaf_alloc_order,
2520 reg_nonleaf_alloc_order};
2521
2522 void
2523 order_regs_for_local_alloc ()
2524 {
2525 static int last_order_nonleaf = 1;
2526
2527 if (regs_ever_live[15] != last_order_nonleaf)
2528 {
2529 last_order_nonleaf = !last_order_nonleaf;
2530 bcopy (reg_alloc_orders[last_order_nonleaf], reg_alloc_order,
2531 FIRST_PSEUDO_REGISTER * sizeof (int));
2532 }
2533 }
2534 \f
2535 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
2536 This makes them candidates for using ldd and std insns.
2537
2538 Note reg1 and reg2 *must* be hard registers. To be sure we will
2539 abort if we are passed pseudo registers. */
2540
2541 int
2542 registers_ok_for_ldd_peep (reg1, reg2)
2543 rtx reg1, reg2;
2544 {
2545
2546 /* We might have been passed a SUBREG. */
2547 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
2548 return 0;
2549
2550 if (REGNO (reg1) % 2 != 0)
2551 return 0;
2552
2553 return (REGNO (reg1) == REGNO (reg2) - 1);
2554
2555 }
2556
2557 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
2558 std insn.
2559
2560 This can only happen when addr1 and addr2 are consecutive memory
2561 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
2562 64 bit boundary (addr1 % 8 == 0).
2563
2564 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
2565 registers are assumed to *never* be properly aligned and are
2566 rejected.
2567
2568 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
2569 need only check that the offset for addr1 % 8 == 0. */
2570
2571 int
2572 addrs_ok_for_ldd_peep (addr1, addr2)
2573 rtx addr1, addr2;
2574 {
2575 int reg1, offset1;
2576
2577 /* Extract a register number and offset (if used) from the first addr. */
2578 if (GET_CODE (addr1) == PLUS)
2579 {
2580 /* If not a REG, return zero. */
2581 if (GET_CODE (XEXP (addr1, 0)) != REG)
2582 return 0;
2583 else
2584 {
2585 reg1 = REGNO (XEXP (addr1, 0));
2586 /* The offset must be constant! */
2587 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
2588 return 0;
2589 offset1 = INTVAL (XEXP (addr1, 1));
2590 }
2591 }
2592 else if (GET_CODE (addr1) != REG)
2593 return 0;
2594 else
2595 {
2596 reg1 = REGNO (addr1);
2597 /* This was a simple (mem (reg)) expression. Offset is 0. */
2598 offset1 = 0;
2599 }
2600
2601 /* Make sure the second address is a (mem (plus (reg) (const_int). */
2602 if (GET_CODE (addr2) != PLUS)
2603 return 0;
2604
2605 if (GET_CODE (XEXP (addr2, 0)) != REG
2606 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
2607 return 0;
2608
2609 /* Only %fp and %sp are allowed. Additionally both addresses must
2610 use the same register. */
2611 if (reg1 != FRAME_POINTER_REGNUM && reg1 != STACK_POINTER_REGNUM)
2612 return 0;
2613
2614 if (reg1 != REGNO (XEXP (addr2, 0)))
2615 return 0;
2616
2617 /* The first offset must be evenly divisible by 8 to ensure the
2618 address is 64 bit aligned. */
2619 if (offset1 % 8 != 0)
2620 return 0;
2621
2622 /* The offset for the second addr must be 4 more than the first addr. */
2623 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
2624 return 0;
2625
2626 /* All the tests passed. addr1 and addr2 are valid for ldd and std
2627 instructions. */
2628 return 1;
2629 }
2630
2631 /* Return 1 if reg is a pseudo, or is the first register in
2632 a hard register pair. This makes it a candidate for use in
2633 ldd and std insns. */
2634
2635 int
2636 register_ok_for_ldd (reg)
2637 rtx reg;
2638 {
2639
2640 /* We might have been passed a SUBREG. */
2641 if (GET_CODE (reg) != REG)
2642 return 0;
2643
2644 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
2645 return (REGNO (reg) % 2 == 0);
2646 else
2647 return 1;
2648
2649 }
2650 \f
2651 /* Print operand X (an rtx) in assembler syntax to file FILE.
2652 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2653 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2654
2655 void
2656 print_operand (file, x, code)
2657 FILE *file;
2658 rtx x;
2659 int code;
2660 {
2661 switch (code)
2662 {
2663 case '#':
2664 /* Output a 'nop' if there's nothing for the delay slot. */
2665 if (dbr_sequence_length () == 0)
2666 fputs ("\n\tnop", file);
2667 return;
2668 case '*':
2669 /* Output an annul flag if there's nothing for the delay slot and we
2670 are optimizing. This is always used with '(' below. */
2671 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
2672 this is a dbx bug. So, we only do this when optimizing. */
2673 if (dbr_sequence_length () == 0 && optimize)
2674 fputs (",a", file);
2675 return;
2676 case '(':
2677 /* Output a 'nop' if there's nothing for the delay slot and we are
2678 not optimizing. This is always used with '*' above. */
2679 if (dbr_sequence_length () == 0 && ! optimize)
2680 fputs ("\n\tnop", file);
2681 return;
2682 case 'Y':
2683 /* Adjust the operand to take into account a RESTORE operation. */
2684 if (GET_CODE (x) != REG)
2685 output_operand_lossage ("Invalid %%Y operand");
2686 else if (REGNO (x) < 8)
2687 fputs (reg_names[REGNO (x)], file);
2688 else if (REGNO (x) >= 24 && REGNO (x) < 32)
2689 fputs (reg_names[REGNO (x)-16], file);
2690 else
2691 output_operand_lossage ("Invalid %%Y operand");
2692 return;
2693 case 'R':
2694 /* Print out the second register name of a register pair or quad.
2695 I.e., R (%o0) => %o1. */
2696 fputs (reg_names[REGNO (x)+1], file);
2697 return;
2698 case 'S':
2699 /* Print out the third register name of a register quad.
2700 I.e., S (%o0) => %o2. */
2701 fputs (reg_names[REGNO (x)+2], file);
2702 return;
2703 case 'T':
2704 /* Print out the fourth register name of a register quad.
2705 I.e., T (%o0) => %o3. */
2706 fputs (reg_names[REGNO (x)+3], file);
2707 return;
2708 case 'm':
2709 /* Print the operand's address only. */
2710 output_address (XEXP (x, 0));
2711 return;
2712 case 'r':
2713 /* In this case we need a register. Use %g0 if the
2714 operand is const0_rtx. */
2715 if (x == const0_rtx
2716 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
2717 {
2718 fputs ("%g0", file);
2719 return;
2720 }
2721 else
2722 break;
2723
2724 case 'A':
2725 switch (GET_CODE (x))
2726 {
2727 case IOR: fputs ("or", file); break;
2728 case AND: fputs ("and", file); break;
2729 case XOR: fputs ("xor", file); break;
2730 default: output_operand_lossage ("Invalid %%A operand");
2731 }
2732 return;
2733
2734 case 'B':
2735 switch (GET_CODE (x))
2736 {
2737 case IOR: fputs ("orn", file); break;
2738 case AND: fputs ("andn", file); break;
2739 case XOR: fputs ("xnor", file); break;
2740 default: output_operand_lossage ("Invalid %%B operand");
2741 }
2742 return;
2743
2744 case 'b':
2745 {
2746 /* Print a sign-extended character. */
2747 int i = INTVAL (x) & 0xff;
2748 if (i & 0x80)
2749 i |= 0xffffff00;
2750 fprintf (file, "%d", i);
2751 return;
2752 }
2753
2754 case 0:
2755 /* Do nothing special. */
2756 break;
2757
2758 default:
2759 /* Undocumented flag. */
2760 output_operand_lossage ("invalid operand output code");
2761 }
2762
2763 if (GET_CODE (x) == REG)
2764 fputs (reg_names[REGNO (x)], file);
2765 else if (GET_CODE (x) == MEM)
2766 {
2767 fputc ('[', file);
2768 if (CONSTANT_P (XEXP (x, 0)))
2769 /* Poor Sun assembler doesn't understand absolute addressing. */
2770 fputs ("%g0+", file);
2771 output_address (XEXP (x, 0));
2772 fputc (']', file);
2773 }
2774 else if (GET_CODE (x) == HIGH)
2775 {
2776 fputs ("%hi(", file);
2777 output_addr_const (file, XEXP (x, 0));
2778 fputc (')', file);
2779 }
2780 else if (GET_CODE (x) == LO_SUM)
2781 {
2782 print_operand (file, XEXP (x, 0), 0);
2783 fputs ("+%lo(", file);
2784 output_addr_const (file, XEXP (x, 1));
2785 fputc (')', file);
2786 }
2787 else if (GET_CODE (x) == CONST_DOUBLE
2788 && (GET_MODE (x) == VOIDmode
2789 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
2790 {
2791 if (CONST_DOUBLE_HIGH (x) == 0)
2792 fprintf (file, "%u", CONST_DOUBLE_LOW (x));
2793 else if (CONST_DOUBLE_HIGH (x) == -1
2794 && CONST_DOUBLE_LOW (x) < 0)
2795 fprintf (file, "%d", CONST_DOUBLE_LOW (x));
2796 else
2797 output_operand_lossage ("long long constant not a valid immediate operand");
2798 }
2799 else if (GET_CODE (x) == CONST_DOUBLE)
2800 output_operand_lossage ("floating point constant not a valid immediate operand");
2801 else { output_addr_const (file, x); }
2802 }
2803 \f
2804 /* This function outputs assembler code for VALUE to FILE, where VALUE is
2805 a 64 bit (DImode) value. */
2806
2807 /* ??? If there is a 64 bit counterpart to .word that the assembler
2808 understands, then using that would simply this code greatly. */
2809
2810 void
2811 output_double_int (file, value)
2812 FILE *file;
2813 rtx value;
2814 {
2815 if (GET_CODE (value) == CONST_INT)
2816 {
2817 if (INTVAL (value) < 0)
2818 ASM_OUTPUT_INT (file, constm1_rtx);
2819 else
2820 ASM_OUTPUT_INT (file, const0_rtx);
2821 ASM_OUTPUT_INT (file, value);
2822 }
2823 else if (GET_CODE (value) == CONST_DOUBLE)
2824 {
2825 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
2826 CONST_DOUBLE_HIGH (value)));
2827 ASM_OUTPUT_INT (file, gen_rtx (CONST_INT, VOIDmode,
2828 CONST_DOUBLE_LOW (value)));
2829 }
2830 else if (GET_CODE (value) == SYMBOL_REF
2831 || GET_CODE (value) == CONST
2832 || GET_CODE (value) == PLUS)
2833 {
2834 /* Addresses are only 32 bits. */
2835 ASM_OUTPUT_INT (file, const0_rtx);
2836 ASM_OUTPUT_INT (file, value);
2837 }
2838 else
2839 abort ();
2840 }
2841 \f
2842 #ifndef CHAR_TYPE_SIZE
2843 #define CHAR_TYPE_SIZE BITS_PER_UNIT
2844 #endif
2845
2846 #ifndef SHORT_TYPE_SIZE
2847 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
2848 #endif
2849
2850 #ifndef INT_TYPE_SIZE
2851 #define INT_TYPE_SIZE BITS_PER_WORD
2852 #endif
2853
2854 #ifndef LONG_TYPE_SIZE
2855 #define LONG_TYPE_SIZE BITS_PER_WORD
2856 #endif
2857
2858 #ifndef LONG_LONG_TYPE_SIZE
2859 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
2860 #endif
2861
2862 #ifndef FLOAT_TYPE_SIZE
2863 #define FLOAT_TYPE_SIZE BITS_PER_WORD
2864 #endif
2865
2866 #ifndef DOUBLE_TYPE_SIZE
2867 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
2868 #endif
2869
2870 #ifndef LONG_DOUBLE_TYPE_SIZE
2871 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
2872 #endif
2873
2874 unsigned long
2875 sparc_type_code (type)
2876 register tree type;
2877 {
2878 register unsigned long qualifiers = 0;
2879 register unsigned shift = 6;
2880
2881 for (;;)
2882 {
2883 switch (TREE_CODE (type))
2884 {
2885 case ERROR_MARK:
2886 return qualifiers;
2887
2888 case ARRAY_TYPE:
2889 qualifiers |= (3 << shift);
2890 shift += 2;
2891 type = TREE_TYPE (type);
2892 break;
2893
2894 case FUNCTION_TYPE:
2895 case METHOD_TYPE:
2896 qualifiers |= (2 << shift);
2897 shift += 2;
2898 type = TREE_TYPE (type);
2899 break;
2900
2901 case POINTER_TYPE:
2902 case REFERENCE_TYPE:
2903 case OFFSET_TYPE:
2904 qualifiers |= (1 << shift);
2905 shift += 2;
2906 type = TREE_TYPE (type);
2907 break;
2908
2909 case RECORD_TYPE:
2910 return (qualifiers | 8);
2911
2912 case UNION_TYPE:
2913 return (qualifiers | 9);
2914
2915 case ENUMERAL_TYPE:
2916 return (qualifiers | 10);
2917
2918 case VOID_TYPE:
2919 return (qualifiers | 16);
2920
2921 case INTEGER_TYPE:
2922 /* Carefully distinguish all the standard types of C,
2923 without messing up if the language is not C.
2924 Note that we check only for the names that contain spaces;
2925 other names might occur by coincidence in other languages. */
2926 if (TYPE_NAME (type) != 0
2927 && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL
2928 && DECL_NAME (TYPE_NAME (type)) != 0
2929 && TREE_CODE (DECL_NAME (TYPE_NAME (type))) == IDENTIFIER_NODE)
2930 {
2931 char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
2932
2933 if (!strcmp (name, "unsigned char"))
2934 return (qualifiers | 12);
2935 if (!strcmp (name, "signed char"))
2936 return (qualifiers | 2);
2937 if (!strcmp (name, "unsigned int"))
2938 return (qualifiers | 14);
2939 if (!strcmp (name, "short int"))
2940 return (qualifiers | 3);
2941 if (!strcmp (name, "short unsigned int"))
2942 return (qualifiers | 13);
2943 if (!strcmp (name, "long int"))
2944 return (qualifiers | 5);
2945 if (!strcmp (name, "long unsigned int"))
2946 return (qualifiers | 15);
2947 if (!strcmp (name, "long long int"))
2948 return (qualifiers | 5); /* Who knows? */
2949 if (!strcmp (name, "long long unsigned int"))
2950 return (qualifiers | 15); /* Who knows? */
2951 }
2952
2953 /* Most integer types will be sorted out above, however, for the
2954 sake of special `array index' integer types, the following code
2955 is also provided. */
2956
2957 if (TYPE_PRECISION (type) == INT_TYPE_SIZE)
2958 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
2959
2960 if (TYPE_PRECISION (type) == LONG_TYPE_SIZE)
2961 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
2962
2963 if (TYPE_PRECISION (type) == LONG_LONG_TYPE_SIZE)
2964 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
2965
2966 if (TYPE_PRECISION (type) == SHORT_TYPE_SIZE)
2967 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
2968
2969 if (TYPE_PRECISION (type) == CHAR_TYPE_SIZE)
2970 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
2971
2972 abort ();
2973
2974 case REAL_TYPE:
2975 /* Carefully distinguish all the standard types of C,
2976 without messing up if the language is not C. */
2977 if (TYPE_NAME (type) != 0
2978 && TREE_CODE (TYPE_NAME (type)) == TYPE_DECL
2979 && DECL_NAME (TYPE_NAME (type)) != 0
2980 && TREE_CODE (DECL_NAME (TYPE_NAME (type))) == IDENTIFIER_NODE)
2981 {
2982 char *name = IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)));
2983
2984 if (!strcmp (name, "long double"))
2985 return (qualifiers | 7); /* Who knows? */
2986 }
2987
2988 if (TYPE_PRECISION (type) == DOUBLE_TYPE_SIZE)
2989 return (qualifiers | 7);
2990 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
2991 return (qualifiers | 6);
2992 if (TYPE_PRECISION (type) == LONG_DOUBLE_TYPE_SIZE)
2993 return (qualifiers | 7); /* Who knows? */
2994 abort ();
2995
2996 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
2997 /* ??? We need to distinguish between double and float complex types,
2998 but I don't know how yet because I can't reach this code from
2999 existing front-ends. */
3000 return (qualifiers | 7); /* Who knows? */
3001
3002 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
3003 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
3004 case FILE_TYPE: /* GNU Pascal FILE type. */
3005 case STRING_TYPE: /* GNU Fortran STRING type. */
3006 case SET_TYPE: /* GNU Pascal SET type. */
3007 case LANG_TYPE: /* ? */
3008 return qualifiers;
3009
3010 default:
3011 abort (); /* Not a type! */
3012 }
3013 }
3014 }
3015 \f
3016 /* Subroutines to support a flat (single) register window calling
3017 convention. */
3018
3019 /* Single-register window sparc stack frames look like:
3020
3021 Before call After call
3022 +-----------------------+ +-----------------------+
3023 high | | | |
3024 mem. | | | |
3025 | caller's temps. | | caller's temps. |
3026 | | | |
3027 +-----------------------+ +-----------------------+
3028 | | | |
3029 | arguments on stack. | | arguments on stack. |
3030 | |FP+92->| |
3031 +-----------------------+ +-----------------------+
3032 | 6 words to save | | 6 words to save |
3033 | arguments passed | | arguments passed |
3034 | in registers, even | | in registers, even |
3035 SP+68->| if not passed. |FP+68->| if not passed. |
3036 +-----------------------+ +-----------------------+
3037 | 1 word struct addr |FP+64->| 1 word struct addr |
3038 +-----------------------+ +-----------------------+
3039 | | | |
3040 | 16 word reg save area | | 16 word reg save area |
3041 SP->| | FP->| |
3042 +-----------------------+ +-----------------------+
3043 | 4 word area for |
3044 FP-16->| fp/alu reg moves |
3045 +-----------------------+
3046 | |
3047 | local variables |
3048 | |
3049 +-----------------------+
3050 | |
3051 | fp register save |
3052 | |
3053 +-----------------------+
3054 | |
3055 | gp register save |
3056 | |
3057 +-----------------------+
3058 | |
3059 | alloca allocations |
3060 | |
3061 +-----------------------+
3062 | |
3063 | arguments on stack |
3064 SP+92->| |
3065 +-----------------------+
3066 | 6 words to save |
3067 | arguments passed |
3068 | in registers, even |
3069 low SP+68->| if not passed. |
3070 memory +-----------------------+
3071 SP+64->| 1 word struct addr |
3072 +-----------------------+
3073 | |
3074 I 16 word reg save area |
3075 SP->| |
3076 +-----------------------+ */
3077
3078 /* Structure to be filled in by sparc_frw_compute_frame_size with register
3079 save masks, and offsets for the current function. */
3080
3081 struct sparc_frame_info
3082 {
3083 unsigned long total_size; /* # bytes that the entire frame takes up. */
3084 unsigned long var_size; /* # bytes that variables take up. */
3085 unsigned long args_size; /* # bytes that outgoing arguments take up. */
3086 unsigned long extra_size; /* # bytes of extra gunk. */
3087 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
3088 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
3089 unsigned long mask; /* Mask of saved gp registers. */
3090 unsigned long fmask; /* Mask of saved fp registers. */
3091 unsigned long gp_sp_offset; /* Offset from new sp to store gp regs. */
3092 unsigned long fp_sp_offset; /* Offset from new sp to store fp regs. */
3093 int initialized; /* Nonzero if frame size already calculated. */
3094 };
3095
3096 /* Current frame information calculated by sparc_frw_compute_frame_size. */
3097 struct sparc_frame_info current_frame_info;
3098
3099 /* Zero structure to initialize current_frame_info. */
3100 struct sparc_frame_info zero_frame_info;
3101
3102 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
3103
3104 #define MUST_SAVE_REGISTER(regno) \
3105 ((regs_ever_live[regno] && !call_used_regs[regno]) \
3106 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
3107 || (regno == 15 && regs_ever_live[15]))
3108
3109 /* Return the bytes needed to compute the frame pointer from the current
3110 stack pointer. */
3111
3112 unsigned long
3113 sparc_frw_compute_frame_size (size)
3114 int size; /* # of var. bytes allocated. */
3115 {
3116 int regno;
3117 unsigned long total_size; /* # bytes that the entire frame takes up. */
3118 unsigned long var_size; /* # bytes that variables take up. */
3119 unsigned long args_size; /* # bytes that outgoing arguments take up. */
3120 unsigned long extra_size; /* # extra bytes. */
3121 unsigned int gp_reg_size; /* # bytes needed to store gp regs. */
3122 unsigned int fp_reg_size; /* # bytes needed to store fp regs. */
3123 unsigned long mask; /* Mask of saved gp registers. */
3124 unsigned long fmask; /* Mask of saved fp registers. */
3125
3126 /* This is the size of the 16 word reg save area, 1 word struct addr
3127 area, and 4 word fp/alu register copy area. */
3128 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
3129 var_size = size;
3130 /* Also include the size needed for the 6 parameter registers. */
3131 args_size = current_function_outgoing_args_size + 24;
3132 total_size = var_size + args_size + extra_size;
3133 gp_reg_size = 0;
3134 fp_reg_size = 0;
3135 mask = 0;
3136 fmask = 0;
3137
3138 /* Calculate space needed for gp registers. */
3139 for (regno = 1; regno <= 31; regno++)
3140 {
3141 if (MUST_SAVE_REGISTER (regno))
3142 {
3143 if ((regno & 0x1) == 0 && MUST_SAVE_REGISTER (regno+1))
3144 {
3145 if (gp_reg_size % 8 != 0)
3146 gp_reg_size += UNITS_PER_WORD;
3147 gp_reg_size += 2 * UNITS_PER_WORD;
3148 mask |= 3 << regno;
3149 regno++;
3150 }
3151 else
3152 {
3153 gp_reg_size += UNITS_PER_WORD;
3154 mask |= 1 << regno;
3155 }
3156 }
3157 }
3158 /* Add extra word in case we have to align the space to a double word
3159 boundary. */
3160 if (gp_reg_size != 0)
3161 gp_reg_size += UNITS_PER_WORD;
3162
3163 /* Calculate space needed for fp registers. */
3164 for (regno = 32; regno <= 63; regno++)
3165 {
3166 if (regs_ever_live[regno] && !call_used_regs[regno])
3167 {
3168 fp_reg_size += UNITS_PER_WORD;
3169 fmask |= 1 << (regno - 32);
3170 }
3171 }
3172
3173 total_size += gp_reg_size + fp_reg_size;
3174
3175 if (total_size == extra_size)
3176 total_size = extra_size = 0;
3177
3178 total_size = SPARC_STACK_ALIGN (total_size);
3179
3180 /* Save other computed information. */
3181 current_frame_info.total_size = total_size;
3182 current_frame_info.var_size = var_size;
3183 current_frame_info.args_size = args_size;
3184 current_frame_info.extra_size = extra_size;
3185 current_frame_info.gp_reg_size = gp_reg_size;
3186 current_frame_info.fp_reg_size = fp_reg_size;
3187 current_frame_info.mask = mask;
3188 current_frame_info.fmask = fmask;
3189 current_frame_info.initialized = reload_completed;
3190
3191 if (mask)
3192 {
3193 unsigned long offset = args_size;
3194 if (extra_size)
3195 offset += FIRST_PARM_OFFSET(0);
3196 current_frame_info.gp_sp_offset = offset;
3197 }
3198
3199 if (fmask)
3200 {
3201 unsigned long offset = args_size + gp_reg_size;
3202 if (extra_size)
3203 offset += FIRST_PARM_OFFSET(0);
3204 current_frame_info.fp_sp_offset = offset;
3205 }
3206
3207 /* Ok, we're done. */
3208 return total_size;
3209 }
3210 \f
3211 /* Common code to save/restore registers. */
3212
3213 void
3214 sparc_frw_save_restore (file, word_op, doubleword_op)
3215 FILE *file; /* Stream to write to. */
3216 char *word_op; /* Operation to do for one word. */
3217 char *doubleword_op; /* Operation to do for doubleword. */
3218 {
3219 int regno;
3220 unsigned long mask = current_frame_info.mask;
3221 unsigned long fmask = current_frame_info.fmask;
3222 unsigned long gp_offset;
3223 unsigned long fp_offset;
3224 unsigned long max_offset;
3225 char *base_reg;
3226
3227 if (mask == 0 && fmask == 0)
3228 return;
3229
3230 base_reg = reg_names[STACK_POINTER_REGNUM];
3231 gp_offset = current_frame_info.gp_sp_offset;
3232 fp_offset = current_frame_info.fp_sp_offset;
3233 max_offset = (gp_offset > fp_offset) ? gp_offset : fp_offset;
3234
3235 /* Deal with calling functions with a large structure. */
3236 if (max_offset >= 4096)
3237 {
3238 char *temp = "%g2";
3239 fprintf (file, "\tset %ld,%s\n", max_offset, temp);
3240 fprintf (file, "\tadd %s,%s,%s\n", temp, base_reg, temp);
3241 base_reg = temp;
3242 gp_offset = max_offset - gp_offset;
3243 fp_offset = max_offset - fp_offset;
3244 }
3245
3246 /* Save registers starting from high to low. The debuggers prefer
3247 at least the return register be stored at func+4, and also it
3248 allows us not to need a nop in the epilog if at least one
3249 register is reloaded in addition to return address. */
3250
3251 if (mask || frame_pointer_needed)
3252 {
3253 for (regno = 1; regno <= 31; regno++)
3254 {
3255 if ((mask & (1L << regno)) != 0
3256 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed))
3257 {
3258 if ((regno & 0x1) == 0 && ((mask & (1L << (regno+1))) != 0))
3259 {
3260 if (gp_offset % 8 != 0)
3261 gp_offset += UNITS_PER_WORD;
3262
3263 if (word_op[0] == 's')
3264 fprintf (file, "\t%s %s,[%s+%d]\n",
3265 doubleword_op, reg_names[regno],
3266 base_reg, gp_offset);
3267 else
3268 fprintf (file, "\t%s [%s+%d],%s\n",
3269 doubleword_op, base_reg, gp_offset,
3270 reg_names[regno]);
3271
3272 gp_offset += 2 * UNITS_PER_WORD;
3273 regno++;
3274 }
3275 else
3276 {
3277 if (word_op[0] == 's')
3278 fprintf (file, "\t%s %s,[%s+%d]\n",
3279 word_op, reg_names[regno],
3280 base_reg, gp_offset);
3281 else
3282 fprintf (file, "\t%s [%s+%d],%s\n",
3283 word_op, base_reg, gp_offset, reg_names[regno]);
3284
3285 gp_offset += UNITS_PER_WORD;
3286 }
3287 }
3288 }
3289 }
3290
3291 if (fmask)
3292 {
3293 for (regno = 32; regno <= 63; regno++)
3294 {
3295 if ((fmask & (1L << (regno - 32))) != 0)
3296 {
3297 if (word_op[0] == 's')
3298 fprintf (file, "\t%s %s,[%s+%d]\n",
3299 word_op, reg_names[regno],
3300 base_reg, gp_offset);
3301 else
3302 fprintf (file, "\t%s [%s+%d],%s\n",
3303 word_op, base_reg, gp_offset, reg_names[regno]);
3304
3305 fp_offset += UNITS_PER_WORD;
3306 }
3307 }
3308 }
3309 }
3310 \f
3311 /* Set up the stack and frame (if desired) for the function. */
3312
3313 void
3314 sparc_frw_output_function_prologue (file, size, ignored)
3315 FILE *file;
3316 int size;
3317 {
3318 extern char call_used_regs[];
3319 int tsize;
3320 char *sp_str = reg_names[STACK_POINTER_REGNUM];
3321
3322 /* ??? This should be %sp+actual_fsize for a leaf function. I think it
3323 works only because it is never used. */
3324 frame_base_name
3325 = (!frame_pointer_needed) ? "%sp+80" : reg_names[FRAME_POINTER_REGNUM];
3326
3327 fprintf (file, "\t!#PROLOGUE# 0\n");
3328
3329 size = SPARC_STACK_ALIGN (size);
3330 tsize = (! current_frame_info.initialized
3331 ? sparc_frw_compute_frame_size (size)
3332 : current_frame_info.total_size);
3333
3334 if (tsize > 0)
3335 {
3336 if (tsize <= 4095)
3337 fprintf (file,
3338 "\tsub %s,%d,%s\t\t!# vars= %d, regs= %d/%d, args = %d, extra= %d\n",
3339 sp_str, tsize, sp_str, current_frame_info.var_size,
3340 current_frame_info.gp_reg_size / 4,
3341 current_frame_info.fp_reg_size / 8,
3342 current_function_outgoing_args_size,
3343 current_frame_info.extra_size);
3344 else
3345 fprintf (file,
3346 "\tset %d,%s\n\tsub\t%s,%s,%s\t\t!# vars= %d, regs= %d/%d, args = %d, sfo= %d\n",
3347 tsize, "%g1", sp_str, "%g1",
3348 sp_str, current_frame_info.var_size,
3349 current_frame_info.gp_reg_size / 4,
3350 current_frame_info.fp_reg_size / 8,
3351 current_function_outgoing_args_size,
3352 current_frame_info.extra_size);
3353 }
3354
3355 sparc_frw_save_restore (file, "st", "std");
3356
3357 if (frame_pointer_needed)
3358 {
3359 if (tsize <= 4095)
3360 fprintf (file, "\tadd %s,%d,%s\t!# set up frame pointer\n", sp_str,
3361 tsize, frame_base_name);
3362 else
3363 fprintf (file, "\tadd %s,%s,%s\t!# set up frame pointer\n", sp_str,
3364 "%g1", frame_base_name);
3365 }
3366 }
3367 \f
3368 /* Do any necessary cleanup after a function to restore stack, frame,
3369 and regs. */
3370
3371 void
3372 sparc_frw_output_function_epilogue (file, size, ignored1, ignored2)
3373 FILE *file;
3374 int size;
3375 {
3376 extern FILE *asm_out_data_file, *asm_out_file;
3377 extern char call_used_regs[];
3378 extern int frame_pointer_needed;
3379 int tsize;
3380 char *sp_str = reg_names[STACK_POINTER_REGNUM];
3381 char *t1_str = "%g1";
3382 rtx epilogue_delay = current_function_epilogue_delay_list;
3383 int noepilogue = FALSE;
3384
3385 /* The epilogue does not depend on any registers, but the stack
3386 registers, so we assume that if we have 1 pending nop, it can be
3387 ignored, and 2 it must be filled (2 nops occur for integer
3388 multiply and divide). */
3389
3390 size = SPARC_STACK_ALIGN (size);
3391 tsize = (!current_frame_info.initialized
3392 ? sparc_frw_compute_frame_size (size)
3393 : current_frame_info.total_size);
3394
3395 if (tsize == 0 && epilogue_delay == 0)
3396 {
3397 rtx insn = get_last_insn ();
3398
3399 /* If the last insn was a BARRIER, we don't have to write any code
3400 because a jump (aka return) was put there. */
3401 if (GET_CODE (insn) == NOTE)
3402 insn = prev_nonnote_insn (insn);
3403 if (insn && GET_CODE (insn) == BARRIER)
3404 noepilogue = TRUE;
3405 }
3406
3407 if (!noepilogue)
3408 {
3409 /* In the reload sequence, we don't need to fill the load delay
3410 slots for most of the loads, also see if we can fill the final
3411 delay slot if not otherwise filled by the reload sequence. */
3412
3413 if (tsize > 4095)
3414 fprintf (file, "\tset %d,%s\n", tsize, t1_str);
3415
3416 if (frame_pointer_needed)
3417 {
3418 char *fp_str = reg_names[FRAME_POINTER_REGNUM];
3419 if (tsize > 4095)
3420 fprintf (file,"\tsub %s,%s,%s\t\t!# sp not trusted here\n",
3421 fp_str, t1_str, sp_str);
3422 else
3423 fprintf (file,"\tsub %s,%d,%s\t\t!# sp not trusted here\n",
3424 fp_str, tsize, sp_str);
3425 }
3426
3427 sparc_frw_save_restore (file, "ld", "ldd");
3428
3429 if (current_function_returns_struct)
3430 fprintf (file, "\tjmp %%o7+12\n");
3431 else
3432 fprintf (file, "\tretl\n");
3433
3434 /* If the only register saved is the return address, we need a
3435 nop, unless we have an instruction to put into it. Otherwise
3436 we don't since reloading multiple registers doesn't reference
3437 the register being loaded. */
3438
3439 if (epilogue_delay)
3440 {
3441 if (tsize)
3442 abort ();
3443 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1);
3444 }
3445
3446 else if (tsize > 4095)
3447 fprintf (file, "\tadd %s,%s,%s\n", sp_str, t1_str, sp_str);
3448
3449 else if (tsize > 0)
3450 fprintf (file, "\tadd %s,%d,%s\n", sp_str, tsize, sp_str);
3451
3452 else
3453 fprintf (file, "\tnop\n");
3454 }
3455
3456 /* Reset state info for each function. */
3457 current_frame_info = zero_frame_info;
3458 }
3459 \f
3460 /* Define the number of delay slots needed for the function epilogue.
3461
3462 On the sparc, we need a slot if either no stack has been allocated,
3463 or the only register saved is the return register. */
3464
3465 int
3466 sparc_frw_epilogue_delay_slots ()
3467 {
3468 if (!current_frame_info.initialized)
3469 (void) sparc_frw_compute_frame_size (get_frame_size ());
3470
3471 if (current_frame_info.total_size == 0)
3472 return 1;
3473
3474 return 0;
3475 }
3476
3477 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
3478 Any single length instruction which doesn't reference the stack or frame
3479 pointer is OK. */
3480
3481 int
3482 sparc_frw_eligible_for_epilogue_delay (trial, slot)
3483 rtx trial;
3484 int slot;
3485 {
3486 if (get_attr_length (trial) == 1
3487 && ! reg_mentioned_p (stack_pointer_rtx, PATTERN (trial))
3488 && ! reg_mentioned_p (frame_pointer_rtx, PATTERN (trial)))
3489 return 1;
3490 return 0;
3491 }
GNU Compiler Collection
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