1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH.
2 Copyright (C) 1993-2015 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
25 #include "config/vxworks-dummy.h"
27 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't
28 include it here, because bconfig.h is also included by gencodes.c . */
29 /* ??? No longer true. */
30 extern int code_for_indirect_jump_scratch
;
32 #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)
34 /* Value should be nonzero if functions must have frame pointers.
35 Zero means the frame pointer need not be set up (and parms may be accessed
36 via the stack pointer) in functions that seem suitable. */
38 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED
39 #define SUBTARGET_FRAME_POINTER_REQUIRED 0
43 /* Nonzero if this is an ELF target - compile time only */
46 /* Nonzero if we should generate code using type 2E insns. */
47 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E)
49 /* Nonzero if we should generate code using type 2A insns. */
50 #define TARGET_SH2A TARGET_HARD_SH2A
51 /* Nonzero if we should generate code using type 2A SF insns. */
52 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E)
53 /* Nonzero if we should generate code using type 2A DF insns. */
54 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A)
56 /* Nonzero if we should generate code using type 3E insns. */
57 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E)
59 /* Nonzero if we schedule for a superscalar implementation. */
60 #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A)
62 /* Nonzero if a double-precision FPU is available. */
63 #define TARGET_FPU_DOUBLE \
64 ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
66 /* Nonzero if an FPU is available. */
67 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
69 /* Nonzero if we should generate code using type 4 insns. */
71 #define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
73 /* Nonzero if we're generating code for SH4a, unless the use of the
74 FPU is disabled (which makes it compatible with SH4al-dsp). */
75 #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY)
77 /* Nonzero if we should generate code using the SHcompact instruction
78 set and 32-bit ABI. */
79 #define TARGET_SHCOMPACT (TARGET_SH5 && TARGET_SH1)
81 /* Nonzero if we should generate code using the SHmedia instruction
83 #define TARGET_SHMEDIA (TARGET_SH5 && ! TARGET_SH1)
85 /* Nonzero if we should generate code using the SHmedia ISA and 32-bit
87 #define TARGET_SHMEDIA32 (TARGET_SH5 && ! TARGET_SH1 && TARGET_SH_E)
89 /* Nonzero if we should generate code using the SHmedia ISA and 64-bit
91 #define TARGET_SHMEDIA64 (TARGET_SH5 && ! TARGET_SH1 && ! TARGET_SH_E)
93 /* Nonzero if we should generate code using SHmedia FPU instructions. */
94 #define TARGET_SHMEDIA_FPU (TARGET_SHMEDIA && TARGET_FPU_DOUBLE)
96 /* This is not used by the SH2E calling convention */
97 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \
98 (TARGET_SH1 && ! TARGET_SH2E && ! TARGET_SH5 \
99 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL)))
101 #ifndef TARGET_CPU_DEFAULT
102 #define TARGET_CPU_DEFAULT SELECT_SH1
103 #define SUPPORT_SH1 1
104 #define SUPPORT_SH2E 1
105 #define SUPPORT_SH4 1
106 #define SUPPORT_SH4_SINGLE 1
107 #define SUPPORT_SH2A 1
108 #define SUPPORT_SH2A_SINGLE 1
111 #define TARGET_DIVIDE_INV \
112 (sh_div_strategy == SH_DIV_INV || sh_div_strategy == SH_DIV_INV_MINLAT \
113 || sh_div_strategy == SH_DIV_INV20U || sh_div_strategy == SH_DIV_INV20L \
114 || sh_div_strategy == SH_DIV_INV_CALL \
115 || sh_div_strategy == SH_DIV_INV_CALL2 || sh_div_strategy == SH_DIV_INV_FP)
116 #define TARGET_DIVIDE_FP (sh_div_strategy == SH_DIV_FP)
117 #define TARGET_DIVIDE_INV_FP (sh_div_strategy == SH_DIV_INV_FP)
118 #define TARGET_DIVIDE_CALL2 (sh_div_strategy == SH_DIV_CALL2)
119 #define TARGET_DIVIDE_INV_MINLAT (sh_div_strategy == SH_DIV_INV_MINLAT)
120 #define TARGET_DIVIDE_INV20U (sh_div_strategy == SH_DIV_INV20U)
121 #define TARGET_DIVIDE_INV20L (sh_div_strategy == SH_DIV_INV20L)
122 #define TARGET_DIVIDE_INV_CALL (sh_div_strategy == SH_DIV_INV_CALL)
123 #define TARGET_DIVIDE_INV_CALL2 (sh_div_strategy == SH_DIV_INV_CALL2)
124 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
125 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP)
126 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE)
128 #define SELECT_SH1 (MASK_SH1)
129 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1)
130 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \
132 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \
133 | MASK_HARD_SH2A_DOUBLE \
134 | MASK_SH2 | MASK_SH1)
135 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1)
136 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \
137 | MASK_SH1 | MASK_FPU_SINGLE \
138 | MASK_FPU_SINGLE_ONLY)
139 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \
140 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \
141 | MASK_SH2 | MASK_SH1)
142 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2)
143 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3)
144 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3)
145 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \
146 | MASK_FPU_SINGLE_ONLY)
147 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \
149 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4)
150 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU)
151 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
152 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
153 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
154 #define SELECT_SH5_64MEDIA (MASK_SH5 | MASK_SH4)
155 #define SELECT_SH5_64MEDIA_NOFPU (MASK_SH5)
156 #define SELECT_SH5_32MEDIA (MASK_SH5 | MASK_SH4 | MASK_SH_E)
157 #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
158 #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
159 #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
162 #define SUPPORT_SH2 1
165 #define SUPPORT_SH3 1
166 #define SUPPORT_SH2A_NOFPU 1
169 #define SUPPORT_SH4_NOFPU 1
171 #if SUPPORT_SH4_NOFPU
172 #define SUPPORT_SH4A_NOFPU 1
173 #define SUPPORT_SH4AL 1
177 #define SUPPORT_SH3E 1
178 #define SUPPORT_SH2A_SINGLE_ONLY 1
181 #define SUPPORT_SH4_SINGLE_ONLY 1
183 #if SUPPORT_SH4_SINGLE_ONLY
184 #define SUPPORT_SH4A_SINGLE_ONLY 1
188 #define SUPPORT_SH4A 1
191 #if SUPPORT_SH4_SINGLE
192 #define SUPPORT_SH4A_SINGLE 1
195 #if SUPPORT_SH5_COMPAT
196 #define SUPPORT_SH5_32MEDIA 1
199 #if SUPPORT_SH5_COMPACT_NOFPU
200 #define SUPPORT_SH5_32MEDIA_NOFPU 1
203 #define SUPPORT_ANY_SH5_32MEDIA \
204 (SUPPORT_SH5_32MEDIA || SUPPORT_SH5_32MEDIA_NOFPU)
205 #define SUPPORT_ANY_SH5_64MEDIA \
206 (SUPPORT_SH5_64MEDIA || SUPPORT_SH5_64MEDIA_NOFPU)
207 #define SUPPORT_ANY_SH5 \
208 (SUPPORT_ANY_SH5_32MEDIA || SUPPORT_ANY_SH5_64MEDIA)
210 /* Reset all target-selection flags. */
211 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
212 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
213 | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
214 | MASK_FPU_SINGLE_ONLY)
216 /* This defaults us to big-endian. */
217 #ifndef TARGET_ENDIAN_DEFAULT
218 #define TARGET_ENDIAN_DEFAULT 0
221 #ifndef TARGET_OPT_DEFAULT
222 #define TARGET_OPT_DEFAULT 0
225 #define TARGET_DEFAULT \
226 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT)
228 #ifndef SH_MULTILIB_CPU_DEFAULT
229 #define SH_MULTILIB_CPU_DEFAULT "m1"
232 #if TARGET_ENDIAN_DEFAULT
233 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT }
235 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT }
238 #define CPP_SPEC " %(subtarget_cpp_spec) "
240 #ifndef SUBTARGET_CPP_SPEC
241 #define SUBTARGET_CPP_SPEC ""
244 #ifndef SUBTARGET_EXTRA_SPECS
245 #define SUBTARGET_EXTRA_SPECS
248 #define EXTRA_SPECS \
249 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
250 { "link_emul_prefix", LINK_EMUL_PREFIX }, \
251 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \
252 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \
253 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \
254 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \
255 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \
256 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \
257 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
258 SUBTARGET_EXTRA_SPECS
260 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4
261 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:%{!m5*:-isa=sh4-up}}}}"
263 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}"
266 /* Define which ISA type to pass to the assembler.
267 For SH4 we pass SH4A to allow using some instructions that are available
268 on some SH4 variants, but officially are part of the SH4A ISA. */
269 #define SH_ASM_SPEC \
270 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \
271 %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \
278 %{m4-single:--isa=sh4a} \
279 %{m4-single-only:--isa=sh4a} \
280 %{m4-nofpu:--isa=sh4a-nofpu} \
282 %{m4a-single:--isa=sh4a} \
283 %{m4a-single-only:--isa=sh4a} \
284 %{m4a-nofpu:--isa=sh4a-nofpu} \
286 %{m2a-single:--isa=sh2a} \
287 %{m2a-single-only:--isa=sh2a} \
288 %{m2a-nofpu:--isa=sh2a-nofpu} \
289 %{m5-compact*:--isa=SHcompact} \
290 %{m5-32media*:--isa=SHmedia --abi=32} \
291 %{m5-64media*:--isa=SHmedia --abi=64} \
292 %{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
294 #define ASM_SPEC SH_ASM_SPEC
296 #ifndef SUBTARGET_ASM_ENDIAN_SPEC
297 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
298 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}"
300 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}"
304 #if STRICT_NOFPU == 1
305 /* Strict nofpu means that the compiler should tell the assembler
306 to reject FPU instructions. E.g. from ASM inserts. */
307 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E)
308 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:%{!m5:-isa=sh4-nofpu}}}}}"
310 /* If there were an -isa option for sh5-nofpu then it would also go here. */
311 #define SUBTARGET_ASM_ISA_SPEC \
312 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC
314 #else /* ! STRICT_NOFPU */
315 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC
318 #ifndef SUBTARGET_ASM_SPEC
319 #define SUBTARGET_ASM_SPEC ""
322 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
323 #define LINK_EMUL_PREFIX "sh%{!mb:l}"
325 #define LINK_EMUL_PREFIX "sh%{ml:l}"
328 #if TARGET_CPU_DEFAULT & MASK_SH5
329 #if TARGET_CPU_DEFAULT & MASK_SH_E
330 #define LINK_DEFAULT_CPU_EMUL "32"
331 #if TARGET_CPU_DEFAULT & MASK_SH1
332 #define ASM_ISA_SPEC_DEFAULT "--isa=SHcompact"
334 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=32"
335 #endif /* MASK_SH1 */
336 #else /* !MASK_SH_E */
337 #define LINK_DEFAULT_CPU_EMUL "64"
338 #define ASM_ISA_SPEC_DEFAULT "--isa=SHmedia --abi=64"
339 #endif /* MASK_SH_E */
340 #define ASM_ISA_DEFAULT_SPEC \
341 " %{!m1:%{!m2*:%{!m3*:%{!m4*:%{!m5*:" ASM_ISA_SPEC_DEFAULT "}}}}}"
342 #else /* !MASK_SH5 */
343 #define LINK_DEFAULT_CPU_EMUL ""
344 #define ASM_ISA_DEFAULT_SPEC ""
345 #endif /* MASK_SH5 */
347 #define SUBTARGET_LINK_EMUL_SUFFIX ""
348 #define SUBTARGET_LINK_SPEC ""
350 /* Go via SH_LINK_SPEC to avoid code replication. */
351 #define LINK_SPEC SH_LINK_SPEC
353 #define SH_LINK_SPEC "\
354 -m %(link_emul_prefix)\
355 %{m5-compact*|m5-32media*:32}\
357 %{!m1:%{!m2:%{!m3*:%{!m4*:%{!m5*:%(link_default_cpu_emul)}}}}}\
358 %(subtarget_link_emul_suffix) \
359 %{mrelax:-relax} %(subtarget_link_spec)"
361 #ifndef SH_DIV_STR_FOR_SIZE
362 #define SH_DIV_STR_FOR_SIZE "call"
365 /* SH2A does not support little-endian. Catch such combinations
366 taking into account the default configuration. */
367 #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN
368 #define IS_LITTLE_ENDIAN_OPTION "%{ml:"
370 #define IS_LITTLE_ENDIAN_OPTION "%{!mb:"
373 #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A
374 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
375 "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:{!m5*:%eSH2a does not support little-endian}}}}}}"
377 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \
378 "%{m2a*:%eSH2a does not support little-endian}}"
381 #undef DRIVER_SELF_SPECS
382 #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A
384 #define ASSEMBLER_DIALECT assembler_dialect
386 extern int assembler_dialect
;
388 enum sh_divide_strategy_e
{
389 /* SH5 strategies. */
392 SH_DIV_FP
, /* We could do this also for SH4. */
400 /* SH1 .. SH4 strategies. Because of the small number of registers
401 available, the compiler uses knowledge of the actual set of registers
402 being clobbered by the different functions called. */
403 SH_DIV_CALL_DIV1
, /* No FPU, medium size, highest latency. */
404 SH_DIV_CALL_FP
, /* FPU needed, small size, high latency. */
405 SH_DIV_CALL_TABLE
, /* No FPU, large size, medium latency. */
409 extern enum sh_divide_strategy_e sh_div_strategy
;
411 #ifndef SH_DIV_STRATEGY_DEFAULT
412 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL
415 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0
418 /* Target machine storage layout. */
420 #define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN)
422 #define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0)
423 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1)
425 /* Define this if most significant bit is lowest numbered
426 in instructions that operate on numbered bit-fields. */
427 #define BITS_BIG_ENDIAN 0
429 /* Define this if most significant byte of a word is the lowest numbered. */
430 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN
432 /* Define this if most significant word of a multiword number is the lowest
434 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN
436 #define MAX_BITS_PER_WORD 64
438 /* Width in bits of an `int'. We want just 32-bits, even if words are
440 #define INT_TYPE_SIZE 32
442 /* Width in bits of a `long'. */
443 #define LONG_TYPE_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
445 /* Width in bits of a `long long'. */
446 #define LONG_LONG_TYPE_SIZE 64
448 /* Width in bits of a `long double'. */
449 #define LONG_DOUBLE_TYPE_SIZE 64
451 /* Width of a word, in units (bytes). */
452 #define UNITS_PER_WORD (TARGET_SHMEDIA ? 8 : 4)
453 #define MIN_UNITS_PER_WORD 4
455 /* Scaling factor for Dwarf data offsets for CFI information.
456 The dwarf2out.c default would use -UNITS_PER_WORD, which is -8 for
457 SHmedia; however, since we do partial register saves for the registers
458 visible to SHcompact, and for target registers for SHMEDIA32, we have
459 to allow saves that are only 4-byte aligned. */
460 #define DWARF_CIE_DATA_ALIGNMENT -4
462 /* Width in bits of a pointer.
463 See also the macro `Pmode' defined below. */
464 #define POINTER_SIZE (TARGET_SHMEDIA64 ? 64 : 32)
466 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
467 #define PARM_BOUNDARY (TARGET_SH5 ? 64 : 32)
469 /* Boundary (in *bits*) on which stack pointer should be aligned. */
470 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
472 /* The log (base 2) of the cache line size, in bytes. Processors prior to
473 SH2 have no actual cache, but they fetch code in chunks of 4 bytes.
474 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */
475 #define CACHE_LOG ((TARGET_HARD_SH4 || TARGET_SH5) ? 5 : TARGET_SH2 ? 4 : 2)
477 /* ABI given & required minimum allocation boundary (in *bits*) for the
478 code of a function. */
479 #define FUNCTION_BOUNDARY (16 << TARGET_SHMEDIA)
481 /* On SH5, the lowest bit is used to indicate SHmedia functions, so
482 the vbit must go into the delta field of
483 pointers-to-member-functions. */
484 #define TARGET_PTRMEMFUNC_VBIT_LOCATION \
485 (TARGET_SH5 ? ptrmemfunc_vbit_in_delta : ptrmemfunc_vbit_in_pfn)
487 /* Alignment of field after `int : 0' in a structure. */
488 #define EMPTY_FIELD_BOUNDARY 32
490 /* No data type wants to be aligned rounder than this. */
491 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32)
493 /* The best alignment to use in cases where we have a choice. */
494 #define FASTEST_ALIGNMENT (TARGET_SH5 ? 64 : 32)
496 /* Make strings word-aligned so strcpy from constants will be faster. */
497 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
498 ((TREE_CODE (EXP) == STRING_CST \
499 && (ALIGN) < FASTEST_ALIGNMENT) \
500 ? FASTEST_ALIGNMENT : (ALIGN))
502 /* get_mode_alignment assumes complex values are always held in multiple
503 registers, but that is not the case on the SH; CQImode and CHImode are
504 held in a single integer register. SH5 also holds CSImode and SCmode
505 values in integer registers. This is relevant for argument passing on
506 SHcompact as we use a stack temp in order to pass CSImode by reference. */
507 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
508 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \
509 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \
510 ? (unsigned) MIN (BIGGEST_ALIGNMENT, GET_MODE_BITSIZE (TYPE_MODE (TYPE))) \
511 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN))
513 /* Make arrays of chars word-aligned for the same reasons. */
514 #define DATA_ALIGNMENT(TYPE, ALIGN) \
515 (TREE_CODE (TYPE) == ARRAY_TYPE \
516 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
517 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))
519 /* Number of bits which any structure or union's size must be a
520 multiple of. Each structure or union's size is rounded up to a
522 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8)
524 /* Set this nonzero if move instructions will actually fail to work
525 when given unaligned data. */
526 #define STRICT_ALIGNMENT 1
528 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */
529 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \
530 barrier_align (LABEL_AFTER_BARRIER)
532 #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL)
534 #define LABEL_ALIGN(A_LABEL) \
536 (PREV_INSN (A_LABEL) \
537 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \
538 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \
539 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \
540 /* explicit alignment insn in constant tables. */ \
541 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \
544 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
545 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
547 /* The base two logarithm of the known minimum alignment of an insn length. */
548 #define INSN_LENGTH_ALIGNMENT(A_INSN) \
549 (NONJUMP_INSN_P (A_INSN) \
550 ? 1 << TARGET_SHMEDIA \
551 : JUMP_P (A_INSN) || CALL_P (A_INSN) \
552 ? 1 << TARGET_SHMEDIA \
555 /* Standard register usage. */
557 /* Register allocation for the Renesas calling convention:
563 r14 frame pointer/call saved
565 ap arg pointer (doesn't really exist, always eliminated)
566 pr subroutine return address
568 mach multiply/accumulate result, high part
569 macl multiply/accumulate result, low part.
570 fpul fp/int communication register
571 rap return address pointer register
573 fr1..fr3 scratch floating point registers
575 fr12..fr15 call saved floating point registers */
577 #define MAX_REGISTER_NAME_LENGTH 6
578 extern char sh_register_names
[][MAX_REGISTER_NAME_LENGTH
+ 1];
580 #define SH_REGISTER_NAMES_INITIALIZER \
582 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
583 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
584 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
585 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
586 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
587 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
588 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
589 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
590 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
591 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \
592 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \
593 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \
594 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \
595 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \
596 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \
597 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \
598 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \
599 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \
600 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \
601 "rap", "sfp", "fpscr0", "fpscr1" \
604 #define REGNAMES_ARR_INDEX_1(index) \
605 (sh_register_names[index])
606 #define REGNAMES_ARR_INDEX_2(index) \
607 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1)
608 #define REGNAMES_ARR_INDEX_4(index) \
609 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2)
610 #define REGNAMES_ARR_INDEX_8(index) \
611 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4)
612 #define REGNAMES_ARR_INDEX_16(index) \
613 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8)
614 #define REGNAMES_ARR_INDEX_32(index) \
615 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16)
616 #define REGNAMES_ARR_INDEX_64(index) \
617 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32)
619 #define REGISTER_NAMES \
621 REGNAMES_ARR_INDEX_64 (0), \
622 REGNAMES_ARR_INDEX_64 (64), \
623 REGNAMES_ARR_INDEX_8 (128), \
624 REGNAMES_ARR_INDEX_8 (136), \
625 REGNAMES_ARR_INDEX_8 (144), \
626 REGNAMES_ARR_INDEX_4 (152) \
629 #define ADDREGNAMES_SIZE 32
630 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4
631 extern char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
632 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1];
634 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \
636 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \
637 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \
638 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \
639 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \
642 #define ADDREGNAMES_REGNO(index) \
643 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \
646 #define ADDREGNAMES_ARR_INDEX_1(index) \
647 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) }
648 #define ADDREGNAMES_ARR_INDEX_2(index) \
649 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1)
650 #define ADDREGNAMES_ARR_INDEX_4(index) \
651 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2)
652 #define ADDREGNAMES_ARR_INDEX_8(index) \
653 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4)
654 #define ADDREGNAMES_ARR_INDEX_16(index) \
655 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8)
656 #define ADDREGNAMES_ARR_INDEX_32(index) \
657 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16)
659 #define ADDITIONAL_REGISTER_NAMES \
661 ADDREGNAMES_ARR_INDEX_32 (0) \
664 /* Number of actual hardware registers.
665 The hardware registers are assigned numbers for the compiler
666 from 0 to just below FIRST_PSEUDO_REGISTER.
667 All registers that the compiler knows about must be given numbers,
668 even those that are not normally considered general registers. */
670 /* There are many other relevant definitions in sh.md's md_constants. */
672 #define FIRST_GENERAL_REG R0_REG
673 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (TARGET_SHMEDIA ? 63 : 15))
674 #define FIRST_FP_REG DR0_REG
675 #define LAST_FP_REG (FIRST_FP_REG + \
676 (TARGET_SHMEDIA_FPU ? 63 : TARGET_SH2E ? 15 : -1))
677 #define FIRST_XD_REG XD0_REG
678 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
679 #define FIRST_TARGET_REG TR0_REG
680 #define LAST_TARGET_REG (FIRST_TARGET_REG + (TARGET_SHMEDIA ? 7 : -1))
682 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
683 #define FIRST_BANKED_REG R0_REG
684 #define LAST_BANKED_REG R7_REG
686 #define BANKED_REGISTER_P(REGNO) \
688 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \
689 (unsigned HOST_WIDE_INT) LAST_BANKED_REG)
691 #define GENERAL_REGISTER_P(REGNO) \
693 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
694 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG)
696 #define GENERAL_OR_AP_REGISTER_P(REGNO) \
697 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \
698 || ((REGNO) == FRAME_POINTER_REGNUM))
700 #define FP_REGISTER_P(REGNO) \
701 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG)
703 #define XD_REGISTER_P(REGNO) \
704 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG)
706 #define FP_OR_XD_REGISTER_P(REGNO) \
707 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO))
709 #define FP_ANY_REGISTER_P(REGNO) \
710 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG)
712 #define SPECIAL_REGISTER_P(REGNO) \
713 ((REGNO) == GBR_REG || (REGNO) == T_REG \
714 || (REGNO) == MACH_REG || (REGNO) == MACL_REG \
715 || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG)
717 #define TARGET_REGISTER_P(REGNO) \
718 ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
720 #define SHMEDIA_REGISTER_P(REGNO) \
721 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
722 || TARGET_REGISTER_P (REGNO))
724 /* This is to be used in TARGET_CONDITIONAL_REGISTER_USAGE, to mark
725 registers that should be fixed. */
726 #define VALID_REGISTER_P(REGNO) \
727 (SHMEDIA_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) \
728 || (REGNO) == AP_REG || (REGNO) == RAP_REG \
729 || (REGNO) == FRAME_POINTER_REGNUM \
730 || (TARGET_SH1 && (SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \
731 || (TARGET_SH2E && (REGNO) == FPUL_REG))
733 /* The mode that should be generally used to store a register by
734 itself in the stack, or to load it back. */
735 #define REGISTER_NATURAL_MODE(REGNO) \
736 (FP_REGISTER_P (REGNO) ? SFmode \
737 : XD_REGISTER_P (REGNO) ? DFmode \
738 : TARGET_SHMEDIA && ! HARD_REGNO_CALL_PART_CLOBBERED ((REGNO), DImode) \
742 #define FIRST_PSEUDO_REGISTER 156
744 /* Don't count soft frame pointer. */
745 #define DWARF_FRAME_REGISTERS (153)
747 /* 1 for registers that have pervasive standard uses
748 and are not available for the register allocator.
750 Mach register is fixed 'cause it's only 10 bits wide for SH1.
751 It is 32 bits wide for SH2. */
752 #define FIXED_REGISTERS \
754 /* Regular registers. */ \
755 0, 0, 0, 0, 0, 0, 0, 0, \
756 0, 0, 0, 0, 0, 0, 0, 1, \
757 /* r16 is reserved, r18 is the former pr. */ \
758 1, 0, 0, 0, 0, 0, 0, 0, \
759 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \
760 /* r26 is a global variable data pointer; r27 is for constants. */ \
761 1, 1, 1, 1, 0, 0, 0, 0, \
762 0, 0, 0, 0, 0, 0, 0, 0, \
763 0, 0, 0, 0, 0, 0, 0, 0, \
764 0, 0, 0, 0, 0, 0, 0, 0, \
765 0, 0, 0, 0, 0, 0, 0, 1, \
766 /* FP registers. */ \
767 0, 0, 0, 0, 0, 0, 0, 0, \
768 0, 0, 0, 0, 0, 0, 0, 0, \
769 0, 0, 0, 0, 0, 0, 0, 0, \
770 0, 0, 0, 0, 0, 0, 0, 0, \
771 0, 0, 0, 0, 0, 0, 0, 0, \
772 0, 0, 0, 0, 0, 0, 0, 0, \
773 0, 0, 0, 0, 0, 0, 0, 0, \
774 0, 0, 0, 0, 0, 0, 0, 0, \
775 /* Branch target registers. */ \
776 0, 0, 0, 0, 0, 0, 0, 0, \
777 /* XD registers. */ \
778 0, 0, 0, 0, 0, 0, 0, 0, \
779 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
780 1, 1, 1, 1, 1, 1, 0, 1, \
781 /*"rap", "sfp","fpscr0","fpscr1" */ \
785 /* 1 for registers not available across function calls.
786 These must include the FIXED_REGISTERS and also any
787 registers that can be used without being saved.
788 The latter must include the registers where values are returned
789 and the register where structure-value addresses are passed.
790 Aside from that, you can include as many other registers as you like. */
791 #define CALL_USED_REGISTERS \
793 /* Regular registers. */ \
794 1, 1, 1, 1, 1, 1, 1, 1, \
795 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
796 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
797 across SH5 function calls. */ \
798 0, 0, 0, 0, 0, 0, 0, 1, \
799 1, 1, 1, 1, 1, 1, 1, 1, \
800 1, 1, 1, 1, 0, 0, 0, 0, \
801 0, 0, 0, 0, 1, 1, 1, 1, \
802 1, 1, 1, 1, 0, 0, 0, 0, \
803 0, 0, 0, 0, 0, 0, 0, 0, \
804 0, 0, 0, 0, 1, 1, 1, 1, \
805 /* FP registers. */ \
806 1, 1, 1, 1, 1, 1, 1, 1, \
807 1, 1, 1, 1, 0, 0, 0, 0, \
808 1, 1, 1, 1, 1, 1, 1, 1, \
809 1, 1, 1, 1, 1, 1, 1, 1, \
810 1, 1, 1, 1, 0, 0, 0, 0, \
811 0, 0, 0, 0, 0, 0, 0, 0, \
812 0, 0, 0, 0, 0, 0, 0, 0, \
813 0, 0, 0, 0, 0, 0, 0, 0, \
814 /* Branch target registers. */ \
815 1, 1, 1, 1, 1, 0, 0, 0, \
816 /* XD registers. */ \
817 1, 1, 1, 1, 1, 1, 0, 0, \
818 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
819 1, 1, 1, 1, 1, 1, 1, 1, \
820 /*"rap", "sfp","fpscr0","fpscr1" */ \
824 /* CALL_REALLY_USED_REGISTERS is used as a default setting, which is then
825 overridden by -fcall-saved-* and -fcall-used-* options and then by
826 TARGET_CONDITIONAL_REGISTER_USAGE. There we might want to make a
827 register call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */
828 #define CALL_REALLY_USED_REGISTERS \
830 /* Regular registers. */ \
831 1, 1, 1, 1, 1, 1, 1, 1, \
832 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \
833 Only the lower 32bits of R10-R14 are guaranteed to be preserved \
834 across SH5 function calls. */ \
835 0, 0, 0, 0, 0, 0, 0, 1, \
836 1, 1, 1, 1, 1, 1, 1, 1, \
837 1, 1, 1, 1, 0, 0, 0, 0, \
838 0, 0, 0, 0, 1, 1, 1, 1, \
839 1, 1, 1, 1, 0, 0, 0, 0, \
840 0, 0, 0, 0, 0, 0, 0, 0, \
841 0, 0, 0, 0, 1, 1, 1, 1, \
842 /* FP registers. */ \
843 1, 1, 1, 1, 1, 1, 1, 1, \
844 1, 1, 1, 1, 0, 0, 0, 0, \
845 1, 1, 1, 1, 1, 1, 1, 1, \
846 1, 1, 1, 1, 1, 1, 1, 1, \
847 1, 1, 1, 1, 0, 0, 0, 0, \
848 0, 0, 0, 0, 0, 0, 0, 0, \
849 0, 0, 0, 0, 0, 0, 0, 0, \
850 0, 0, 0, 0, 0, 0, 0, 0, \
851 /* Branch target registers. */ \
852 1, 1, 1, 1, 1, 0, 0, 0, \
853 /* XD registers. */ \
854 1, 1, 1, 1, 1, 1, 0, 0, \
855 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \
856 0, 1, 1, 1, 1, 1, 1, 1, \
857 /*"rap", "sfp","fpscr0","fpscr1" */ \
861 /* Only the lower 32-bits of R10-R14 are guaranteed to be preserved
862 across SHcompact function calls. We can't tell whether a called
863 function is SHmedia or SHcompact, so we assume it may be when
864 compiling SHmedia code with the 32-bit ABI, since that's the only
865 ABI that can be linked with SHcompact code. */
866 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO,MODE) \
868 && GET_MODE_SIZE (MODE) > 4 \
869 && (((REGNO) >= FIRST_GENERAL_REG + 10 \
870 && (REGNO) <= FIRST_GENERAL_REG + 15) \
871 || TARGET_REGISTER_P (REGNO) \
872 || (REGNO) == PR_MEDIA_REG))
874 /* Return number of consecutive hard regs needed starting at reg REGNO
875 to hold something of mode MODE.
876 This is ordinarily the length in words of a value of mode MODE
877 but can be less for certain modes in special long registers.
879 On the SH all but the XD regs are UNITS_PER_WORD bits wide. */
880 #define HARD_REGNO_NREGS(REGNO, MODE) \
881 (XD_REGISTER_P (REGNO) \
882 ? ((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD - 1)) / (2*UNITS_PER_WORD)) \
883 : (TARGET_SHMEDIA && FP_REGISTER_P (REGNO)) \
884 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2)) \
885 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
887 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
888 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
889 sh_hard_regno_mode_ok ((REGNO), (MODE))
891 /* Value is 1 if it is a good idea to tie two pseudo registers
892 when one has mode MODE1 and one has mode MODE2.
893 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
894 for any hard reg, then this must be 0 for correct output.
895 That's the case for xd registers: we don't hold SFmode values in
896 them, so we can't tie an SFmode pseudos with one in another
897 floating-point mode. */
898 #define MODES_TIEABLE_P(MODE1, MODE2) \
899 ((MODE1) == (MODE2) \
901 && GET_MODE_SIZE (MODE1) == GET_MODE_SIZE (MODE2) \
902 && INTEGRAL_MODE_P (MODE1) && INTEGRAL_MODE_P (MODE2)) \
903 || (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \
904 && (TARGET_SHMEDIA ? ((GET_MODE_SIZE (MODE1) <= 4) \
905 && (GET_MODE_SIZE (MODE2) <= 4)) \
906 : ((MODE1) != SFmode && (MODE2) != SFmode))))
908 /* Specify the modes required to caller save a given hard regno. */
909 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
910 sh_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE))
912 /* A C expression that is nonzero if hard register NEW_REG can be
913 considered for use as a rename register for OLD_REG register */
914 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
915 sh_hard_regno_rename_ok (OLD_REG, NEW_REG)
917 /* Specify the registers used for certain standard purposes.
918 The values of these macros are register numbers. */
920 /* Define this if the program counter is overloaded on a register. */
921 /* #define PC_REGNUM 15*/
923 /* Register to use for pushing function arguments. */
924 #define STACK_POINTER_REGNUM SP_REG
926 /* Base register for access to local variables of the function. */
927 #define HARD_FRAME_POINTER_REGNUM FP_REG
929 /* Base register for access to local variables of the function. */
930 #define FRAME_POINTER_REGNUM 153
932 /* Fake register that holds the address on the stack of the
933 current function's return address. */
934 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG
936 /* Register to hold the addressing base for position independent
937 code access to data items. */
938 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
940 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
942 /* Definitions for register eliminations.
944 We have three registers that can be eliminated on the SH. First, the
945 frame pointer register can often be eliminated in favor of the stack
946 pointer register. Secondly, the argument pointer register can always be
947 eliminated; it is replaced with either the stack or frame pointer.
948 Third, there is the return address pointer, which can also be replaced
949 with either the stack or the frame pointer.
951 This is an array of structures. Each structure initializes one pair
952 of eliminable registers. The "from" register number is given first,
953 followed by "to". Eliminations of the same "from" register are listed
954 in order of preference.
956 If you add any registers here that are not actually hard registers,
957 and that have any alternative of elimination that doesn't always
958 apply, you need to amend calc_live_regs to exclude it, because
959 reload spills all eliminable registers where it sees an
960 can_eliminate == 0 entry, thus making them 'live' .
961 If you add any hard registers that can be eliminated in different
962 ways, you have to patch reload to spill them only when all alternatives
963 of elimination fail. */
964 #define ELIMINABLE_REGS \
965 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
966 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
967 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
968 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
969 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
970 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
971 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},}
973 /* Define the offset between two registers, one to be eliminated, and the other
974 its replacement, at the start of a routine. */
975 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
976 OFFSET = initial_elimination_offset ((FROM), (TO))
978 /* Base register for access to arguments of the function. */
979 #define ARG_POINTER_REGNUM AP_REG
981 /* Register in which the static-chain is passed to a function. */
982 #define STATIC_CHAIN_REGNUM (TARGET_SH5 ? 1 : 3)
984 /* Don't default to pcc-struct-return, because we have already specified
985 exactly how to return structures in the TARGET_RETURN_IN_MEMORY
987 #define DEFAULT_PCC_STRUCT_RETURN 0
989 #define SHMEDIA_REGS_STACK_ADJUST() \
990 (TARGET_SHCOMPACT && crtl->saves_all_registers \
991 ? (8 * (/* r28-r35 */ 8 + /* r44-r59 */ 16 + /* tr5-tr7 */ 3) \
992 + (TARGET_FPU_ANY ? 4 * (/* fr36 - fr63 */ 28) : 0)) \
996 /* Define the classes of registers for register constraints in the
997 machine description. Also define ranges of constants.
999 One of the classes must always be named ALL_REGS and include all hard regs.
1000 If there is more than one class, another class must be named NO_REGS
1001 and contain no registers.
1003 The name GENERAL_REGS must be the name of a class (or an alias for
1004 another name such as ALL_REGS). This is the class of registers
1005 that is allowed by "g" or "r" in a register constraint.
1006 Also, registers outside this class are allocated only when
1007 instructions express preferences for them.
1009 The classes must be numbered in nondecreasing order; that is,
1010 a larger-numbered class must never be contained completely
1011 in a smaller-numbered class.
1013 For any two classes, it is very desirable that there be another
1014 class that represents their union.
1016 The SH has two sorts of general registers, R0 and the rest. R0 can
1017 be used as the destination of some of the arithmetic ops. There are
1018 also some special purpose registers; the T bit register, the
1019 Procedure Return Register and the Multiply Accumulate Registers.
1021 Place GENERAL_REGS after FPUL_REGS so that it will be preferred by
1022 reg_class_subunion. We don't want to have an actual union class
1023 of these, because it would only be used when both classes are calculated
1024 to give the same cost, but there is only one FPUL register.
1025 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS
1026 applying to the actual instruction alternative considered. E.g., the
1027 y/r alternative of movsi_ie is considered to have no more cost that
1028 the r/r alternative, which is patently untrue. */
1051 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1053 /* Give names of register classes as strings for dump file. */
1054 #define REG_CLASS_NAMES \
1069 "GENERAL_FP_REGS", \
1070 "GENERAL_DF_REGS", \
1075 /* Define which registers fit in which classes.
1076 This is an initializer for a vector of HARD_REG_SET
1077 of length N_REG_CLASSES. */
1078 #define REG_CLASS_CONTENTS \
1081 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1083 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1085 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \
1087 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \
1089 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \
1091 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \
1092 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \
1093 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1094 /* NON_SP_REGS: */ \
1095 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1096 /* GENERAL_REGS: */ \
1097 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \
1099 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \
1101 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \
1103 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \
1105 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \
1106 /* GENERAL_FP_REGS: */ \
1107 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \
1108 /* GENERAL_DF_REGS: */ \
1109 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \
1110 /* TARGET_REGS: */ \
1111 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \
1113 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff }, \
1116 /* The same information, inverted:
1117 Return the class number of the smallest class containing
1118 reg number REGNO. This could be a conditional expression
1119 or could index an array. */
1120 extern enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
1121 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)]
1123 /* When this hook returns true for MODE, the compiler allows
1124 registers explicitly used in the rtl to be used as spill registers
1125 but prevents the compiler from extending the lifetime of these
1127 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
1128 sh_small_register_classes_for_mode_p
1130 /* The order in which register should be allocated. */
1131 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo,
1132 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be
1133 spilled or used otherwise, we better have the FP_REGS allocated first. */
1134 #define REG_ALLOC_ORDER \
1135 {/* Caller-saved FPRs */ \
1136 65, 66, 67, 68, 69, 70, 71, 64, \
1137 72, 73, 74, 75, 80, 81, 82, 83, \
1138 84, 85, 86, 87, 88, 89, 90, 91, \
1139 92, 93, 94, 95, 96, 97, 98, 99, \
1140 /* Callee-saved FPRs */ \
1141 76, 77, 78, 79,100,101,102,103, \
1142 104,105,106,107,108,109,110,111, \
1143 112,113,114,115,116,117,118,119, \
1144 120,121,122,123,124,125,126,127, \
1145 136,137,138,139,140,141,142,143, \
1147 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \
1148 1, 2, 3, 7, 6, 5, 4, 0, \
1149 8, 9, 17, 19, 20, 21, 22, 23, \
1150 36, 37, 38, 39, 40, 41, 42, 43, \
1152 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \
1153 10, 11, 12, 13, 14, 18, \
1154 /* SH5 callee-saved GPRs */ \
1155 28, 29, 30, 31, 32, 33, 34, 35, \
1156 44, 45, 46, 47, 48, 49, 50, 51, \
1157 52, 53, 54, 55, 56, 57, 58, 59, \
1159 /* SH5 branch target registers */ \
1160 128,129,130,131,132,133,134,135, \
1161 /* Fixed registers */ \
1162 15, 16, 24, 25, 26, 27, 63,144, \
1163 145,146,147,148,149,152,153,154,155 }
1165 /* The class value for index registers, and the one for base regs. */
1166 #define INDEX_REG_CLASS \
1167 (!ALLOW_INDEXED_ADDRESS ? NO_REGS : TARGET_SHMEDIA ? GENERAL_REGS : R0_REGS)
1168 #define BASE_REG_CLASS GENERAL_REGS
1170 /* Defines for sh.md and constraints.md. */
1172 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \
1173 && ((HOST_WIDE_INT)(VALUE)) <= 127)
1174 #define CONST_OK_FOR_I16(VALUE) (((HOST_WIDE_INT)(VALUE)) >= -32768 \
1175 && ((HOST_WIDE_INT)(VALUE)) <= 32767)
1177 #define CONST_OK_FOR_J16(VALUE) \
1178 ((HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) 0xffffffff) \
1179 || (HOST_BITS_PER_WIDE_INT >= 64 && (VALUE) == (HOST_WIDE_INT) -1 << 32))
1181 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \
1182 && ((HOST_WIDE_INT)(VALUE)) <= 255)
1184 #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\
1185 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX))
1187 /* Return the maximum number of consecutive registers
1188 needed to represent mode MODE in a register of class CLASS.
1190 If TARGET_SHMEDIA, we need two FP registers per word.
1191 Otherwise we will need at most one register per word. */
1192 #define CLASS_MAX_NREGS(CLASS, MODE) \
1194 && TEST_HARD_REG_BIT (reg_class_contents[CLASS], FIRST_FP_REG) \
1195 ? (GET_MODE_SIZE (MODE) + UNITS_PER_WORD/2 - 1) / (UNITS_PER_WORD/2) \
1196 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1198 /* If defined, gives a class of registers that cannot be used as the
1199 operand of a SUBREG that changes the mode of the object illegally.
1200 ??? We need to renumber the internal numbers for the frnn registers
1201 when in little endian in order to allow mode size changes. */
1202 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1203 sh_cannot_change_mode_class (FROM, TO, CLASS)
1205 /* Stack layout; function entry, exit and calling. */
1207 /* Define the number of registers that can hold parameters.
1208 These macros are used only in other macro definitions below. */
1209 #define NPARM_REGS(MODE) \
1210 (TARGET_FPU_ANY && (MODE) == SFmode \
1211 ? (TARGET_SH5 ? 12 : 8) \
1212 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) \
1213 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1214 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1215 ? (TARGET_SH5 ? 12 : 8) \
1216 : (TARGET_SH5 ? 8 : 4))
1218 #define FIRST_PARM_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 4))
1219 #define FIRST_RET_REG (FIRST_GENERAL_REG + (TARGET_SH5 ? 2 : 0))
1221 #define FIRST_FP_PARM_REG (FIRST_FP_REG + (TARGET_SH5 ? 0 : 4))
1222 #define FIRST_FP_RET_REG FIRST_FP_REG
1224 /* Define this if pushing a word on the stack
1225 makes the stack pointer a smaller address. */
1226 #define STACK_GROWS_DOWNWARD
1228 /* Define this macro to nonzero if the addresses of local variable slots
1229 are at negative offsets from the frame pointer. */
1230 #define FRAME_GROWS_DOWNWARD 1
1232 /* Offset from the frame pointer to the first local variable slot to
1234 #define STARTING_FRAME_OFFSET 0
1236 /* If we generate an insn to push BYTES bytes,
1237 this says how many the stack pointer really advances by. */
1238 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this.
1239 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to
1240 do correct alignment. */
1242 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
1245 /* Offset of first parameter from the argument pointer register value. */
1246 #define FIRST_PARM_OFFSET(FNDECL) 0
1248 /* Value is the number of bytes of arguments automatically popped when
1249 calling a subroutine.
1250 CUM is the accumulated argument list.
1252 On SHcompact, the call trampoline pops arguments off the stack. */
1253 #define CALL_POPS_ARGS(CUM) (TARGET_SHCOMPACT ? (CUM).stack_regs * 8 : 0)
1255 /* Some subroutine macros specific to this machine. */
1257 #define BASE_RETURN_VALUE_REG(MODE) \
1258 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \
1259 ? FIRST_FP_RET_REG \
1260 : TARGET_FPU_ANY && (MODE) == SCmode \
1261 ? FIRST_FP_RET_REG \
1262 : (TARGET_FPU_DOUBLE \
1263 && ((MODE) == DFmode || (MODE) == SFmode \
1264 || (MODE) == DCmode || (MODE) == SCmode )) \
1265 ? FIRST_FP_RET_REG \
1268 #define BASE_ARG_REG(MODE) \
1269 ((TARGET_SH2E && ((MODE) == SFmode)) \
1270 ? FIRST_FP_PARM_REG \
1271 : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1272 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
1273 ? FIRST_FP_PARM_REG \
1276 /* 1 if N is a possible register number for function argument passing. */
1277 /* ??? There are some callers that pass REGNO as int, and others that pass
1278 it as unsigned. We get warnings unless we do casts everywhere. */
1279 #define FUNCTION_ARG_REGNO_P(REGNO) \
1280 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \
1281 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\
1282 || (TARGET_FPU_ANY \
1283 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \
1284 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \
1285 + NPARM_REGS (SFmode))))
1287 /* Define a data type for recording info about an argument list
1288 during the scan of that argument list. This data type should
1289 hold all necessary information about the function itself
1290 and about the args processed so far, enough to enable macros
1291 such as FUNCTION_ARG to determine where the next arg should go.
1293 On SH, this is a single integer, which is a number of words
1294 of arguments scanned so far (including the invisible argument,
1295 if any, which holds the structure-value-address).
1296 Thus NARGREGS or more means all following args should go on the stack. */
1297 enum sh_arg_class
{ SH_ARG_INT
= 0, SH_ARG_FLOAT
= 1 };
1301 /* Nonzero if a prototype is available for the function. */
1303 /* The number of an odd floating-point register, that should be used
1304 for the next argument of type float. */
1305 int free_single_fp_reg
;
1306 /* Whether we're processing an outgoing function call. */
1308 /* The number of general-purpose registers that should have been
1309 used to pass partial arguments, that are passed totally on the
1310 stack. On SHcompact, a call trampoline will pop them off the
1311 stack before calling the actual function, and, if the called
1312 function is implemented in SHcompact mode, the incoming arguments
1313 decoder will push such arguments back onto the stack. For
1314 incoming arguments, STACK_REGS also takes into account other
1315 arguments passed by reference, that the decoder will also push
1318 /* The number of general-purpose registers that should have been
1319 used to pass arguments, if the arguments didn't have to be passed
1322 /* Set as by shcompact_byref if the current argument is to be passed
1326 /* call_cookie is a bitmask used by call expanders, as well as
1327 function prologue and epilogues, to allow SHcompact to comply
1328 with the SH5 32-bit ABI, that requires 64-bit registers to be
1329 used even though only the lower 32-bit half is visible in
1330 SHcompact mode. The strategy is to call SHmedia trampolines.
1332 The alternatives for each of the argument-passing registers are
1333 (a) leave it unchanged; (b) pop it off the stack; (c) load its
1334 contents from the address in it; (d) add 8 to it, storing the
1335 result in the next register, then (c); (e) copy it from some
1336 floating-point register,
1338 Regarding copies from floating-point registers, r2 may only be
1339 copied from dr0. r3 may be copied from dr0 or dr2. r4 maybe
1340 copied from dr0, dr2 or dr4. r5 maybe copied from dr0, dr2,
1341 dr4 or dr6. r6 may be copied from dr0, dr2, dr4, dr6 or dr8.
1342 r7 through to r9 may be copied from dr0, dr2, dr4, dr8, dr8 or
1345 The bit mask is structured as follows:
1347 - 1 bit to tell whether to set up a return trampoline.
1349 - 3 bits to count the number consecutive registers to pop off the
1352 - 4 bits for each of r9, r8, r7 and r6.
1354 - 3 bits for each of r5, r4, r3 and r2.
1356 - 3 bits set to 0 (the most significant ones)
1359 1098 7654 3210 9876 5432 1098 7654 3210
1360 FLPF LPFL PFLP FFLP FFLP FFLP FFLP SSST
1361 2223 3344 4555 6666 7777 8888 9999 SSS-
1363 - If F is set, the register must be copied from an FP register,
1364 whose number is encoded in the remaining bits.
1366 - Else, if L is set, the register must be loaded from the address
1367 contained in it. If the P bit is *not* set, the address of the
1368 following dword should be computed first, and stored in the
1371 - Else, if P is set, the register alone should be popped off the
1374 - After all this processing, the number of registers represented
1375 in SSS will be popped off the stack. This is an optimization
1376 for pushing/popping consecutive registers, typically used for
1377 varargs and large arguments partially passed in registers.
1379 - If T is set, a return trampoline will be set up for 64-bit
1380 return values to be split into 2 32-bit registers. */
1383 /* This is set to nonzero when the call in question must use the Renesas ABI,
1384 even without the -mrenesas option. */
1388 #define CALL_COOKIE_RET_TRAMP_SHIFT 0
1389 #define CALL_COOKIE_RET_TRAMP(VAL) ((VAL) << CALL_COOKIE_RET_TRAMP_SHIFT)
1390 #define CALL_COOKIE_STACKSEQ_SHIFT 1
1391 #define CALL_COOKIE_STACKSEQ(VAL) ((VAL) << CALL_COOKIE_STACKSEQ_SHIFT)
1392 #define CALL_COOKIE_STACKSEQ_GET(COOKIE) \
1393 (((COOKIE) >> CALL_COOKIE_STACKSEQ_SHIFT) & 7)
1394 #define CALL_COOKIE_INT_REG_SHIFT(REG) \
1395 (4 * (7 - (REG)) + (((REG) <= 2) ? ((REG) - 2) : 1) + 3)
1396 #define CALL_COOKIE_INT_REG(REG, VAL) \
1397 ((VAL) << CALL_COOKIE_INT_REG_SHIFT (REG))
1398 #define CALL_COOKIE_INT_REG_GET(COOKIE, REG) \
1399 (((COOKIE) >> CALL_COOKIE_INT_REG_SHIFT (REG)) & ((REG) < 4 ? 7 : 15))
1401 #define CUMULATIVE_ARGS struct sh_args
1403 #define GET_SH_ARG_CLASS(MODE) \
1404 ((TARGET_FPU_ANY && (MODE) == SFmode) \
1406 /* There's no mention of complex float types in the SH5 ABI, so we
1407 should presumably handle them as aggregate types. */ \
1408 : TARGET_SH5 && GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT \
1410 : TARGET_FPU_DOUBLE && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1411 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
1412 ? SH_ARG_FLOAT : SH_ARG_INT)
1414 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1415 for a call to a function whose data type is FNTYPE.
1416 For a library call, FNTYPE is 0.
1418 On SH, the offset always starts at 0: the first parm reg is always
1419 the same reg for a given argument class.
1421 For TARGET_HITACHI, the structure value pointer is passed in memory. */
1422 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1423 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\
1424 (N_NAMED_ARGS), VOIDmode)
1426 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1427 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE))
1429 /* By accident we got stuck with passing SCmode on SH4 little endian
1430 in two registers that are nominally successive - which is different from
1431 two single SFmode values, where we take endianness translation into
1432 account. That does not work at all if an odd number of registers is
1433 already in use, so that got fixed, but library functions are still more
1434 likely to use complex numbers without mixing them with SFmode arguments
1435 (which in C would have to be structures), so for the sake of ABI
1436 compatibility the way SCmode values are passed when an even number of
1437 FP registers is in use remains different from a pair of SFmode values for
1440 foo (double); a: fr5,fr4
1441 foo (float a, float b); a: fr5 b: fr4
1442 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency,
1443 this should be the other way round...
1444 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */
1445 #define FUNCTION_ARG_SCmode_WART 1
1447 /* If an argument of size 5, 6 or 7 bytes is to be passed in a 64-bit
1448 register in SHcompact mode, it must be padded in the most
1449 significant end. This means that passing it by reference wouldn't
1450 pad properly on a big-endian machine. In this particular case, we
1451 pass this argument on the stack, in a way that the call trampoline
1452 will load its value into the appropriate register. */
1453 #define SHCOMPACT_FORCE_ON_STACK(MODE,TYPE) \
1454 ((MODE) == BLKmode \
1455 && TARGET_SHCOMPACT \
1456 && TARGET_BIG_ENDIAN \
1457 && int_size_in_bytes (TYPE) > 4 \
1458 && int_size_in_bytes (TYPE) < 8)
1460 /* Minimum alignment for an argument to be passed by callee-copy
1461 reference. We need such arguments to be aligned to 8 byte
1462 boundaries, because they'll be loaded using quad loads. */
1463 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT)
1465 /* The SH5 ABI requires floating-point arguments to be passed to
1466 functions without a prototype in both an FP register and a regular
1467 register or the stack. When passing the argument in both FP and
1468 general-purpose registers, list the FP register first. */
1469 #define SH5_PROTOTYPELESS_FLOAT_ARG(CUM,MODE) \
1475 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1476 ? gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1477 + (CUM).arg_count[(int) SH_ARG_FLOAT]) \
1482 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1483 ? gen_rtx_REG ((MODE), FIRST_PARM_REG \
1484 + (CUM).arg_count[(int) SH_ARG_INT]) \
1485 : gen_rtx_REG ((MODE), FIRST_FP_PARM_REG \
1486 + (CUM).arg_count[(int) SH_ARG_FLOAT])), \
1489 /* The SH5 ABI requires regular registers or stack slots to be
1490 reserved for floating-point arguments. Registers are taken care of
1491 in FUNCTION_ARG_ADVANCE, but stack slots must be reserved here.
1492 Unfortunately, there's no way to just reserve a stack slot, so
1493 we'll end up needlessly storing a copy of the argument in the
1494 stack. For incoming arguments, however, the PARALLEL will be
1495 optimized to the register-only form, and the value in the stack
1496 slot won't be used at all. */
1497 #define SH5_PROTOTYPED_FLOAT_ARG(CUM,MODE,REG) \
1498 ((CUM).arg_count[(int) SH_ARG_INT] < NPARM_REGS (SImode) \
1499 ? gen_rtx_REG ((MODE), (REG)) \
1500 : gen_rtx_PARALLEL ((MODE), \
1503 (VOIDmode, NULL_RTX, \
1506 (VOIDmode, gen_rtx_REG ((MODE), \
1510 #define SH5_WOULD_BE_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1512 && ((MODE) == BLKmode || (MODE) == TImode || (MODE) == CDImode \
1513 || (MODE) == DCmode) \
1514 && ((CUM).arg_count[(int) SH_ARG_INT] \
1515 + (((MODE) == BLKmode ? int_size_in_bytes (TYPE) \
1516 : GET_MODE_SIZE (MODE)) \
1517 + 7) / 8) > NPARM_REGS (SImode))
1519 /* Perform any needed actions needed for a function that is receiving a
1520 variable number of arguments. */
1522 /* Call the function profiler with a given profile label.
1523 We use two .aligns, so as to make sure that both the .long is aligned
1524 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes)
1525 from the trapa instruction. */
1526 #define FUNCTION_PROFILER(STREAM,LABELNO) \
1528 if (TARGET_SHMEDIA) \
1530 fprintf((STREAM), "\tmovi\t33,r0\n"); \
1531 fprintf((STREAM), "\ttrapa\tr0\n"); \
1532 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1536 fprintf((STREAM), "\t.align\t2\n"); \
1537 fprintf((STREAM), "\ttrapa\t#33\n"); \
1538 fprintf((STREAM), "\t.align\t2\n"); \
1539 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \
1543 /* Define this macro if the code for function profiling should come
1544 before the function prologue. Normally, the profiling code comes
1546 #define PROFILE_BEFORE_PROLOGUE
1548 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1549 the stack pointer does not matter. The value is tested only in
1550 functions that have frame pointers.
1551 No definition is equivalent to always zero. */
1552 #define EXIT_IGNORE_STACK 1
1555 On the SH, the trampoline looks like
1556 2 0002 D202 mov.l l2,r2
1557 1 0000 D301 mov.l l1,r3
1560 5 0008 00000000 l1: .long area
1561 6 000c 00000000 l2: .long function */
1563 /* Length in units of the trampoline for entering a nested function. */
1564 #define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
1566 /* Alignment required for a trampoline in bits. */
1567 #define TRAMPOLINE_ALIGNMENT \
1569 || (optimize_size && ! (TARGET_HARD_SH4 || TARGET_SH5))) ? 32 \
1570 : TARGET_SHMEDIA ? 256 : 64)
1572 /* A C expression whose value is RTL representing the value of the return
1573 address for the frame COUNT steps up from the current frame.
1574 FRAMEADDR is already the frame pointer of the COUNT frame, so we
1575 can ignore COUNT. */
1576 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1577 (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX)
1579 /* A C expression whose value is RTL representing the location of the
1580 incoming return address at the beginning of any function, before the
1581 prologue. This RTL is either a REG, indicating that the return
1582 value is saved in REG, or a MEM representing a location in
1584 #define INCOMING_RETURN_ADDR_RTX \
1585 gen_rtx_REG (Pmode, TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG)
1587 /* Addressing modes, and classification of registers for them. */
1588 #define HAVE_POST_INCREMENT TARGET_SH1
1589 #define HAVE_PRE_DECREMENT TARGET_SH1
1591 #define USE_LOAD_POST_INCREMENT(mode) ((mode == SImode || mode == DImode) \
1593 #define USE_LOAD_PRE_DECREMENT(mode) 0
1594 #define USE_STORE_POST_INCREMENT(mode) 0
1595 #define USE_STORE_PRE_DECREMENT(mode) ((mode == SImode || mode == DImode) \
1598 /* If a memory clear move would take CLEAR_RATIO or more simple
1599 move-instruction pairs, we will do a setmem instead. */
1601 #define CLEAR_RATIO(speed) ((speed) ? 15 : 3)
1603 /* Macros to check register numbers against specific register classes. */
1605 /* These assume that REGNO is a hard or pseudo reg number.
1606 They give nonzero only if REGNO is a hard reg of the suitable class
1607 or a pseudo reg currently allocated to a suitable hard reg.
1608 Since they use reg_renumber, they are safe only once reg_renumber
1609 has been allocated, which happens in reginfo.c during register
1611 #define REGNO_OK_FOR_BASE_P(REGNO) \
1612 (GENERAL_OR_AP_REGISTER_P (REGNO) \
1613 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)]))
1614 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1616 ? (GENERAL_REGISTER_P (REGNO) \
1617 || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
1618 : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
1620 /* Maximum number of registers that can appear in a valid memory
1622 #define MAX_REGS_PER_ADDRESS 2
1624 /* Recognize any constant value that is a valid address. */
1625 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
1627 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1628 and check its validity for a certain class.
1629 The suitable hard regs are always accepted and all pseudo regs
1630 are also accepted if STRICT is not set. */
1632 /* Nonzero if X is a reg that can be used as a base reg. */
1633 #define REG_OK_FOR_BASE_P(X, STRICT) \
1634 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \
1635 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1637 /* Nonzero if X is a reg that can be used as an index. */
1638 #define REG_OK_FOR_INDEX_P(X, STRICT) \
1639 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1640 : REGNO (X) == R0_REG) \
1641 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1643 /* Nonzero if X/OFFSET is a reg that can be used as an index. */
1644 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \
1645 ((TARGET_SHMEDIA ? GENERAL_REGISTER_P (REGNO (X)) \
1646 : REGNO (X) == R0_REG && OFFSET == 0) \
1647 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER))
1649 /* Macros for extra constraints. */
1651 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
1652 ((GET_CODE ((OP)) == LABEL_REF) \
1653 || (GET_CODE ((OP)) == CONST \
1654 && GET_CODE (XEXP ((OP), 0)) == PLUS \
1655 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1656 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1658 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \
1660 && !CONST_INT_P (OP) \
1661 && GET_CODE (OP) != CONST_DOUBLE \
1663 || (LEGITIMATE_PIC_OPERAND_P (OP) \
1664 && !PIC_ADDR_P (OP) \
1665 && GET_CODE (OP) != LABEL_REF)))
1667 /* Check whether OP is a datalabel unspec. */
1668 #define DATALABEL_REF_NO_CONST_P(OP) \
1669 (GET_CODE (OP) == UNSPEC \
1670 && XINT ((OP), 1) == UNSPEC_DATALABEL \
1671 && XVECLEN ((OP), 0) == 1 \
1672 && GET_CODE (XVECEXP ((OP), 0, 0)) == LABEL_REF)
1674 #define GOT_ENTRY_P(OP) \
1675 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1676 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT)
1678 #define GOTPLT_ENTRY_P(OP) \
1679 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1680 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT)
1682 #define UNSPEC_GOTOFF_P(OP) \
1683 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF)
1685 #define GOTOFF_P(OP) \
1686 (GET_CODE (OP) == CONST \
1687 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \
1688 || (GET_CODE (XEXP ((OP), 0)) == PLUS \
1689 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \
1690 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))))
1692 #define PIC_ADDR_P(OP) \
1693 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1694 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC)
1696 #define PCREL_SYMOFF_P(OP) \
1697 (GET_CODE (OP) == CONST \
1698 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
1699 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
1701 #define NON_PIC_REFERENCE_P(OP) \
1702 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
1703 || (GET_CODE (OP) == CONST \
1704 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
1705 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF \
1706 || DATALABEL_REF_NO_CONST_P (XEXP ((OP), 0)))) \
1707 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
1708 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
1709 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
1710 || DATALABEL_REF_NO_CONST_P (XEXP (XEXP ((OP), 0), 0))) \
1711 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
1713 #define PIC_REFERENCE_P(OP) \
1714 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \
1715 || GOTOFF_P (OP) || PIC_ADDR_P (OP))
1717 #define MOVI_SHORI_BASE_OPERAND_P(OP) \
1719 ? (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) || GOTOFF_P (OP) \
1720 || PCREL_SYMOFF_P (OP)) \
1721 : NON_PIC_REFERENCE_P (OP))
1723 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
1724 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
1725 || (GET_CODE (X) == SUBREG \
1726 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1727 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1728 && REG_P (SUBREG_REG (X)) \
1729 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
1731 /* Since this must be r0, which is a single register class, we must check
1732 SUBREGs more carefully, to be sure that we don't accept one that extends
1733 outside the class. */
1734 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
1735 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
1736 || (GET_CODE (X) == SUBREG \
1737 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE ((X))), \
1738 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (X)))) \
1739 && REG_P (SUBREG_REG (X)) \
1740 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
1742 #ifdef REG_OK_STRICT
1743 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true)
1744 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true)
1746 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false)
1747 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false)
1750 #define ALLOW_INDEXED_ADDRESS \
1751 ((!TARGET_SHMEDIA32 && !TARGET_SHCOMPACT) || TARGET_ALLOW_INDEXED_ADDRESS)
1753 /* A C compound statement that attempts to replace X, which is an address
1754 that needs reloading, with a valid memory address for an operand of
1755 mode MODE. WIN is a C statement label elsewhere in the code. */
1756 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1758 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \
1762 /* Specify the machine mode that this machine uses
1763 for the index in the tablejump instruction. */
1764 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode)
1766 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \
1767 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \
1768 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \
1769 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \
1770 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \
1771 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \
1774 /* Define as C expression which evaluates to nonzero if the tablejump
1775 instruction expects the table to contain offsets from the address of the
1777 Do not define this if the table should contain absolute addresses. */
1778 #define CASE_VECTOR_PC_RELATIVE 1
1780 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */
1781 #define FLOAT_TYPE_SIZE 32
1783 /* Since the SH2e has only `float' support, it is desirable to make all
1784 floating point types equivalent to `float'. */
1785 #define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE)\
1788 /* 'char' is signed by default. */
1789 #define DEFAULT_SIGNED_CHAR 1
1791 /* The type of size_t unsigned int. */
1792 #define SIZE_TYPE (TARGET_SH5 ? "long unsigned int" : "unsigned int")
1795 #define PTRDIFF_TYPE (TARGET_SH5 ? "long int" : "int")
1797 #define WCHAR_TYPE "short unsigned int"
1798 #define WCHAR_TYPE_SIZE 16
1800 #define SH_ELF_WCHAR_TYPE "long int"
1802 /* Max number of bytes we can move from memory to memory
1803 in one reasonably fast instruction. */
1804 #define MOVE_MAX (TARGET_SHMEDIA ? 8 : 4)
1806 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever
1807 MOVE_MAX is not a compile-time constant. */
1808 #define MAX_MOVE_MAX 8
1810 /* Max number of bytes we want move_by_pieces to be able to copy
1812 #define MOVE_MAX_PIECES (TARGET_SH4 || TARGET_SHMEDIA ? 8 : 4)
1814 /* Define if operations between registers always perform the operation
1815 on the full register even if a narrower mode is specified. */
1816 #define WORD_REGISTER_OPERATIONS
1818 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1819 will either zero-extend or sign-extend. The value of this macro should
1820 be the code that says which one of the two operations is implicitly
1821 done, UNKNOWN if none.
1822 For SHmedia, we can truncate to QImode easier using zero extension.
1823 FP registers can load SImode values, but don't implicitly sign-extend
1825 #define LOAD_EXTEND_OP(MODE) \
1826 (((MODE) == QImode && TARGET_SHMEDIA) ? ZERO_EXTEND \
1827 : (MODE) != SImode ? SIGN_EXTEND : UNKNOWN)
1829 /* Define if loading short immediate values into registers sign extends. */
1830 #define SHORT_IMMEDIATES_SIGN_EXTEND
1832 /* Nonzero if access to memory by bytes is no faster than for words. */
1833 #define SLOW_BYTE_ACCESS 1
1835 /* Nonzero if the target supports dynamic shift instructions
1836 like shad and shld. */
1837 #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
1839 /* The cost of using the dynamic shift insns (shad, shld) are the same
1840 if they are available. If they are not available a library function will
1841 be emitted instead, which is more expensive. */
1842 #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20)
1844 /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like
1845 (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
1846 This is not generally true when hardware dynamic shifts (shad, shld) are
1847 used, because they check the sign bit _before_ the modulo op. The sign
1848 bit determines whether it is a left shift or a right shift:
1850 return X << (Y & 31);
1852 return X >> (-Y) & 31);
1854 The dynamic shift library routines in lib1funcs.S do not use the sign bit
1855 like the hardware dynamic shifts and truncate the shift count to 31.
1856 We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count
1857 truncation in the library function call patterns, as this gives slightly
1858 more compact code. */
1859 #define SHIFT_COUNT_TRUNCATED (0)
1861 /* All integers have the same format so truncation is easy. */
1862 /* But SHmedia must sign-extend DImode when truncating to SImode. */
1863 #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) \
1864 (!TARGET_SHMEDIA || (INPREC) < 64 || (OUTPREC) >= 64)
1866 /* Define this if addresses of constant functions
1867 shouldn't be put through pseudo regs where they can be cse'd.
1868 Desirable on machines where ordinary constants are expensive
1869 but a CALL with constant address is cheap. */
1870 /*#define NO_FUNCTION_CSE 1*/
1872 /* The machine modes of pointers and functions. */
1873 #define Pmode (TARGET_SHMEDIA64 ? DImode : SImode)
1874 #define FUNCTION_MODE Pmode
1876 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2
1877 are actually function calls with some special constraints on arguments
1880 These macros tell reorg that the references to arguments and
1881 register clobbers for insns of type sfunc do not appear to happen
1882 until after the millicode call. This allows reorg to put insns
1883 which set the argument registers into the delay slot of the millicode
1884 call -- thus they act more like traditional CALL_INSNs.
1886 get_attr_is_sfunc will try to recognize the given insn, so make sure to
1887 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1890 #define INSN_SETS_ARE_DELAYED(X) \
1891 ((NONJUMP_INSN_P (X) \
1892 && GET_CODE (PATTERN (X)) != SEQUENCE \
1893 && GET_CODE (PATTERN (X)) != USE \
1894 && GET_CODE (PATTERN (X)) != CLOBBER \
1895 && get_attr_is_sfunc (X)))
1897 #define INSN_REFERENCES_ARE_DELAYED(X) \
1898 ((NONJUMP_INSN_P (X) \
1899 && GET_CODE (PATTERN (X)) != SEQUENCE \
1900 && GET_CODE (PATTERN (X)) != USE \
1901 && GET_CODE (PATTERN (X)) != CLOBBER \
1902 && get_attr_is_sfunc (X)))
1905 /* Position Independent Code. */
1907 /* We can't directly access anything that contains a symbol,
1908 nor can we indirect via the constant pool. */
1909 #define LEGITIMATE_PIC_OPERAND_P(X) \
1910 ((! nonpic_symbol_mentioned_p (X) \
1911 && (GET_CODE (X) != SYMBOL_REF \
1912 || ! CONSTANT_POOL_ADDRESS_P (X) \
1913 || ! nonpic_symbol_mentioned_p (get_pool_constant (X)))) \
1914 || (TARGET_SHMEDIA && GET_CODE (X) == LABEL_REF))
1916 #define SYMBOLIC_CONST_P(X) \
1917 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
1918 && nonpic_symbol_mentioned_p (X))
1920 /* Compute extra cost of moving data between one register class
1923 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
1924 uses this information. Hence, the general register <-> floating point
1925 register information here is not used for SFmode. */
1926 #define REGCLASS_HAS_GENERAL_REG(CLASS) \
1927 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \
1928 || (! TARGET_SHMEDIA && (CLASS) == SIBCALL_REGS))
1930 #define REGCLASS_HAS_FP_REG(CLASS) \
1931 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \
1932 || (CLASS) == DF_REGS)
1934 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This
1935 would be so that people with slow memory systems could generate
1936 different code that does fewer memory accesses. */
1938 /* A C expression for the cost of a branch instruction. A value of 1
1939 is the default; other values are interpreted relative to that. */
1940 #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost
1942 /* Assembler output control. */
1944 /* A C string constant describing how to begin a comment in the target
1945 assembler language. The compiler assumes that the comment will end at
1946 the end of the line. */
1947 #define ASM_COMMENT_START "!"
1949 #define ASM_APP_ON ""
1950 #define ASM_APP_OFF ""
1951 #define FILE_ASM_OP "\t.file\n"
1952 #define SET_ASM_OP "\t.set\t"
1954 /* How to change between sections. */
1955 #define TEXT_SECTION_ASM_OP (TARGET_SHMEDIA32 \
1956 ? "\t.section\t.text..SHmedia32,\"ax\"" \
1958 #define DATA_SECTION_ASM_OP "\t.data"
1960 #if defined CRT_BEGIN || defined CRT_END
1961 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */
1962 # undef TEXT_SECTION_ASM_OP
1963 # if __SHMEDIA__ == 1 && __SH5__ == 32
1964 # define TEXT_SECTION_ASM_OP "\t.section\t.text..SHmedia32,\"ax\""
1966 # define TEXT_SECTION_ASM_OP "\t.text"
1970 #ifndef BSS_SECTION_ASM_OP
1971 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
1974 #ifndef ASM_OUTPUT_ALIGNED_BSS
1975 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1976 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
1979 /* Define this so that jump tables go in same section as the current function,
1980 which could be text or it could be a user defined section. */
1981 #define JUMP_TABLES_IN_TEXT_SECTION 1
1983 #undef DO_GLOBAL_CTORS_BODY
1984 #define DO_GLOBAL_CTORS_BODY \
1986 typedef void (*pfunc) (void); \
1987 extern pfunc __ctors[]; \
1988 extern pfunc __ctors_end[]; \
1990 for (p = __ctors_end; p > __ctors; ) \
1996 #undef DO_GLOBAL_DTORS_BODY
1997 #define DO_GLOBAL_DTORS_BODY \
1999 typedef void (*pfunc) (void); \
2000 extern pfunc __dtors[]; \
2001 extern pfunc __dtors_end[]; \
2003 for (p = __dtors; p < __dtors_end; p++) \
2009 #define ASM_OUTPUT_REG_PUSH(file, v) \
2011 if (TARGET_SHMEDIA) \
2013 fprintf ((file), "\taddi.l\tr15,-8,r15\n"); \
2014 fprintf ((file), "\tst.q\tr15,0,r%d\n", (v)); \
2017 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \
2020 #define ASM_OUTPUT_REG_POP(file, v) \
2022 if (TARGET_SHMEDIA) \
2024 fprintf ((file), "\tld.q\tr15,0,r%d\n", (v)); \
2025 fprintf ((file), "\taddi.l\tr15,8,r15\n"); \
2028 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \
2031 /* DBX register number for a given compiler register number. */
2032 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers
2034 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a
2035 register exists, so we should return -1 for invalid register numbers. */
2036 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
2038 /* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
2039 used to use the encodings 245..260, but that doesn't make sense:
2040 PR_REG and PR_MEDIA_REG are actually the same register, and likewise
2041 the FP registers stay the same when switching between compact and media
2042 mode. Hence, we also need to use the same dwarf frame columns.
2043 Likewise, we need to support unwind information for SHmedia registers
2044 even in compact code. */
2045 #define SH_DBX_REGISTER_NUMBER(REGNO) \
2046 (IN_RANGE ((REGNO), \
2047 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
2048 FIRST_GENERAL_REG + (TARGET_SH5 ? 63U :15U)) \
2049 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \
2050 : ((int) (REGNO) >= FIRST_FP_REG \
2052 <= (FIRST_FP_REG + \
2053 ((TARGET_SH5 && TARGET_FPU_ANY) ? 63 : TARGET_SH2E ? 15 : -1)))) \
2054 ? ((unsigned) (REGNO) - FIRST_FP_REG \
2055 + (TARGET_SH5 ? 77 : 25)) \
2056 : XD_REGISTER_P (REGNO) \
2057 ? ((unsigned) (REGNO) - FIRST_XD_REG + (TARGET_SH5 ? 289 : 87)) \
2058 : TARGET_REGISTER_P (REGNO) \
2059 ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
2060 : (REGNO) == PR_REG \
2061 ? (TARGET_SH5 ? 18 : 17) \
2062 : (REGNO) == PR_MEDIA_REG \
2063 ? (TARGET_SH5 ? 18 : (unsigned) -1) \
2064 : (REGNO) == GBR_REG \
2065 ? (TARGET_SH5 ? 238 : 18) \
2066 : (REGNO) == MACH_REG \
2067 ? (TARGET_SH5 ? 239 : 20) \
2068 : (REGNO) == MACL_REG \
2069 ? (TARGET_SH5 ? 240 : 21) \
2070 : (REGNO) == T_REG \
2071 ? (TARGET_SH5 ? 242 : 22) \
2072 : (REGNO) == FPUL_REG \
2073 ? (TARGET_SH5 ? 244 : 23) \
2074 : (REGNO) == FPSCR_REG \
2075 ? (TARGET_SH5 ? 243 : 24) \
2078 /* This is how to output a reference to a symbol_ref. On SH5,
2079 references to non-code symbols must be preceded by `datalabel'. */
2080 #define ASM_OUTPUT_SYMBOL_REF(FILE,SYM) \
2083 if (TARGET_SH5 && !SYMBOL_REF_FUNCTION_P (SYM)) \
2084 fputs ("datalabel ", (FILE)); \
2085 assemble_name ((FILE), XSTR ((SYM), 0)); \
2089 /* This is how to output an assembler line
2090 that says to advance the location counter
2091 to a multiple of 2**LOG bytes. */
2093 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2095 fprintf ((FILE), "\t.align %d\n", (LOG))
2097 /* Globalizing directive for a label. */
2098 #define GLOBAL_ASM_OP "\t.global\t"
2100 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */
2102 /* Output a relative address table. */
2103 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \
2104 switch (GET_MODE (BODY)) \
2109 asm_fprintf ((STREAM), "\t.long\t%LL%d-datalabel %LL%d\n", \
2113 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2118 asm_fprintf ((STREAM), "\t.word\t%LL%d-datalabel %LL%d\n", \
2122 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2127 asm_fprintf ((STREAM), "\t.byte\t%LL%d-datalabel %LL%d\n", \
2131 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \
2137 /* Output an absolute table element. */
2138 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \
2139 if (! optimize || TARGET_BIGTABLE) \
2140 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \
2142 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE));
2145 /* A C statement to be executed just prior to the output of
2146 assembler code for INSN, to modify the extracted operands so
2147 they will be output differently.
2149 Here the argument OPVEC is the vector containing the operands
2150 extracted from INSN, and NOPERANDS is the number of elements of
2151 the vector which contain meaningful data for this insn.
2152 The contents of this vector are what will be used to convert the insn
2153 template into assembler code, so you can change the assembler output
2154 by changing the contents of the vector. */
2155 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2156 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
2159 extern rtx sh_compare_op0
;
2160 extern rtx sh_compare_op1
;
2162 /* Which processor to schedule for. The elements of the enumeration must
2163 match exactly the cpu attribute in the sh.md file. */
2164 enum processor_type
{
2176 #define sh_cpu_attr ((enum attr_cpu)sh_cpu)
2177 extern enum processor_type sh_cpu
;
2179 enum mdep_reorg_phase_e
2181 SH_BEFORE_MDEP_REORG
,
2182 SH_INSERT_USES_LABELS
,
2183 SH_SHORTEN_BRANCHES0
,
2185 SH_SHORTEN_BRANCHES1
,
2189 extern enum mdep_reorg_phase_e mdep_reorg_phase
;
2191 /* Handle Renesas compiler's pragmas. */
2192 #define REGISTER_TARGET_PRAGMAS() do { \
2193 c_register_pragma (0, "interrupt", sh_pr_interrupt); \
2194 c_register_pragma (0, "trapa", sh_pr_trapa); \
2195 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \
2198 extern tree sh_deferred_function_attributes
;
2199 extern tree
*sh_deferred_function_attributes_tail
;
2201 /* Set when processing a function with interrupt attribute. */
2202 extern int current_function_interrupt
;
2205 /* Instructions with unfilled delay slots take up an
2206 extra two bytes for the nop in the delay slot.
2207 sh-dsp parallel processing insns are four bytes long. */
2208 #define ADJUST_INSN_LENGTH(X, LENGTH) \
2209 (LENGTH) += sh_insn_length_adjustment (X);
2211 /* Define this macro if it is advisable to hold scalars in registers
2212 in a wider mode than that declared by the program. In such cases,
2213 the value is constrained to be within the bounds of the declared
2214 type, but kept valid in the wider mode. The signedness of the
2215 extension may differ from that of the type.
2217 Leaving the unsignedp unchanged gives better code than always setting it
2218 to 0. This is despite the fact that we have only signed char and short
2219 load instructions. */
2220 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
2221 if (GET_MODE_CLASS (MODE) == MODE_INT \
2222 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\
2223 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), \
2224 (MODE) = (TARGET_SH1 ? SImode \
2225 : TARGET_SHMEDIA32 ? SImode : DImode);
2227 #define MAX_FIXED_MODE_SIZE (TARGET_SH5 ? 128 : 64)
2229 /* Better to allocate once the maximum space for outgoing args in the
2230 prologue rather than duplicate around each call. */
2231 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS
2233 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
2235 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
2237 #define ACTUAL_NORMAL_MODE(ENTITY) \
2238 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
2240 #define NORMAL_MODE(ENTITY) \
2241 (sh_cfun_interrupt_handler_p () \
2242 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \
2243 : ACTUAL_NORMAL_MODE (ENTITY))
2245 #define EPILOGUE_USES(REGNO) ((TARGET_SH2E || TARGET_SH4) \
2246 && (REGNO) == FPSCR_REG)
2248 #define MD_CAN_REDIRECT_BRANCH(INSN, SEQ) \
2249 sh_can_redirect_branch ((INSN), (SEQ))
2251 #define DWARF_FRAME_RETURN_COLUMN \
2252 (TARGET_SH5 ? DWARF_FRAME_REGNUM (PR_MEDIA_REG) : DWARF_FRAME_REGNUM (PR_REG))
2254 #define EH_RETURN_DATA_REGNO(N) \
2255 ((N) < 4 ? (N) + (TARGET_SH5 ? 2U : 4U) : INVALID_REGNUM)
2257 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM
2258 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO)
2260 /* We have to distinguish between code and data, so that we apply
2261 datalabel where and only where appropriate. Use sdataN for data. */
2262 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
2263 ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
2264 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
2265 | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
2267 /* Handle special EH pointer encodings. Absolute, pc-relative, and
2268 indirect are handled automatically. */
2269 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
2271 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
2272 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
2274 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
2275 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
2280 #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
2281 /* SH constant pool breaks the devices in crtstuff.c to control section
2282 in where code resides. We have to write it as asm code. */
2283 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2284 asm (SECTION_OP "\n\
2290 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\
2291 2:\n" TEXT_SECTION_ASM_OP);
2292 #endif /* (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__ */
2294 #endif /* ! GCC_SH_H */
git://gcc.gnu.org / gcc.git / blob