1 /* Output routines for GCC for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
30 #include "insn-flags.h"
34 #include "hard-reg-set.h"
36 #include "insn-attr.h"
42 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
44 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
45 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
47 /* ??? The pragma interrupt support will not work for SH3. */
48 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
49 output code for the next function appropriate for an interrupt handler. */
52 /* This is set by the trap_exit attribute for functions. It specifies
53 a trap number to be used in a trapa instruction at function exit
54 (instead of an rte instruction). */
57 /* This is used by the sp_switch attribute for functions. It specifies
58 a variable holding the address of the stack the interrupt function
59 should switch to/from at entry/exit. */
62 /* This is set by #pragma trapa, and is similar to the above, except that
63 the compiler doesn't emit code to preserve all registers. */
64 static int pragma_trapa
;
66 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
67 which has a separate set of low regs for User and Supervisor modes.
68 This should only be used for the lowest level of interrupts. Higher levels
69 of interrupts must save the registers in case they themselves are
71 int pragma_nosave_low_regs
;
73 /* This is used for communication between SETUP_INCOMING_VARARGS and
74 sh_expand_prologue. */
75 int current_function_anonymous_args
;
77 /* Global variables for machine-dependent things. */
79 /* Which cpu are we scheduling for. */
80 enum processor_type sh_cpu
;
82 /* Saved operands from the last compare to use when we generate an scc
88 /* Provides the class number of the smallest class containing
91 int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
93 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
94 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
95 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
96 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
97 GENERAL_REGS
, PR_REGS
, T_REGS
, NO_REGS
,
98 MAC_REGS
, MAC_REGS
, FPUL_REGS
, GENERAL_REGS
,
99 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
100 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
101 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
102 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
103 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
104 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
108 char fp_reg_names
[][5] =
110 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
111 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
113 "xd0","xd2","xd4", "xd6", "xd8", "xd10", "xd12", "xd14",
116 /* Provide reg_class from a letter such as appears in the machine
119 enum reg_class reg_class_from_letter
[] =
121 /* a */ ALL_REGS
, /* b */ NO_REGS
, /* c */ FPSCR_REGS
, /* d */ DF_REGS
,
122 /* e */ NO_REGS
, /* f */ FP_REGS
, /* g */ NO_REGS
, /* h */ NO_REGS
,
123 /* i */ NO_REGS
, /* j */ NO_REGS
, /* k */ SIBCALL_REGS
, /* l */ PR_REGS
,
124 /* m */ NO_REGS
, /* n */ NO_REGS
, /* o */ NO_REGS
, /* p */ NO_REGS
,
125 /* q */ NO_REGS
, /* r */ NO_REGS
, /* s */ NO_REGS
, /* t */ T_REGS
,
126 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ FP0_REGS
, /* x */ MAC_REGS
,
127 /* y */ FPUL_REGS
, /* z */ R0_REGS
130 int assembler_dialect
;
132 static void split_branches
PARAMS ((rtx
));
133 static int branch_dest
PARAMS ((rtx
));
134 static void force_into
PARAMS ((rtx
, rtx
));
135 static void print_slot
PARAMS ((rtx
));
136 static rtx add_constant
PARAMS ((rtx
, enum machine_mode
, rtx
));
137 static void dump_table
PARAMS ((rtx
));
138 static int hi_const
PARAMS ((rtx
));
139 static int broken_move
PARAMS ((rtx
));
140 static int mova_p
PARAMS ((rtx
));
141 static rtx find_barrier
PARAMS ((int, rtx
, rtx
));
142 static int noncall_uses_reg
PARAMS ((rtx
, rtx
, rtx
*));
143 static rtx gen_block_redirect
PARAMS ((rtx
, int, int));
144 static void output_stack_adjust
PARAMS ((int, rtx
, int));
145 static void push
PARAMS ((int));
146 static void pop
PARAMS ((int));
147 static void push_regs
PARAMS ((int, int));
148 static int calc_live_regs
PARAMS ((int *, int *));
149 static void mark_use
PARAMS ((rtx
, rtx
*));
150 static HOST_WIDE_INT rounded_frame_size
PARAMS ((int));
152 /* Print the operand address in x to the stream. */
155 print_operand_address (stream
, x
)
159 switch (GET_CODE (x
))
163 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
168 rtx base
= XEXP (x
, 0);
169 rtx index
= XEXP (x
, 1);
171 switch (GET_CODE (index
))
174 fprintf (stream
, "@(%d,%s)", INTVAL (index
),
175 reg_names
[true_regnum (base
)]);
181 int base_num
= true_regnum (base
);
182 int index_num
= true_regnum (index
);
184 fprintf (stream
, "@(r0,%s)",
185 reg_names
[MAX (base_num
, index_num
)]);
197 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
201 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
205 output_addr_const (stream
, x
);
210 /* Print operand x (an rtx) in assembler syntax to file stream
211 according to modifier code.
213 '.' print a .s if insn needs delay slot
214 ',' print LOCAL_LABEL_PREFIX
215 '@' print trap, rte or rts depending upon pragma interruptness
216 '#' output a nop if there is nothing to put in the delay slot
217 'O' print a constant without the #
218 'R' print the LSW of a dp value - changes if in little endian
219 'S' print the MSW of a dp value - changes if in little endian
220 'T' print the next word of a dp value - same as 'R' in big endian mode.
221 'o' output an operator. */
224 print_operand (stream
, x
, code
)
233 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
234 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
237 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
241 int interrupt_handler
;
243 if ((lookup_attribute
244 ("interrupt_handler",
245 DECL_MACHINE_ATTRIBUTES (current_function_decl
)))
247 interrupt_handler
= 1;
249 interrupt_handler
= 0;
252 fprintf (stream
, "trapa #%d", trap_exit
);
253 else if (interrupt_handler
)
254 fprintf (stream
, "rte");
256 fprintf (stream
, "rts");
260 /* Output a nop if there's nothing in the delay slot. */
261 if (dbr_sequence_length () == 0)
262 fprintf (stream
, "\n\tnop");
265 output_addr_const (stream
, x
);
268 fputs (reg_names
[REGNO (x
) + LSW
], (stream
));
271 fputs (reg_names
[REGNO (x
) + MSW
], (stream
));
274 /* Next word of a double. */
275 switch (GET_CODE (x
))
278 fputs (reg_names
[REGNO (x
) + 1], (stream
));
281 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
282 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
283 x
= adj_offsettable_operand (x
, 4);
284 print_operand_address (stream
, XEXP (x
, 0));
291 switch (GET_CODE (x
))
293 case PLUS
: fputs ("add", stream
); break;
294 case MINUS
: fputs ("sub", stream
); break;
295 case MULT
: fputs ("mul", stream
); break;
296 case DIV
: fputs ("div", stream
); break;
302 switch (GET_CODE (x
))
305 if (FP_REGISTER_P (REGNO (x
))
306 && GET_MODE_SIZE (GET_MODE (x
)) > 4)
307 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)]+1);
309 fputs (reg_names
[REGNO (x
)], (stream
));
312 output_address (XEXP (x
, 0));
316 output_addr_const (stream
, x
);
323 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
325 force_into (value
, target
)
328 value
= force_operand (value
, target
);
329 if (! rtx_equal_p (value
, target
))
330 emit_insn (gen_move_insn (target
, value
));
333 /* Emit code to perform a block move. Choose the best method.
335 OPERANDS[0] is the destination.
336 OPERANDS[1] is the source.
337 OPERANDS[2] is the size.
338 OPERANDS[3] is the alignment safe to use. */
341 expand_block_move (operands
)
344 int align
= INTVAL (operands
[3]);
345 int constp
= (GET_CODE (operands
[2]) == CONST_INT
);
346 int bytes
= (constp
? INTVAL (operands
[2]) : 0);
348 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
349 alignment, or if it isn't a multiple of 4 bytes, then fail. */
350 if (! constp
|| align
< 4 || (bytes
% 4 != 0))
357 else if (bytes
== 12)
362 rtx r4
= gen_rtx (REG
, SImode
, 4);
363 rtx r5
= gen_rtx (REG
, SImode
, 5);
365 entry_name
= get_identifier ("__movstrSI12_i4");
367 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
368 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
369 force_into (XEXP (operands
[0], 0), r4
);
370 force_into (XEXP (operands
[1], 0), r5
);
371 emit_insn (gen_block_move_real_i4 (func_addr_rtx
));
374 else if (! TARGET_SMALLCODE
)
380 rtx r4
= gen_rtx (REG
, SImode
, 4);
381 rtx r5
= gen_rtx (REG
, SImode
, 5);
382 rtx r6
= gen_rtx (REG
, SImode
, 6);
384 entry_name
= get_identifier (bytes
& 4
386 : "__movstr_i4_even");
387 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
388 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
389 force_into (XEXP (operands
[0], 0), r4
);
390 force_into (XEXP (operands
[1], 0), r5
);
393 emit_insn (gen_move_insn (r6
, GEN_INT (dwords
- 1)));
394 emit_insn (gen_block_lump_real_i4 (func_addr_rtx
));
406 rtx r4
= gen_rtx_REG (SImode
, 4);
407 rtx r5
= gen_rtx_REG (SImode
, 5);
409 sprintf (entry
, "__movstrSI%d", bytes
);
410 entry_name
= get_identifier (entry
);
411 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
412 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
413 force_into (XEXP (operands
[0], 0), r4
);
414 force_into (XEXP (operands
[1], 0), r5
);
415 emit_insn (gen_block_move_real (func_addr_rtx
));
419 /* This is the same number of bytes as a memcpy call, but to a different
420 less common function name, so this will occasionally use more space. */
421 if (! TARGET_SMALLCODE
)
426 int final_switch
, while_loop
;
427 rtx r4
= gen_rtx_REG (SImode
, 4);
428 rtx r5
= gen_rtx_REG (SImode
, 5);
429 rtx r6
= gen_rtx_REG (SImode
, 6);
431 entry_name
= get_identifier ("__movstr");
432 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
433 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
434 force_into (XEXP (operands
[0], 0), r4
);
435 force_into (XEXP (operands
[1], 0), r5
);
437 /* r6 controls the size of the move. 16 is decremented from it
438 for each 64 bytes moved. Then the negative bit left over is used
439 as an index into a list of move instructions. e.g., a 72 byte move
440 would be set up with size(r6) = 14, for one iteration through the
441 big while loop, and a switch of -2 for the last part. */
443 final_switch
= 16 - ((bytes
/ 4) % 16);
444 while_loop
= ((bytes
/ 4) / 16 - 1) * 16;
445 emit_insn (gen_move_insn (r6
, GEN_INT (while_loop
+ final_switch
)));
446 emit_insn (gen_block_lump_real (func_addr_rtx
));
453 /* Prepare operands for a move define_expand; specifically, one of the
454 operands must be in a register. */
457 prepare_move_operands (operands
, mode
)
459 enum machine_mode mode
;
461 if (mode
== SImode
&& flag_pic
)
464 if (SYMBOLIC_CONST_P (operands
[1]))
466 if (GET_CODE (operands
[0]) == MEM
)
467 operands
[1] = force_reg (Pmode
, operands
[1]);
470 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
471 operands
[1] = legitimize_pic_address (operands
[1], SImode
, temp
);
474 else if (GET_CODE (operands
[1]) == CONST
475 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
476 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
478 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
479 SImode
, gen_reg_rtx (Pmode
));
480 operands
[1] = expand_binop (SImode
, add_optab
, temp
,
481 XEXP (XEXP (operands
[1], 0), 1),
482 gen_reg_rtx (Pmode
), 0, OPTAB_LIB_WIDEN
);
486 if (! reload_in_progress
&& ! reload_completed
)
488 /* Copy the source to a register if both operands aren't registers. */
489 if (! register_operand (operands
[0], mode
)
490 && ! register_operand (operands
[1], mode
))
491 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
493 /* This case can happen while generating code to move the result
494 of a library call to the target. Reject `st r0,@(rX,rY)' because
495 reload will fail to find a spill register for rX, since r0 is already
496 being used for the source. */
497 else if (GET_CODE (operands
[1]) == REG
&& REGNO (operands
[1]) == 0
498 && GET_CODE (operands
[0]) == MEM
499 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
500 && GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == REG
)
501 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
507 /* Prepare the operands for an scc instruction; make sure that the
508 compare has been done. */
510 prepare_scc_operands (code
)
513 rtx t_reg
= gen_rtx_REG (SImode
, T_REG
);
514 enum rtx_code oldcode
= code
;
515 enum machine_mode mode
;
517 /* First need a compare insn. */
521 /* It isn't possible to handle this case. */
540 rtx tmp
= sh_compare_op0
;
541 sh_compare_op0
= sh_compare_op1
;
542 sh_compare_op1
= tmp
;
545 mode
= GET_MODE (sh_compare_op0
);
546 if (mode
== VOIDmode
)
547 mode
= GET_MODE (sh_compare_op1
);
549 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
550 if ((code
!= EQ
&& code
!= NE
551 && (sh_compare_op1
!= const0_rtx
552 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
553 || (mode
== DImode
&& sh_compare_op1
!= const0_rtx
)
554 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
555 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
557 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
558 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
)
559 (gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec (2,
560 gen_rtx (SET
, VOIDmode
, t_reg
,
561 gen_rtx (code
, SImode
,
562 sh_compare_op0
, sh_compare_op1
)),
563 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ()))));
565 emit_insn (gen_rtx (SET
, VOIDmode
, t_reg
,
566 gen_rtx (code
, SImode
, sh_compare_op0
,
572 /* Called from the md file, set up the operands of a compare instruction. */
575 from_compare (operands
, code
)
579 enum machine_mode mode
= GET_MODE (sh_compare_op0
);
581 if (mode
== VOIDmode
)
582 mode
= GET_MODE (sh_compare_op1
);
585 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
587 /* Force args into regs, since we can't use constants here. */
588 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
589 if (sh_compare_op1
!= const0_rtx
590 || code
== GTU
|| code
== GEU
591 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
592 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
594 if (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
&& code
== GE
)
596 from_compare (operands
, GT
);
597 insn
= gen_ieee_ccmpeqsf_t (sh_compare_op0
, sh_compare_op1
);
600 insn
= gen_rtx_SET (VOIDmode
,
601 gen_rtx_REG (SImode
, T_REG
),
602 gen_rtx (code
, SImode
, sh_compare_op0
,
604 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
606 insn
= gen_rtx (PARALLEL
, VOIDmode
,
608 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ())));
609 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
) (insn
);
615 /* Functions to output assembly code. */
617 /* Return a sequence of instructions to perform DI or DF move.
619 Since the SH cannot move a DI or DF in one instruction, we have
620 to take care when we see overlapping source and dest registers. */
623 output_movedouble (insn
, operands
, mode
)
624 rtx insn ATTRIBUTE_UNUSED
;
626 enum machine_mode mode
;
628 rtx dst
= operands
[0];
629 rtx src
= operands
[1];
631 if (GET_CODE (dst
) == MEM
632 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
633 return "mov.l %T1,%0\n\tmov.l %1,%0";
635 if (register_operand (dst
, mode
)
636 && register_operand (src
, mode
))
638 if (REGNO (src
) == MACH_REG
)
639 return "sts mach,%S0\n\tsts macl,%R0";
641 /* When mov.d r1,r2 do r2->r3 then r1->r2;
642 when mov.d r1,r0 do r1->r0 then r2->r1. */
644 if (REGNO (src
) + 1 == REGNO (dst
))
645 return "mov %T1,%T0\n\tmov %1,%0";
647 return "mov %1,%0\n\tmov %T1,%T0";
649 else if (GET_CODE (src
) == CONST_INT
)
651 if (INTVAL (src
) < 0)
652 output_asm_insn ("mov #-1,%S0", operands
);
654 output_asm_insn ("mov #0,%S0", operands
);
658 else if (GET_CODE (src
) == MEM
)
661 int dreg
= REGNO (dst
);
662 rtx inside
= XEXP (src
, 0);
664 if (GET_CODE (inside
) == REG
)
665 ptrreg
= REGNO (inside
);
666 else if (GET_CODE (inside
) == SUBREG
)
667 ptrreg
= REGNO (SUBREG_REG (inside
)) + SUBREG_WORD (inside
);
668 else if (GET_CODE (inside
) == PLUS
)
670 ptrreg
= REGNO (XEXP (inside
, 0));
671 /* ??? A r0+REG address shouldn't be possible here, because it isn't
672 an offsettable address. Unfortunately, offsettable addresses use
673 QImode to check the offset, and a QImode offsettable address
674 requires r0 for the other operand, which is not currently
675 supported, so we can't use the 'o' constraint.
676 Thus we must check for and handle r0+REG addresses here.
677 We punt for now, since this is likely very rare. */
678 if (GET_CODE (XEXP (inside
, 1)) == REG
)
681 else if (GET_CODE (inside
) == LABEL_REF
)
682 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
683 else if (GET_CODE (inside
) == POST_INC
)
684 return "mov.l %1,%0\n\tmov.l %1,%T0";
688 /* Work out the safe way to copy. Copy into the second half first. */
690 return "mov.l %T1,%T0\n\tmov.l %1,%0";
693 return "mov.l %1,%0\n\tmov.l %T1,%T0";
696 /* Print an instruction which would have gone into a delay slot after
697 another instruction, but couldn't because the other instruction expanded
698 into a sequence where putting the slot insn at the end wouldn't work. */
704 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
, optimize
, 0, 1);
706 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
710 output_far_jump (insn
, op
)
714 struct { rtx lab
, reg
, op
; } this;
717 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
719 this.lab
= gen_label_rtx ();
723 && offset
- get_attr_length (insn
) <= 32766)
726 jump
= "mov.w %O0,%1;braf %1";
732 jump
= "mov.l %O0,%1;braf %1";
734 jump
= "mov.l %O0,%1;jmp @%1";
736 /* If we have a scratch register available, use it. */
737 if (GET_CODE (PREV_INSN (insn
)) == INSN
738 && INSN_CODE (PREV_INSN (insn
)) == CODE_FOR_indirect_jump_scratch
)
740 this.reg
= SET_DEST (PATTERN (PREV_INSN (insn
)));
741 output_asm_insn (jump
, &this.lab
);
742 if (dbr_sequence_length ())
743 print_slot (final_sequence
);
745 output_asm_insn ("nop", 0);
749 /* Output the delay slot insn first if any. */
750 if (dbr_sequence_length ())
751 print_slot (final_sequence
);
753 this.reg
= gen_rtx_REG (SImode
, 13);
754 output_asm_insn ("mov.l r13,@-r15", 0);
755 output_asm_insn (jump
, &this.lab
);
756 output_asm_insn ("mov.l @r15+,r13", 0);
759 output_asm_insn (".align 2", 0);
760 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (this.lab
));
763 output_asm_insn (".long %O2-%O0", &this.lab
);
765 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this.lab
);
769 /* Local label counter, used for constants in the pool and inside
774 /* Output code for ordinary branches. */
777 output_branch (logic
, insn
, operands
)
782 switch (get_attr_length (insn
))
785 /* This can happen if filling the delay slot has caused a forward
786 branch to exceed its range (we could reverse it, but only
787 when we know we won't overextend other branches; this should
788 best be handled by relaxation).
789 It can also happen when other condbranches hoist delay slot insn
790 from their destination, thus leading to code size increase.
791 But the branch will still be in the range -4092..+4098 bytes. */
796 /* The call to print_slot will clobber the operands. */
797 rtx op0
= operands
[0];
799 /* If the instruction in the delay slot is annulled (true), then
800 there is no delay slot where we can put it now. The only safe
801 place for it is after the label. final will do that by default. */
804 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
806 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
807 ASSEMBLER_DIALECT
? "/" : ".", label
);
808 print_slot (final_sequence
);
811 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
813 output_asm_insn ("bra\t%l0", &op0
);
814 fprintf (asm_out_file
, "\tnop\n");
815 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file
, "LF", label
);
819 /* When relaxing, handle this like a short branch. The linker
820 will fix it up if it still doesn't fit after relaxation. */
822 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
829 output_branchy_insn (code
, template, insn
, operands
)
831 const char *template;
835 rtx next_insn
= NEXT_INSN (insn
);
837 if (next_insn
&& GET_CODE (next_insn
) == JUMP_INSN
&& condjump_p (next_insn
))
839 rtx src
= SET_SRC (PATTERN (next_insn
));
840 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
842 /* Following branch not taken */
843 operands
[9] = gen_label_rtx ();
844 emit_label_after (operands
[9], next_insn
);
845 INSN_ADDRESSES_NEW (operands
[9],
846 INSN_ADDRESSES (INSN_UID (next_insn
))
847 + get_attr_length (next_insn
));
852 int offset
= (branch_dest (next_insn
)
853 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
854 if (offset
>= -252 && offset
<= 258)
856 if (GET_CODE (src
) == IF_THEN_ELSE
)
864 operands
[9] = gen_label_rtx ();
865 emit_label_after (operands
[9], insn
);
866 INSN_ADDRESSES_NEW (operands
[9],
867 INSN_ADDRESSES (INSN_UID (insn
))
868 + get_attr_length (insn
));
873 output_ieee_ccmpeq (insn
, operands
)
876 return output_branchy_insn (NE
, "bt\t%l9\\;fcmp/eq\t%1,%0", insn
, operands
);
879 /* Output to FILE the start of the assembler file. */
882 output_file_start (file
)
885 output_file_directive (file
, main_input_filename
);
887 /* Switch to the data section so that the coffsem symbol and the
888 gcc2_compiled. symbol aren't in the text section. */
891 if (TARGET_LITTLE_ENDIAN
)
892 fprintf (file
, "\t.little\n");
895 /* Actual number of instructions used to make a shift by N. */
896 static char ashiftrt_insns
[] =
897 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
899 /* Left shift and logical right shift are the same. */
900 static char shift_insns
[] =
901 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
903 /* Individual shift amounts needed to get the above length sequences.
904 One bit right shifts clobber the T bit, so when possible, put one bit
905 shifts in the middle of the sequence, so the ends are eligible for
906 branch delay slots. */
907 static short shift_amounts
[32][5] = {
908 {0}, {1}, {2}, {2, 1},
909 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
910 {8}, {8, 1}, {8, 2}, {8, 1, 2},
911 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
912 {16}, {16, 1}, {16, 2}, {16, 1, 2},
913 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
914 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
915 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
917 /* Likewise, but for shift amounts < 16, up to three highmost bits
918 might be clobbered. This is typically used when combined with some
919 kind of sign or zero extension. */
921 static char ext_shift_insns
[] =
922 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
924 static short ext_shift_amounts
[32][4] = {
925 {0}, {1}, {2}, {2, 1},
926 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
927 {8}, {8, 1}, {8, 2}, {8, 1, 2},
928 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
929 {16}, {16, 1}, {16, 2}, {16, 1, 2},
930 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
931 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
932 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
934 /* Assuming we have a value that has been sign-extended by at least one bit,
935 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
936 to shift it by N without data loss, and quicker than by other means? */
937 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
939 /* This is used in length attributes in sh.md to help compute the length
940 of arbitrary constant shift instructions. */
943 shift_insns_rtx (insn
)
946 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
947 int shift_count
= INTVAL (XEXP (set_src
, 1));
948 enum rtx_code shift_code
= GET_CODE (set_src
);
953 return ashiftrt_insns
[shift_count
];
956 return shift_insns
[shift_count
];
962 /* Return the cost of a shift. */
970 /* If shift by a non constant, then this will be expensive. */
971 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
972 return SH_DYNAMIC_SHIFT_COST
;
974 value
= INTVAL (XEXP (x
, 1));
976 /* Otherwise, return the true cost in instructions. */
977 if (GET_CODE (x
) == ASHIFTRT
)
979 int cost
= ashiftrt_insns
[value
];
980 /* If SH3, then we put the constant in a reg and use shad. */
981 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
982 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
986 return shift_insns
[value
];
989 /* Return the cost of an AND operation. */
997 /* Anding with a register is a single cycle and instruction. */
998 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1001 i
= INTVAL (XEXP (x
, 1));
1002 /* These constants are single cycle extu.[bw] instructions. */
1003 if (i
== 0xff || i
== 0xffff)
1005 /* Constants that can be used in an and immediate instruction is a single
1006 cycle, but this requires r0, so make it a little more expensive. */
1007 if (CONST_OK_FOR_L (i
))
1009 /* Constants that can be loaded with a mov immediate and an and.
1010 This case is probably unnecessary. */
1011 if (CONST_OK_FOR_I (i
))
1013 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1014 This case is probably unnecessary. */
1018 /* Return the cost of an addition or a subtraction. */
1024 /* Adding a register is a single cycle insn. */
1025 if (GET_CODE (XEXP (x
, 1)) == REG
1026 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1029 /* Likewise for small constants. */
1030 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1031 && CONST_OK_FOR_I (INTVAL (XEXP (x
, 1))))
1034 /* Any other constant requires a 2 cycle pc-relative load plus an
1039 /* Return the cost of a multiply. */
1042 rtx x ATTRIBUTE_UNUSED
;
1046 /* We have a mul insn, so we can never take more than the mul and the
1047 read of the mac reg, but count more because of the latency and extra
1049 if (TARGET_SMALLCODE
)
1054 /* If we're aiming at small code, then just count the number of
1055 insns in a multiply call sequence. */
1056 if (TARGET_SMALLCODE
)
1059 /* Otherwise count all the insns in the routine we'd be calling too. */
1063 /* Code to expand a shift. */
1066 gen_ashift (type
, n
, reg
)
1071 /* Negative values here come from the shift_amounts array. */
1084 emit_insn (gen_ashrsi3_k (reg
, reg
, GEN_INT (n
)));
1088 emit_insn (gen_lshrsi3_m (reg
, reg
, GEN_INT (n
)));
1090 emit_insn (gen_lshrsi3_k (reg
, reg
, GEN_INT (n
)));
1093 emit_insn (gen_ashlsi3_std (reg
, reg
, GEN_INT (n
)));
1098 /* Same for HImode */
1101 gen_ashift_hi (type
, n
, reg
)
1106 /* Negative values here come from the shift_amounts array. */
1120 /* We don't have HImode right shift operations because using the
1121 ordinary 32 bit shift instructions for that doesn't generate proper
1122 zero/sign extension.
1123 gen_ashift_hi is only called in contexts where we know that the
1124 sign extension works out correctly. */
1127 if (GET_CODE (reg
) == SUBREG
)
1129 word
= SUBREG_WORD (reg
);
1130 reg
= SUBREG_REG (reg
);
1132 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, word
));
1136 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
1141 /* Output RTL to split a constant shift into its component SH constant
1142 shift instructions. */
1145 gen_shifty_op (code
, operands
)
1149 int value
= INTVAL (operands
[2]);
1152 /* Truncate the shift count in case it is out of bounds. */
1153 value
= value
& 0x1f;
1157 if (code
== LSHIFTRT
)
1159 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
1160 emit_insn (gen_movt (operands
[0]));
1163 else if (code
== ASHIFT
)
1165 /* There is a two instruction sequence for 31 bit left shifts,
1166 but it requires r0. */
1167 if (GET_CODE (operands
[0]) == REG
&& REGNO (operands
[0]) == 0)
1169 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
1170 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
1175 else if (value
== 0)
1177 /* This can happen when not optimizing. We must output something here
1178 to prevent the compiler from aborting in final.c after the try_split
1180 emit_insn (gen_nop ());
1184 max
= shift_insns
[value
];
1185 for (i
= 0; i
< max
; i
++)
1186 gen_ashift (code
, shift_amounts
[value
][i
], operands
[0]);
1189 /* Same as above, but optimized for values where the topmost bits don't
1193 gen_shifty_hi_op (code
, operands
)
1197 int value
= INTVAL (operands
[2]);
1199 void (*gen_fun
) PARAMS ((int, int, rtx
));
1201 /* This operation is used by and_shl for SImode values with a few
1202 high bits known to be cleared. */
1206 emit_insn (gen_nop ());
1210 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
1213 max
= ext_shift_insns
[value
];
1214 for (i
= 0; i
< max
; i
++)
1215 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1218 /* When shifting right, emit the shifts in reverse order, so that
1219 solitary negative values come first. */
1220 for (i
= ext_shift_insns
[value
] - 1; i
>= 0; i
--)
1221 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1224 /* Output RTL for an arithmetic right shift. */
1226 /* ??? Rewrite to use super-optimizer sequences. */
1229 expand_ashiftrt (operands
)
1240 if (GET_CODE (operands
[2]) != CONST_INT
)
1242 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
1243 emit_insn (gen_negsi2 (count
, count
));
1244 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1247 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
1248 > 1 + SH_DYNAMIC_SHIFT_COST
)
1251 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
1252 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1256 if (GET_CODE (operands
[2]) != CONST_INT
)
1259 value
= INTVAL (operands
[2]) & 31;
1263 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
1266 else if (value
>= 16 && value
<= 19)
1268 wrk
= gen_reg_rtx (SImode
);
1269 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
1272 gen_ashift (ASHIFTRT
, 1, wrk
);
1273 emit_move_insn (operands
[0], wrk
);
1276 /* Expand a short sequence inline, longer call a magic routine. */
1277 else if (value
<= 5)
1279 wrk
= gen_reg_rtx (SImode
);
1280 emit_move_insn (wrk
, operands
[1]);
1282 gen_ashift (ASHIFTRT
, 1, wrk
);
1283 emit_move_insn (operands
[0], wrk
);
1287 wrk
= gen_reg_rtx (Pmode
);
1289 /* Load the value into an arg reg and call a helper. */
1290 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
1291 sprintf (func
, "__ashiftrt_r4_%d", value
);
1292 func_name
= get_identifier (func
);
1293 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (func_name
));
1294 emit_move_insn (wrk
, sym
);
1295 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
1296 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
1301 sh_dynamicalize_shift_p (count
)
1304 return shift_insns
[INTVAL (count
)] > 1 + SH_DYNAMIC_SHIFT_COST
;
1307 /* Try to find a good way to implement the combiner pattern
1308 [(set (match_operand:SI 0 "register_operand" "r")
1309 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1310 (match_operand:SI 2 "const_int_operand" "n"))
1311 (match_operand:SI 3 "const_int_operand" "n"))) .
1312 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1313 return 0 for simple right / left or left/right shift combination.
1314 return 1 for a combination of shifts with zero_extend.
1315 return 2 for a combination of shifts with an AND that needs r0.
1316 return 3 for a combination of shifts with an AND that needs an extra
1317 scratch register, when the three highmost bits of the AND mask are clear.
1318 return 4 for a combination of shifts with an AND that needs an extra
1319 scratch register, when any of the three highmost bits of the AND mask
1321 If ATTRP is set, store an initial right shift width in ATTRP[0],
1322 and the instruction length in ATTRP[1] . These values are not valid
1324 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1325 shift_amounts for the last shift value that is to be used before the
1328 shl_and_kind (left_rtx
, mask_rtx
, attrp
)
1329 rtx left_rtx
, mask_rtx
;
1332 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
1333 int left
= INTVAL (left_rtx
), right
;
1335 int cost
, best_cost
= 10000;
1336 int best_right
= 0, best_len
= 0;
1340 if (left
< 0 || left
> 31)
1342 if (GET_CODE (mask_rtx
) == CONST_INT
)
1343 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
1345 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
1346 /* Can this be expressed as a right shift / left shift pair ? */
1347 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
1348 right
= exact_log2 (lsb
);
1349 mask2
= ~(mask
+ lsb
- 1);
1350 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
1351 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1353 best_cost
= shift_insns
[right
] + shift_insns
[right
+ left
];
1354 /* mask has no trailing zeroes <==> ! right */
1355 else if (! right
&& mask2
== ~(lsb2
- 1))
1357 int late_right
= exact_log2 (lsb2
);
1358 best_cost
= shift_insns
[left
+ late_right
] + shift_insns
[late_right
];
1360 /* Try to use zero extend */
1361 if (mask2
== ~(lsb2
- 1))
1365 for (width
= 8; width
<= 16; width
+= 8)
1367 /* Can we zero-extend right away? */
1368 if (lsb2
== (unsigned HOST_WIDE_INT
)1 << width
)
1371 = 1 + ext_shift_insns
[right
] + ext_shift_insns
[left
+ right
];
1372 if (cost
< best_cost
)
1383 /* ??? Could try to put zero extend into initial right shift,
1384 or even shift a bit left before the right shift. */
1385 /* Determine value of first part of left shift, to get to the
1386 zero extend cut-off point. */
1387 first
= width
- exact_log2 (lsb2
) + right
;
1388 if (first
>= 0 && right
+ left
- first
>= 0)
1390 cost
= ext_shift_insns
[right
] + ext_shift_insns
[first
] + 1
1391 + ext_shift_insns
[right
+ left
- first
];
1392 if (cost
< best_cost
)
1404 /* Try to use r0 AND pattern */
1405 for (i
= 0; i
<= 2; i
++)
1409 if (! CONST_OK_FOR_L (mask
>> i
))
1411 cost
= (i
!= 0) + 2 + ext_shift_insns
[left
+ i
];
1412 if (cost
< best_cost
)
1417 best_len
= cost
- 1;
1420 /* Try to use a scratch register to hold the AND operand. */
1421 can_ext
= ((mask
<< left
) & 0xe0000000) == 0;
1422 for (i
= 0; i
<= 2; i
++)
1426 cost
= (i
!= 0) + (CONST_OK_FOR_I (mask
>> i
) ? 2 : 3)
1427 + (can_ext
? ext_shift_insns
: shift_insns
)[left
+ i
];
1428 if (cost
< best_cost
)
1433 best_len
= cost
- 1 - ! CONST_OK_FOR_I (mask
>> i
);
1439 attrp
[0] = best_right
;
1440 attrp
[1] = best_len
;
1445 /* This is used in length attributes of the unnamed instructions
1446 corresponding to shl_and_kind return values of 1 and 2. */
1448 shl_and_length (insn
)
1451 rtx set_src
, left_rtx
, mask_rtx
;
1454 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1455 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
1456 mask_rtx
= XEXP (set_src
, 1);
1457 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1458 return attributes
[1];
1461 /* This is used in length attribute of the and_shl_scratch instruction. */
1464 shl_and_scr_length (insn
)
1467 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1468 int len
= shift_insns
[INTVAL (XEXP (set_src
, 1))];
1469 rtx op
= XEXP (set_src
, 0);
1470 len
+= shift_insns
[INTVAL (XEXP (op
, 1))] + 1;
1471 op
= XEXP (XEXP (op
, 0), 0);
1472 return len
+ shift_insns
[INTVAL (XEXP (op
, 1))];
1475 /* Generating rtl? */
1476 extern int rtx_equal_function_value_matters
;
1478 /* Generate rtl for instructions for which shl_and_kind advised a particular
1479 method of generating them, i.e. returned zero. */
1482 gen_shl_and (dest
, left_rtx
, mask_rtx
, source
)
1483 rtx dest
, left_rtx
, mask_rtx
, source
;
1486 unsigned HOST_WIDE_INT mask
;
1487 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1488 int right
, total_shift
;
1489 void (*shift_gen_fun
) PARAMS ((int, rtx
*)) = gen_shifty_hi_op
;
1491 right
= attributes
[0];
1492 total_shift
= INTVAL (left_rtx
) + right
;
1493 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
1500 int first
= attributes
[2];
1505 emit_insn ((mask
<< right
) <= 0xff
1506 ? gen_zero_extendqisi2(dest
,
1507 gen_lowpart (QImode
, source
))
1508 : gen_zero_extendhisi2(dest
,
1509 gen_lowpart (HImode
, source
)));
1513 emit_insn (gen_movsi (dest
, source
));
1517 operands
[2] = GEN_INT (right
);
1518 gen_shifty_hi_op (LSHIFTRT
, operands
);
1522 operands
[2] = GEN_INT (first
);
1523 gen_shifty_hi_op (ASHIFT
, operands
);
1524 total_shift
-= first
;
1528 emit_insn (mask
<= 0xff
1529 ? gen_zero_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
1530 : gen_zero_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
1531 if (total_shift
> 0)
1533 operands
[2] = GEN_INT (total_shift
);
1534 gen_shifty_hi_op (ASHIFT
, operands
);
1539 shift_gen_fun
= gen_shifty_op
;
1541 /* If the topmost bit that matters is set, set the topmost bits
1542 that don't matter. This way, we might be able to get a shorter
1544 if (mask
& ((HOST_WIDE_INT
)1 << (31 - total_shift
)))
1545 mask
|= (HOST_WIDE_INT
)~0 << (31 - total_shift
);
1547 /* Don't expand fine-grained when combining, because that will
1548 make the pattern fail. */
1549 if (rtx_equal_function_value_matters
1550 || reload_in_progress
|| reload_completed
)
1554 /* Cases 3 and 4 should be handled by this split
1555 only while combining */
1560 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
1563 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
1568 operands
[2] = GEN_INT (total_shift
);
1569 shift_gen_fun (ASHIFT
, operands
);
1576 if (kind
!= 4 && total_shift
< 16)
1578 neg
= -ext_shift_amounts
[total_shift
][1];
1580 neg
-= ext_shift_amounts
[total_shift
][2];
1584 emit_insn (gen_and_shl_scratch (dest
, source
,
1587 GEN_INT (total_shift
+ neg
),
1589 emit_insn (gen_movsi (dest
, dest
));
1596 /* Try to find a good way to implement the combiner pattern
1597 [(set (match_operand:SI 0 "register_operand" "=r")
1598 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1599 (match_operand:SI 2 "const_int_operand" "n")
1600 (match_operand:SI 3 "const_int_operand" "n")
1602 (clobber (reg:SI T_REG))]
1603 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1604 return 0 for simple left / right shift combination.
1605 return 1 for left shift / 8 bit sign extend / left shift.
1606 return 2 for left shift / 16 bit sign extend / left shift.
1607 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1608 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1609 return 5 for left shift / 16 bit sign extend / right shift
1610 return 6 for < 8 bit sign extend / left shift.
1611 return 7 for < 8 bit sign extend / left shift / single right shift.
1612 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1615 shl_sext_kind (left_rtx
, size_rtx
, costp
)
1616 rtx left_rtx
, size_rtx
;
1619 int left
, size
, insize
, ext
;
1620 int cost
, best_cost
;
1623 left
= INTVAL (left_rtx
);
1624 size
= INTVAL (size_rtx
);
1625 insize
= size
- left
;
1628 /* Default to left / right shift. */
1630 best_cost
= shift_insns
[32 - insize
] + ashiftrt_insns
[32 - size
];
1633 /* 16 bit shift / sign extend / 16 bit shift */
1634 cost
= shift_insns
[16 - insize
] + 1 + ashiftrt_insns
[16 - size
];
1635 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1636 below, by alternative 3 or something even better. */
1637 if (cost
< best_cost
)
1643 /* Try a plain sign extend between two shifts. */
1644 for (ext
= 16; ext
>= insize
; ext
-= 8)
1648 cost
= ext_shift_insns
[ext
- insize
] + 1 + shift_insns
[size
- ext
];
1649 if (cost
< best_cost
)
1655 /* Check if we can do a sloppy shift with a final signed shift
1656 restoring the sign. */
1657 if (EXT_SHIFT_SIGNED (size
- ext
))
1658 cost
= ext_shift_insns
[ext
- insize
] + ext_shift_insns
[size
- ext
] + 1;
1659 /* If not, maybe it's still cheaper to do the second shift sloppy,
1660 and do a final sign extend? */
1661 else if (size
<= 16)
1662 cost
= ext_shift_insns
[ext
- insize
] + 1
1663 + ext_shift_insns
[size
> ext
? size
- ext
: ext
- size
] + 1;
1666 if (cost
< best_cost
)
1668 kind
= ext
/ 8U + 2;
1672 /* Check if we can sign extend in r0 */
1675 cost
= 3 + shift_insns
[left
];
1676 if (cost
< best_cost
)
1681 /* Try the same with a final signed shift. */
1684 cost
= 3 + ext_shift_insns
[left
+ 1] + 1;
1685 if (cost
< best_cost
)
1694 /* Try to use a dynamic shift. */
1695 cost
= shift_insns
[32 - insize
] + 1 + SH_DYNAMIC_SHIFT_COST
;
1696 if (cost
< best_cost
)
1707 /* Function to be used in the length attribute of the instructions
1708 implementing this pattern. */
1711 shl_sext_length (insn
)
1714 rtx set_src
, left_rtx
, size_rtx
;
1717 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1718 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
1719 size_rtx
= XEXP (set_src
, 1);
1720 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
1724 /* Generate rtl for this pattern */
1727 gen_shl_sext (dest
, left_rtx
, size_rtx
, source
)
1728 rtx dest
, left_rtx
, size_rtx
, source
;
1731 int left
, size
, insize
, cost
;
1734 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
1735 left
= INTVAL (left_rtx
);
1736 size
= INTVAL (size_rtx
);
1737 insize
= size
- left
;
1745 int ext
= kind
& 1 ? 8 : 16;
1746 int shift2
= size
- ext
;
1748 /* Don't expand fine-grained when combining, because that will
1749 make the pattern fail. */
1750 if (! rtx_equal_function_value_matters
1751 && ! reload_in_progress
&& ! reload_completed
)
1753 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
1754 emit_insn (gen_movsi (dest
, source
));
1758 emit_insn (gen_movsi (dest
, source
));
1762 operands
[2] = GEN_INT (ext
- insize
);
1763 gen_shifty_hi_op (ASHIFT
, operands
);
1766 ? gen_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
1767 : gen_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
1772 operands
[2] = GEN_INT (shift2
);
1773 gen_shifty_op (ASHIFT
, operands
);
1780 if (EXT_SHIFT_SIGNED (shift2
))
1782 operands
[2] = GEN_INT (shift2
+ 1);
1783 gen_shifty_op (ASHIFT
, operands
);
1784 operands
[2] = GEN_INT (1);
1785 gen_shifty_op (ASHIFTRT
, operands
);
1788 operands
[2] = GEN_INT (shift2
);
1789 gen_shifty_hi_op (ASHIFT
, operands
);
1793 operands
[2] = GEN_INT (-shift2
);
1794 gen_shifty_hi_op (LSHIFTRT
, operands
);
1796 emit_insn (size
<= 8
1797 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
1798 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
1805 if (! rtx_equal_function_value_matters
1806 && ! reload_in_progress
&& ! reload_completed
)
1807 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
1811 operands
[2] = GEN_INT (16 - insize
);
1812 gen_shifty_hi_op (ASHIFT
, operands
);
1813 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
1815 /* Don't use gen_ashrsi3 because it generates new pseudos. */
1817 gen_ashift (ASHIFTRT
, 1, dest
);
1822 /* Don't expand fine-grained when combining, because that will
1823 make the pattern fail. */
1824 if (! rtx_equal_function_value_matters
1825 && ! reload_in_progress
&& ! reload_completed
)
1827 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
1828 emit_insn (gen_movsi (dest
, source
));
1831 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
1832 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
1833 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
1835 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
1836 gen_shifty_op (ASHIFT
, operands
);
1838 emit_insn (gen_ashrsi3_k (dest
, dest
, GEN_INT (1)));
1846 /* The SH cannot load a large constant into a register, constants have to
1847 come from a pc relative load. The reference of a pc relative load
1848 instruction must be less than 1k infront of the instruction. This
1849 means that we often have to dump a constant inside a function, and
1850 generate code to branch around it.
1852 It is important to minimize this, since the branches will slow things
1853 down and make things bigger.
1855 Worst case code looks like:
1873 We fix this by performing a scan before scheduling, which notices which
1874 instructions need to have their operands fetched from the constant table
1875 and builds the table.
1879 scan, find an instruction which needs a pcrel move. Look forward, find the
1880 last barrier which is within MAX_COUNT bytes of the requirement.
1881 If there isn't one, make one. Process all the instructions between
1882 the find and the barrier.
1884 In the above example, we can tell that L3 is within 1k of L1, so
1885 the first move can be shrunk from the 3 insn+constant sequence into
1886 just 1 insn, and the constant moved to L3 to make:
1897 Then the second move becomes the target for the shortening process. */
1901 rtx value
; /* Value in table. */
1902 rtx label
; /* Label of value. */
1903 enum machine_mode mode
; /* Mode of value. */
1906 /* The maximum number of constants that can fit into one pool, since
1907 the pc relative range is 0...1020 bytes and constants are at least 4
1910 #define MAX_POOL_SIZE (1020/4)
1911 static pool_node pool_vector
[MAX_POOL_SIZE
];
1912 static int pool_size
;
1914 /* ??? If we need a constant in HImode which is the truncated value of a
1915 constant we need in SImode, we could combine the two entries thus saving
1916 two bytes. Is this common enough to be worth the effort of implementing
1919 /* ??? This stuff should be done at the same time that we shorten branches.
1920 As it is now, we must assume that all branches are the maximum size, and
1921 this causes us to almost always output constant pools sooner than
1924 /* Add a constant to the pool and return its label. */
1927 add_constant (x
, mode
, last_value
)
1929 enum machine_mode mode
;
1935 /* First see if we've already got it. */
1936 for (i
= 0; i
< pool_size
; i
++)
1938 if (x
->code
== pool_vector
[i
].value
->code
1939 && mode
== pool_vector
[i
].mode
)
1941 if (x
->code
== CODE_LABEL
)
1943 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
1946 if (rtx_equal_p (x
, pool_vector
[i
].value
))
1951 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
1953 lab
= pool_vector
[i
].label
;
1955 pool_vector
[i
].label
= lab
= gen_label_rtx ();
1962 /* Need a new one. */
1963 pool_vector
[pool_size
].value
= x
;
1964 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
1967 lab
= gen_label_rtx ();
1968 pool_vector
[pool_size
].mode
= mode
;
1969 pool_vector
[pool_size
].label
= lab
;
1974 /* Output the literal table. */
1983 /* Do two passes, first time dump out the HI sized constants. */
1985 for (i
= 0; i
< pool_size
; i
++)
1987 pool_node
*p
= &pool_vector
[i
];
1989 if (p
->mode
== HImode
)
1993 scan
= emit_insn_after (gen_align_2 (), scan
);
1996 scan
= emit_label_after (p
->label
, scan
);
1997 scan
= emit_insn_after (gen_consttable_2 (p
->value
), scan
);
2003 for (i
= 0; i
< pool_size
; i
++)
2005 pool_node
*p
= &pool_vector
[i
];
2016 scan
= emit_label_after (gen_label_rtx (), scan
);
2017 scan
= emit_insn_after (gen_align_4 (), scan
);
2020 scan
= emit_label_after (p
->label
, scan
);
2021 scan
= emit_insn_after (gen_consttable_4 (p
->value
), scan
);
2028 scan
= emit_label_after (gen_label_rtx (), scan
);
2029 scan
= emit_insn_after (gen_align_4 (), scan
);
2032 scan
= emit_label_after (p
->label
, scan
);
2033 scan
= emit_insn_after (gen_consttable_8 (p
->value
), scan
);
2041 scan
= emit_insn_after (gen_consttable_end (), scan
);
2042 scan
= emit_barrier_after (scan
);
2046 /* Return non-zero if constant would be an ok source for a
2047 mov.w instead of a mov.l. */
2053 return (GET_CODE (src
) == CONST_INT
2054 && INTVAL (src
) >= -32768
2055 && INTVAL (src
) <= 32767);
2058 /* Non-zero if the insn is a move instruction which needs to be fixed. */
2060 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2061 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2062 need to fix it if the input value is CONST_OK_FOR_I. */
2068 if (GET_CODE (insn
) == INSN
)
2070 rtx pat
= PATTERN (insn
);
2071 if (GET_CODE (pat
) == PARALLEL
)
2072 pat
= XVECEXP (pat
, 0, 0);
2073 if (GET_CODE (pat
) == SET
2074 /* We can load any 8 bit value if we don't care what the high
2075 order bits end up as. */
2076 && GET_MODE (SET_DEST (pat
)) != QImode
2077 && (CONSTANT_P (SET_SRC (pat
))
2078 /* Match mova_const. */
2079 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
2080 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
2081 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
2083 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
2084 && (fp_zero_operand (SET_SRC (pat
))
2085 || fp_one_operand (SET_SRC (pat
)))
2086 /* ??? If this is a -m4 or -m4-single compilation, we don't
2087 know the current setting of fpscr, so disable fldi. */
2088 && (! TARGET_SH4
|| TARGET_FMOVD
)
2089 && GET_CODE (SET_DEST (pat
)) == REG
2090 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
2091 && (GET_CODE (SET_SRC (pat
)) != CONST_INT
2092 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat
)))))
2103 return (GET_CODE (insn
) == INSN
2104 && GET_CODE (PATTERN (insn
)) == SET
2105 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
2106 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
2107 /* Don't match mova_const. */
2108 && XVECEXP (SET_SRC (PATTERN (insn
)), 0, 0) == LABEL_REF
);
2111 /* Find the last barrier from insn FROM which is close enough to hold the
2112 constant pool. If we can't find one, then create one near the end of
2116 find_barrier (num_mova
, mova
, from
)
2126 int leading_mova
= num_mova
;
2127 rtx barrier_before_mova
, found_barrier
= 0, good_barrier
= 0;
2131 /* For HImode: range is 510, add 4 because pc counts from address of
2132 second instruction after this one, subtract 2 for the jump instruction
2133 that we may need to emit before the table, subtract 2 for the instruction
2134 that fills the jump delay slot (in very rare cases, reorg will take an
2135 instruction from after the constant pool or will leave the delay slot
2136 empty). This gives 510.
2137 For SImode: range is 1020, add 4 because pc counts from address of
2138 second instruction after this one, subtract 2 in case pc is 2 byte
2139 aligned, subtract 2 for the jump instruction that we may need to emit
2140 before the table, subtract 2 for the instruction that fills the jump
2141 delay slot. This gives 1018. */
2143 /* The branch will always be shortened now that the reference address for
2144 forward branches is the successor address, thus we need no longer make
2145 adjustments to the [sh]i_limit for -O0. */
2150 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
2152 int inc
= get_attr_length (from
);
2155 if (GET_CODE (from
) == CODE_LABEL
)
2158 new_align
= 1 << label_to_alignment (from
);
2159 else if (GET_CODE (prev_nonnote_insn (from
)) == BARRIER
)
2160 new_align
= 1 << barrier_align (from
);
2166 if (GET_CODE (from
) == BARRIER
)
2169 found_barrier
= from
;
2171 /* If we are at the end of the function, or in front of an alignment
2172 instruction, we need not insert an extra alignment. We prefer
2173 this kind of barrier. */
2174 if (barrier_align (from
) > 2)
2175 good_barrier
= from
;
2178 if (broken_move (from
))
2181 enum machine_mode mode
;
2183 pat
= PATTERN (from
);
2184 if (GET_CODE (pat
) == PARALLEL
)
2185 pat
= XVECEXP (pat
, 0, 0);
2186 src
= SET_SRC (pat
);
2187 dst
= SET_DEST (pat
);
2188 mode
= GET_MODE (dst
);
2190 /* We must explicitly check the mode, because sometimes the
2191 front end will generate code to load unsigned constants into
2192 HImode targets without properly sign extending them. */
2194 || (mode
== SImode
&& hi_const (src
) && REGNO (dst
) != FPUL_REG
))
2197 /* We put the short constants before the long constants, so
2198 we must count the length of short constants in the range
2199 for the long constants. */
2200 /* ??? This isn't optimal, but is easy to do. */
2205 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
2207 if (found_si
> count_si
)
2208 count_si
= found_si
;
2209 found_si
+= GET_MODE_SIZE (mode
);
2211 si_limit
-= GET_MODE_SIZE (mode
);
2214 /* See the code in machine_dependent_reorg, which has a similar if
2215 statement that generates a new mova insn in many cases. */
2216 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
2226 barrier_before_mova
= good_barrier
? good_barrier
: found_barrier
;
2228 if (found_si
> count_si
)
2229 count_si
= found_si
;
2231 else if (GET_CODE (from
) == JUMP_INSN
2232 && (GET_CODE (PATTERN (from
)) == ADDR_VEC
2233 || GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
))
2237 if (barrier_align (next_real_insn (from
)) == CACHE_LOG
)
2239 /* We have just passed the barrier in front of the
2240 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2241 the ADDR_DIFF_VEC is accessed as data, just like our pool
2242 constants, this is a good opportunity to accommodate what
2243 we have gathered so far.
2244 If we waited any longer, we could end up at a barrier in
2245 front of code, which gives worse cache usage for separated
2246 instruction / data caches. */
2247 good_barrier
= found_barrier
;
2252 rtx body
= PATTERN (from
);
2253 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
2256 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2257 else if (GET_CODE (from
) == JUMP_INSN
2259 && ! TARGET_SMALLCODE
)
2265 if (new_align
> si_align
)
2267 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
2268 si_align
= new_align
;
2270 count_si
= (count_si
+ new_align
- 1) & -new_align
;
2275 if (new_align
> hi_align
)
2277 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
2278 hi_align
= new_align
;
2280 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
2282 from
= NEXT_INSN (from
);
2289 /* Try as we might, the leading mova is out of range. Change
2290 it into a load (which will become a pcload) and retry. */
2291 SET_SRC (PATTERN (mova
)) = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
2292 INSN_CODE (mova
) = -1;
2293 return find_barrier (0, 0, mova
);
2297 /* Insert the constant pool table before the mova instruction,
2298 to prevent the mova label reference from going out of range. */
2300 good_barrier
= found_barrier
= barrier_before_mova
;
2306 if (good_barrier
&& next_real_insn (found_barrier
))
2307 found_barrier
= good_barrier
;
2311 /* We didn't find a barrier in time to dump our stuff,
2312 so we'll make one. */
2313 rtx label
= gen_label_rtx ();
2315 /* If we exceeded the range, then we must back up over the last
2316 instruction we looked at. Otherwise, we just need to undo the
2317 NEXT_INSN at the end of the loop. */
2318 if (count_hi
> hi_limit
|| count_si
> si_limit
)
2319 from
= PREV_INSN (PREV_INSN (from
));
2321 from
= PREV_INSN (from
);
2323 /* Walk back to be just before any jump or label.
2324 Putting it before a label reduces the number of times the branch
2325 around the constant pool table will be hit. Putting it before
2326 a jump makes it more likely that the bra delay slot will be
2328 while (GET_CODE (from
) == JUMP_INSN
|| GET_CODE (from
) == NOTE
2329 || GET_CODE (from
) == CODE_LABEL
)
2330 from
= PREV_INSN (from
);
2332 from
= emit_jump_insn_after (gen_jump (label
), from
);
2333 JUMP_LABEL (from
) = label
;
2334 LABEL_NUSES (label
) = 1;
2335 found_barrier
= emit_barrier_after (from
);
2336 emit_label_after (label
, found_barrier
);
2339 return found_barrier
;
2342 /* If the instruction INSN is implemented by a special function, and we can
2343 positively find the register that is used to call the sfunc, and this
2344 register is not used anywhere else in this instruction - except as the
2345 destination of a set, return this register; else, return 0. */
2347 sfunc_uses_reg (insn
)
2351 rtx pattern
, part
, reg_part
, reg
;
2353 if (GET_CODE (insn
) != INSN
)
2355 pattern
= PATTERN (insn
);
2356 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
2359 for (reg_part
= 0, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2361 part
= XVECEXP (pattern
, 0, i
);
2362 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
2367 reg
= XEXP (reg_part
, 0);
2368 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2370 part
= XVECEXP (pattern
, 0, i
);
2371 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
2373 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
2374 && GET_CODE (SET_DEST (part
)) == REG
)
2375 ? SET_SRC (part
) : part
)))
2381 /* See if the only way in which INSN uses REG is by calling it, or by
2382 setting it while calling it. Set *SET to a SET rtx if the register
2386 noncall_uses_reg (reg
, insn
, set
)
2395 reg2
= sfunc_uses_reg (insn
);
2396 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
2398 pattern
= single_set (insn
);
2400 && GET_CODE (SET_DEST (pattern
)) == REG
2401 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2405 if (GET_CODE (insn
) != CALL_INSN
)
2407 /* We don't use rtx_equal_p because we don't care if the mode is
2409 pattern
= single_set (insn
);
2411 && GET_CODE (SET_DEST (pattern
)) == REG
2412 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2418 par
= PATTERN (insn
);
2419 if (GET_CODE (par
) == PARALLEL
)
2420 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
2422 part
= XVECEXP (par
, 0, i
);
2423 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
2426 return reg_mentioned_p (reg
, SET_SRC (pattern
));
2432 pattern
= PATTERN (insn
);
2434 if (GET_CODE (pattern
) == PARALLEL
)
2438 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2439 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
2441 pattern
= XVECEXP (pattern
, 0, 0);
2444 if (GET_CODE (pattern
) == SET
)
2446 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
2448 /* We don't use rtx_equal_p, because we don't care if the
2449 mode is different. */
2450 if (GET_CODE (SET_DEST (pattern
)) != REG
2451 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
2457 pattern
= SET_SRC (pattern
);
2460 if (GET_CODE (pattern
) != CALL
2461 || GET_CODE (XEXP (pattern
, 0)) != MEM
2462 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
2468 /* Given a X, a pattern of an insn or a part of it, return a mask of used
2469 general registers. Bits 0..15 mean that the respective registers
2470 are used as inputs in the instruction. Bits 16..31 mean that the
2471 registers 0..15, respectively, are used as outputs, or are clobbered.
2472 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
2474 regs_used (x
, is_dest
)
2483 code
= GET_CODE (x
);
2488 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2489 << (REGNO (x
) + is_dest
));
2493 rtx y
= SUBREG_REG (x
);
2495 if (GET_CODE (y
) != REG
)
2498 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2499 << (REGNO (y
) + SUBREG_WORD (x
) + is_dest
));
2503 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
2505 /* If there was a return value, it must have been indicated with USE. */
2520 fmt
= GET_RTX_FORMAT (code
);
2522 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2527 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2528 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
2530 else if (fmt
[i
] == 'e')
2531 used
|= regs_used (XEXP (x
, i
), is_dest
);
2536 /* Create an instruction that prevents redirection of a conditional branch
2537 to the destination of the JUMP with address ADDR.
2538 If the branch needs to be implemented as an indirect jump, try to find
2539 a scratch register for it.
2540 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
2541 If any preceding insn that doesn't fit into a delay slot is good enough,
2542 pass 1. Pass 2 if a definite blocking insn is needed.
2543 -1 is used internally to avoid deep recursion.
2544 If a blocking instruction is made or recognized, return it. */
2547 gen_block_redirect (jump
, addr
, need_block
)
2549 int addr
, need_block
;
2552 rtx prev
= prev_nonnote_insn (jump
);
2555 /* First, check if we already have an instruction that satisfies our need. */
2556 if (prev
&& GET_CODE (prev
) == INSN
&& ! INSN_DELETED_P (prev
))
2558 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
2560 if (GET_CODE (PATTERN (prev
)) == USE
2561 || GET_CODE (PATTERN (prev
)) == CLOBBER
2562 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
2564 else if ((need_block
&= ~1) < 0)
2566 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
2569 /* We can't use JUMP_LABEL here because it might be undefined
2570 when not optimizing. */
2571 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
2572 /* If the branch is out of range, try to find a scratch register for it. */
2574 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ 4092U > 4092 + 4098))
2577 /* Don't look for the stack pointer as a scratch register,
2578 it would cause trouble if an interrupt occurred. */
2579 unsigned try = 0x7fff, used
;
2580 int jump_left
= flag_expensive_optimizations
+ 1;
2582 /* It is likely that the most recent eligible instruction is wanted for
2583 the delay slot. Therefore, find out which registers it uses, and
2584 try to avoid using them. */
2586 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
2590 if (INSN_DELETED_P (scan
))
2592 code
= GET_CODE (scan
);
2593 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
2596 && GET_CODE (PATTERN (scan
)) != USE
2597 && GET_CODE (PATTERN (scan
)) != CLOBBER
2598 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
2600 try &= ~regs_used (PATTERN (scan
), 0);
2604 for (used
= dead
= 0, scan
= JUMP_LABEL (jump
);
2605 (scan
= NEXT_INSN (scan
)); )
2609 if (INSN_DELETED_P (scan
))
2611 code
= GET_CODE (scan
);
2612 if (GET_RTX_CLASS (code
) == 'i')
2614 used
|= regs_used (PATTERN (scan
), 0);
2615 if (code
== CALL_INSN
)
2616 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
2617 dead
|= (used
>> 16) & ~used
;
2623 if (code
== JUMP_INSN
)
2625 if (jump_left
-- && simplejump_p (scan
))
2626 scan
= JUMP_LABEL (scan
);
2632 /* Mask out the stack pointer again, in case it was
2633 the only 'free' register we have found. */
2636 /* If the immediate destination is still in range, check for possible
2637 threading with a jump beyond the delay slot insn.
2638 Don't check if we are called recursively; the jump has been or will be
2639 checked in a different invocation then. */
2641 else if (optimize
&& need_block
>= 0)
2643 rtx next
= next_active_insn (next_active_insn (dest
));
2644 if (next
&& GET_CODE (next
) == JUMP_INSN
2645 && GET_CODE (PATTERN (next
)) == SET
2646 && recog_memoized (next
) == CODE_FOR_jump
)
2648 dest
= JUMP_LABEL (next
);
2650 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ 4092U
2652 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
2658 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
2660 /* It would be nice if we could convert the jump into an indirect
2661 jump / far branch right now, and thus exposing all constituent
2662 instructions to further optimization. However, reorg uses
2663 simplejump_p to determine if there is an unconditional jump where
2664 it should try to schedule instructions from the target of the
2665 branch; simplejump_p fails for indirect jumps even if they have
2667 rtx insn
= emit_insn_before (gen_indirect_jump_scratch
2668 (reg
, GEN_INT (INSN_UID (JUMP_LABEL (jump
))))
2670 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
2673 else if (need_block
)
2674 /* We can't use JUMP_LABEL here because it might be undefined
2675 when not optimizing. */
2676 return emit_insn_before (gen_block_branch_redirect
2677 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))))
2682 #define CONDJUMP_MIN -252
2683 #define CONDJUMP_MAX 262
2686 /* A label (to be placed) in front of the jump
2687 that jumps to our ultimate destination. */
2689 /* Where we are going to insert it if we cannot move the jump any farther,
2690 or the jump itself if we have picked up an existing jump. */
2692 /* The ultimate destination. */
2694 struct far_branch
*prev
;
2695 /* If the branch has already been created, its address;
2696 else the address of its first prospective user. */
2700 static void gen_far_branch
PARAMS ((struct far_branch
*));
2701 enum mdep_reorg_phase_e mdep_reorg_phase
;
2704 struct far_branch
*bp
;
2706 rtx insn
= bp
->insert_place
;
2708 rtx label
= gen_label_rtx ();
2710 emit_label_after (label
, insn
);
2713 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
2714 LABEL_NUSES (bp
->far_label
)++;
2717 jump
= emit_jump_insn_after (gen_return (), insn
);
2718 /* Emit a barrier so that reorg knows that any following instructions
2719 are not reachable via a fall-through path.
2720 But don't do this when not optimizing, since we wouldn't supress the
2721 alignment for the barrier then, and could end up with out-of-range
2722 pc-relative loads. */
2724 emit_barrier_after (jump
);
2725 emit_label_after (bp
->near_label
, insn
);
2726 JUMP_LABEL (jump
) = bp
->far_label
;
2727 if (! invert_jump (insn
, label
, 1))
2729 /* Prevent reorg from undoing our splits. */
2730 gen_block_redirect (jump
, bp
->address
+= 2, 2);
2733 /* Fix up ADDR_DIFF_VECs. */
2735 fixup_addr_diff_vecs (first
)
2740 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2742 rtx vec_lab
, pat
, prev
, prevpat
, x
, braf_label
;
2744 if (GET_CODE (insn
) != JUMP_INSN
2745 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
2747 pat
= PATTERN (insn
);
2748 vec_lab
= XEXP (XEXP (pat
, 0), 0);
2750 /* Search the matching casesi_jump_2. */
2751 for (prev
= vec_lab
; ; prev
= PREV_INSN (prev
))
2753 if (GET_CODE (prev
) != JUMP_INSN
)
2755 prevpat
= PATTERN (prev
);
2756 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
2758 x
= XVECEXP (prevpat
, 0, 1);
2759 if (GET_CODE (x
) != USE
)
2762 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
2766 /* Emit the reference label of the braf where it belongs, right after
2767 the casesi_jump_2 (i.e. braf). */
2768 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
2769 emit_label_after (braf_label
, prev
);
2771 /* Fix up the ADDR_DIF_VEC to be relative
2772 to the reference address of the braf. */
2773 XEXP (XEXP (pat
, 0), 0) = braf_label
;
2777 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
2778 a barrier. Return the base 2 logarithm of the desired alignment. */
2780 barrier_align (barrier_or_label
)
2781 rtx barrier_or_label
;
2783 rtx next
= next_real_insn (barrier_or_label
), pat
, prev
;
2784 int slot
, credit
, jump_to_next
;
2789 pat
= PATTERN (next
);
2791 if (GET_CODE (pat
) == ADDR_DIFF_VEC
)
2794 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
2795 /* This is a barrier in front of a constant table. */
2798 prev
= prev_real_insn (barrier_or_label
);
2799 if (GET_CODE (PATTERN (prev
)) == ADDR_DIFF_VEC
)
2801 pat
= PATTERN (prev
);
2802 /* If this is a very small table, we want to keep the alignment after
2803 the table to the minimum for proper code alignment. */
2804 return ((TARGET_SMALLCODE
2805 || (XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
2806 <= 1 << (CACHE_LOG
- 2)))
2810 if (TARGET_SMALLCODE
)
2813 if (! TARGET_SH2
|| ! optimize
)
2816 /* When fixing up pcloads, a constant table might be inserted just before
2817 the basic block that ends with the barrier. Thus, we can't trust the
2818 instruction lengths before that. */
2819 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
2821 /* Check if there is an immediately preceding branch to the insn beyond
2822 the barrier. We must weight the cost of discarding useful information
2823 from the current cache line when executing this branch and there is
2824 an alignment, against that of fetching unneeded insn in front of the
2825 branch target when there is no alignment. */
2827 /* There are two delay_slot cases to consider. One is the simple case
2828 where the preceding branch is to the insn beyond the barrier (simple
2829 delay slot filling), and the other is where the preceding branch has
2830 a delay slot that is a duplicate of the insn after the barrier
2831 (fill_eager_delay_slots) and the branch is to the insn after the insn
2832 after the barrier. */
2834 /* PREV is presumed to be the JUMP_INSN for the barrier under
2835 investigation. Skip to the insn before it. */
2836 prev
= prev_real_insn (prev
);
2838 for (slot
= 2, credit
= 1 << (CACHE_LOG
- 2) + 2;
2839 credit
>= 0 && prev
&& GET_CODE (prev
) == INSN
;
2840 prev
= prev_real_insn (prev
))
2843 if (GET_CODE (PATTERN (prev
)) == USE
2844 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
2846 if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
2848 prev
= XVECEXP (PATTERN (prev
), 0, 1);
2849 if (INSN_UID (prev
) == INSN_UID (next
))
2851 /* Delay slot was filled with insn at jump target. */
2858 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
2860 credit
-= get_attr_length (prev
);
2863 && GET_CODE (prev
) == JUMP_INSN
2864 && JUMP_LABEL (prev
)
2865 && (jump_to_next
|| next_real_insn (JUMP_LABEL (prev
)) == next
))
2867 rtx pat
= PATTERN (prev
);
2868 if (GET_CODE (pat
) == PARALLEL
)
2869 pat
= XVECEXP (pat
, 0, 0);
2870 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
2878 /* If we are inside a phony loop, almost any kind of label can turn up as the
2879 first one in the loop. Aligning a braf label causes incorrect switch
2880 destination addresses; we can detect braf labels because they are
2881 followed by a BARRIER.
2882 Applying loop alignment to small constant or switch tables is a waste
2883 of space, so we suppress this too. */
2885 sh_loop_align (label
)
2891 next
= next_nonnote_insn (next
);
2892 while (next
&& GET_CODE (next
) == CODE_LABEL
);
2896 || GET_CODE (PATTERN (next
)) == ADDR_DIFF_VEC
2897 || recog_memoized (next
) == CODE_FOR_consttable_2
)
2902 /* Exported to toplev.c.
2904 Do a final pass over the function, just before delayed branch
2908 machine_dependent_reorg (first
)
2913 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
2914 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
2916 /* We must split call insns before introducing `mova's. If we're
2917 optimizing, they'll have already been split. Otherwise, make
2918 sure we don't split them too late. */
2920 split_all_insns (0);
2922 /* If relaxing, generate pseudo-ops to associate function calls with
2923 the symbols they call. It does no harm to not generate these
2924 pseudo-ops. However, when we can generate them, it enables to
2925 linker to potentially relax the jsr to a bsr, and eliminate the
2926 register load and, possibly, the constant pool entry. */
2928 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
2931 /* Remove all REG_LABEL notes. We want to use them for our own
2932 purposes. This works because none of the remaining passes
2933 need to look at them.
2935 ??? But it may break in the future. We should use a machine
2936 dependent REG_NOTE, or some other approach entirely. */
2937 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2943 while ((note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
)) != 0)
2944 remove_note (insn
, note
);
2948 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2950 rtx pattern
, reg
, link
, set
, scan
, dies
, label
;
2951 int rescan
= 0, foundinsn
= 0;
2953 if (GET_CODE (insn
) == CALL_INSN
)
2955 pattern
= PATTERN (insn
);
2957 if (GET_CODE (pattern
) == PARALLEL
)
2958 pattern
= XVECEXP (pattern
, 0, 0);
2959 if (GET_CODE (pattern
) == SET
)
2960 pattern
= SET_SRC (pattern
);
2962 if (GET_CODE (pattern
) != CALL
2963 || GET_CODE (XEXP (pattern
, 0)) != MEM
)
2966 reg
= XEXP (XEXP (pattern
, 0), 0);
2970 reg
= sfunc_uses_reg (insn
);
2975 if (GET_CODE (reg
) != REG
)
2978 /* This is a function call via REG. If the only uses of REG
2979 between the time that it is set and the time that it dies
2980 are in function calls, then we can associate all the
2981 function calls with the setting of REG. */
2983 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
2985 if (REG_NOTE_KIND (link
) != 0)
2987 set
= single_set (XEXP (link
, 0));
2988 if (set
&& rtx_equal_p (reg
, SET_DEST (set
)))
2990 link
= XEXP (link
, 0);
2997 /* ??? Sometimes global register allocation will have
2998 deleted the insn pointed to by LOG_LINKS. Try
2999 scanning backward to find where the register is set. */
3000 for (scan
= PREV_INSN (insn
);
3001 scan
&& GET_CODE (scan
) != CODE_LABEL
;
3002 scan
= PREV_INSN (scan
))
3004 if (! INSN_P (scan
))
3007 if (! reg_mentioned_p (reg
, scan
))
3010 if (noncall_uses_reg (reg
, scan
, &set
))
3024 /* The register is set at LINK. */
3026 /* We can only optimize the function call if the register is
3027 being set to a symbol. In theory, we could sometimes
3028 optimize calls to a constant location, but the assembler
3029 and linker do not support that at present. */
3030 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
3031 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
3034 /* Scan forward from LINK to the place where REG dies, and
3035 make sure that the only insns which use REG are
3036 themselves function calls. */
3038 /* ??? This doesn't work for call targets that were allocated
3039 by reload, since there may not be a REG_DEAD note for the
3043 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
3047 /* Don't try to trace forward past a CODE_LABEL if we haven't
3048 seen INSN yet. Ordinarily, we will only find the setting insn
3049 in LOG_LINKS if it is in the same basic block. However,
3050 cross-jumping can insert code labels in between the load and
3051 the call, and can result in situations where a single call
3052 insn may have two targets depending on where we came from. */
3054 if (GET_CODE (scan
) == CODE_LABEL
&& ! foundinsn
)
3057 if (! INSN_P (scan
))
3060 /* Don't try to trace forward past a JUMP. To optimize
3061 safely, we would have to check that all the
3062 instructions at the jump destination did not use REG. */
3064 if (GET_CODE (scan
) == JUMP_INSN
)
3067 if (! reg_mentioned_p (reg
, scan
))
3070 if (noncall_uses_reg (reg
, scan
, &scanset
))
3077 && (GET_CODE (scan
) == CALL_INSN
|| sfunc_uses_reg (scan
)))
3079 /* There is a function call to this register other
3080 than the one we are checking. If we optimize
3081 this call, we need to rescan again below. */
3085 /* ??? We shouldn't have to worry about SCANSET here.
3086 We should just be able to check for a REG_DEAD note
3087 on a function call. However, the REG_DEAD notes are
3088 apparently not dependable around libcalls; c-torture
3089 execute/920501-2 is a test case. If SCANSET is set,
3090 then this insn sets the register, so it must have
3091 died earlier. Unfortunately, this will only handle
3092 the cases in which the register is, in fact, set in a
3095 /* ??? We shouldn't have to use FOUNDINSN here.
3096 However, the LOG_LINKS fields are apparently not
3097 entirely reliable around libcalls;
3098 newlib/libm/math/e_pow.c is a test case. Sometimes
3099 an insn will appear in LOG_LINKS even though it is
3100 not the most recent insn which sets the register. */
3104 || find_reg_note (scan
, REG_DEAD
, reg
)))
3113 /* Either there was a branch, or some insn used REG
3114 other than as a function call address. */
3118 /* Create a code label, and put it in a REG_LABEL note on
3119 the insn which sets the register, and on each call insn
3120 which uses the register. In final_prescan_insn we look
3121 for the REG_LABEL notes, and output the appropriate label
3124 label
= gen_label_rtx ();
3125 REG_NOTES (link
) = gen_rtx_EXPR_LIST (REG_LABEL
, label
,
3127 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_LABEL
, label
,
3136 scan
= NEXT_INSN (scan
);
3138 && ((GET_CODE (scan
) == CALL_INSN
3139 && reg_mentioned_p (reg
, scan
))
3140 || ((reg2
= sfunc_uses_reg (scan
))
3141 && REGNO (reg2
) == REGNO (reg
))))
3143 = gen_rtx_EXPR_LIST (REG_LABEL
, label
, REG_NOTES (scan
));
3145 while (scan
!= dies
);
3151 fixup_addr_diff_vecs (first
);
3155 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
3156 shorten_branches (first
);
3158 /* Scan the function looking for move instructions which have to be
3159 changed to pc-relative loads and insert the literal tables. */
3161 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
3162 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
3169 else if (GET_CODE (insn
) == JUMP_INSN
3170 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3178 /* Some code might have been inserted between the mova and
3179 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3180 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
3181 total
+= get_attr_length (scan
);
3183 /* range of mova is 1020, add 4 because pc counts from address of
3184 second instruction after this one, subtract 2 in case pc is 2
3185 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3186 cancels out with alignment effects of the mova itself. */
3189 /* Change the mova into a load, and restart scanning
3190 there. broken_move will then return true for mova. */
3191 SET_SRC (PATTERN (mova
))
3192 = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
3193 INSN_CODE (mova
) = -1;
3197 if (broken_move (insn
))
3200 /* Scan ahead looking for a barrier to stick the constant table
3202 rtx barrier
= find_barrier (num_mova
, mova
, insn
);
3203 rtx last_float_move
, last_float
= 0, *last_float_addr
;
3205 if (num_mova
&& ! mova_p (mova
))
3207 /* find_barrier had to change the first mova into a
3208 pcload; thus, we have to start with this new pcload. */
3212 /* Now find all the moves between the points and modify them. */
3213 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
3215 if (GET_CODE (scan
) == CODE_LABEL
)
3217 if (broken_move (scan
))
3219 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
3223 enum machine_mode mode
;
3225 if (GET_CODE (pat
) == PARALLEL
)
3226 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
3227 src
= SET_SRC (pat
);
3228 dst
= SET_DEST (pat
);
3229 mode
= GET_MODE (dst
);
3231 if (mode
== SImode
&& hi_const (src
)
3232 && REGNO (dst
) != FPUL_REG
)
3237 while (GET_CODE (dst
) == SUBREG
)
3239 offset
+= SUBREG_WORD (dst
);
3240 dst
= SUBREG_REG (dst
);
3242 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
3245 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
3247 /* This must be an insn that clobbers r0. */
3248 rtx clobber
= XVECEXP (PATTERN (scan
), 0,
3249 XVECLEN (PATTERN (scan
), 0) - 1);
3251 if (GET_CODE (clobber
) != CLOBBER
3252 || ! rtx_equal_p (XEXP (clobber
, 0), r0_rtx
))
3256 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
3258 lab
= add_constant (src
, mode
, last_float
);
3260 emit_insn_before (gen_mova (lab
), scan
);
3263 /* There will be a REG_UNUSED note for r0 on
3264 LAST_FLOAT_MOVE; we have to change it to REG_INC,
3265 lest reorg:mark_target_live_regs will not
3266 consider r0 to be used, and we end up with delay
3267 slot insn in front of SCAN that clobbers r0. */
3269 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
3271 /* If we are not optimizing, then there may not be
3274 PUT_MODE (note
, REG_INC
);
3276 *last_float_addr
= r0_inc_rtx
;
3278 last_float_move
= scan
;
3280 newsrc
= gen_rtx (MEM
, mode
,
3281 (((TARGET_SH4
&& ! TARGET_FMOVD
)
3282 || REGNO (dst
) == FPUL_REG
)
3285 last_float_addr
= &XEXP (newsrc
, 0);
3287 /* Remove the clobber of r0. */
3288 XEXP (clobber
, 0) = gen_rtx_SCRATCH (Pmode
);
3290 /* This is a mova needing a label. Create it. */
3291 else if (GET_CODE (src
) == UNSPEC
3292 && XINT (src
, 1) == UNSPEC_MOVA
3293 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
3295 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
3296 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
3297 newsrc
= gen_rtx_UNSPEC (VOIDmode
,
3298 gen_rtvec (1, newsrc
),
3303 lab
= add_constant (src
, mode
, 0);
3304 newsrc
= gen_rtx_MEM (mode
,
3305 gen_rtx_LABEL_REF (VOIDmode
, lab
));
3307 RTX_UNCHANGING_P (newsrc
) = 1;
3308 *patp
= gen_rtx_SET (VOIDmode
, dst
, newsrc
);
3309 INSN_CODE (scan
) = -1;
3312 dump_table (barrier
);
3317 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
3318 INSN_ADDRESSES_FREE ();
3319 split_branches (first
);
3321 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
3322 also has an effect on the register that holds the addres of the sfunc.
3323 Insert an extra dummy insn in front of each sfunc that pretends to
3324 use this register. */
3325 if (flag_delayed_branch
)
3327 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3329 rtx reg
= sfunc_uses_reg (insn
);
3333 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
3337 /* fpscr is not actually a user variable, but we pretend it is for the
3338 sake of the previous optimization passes, since we want it handled like
3339 one. However, we don't have any debugging information for it, so turn
3340 it into a non-user variable now. */
3342 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
3344 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
3348 get_dest_uid (label
, max_uid
)
3352 rtx dest
= next_real_insn (label
);
3355 /* This can happen for an undefined label. */
3357 dest_uid
= INSN_UID (dest
);
3358 /* If this is a newly created branch redirection blocking instruction,
3359 we cannot index the branch_uid or insn_addresses arrays with its
3360 uid. But then, we won't need to, because the actual destination is
3361 the following branch. */
3362 while (dest_uid
>= max_uid
)
3364 dest
= NEXT_INSN (dest
);
3365 dest_uid
= INSN_UID (dest
);
3367 if (GET_CODE (dest
) == JUMP_INSN
&& GET_CODE (PATTERN (dest
)) == RETURN
)
3372 /* Split condbranches that are out of range. Also add clobbers for
3373 scratch registers that are needed in far jumps.
3374 We do this before delay slot scheduling, so that it can take our
3375 newly created instructions into account. It also allows us to
3376 find branches with common targets more easily. */
3379 split_branches (first
)
3383 struct far_branch
**uid_branch
, *far_branch_list
= 0;
3384 int max_uid
= get_max_uid ();
3386 /* Find out which branches are out of range. */
3387 shorten_branches (first
);
3389 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
3390 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
3392 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3393 if (! INSN_P (insn
))
3395 else if (INSN_DELETED_P (insn
))
3397 /* Shorten_branches would split this instruction again,
3398 so transform it into a note. */
3399 PUT_CODE (insn
, NOTE
);
3400 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
3401 NOTE_SOURCE_FILE (insn
) = 0;
3403 else if (GET_CODE (insn
) == JUMP_INSN
3404 /* Don't mess with ADDR_DIFF_VEC */
3405 && (GET_CODE (PATTERN (insn
)) == SET
3406 || GET_CODE (PATTERN (insn
)) == RETURN
))
3408 enum attr_type type
= get_attr_type (insn
);
3409 if (type
== TYPE_CBRANCH
)
3413 if (get_attr_length (insn
) > 4)
3415 rtx src
= SET_SRC (PATTERN (insn
));
3416 rtx olabel
= XEXP (XEXP (src
, 1), 0);
3417 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
3419 int dest_uid
= get_dest_uid (olabel
, max_uid
);
3420 struct far_branch
*bp
= uid_branch
[dest_uid
];
3422 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
3423 the label if the LABEL_NUSES count drops to zero. There is
3424 always a jump_optimize pass that sets these values, but it
3425 proceeds to delete unreferenced code, and then if not
3426 optimizing, to un-delete the deleted instructions, thus
3427 leaving labels with too low uses counts. */
3430 JUMP_LABEL (insn
) = olabel
;
3431 LABEL_NUSES (olabel
)++;
3435 bp
= (struct far_branch
*) alloca (sizeof *bp
);
3436 uid_branch
[dest_uid
] = bp
;
3437 bp
->prev
= far_branch_list
;
3438 far_branch_list
= bp
;
3440 = XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1), 0);
3441 LABEL_NUSES (bp
->far_label
)++;
3445 label
= bp
->near_label
;
3446 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
3448 rtx block
= bp
->insert_place
;
3450 if (GET_CODE (PATTERN (block
)) == RETURN
)
3451 block
= PREV_INSN (block
);
3453 block
= gen_block_redirect (block
,
3455 label
= emit_label_after (gen_label_rtx (),
3457 bp
->near_label
= label
;
3459 else if (label
&& ! NEXT_INSN (label
))
3461 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
3462 bp
->insert_place
= insn
;
3464 gen_far_branch (bp
);
3468 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
3470 bp
->near_label
= label
= gen_label_rtx ();
3471 bp
->insert_place
= insn
;
3474 if (! redirect_jump (insn
, label
, 1))
3479 /* get_attr_length (insn) == 2 */
3480 /* Check if we have a pattern where reorg wants to redirect
3481 the branch to a label from an unconditional branch that
3483 /* We can't use JUMP_LABEL here because it might be undefined
3484 when not optimizing. */
3485 /* A syntax error might cause beyond to be NULL_RTX. */
3487 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
3491 && (GET_CODE (beyond
) == JUMP_INSN
3492 || ((beyond
= next_active_insn (beyond
))
3493 && GET_CODE (beyond
) == JUMP_INSN
))
3494 && GET_CODE (PATTERN (beyond
)) == SET
3495 && recog_memoized (beyond
) == CODE_FOR_jump
3497 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
3498 - INSN_ADDRESSES (INSN_UID (insn
)) + 252U)
3500 gen_block_redirect (beyond
,
3501 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
3504 next
= next_active_insn (insn
);
3506 if ((GET_CODE (next
) == JUMP_INSN
3507 || GET_CODE (next
= next_active_insn (next
)) == JUMP_INSN
)
3508 && GET_CODE (PATTERN (next
)) == SET
3509 && recog_memoized (next
) == CODE_FOR_jump
3511 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
3512 - INSN_ADDRESSES (INSN_UID (insn
)) + 252U)
3514 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
3516 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
3518 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
3521 struct far_branch
*bp
;
3523 if (type
== TYPE_JUMP
)
3525 far_label
= XEXP (SET_SRC (PATTERN (insn
)), 0);
3526 dest_uid
= get_dest_uid (far_label
, max_uid
);
3529 /* Parse errors can lead to labels outside
3531 if (! NEXT_INSN (far_label
))
3536 JUMP_LABEL (insn
) = far_label
;
3537 LABEL_NUSES (far_label
)++;
3539 redirect_jump (insn
, NULL_RTX
, 1);
3543 bp
= uid_branch
[dest_uid
];
3546 bp
= (struct far_branch
*) alloca (sizeof *bp
);
3547 uid_branch
[dest_uid
] = bp
;
3548 bp
->prev
= far_branch_list
;
3549 far_branch_list
= bp
;
3551 bp
->far_label
= far_label
;
3553 LABEL_NUSES (far_label
)++;
3555 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
3556 if (addr
- bp
->address
<= CONDJUMP_MAX
)
3557 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
3560 gen_far_branch (bp
);
3566 bp
->insert_place
= insn
;
3568 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
3570 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
3573 /* Generate all pending far branches,
3574 and free our references to the far labels. */
3575 while (far_branch_list
)
3577 if (far_branch_list
->near_label
3578 && ! NEXT_INSN (far_branch_list
->near_label
))
3579 gen_far_branch (far_branch_list
);
3581 && far_branch_list
->far_label
3582 && ! --LABEL_NUSES (far_branch_list
->far_label
))
3583 delete_insn (far_branch_list
->far_label
);
3584 far_branch_list
= far_branch_list
->prev
;
3587 /* Instruction length information is no longer valid due to the new
3588 instructions that have been generated. */
3589 init_insn_lengths ();
3592 /* Dump out instruction addresses, which is useful for debugging the
3593 constant pool table stuff.
3595 If relaxing, output the label and pseudo-ops used to link together
3596 calls and the instruction which set the registers. */
3598 /* ??? This is unnecessary, and probably should be deleted. This makes
3599 the insn_addresses declaration above unnecessary. */
3601 /* ??? The addresses printed by this routine for insns are nonsense for
3602 insns which are inside of a sequence where none of the inner insns have
3603 variable length. This is because the second pass of shorten_branches
3604 does not bother to update them. */
3607 final_prescan_insn (insn
, opvec
, noperands
)
3609 rtx
*opvec ATTRIBUTE_UNUSED
;
3610 int noperands ATTRIBUTE_UNUSED
;
3612 if (TARGET_DUMPISIZE
)
3613 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
3619 note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
);
3624 pattern
= PATTERN (insn
);
3625 if (GET_CODE (pattern
) == PARALLEL
)
3626 pattern
= XVECEXP (pattern
, 0, 0);
3627 if (GET_CODE (pattern
) == CALL
3628 || (GET_CODE (pattern
) == SET
3629 && (GET_CODE (SET_SRC (pattern
)) == CALL
3630 || get_attr_type (insn
) == TYPE_SFUNC
)))
3631 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
3632 CODE_LABEL_NUMBER (XEXP (note
, 0)));
3633 else if (GET_CODE (pattern
) == SET
)
3634 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
3635 CODE_LABEL_NUMBER (XEXP (note
, 0)));
3642 /* Dump out any constants accumulated in the final pass. These will
3646 output_jump_label_table ()
3652 fprintf (asm_out_file
, "\t.align 2\n");
3653 for (i
= 0; i
< pool_size
; i
++)
3655 pool_node
*p
= &pool_vector
[i
];
3657 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
3658 CODE_LABEL_NUMBER (p
->label
));
3659 output_asm_insn (".long %O0", &p
->value
);
3667 /* A full frame looks like:
3671 [ if current_function_anonymous_args
3684 local-0 <- fp points here. */
3686 /* Number of bytes pushed for anonymous args, used to pass information
3687 between expand_prologue and expand_epilogue. */
3689 static int extra_push
;
3691 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
3692 to be adjusted, and TEMP, if nonnegative, holds the register number
3693 of a general register that we may clobber. */
3696 output_stack_adjust (size
, reg
, temp
)
3703 if (CONST_OK_FOR_I (size
))
3704 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
3705 /* Try to do it with two partial adjustments; however, we must make
3706 sure that the stack is properly aligned at all times, in case
3707 an interrupt occurs between the two partial adjustments. */
3708 else if (CONST_OK_FOR_I (size
/ 2 & -4)
3709 && CONST_OK_FOR_I (size
- (size
/ 2 & -4)))
3711 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
/ 2 & -4)));
3712 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -4))));
3718 /* If TEMP is invalid, we could temporarily save a general
3719 register to MACL. However, there is currently no need
3720 to handle this case, so just abort when we see it. */
3723 const_reg
= gen_rtx_REG (SImode
, temp
);
3725 /* If SIZE is negative, subtract the positive value.
3726 This sometimes allows a constant pool entry to be shared
3727 between prologue and epilogue code. */
3730 emit_insn (gen_movsi (const_reg
, GEN_INT (-size
)));
3731 emit_insn (gen_subsi3 (reg
, reg
, const_reg
));
3735 emit_insn (gen_movsi (const_reg
, GEN_INT (size
)));
3736 emit_insn (gen_addsi3 (reg
, reg
, const_reg
));
3742 /* Output RTL to push register RN onto the stack. */
3750 x
= gen_push_fpul ();
3751 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
3752 && FP_OR_XD_REGISTER_P (rn
))
3754 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
3756 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
3758 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
3759 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
3761 x
= gen_push (gen_rtx_REG (SImode
, rn
));
3765 = gen_rtx_EXPR_LIST (REG_INC
,
3766 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
3769 /* Output RTL to pop register RN from the stack. */
3777 x
= gen_pop_fpul ();
3778 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
3779 && FP_OR_XD_REGISTER_P (rn
))
3781 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
3783 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
3785 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
3786 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
3788 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
3792 = gen_rtx_EXPR_LIST (REG_INC
,
3793 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
3796 /* Generate code to push the regs specified in the mask. */
3799 push_regs (mask
, mask2
)
3804 /* Push PR last; this gives better latencies after the prologue, and
3805 candidates for the return delay slot when there are no general
3806 registers pushed. */
3807 for (i
= 0; i
< 32; i
++)
3808 if (mask
& (1 << i
) && i
!= PR_REG
)
3810 for (i
= 32; i
< FIRST_PSEUDO_REGISTER
; i
++)
3811 if (mask2
& (1 << (i
- 32)))
3813 if (mask
& (1 << PR_REG
))
3817 /* Work out the registers which need to be saved, both as a mask and a
3818 count of saved words.
3820 If doing a pragma interrupt function, then push all regs used by the
3821 function, and if we call another function (we can tell by looking at PR),
3822 make sure that all the regs it clobbers are safe too. */
3825 calc_live_regs (count_ptr
, live_regs_mask2
)
3827 int *live_regs_mask2
;
3830 int live_regs_mask
= 0;
3832 int interrupt_handler
;
3834 if ((lookup_attribute
3835 ("interrupt_handler",
3836 DECL_MACHINE_ATTRIBUTES (current_function_decl
)))
3838 interrupt_handler
= 1;
3840 interrupt_handler
= 0;
3842 *live_regs_mask2
= 0;
3843 /* If we can save a lot of saves by switching to double mode, do that. */
3844 if (TARGET_SH4
&& TARGET_FMOVD
&& TARGET_FPU_SINGLE
)
3845 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
3846 if (regs_ever_live
[reg
] && regs_ever_live
[reg
+1]
3847 && (! call_used_regs
[reg
] || (interrupt_handler
&& ! pragma_trapa
))
3850 target_flags
&= ~FPU_SINGLE_BIT
;
3853 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
- 1; reg
>= 0; reg
--)
3855 if ((interrupt_handler
&& ! pragma_trapa
)
3856 ? (/* Need to save all the regs ever live. */
3857 (regs_ever_live
[reg
]
3858 || (call_used_regs
[reg
]
3859 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
)
3860 && regs_ever_live
[PR_REG
]))
3861 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
3862 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
3863 && reg
!= T_REG
&& reg
!= GBR_REG
&& reg
!= FPSCR_REG
)
3864 : (/* Only push those regs which are used and need to be saved. */
3865 regs_ever_live
[reg
] && ! call_used_regs
[reg
]))
3868 *live_regs_mask2
|= 1 << (reg
- 32);
3870 live_regs_mask
|= 1 << reg
;
3872 if (TARGET_SH4
&& TARGET_FMOVD
&& FP_OR_XD_REGISTER_P (reg
))
3874 if (FP_REGISTER_P (reg
))
3876 if (! TARGET_FPU_SINGLE
&& ! regs_ever_live
[reg
^ 1])
3879 *live_regs_mask2
|= 1 << ((reg
^ 1) - 32);
3881 live_regs_mask
|= 1 << (reg
^ 1);
3885 else /* if (XD_REGISTER_P (reg)) */
3887 /* Must switch to double mode to access these registers. */
3888 target_flags
&= ~FPU_SINGLE_BIT
;
3895 *count_ptr
= count
* UNITS_PER_WORD
;
3896 return live_regs_mask
;
3899 /* Code to generate prologue and epilogue sequences */
3901 /* PUSHED is the number of bytes that are bing pushed on the
3902 stack for register saves. Return the frame size, padded
3903 appropriately so that the stack stays properly aligned. */
3904 static HOST_WIDE_INT
3905 rounded_frame_size (pushed
)
3908 HOST_WIDE_INT size
= get_frame_size ();
3909 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
3911 return (size
+ pushed
+ align
- 1 & -align
) - pushed
;
3915 sh_expand_prologue ()
3919 int live_regs_mask2
;
3920 int save_flags
= target_flags
;
3922 /* We have pretend args if we had an object sent partially in registers
3923 and partially on the stack, e.g. a large structure. */
3924 output_stack_adjust (-current_function_pretend_args_size
,
3925 stack_pointer_rtx
, 3);
3929 /* This is set by SETUP_VARARGS to indicate that this is a varargs
3930 routine. Clear it here so that the next function isn't affected. */
3931 if (current_function_anonymous_args
)
3933 current_function_anonymous_args
= 0;
3935 /* This is not used by the SH3E calling convention */
3936 if (! TARGET_SH3E
&& ! TARGET_HITACHI
)
3938 /* Push arg regs as if they'd been provided by caller in stack. */
3939 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
3941 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
3942 if (i
>= (NPARM_REGS(SImode
)
3943 - current_function_args_info
.arg_count
[(int) SH_ARG_INT
]
3952 /* If we're supposed to switch stacks at function entry, do so now. */
3954 emit_insn (gen_sp_switch_1 ());
3956 live_regs_mask
= calc_live_regs (&d
, &live_regs_mask2
);
3957 /* ??? Maybe we could save some switching if we can move a mode switch
3958 that already happens to be at the function start into the prologue. */
3959 if (target_flags
!= save_flags
)
3960 emit_insn (gen_toggle_sz ());
3962 push_regs (live_regs_mask
, live_regs_mask2
);
3964 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
3965 emit_insn (gen_GOTaddr2picreg ());
3967 if (target_flags
!= save_flags
)
3968 emit_insn (gen_toggle_sz ());
3970 target_flags
= save_flags
;
3972 output_stack_adjust (-rounded_frame_size (d
),
3973 stack_pointer_rtx
, 3);
3975 if (frame_pointer_needed
)
3976 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
3980 sh_expand_epilogue ()
3985 int live_regs_mask2
;
3986 int save_flags
= target_flags
;
3989 live_regs_mask
= calc_live_regs (&d
, &live_regs_mask2
);
3991 frame_size
= rounded_frame_size (d
);
3993 if (frame_pointer_needed
)
3995 output_stack_adjust (frame_size
, frame_pointer_rtx
, 7);
3997 /* We must avoid moving the stack pointer adjustment past code
3998 which reads from the local frame, else an interrupt could
3999 occur after the SP adjustment and clobber data in the local
4001 emit_insn (gen_blockage ());
4002 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
4004 else if (frame_size
)
4006 /* We must avoid moving the stack pointer adjustment past code
4007 which reads from the local frame, else an interrupt could
4008 occur after the SP adjustment and clobber data in the local
4010 emit_insn (gen_blockage ());
4011 output_stack_adjust (frame_size
, stack_pointer_rtx
, 7);
4014 /* Pop all the registers. */
4016 if (target_flags
!= save_flags
)
4017 emit_insn (gen_toggle_sz ());
4018 if (live_regs_mask
& (1 << PR_REG
))
4020 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4022 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
4023 if (j
< 32 && (live_regs_mask
& (1 << j
)) && j
!= PR_REG
)
4025 else if (j
>= 32 && (live_regs_mask2
& (1 << (j
- 32))))
4028 if (target_flags
!= save_flags
)
4029 emit_insn (gen_toggle_sz ());
4030 target_flags
= save_flags
;
4032 output_stack_adjust (extra_push
+ current_function_pretend_args_size
,
4033 stack_pointer_rtx
, 7);
4035 /* Switch back to the normal stack if necessary. */
4037 emit_insn (gen_sp_switch_2 ());
4040 static int sh_need_epilogue_known
= 0;
4045 if (! sh_need_epilogue_known
)
4050 sh_expand_epilogue ();
4051 epilogue
= gen_sequence ();
4053 sh_need_epilogue_known
4054 = (GET_CODE (epilogue
) == SEQUENCE
&& XVECLEN (epilogue
, 0) == 0
4057 return sh_need_epilogue_known
> 0;
4060 /* Clear variables at function end. */
4063 function_epilogue (stream
, size
)
4064 FILE *stream ATTRIBUTE_UNUSED
;
4065 int size ATTRIBUTE_UNUSED
;
4067 trap_exit
= pragma_interrupt
= pragma_trapa
= pragma_nosave_low_regs
= 0;
4068 sh_need_epilogue_known
= 0;
4069 sp_switch
= NULL_RTX
;
4073 sh_builtin_saveregs ()
4075 /* First unnamed integer register. */
4076 int first_intreg
= current_function_args_info
.arg_count
[(int) SH_ARG_INT
];
4077 /* Number of integer registers we need to save. */
4078 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
4079 /* First unnamed SFmode float reg */
4080 int first_floatreg
= current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
4081 /* Number of SFmode float regs to save. */
4082 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
4084 int bufsize
, regno
, alias_set
;
4086 /* Allocate block of memory for the regs. */
4087 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
4088 Or can assign_stack_local accept a 0 SIZE argument? */
4089 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
4091 regbuf
= assign_stack_local (BLKmode
, bufsize
, 0);
4092 alias_set
= get_varargs_alias_set ();
4093 MEM_ALIAS_SET (regbuf
) = alias_set
;
4096 This is optimized to only save the regs that are necessary. Explicitly
4097 named args need not be saved. */
4099 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
4100 change_address (regbuf
, BLKmode
,
4101 plus_constant (XEXP (regbuf
, 0),
4103 * UNITS_PER_WORD
))),
4104 n_intregs
, n_intregs
* UNITS_PER_WORD
);
4107 This is optimized to only save the regs that are necessary. Explicitly
4108 named args need not be saved.
4109 We explicitly build a pointer to the buffer because it halves the insn
4110 count when not optimizing (otherwise the pointer is built for each reg
4112 We emit the moves in reverse order so that we can use predecrement. */
4114 fpregs
= gen_reg_rtx (Pmode
);
4115 emit_move_insn (fpregs
, XEXP (regbuf
, 0));
4116 emit_insn (gen_addsi3 (fpregs
, fpregs
,
4117 GEN_INT (n_floatregs
* UNITS_PER_WORD
)));
4121 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
4123 emit_insn (gen_addsi3 (fpregs
, fpregs
,
4124 GEN_INT (-2 * UNITS_PER_WORD
)));
4125 mem
= gen_rtx_MEM (DFmode
, fpregs
);
4126 MEM_ALIAS_SET (mem
) = alias_set
;
4127 emit_move_insn (mem
,
4128 gen_rtx (REG
, DFmode
, BASE_ARG_REG (DFmode
) + regno
));
4130 regno
= first_floatreg
;
4133 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
4134 mem
= gen_rtx_MEM (SFmode
, fpregs
);
4135 MEM_ALIAS_SET (mem
) = alias_set
;
4136 emit_move_insn (mem
,
4137 gen_rtx (REG
, SFmode
, BASE_ARG_REG (SFmode
) + regno
4138 - (TARGET_LITTLE_ENDIAN
!= 0)));
4142 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
4145 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
4146 mem
= gen_rtx_MEM (SFmode
, fpregs
);
4147 MEM_ALIAS_SET (mem
) = alias_set
;
4148 emit_move_insn (mem
,
4149 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
4152 /* Return the address of the regbuf. */
4153 return XEXP (regbuf
, 0);
4156 /* Define the `__builtin_va_list' type for the ABI. */
4161 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
4164 if ((! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
4165 return ptr_type_node
;
4167 record
= make_node (RECORD_TYPE
);
4169 f_next_o
= build_decl (FIELD_DECL
, get_identifier ("__va_next_o"),
4171 f_next_o_limit
= build_decl (FIELD_DECL
,
4172 get_identifier ("__va_next_o_limit"),
4174 f_next_fp
= build_decl (FIELD_DECL
, get_identifier ("__va_next_fp"),
4176 f_next_fp_limit
= build_decl (FIELD_DECL
,
4177 get_identifier ("__va_next_fp_limit"),
4179 f_next_stack
= build_decl (FIELD_DECL
, get_identifier ("__va_next_stack"),
4182 DECL_FIELD_CONTEXT (f_next_o
) = record
;
4183 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
4184 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
4185 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
4186 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
4188 TYPE_FIELDS (record
) = f_next_o
;
4189 TREE_CHAIN (f_next_o
) = f_next_o_limit
;
4190 TREE_CHAIN (f_next_o_limit
) = f_next_fp
;
4191 TREE_CHAIN (f_next_fp
) = f_next_fp_limit
;
4192 TREE_CHAIN (f_next_fp_limit
) = f_next_stack
;
4194 layout_type (record
);
4199 /* Implement `va_start' for varargs and stdarg. */
4202 sh_va_start (stdarg_p
, valist
, nextarg
)
4207 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
4208 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
4212 if ((! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
4214 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
4218 f_next_o
= TYPE_FIELDS (va_list_type_node
);
4219 f_next_o_limit
= TREE_CHAIN (f_next_o
);
4220 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
4221 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
4222 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
4224 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
4225 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
4226 valist
, f_next_o_limit
);
4227 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
);
4228 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
4229 valist
, f_next_fp_limit
);
4230 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
4231 valist
, f_next_stack
);
4233 /* Call __builtin_saveregs. */
4234 u
= make_tree (ptr_type_node
, expand_builtin_saveregs ());
4235 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
4236 TREE_SIDE_EFFECTS (t
) = 1;
4237 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4239 nfp
= current_function_args_info
.arg_count
[SH_ARG_FLOAT
];
4244 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
4245 build_int_2 (UNITS_PER_WORD
* nfp
, 0)));
4246 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
4247 TREE_SIDE_EFFECTS (t
) = 1;
4248 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4250 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
4251 TREE_SIDE_EFFECTS (t
) = 1;
4252 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4254 nint
= current_function_args_info
.arg_count
[SH_ARG_INT
];
4259 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
4260 build_int_2 (UNITS_PER_WORD
* nint
, 0)));
4261 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
4262 TREE_SIDE_EFFECTS (t
) = 1;
4263 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4265 u
= make_tree (ptr_type_node
, nextarg
);
4266 if (! stdarg_p
&& (nint
== 0 || nfp
== 0))
4268 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
4269 build_int_2 (-UNITS_PER_WORD
, -1)));
4271 t
= build (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
4272 TREE_SIDE_EFFECTS (t
) = 1;
4273 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4276 /* Implement `va_arg'. */
4279 sh_va_arg (valist
, type
)
4282 HOST_WIDE_INT size
, rsize
;
4283 tree tmp
, pptr_type_node
;
4286 size
= int_size_in_bytes (type
);
4287 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4288 pptr_type_node
= build_pointer_type (ptr_type_node
);
4290 if ((TARGET_SH3E
|| TARGET_SH4
) && ! TARGET_HITACHI
)
4292 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
4293 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
4295 rtx lab_false
, lab_over
;
4297 f_next_o
= TYPE_FIELDS (va_list_type_node
);
4298 f_next_o_limit
= TREE_CHAIN (f_next_o
);
4299 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
4300 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
4301 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
4303 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
4304 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
4305 valist
, f_next_o_limit
);
4306 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
4308 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
4309 valist
, f_next_fp_limit
);
4310 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
4311 valist
, f_next_stack
);
4315 pass_as_float
= ((TREE_CODE (type
) == REAL_TYPE
&& size
<= 8)
4316 || (TREE_CODE (type
) == COMPLEX_TYPE
4317 && TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
4322 pass_as_float
= (TREE_CODE (type
) == REAL_TYPE
&& size
== 4);
4325 addr_rtx
= gen_reg_rtx (Pmode
);
4326 lab_false
= gen_label_rtx ();
4327 lab_over
= gen_label_rtx ();
4331 emit_cmp_and_jump_insns (expand_expr (next_fp
, NULL_RTX
, Pmode
,
4333 expand_expr (next_fp_limit
, NULL_RTX
,
4334 Pmode
, EXPAND_NORMAL
),
4335 GE
, const1_rtx
, Pmode
, 1, 1, lab_false
);
4337 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
4339 tmp
= build (BIT_AND_EXPR
, ptr_type_node
, next_fp
,
4340 build_int_2 (UNITS_PER_WORD
, 0));
4341 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_fp
, tmp
);
4342 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, tmp
);
4343 TREE_SIDE_EFFECTS (tmp
) = 1;
4344 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4347 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_fp
);
4348 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4350 emit_move_insn (addr_rtx
, r
);
4352 emit_jump_insn (gen_jump (lab_over
));
4354 emit_label (lab_false
);
4356 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
4357 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4359 emit_move_insn (addr_rtx
, r
);
4363 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_o
,
4364 build_int_2 (rsize
, 0));
4366 emit_cmp_and_jump_insns (expand_expr (tmp
, NULL_RTX
, Pmode
,
4368 expand_expr (next_o_limit
, NULL_RTX
,
4369 Pmode
, EXPAND_NORMAL
),
4370 GT
, const1_rtx
, Pmode
, 1, 1, lab_false
);
4372 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_o
);
4373 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4375 emit_move_insn (addr_rtx
, r
);
4377 emit_jump_insn (gen_jump (lab_over
));
4379 emit_label (lab_false
);
4381 if (size
> 4 && ! TARGET_SH4
)
4383 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, next_o_limit
);
4384 TREE_SIDE_EFFECTS (tmp
) = 1;
4385 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4388 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
4389 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4391 emit_move_insn (addr_rtx
, r
);
4394 emit_label (lab_over
);
4396 tmp
= make_tree (pptr_type_node
, addr_rtx
);
4397 valist
= build1 (INDIRECT_REF
, ptr_type_node
, tmp
);
4400 /* ??? In va-sh.h, there had been code to make values larger than
4401 size 8 indirect. This does not match the FUNCTION_ARG macros. */
4403 return std_expand_builtin_va_arg (valist
, type
);
4406 /* Define the offset between two registers, one to be eliminated, and
4407 the other its replacement, at the start of a routine. */
4410 initial_elimination_offset (from
, to
)
4415 int total_saved_regs_space
;
4416 int total_auto_space
;
4417 int save_flags
= target_flags
;
4419 int live_regs_mask
, live_regs_mask2
;
4420 live_regs_mask
= calc_live_regs (®s_saved
, &live_regs_mask2
);
4421 total_auto_space
= rounded_frame_size (regs_saved
);
4422 target_flags
= save_flags
;
4424 total_saved_regs_space
= regs_saved
;
4426 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
4427 return total_saved_regs_space
+ total_auto_space
;
4429 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
4430 return total_saved_regs_space
+ total_auto_space
;
4432 /* Initial gap between fp and sp is 0. */
4433 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
4436 if (from
== RETURN_ADDRESS_POINTER_REGNUM
4437 && (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
))
4439 int i
, n
= total_saved_regs_space
;
4440 for (i
= PR_REG
-1; i
>= 0; i
--)
4441 if (live_regs_mask
& (1 << i
))
4443 return n
+ total_auto_space
;
4449 /* Handle machine specific pragmas to be semi-compatible with Hitachi
4453 sh_pr_interrupt (pfile
)
4454 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
4456 pragma_interrupt
= 1;
4461 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
4463 pragma_interrupt
= pragma_trapa
= 1;
4467 sh_pr_nosave_low_regs (pfile
)
4468 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
4470 pragma_nosave_low_regs
= 1;
4473 /* Generate 'handle_interrupt' attribute for decls */
4476 sh_pragma_insert_attributes (node
, attributes
, prefix
)
4479 tree
* prefix ATTRIBUTE_UNUSED
;
4481 if (! pragma_interrupt
4482 || TREE_CODE (node
) != FUNCTION_DECL
)
4485 /* We are only interested in fields. */
4486 if (TREE_CODE_CLASS (TREE_CODE (node
)) != 'd')
4489 /* Add a 'handle_interrupt' attribute. */
4490 * attributes
= tree_cons (get_identifier ("interrupt_handler"), NULL
, * attributes
);
4495 /* Return nonzero if ATTR is a valid attribute for DECL.
4496 ATTRIBUTES are any existing attributes and ARGS are the arguments
4499 Supported attributes:
4501 interrupt_handler -- specifies this function is an interrupt handler.
4503 sp_switch -- specifies an alternate stack for an interrupt handler
4506 trap_exit -- use a trapa to exit an interrupt function instead of
4507 an rte instruction. */
4510 sh_valid_machine_decl_attribute (decl
, attributes
, attr
, args
)
4512 tree attributes ATTRIBUTE_UNUSED
;
4516 if (TREE_CODE (decl
) != FUNCTION_DECL
)
4519 if (is_attribute_p ("interrupt_handler", attr
))
4524 if (is_attribute_p ("sp_switch", attr
))
4526 /* The sp_switch attribute only has meaning for interrupt functions. */
4527 if (!pragma_interrupt
)
4530 /* sp_switch must have an argument. */
4531 if (!args
|| TREE_CODE (args
) != TREE_LIST
)
4534 /* The argument must be a constant string. */
4535 if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
4538 sp_switch
= gen_rtx_SYMBOL_REF (VOIDmode
,
4539 TREE_STRING_POINTER (TREE_VALUE (args
)));
4543 if (is_attribute_p ("trap_exit", attr
))
4545 /* The trap_exit attribute only has meaning for interrupt functions. */
4546 if (!pragma_interrupt
)
4549 /* trap_exit must have an argument. */
4550 if (!args
|| TREE_CODE (args
) != TREE_LIST
)
4553 /* The argument must be a constant integer. */
4554 if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
4557 trap_exit
= TREE_INT_CST_LOW (TREE_VALUE (args
));
4565 /* Predicates used by the templates. */
4567 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
4568 Used only in general_movsrc_operand. */
4571 system_reg_operand (op
, mode
)
4573 enum machine_mode mode ATTRIBUTE_UNUSED
;
4585 /* Returns 1 if OP can be source of a simple move operation.
4586 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
4587 invalid as are subregs of system registers. */
4590 general_movsrc_operand (op
, mode
)
4592 enum machine_mode mode
;
4594 if (GET_CODE (op
) == MEM
)
4596 rtx inside
= XEXP (op
, 0);
4597 if (GET_CODE (inside
) == CONST
)
4598 inside
= XEXP (inside
, 0);
4600 if (GET_CODE (inside
) == LABEL_REF
)
4603 if (GET_CODE (inside
) == PLUS
4604 && GET_CODE (XEXP (inside
, 0)) == LABEL_REF
4605 && GET_CODE (XEXP (inside
, 1)) == CONST_INT
)
4608 /* Only post inc allowed. */
4609 if (GET_CODE (inside
) == PRE_DEC
)
4613 if ((mode
== QImode
|| mode
== HImode
)
4614 && (GET_CODE (op
) == SUBREG
4615 && GET_CODE (XEXP (op
, 0)) == REG
4616 && system_reg_operand (XEXP (op
, 0), mode
)))
4619 return general_operand (op
, mode
);
4622 /* Returns 1 if OP can be a destination of a move.
4623 Same as general_operand, but no preinc allowed. */
4626 general_movdst_operand (op
, mode
)
4628 enum machine_mode mode
;
4630 /* Only pre dec allowed. */
4631 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
4634 return general_operand (op
, mode
);
4637 /* Returns 1 if OP is a normal arithmetic register. */
4640 arith_reg_operand (op
, mode
)
4642 enum machine_mode mode
;
4644 if (register_operand (op
, mode
))
4648 if (GET_CODE (op
) == REG
)
4650 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
4651 regno
= REGNO (SUBREG_REG (op
));
4655 return (regno
!= T_REG
&& regno
!= PR_REG
4656 && (regno
!= FPUL_REG
|| TARGET_SH4
)
4657 && regno
!= MACH_REG
&& regno
!= MACL_REG
);
4663 fp_arith_reg_operand (op
, mode
)
4665 enum machine_mode mode
;
4667 if (register_operand (op
, mode
))
4671 if (GET_CODE (op
) == REG
)
4673 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
4674 regno
= REGNO (SUBREG_REG (op
));
4678 return (regno
>= FIRST_PSEUDO_REGISTER
4679 || FP_REGISTER_P (regno
));
4684 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
4687 arith_operand (op
, mode
)
4689 enum machine_mode mode
;
4691 if (arith_reg_operand (op
, mode
))
4694 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
4700 /* Returns 1 if OP is a valid source operand for a compare insn. */
4703 arith_reg_or_0_operand (op
, mode
)
4705 enum machine_mode mode
;
4707 if (arith_reg_operand (op
, mode
))
4710 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_N (INTVAL (op
)))
4716 /* Returns 1 if OP is a valid source operand for a logical operation. */
4719 logical_operand (op
, mode
)
4721 enum machine_mode mode
;
4723 if (arith_reg_operand (op
, mode
))
4726 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
4732 /* Nonzero if OP is a floating point value with value 0.0. */
4735 fp_zero_operand (op
)
4740 if (GET_MODE (op
) != SFmode
)
4743 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4744 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
4747 /* Nonzero if OP is a floating point value with value 1.0. */
4755 if (GET_MODE (op
) != SFmode
)
4758 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4759 return REAL_VALUES_EQUAL (r
, dconst1
);
4762 /* For -m4 and -m4-single-only, mode switching is used. If we are
4763 compiling without -mfmovd, movsf_ie isn't taken into account for
4764 mode switching. We could check in machine_dependent_reorg for
4765 cases where we know we are in single precision mode, but there is
4766 interface to find that out during reload, so we must avoid
4767 choosing an fldi alternative during reload and thus failing to
4768 allocate a scratch register for the constant loading. */
4772 return ! TARGET_SH4
|| TARGET_FMOVD
|| reload_completed
;
4776 tertiary_reload_operand (op
, mode
)
4778 enum machine_mode mode ATTRIBUTE_UNUSED
;
4780 enum rtx_code code
= GET_CODE (op
);
4781 return code
== MEM
|| (TARGET_SH4
&& code
== CONST_DOUBLE
);
4785 fpscr_operand (op
, mode
)
4787 enum machine_mode mode ATTRIBUTE_UNUSED
;
4789 return (GET_CODE (op
) == REG
&& REGNO (op
) == FPSCR_REG
4790 && GET_MODE (op
) == PSImode
);
4794 fpul_operand (op
, mode
)
4796 enum machine_mode mode
;
4798 return (GET_CODE (op
) == REG
4799 && (REGNO (op
) == FPUL_REG
|| REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
4800 && GET_MODE (op
) == mode
);
4804 symbol_ref_operand (op
, mode
)
4806 enum machine_mode mode ATTRIBUTE_UNUSED
;
4808 return (GET_CODE (op
) == SYMBOL_REF
);
4812 commutative_float_operator (op
, mode
)
4814 enum machine_mode mode
;
4816 if (GET_MODE (op
) != mode
)
4818 switch (GET_CODE (op
))
4830 noncommutative_float_operator (op
, mode
)
4832 enum machine_mode mode
;
4834 if (GET_MODE (op
) != mode
)
4836 switch (GET_CODE (op
))
4848 binary_float_operator (op
, mode
)
4850 enum machine_mode mode
;
4852 if (GET_MODE (op
) != mode
)
4854 switch (GET_CODE (op
))
4867 /* Return the destination address of a branch. */
4870 branch_dest (branch
)
4873 rtx dest
= SET_SRC (PATTERN (branch
));
4876 if (GET_CODE (dest
) == IF_THEN_ELSE
)
4877 dest
= XEXP (dest
, 1);
4878 dest
= XEXP (dest
, 0);
4879 dest_uid
= INSN_UID (dest
);
4880 return INSN_ADDRESSES (dest_uid
);
4883 /* Return non-zero if REG is not used after INSN.
4884 We assume REG is a reload reg, and therefore does
4885 not live past labels. It may live past calls or jumps though. */
4887 reg_unused_after (reg
, insn
)
4894 /* If the reg is set by this instruction, then it is safe for our
4895 case. Disregard the case where this is a store to memory, since
4896 we are checking a register used in the store address. */
4897 set
= single_set (insn
);
4898 if (set
&& GET_CODE (SET_DEST (set
)) != MEM
4899 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
4902 while ((insn
= NEXT_INSN (insn
)))
4904 code
= GET_CODE (insn
);
4907 /* If this is a label that existed before reload, then the register
4908 if dead here. However, if this is a label added by reorg, then
4909 the register may still be live here. We can't tell the difference,
4910 so we just ignore labels completely. */
4911 if (code
== CODE_LABEL
)
4916 if (code
== JUMP_INSN
)
4919 /* If this is a sequence, we must handle them all at once.
4920 We could have for instance a call that sets the target register,
4921 and a insn in a delay slot that uses the register. In this case,
4922 we must return 0. */
4923 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
4928 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
4930 rtx this_insn
= XVECEXP (PATTERN (insn
), 0, i
);
4931 rtx set
= single_set (this_insn
);
4933 if (GET_CODE (this_insn
) == CALL_INSN
)
4935 else if (GET_CODE (this_insn
) == JUMP_INSN
)
4937 if (INSN_ANNULLED_BRANCH_P (this_insn
))
4942 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
4944 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
4946 if (GET_CODE (SET_DEST (set
)) != MEM
)
4952 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
4957 else if (code
== JUMP_INSN
)
4960 else if (GET_RTX_CLASS (code
) == 'i')
4962 rtx set
= single_set (insn
);
4964 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
4966 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
4967 return GET_CODE (SET_DEST (set
)) != MEM
;
4968 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
4972 if (code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
4978 extern struct obstack permanent_obstack
;
4983 static rtx fpscr_rtx
;
4987 fpscr_rtx
= gen_rtx (REG
, PSImode
, FPSCR_REG
);
4988 REG_USERVAR_P (fpscr_rtx
) = 1;
4989 ggc_add_rtx_root (&fpscr_rtx
, 1);
4990 mark_user_reg (fpscr_rtx
);
4992 if (! reload_completed
|| mdep_reorg_phase
!= SH_AFTER_MDEP_REORG
)
4993 mark_user_reg (fpscr_rtx
);
5012 expand_sf_unop (fun
, operands
)
5013 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
5016 emit_sf_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
5020 expand_sf_binop (fun
, operands
)
5021 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
5024 emit_sf_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
5029 expand_df_unop (fun
, operands
)
5030 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
5033 emit_df_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
5037 expand_df_binop (fun
, operands
)
5038 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
5041 emit_df_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
5045 /* ??? gcc does flow analysis strictly after common subexpression
5046 elimination. As a result, common subespression elimination fails
5047 when there are some intervening statements setting the same register.
5048 If we did nothing about this, this would hurt the precision switching
5049 for SH4 badly. There is some cse after reload, but it is unable to
5050 undo the extra register pressure from the unused instructions, and
5051 it cannot remove auto-increment loads.
5053 A C code example that shows this flow/cse weakness for (at least) SH
5054 and sparc (as of gcc ss-970706) is this:
5068 So we add another pass before common subexpression elimination, to
5069 remove assignments that are dead due to a following assignment in the
5070 same basic block. */
5073 mark_use (x
, reg_set_block
)
5074 rtx x
, *reg_set_block
;
5080 code
= GET_CODE (x
);
5085 int regno
= REGNO (x
);
5086 int nregs
= (regno
< FIRST_PSEUDO_REGISTER
5087 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
))
5091 reg_set_block
[regno
+ nregs
- 1] = 0;
5098 rtx dest
= SET_DEST (x
);
5100 if (GET_CODE (dest
) == SUBREG
)
5101 dest
= SUBREG_REG (dest
);
5102 if (GET_CODE (dest
) != REG
)
5103 mark_use (dest
, reg_set_block
);
5104 mark_use (SET_SRC (x
), reg_set_block
);
5111 const char *fmt
= GET_RTX_FORMAT (code
);
5113 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5116 mark_use (XEXP (x
, i
), reg_set_block
);
5117 else if (fmt
[i
] == 'E')
5118 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5119 mark_use (XVECEXP (x
, i
, j
), reg_set_block
);
5126 static rtx get_free_reg
PARAMS ((HARD_REG_SET
));
5128 /* This function returns a register to use to load the address to load
5129 the fpscr from. Currently it always returns r1 or r7, but when we are
5130 able to use pseudo registers after combine, or have a better mechanism
5131 for choosing a register, it should be done here. */
5132 /* REGS_LIVE is the liveness information for the point for which we
5133 need this allocation. In some bare-bones exit blocks, r1 is live at the
5134 start. We can even have all of r0..r3 being live:
5135 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
5136 INSN before which new insns are placed with will clobber the register
5137 we return. If a basic block consists only of setting the return value
5138 register to a pseudo and using that register, the return value is not
5139 live before or after this block, yet we we'll insert our insns right in
5143 get_free_reg (regs_live
)
5144 HARD_REG_SET regs_live
;
5148 if (! TEST_HARD_REG_BIT (regs_live
, 1))
5149 return gen_rtx_REG (Pmode
, 1);
5151 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
5152 there shouldn't be anything but a jump before the function end. */
5153 if (! TEST_HARD_REG_BIT (regs_live
, 7))
5154 return gen_rtx_REG (Pmode
, 7);
5159 /* This function will set the fpscr from memory.
5160 MODE is the mode we are setting it to. */
5162 fpscr_set_from_mem (mode
, regs_live
)
5164 HARD_REG_SET regs_live
;
5166 enum attr_fp_mode fp_mode
= mode
;
5167 rtx addr_reg
= get_free_reg (regs_live
);
5169 emit_insn ((fp_mode
== (TARGET_FPU_SINGLE
? FP_MODE_SINGLE
: FP_MODE_DOUBLE
)
5170 ? gen_fpu_switch1
: gen_fpu_switch0
) (addr_reg
));
5173 /* Is the given character a logical line separator for the assembler? */
5174 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
5175 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
5179 sh_insn_length_adjustment (insn
)
5182 /* Instructions with unfilled delay slots take up an extra two bytes for
5183 the nop in the delay slot. */
5184 if (((GET_CODE (insn
) == INSN
5185 && GET_CODE (PATTERN (insn
)) != USE
5186 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
5187 || GET_CODE (insn
) == CALL_INSN
5188 || (GET_CODE (insn
) == JUMP_INSN
5189 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
5190 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
))
5191 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
5192 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
5195 /* sh-dsp parallel processing insn take four bytes instead of two. */
5197 if (GET_CODE (insn
) == INSN
)
5200 rtx body
= PATTERN (insn
);
5201 const char *template;
5203 int maybe_label
= 1;
5205 if (GET_CODE (body
) == ASM_INPUT
)
5206 template = XSTR (body
, 0);
5207 else if (asm_noperands (body
) >= 0)
5209 = decode_asm_operands (body
, NULL_PTR
, NULL_PTR
, NULL_PTR
, NULL_PTR
);
5218 while (c
== ' ' || c
== '\t');
5219 /* all sh-dsp parallel-processing insns start with p.
5220 The only non-ppi sh insn starting with p is pref.
5221 The only ppi starting with pr is prnd. */
5222 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", template, 2))
5224 /* The repeat pseudo-insn expands two three insns, a total of
5225 six bytes in size. */
5226 else if ((c
== 'r' || c
== 'R')
5227 && ! strncasecmp ("epeat", template, 5))
5229 while (c
&& c
!= '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
))
5231 /* If this is a label, it is obviously not a ppi insn. */
5232 if (c
== ':' && maybe_label
)
5237 else if (c
== '\'' || c
== '"')
5242 maybe_label
= c
!= ':';
5250 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
5251 isn't protected by a PIC unspec. */
5253 nonpic_symbol_mentioned_p (x
)
5256 register const char *fmt
;
5259 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
5262 if (GET_CODE (x
) == UNSPEC
5263 && (XINT (x
, 1) == UNSPEC_PIC
5264 || XINT (x
, 1) == UNSPEC_GOT
5265 || XINT (x
, 1) == UNSPEC_GOTOFF
5266 || XINT (x
, 1) == UNSPEC_PLT
))
5269 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5270 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5276 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5277 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5280 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
5287 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
5288 @GOTOFF in `reg'. */
5290 legitimize_pic_address (orig
, mode
, reg
)
5292 enum machine_mode mode
;
5295 if (GET_CODE (orig
) == LABEL_REF
5296 || (GET_CODE (orig
) == SYMBOL_REF
5297 && (CONSTANT_POOL_ADDRESS_P (orig
)
5298 /* SYMBOL_REF_FLAG is set on static symbols. */
5299 || SYMBOL_REF_FLAG (orig
))))
5302 reg
= gen_reg_rtx (Pmode
);
5304 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
5307 else if (GET_CODE (orig
) == SYMBOL_REF
)
5310 reg
= gen_reg_rtx (Pmode
);
5312 emit_insn (gen_symGOT2reg (reg
, orig
));