1 /* Output routines for GCC for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
34 #include "hard-reg-set.h"
36 #include "insn-attr.h"
40 #include "integrate.h"
43 #include "target-def.h"
45 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
47 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
48 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
50 /* These are some macros to abstract register modes. */
51 #define CONST_OK_FOR_ADD(size) \
52 (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size))
53 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
54 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
55 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
57 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
58 int current_function_interrupt
;
60 /* ??? The pragma interrupt support will not work for SH3. */
61 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
62 output code for the next function appropriate for an interrupt handler. */
65 /* This is set by the trap_exit attribute for functions. It specifies
66 a trap number to be used in a trapa instruction at function exit
67 (instead of an rte instruction). */
70 /* This is used by the sp_switch attribute for functions. It specifies
71 a variable holding the address of the stack the interrupt function
72 should switch to/from at entry/exit. */
75 /* This is set by #pragma trapa, and is similar to the above, except that
76 the compiler doesn't emit code to preserve all registers. */
77 static int pragma_trapa
;
79 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
80 which has a separate set of low regs for User and Supervisor modes.
81 This should only be used for the lowest level of interrupts. Higher levels
82 of interrupts must save the registers in case they themselves are
84 int pragma_nosave_low_regs
;
86 /* This is used for communication between SETUP_INCOMING_VARARGS and
87 sh_expand_prologue. */
88 int current_function_anonymous_args
;
90 /* Global variables for machine-dependent things. */
92 /* Which cpu are we scheduling for. */
93 enum processor_type sh_cpu
;
95 /* Saved operands from the last compare to use when we generate an scc
101 /* Provides the class number of the smallest class containing
104 int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
106 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
107 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
108 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
109 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
110 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
111 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
112 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
113 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
114 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
115 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
116 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
117 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
118 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
119 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
120 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
121 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
122 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
123 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
124 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
125 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
126 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
127 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
128 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
129 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
130 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
131 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
132 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
133 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
134 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
135 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
136 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
137 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
138 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
139 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
140 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
141 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
142 NO_REGS
, GENERAL_REGS
, PR_REGS
, T_REGS
,
143 MAC_REGS
, MAC_REGS
, FPUL_REGS
, FPSCR_REGS
,
147 char sh_register_names
[FIRST_PSEUDO_REGISTER
] \
148 [MAX_REGISTER_NAME_LENGTH
+ 1] = SH_REGISTER_NAMES_INITIALIZER
;
150 char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
151 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1]
152 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER
;
154 /* Provide reg_class from a letter such as appears in the machine
157 const enum reg_class reg_class_from_letter
[] =
159 /* a */ ALL_REGS
, /* b */ TARGET_REGS
, /* c */ FPSCR_REGS
, /* d */ DF_REGS
,
160 /* e */ NO_REGS
, /* f */ FP_REGS
, /* g */ NO_REGS
, /* h */ NO_REGS
,
161 /* i */ NO_REGS
, /* j */ NO_REGS
, /* k */ SIBCALL_REGS
, /* l */ PR_REGS
,
162 /* m */ NO_REGS
, /* n */ NO_REGS
, /* o */ NO_REGS
, /* p */ NO_REGS
,
163 /* q */ NO_REGS
, /* r */ NO_REGS
, /* s */ NO_REGS
, /* t */ T_REGS
,
164 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ FP0_REGS
, /* x */ MAC_REGS
,
165 /* y */ FPUL_REGS
, /* z */ R0_REGS
168 int assembler_dialect
;
170 static void split_branches
PARAMS ((rtx
));
171 static int branch_dest
PARAMS ((rtx
));
172 static void force_into
PARAMS ((rtx
, rtx
));
173 static void print_slot
PARAMS ((rtx
));
174 static rtx add_constant
PARAMS ((rtx
, enum machine_mode
, rtx
));
175 static void dump_table
PARAMS ((rtx
));
176 static int hi_const
PARAMS ((rtx
));
177 static int broken_move
PARAMS ((rtx
));
178 static int mova_p
PARAMS ((rtx
));
179 static rtx find_barrier
PARAMS ((int, rtx
, rtx
));
180 static int noncall_uses_reg
PARAMS ((rtx
, rtx
, rtx
*));
181 static rtx gen_block_redirect
PARAMS ((rtx
, int, int));
182 static void output_stack_adjust
PARAMS ((int, rtx
, int));
183 static void push
PARAMS ((int));
184 static void pop
PARAMS ((int));
185 static void push_regs
PARAMS ((HOST_WIDE_INT
*));
186 static void calc_live_regs
PARAMS ((int *, HOST_WIDE_INT
*));
187 static void mark_use
PARAMS ((rtx
, rtx
*));
188 static HOST_WIDE_INT rounded_frame_size
PARAMS ((int));
189 static rtx mark_constant_pool_use
PARAMS ((rtx
));
190 const struct attribute_spec sh_attribute_table
[];
191 static tree sh_handle_interrupt_handler_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
192 static tree sh_handle_sp_switch_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
193 static tree sh_handle_trap_exit_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
194 static void sh_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
195 static void sh_insert_attributes
PARAMS ((tree
, tree
*));
196 #ifndef OBJECT_FORMAT_ELF
197 static void sh_asm_named_section
PARAMS ((const char *, unsigned int));
199 static int sh_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
200 static int sh_use_dfa_interface
PARAMS ((void));
201 static int sh_issue_rate
PARAMS ((void));
203 static bool sh_cannot_modify_jumps_p
PARAMS ((void));
204 static bool sh_ms_bitfield_layout_p
PARAMS ((tree
));
206 static void sh_encode_section_info
PARAMS ((tree
, int));
207 static const char *sh_strip_name_encoding
PARAMS ((const char *));
209 /* Initialize the GCC target structure. */
210 #undef TARGET_ATTRIBUTE_TABLE
211 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
213 /* The next two are used for debug info when compiling with -gdwarf. */
214 #undef TARGET_ASM_UNALIGNED_HI_OP
215 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
216 #undef TARGET_ASM_UNALIGNED_SI_OP
217 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
219 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
220 #undef TARGET_ASM_UNALIGNED_DI_OP
221 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
222 #undef TARGET_ASM_ALIGNED_DI_OP
223 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
225 #undef TARGET_ASM_FUNCTION_EPILOGUE
226 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
228 #undef TARGET_INSERT_ATTRIBUTES
229 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
231 #undef TARGET_SCHED_ADJUST_COST
232 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
234 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
235 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
237 #undef TARGET_SCHED_ISSUE_RATE
238 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
240 #undef TARGET_CANNOT_MODIFY_JUMPS_P
241 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
243 #undef TARGET_MS_BITFIELD_LAYOUT_P
244 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
246 #undef TARGET_ENCODE_SECTION_INFO
247 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
248 #undef TARGET_STRIP_NAME_ENCODING
249 #define TARGET_STRIP_NAME_ENCODING sh_strip_name_encoding
251 struct gcc_target targetm
= TARGET_INITIALIZER
;
253 /* Print the operand address in x to the stream. */
256 print_operand_address (stream
, x
)
260 switch (GET_CODE (x
))
264 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
269 rtx base
= XEXP (x
, 0);
270 rtx index
= XEXP (x
, 1);
272 switch (GET_CODE (index
))
275 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
276 reg_names
[true_regnum (base
)]);
282 int base_num
= true_regnum (base
);
283 int index_num
= true_regnum (index
);
285 fprintf (stream
, "@(r0,%s)",
286 reg_names
[MAX (base_num
, index_num
)]);
298 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
302 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
306 x
= mark_constant_pool_use (x
);
307 output_addr_const (stream
, x
);
312 /* Print operand x (an rtx) in assembler syntax to file stream
313 according to modifier code.
315 '.' print a .s if insn needs delay slot
316 ',' print LOCAL_LABEL_PREFIX
317 '@' print trap, rte or rts depending upon pragma interruptness
318 '#' output a nop if there is nothing to put in the delay slot
319 'O' print a constant without the #
320 'R' print the LSW of a dp value - changes if in little endian
321 'S' print the MSW of a dp value - changes if in little endian
322 'T' print the next word of a dp value - same as 'R' in big endian mode.
323 'M' print an `x' if `m' will print `base,index'.
324 'm' print a pair `base,offset' or `base,index', for LD and ST.
325 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
326 'o' output an operator. */
329 print_operand (stream
, x
, code
)
338 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
339 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
342 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
346 int interrupt_handler
;
348 if ((lookup_attribute
349 ("interrupt_handler",
350 DECL_ATTRIBUTES (current_function_decl
)))
352 interrupt_handler
= 1;
354 interrupt_handler
= 0;
357 fprintf (stream
, "trapa #%d", trap_exit
);
358 else if (interrupt_handler
)
359 fprintf (stream
, "rte");
361 fprintf (stream
, "rts");
365 /* Output a nop if there's nothing in the delay slot. */
366 if (dbr_sequence_length () == 0)
367 fprintf (stream
, "\n\tnop");
370 x
= mark_constant_pool_use (x
);
371 output_addr_const (stream
, x
);
374 fputs (reg_names
[REGNO (x
) + LSW
], (stream
));
377 fputs (reg_names
[REGNO (x
) + MSW
], (stream
));
380 /* Next word of a double. */
381 switch (GET_CODE (x
))
384 fputs (reg_names
[REGNO (x
) + 1], (stream
));
387 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
388 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
389 x
= adjust_address (x
, SImode
, 4);
390 print_operand_address (stream
, XEXP (x
, 0));
397 switch (GET_CODE (x
))
399 case PLUS
: fputs ("add", stream
); break;
400 case MINUS
: fputs ("sub", stream
); break;
401 case MULT
: fputs ("mul", stream
); break;
402 case DIV
: fputs ("div", stream
); break;
408 if (GET_CODE (x
) == MEM
409 && GET_CODE (XEXP (x
, 0)) == PLUS
410 && (GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
411 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == SUBREG
))
416 if (GET_CODE (x
) != MEM
)
419 switch (GET_CODE (x
))
423 print_operand (stream
, x
, 0);
424 fputs (", 0", stream
);
428 print_operand (stream
, XEXP (x
, 0), 0);
429 fputs (", ", stream
);
430 print_operand (stream
, XEXP (x
, 1), 0);
439 if (GET_CODE (x
) == CONST_INT
)
441 fprintf ((stream
), "%u", (unsigned) INTVAL (x
) & (0x10000 - 1));
447 switch (GET_CODE (x
))
449 /* FIXME: We need this on SHmedia32 because reload generates
450 some sign-extended HI or QI loads into DImode registers
451 but, because Pmode is SImode, the address ends up with a
452 subreg:SI of the DImode register. Maybe reload should be
453 fixed so as to apply alter_subreg to such loads? */
455 if (SUBREG_BYTE (x
) != 0
456 || GET_CODE (SUBREG_REG (x
)) != REG
)
463 if (FP_REGISTER_P (REGNO (x
))
464 && GET_MODE (x
) == V16SFmode
)
465 fprintf ((stream
), "mtrx%s", reg_names
[REGNO (x
)] + 2);
466 else if (FP_REGISTER_P (REGNO (x
))
467 && GET_MODE (x
) == V4SFmode
)
468 fprintf ((stream
), "fv%s", reg_names
[REGNO (x
)] + 2);
469 else if (GET_CODE (x
) == REG
470 && GET_MODE (x
) == V2SFmode
)
471 fprintf ((stream
), "fp%s", reg_names
[REGNO (x
)] + 2);
472 else if (FP_REGISTER_P (REGNO (x
))
473 && GET_MODE_SIZE (GET_MODE (x
)) > 4)
474 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)] + 1);
476 fputs (reg_names
[REGNO (x
)], (stream
));
480 output_address (XEXP (x
, 0));
485 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
486 && GET_MODE (XEXP (x
, 0)) == DImode
487 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == TRUNCATE
488 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
)
490 rtx val
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
493 if (GET_CODE (val
) == ASHIFTRT
)
496 if (GET_CODE (XEXP (val
, 0)) == CONST
)
498 output_addr_const (stream
, XEXP (val
, 0));
499 if (GET_CODE (XEXP (val
, 0)) == CONST
)
501 fputs (" >> ", stream
);
502 output_addr_const (stream
, XEXP (val
, 1));
507 if (GET_CODE (val
) == CONST
)
509 output_addr_const (stream
, val
);
510 if (GET_CODE (val
) == CONST
)
513 fputs (" & 65535)", stream
);
521 output_addr_const (stream
, x
);
528 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
530 force_into (value
, target
)
533 value
= force_operand (value
, target
);
534 if (! rtx_equal_p (value
, target
))
535 emit_insn (gen_move_insn (target
, value
));
538 /* Emit code to perform a block move. Choose the best method.
540 OPERANDS[0] is the destination.
541 OPERANDS[1] is the source.
542 OPERANDS[2] is the size.
543 OPERANDS[3] is the alignment safe to use. */
546 expand_block_move (operands
)
549 int align
= INTVAL (operands
[3]);
550 int constp
= (GET_CODE (operands
[2]) == CONST_INT
);
551 int bytes
= (constp
? INTVAL (operands
[2]) : 0);
553 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
554 alignment, or if it isn't a multiple of 4 bytes, then fail. */
555 if (! constp
|| align
< 4 || (bytes
% 4 != 0))
562 else if (bytes
== 12)
567 rtx r4
= gen_rtx (REG
, SImode
, 4);
568 rtx r5
= gen_rtx (REG
, SImode
, 5);
570 entry_name
= get_identifier ("__movstrSI12_i4");
572 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
573 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
574 force_into (XEXP (operands
[0], 0), r4
);
575 force_into (XEXP (operands
[1], 0), r5
);
576 emit_insn (gen_block_move_real_i4 (func_addr_rtx
));
579 else if (! TARGET_SMALLCODE
)
585 rtx r4
= gen_rtx (REG
, SImode
, 4);
586 rtx r5
= gen_rtx (REG
, SImode
, 5);
587 rtx r6
= gen_rtx (REG
, SImode
, 6);
589 entry_name
= get_identifier (bytes
& 4
591 : "__movstr_i4_even");
592 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
593 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
594 force_into (XEXP (operands
[0], 0), r4
);
595 force_into (XEXP (operands
[1], 0), r5
);
598 emit_insn (gen_move_insn (r6
, GEN_INT (dwords
- 1)));
599 emit_insn (gen_block_lump_real_i4 (func_addr_rtx
));
611 rtx r4
= gen_rtx_REG (SImode
, 4);
612 rtx r5
= gen_rtx_REG (SImode
, 5);
614 sprintf (entry
, "__movstrSI%d", bytes
);
615 entry_name
= get_identifier (entry
);
616 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
617 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
618 force_into (XEXP (operands
[0], 0), r4
);
619 force_into (XEXP (operands
[1], 0), r5
);
620 emit_insn (gen_block_move_real (func_addr_rtx
));
624 /* This is the same number of bytes as a memcpy call, but to a different
625 less common function name, so this will occasionally use more space. */
626 if (! TARGET_SMALLCODE
)
631 int final_switch
, while_loop
;
632 rtx r4
= gen_rtx_REG (SImode
, 4);
633 rtx r5
= gen_rtx_REG (SImode
, 5);
634 rtx r6
= gen_rtx_REG (SImode
, 6);
636 entry_name
= get_identifier ("__movstr");
637 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
638 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
639 force_into (XEXP (operands
[0], 0), r4
);
640 force_into (XEXP (operands
[1], 0), r5
);
642 /* r6 controls the size of the move. 16 is decremented from it
643 for each 64 bytes moved. Then the negative bit left over is used
644 as an index into a list of move instructions. e.g., a 72 byte move
645 would be set up with size(r6) = 14, for one iteration through the
646 big while loop, and a switch of -2 for the last part. */
648 final_switch
= 16 - ((bytes
/ 4) % 16);
649 while_loop
= ((bytes
/ 4) / 16 - 1) * 16;
650 emit_insn (gen_move_insn (r6
, GEN_INT (while_loop
+ final_switch
)));
651 emit_insn (gen_block_lump_real (func_addr_rtx
));
658 /* Prepare operands for a move define_expand; specifically, one of the
659 operands must be in a register. */
662 prepare_move_operands (operands
, mode
)
664 enum machine_mode mode
;
666 if ((mode
== SImode
|| mode
== DImode
) && flag_pic
)
669 if (SYMBOLIC_CONST_P (operands
[1]))
671 if (GET_CODE (operands
[0]) == MEM
)
672 operands
[1] = force_reg (Pmode
, operands
[1]);
673 else if (GET_CODE (operands
[1]) == LABEL_REF
674 && target_reg_operand (operands
[0], mode
))
678 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
679 operands
[1] = legitimize_pic_address (operands
[1], mode
, temp
);
682 else if (GET_CODE (operands
[1]) == CONST
683 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
684 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
686 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
687 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
689 operands
[1] = expand_binop (mode
, add_optab
, temp
,
690 XEXP (XEXP (operands
[1], 0), 1),
691 no_new_pseudos
? temp
692 : gen_reg_rtx (Pmode
),
697 if (! reload_in_progress
&& ! reload_completed
)
699 /* Copy the source to a register if both operands aren't registers. */
700 if (! register_operand (operands
[0], mode
)
701 && ! register_operand (operands
[1], mode
))
702 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
704 /* This case can happen while generating code to move the result
705 of a library call to the target. Reject `st r0,@(rX,rY)' because
706 reload will fail to find a spill register for rX, since r0 is already
707 being used for the source. */
708 else if (GET_CODE (operands
[1]) == REG
&& REGNO (operands
[1]) == 0
709 && GET_CODE (operands
[0]) == MEM
710 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
711 && GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == REG
)
712 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
718 /* Prepare the operands for an scc instruction; make sure that the
719 compare has been done. */
721 prepare_scc_operands (code
)
724 rtx t_reg
= gen_rtx_REG (SImode
, T_REG
);
725 enum rtx_code oldcode
= code
;
726 enum machine_mode mode
;
728 /* First need a compare insn. */
732 /* It isn't possible to handle this case. */
751 rtx tmp
= sh_compare_op0
;
752 sh_compare_op0
= sh_compare_op1
;
753 sh_compare_op1
= tmp
;
756 mode
= GET_MODE (sh_compare_op0
);
757 if (mode
== VOIDmode
)
758 mode
= GET_MODE (sh_compare_op1
);
760 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
761 if ((code
!= EQ
&& code
!= NE
762 && (sh_compare_op1
!= const0_rtx
763 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
764 || (mode
== DImode
&& sh_compare_op1
!= const0_rtx
)
765 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
766 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
768 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
769 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
)
770 (gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec (2,
771 gen_rtx (SET
, VOIDmode
, t_reg
,
772 gen_rtx (code
, SImode
,
773 sh_compare_op0
, sh_compare_op1
)),
774 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ()))));
776 emit_insn (gen_rtx (SET
, VOIDmode
, t_reg
,
777 gen_rtx (code
, SImode
, sh_compare_op0
,
783 /* Called from the md file, set up the operands of a compare instruction. */
786 from_compare (operands
, code
)
790 enum machine_mode mode
= GET_MODE (sh_compare_op0
);
792 if (mode
== VOIDmode
)
793 mode
= GET_MODE (sh_compare_op1
);
796 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
798 /* Force args into regs, since we can't use constants here. */
799 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
800 if (sh_compare_op1
!= const0_rtx
801 || code
== GTU
|| code
== GEU
802 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
803 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
805 if (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
&& code
== GE
)
807 from_compare (operands
, GT
);
808 insn
= gen_ieee_ccmpeqsf_t (sh_compare_op0
, sh_compare_op1
);
811 insn
= gen_rtx_SET (VOIDmode
,
812 gen_rtx_REG (SImode
, T_REG
),
813 gen_rtx (code
, SImode
, sh_compare_op0
,
815 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
817 insn
= gen_rtx (PARALLEL
, VOIDmode
,
819 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ())));
820 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
) (insn
);
826 /* Functions to output assembly code. */
828 /* Return a sequence of instructions to perform DI or DF move.
830 Since the SH cannot move a DI or DF in one instruction, we have
831 to take care when we see overlapping source and dest registers. */
834 output_movedouble (insn
, operands
, mode
)
835 rtx insn ATTRIBUTE_UNUSED
;
837 enum machine_mode mode
;
839 rtx dst
= operands
[0];
840 rtx src
= operands
[1];
842 if (GET_CODE (dst
) == MEM
843 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
844 return "mov.l %T1,%0\n\tmov.l %1,%0";
846 if (register_operand (dst
, mode
)
847 && register_operand (src
, mode
))
849 if (REGNO (src
) == MACH_REG
)
850 return "sts mach,%S0\n\tsts macl,%R0";
852 /* When mov.d r1,r2 do r2->r3 then r1->r2;
853 when mov.d r1,r0 do r1->r0 then r2->r1. */
855 if (REGNO (src
) + 1 == REGNO (dst
))
856 return "mov %T1,%T0\n\tmov %1,%0";
858 return "mov %1,%0\n\tmov %T1,%T0";
860 else if (GET_CODE (src
) == CONST_INT
)
862 if (INTVAL (src
) < 0)
863 output_asm_insn ("mov #-1,%S0", operands
);
865 output_asm_insn ("mov #0,%S0", operands
);
869 else if (GET_CODE (src
) == MEM
)
872 int dreg
= REGNO (dst
);
873 rtx inside
= XEXP (src
, 0);
875 if (GET_CODE (inside
) == REG
)
876 ptrreg
= REGNO (inside
);
877 else if (GET_CODE (inside
) == SUBREG
)
878 ptrreg
= subreg_regno (inside
);
879 else if (GET_CODE (inside
) == PLUS
)
881 ptrreg
= REGNO (XEXP (inside
, 0));
882 /* ??? A r0+REG address shouldn't be possible here, because it isn't
883 an offsettable address. Unfortunately, offsettable addresses use
884 QImode to check the offset, and a QImode offsettable address
885 requires r0 for the other operand, which is not currently
886 supported, so we can't use the 'o' constraint.
887 Thus we must check for and handle r0+REG addresses here.
888 We punt for now, since this is likely very rare. */
889 if (GET_CODE (XEXP (inside
, 1)) == REG
)
892 else if (GET_CODE (inside
) == LABEL_REF
)
893 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
894 else if (GET_CODE (inside
) == POST_INC
)
895 return "mov.l %1,%0\n\tmov.l %1,%T0";
899 /* Work out the safe way to copy. Copy into the second half first. */
901 return "mov.l %T1,%T0\n\tmov.l %1,%0";
904 return "mov.l %1,%0\n\tmov.l %T1,%T0";
907 /* Print an instruction which would have gone into a delay slot after
908 another instruction, but couldn't because the other instruction expanded
909 into a sequence where putting the slot insn at the end wouldn't work. */
915 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
, optimize
, 0, 1);
917 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
921 output_far_jump (insn
, op
)
925 struct { rtx lab
, reg
, op
; } this;
926 rtx braf_base_lab
= NULL_RTX
;
929 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
931 this.lab
= gen_label_rtx ();
935 && offset
- get_attr_length (insn
) <= 32766)
938 jump
= "mov.w %O0,%1; braf %1";
946 jump
= "mov.l %O0,%1; braf %1";
948 jump
= "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
951 jump
= "mov.l %O0,%1; jmp @%1";
953 /* If we have a scratch register available, use it. */
954 if (GET_CODE (PREV_INSN (insn
)) == INSN
955 && INSN_CODE (PREV_INSN (insn
)) == CODE_FOR_indirect_jump_scratch
)
957 this.reg
= SET_DEST (PATTERN (PREV_INSN (insn
)));
958 if (REGNO (this.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
959 jump
= "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
960 output_asm_insn (jump
, &this.lab
);
961 if (dbr_sequence_length ())
962 print_slot (final_sequence
);
964 output_asm_insn ("nop", 0);
968 /* Output the delay slot insn first if any. */
969 if (dbr_sequence_length ())
970 print_slot (final_sequence
);
972 this.reg
= gen_rtx_REG (SImode
, 13);
973 /* We must keep the stack aligned to 8-byte boundaries on SH5.
974 Fortunately, MACL is fixed and call-clobbered, and we never
975 need its value across jumps, so save r13 in it instead of in
978 output_asm_insn ("lds r13, macl", 0);
980 output_asm_insn ("mov.l r13,@-r15", 0);
981 output_asm_insn (jump
, &this.lab
);
983 output_asm_insn ("sts macl, r13", 0);
985 output_asm_insn ("mov.l @r15+,r13", 0);
987 if (far
&& flag_pic
&& TARGET_SH2
)
989 braf_base_lab
= gen_label_rtx ();
990 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
991 CODE_LABEL_NUMBER (braf_base_lab
));
994 output_asm_insn (".align 2", 0);
995 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (this.lab
));
1000 this.lab
= braf_base_lab
;
1001 output_asm_insn (".long %O2-%O0", &this.lab
);
1004 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this.lab
);
1008 /* Local label counter, used for constants in the pool and inside
1009 pattern branches. */
1011 static int lf
= 100;
1013 /* Output code for ordinary branches. */
1016 output_branch (logic
, insn
, operands
)
1021 switch (get_attr_length (insn
))
1024 /* This can happen if filling the delay slot has caused a forward
1025 branch to exceed its range (we could reverse it, but only
1026 when we know we won't overextend other branches; this should
1027 best be handled by relaxation).
1028 It can also happen when other condbranches hoist delay slot insn
1029 from their destination, thus leading to code size increase.
1030 But the branch will still be in the range -4092..+4098 bytes. */
1035 /* The call to print_slot will clobber the operands. */
1036 rtx op0
= operands
[0];
1038 /* If the instruction in the delay slot is annulled (true), then
1039 there is no delay slot where we can put it now. The only safe
1040 place for it is after the label. final will do that by default. */
1043 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
1045 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
1046 ASSEMBLER_DIALECT
? "/" : ".", label
);
1047 print_slot (final_sequence
);
1050 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
1052 output_asm_insn ("bra\t%l0", &op0
);
1053 fprintf (asm_out_file
, "\tnop\n");
1054 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file
, "LF", label
);
1058 /* When relaxing, handle this like a short branch. The linker
1059 will fix it up if it still doesn't fit after relaxation. */
1061 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
1063 /* There should be no longer branches now - that would
1064 indicate that something has destroyed the branches set
1065 up in machine_dependent_reorg. */
1071 output_branchy_insn (code
, template, insn
, operands
)
1073 const char *template;
1077 rtx next_insn
= NEXT_INSN (insn
);
1079 if (next_insn
&& GET_CODE (next_insn
) == JUMP_INSN
&& condjump_p (next_insn
))
1081 rtx src
= SET_SRC (PATTERN (next_insn
));
1082 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
1084 /* Following branch not taken */
1085 operands
[9] = gen_label_rtx ();
1086 emit_label_after (operands
[9], next_insn
);
1087 INSN_ADDRESSES_NEW (operands
[9],
1088 INSN_ADDRESSES (INSN_UID (next_insn
))
1089 + get_attr_length (next_insn
));
1094 int offset
= (branch_dest (next_insn
)
1095 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
1096 if (offset
>= -252 && offset
<= 258)
1098 if (GET_CODE (src
) == IF_THEN_ELSE
)
1100 src
= XEXP (src
, 1);
1106 operands
[9] = gen_label_rtx ();
1107 emit_label_after (operands
[9], insn
);
1108 INSN_ADDRESSES_NEW (operands
[9],
1109 INSN_ADDRESSES (INSN_UID (insn
))
1110 + get_attr_length (insn
));
1115 output_ieee_ccmpeq (insn
, operands
)
1116 rtx insn
, *operands
;
1118 return output_branchy_insn (NE
, "bt\t%l9\\;fcmp/eq\t%1,%0", insn
, operands
);
1121 /* Output to FILE the start of the assembler file. */
1124 output_file_start (file
)
1127 output_file_directive (file
, main_input_filename
);
1129 /* Switch to the data section so that the coffsem symbol
1130 isn't in the text section. */
1133 if (TARGET_LITTLE_ENDIAN
)
1134 fprintf (file
, "\t.little\n");
1136 if (TARGET_SHCOMPACT
)
1137 fprintf (file
, "\t.mode\tSHcompact\n");
1138 else if (TARGET_SHMEDIA
)
1139 fprintf (file
, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1140 TARGET_SHMEDIA64
? 64 : 32);
1143 /* Actual number of instructions used to make a shift by N. */
1144 static const char ashiftrt_insns
[] =
1145 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1147 /* Left shift and logical right shift are the same. */
1148 static const char shift_insns
[] =
1149 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1151 /* Individual shift amounts needed to get the above length sequences.
1152 One bit right shifts clobber the T bit, so when possible, put one bit
1153 shifts in the middle of the sequence, so the ends are eligible for
1154 branch delay slots. */
1155 static const short shift_amounts
[32][5] = {
1156 {0}, {1}, {2}, {2, 1},
1157 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1158 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1159 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1160 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1161 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1162 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1163 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1165 /* Likewise, but for shift amounts < 16, up to three highmost bits
1166 might be clobbered. This is typically used when combined with some
1167 kind of sign or zero extension. */
1169 static const char ext_shift_insns
[] =
1170 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1172 static const short ext_shift_amounts
[32][4] = {
1173 {0}, {1}, {2}, {2, 1},
1174 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1175 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1176 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1177 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1178 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1179 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1180 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1182 /* Assuming we have a value that has been sign-extended by at least one bit,
1183 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1184 to shift it by N without data loss, and quicker than by other means? */
1185 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1187 /* This is used in length attributes in sh.md to help compute the length
1188 of arbitrary constant shift instructions. */
1191 shift_insns_rtx (insn
)
1194 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1195 int shift_count
= INTVAL (XEXP (set_src
, 1));
1196 enum rtx_code shift_code
= GET_CODE (set_src
);
1201 return ashiftrt_insns
[shift_count
];
1204 return shift_insns
[shift_count
];
1210 /* Return the cost of a shift. */
1221 if (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
1223 if (GET_MODE (x
) == DImode
1224 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1225 && INTVAL (XEXP (x
, 1)) == 1)
1228 /* Everything else is invalid, because there is no pattern for it. */
1231 /* If shift by a non constant, then this will be expensive. */
1232 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1233 return SH_DYNAMIC_SHIFT_COST
;
1235 value
= INTVAL (XEXP (x
, 1));
1237 /* Otherwise, return the true cost in instructions. */
1238 if (GET_CODE (x
) == ASHIFTRT
)
1240 int cost
= ashiftrt_insns
[value
];
1241 /* If SH3, then we put the constant in a reg and use shad. */
1242 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
1243 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
1247 return shift_insns
[value
];
1250 /* Return the cost of an AND operation. */
1258 /* Anding with a register is a single cycle and instruction. */
1259 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1262 i
= INTVAL (XEXP (x
, 1));
1266 if ((GET_CODE (XEXP (x
, 1)) == CONST_INT
1267 && CONST_OK_FOR_J (INTVAL (XEXP (x
, 1))))
1268 || EXTRA_CONSTRAINT_S (XEXP (x
, 1)))
1274 /* These constants are single cycle extu.[bw] instructions. */
1275 if (i
== 0xff || i
== 0xffff)
1277 /* Constants that can be used in an and immediate instruction is a single
1278 cycle, but this requires r0, so make it a little more expensive. */
1279 if (CONST_OK_FOR_L (i
))
1281 /* Constants that can be loaded with a mov immediate and an and.
1282 This case is probably unnecessary. */
1283 if (CONST_OK_FOR_I (i
))
1285 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1286 This case is probably unnecessary. */
1290 /* Return the cost of an addition or a subtraction. */
1296 /* Adding a register is a single cycle insn. */
1297 if (GET_CODE (XEXP (x
, 1)) == REG
1298 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1301 /* Likewise for small constants. */
1302 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1303 && CONST_OK_FOR_ADD (INTVAL (XEXP (x
, 1))))
1307 switch (GET_CODE (XEXP (x
, 1)))
1312 return TARGET_SHMEDIA64
? 5 : 3;
1315 if (CONST_OK_FOR_J (INTVAL (XEXP (x
, 1))))
1317 else if (CONST_OK_FOR_J (INTVAL (XEXP (x
, 1)) >> 16))
1319 else if (CONST_OK_FOR_J ((INTVAL (XEXP (x
, 1)) >> 16) >> 16))
1327 /* Any other constant requires a 2 cycle pc-relative load plus an
1332 /* Return the cost of a multiply. */
1335 rtx x ATTRIBUTE_UNUSED
;
1342 /* We have a mul insn, so we can never take more than the mul and the
1343 read of the mac reg, but count more because of the latency and extra
1345 if (TARGET_SMALLCODE
)
1350 /* If we're aiming at small code, then just count the number of
1351 insns in a multiply call sequence. */
1352 if (TARGET_SMALLCODE
)
1355 /* Otherwise count all the insns in the routine we'd be calling too. */
1359 /* Code to expand a shift. */
1362 gen_ashift (type
, n
, reg
)
1367 /* Negative values here come from the shift_amounts array. */
1380 emit_insn (gen_ashrsi3_k (reg
, reg
, GEN_INT (n
)));
1384 emit_insn (gen_lshrsi3_m (reg
, reg
, GEN_INT (n
)));
1386 emit_insn (gen_lshrsi3_k (reg
, reg
, GEN_INT (n
)));
1389 emit_insn (gen_ashlsi3_std (reg
, reg
, GEN_INT (n
)));
1394 /* Same for HImode */
1397 gen_ashift_hi (type
, n
, reg
)
1402 /* Negative values here come from the shift_amounts array. */
1416 /* We don't have HImode right shift operations because using the
1417 ordinary 32 bit shift instructions for that doesn't generate proper
1418 zero/sign extension.
1419 gen_ashift_hi is only called in contexts where we know that the
1420 sign extension works out correctly. */
1423 if (GET_CODE (reg
) == SUBREG
)
1425 offset
= SUBREG_BYTE (reg
);
1426 reg
= SUBREG_REG (reg
);
1428 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
1432 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
1437 /* Output RTL to split a constant shift into its component SH constant
1438 shift instructions. */
1441 gen_shifty_op (code
, operands
)
1445 int value
= INTVAL (operands
[2]);
1448 /* Truncate the shift count in case it is out of bounds. */
1449 value
= value
& 0x1f;
1453 if (code
== LSHIFTRT
)
1455 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
1456 emit_insn (gen_movt (operands
[0]));
1459 else if (code
== ASHIFT
)
1461 /* There is a two instruction sequence for 31 bit left shifts,
1462 but it requires r0. */
1463 if (GET_CODE (operands
[0]) == REG
&& REGNO (operands
[0]) == 0)
1465 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
1466 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
1471 else if (value
== 0)
1473 /* This can happen when not optimizing. We must output something here
1474 to prevent the compiler from aborting in final.c after the try_split
1476 emit_insn (gen_nop ());
1480 max
= shift_insns
[value
];
1481 for (i
= 0; i
< max
; i
++)
1482 gen_ashift (code
, shift_amounts
[value
][i
], operands
[0]);
1485 /* Same as above, but optimized for values where the topmost bits don't
1489 gen_shifty_hi_op (code
, operands
)
1493 int value
= INTVAL (operands
[2]);
1495 void (*gen_fun
) PARAMS ((int, int, rtx
));
1497 /* This operation is used by and_shl for SImode values with a few
1498 high bits known to be cleared. */
1502 emit_insn (gen_nop ());
1506 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
1509 max
= ext_shift_insns
[value
];
1510 for (i
= 0; i
< max
; i
++)
1511 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1514 /* When shifting right, emit the shifts in reverse order, so that
1515 solitary negative values come first. */
1516 for (i
= ext_shift_insns
[value
] - 1; i
>= 0; i
--)
1517 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1520 /* Output RTL for an arithmetic right shift. */
1522 /* ??? Rewrite to use super-optimizer sequences. */
1525 expand_ashiftrt (operands
)
1536 if (GET_CODE (operands
[2]) != CONST_INT
)
1538 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
1539 emit_insn (gen_negsi2 (count
, count
));
1540 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1543 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
1544 > 1 + SH_DYNAMIC_SHIFT_COST
)
1547 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
1548 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1552 if (GET_CODE (operands
[2]) != CONST_INT
)
1555 value
= INTVAL (operands
[2]) & 31;
1559 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
1562 else if (value
>= 16 && value
<= 19)
1564 wrk
= gen_reg_rtx (SImode
);
1565 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
1568 gen_ashift (ASHIFTRT
, 1, wrk
);
1569 emit_move_insn (operands
[0], wrk
);
1572 /* Expand a short sequence inline, longer call a magic routine. */
1573 else if (value
<= 5)
1575 wrk
= gen_reg_rtx (SImode
);
1576 emit_move_insn (wrk
, operands
[1]);
1578 gen_ashift (ASHIFTRT
, 1, wrk
);
1579 emit_move_insn (operands
[0], wrk
);
1583 wrk
= gen_reg_rtx (Pmode
);
1585 /* Load the value into an arg reg and call a helper. */
1586 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
1587 sprintf (func
, "__ashiftrt_r4_%d", value
);
1588 func_name
= get_identifier (func
);
1589 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (func_name
));
1590 emit_move_insn (wrk
, sym
);
1591 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
1592 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
1597 sh_dynamicalize_shift_p (count
)
1600 return shift_insns
[INTVAL (count
)] > 1 + SH_DYNAMIC_SHIFT_COST
;
1603 /* Try to find a good way to implement the combiner pattern
1604 [(set (match_operand:SI 0 "register_operand" "r")
1605 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1606 (match_operand:SI 2 "const_int_operand" "n"))
1607 (match_operand:SI 3 "const_int_operand" "n"))) .
1608 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1609 return 0 for simple right / left or left/right shift combination.
1610 return 1 for a combination of shifts with zero_extend.
1611 return 2 for a combination of shifts with an AND that needs r0.
1612 return 3 for a combination of shifts with an AND that needs an extra
1613 scratch register, when the three highmost bits of the AND mask are clear.
1614 return 4 for a combination of shifts with an AND that needs an extra
1615 scratch register, when any of the three highmost bits of the AND mask
1617 If ATTRP is set, store an initial right shift width in ATTRP[0],
1618 and the instruction length in ATTRP[1] . These values are not valid
1620 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1621 shift_amounts for the last shift value that is to be used before the
1624 shl_and_kind (left_rtx
, mask_rtx
, attrp
)
1625 rtx left_rtx
, mask_rtx
;
1628 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
1629 int left
= INTVAL (left_rtx
), right
;
1631 int cost
, best_cost
= 10000;
1632 int best_right
= 0, best_len
= 0;
1636 if (left
< 0 || left
> 31)
1638 if (GET_CODE (mask_rtx
) == CONST_INT
)
1639 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
1641 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
1642 /* Can this be expressed as a right shift / left shift pair ? */
1643 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
1644 right
= exact_log2 (lsb
);
1645 mask2
= ~(mask
+ lsb
- 1);
1646 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
1647 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1649 best_cost
= shift_insns
[right
] + shift_insns
[right
+ left
];
1650 /* mask has no trailing zeroes <==> ! right */
1651 else if (! right
&& mask2
== ~(lsb2
- 1))
1653 int late_right
= exact_log2 (lsb2
);
1654 best_cost
= shift_insns
[left
+ late_right
] + shift_insns
[late_right
];
1656 /* Try to use zero extend */
1657 if (mask2
== ~(lsb2
- 1))
1661 for (width
= 8; width
<= 16; width
+= 8)
1663 /* Can we zero-extend right away? */
1664 if (lsb2
== (unsigned HOST_WIDE_INT
)1 << width
)
1667 = 1 + ext_shift_insns
[right
] + ext_shift_insns
[left
+ right
];
1668 if (cost
< best_cost
)
1679 /* ??? Could try to put zero extend into initial right shift,
1680 or even shift a bit left before the right shift. */
1681 /* Determine value of first part of left shift, to get to the
1682 zero extend cut-off point. */
1683 first
= width
- exact_log2 (lsb2
) + right
;
1684 if (first
>= 0 && right
+ left
- first
>= 0)
1686 cost
= ext_shift_insns
[right
] + ext_shift_insns
[first
] + 1
1687 + ext_shift_insns
[right
+ left
- first
];
1688 if (cost
< best_cost
)
1700 /* Try to use r0 AND pattern */
1701 for (i
= 0; i
<= 2; i
++)
1705 if (! CONST_OK_FOR_L (mask
>> i
))
1707 cost
= (i
!= 0) + 2 + ext_shift_insns
[left
+ i
];
1708 if (cost
< best_cost
)
1713 best_len
= cost
- 1;
1716 /* Try to use a scratch register to hold the AND operand. */
1717 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
)3 << 30)) == 0;
1718 for (i
= 0; i
<= 2; i
++)
1722 cost
= (i
!= 0) + (CONST_OK_FOR_I (mask
>> i
) ? 2 : 3)
1723 + (can_ext
? ext_shift_insns
: shift_insns
)[left
+ i
];
1724 if (cost
< best_cost
)
1729 best_len
= cost
- 1 - ! CONST_OK_FOR_I (mask
>> i
);
1735 attrp
[0] = best_right
;
1736 attrp
[1] = best_len
;
1741 /* This is used in length attributes of the unnamed instructions
1742 corresponding to shl_and_kind return values of 1 and 2. */
1744 shl_and_length (insn
)
1747 rtx set_src
, left_rtx
, mask_rtx
;
1750 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1751 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
1752 mask_rtx
= XEXP (set_src
, 1);
1753 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1754 return attributes
[1];
1757 /* This is used in length attribute of the and_shl_scratch instruction. */
1760 shl_and_scr_length (insn
)
1763 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1764 int len
= shift_insns
[INTVAL (XEXP (set_src
, 1))];
1765 rtx op
= XEXP (set_src
, 0);
1766 len
+= shift_insns
[INTVAL (XEXP (op
, 1))] + 1;
1767 op
= XEXP (XEXP (op
, 0), 0);
1768 return len
+ shift_insns
[INTVAL (XEXP (op
, 1))];
1771 /* Generating rtl? */
1772 extern int rtx_equal_function_value_matters
;
1774 /* Generate rtl for instructions for which shl_and_kind advised a particular
1775 method of generating them, i.e. returned zero. */
1778 gen_shl_and (dest
, left_rtx
, mask_rtx
, source
)
1779 rtx dest
, left_rtx
, mask_rtx
, source
;
1782 unsigned HOST_WIDE_INT mask
;
1783 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1784 int right
, total_shift
;
1785 void (*shift_gen_fun
) PARAMS ((int, rtx
*)) = gen_shifty_hi_op
;
1787 right
= attributes
[0];
1788 total_shift
= INTVAL (left_rtx
) + right
;
1789 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
1796 int first
= attributes
[2];
1801 emit_insn ((mask
<< right
) <= 0xff
1802 ? gen_zero_extendqisi2(dest
,
1803 gen_lowpart (QImode
, source
))
1804 : gen_zero_extendhisi2(dest
,
1805 gen_lowpart (HImode
, source
)));
1809 emit_insn (gen_movsi (dest
, source
));
1813 operands
[2] = GEN_INT (right
);
1814 gen_shifty_hi_op (LSHIFTRT
, operands
);
1818 operands
[2] = GEN_INT (first
);
1819 gen_shifty_hi_op (ASHIFT
, operands
);
1820 total_shift
-= first
;
1824 emit_insn (mask
<= 0xff
1825 ? gen_zero_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
1826 : gen_zero_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
1827 if (total_shift
> 0)
1829 operands
[2] = GEN_INT (total_shift
);
1830 gen_shifty_hi_op (ASHIFT
, operands
);
1835 shift_gen_fun
= gen_shifty_op
;
1837 /* If the topmost bit that matters is set, set the topmost bits
1838 that don't matter. This way, we might be able to get a shorter
1840 if (mask
& ((HOST_WIDE_INT
)1 << (31 - total_shift
)))
1841 mask
|= (HOST_WIDE_INT
)~0 << (31 - total_shift
);
1843 /* Don't expand fine-grained when combining, because that will
1844 make the pattern fail. */
1845 if (rtx_equal_function_value_matters
1846 || reload_in_progress
|| reload_completed
)
1850 /* Cases 3 and 4 should be handled by this split
1851 only while combining */
1856 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
1859 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
1864 operands
[2] = GEN_INT (total_shift
);
1865 shift_gen_fun (ASHIFT
, operands
);
1872 if (kind
!= 4 && total_shift
< 16)
1874 neg
= -ext_shift_amounts
[total_shift
][1];
1876 neg
-= ext_shift_amounts
[total_shift
][2];
1880 emit_insn (gen_and_shl_scratch (dest
, source
,
1883 GEN_INT (total_shift
+ neg
),
1885 emit_insn (gen_movsi (dest
, dest
));
1892 /* Try to find a good way to implement the combiner pattern
1893 [(set (match_operand:SI 0 "register_operand" "=r")
1894 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1895 (match_operand:SI 2 "const_int_operand" "n")
1896 (match_operand:SI 3 "const_int_operand" "n")
1898 (clobber (reg:SI T_REG))]
1899 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1900 return 0 for simple left / right shift combination.
1901 return 1 for left shift / 8 bit sign extend / left shift.
1902 return 2 for left shift / 16 bit sign extend / left shift.
1903 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1904 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1905 return 5 for left shift / 16 bit sign extend / right shift
1906 return 6 for < 8 bit sign extend / left shift.
1907 return 7 for < 8 bit sign extend / left shift / single right shift.
1908 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1911 shl_sext_kind (left_rtx
, size_rtx
, costp
)
1912 rtx left_rtx
, size_rtx
;
1915 int left
, size
, insize
, ext
;
1916 int cost
, best_cost
;
1919 left
= INTVAL (left_rtx
);
1920 size
= INTVAL (size_rtx
);
1921 insize
= size
- left
;
1924 /* Default to left / right shift. */
1926 best_cost
= shift_insns
[32 - insize
] + ashiftrt_insns
[32 - size
];
1929 /* 16 bit shift / sign extend / 16 bit shift */
1930 cost
= shift_insns
[16 - insize
] + 1 + ashiftrt_insns
[16 - size
];
1931 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1932 below, by alternative 3 or something even better. */
1933 if (cost
< best_cost
)
1939 /* Try a plain sign extend between two shifts. */
1940 for (ext
= 16; ext
>= insize
; ext
-= 8)
1944 cost
= ext_shift_insns
[ext
- insize
] + 1 + shift_insns
[size
- ext
];
1945 if (cost
< best_cost
)
1947 kind
= ext
/ (unsigned) 8;
1951 /* Check if we can do a sloppy shift with a final signed shift
1952 restoring the sign. */
1953 if (EXT_SHIFT_SIGNED (size
- ext
))
1954 cost
= ext_shift_insns
[ext
- insize
] + ext_shift_insns
[size
- ext
] + 1;
1955 /* If not, maybe it's still cheaper to do the second shift sloppy,
1956 and do a final sign extend? */
1957 else if (size
<= 16)
1958 cost
= ext_shift_insns
[ext
- insize
] + 1
1959 + ext_shift_insns
[size
> ext
? size
- ext
: ext
- size
] + 1;
1962 if (cost
< best_cost
)
1964 kind
= ext
/ (unsigned) 8 + 2;
1968 /* Check if we can sign extend in r0 */
1971 cost
= 3 + shift_insns
[left
];
1972 if (cost
< best_cost
)
1977 /* Try the same with a final signed shift. */
1980 cost
= 3 + ext_shift_insns
[left
+ 1] + 1;
1981 if (cost
< best_cost
)
1990 /* Try to use a dynamic shift. */
1991 cost
= shift_insns
[32 - insize
] + 1 + SH_DYNAMIC_SHIFT_COST
;
1992 if (cost
< best_cost
)
2003 /* Function to be used in the length attribute of the instructions
2004 implementing this pattern. */
2007 shl_sext_length (insn
)
2010 rtx set_src
, left_rtx
, size_rtx
;
2013 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
2014 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
2015 size_rtx
= XEXP (set_src
, 1);
2016 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2020 /* Generate rtl for this pattern */
2023 gen_shl_sext (dest
, left_rtx
, size_rtx
, source
)
2024 rtx dest
, left_rtx
, size_rtx
, source
;
2027 int left
, size
, insize
, cost
;
2030 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2031 left
= INTVAL (left_rtx
);
2032 size
= INTVAL (size_rtx
);
2033 insize
= size
- left
;
2041 int ext
= kind
& 1 ? 8 : 16;
2042 int shift2
= size
- ext
;
2044 /* Don't expand fine-grained when combining, because that will
2045 make the pattern fail. */
2046 if (! rtx_equal_function_value_matters
2047 && ! reload_in_progress
&& ! reload_completed
)
2049 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2050 emit_insn (gen_movsi (dest
, source
));
2054 emit_insn (gen_movsi (dest
, source
));
2058 operands
[2] = GEN_INT (ext
- insize
);
2059 gen_shifty_hi_op (ASHIFT
, operands
);
2062 ? gen_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
2063 : gen_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
2068 operands
[2] = GEN_INT (shift2
);
2069 gen_shifty_op (ASHIFT
, operands
);
2076 if (EXT_SHIFT_SIGNED (shift2
))
2078 operands
[2] = GEN_INT (shift2
+ 1);
2079 gen_shifty_op (ASHIFT
, operands
);
2080 operands
[2] = GEN_INT (1);
2081 gen_shifty_op (ASHIFTRT
, operands
);
2084 operands
[2] = GEN_INT (shift2
);
2085 gen_shifty_hi_op (ASHIFT
, operands
);
2089 operands
[2] = GEN_INT (-shift2
);
2090 gen_shifty_hi_op (LSHIFTRT
, operands
);
2092 emit_insn (size
<= 8
2093 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
2094 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2101 if (! rtx_equal_function_value_matters
2102 && ! reload_in_progress
&& ! reload_completed
)
2103 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2107 operands
[2] = GEN_INT (16 - insize
);
2108 gen_shifty_hi_op (ASHIFT
, operands
);
2109 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2111 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2113 gen_ashift (ASHIFTRT
, 1, dest
);
2118 /* Don't expand fine-grained when combining, because that will
2119 make the pattern fail. */
2120 if (! rtx_equal_function_value_matters
2121 && ! reload_in_progress
&& ! reload_completed
)
2123 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2124 emit_insn (gen_movsi (dest
, source
));
2127 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
2128 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
2129 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
2131 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
2132 gen_shifty_op (ASHIFT
, operands
);
2134 emit_insn (gen_ashrsi3_k (dest
, dest
, GEN_INT (1)));
2142 /* Prefix a symbol_ref name with "datalabel". */
2145 gen_datalabel_ref (sym
)
2148 if (GET_CODE (sym
) == LABEL_REF
)
2149 return gen_rtx_CONST (GET_MODE (sym
),
2150 gen_rtx_UNSPEC (GET_MODE (sym
),
2154 if (GET_CODE (sym
) != SYMBOL_REF
)
2157 XSTR (sym
, 0) = concat (SH_DATALABEL_ENCODING
, XSTR (sym
, 0), NULL
);
2163 /* The SH cannot load a large constant into a register, constants have to
2164 come from a pc relative load. The reference of a pc relative load
2165 instruction must be less than 1k infront of the instruction. This
2166 means that we often have to dump a constant inside a function, and
2167 generate code to branch around it.
2169 It is important to minimize this, since the branches will slow things
2170 down and make things bigger.
2172 Worst case code looks like:
2190 We fix this by performing a scan before scheduling, which notices which
2191 instructions need to have their operands fetched from the constant table
2192 and builds the table.
2196 scan, find an instruction which needs a pcrel move. Look forward, find the
2197 last barrier which is within MAX_COUNT bytes of the requirement.
2198 If there isn't one, make one. Process all the instructions between
2199 the find and the barrier.
2201 In the above example, we can tell that L3 is within 1k of L1, so
2202 the first move can be shrunk from the 3 insn+constant sequence into
2203 just 1 insn, and the constant moved to L3 to make:
2214 Then the second move becomes the target for the shortening process. */
2218 rtx value
; /* Value in table. */
2219 rtx label
; /* Label of value. */
2220 rtx wend
; /* End of window. */
2221 enum machine_mode mode
; /* Mode of value. */
2224 /* The maximum number of constants that can fit into one pool, since
2225 the pc relative range is 0...1020 bytes and constants are at least 4
2228 #define MAX_POOL_SIZE (1020/4)
2229 static pool_node pool_vector
[MAX_POOL_SIZE
];
2230 static int pool_size
;
2231 static rtx pool_window_label
;
2232 static int pool_window_last
;
2234 /* ??? If we need a constant in HImode which is the truncated value of a
2235 constant we need in SImode, we could combine the two entries thus saving
2236 two bytes. Is this common enough to be worth the effort of implementing
2239 /* ??? This stuff should be done at the same time that we shorten branches.
2240 As it is now, we must assume that all branches are the maximum size, and
2241 this causes us to almost always output constant pools sooner than
2244 /* Add a constant to the pool and return its label. */
2247 add_constant (x
, mode
, last_value
)
2249 enum machine_mode mode
;
2253 rtx lab
, new, ref
, newref
;
2255 /* First see if we've already got it. */
2256 for (i
= 0; i
< pool_size
; i
++)
2258 if (x
->code
== pool_vector
[i
].value
->code
2259 && mode
== pool_vector
[i
].mode
)
2261 if (x
->code
== CODE_LABEL
)
2263 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
2266 if (rtx_equal_p (x
, pool_vector
[i
].value
))
2271 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
2273 new = gen_label_rtx ();
2274 LABEL_REFS (new) = pool_vector
[i
].label
;
2275 pool_vector
[i
].label
= lab
= new;
2277 if (lab
&& pool_window_label
)
2279 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2280 ref
= pool_vector
[pool_window_last
].wend
;
2281 LABEL_NEXTREF (newref
) = ref
;
2282 pool_vector
[pool_window_last
].wend
= newref
;
2285 pool_window_label
= new;
2286 pool_window_last
= i
;
2292 /* Need a new one. */
2293 pool_vector
[pool_size
].value
= x
;
2294 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
2297 lab
= gen_label_rtx ();
2298 pool_vector
[pool_size
].mode
= mode
;
2299 pool_vector
[pool_size
].label
= lab
;
2300 pool_vector
[pool_size
].wend
= NULL_RTX
;
2301 if (lab
&& pool_window_label
)
2303 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2304 ref
= pool_vector
[pool_window_last
].wend
;
2305 LABEL_NEXTREF (newref
) = ref
;
2306 pool_vector
[pool_window_last
].wend
= newref
;
2309 pool_window_label
= lab
;
2310 pool_window_last
= pool_size
;
2315 /* Output the literal table. */
2326 /* Do two passes, first time dump out the HI sized constants. */
2328 for (i
= 0; i
< pool_size
; i
++)
2330 pool_node
*p
= &pool_vector
[i
];
2332 if (p
->mode
== HImode
)
2336 scan
= emit_insn_after (gen_align_2 (), scan
);
2339 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2340 scan
= emit_label_after (lab
, scan
);
2341 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
2343 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2345 lab
= XEXP (ref
, 0);
2346 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2349 else if (p
->mode
== DImode
|| p
->mode
== DFmode
)
2355 if (TARGET_SHCOMPACT
&& have_di
)
2357 rtx align_insn
= NULL_RTX
;
2359 scan
= emit_label_after (gen_label_rtx (), scan
);
2360 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2363 for (i
= 0; i
< pool_size
; i
++)
2365 pool_node
*p
= &pool_vector
[i
];
2375 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2376 emit_label_before (lab
, align_insn
);
2377 emit_insn_before (gen_consttable_4 (p
->value
, const0_rtx
),
2379 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2381 lab
= XEXP (ref
, 0);
2382 emit_insn_before (gen_consttable_window_end (lab
),
2385 delete_insn (align_insn
);
2386 align_insn
= NULL_RTX
;
2391 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2392 scan
= emit_label_after (lab
, scan
);
2393 scan
= emit_insn_after (gen_consttable_4 (p
->value
,
2395 need_align
= ! need_align
;
2402 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2406 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2407 scan
= emit_label_after (lab
, scan
);
2408 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2416 if (p
->mode
!= HImode
)
2418 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2420 lab
= XEXP (ref
, 0);
2421 scan
= emit_insn_after (gen_consttable_window_end (lab
),
2430 for (i
= 0; i
< pool_size
; i
++)
2432 pool_node
*p
= &pool_vector
[i
];
2443 scan
= emit_label_after (gen_label_rtx (), scan
);
2444 scan
= emit_insn_after (gen_align_4 (), scan
);
2446 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2447 scan
= emit_label_after (lab
, scan
);
2448 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
2456 scan
= emit_label_after (gen_label_rtx (), scan
);
2457 scan
= emit_insn_after (gen_align_4 (), scan
);
2459 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2460 scan
= emit_label_after (lab
, scan
);
2461 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2469 if (p
->mode
!= HImode
)
2471 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2473 lab
= XEXP (ref
, 0);
2474 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2479 scan
= emit_insn_after (gen_consttable_end (), scan
);
2480 scan
= emit_barrier_after (scan
);
2482 pool_window_label
= NULL_RTX
;
2483 pool_window_last
= 0;
2486 /* Return non-zero if constant would be an ok source for a
2487 mov.w instead of a mov.l. */
2493 return (GET_CODE (src
) == CONST_INT
2494 && INTVAL (src
) >= -32768
2495 && INTVAL (src
) <= 32767);
2498 /* Non-zero if the insn is a move instruction which needs to be fixed. */
2500 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2501 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2502 need to fix it if the input value is CONST_OK_FOR_I. */
2508 if (GET_CODE (insn
) == INSN
)
2510 rtx pat
= PATTERN (insn
);
2511 if (GET_CODE (pat
) == PARALLEL
)
2512 pat
= XVECEXP (pat
, 0, 0);
2513 if (GET_CODE (pat
) == SET
2514 /* We can load any 8 bit value if we don't care what the high
2515 order bits end up as. */
2516 && GET_MODE (SET_DEST (pat
)) != QImode
2517 && (CONSTANT_P (SET_SRC (pat
))
2518 /* Match mova_const. */
2519 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
2520 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
2521 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
2523 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
2524 && (fp_zero_operand (SET_SRC (pat
))
2525 || fp_one_operand (SET_SRC (pat
)))
2526 /* ??? If this is a -m4 or -m4-single compilation, in general
2527 we don't know the current setting of fpscr, so disable fldi.
2528 There is an exception if this was a register-register move
2529 before reload - and hence it was ascertained that we have
2530 single precision setting - and in a post-reload optimization
2531 we changed this to do a constant load. In that case
2532 we don't have an r0 clobber, hence we must use fldi. */
2533 && (! TARGET_SH4
|| TARGET_FMOVD
2534 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn
), 0, 2), 0))
2536 && GET_CODE (SET_DEST (pat
)) == REG
2537 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
2538 && (GET_CODE (SET_SRC (pat
)) != CONST_INT
2539 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat
)))))
2550 return (GET_CODE (insn
) == INSN
2551 && GET_CODE (PATTERN (insn
)) == SET
2552 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
2553 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
2554 /* Don't match mova_const. */
2555 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn
)), 0, 0)) == LABEL_REF
);
2558 /* Find the last barrier from insn FROM which is close enough to hold the
2559 constant pool. If we can't find one, then create one near the end of
2563 find_barrier (num_mova
, mova
, from
)
2574 int leading_mova
= num_mova
;
2575 rtx barrier_before_mova
, found_barrier
= 0, good_barrier
= 0;
2579 /* For HImode: range is 510, add 4 because pc counts from address of
2580 second instruction after this one, subtract 2 for the jump instruction
2581 that we may need to emit before the table, subtract 2 for the instruction
2582 that fills the jump delay slot (in very rare cases, reorg will take an
2583 instruction from after the constant pool or will leave the delay slot
2584 empty). This gives 510.
2585 For SImode: range is 1020, add 4 because pc counts from address of
2586 second instruction after this one, subtract 2 in case pc is 2 byte
2587 aligned, subtract 2 for the jump instruction that we may need to emit
2588 before the table, subtract 2 for the instruction that fills the jump
2589 delay slot. This gives 1018. */
2591 /* The branch will always be shortened now that the reference address for
2592 forward branches is the successor address, thus we need no longer make
2593 adjustments to the [sh]i_limit for -O0. */
2598 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
2600 int inc
= get_attr_length (from
);
2603 if (GET_CODE (from
) == CODE_LABEL
)
2606 new_align
= 1 << label_to_alignment (from
);
2607 else if (GET_CODE (prev_nonnote_insn (from
)) == BARRIER
)
2608 new_align
= 1 << barrier_align (from
);
2614 if (GET_CODE (from
) == BARRIER
)
2617 found_barrier
= from
;
2619 /* If we are at the end of the function, or in front of an alignment
2620 instruction, we need not insert an extra alignment. We prefer
2621 this kind of barrier. */
2622 if (barrier_align (from
) > 2)
2623 good_barrier
= from
;
2626 if (broken_move (from
))
2629 enum machine_mode mode
;
2631 pat
= PATTERN (from
);
2632 if (GET_CODE (pat
) == PARALLEL
)
2633 pat
= XVECEXP (pat
, 0, 0);
2634 src
= SET_SRC (pat
);
2635 dst
= SET_DEST (pat
);
2636 mode
= GET_MODE (dst
);
2638 /* We must explicitly check the mode, because sometimes the
2639 front end will generate code to load unsigned constants into
2640 HImode targets without properly sign extending them. */
2642 || (mode
== SImode
&& hi_const (src
) && REGNO (dst
) != FPUL_REG
))
2645 /* We put the short constants before the long constants, so
2646 we must count the length of short constants in the range
2647 for the long constants. */
2648 /* ??? This isn't optimal, but is easy to do. */
2653 /* We dump DF/DI constants before SF/SI ones, because
2654 the limit is the same, but the alignment requirements
2655 are higher. We may waste up to 4 additional bytes
2656 for alignment, and the DF/DI constant may have
2657 another SF/SI constant placed before it. */
2658 if (TARGET_SHCOMPACT
2660 && (mode
== DFmode
|| mode
== DImode
))
2665 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
2667 if (found_si
> count_si
)
2668 count_si
= found_si
;
2669 found_si
+= GET_MODE_SIZE (mode
);
2671 si_limit
-= GET_MODE_SIZE (mode
);
2674 /* See the code in machine_dependent_reorg, which has a similar if
2675 statement that generates a new mova insn in many cases. */
2676 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
2686 barrier_before_mova
= good_barrier
? good_barrier
: found_barrier
;
2688 if (found_si
> count_si
)
2689 count_si
= found_si
;
2691 else if (GET_CODE (from
) == JUMP_INSN
2692 && (GET_CODE (PATTERN (from
)) == ADDR_VEC
2693 || GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
))
2697 if (barrier_align (next_real_insn (from
)) == CACHE_LOG
)
2699 /* We have just passed the barrier in front of the
2700 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2701 the ADDR_DIFF_VEC is accessed as data, just like our pool
2702 constants, this is a good opportunity to accommodate what
2703 we have gathered so far.
2704 If we waited any longer, we could end up at a barrier in
2705 front of code, which gives worse cache usage for separated
2706 instruction / data caches. */
2707 good_barrier
= found_barrier
;
2712 rtx body
= PATTERN (from
);
2713 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
2716 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2717 else if (GET_CODE (from
) == JUMP_INSN
2719 && ! TARGET_SMALLCODE
)
2725 if (new_align
> si_align
)
2727 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
2728 si_align
= new_align
;
2730 count_si
= (count_si
+ new_align
- 1) & -new_align
;
2735 if (new_align
> hi_align
)
2737 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
2738 hi_align
= new_align
;
2740 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
2742 from
= NEXT_INSN (from
);
2749 /* Try as we might, the leading mova is out of range. Change
2750 it into a load (which will become a pcload) and retry. */
2751 SET_SRC (PATTERN (mova
)) = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
2752 INSN_CODE (mova
) = -1;
2753 return find_barrier (0, 0, mova
);
2757 /* Insert the constant pool table before the mova instruction,
2758 to prevent the mova label reference from going out of range. */
2760 good_barrier
= found_barrier
= barrier_before_mova
;
2766 if (good_barrier
&& next_real_insn (found_barrier
))
2767 found_barrier
= good_barrier
;
2771 /* We didn't find a barrier in time to dump our stuff,
2772 so we'll make one. */
2773 rtx label
= gen_label_rtx ();
2775 /* If we exceeded the range, then we must back up over the last
2776 instruction we looked at. Otherwise, we just need to undo the
2777 NEXT_INSN at the end of the loop. */
2778 if (count_hi
> hi_limit
|| count_si
> si_limit
)
2779 from
= PREV_INSN (PREV_INSN (from
));
2781 from
= PREV_INSN (from
);
2783 /* Walk back to be just before any jump or label.
2784 Putting it before a label reduces the number of times the branch
2785 around the constant pool table will be hit. Putting it before
2786 a jump makes it more likely that the bra delay slot will be
2788 while (GET_CODE (from
) == JUMP_INSN
|| GET_CODE (from
) == NOTE
2789 || GET_CODE (from
) == CODE_LABEL
)
2790 from
= PREV_INSN (from
);
2792 from
= emit_jump_insn_after (gen_jump (label
), from
);
2793 JUMP_LABEL (from
) = label
;
2794 LABEL_NUSES (label
) = 1;
2795 found_barrier
= emit_barrier_after (from
);
2796 emit_label_after (label
, found_barrier
);
2799 return found_barrier
;
2802 /* If the instruction INSN is implemented by a special function, and we can
2803 positively find the register that is used to call the sfunc, and this
2804 register is not used anywhere else in this instruction - except as the
2805 destination of a set, return this register; else, return 0. */
2807 sfunc_uses_reg (insn
)
2811 rtx pattern
, part
, reg_part
, reg
;
2813 if (GET_CODE (insn
) != INSN
)
2815 pattern
= PATTERN (insn
);
2816 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
2819 for (reg_part
= 0, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2821 part
= XVECEXP (pattern
, 0, i
);
2822 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
2827 reg
= XEXP (reg_part
, 0);
2828 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2830 part
= XVECEXP (pattern
, 0, i
);
2831 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
2833 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
2834 && GET_CODE (SET_DEST (part
)) == REG
)
2835 ? SET_SRC (part
) : part
)))
2841 /* See if the only way in which INSN uses REG is by calling it, or by
2842 setting it while calling it. Set *SET to a SET rtx if the register
2846 noncall_uses_reg (reg
, insn
, set
)
2855 reg2
= sfunc_uses_reg (insn
);
2856 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
2858 pattern
= single_set (insn
);
2860 && GET_CODE (SET_DEST (pattern
)) == REG
2861 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2865 if (GET_CODE (insn
) != CALL_INSN
)
2867 /* We don't use rtx_equal_p because we don't care if the mode is
2869 pattern
= single_set (insn
);
2871 && GET_CODE (SET_DEST (pattern
)) == REG
2872 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2878 par
= PATTERN (insn
);
2879 if (GET_CODE (par
) == PARALLEL
)
2880 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
2882 part
= XVECEXP (par
, 0, i
);
2883 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
2886 return reg_mentioned_p (reg
, SET_SRC (pattern
));
2892 pattern
= PATTERN (insn
);
2894 if (GET_CODE (pattern
) == PARALLEL
)
2898 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2899 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
2901 pattern
= XVECEXP (pattern
, 0, 0);
2904 if (GET_CODE (pattern
) == SET
)
2906 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
2908 /* We don't use rtx_equal_p, because we don't care if the
2909 mode is different. */
2910 if (GET_CODE (SET_DEST (pattern
)) != REG
2911 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
2917 pattern
= SET_SRC (pattern
);
2920 if (GET_CODE (pattern
) != CALL
2921 || GET_CODE (XEXP (pattern
, 0)) != MEM
2922 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
2928 /* Given a X, a pattern of an insn or a part of it, return a mask of used
2929 general registers. Bits 0..15 mean that the respective registers
2930 are used as inputs in the instruction. Bits 16..31 mean that the
2931 registers 0..15, respectively, are used as outputs, or are clobbered.
2932 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
2934 regs_used (x
, is_dest
)
2943 code
= GET_CODE (x
);
2948 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2949 << (REGNO (x
) + is_dest
));
2953 rtx y
= SUBREG_REG (x
);
2955 if (GET_CODE (y
) != REG
)
2958 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2960 subreg_regno_offset (REGNO (y
),
2963 GET_MODE (x
)) + is_dest
));
2967 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
2969 /* If there was a return value, it must have been indicated with USE. */
2984 fmt
= GET_RTX_FORMAT (code
);
2986 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2991 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2992 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
2994 else if (fmt
[i
] == 'e')
2995 used
|= regs_used (XEXP (x
, i
), is_dest
);
3000 /* Create an instruction that prevents redirection of a conditional branch
3001 to the destination of the JUMP with address ADDR.
3002 If the branch needs to be implemented as an indirect jump, try to find
3003 a scratch register for it.
3004 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3005 If any preceding insn that doesn't fit into a delay slot is good enough,
3006 pass 1. Pass 2 if a definite blocking insn is needed.
3007 -1 is used internally to avoid deep recursion.
3008 If a blocking instruction is made or recognized, return it. */
3011 gen_block_redirect (jump
, addr
, need_block
)
3013 int addr
, need_block
;
3016 rtx prev
= prev_nonnote_insn (jump
);
3019 /* First, check if we already have an instruction that satisfies our need. */
3020 if (prev
&& GET_CODE (prev
) == INSN
&& ! INSN_DELETED_P (prev
))
3022 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
3024 if (GET_CODE (PATTERN (prev
)) == USE
3025 || GET_CODE (PATTERN (prev
)) == CLOBBER
3026 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3028 else if ((need_block
&= ~1) < 0)
3030 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
3033 /* We can't use JUMP_LABEL here because it might be undefined
3034 when not optimizing. */
3035 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
3036 /* If the branch is out of range, try to find a scratch register for it. */
3038 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3042 /* Don't look for the stack pointer as a scratch register,
3043 it would cause trouble if an interrupt occurred. */
3044 unsigned try = 0x7fff, used
;
3045 int jump_left
= flag_expensive_optimizations
+ 1;
3047 /* It is likely that the most recent eligible instruction is wanted for
3048 the delay slot. Therefore, find out which registers it uses, and
3049 try to avoid using them. */
3051 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
3055 if (INSN_DELETED_P (scan
))
3057 code
= GET_CODE (scan
);
3058 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
3061 && GET_CODE (PATTERN (scan
)) != USE
3062 && GET_CODE (PATTERN (scan
)) != CLOBBER
3063 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
3065 try &= ~regs_used (PATTERN (scan
), 0);
3069 for (used
= dead
= 0, scan
= JUMP_LABEL (jump
);
3070 (scan
= NEXT_INSN (scan
)); )
3074 if (INSN_DELETED_P (scan
))
3076 code
= GET_CODE (scan
);
3077 if (GET_RTX_CLASS (code
) == 'i')
3079 used
|= regs_used (PATTERN (scan
), 0);
3080 if (code
== CALL_INSN
)
3081 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
3082 dead
|= (used
>> 16) & ~used
;
3088 if (code
== JUMP_INSN
)
3090 if (jump_left
-- && simplejump_p (scan
))
3091 scan
= JUMP_LABEL (scan
);
3097 /* Mask out the stack pointer again, in case it was
3098 the only 'free' register we have found. */
3101 /* If the immediate destination is still in range, check for possible
3102 threading with a jump beyond the delay slot insn.
3103 Don't check if we are called recursively; the jump has been or will be
3104 checked in a different invocation then. */
3106 else if (optimize
&& need_block
>= 0)
3108 rtx next
= next_active_insn (next_active_insn (dest
));
3109 if (next
&& GET_CODE (next
) == JUMP_INSN
3110 && GET_CODE (PATTERN (next
)) == SET
3111 && recog_memoized (next
) == CODE_FOR_jump
)
3113 dest
= JUMP_LABEL (next
);
3115 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3117 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
3123 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
3125 /* It would be nice if we could convert the jump into an indirect
3126 jump / far branch right now, and thus exposing all constituent
3127 instructions to further optimization. However, reorg uses
3128 simplejump_p to determine if there is an unconditional jump where
3129 it should try to schedule instructions from the target of the
3130 branch; simplejump_p fails for indirect jumps even if they have
3132 rtx insn
= emit_insn_before (gen_indirect_jump_scratch
3133 (reg
, GEN_INT (INSN_UID (JUMP_LABEL (jump
))))
3135 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
3138 else if (need_block
)
3139 /* We can't use JUMP_LABEL here because it might be undefined
3140 when not optimizing. */
3141 return emit_insn_before (gen_block_branch_redirect
3142 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))))
3147 #define CONDJUMP_MIN -252
3148 #define CONDJUMP_MAX 262
3151 /* A label (to be placed) in front of the jump
3152 that jumps to our ultimate destination. */
3154 /* Where we are going to insert it if we cannot move the jump any farther,
3155 or the jump itself if we have picked up an existing jump. */
3157 /* The ultimate destination. */
3159 struct far_branch
*prev
;
3160 /* If the branch has already been created, its address;
3161 else the address of its first prospective user. */
3165 static void gen_far_branch
PARAMS ((struct far_branch
*));
3166 enum mdep_reorg_phase_e mdep_reorg_phase
;
3169 struct far_branch
*bp
;
3171 rtx insn
= bp
->insert_place
;
3173 rtx label
= gen_label_rtx ();
3175 emit_label_after (label
, insn
);
3178 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
3179 LABEL_NUSES (bp
->far_label
)++;
3182 jump
= emit_jump_insn_after (gen_return (), insn
);
3183 /* Emit a barrier so that reorg knows that any following instructions
3184 are not reachable via a fall-through path.
3185 But don't do this when not optimizing, since we wouldn't supress the
3186 alignment for the barrier then, and could end up with out-of-range
3187 pc-relative loads. */
3189 emit_barrier_after (jump
);
3190 emit_label_after (bp
->near_label
, insn
);
3191 JUMP_LABEL (jump
) = bp
->far_label
;
3192 if (! invert_jump (insn
, label
, 1))
3194 /* Prevent reorg from undoing our splits. */
3195 gen_block_redirect (jump
, bp
->address
+= 2, 2);
3198 /* Fix up ADDR_DIFF_VECs. */
3200 fixup_addr_diff_vecs (first
)
3205 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3207 rtx vec_lab
, pat
, prev
, prevpat
, x
, braf_label
;
3209 if (GET_CODE (insn
) != JUMP_INSN
3210 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
3212 pat
= PATTERN (insn
);
3213 vec_lab
= XEXP (XEXP (pat
, 0), 0);
3215 /* Search the matching casesi_jump_2. */
3216 for (prev
= vec_lab
; ; prev
= PREV_INSN (prev
))
3218 if (GET_CODE (prev
) != JUMP_INSN
)
3220 prevpat
= PATTERN (prev
);
3221 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
3223 x
= XVECEXP (prevpat
, 0, 1);
3224 if (GET_CODE (x
) != USE
)
3227 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
3231 /* Emit the reference label of the braf where it belongs, right after
3232 the casesi_jump_2 (i.e. braf). */
3233 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
3234 emit_label_after (braf_label
, prev
);
3236 /* Fix up the ADDR_DIF_VEC to be relative
3237 to the reference address of the braf. */
3238 XEXP (XEXP (pat
, 0), 0) = braf_label
;
3242 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3243 a barrier. Return the base 2 logarithm of the desired alignment. */
3245 barrier_align (barrier_or_label
)
3246 rtx barrier_or_label
;
3248 rtx next
= next_real_insn (barrier_or_label
), pat
, prev
;
3249 int slot
, credit
, jump_to_next
;
3254 pat
= PATTERN (next
);
3256 if (GET_CODE (pat
) == ADDR_DIFF_VEC
)
3259 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
3260 /* This is a barrier in front of a constant table. */
3263 prev
= prev_real_insn (barrier_or_label
);
3264 if (GET_CODE (PATTERN (prev
)) == ADDR_DIFF_VEC
)
3266 pat
= PATTERN (prev
);
3267 /* If this is a very small table, we want to keep the alignment after
3268 the table to the minimum for proper code alignment. */
3269 return ((TARGET_SMALLCODE
3270 || (XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
3271 <= (unsigned)1 << (CACHE_LOG
- 2)))
3272 ? 1 << TARGET_SHMEDIA
: CACHE_LOG
);
3275 if (TARGET_SMALLCODE
)
3278 if (! TARGET_SH2
|| ! optimize
)
3281 /* When fixing up pcloads, a constant table might be inserted just before
3282 the basic block that ends with the barrier. Thus, we can't trust the
3283 instruction lengths before that. */
3284 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
3286 /* Check if there is an immediately preceding branch to the insn beyond
3287 the barrier. We must weight the cost of discarding useful information
3288 from the current cache line when executing this branch and there is
3289 an alignment, against that of fetching unneeded insn in front of the
3290 branch target when there is no alignment. */
3292 /* There are two delay_slot cases to consider. One is the simple case
3293 where the preceding branch is to the insn beyond the barrier (simple
3294 delay slot filling), and the other is where the preceding branch has
3295 a delay slot that is a duplicate of the insn after the barrier
3296 (fill_eager_delay_slots) and the branch is to the insn after the insn
3297 after the barrier. */
3299 /* PREV is presumed to be the JUMP_INSN for the barrier under
3300 investigation. Skip to the insn before it. */
3301 prev
= prev_real_insn (prev
);
3303 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
3304 credit
>= 0 && prev
&& GET_CODE (prev
) == INSN
;
3305 prev
= prev_real_insn (prev
))
3308 if (GET_CODE (PATTERN (prev
)) == USE
3309 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
3311 if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
3313 prev
= XVECEXP (PATTERN (prev
), 0, 1);
3314 if (INSN_UID (prev
) == INSN_UID (next
))
3316 /* Delay slot was filled with insn at jump target. */
3323 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3325 credit
-= get_attr_length (prev
);
3328 && GET_CODE (prev
) == JUMP_INSN
3329 && JUMP_LABEL (prev
))
3333 || next_real_insn (JUMP_LABEL (prev
)) == next
3334 /* If relax_delay_slots() decides NEXT was redundant
3335 with some previous instruction, it will have
3336 redirected PREV's jump to the following insn. */
3337 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
3338 /* There is no upper bound on redundant instructions
3339 that might have been skipped, but we must not put an
3340 alignment where none had been before. */
3341 || (x
= (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
)))),
3343 && (INSN_CODE (x
) == CODE_FOR_block_branch_redirect
3344 || INSN_CODE (x
) == CODE_FOR_indirect_jump_scratch
))))
3346 rtx pat
= PATTERN (prev
);
3347 if (GET_CODE (pat
) == PARALLEL
)
3348 pat
= XVECEXP (pat
, 0, 0);
3349 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
3358 /* If we are inside a phony loop, almost any kind of label can turn up as the
3359 first one in the loop. Aligning a braf label causes incorrect switch
3360 destination addresses; we can detect braf labels because they are
3361 followed by a BARRIER.
3362 Applying loop alignment to small constant or switch tables is a waste
3363 of space, so we suppress this too. */
3365 sh_loop_align (label
)
3371 next
= next_nonnote_insn (next
);
3372 while (next
&& GET_CODE (next
) == CODE_LABEL
);
3376 || GET_CODE (PATTERN (next
)) == ADDR_DIFF_VEC
3377 || recog_memoized (next
) == CODE_FOR_consttable_2
)
3386 /* Exported to toplev.c.
3388 Do a final pass over the function, just before delayed branch
3392 machine_dependent_reorg (first
)
3397 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
3398 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
3400 /* We must split call insns before introducing `mova's. If we're
3401 optimizing, they'll have already been split. Otherwise, make
3402 sure we don't split them too late. */
3404 split_all_insns_noflow ();
3409 /* If relaxing, generate pseudo-ops to associate function calls with
3410 the symbols they call. It does no harm to not generate these
3411 pseudo-ops. However, when we can generate them, it enables to
3412 linker to potentially relax the jsr to a bsr, and eliminate the
3413 register load and, possibly, the constant pool entry. */
3415 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
3418 /* Remove all REG_LABEL notes. We want to use them for our own
3419 purposes. This works because none of the remaining passes
3420 need to look at them.
3422 ??? But it may break in the future. We should use a machine
3423 dependent REG_NOTE, or some other approach entirely. */
3424 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3430 while ((note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
)) != 0)
3431 remove_note (insn
, note
);
3435 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3437 rtx pattern
, reg
, link
, set
, scan
, dies
, label
;
3438 int rescan
= 0, foundinsn
= 0;
3440 if (GET_CODE (insn
) == CALL_INSN
)
3442 pattern
= PATTERN (insn
);
3444 if (GET_CODE (pattern
) == PARALLEL
)
3445 pattern
= XVECEXP (pattern
, 0, 0);
3446 if (GET_CODE (pattern
) == SET
)
3447 pattern
= SET_SRC (pattern
);
3449 if (GET_CODE (pattern
) != CALL
3450 || GET_CODE (XEXP (pattern
, 0)) != MEM
)
3453 reg
= XEXP (XEXP (pattern
, 0), 0);
3457 reg
= sfunc_uses_reg (insn
);
3462 if (GET_CODE (reg
) != REG
)
3465 /* This is a function call via REG. If the only uses of REG
3466 between the time that it is set and the time that it dies
3467 are in function calls, then we can associate all the
3468 function calls with the setting of REG. */
3470 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
3472 if (REG_NOTE_KIND (link
) != 0)
3474 set
= single_set (XEXP (link
, 0));
3475 if (set
&& rtx_equal_p (reg
, SET_DEST (set
)))
3477 link
= XEXP (link
, 0);
3484 /* ??? Sometimes global register allocation will have
3485 deleted the insn pointed to by LOG_LINKS. Try
3486 scanning backward to find where the register is set. */
3487 for (scan
= PREV_INSN (insn
);
3488 scan
&& GET_CODE (scan
) != CODE_LABEL
;
3489 scan
= PREV_INSN (scan
))
3491 if (! INSN_P (scan
))
3494 if (! reg_mentioned_p (reg
, scan
))
3497 if (noncall_uses_reg (reg
, scan
, &set
))
3511 /* The register is set at LINK. */
3513 /* We can only optimize the function call if the register is
3514 being set to a symbol. In theory, we could sometimes
3515 optimize calls to a constant location, but the assembler
3516 and linker do not support that at present. */
3517 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
3518 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
3521 /* Scan forward from LINK to the place where REG dies, and
3522 make sure that the only insns which use REG are
3523 themselves function calls. */
3525 /* ??? This doesn't work for call targets that were allocated
3526 by reload, since there may not be a REG_DEAD note for the
3530 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
3534 /* Don't try to trace forward past a CODE_LABEL if we haven't
3535 seen INSN yet. Ordinarily, we will only find the setting insn
3536 in LOG_LINKS if it is in the same basic block. However,
3537 cross-jumping can insert code labels in between the load and
3538 the call, and can result in situations where a single call
3539 insn may have two targets depending on where we came from. */
3541 if (GET_CODE (scan
) == CODE_LABEL
&& ! foundinsn
)
3544 if (! INSN_P (scan
))
3547 /* Don't try to trace forward past a JUMP. To optimize
3548 safely, we would have to check that all the
3549 instructions at the jump destination did not use REG. */
3551 if (GET_CODE (scan
) == JUMP_INSN
)
3554 if (! reg_mentioned_p (reg
, scan
))
3557 if (noncall_uses_reg (reg
, scan
, &scanset
))
3564 && (GET_CODE (scan
) == CALL_INSN
|| sfunc_uses_reg (scan
)))
3566 /* There is a function call to this register other
3567 than the one we are checking. If we optimize
3568 this call, we need to rescan again below. */
3572 /* ??? We shouldn't have to worry about SCANSET here.
3573 We should just be able to check for a REG_DEAD note
3574 on a function call. However, the REG_DEAD notes are
3575 apparently not dependable around libcalls; c-torture
3576 execute/920501-2 is a test case. If SCANSET is set,
3577 then this insn sets the register, so it must have
3578 died earlier. Unfortunately, this will only handle
3579 the cases in which the register is, in fact, set in a
3582 /* ??? We shouldn't have to use FOUNDINSN here.
3583 However, the LOG_LINKS fields are apparently not
3584 entirely reliable around libcalls;
3585 newlib/libm/math/e_pow.c is a test case. Sometimes
3586 an insn will appear in LOG_LINKS even though it is
3587 not the most recent insn which sets the register. */
3591 || find_reg_note (scan
, REG_DEAD
, reg
)))
3600 /* Either there was a branch, or some insn used REG
3601 other than as a function call address. */
3605 /* Create a code label, and put it in a REG_LABEL note on
3606 the insn which sets the register, and on each call insn
3607 which uses the register. In final_prescan_insn we look
3608 for the REG_LABEL notes, and output the appropriate label
3611 label
= gen_label_rtx ();
3612 REG_NOTES (link
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
3614 REG_NOTES (insn
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
3623 scan
= NEXT_INSN (scan
);
3625 && ((GET_CODE (scan
) == CALL_INSN
3626 && reg_mentioned_p (reg
, scan
))
3627 || ((reg2
= sfunc_uses_reg (scan
))
3628 && REGNO (reg2
) == REGNO (reg
))))
3630 = gen_rtx_INSN_LIST (REG_LABEL
, label
, REG_NOTES (scan
));
3632 while (scan
!= dies
);
3638 fixup_addr_diff_vecs (first
);
3642 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
3643 shorten_branches (first
);
3645 /* Scan the function looking for move instructions which have to be
3646 changed to pc-relative loads and insert the literal tables. */
3648 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
3649 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
3656 else if (GET_CODE (insn
) == JUMP_INSN
3657 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3665 /* Some code might have been inserted between the mova and
3666 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3667 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
3668 total
+= get_attr_length (scan
);
3670 /* range of mova is 1020, add 4 because pc counts from address of
3671 second instruction after this one, subtract 2 in case pc is 2
3672 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3673 cancels out with alignment effects of the mova itself. */
3676 /* Change the mova into a load, and restart scanning
3677 there. broken_move will then return true for mova. */
3678 SET_SRC (PATTERN (mova
))
3679 = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
3680 INSN_CODE (mova
) = -1;
3684 if (broken_move (insn
))
3687 /* Scan ahead looking for a barrier to stick the constant table
3689 rtx barrier
= find_barrier (num_mova
, mova
, insn
);
3690 rtx last_float_move
, last_float
= 0, *last_float_addr
;
3691 int may_need_align
= 1;
3693 if (num_mova
&& ! mova_p (mova
))
3695 /* find_barrier had to change the first mova into a
3696 pcload; thus, we have to start with this new pcload. */
3700 /* Now find all the moves between the points and modify them. */
3701 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
3703 if (GET_CODE (scan
) == CODE_LABEL
)
3705 if (broken_move (scan
))
3707 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
3711 enum machine_mode mode
;
3713 if (GET_CODE (pat
) == PARALLEL
)
3714 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
3715 src
= SET_SRC (pat
);
3716 dst
= SET_DEST (pat
);
3717 mode
= GET_MODE (dst
);
3719 if (mode
== SImode
&& hi_const (src
)
3720 && REGNO (dst
) != FPUL_REG
)
3725 while (GET_CODE (dst
) == SUBREG
)
3727 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
3728 GET_MODE (SUBREG_REG (dst
)),
3731 dst
= SUBREG_REG (dst
);
3733 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
3736 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
3738 /* This must be an insn that clobbers r0. */
3739 rtx clobber
= XVECEXP (PATTERN (scan
), 0,
3740 XVECLEN (PATTERN (scan
), 0) - 1);
3742 if (GET_CODE (clobber
) != CLOBBER
3743 || ! rtx_equal_p (XEXP (clobber
, 0), r0_rtx
))
3747 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
3749 if (TARGET_SHCOMPACT
)
3751 /* The first SFmode constant after a DFmode
3752 constant may be pulled before a sequence
3753 of DFmode constants, so the second SFmode
3754 needs a label, just in case. */
3755 if (GET_MODE_SIZE (mode
) == 4)
3757 if (last_float
&& may_need_align
)
3762 && (GET_MODE_SIZE (GET_MODE (last_float
))
3763 != GET_MODE_SIZE (mode
)))
3766 if (GET_MODE_SIZE (mode
) == 4)
3770 lab
= add_constant (src
, mode
, last_float
);
3772 emit_insn_before (gen_mova (lab
), scan
);
3775 /* There will be a REG_UNUSED note for r0 on
3776 LAST_FLOAT_MOVE; we have to change it to REG_INC,
3777 lest reorg:mark_target_live_regs will not
3778 consider r0 to be used, and we end up with delay
3779 slot insn in front of SCAN that clobbers r0. */
3781 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
3783 /* If we are not optimizing, then there may not be
3786 PUT_MODE (note
, REG_INC
);
3788 *last_float_addr
= r0_inc_rtx
;
3790 last_float_move
= scan
;
3792 newsrc
= gen_rtx (MEM
, mode
,
3793 (((TARGET_SH4
&& ! TARGET_FMOVD
)
3794 || REGNO (dst
) == FPUL_REG
)
3797 last_float_addr
= &XEXP (newsrc
, 0);
3799 /* Remove the clobber of r0. */
3800 XEXP (clobber
, 0) = gen_rtx_SCRATCH (Pmode
);
3802 /* This is a mova needing a label. Create it. */
3803 else if (GET_CODE (src
) == UNSPEC
3804 && XINT (src
, 1) == UNSPEC_MOVA
3805 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
3807 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
3808 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
3809 newsrc
= gen_rtx_UNSPEC (VOIDmode
,
3810 gen_rtvec (1, newsrc
),
3815 lab
= add_constant (src
, mode
, 0);
3816 newsrc
= gen_rtx_MEM (mode
,
3817 gen_rtx_LABEL_REF (VOIDmode
, lab
));
3819 RTX_UNCHANGING_P (newsrc
) = 1;
3820 *patp
= gen_rtx_SET (VOIDmode
, dst
, newsrc
);
3821 INSN_CODE (scan
) = -1;
3824 dump_table (barrier
);
3829 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
3830 INSN_ADDRESSES_FREE ();
3831 split_branches (first
);
3833 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
3834 also has an effect on the register that holds the addres of the sfunc.
3835 Insert an extra dummy insn in front of each sfunc that pretends to
3836 use this register. */
3837 if (flag_delayed_branch
)
3839 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3841 rtx reg
= sfunc_uses_reg (insn
);
3845 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
3849 /* fpscr is not actually a user variable, but we pretend it is for the
3850 sake of the previous optimization passes, since we want it handled like
3851 one. However, we don't have any debugging information for it, so turn
3852 it into a non-user variable now. */
3854 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
3856 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
3860 get_dest_uid (label
, max_uid
)
3864 rtx dest
= next_real_insn (label
);
3867 /* This can happen for an undefined label. */
3869 dest_uid
= INSN_UID (dest
);
3870 /* If this is a newly created branch redirection blocking instruction,
3871 we cannot index the branch_uid or insn_addresses arrays with its
3872 uid. But then, we won't need to, because the actual destination is
3873 the following branch. */
3874 while (dest_uid
>= max_uid
)
3876 dest
= NEXT_INSN (dest
);
3877 dest_uid
= INSN_UID (dest
);
3879 if (GET_CODE (dest
) == JUMP_INSN
&& GET_CODE (PATTERN (dest
)) == RETURN
)
3884 /* Split condbranches that are out of range. Also add clobbers for
3885 scratch registers that are needed in far jumps.
3886 We do this before delay slot scheduling, so that it can take our
3887 newly created instructions into account. It also allows us to
3888 find branches with common targets more easily. */
3891 split_branches (first
)
3895 struct far_branch
**uid_branch
, *far_branch_list
= 0;
3896 int max_uid
= get_max_uid ();
3898 /* Find out which branches are out of range. */
3899 shorten_branches (first
);
3901 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
3902 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
3904 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3905 if (! INSN_P (insn
))
3907 else if (INSN_DELETED_P (insn
))
3909 /* Shorten_branches would split this instruction again,
3910 so transform it into a note. */
3911 PUT_CODE (insn
, NOTE
);
3912 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
3913 NOTE_SOURCE_FILE (insn
) = 0;
3915 else if (GET_CODE (insn
) == JUMP_INSN
3916 /* Don't mess with ADDR_DIFF_VEC */
3917 && (GET_CODE (PATTERN (insn
)) == SET
3918 || GET_CODE (PATTERN (insn
)) == RETURN
))
3920 enum attr_type type
= get_attr_type (insn
);
3921 if (type
== TYPE_CBRANCH
)
3925 if (get_attr_length (insn
) > 4)
3927 rtx src
= SET_SRC (PATTERN (insn
));
3928 rtx olabel
= XEXP (XEXP (src
, 1), 0);
3929 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
3931 int dest_uid
= get_dest_uid (olabel
, max_uid
);
3932 struct far_branch
*bp
= uid_branch
[dest_uid
];
3934 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
3935 the label if the LABEL_NUSES count drops to zero. There is
3936 always a jump_optimize pass that sets these values, but it
3937 proceeds to delete unreferenced code, and then if not
3938 optimizing, to un-delete the deleted instructions, thus
3939 leaving labels with too low uses counts. */
3942 JUMP_LABEL (insn
) = olabel
;
3943 LABEL_NUSES (olabel
)++;
3947 bp
= (struct far_branch
*) alloca (sizeof *bp
);
3948 uid_branch
[dest_uid
] = bp
;
3949 bp
->prev
= far_branch_list
;
3950 far_branch_list
= bp
;
3952 = XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1), 0);
3953 LABEL_NUSES (bp
->far_label
)++;
3957 label
= bp
->near_label
;
3958 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
3960 rtx block
= bp
->insert_place
;
3962 if (GET_CODE (PATTERN (block
)) == RETURN
)
3963 block
= PREV_INSN (block
);
3965 block
= gen_block_redirect (block
,
3967 label
= emit_label_after (gen_label_rtx (),
3969 bp
->near_label
= label
;
3971 else if (label
&& ! NEXT_INSN (label
))
3973 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
3974 bp
->insert_place
= insn
;
3976 gen_far_branch (bp
);
3980 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
3982 bp
->near_label
= label
= gen_label_rtx ();
3983 bp
->insert_place
= insn
;
3986 if (! redirect_jump (insn
, label
, 1))
3991 /* get_attr_length (insn) == 2 */
3992 /* Check if we have a pattern where reorg wants to redirect
3993 the branch to a label from an unconditional branch that
3995 /* We can't use JUMP_LABEL here because it might be undefined
3996 when not optimizing. */
3997 /* A syntax error might cause beyond to be NULL_RTX. */
3999 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
4003 && (GET_CODE (beyond
) == JUMP_INSN
4004 || ((beyond
= next_active_insn (beyond
))
4005 && GET_CODE (beyond
) == JUMP_INSN
))
4006 && GET_CODE (PATTERN (beyond
)) == SET
4007 && recog_memoized (beyond
) == CODE_FOR_jump
4009 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
4010 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
4012 gen_block_redirect (beyond
,
4013 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
4016 next
= next_active_insn (insn
);
4018 if ((GET_CODE (next
) == JUMP_INSN
4019 || GET_CODE (next
= next_active_insn (next
)) == JUMP_INSN
)
4020 && GET_CODE (PATTERN (next
)) == SET
4021 && recog_memoized (next
) == CODE_FOR_jump
4023 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
4024 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
4026 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
4028 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
4030 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
4033 struct far_branch
*bp
;
4035 if (type
== TYPE_JUMP
)
4037 far_label
= XEXP (SET_SRC (PATTERN (insn
)), 0);
4038 dest_uid
= get_dest_uid (far_label
, max_uid
);
4041 /* Parse errors can lead to labels outside
4043 if (! NEXT_INSN (far_label
))
4048 JUMP_LABEL (insn
) = far_label
;
4049 LABEL_NUSES (far_label
)++;
4051 redirect_jump (insn
, NULL_RTX
, 1);
4055 bp
= uid_branch
[dest_uid
];
4058 bp
= (struct far_branch
*) alloca (sizeof *bp
);
4059 uid_branch
[dest_uid
] = bp
;
4060 bp
->prev
= far_branch_list
;
4061 far_branch_list
= bp
;
4063 bp
->far_label
= far_label
;
4065 LABEL_NUSES (far_label
)++;
4067 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
4068 if (addr
- bp
->address
<= CONDJUMP_MAX
)
4069 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
4072 gen_far_branch (bp
);
4078 bp
->insert_place
= insn
;
4080 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
4082 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
4085 /* Generate all pending far branches,
4086 and free our references to the far labels. */
4087 while (far_branch_list
)
4089 if (far_branch_list
->near_label
4090 && ! NEXT_INSN (far_branch_list
->near_label
))
4091 gen_far_branch (far_branch_list
);
4093 && far_branch_list
->far_label
4094 && ! --LABEL_NUSES (far_branch_list
->far_label
))
4095 delete_insn (far_branch_list
->far_label
);
4096 far_branch_list
= far_branch_list
->prev
;
4099 /* Instruction length information is no longer valid due to the new
4100 instructions that have been generated. */
4101 init_insn_lengths ();
4104 /* Dump out instruction addresses, which is useful for debugging the
4105 constant pool table stuff.
4107 If relaxing, output the label and pseudo-ops used to link together
4108 calls and the instruction which set the registers. */
4110 /* ??? This is unnecessary, and probably should be deleted. This makes
4111 the insn_addresses declaration above unnecessary. */
4113 /* ??? The addresses printed by this routine for insns are nonsense for
4114 insns which are inside of a sequence where none of the inner insns have
4115 variable length. This is because the second pass of shorten_branches
4116 does not bother to update them. */
4119 final_prescan_insn (insn
, opvec
, noperands
)
4121 rtx
*opvec ATTRIBUTE_UNUSED
;
4122 int noperands ATTRIBUTE_UNUSED
;
4124 if (TARGET_DUMPISIZE
)
4125 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
4131 note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
);
4136 pattern
= PATTERN (insn
);
4137 if (GET_CODE (pattern
) == PARALLEL
)
4138 pattern
= XVECEXP (pattern
, 0, 0);
4139 if (GET_CODE (pattern
) == CALL
4140 || (GET_CODE (pattern
) == SET
4141 && (GET_CODE (SET_SRC (pattern
)) == CALL
4142 || get_attr_type (insn
) == TYPE_SFUNC
)))
4143 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
4144 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4145 else if (GET_CODE (pattern
) == SET
)
4146 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4147 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4154 /* Dump out any constants accumulated in the final pass. These will
4158 output_jump_label_table ()
4164 fprintf (asm_out_file
, "\t.align 2\n");
4165 for (i
= 0; i
< pool_size
; i
++)
4167 pool_node
*p
= &pool_vector
[i
];
4169 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4170 CODE_LABEL_NUMBER (p
->label
));
4171 output_asm_insn (".long %O0", &p
->value
);
4179 /* A full frame looks like:
4183 [ if current_function_anonymous_args
4196 local-0 <- fp points here. */
4198 /* Number of bytes pushed for anonymous args, used to pass information
4199 between expand_prologue and expand_epilogue. */
4201 static int extra_push
;
4203 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
4204 to be adjusted, and TEMP, if nonnegative, holds the register number
4205 of a general register that we may clobber. */
4208 output_stack_adjust (size
, reg
, temp
)
4215 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4220 if (CONST_OK_FOR_ADD (size
))
4221 emit_insn (GEN_ADD3 (reg
, reg
, GEN_INT (size
)));
4222 /* Try to do it with two partial adjustments; however, we must make
4223 sure that the stack is properly aligned at all times, in case
4224 an interrupt occurs between the two partial adjustments. */
4225 else if (CONST_OK_FOR_ADD (size
/ 2 & -align
)
4226 && CONST_OK_FOR_ADD (size
- (size
/ 2 & -align
)))
4228 emit_insn (GEN_ADD3 (reg
, reg
, GEN_INT (size
/ 2 & -align
)));
4229 emit_insn (GEN_ADD3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -align
))));
4235 /* If TEMP is invalid, we could temporarily save a general
4236 register to MACL. However, there is currently no need
4237 to handle this case, so just abort when we see it. */
4240 const_reg
= gen_rtx_REG (GET_MODE (reg
), temp
);
4242 /* If SIZE is negative, subtract the positive value.
4243 This sometimes allows a constant pool entry to be shared
4244 between prologue and epilogue code. */
4247 emit_insn (GEN_MOV (const_reg
, GEN_INT (-size
)));
4248 emit_insn (GEN_SUB3 (reg
, reg
, const_reg
));
4252 emit_insn (GEN_MOV (const_reg
, GEN_INT (size
)));
4253 emit_insn (GEN_ADD3 (reg
, reg
, const_reg
));
4259 /* Output RTL to push register RN onto the stack. */
4267 x
= gen_push_fpul ();
4268 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4269 && FP_OR_XD_REGISTER_P (rn
))
4271 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4273 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
4275 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
4276 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
4278 x
= gen_push (gen_rtx_REG (SImode
, rn
));
4282 = gen_rtx_EXPR_LIST (REG_INC
,
4283 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4286 /* Output RTL to pop register RN from the stack. */
4294 x
= gen_pop_fpul ();
4295 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4296 && FP_OR_XD_REGISTER_P (rn
))
4298 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4300 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
4302 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
4303 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
4305 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
4309 = gen_rtx_EXPR_LIST (REG_INC
,
4310 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4313 /* Generate code to push the regs specified in the mask. */
4317 HOST_WIDE_INT
*mask
;
4321 /* Push PR last; this gives better latencies after the prologue, and
4322 candidates for the return delay slot when there are no general
4323 registers pushed. */
4324 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4325 if (i
!= PR_REG
&& mask
[i
/ 32] & (1 << (i
% 32)))
4327 if (mask
[PR_REG
/ 32] & (1 << (PR_REG
% 32)))
4331 /* Work out the registers which need to be saved, both as a mask and a
4332 count of saved words.
4334 If doing a pragma interrupt function, then push all regs used by the
4335 function, and if we call another function (we can tell by looking at PR),
4336 make sure that all the regs it clobbers are safe too. */
4339 calc_live_regs (count_ptr
, live_regs_mask
)
4341 HOST_WIDE_INT
*live_regs_mask
;
4345 int interrupt_handler
;
4349 if ((lookup_attribute
4350 ("interrupt_handler",
4351 DECL_ATTRIBUTES (current_function_decl
)))
4353 interrupt_handler
= 1;
4355 interrupt_handler
= 0;
4357 for (count
= 0; 32 * count
< FIRST_PSEUDO_REGISTER
; count
++)
4358 live_regs_mask
[count
] = 0;
4359 /* If we can save a lot of saves by switching to double mode, do that. */
4360 if (TARGET_SH4
&& TARGET_FMOVD
&& TARGET_FPU_SINGLE
)
4361 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
4362 if (regs_ever_live
[reg
] && regs_ever_live
[reg
+1]
4363 && (! call_used_regs
[reg
] || (interrupt_handler
&& ! pragma_trapa
))
4366 target_flags
&= ~FPU_SINGLE_BIT
;
4369 pr_initial
= has_hard_reg_initial_val (Pmode
,
4371 ? PR_MEDIA_REG
: PR_REG
);
4372 pr_live
= (pr_initial
4373 ? REGNO (pr_initial
) != (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
4374 : regs_ever_live
[TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
]);
4375 /* Force PR to be live if the prologue has to call the SHmedia
4376 argument decoder or register saver. */
4377 if (TARGET_SHCOMPACT
4378 && ((current_function_args_info
.call_cookie
4379 & ~ CALL_COOKIE_RET_TRAMP (1))
4380 || current_function_has_nonlocal_label
))
4382 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
- 1; reg
>= 0; reg
--)
4384 if (reg
== (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
4386 : (interrupt_handler
&& ! pragma_trapa
)
4387 ? (/* Need to save all the regs ever live. */
4388 (regs_ever_live
[reg
]
4389 || (call_used_regs
[reg
]
4390 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
)
4392 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
4393 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
4394 && reg
!= T_REG
&& reg
!= GBR_REG
&& reg
!= FPSCR_REG
)
4395 : (/* Only push those regs which are used and need to be saved. */
4396 regs_ever_live
[reg
] && ! call_used_regs
[reg
]))
4398 live_regs_mask
[reg
/ 32] |= 1 << (reg
% 32);
4399 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
4401 if ((TARGET_SH4
|| TARGET_SH5
) && TARGET_FMOVD
4402 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg
)) == MODE_FLOAT
)
4404 if (FP_REGISTER_P (reg
))
4406 if (! TARGET_FPU_SINGLE
&& ! regs_ever_live
[reg
^ 1])
4408 live_regs_mask
[(reg
^ 1) / 32] |= 1 << ((reg
^ 1) % 32);
4409 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
^ 1));
4412 else if (XD_REGISTER_P (reg
))
4414 /* Must switch to double mode to access these registers. */
4415 target_flags
&= ~FPU_SINGLE_BIT
;
4424 /* Code to generate prologue and epilogue sequences */
4426 /* PUSHED is the number of bytes that are bing pushed on the
4427 stack for register saves. Return the frame size, padded
4428 appropriately so that the stack stays properly aligned. */
4429 static HOST_WIDE_INT
4430 rounded_frame_size (pushed
)
4433 HOST_WIDE_INT size
= get_frame_size ();
4434 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4436 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
4439 /* Choose a call-clobbered target-branch register that remains
4440 unchanged along the whole function. We set it up as the return
4441 value in the prologue. */
4443 sh_media_register_for_return ()
4448 if (! current_function_is_leaf
)
4451 tr0_used
= flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
];
4453 for (regno
= FIRST_TARGET_REG
+ tr0_used
; regno
<= LAST_TARGET_REG
; regno
++)
4454 if (call_used_regs
[regno
] && ! regs_ever_live
[regno
])
4461 sh_expand_prologue ()
4463 HOST_WIDE_INT live_regs_mask
[(FIRST_PSEUDO_REGISTER
+ 31) / 32];
4466 int save_flags
= target_flags
;
4468 current_function_interrupt
4469 = lookup_attribute ("interrupt_handler",
4470 DECL_ATTRIBUTES (current_function_decl
))
4473 /* We have pretend args if we had an object sent partially in registers
4474 and partially on the stack, e.g. a large structure. */
4475 output_stack_adjust (-current_function_pretend_args_size
4476 - current_function_args_info
.stack_regs
* 8,
4477 stack_pointer_rtx
, TARGET_SH5
? 0 : 1);
4481 if (TARGET_SHCOMPACT
&& flag_pic
&& current_function_args_info
.call_cookie
)
4482 /* We're going to use the PIC register to load the address of the
4483 incoming-argument decoder and/or of the return trampoline from
4484 the GOT, so make sure the PIC register is preserved and
4486 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
4488 if (TARGET_SHCOMPACT
4489 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
4493 /* First, make all registers with incoming arguments that will
4494 be pushed onto the stack live, so that register renaming
4495 doesn't overwrite them. */
4496 for (reg
= 0; reg
< NPARM_REGS (SImode
); reg
++)
4497 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info
.call_cookie
)
4498 >= NPARM_REGS (SImode
) - reg
)
4499 for (; reg
< NPARM_REGS (SImode
); reg
++)
4500 emit_insn (gen_shcompact_preserve_incoming_args
4501 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
4502 else if (CALL_COOKIE_INT_REG_GET
4503 (current_function_args_info
.call_cookie
, reg
) == 1)
4504 emit_insn (gen_shcompact_preserve_incoming_args
4505 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
4507 emit_move_insn (gen_rtx_REG (Pmode
, MACL_REG
),
4509 emit_move_insn (gen_rtx_REG (SImode
, R0_REG
),
4510 GEN_INT (current_function_args_info
.call_cookie
));
4511 emit_move_insn (gen_rtx_REG (SImode
, MACH_REG
),
4512 gen_rtx_REG (SImode
, R0_REG
));
4514 else if (TARGET_SHMEDIA
)
4516 int tr
= sh_media_register_for_return ();
4520 rtx insn
= emit_move_insn (gen_rtx_REG (DImode
, tr
),
4521 gen_rtx_REG (DImode
, PR_MEDIA_REG
));
4523 /* If this function only exits with sibcalls, this copy
4524 will be flagged as dead. */
4525 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4531 /* Emit the code for SETUP_VARARGS. */
4532 if (current_function_varargs
|| current_function_stdarg
)
4534 /* This is not used by the SH3E calling convention */
4535 if (TARGET_SH1
&& ! TARGET_SH3E
&& ! TARGET_SH5
&& ! TARGET_HITACHI
)
4537 /* Push arg regs as if they'd been provided by caller in stack. */
4538 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
4540 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
4541 if (i
>= (NPARM_REGS(SImode
)
4542 - current_function_args_info
.arg_count
[(int) SH_ARG_INT
]
4551 /* If we're supposed to switch stacks at function entry, do so now. */
4553 emit_insn (gen_sp_switch_1 ());
4555 calc_live_regs (&d
, live_regs_mask
);
4556 /* ??? Maybe we could save some switching if we can move a mode switch
4557 that already happens to be at the function start into the prologue. */
4558 if (target_flags
!= save_flags
)
4559 emit_insn (gen_toggle_sz ());
4566 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
4567 int offset_in_r0
= -1;
4570 if (d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
4571 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
4572 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
4574 offset
= d
+ d_rounding
;
4575 output_stack_adjust (-offset
, stack_pointer_rtx
, 1);
4577 /* We loop twice: first, we save 8-byte aligned registers in the
4578 higher addresses, that are known to be aligned. Then, we
4579 proceed to saving 32-bit registers that don't need 8-byte
4581 for (align
= 1; align
>= 0; align
--)
4582 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
4583 if (live_regs_mask
[i
/32] & (1 << (i
% 32)))
4585 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
4587 rtx reg_rtx
, mem_rtx
, pre_dec
= NULL_RTX
;
4589 if (mode
== SFmode
&& (i
% 2) == 1
4590 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
4591 && (live_regs_mask
[(i
^ 1) / 32] & (1 << ((i
^ 1) % 32))))
4598 /* If we're doing the aligned pass and this is not aligned,
4599 or we're doing the unaligned pass and this is aligned,
4601 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
4605 offset
-= GET_MODE_SIZE (mode
);
4607 reg_rtx
= gen_rtx_REG (mode
, reg
);
4609 mem_rtx
= gen_rtx_MEM (mode
,
4610 gen_rtx_PLUS (Pmode
,
4614 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_pre_dec
);
4620 if (HAVE_PRE_DECREMENT
4621 && (offset_in_r0
- offset
== GET_MODE_SIZE (mode
)
4622 || mem_rtx
== NULL_RTX
4623 || i
== PR_REG
|| SPECIAL_REGISTER_P (i
)))
4625 pre_dec
= gen_rtx_MEM (mode
,
4626 gen_rtx_PRE_DEC (Pmode
, r0
));
4628 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (pre_dec
, 0),
4637 offset
+= GET_MODE_SIZE (mode
);
4641 if (mem_rtx
!= NULL_RTX
)
4644 if (offset_in_r0
== -1)
4646 emit_move_insn (r0
, GEN_INT (offset
));
4647 offset_in_r0
= offset
;
4649 else if (offset
!= offset_in_r0
)
4654 GEN_INT (offset
- offset_in_r0
)));
4655 offset_in_r0
+= offset
- offset_in_r0
;
4658 if (pre_dec
!= NULL_RTX
)
4664 (Pmode
, r0
, stack_pointer_rtx
));
4668 offset
-= GET_MODE_SIZE (mode
);
4669 offset_in_r0
-= GET_MODE_SIZE (mode
);
4674 mem_rtx
= gen_rtx_MEM (mode
, r0
);
4676 mem_rtx
= gen_rtx_MEM (mode
,
4677 gen_rtx_PLUS (Pmode
,
4681 /* We must not use an r0-based address for target-branch
4682 registers or for special registers without pre-dec
4683 memory addresses, since we store their values in r0
4685 if (TARGET_REGISTER_P (i
)
4686 || ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4687 && mem_rtx
!= pre_dec
))
4691 if (TARGET_REGISTER_P (i
)
4692 || ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4693 && mem_rtx
!= pre_dec
))
4695 rtx r0mode
= gen_rtx_REG (GET_MODE (reg_rtx
), R0_REG
);
4697 emit_move_insn (r0mode
, reg_rtx
);
4705 emit_move_insn (mem_rtx
, reg_rtx
);
4708 if (offset
!= d_rounding
)
4712 push_regs (live_regs_mask
);
4714 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
4716 rtx insn
= get_last_insn ();
4717 rtx last
= emit_insn (gen_GOTaddr2picreg ());
4719 /* Mark these insns as possibly dead. Sometimes, flow2 may
4720 delete all uses of the PIC register. In this case, let it
4721 delete the initialization too. */
4724 insn
= NEXT_INSN (insn
);
4726 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4730 while (insn
!= last
);
4733 if (SHMEDIA_REGS_STACK_ADJUST ())
4735 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
4736 gen_rtx_SYMBOL_REF (Pmode
,
4738 ? "__GCC_push_shmedia_regs"
4739 : "__GCC_push_shmedia_regs_nofpu"));
4740 /* This must NOT go through the PLT, otherwise mach and macl
4741 may be clobbered. */
4742 emit_insn (gen_shmedia_save_restore_regs_compact
4743 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
4746 if (target_flags
!= save_flags
)
4748 rtx insn
= emit_insn (gen_toggle_sz ());
4750 /* If we're lucky, a mode switch in the function body will
4751 overwrite fpscr, turning this insn dead. Tell flow this
4752 insn is ok to delete. */
4753 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4758 target_flags
= save_flags
;
4760 output_stack_adjust (-rounded_frame_size (d
) + d_rounding
,
4761 stack_pointer_rtx
, TARGET_SH5
? 0 : 1);
4763 if (frame_pointer_needed
)
4764 emit_insn (GEN_MOV (frame_pointer_rtx
, stack_pointer_rtx
));
4766 if (TARGET_SHCOMPACT
4767 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
4769 /* This must NOT go through the PLT, otherwise mach and macl
4770 may be clobbered. */
4771 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
4772 gen_rtx_SYMBOL_REF (Pmode
,
4773 "__GCC_shcompact_incoming_args"));
4774 emit_insn (gen_shcompact_incoming_args ());
4779 sh_expand_epilogue ()
4781 HOST_WIDE_INT live_regs_mask
[(FIRST_PSEUDO_REGISTER
+ 31) / 32];
4785 int save_flags
= target_flags
;
4788 calc_live_regs (&d
, live_regs_mask
);
4790 if (TARGET_SH5
&& d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
4791 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
4792 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
4794 frame_size
= rounded_frame_size (d
) - d_rounding
;
4796 if (frame_pointer_needed
)
4798 output_stack_adjust (frame_size
, frame_pointer_rtx
, 7);
4800 /* We must avoid moving the stack pointer adjustment past code
4801 which reads from the local frame, else an interrupt could
4802 occur after the SP adjustment and clobber data in the local
4804 emit_insn (gen_blockage ());
4805 emit_insn (GEN_MOV (stack_pointer_rtx
, frame_pointer_rtx
));
4807 else if (frame_size
)
4809 /* We must avoid moving the stack pointer adjustment past code
4810 which reads from the local frame, else an interrupt could
4811 occur after the SP adjustment and clobber data in the local
4813 emit_insn (gen_blockage ());
4814 output_stack_adjust (frame_size
, stack_pointer_rtx
, 7);
4817 if (SHMEDIA_REGS_STACK_ADJUST ())
4819 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
4820 gen_rtx_SYMBOL_REF (Pmode
,
4822 ? "__GCC_pop_shmedia_regs"
4823 : "__GCC_pop_shmedia_regs_nofpu"));
4824 /* This must NOT go through the PLT, otherwise mach and macl
4825 may be clobbered. */
4826 emit_insn (gen_shmedia_save_restore_regs_compact
4827 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
4830 /* Pop all the registers. */
4832 if (target_flags
!= save_flags
)
4833 emit_insn (gen_toggle_sz ());
4836 int offset
= d_rounding
;
4837 int offset_in_r0
= -1;
4840 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
4842 /* We loop twice: first, we save 8-byte aligned registers in the
4843 higher addresses, that are known to be aligned. Then, we
4844 proceed to saving 32-bit registers that don't need 8-byte
4846 for (align
= 0; align
<= 1; align
++)
4847 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4848 if (live_regs_mask
[i
/32] & (1 << (i
% 32)))
4850 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
4852 rtx reg_rtx
, mem_rtx
, post_inc
= NULL_RTX
, insn
;
4854 if (mode
== SFmode
&& (i
% 2) == 0
4855 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
4856 && (live_regs_mask
[(i
^ 1) / 32] & (1 << ((i
^ 1) % 32))))
4862 /* If we're doing the aligned pass and this is not aligned,
4863 or we're doing the unaligned pass and this is aligned,
4865 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
4869 reg_rtx
= gen_rtx_REG (mode
, reg
);
4871 mem_rtx
= gen_rtx_MEM (mode
,
4872 gen_rtx_PLUS (Pmode
,
4876 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_post_inc
);
4882 if (HAVE_POST_INCREMENT
4883 && (offset
== offset_in_r0
4884 || (offset
+ GET_MODE_SIZE (mode
) != d
+ d_rounding
4885 && mem_rtx
== NULL_RTX
)
4886 || i
== PR_REG
|| SPECIAL_REGISTER_P (i
)))
4888 post_inc
= gen_rtx_MEM (mode
,
4889 gen_rtx_POST_INC (Pmode
, r0
));
4891 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (post_inc
, 0),
4894 post_inc
= NULL_RTX
;
4903 if (mem_rtx
!= NULL_RTX
)
4906 if (offset_in_r0
== -1)
4908 emit_move_insn (r0
, GEN_INT (offset
));
4909 offset_in_r0
= offset
;
4911 else if (offset
!= offset_in_r0
)
4916 GEN_INT (offset
- offset_in_r0
)));
4917 offset_in_r0
+= offset
- offset_in_r0
;
4920 if (post_inc
!= NULL_RTX
)
4926 (Pmode
, r0
, stack_pointer_rtx
));
4932 offset_in_r0
+= GET_MODE_SIZE (mode
);
4935 mem_rtx
= gen_rtx_MEM (mode
, r0
);
4937 mem_rtx
= gen_rtx_MEM (mode
,
4938 gen_rtx_PLUS (Pmode
,
4942 if ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4943 && mem_rtx
!= post_inc
)
4947 if ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4948 && mem_rtx
!= post_inc
)
4950 insn
= emit_move_insn (r0
, mem_rtx
);
4953 else if (TARGET_REGISTER_P (i
))
4955 rtx r1
= gen_rtx_REG (mode
, R1_REG
);
4957 insn
= emit_move_insn (r1
, mem_rtx
);
4961 insn
= emit_move_insn (reg_rtx
, mem_rtx
);
4963 offset
+= GET_MODE_SIZE (mode
);
4966 if (offset
!= d
+ d_rounding
)
4973 if (live_regs_mask
[PR_REG
/ 32] & (1 << (PR_REG
% 32)))
4975 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4977 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
4979 if (j
!= PR_REG
&& live_regs_mask
[j
/ 32] & (1 << (j
% 32)))
4983 if (target_flags
!= save_flags
)
4984 emit_insn (gen_toggle_sz ());
4985 target_flags
= save_flags
;
4987 output_stack_adjust (extra_push
+ current_function_pretend_args_size
4989 + current_function_args_info
.stack_regs
* 8,
4990 stack_pointer_rtx
, 7);
4992 /* Switch back to the normal stack if necessary. */
4994 emit_insn (gen_sp_switch_2 ());
4996 /* Tell flow the insn that pops PR isn't dead. */
4997 /* PR_REG will never be live in SHmedia mode, and we don't need to
4998 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
4999 by the return pattern. */
5000 if (live_regs_mask
[PR_REG
/ 32] & (1 << (PR_REG
% 32)))
5001 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, PR_REG
)));
5004 static int sh_need_epilogue_known
= 0;
5009 if (! sh_need_epilogue_known
)
5014 sh_expand_epilogue ();
5015 epilogue
= gen_sequence ();
5017 sh_need_epilogue_known
5018 = (GET_CODE (epilogue
) == SEQUENCE
&& XVECLEN (epilogue
, 0) == 0
5021 return sh_need_epilogue_known
> 0;
5024 /* Clear variables at function end. */
5027 sh_output_function_epilogue (file
, size
)
5028 FILE *file ATTRIBUTE_UNUSED
;
5029 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
5031 trap_exit
= pragma_interrupt
= pragma_trapa
= pragma_nosave_low_regs
= 0;
5032 sh_need_epilogue_known
= 0;
5033 sp_switch
= NULL_RTX
;
5037 sh_builtin_saveregs ()
5039 /* First unnamed integer register. */
5040 int first_intreg
= current_function_args_info
.arg_count
[(int) SH_ARG_INT
];
5041 /* Number of integer registers we need to save. */
5042 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
5043 /* First unnamed SFmode float reg */
5044 int first_floatreg
= current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
5045 /* Number of SFmode float regs to save. */
5046 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
5049 HOST_WIDE_INT alias_set
;
5055 int pushregs
= n_intregs
;
5057 while (pushregs
< NPARM_REGS (SImode
) - 1
5058 && (CALL_COOKIE_INT_REG_GET
5059 (current_function_args_info
.call_cookie
,
5060 NPARM_REGS (SImode
) - pushregs
)
5063 current_function_args_info
.call_cookie
5064 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
5069 if (pushregs
== NPARM_REGS (SImode
))
5070 current_function_args_info
.call_cookie
5071 |= (CALL_COOKIE_INT_REG (0, 1)
5072 | CALL_COOKIE_STACKSEQ (pushregs
- 1));
5074 current_function_args_info
.call_cookie
5075 |= CALL_COOKIE_STACKSEQ (pushregs
);
5077 current_function_pretend_args_size
+= 8 * n_intregs
;
5079 if (TARGET_SHCOMPACT
)
5083 if (! TARGET_SH3E
&& ! TARGET_SH4
&& ! TARGET_SH5
)
5085 error ("__builtin_saveregs not supported by this subtarget");
5092 /* Allocate block of memory for the regs. */
5093 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5094 Or can assign_stack_local accept a 0 SIZE argument? */
5095 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
5098 regbuf
= gen_rtx_MEM (BLKmode
,
5099 gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
));
5100 else if (n_floatregs
& 1)
5104 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
5105 addr
= copy_to_mode_reg (Pmode
, XEXP (regbuf
, 0));
5106 emit_insn (gen_iorsi3 (addr
, addr
, GEN_INT (UNITS_PER_WORD
)));
5107 regbuf
= change_address (regbuf
, BLKmode
, addr
);
5110 regbuf
= assign_stack_local (BLKmode
, bufsize
, 0);
5111 alias_set
= get_varargs_alias_set ();
5112 set_mem_alias_set (regbuf
, alias_set
);
5115 This is optimized to only save the regs that are necessary. Explicitly
5116 named args need not be saved. */
5118 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
5119 adjust_address (regbuf
, BLKmode
,
5120 n_floatregs
* UNITS_PER_WORD
),
5121 n_intregs
, n_intregs
* UNITS_PER_WORD
);
5124 /* Return the address of the regbuf. */
5125 return XEXP (regbuf
, 0);
5128 This is optimized to only save the regs that are necessary. Explicitly
5129 named args need not be saved.
5130 We explicitly build a pointer to the buffer because it halves the insn
5131 count when not optimizing (otherwise the pointer is built for each reg
5133 We emit the moves in reverse order so that we can use predecrement. */
5135 fpregs
= gen_reg_rtx (Pmode
);
5136 emit_move_insn (fpregs
, XEXP (regbuf
, 0));
5137 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5138 GEN_INT (n_floatregs
* UNITS_PER_WORD
)));
5142 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
5144 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5145 GEN_INT (-2 * UNITS_PER_WORD
)));
5146 mem
= gen_rtx_MEM (DFmode
, fpregs
);
5147 set_mem_alias_set (mem
, alias_set
);
5148 emit_move_insn (mem
,
5149 gen_rtx (REG
, DFmode
, BASE_ARG_REG (DFmode
) + regno
));
5151 regno
= first_floatreg
;
5154 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5155 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5156 set_mem_alias_set (mem
, alias_set
);
5157 emit_move_insn (mem
,
5158 gen_rtx (REG
, SFmode
, BASE_ARG_REG (SFmode
) + regno
5159 - (TARGET_LITTLE_ENDIAN
!= 0)));
5163 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
5167 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5168 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5169 set_mem_alias_set (mem
, alias_set
);
5170 emit_move_insn (mem
,
5171 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
5174 /* Return the address of the regbuf. */
5175 return XEXP (regbuf
, 0);
5178 /* Define the `__builtin_va_list' type for the ABI. */
5183 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5186 if (TARGET_SH5
|| (! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
5187 return ptr_type_node
;
5189 record
= make_node (RECORD_TYPE
);
5191 f_next_o
= build_decl (FIELD_DECL
, get_identifier ("__va_next_o"),
5193 f_next_o_limit
= build_decl (FIELD_DECL
,
5194 get_identifier ("__va_next_o_limit"),
5196 f_next_fp
= build_decl (FIELD_DECL
, get_identifier ("__va_next_fp"),
5198 f_next_fp_limit
= build_decl (FIELD_DECL
,
5199 get_identifier ("__va_next_fp_limit"),
5201 f_next_stack
= build_decl (FIELD_DECL
, get_identifier ("__va_next_stack"),
5204 DECL_FIELD_CONTEXT (f_next_o
) = record
;
5205 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
5206 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
5207 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
5208 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
5210 TYPE_FIELDS (record
) = f_next_o
;
5211 TREE_CHAIN (f_next_o
) = f_next_o_limit
;
5212 TREE_CHAIN (f_next_o_limit
) = f_next_fp
;
5213 TREE_CHAIN (f_next_fp
) = f_next_fp_limit
;
5214 TREE_CHAIN (f_next_fp_limit
) = f_next_stack
;
5216 layout_type (record
);
5221 /* Implement `va_start' for varargs and stdarg. */
5224 sh_va_start (stdarg_p
, valist
, nextarg
)
5229 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5230 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
5236 expand_builtin_saveregs ();
5237 /* When the varargs dummy argument is ``passed'' on a register,
5238 we don't want std_expand_builtin_va_start() to apply any
5239 correction for it, so set stdarg_p so as to pretend there's
5240 no such dummy argument. */
5241 if (current_function_args_info
.arg_count
[(int) SH_ARG_INT
]
5242 < NPARM_REGS (SImode
))
5244 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
5248 if ((! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
5250 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
5254 f_next_o
= TYPE_FIELDS (va_list_type_node
);
5255 f_next_o_limit
= TREE_CHAIN (f_next_o
);
5256 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
5257 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
5258 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
5260 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
5261 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
5262 valist
, f_next_o_limit
);
5263 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
);
5264 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
5265 valist
, f_next_fp_limit
);
5266 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
5267 valist
, f_next_stack
);
5269 /* Call __builtin_saveregs. */
5270 u
= make_tree (ptr_type_node
, expand_builtin_saveregs ());
5271 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
5272 TREE_SIDE_EFFECTS (t
) = 1;
5273 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5275 nfp
= current_function_args_info
.arg_count
[SH_ARG_FLOAT
];
5280 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5281 build_int_2 (UNITS_PER_WORD
* nfp
, 0)));
5282 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
5283 TREE_SIDE_EFFECTS (t
) = 1;
5284 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5286 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
5287 TREE_SIDE_EFFECTS (t
) = 1;
5288 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5290 nint
= current_function_args_info
.arg_count
[SH_ARG_INT
];
5295 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5296 build_int_2 (UNITS_PER_WORD
* nint
, 0)));
5297 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
5298 TREE_SIDE_EFFECTS (t
) = 1;
5299 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5301 u
= make_tree (ptr_type_node
, nextarg
);
5302 if (! stdarg_p
&& (nint
== 0 || nfp
== 0))
5304 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5305 build_int_2 (-UNITS_PER_WORD
, -1)));
5307 t
= build (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
5308 TREE_SIDE_EFFECTS (t
) = 1;
5309 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5312 /* Implement `va_arg'. */
5315 sh_va_arg (valist
, type
)
5318 HOST_WIDE_INT size
, rsize
;
5319 tree tmp
, pptr_type_node
;
5322 int pass_by_ref
= MUST_PASS_IN_STACK (TYPE_MODE (type
), type
);
5324 size
= int_size_in_bytes (type
);
5325 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5326 pptr_type_node
= build_pointer_type (ptr_type_node
);
5329 type
= build_pointer_type (type
);
5331 if (! TARGET_SH5
&& (TARGET_SH3E
|| TARGET_SH4
) && ! TARGET_HITACHI
)
5333 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5334 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
5336 rtx lab_false
, lab_over
;
5338 f_next_o
= TYPE_FIELDS (va_list_type_node
);
5339 f_next_o_limit
= TREE_CHAIN (f_next_o
);
5340 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
5341 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
5342 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
5344 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
5345 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
5346 valist
, f_next_o_limit
);
5347 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
5349 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
5350 valist
, f_next_fp_limit
);
5351 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
5352 valist
, f_next_stack
);
5356 pass_as_float
= ((TREE_CODE (type
) == REAL_TYPE
&& size
<= 8)
5357 || (TREE_CODE (type
) == COMPLEX_TYPE
5358 && TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
5363 pass_as_float
= (TREE_CODE (type
) == REAL_TYPE
&& size
== 4);
5366 addr_rtx
= gen_reg_rtx (Pmode
);
5367 lab_false
= gen_label_rtx ();
5368 lab_over
= gen_label_rtx ();
5373 = current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
5374 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
5376 emit_cmp_and_jump_insns (expand_expr (next_fp
, NULL_RTX
, Pmode
,
5378 expand_expr (next_fp_limit
, NULL_RTX
,
5379 Pmode
, EXPAND_NORMAL
),
5380 GE
, const1_rtx
, Pmode
, 1, lab_false
);
5382 if (TYPE_ALIGN (type
) > BITS_PER_WORD
5383 || (((TREE_CODE (type
) == REAL_TYPE
&& size
== 8) || size
== 16)
5384 && (n_floatregs
& 1)))
5386 tmp
= build (BIT_AND_EXPR
, ptr_type_node
, next_fp
,
5387 build_int_2 (UNITS_PER_WORD
, 0));
5388 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_fp
, tmp
);
5389 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, tmp
);
5390 TREE_SIDE_EFFECTS (tmp
) = 1;
5391 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5394 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_fp
);
5395 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5397 emit_move_insn (addr_rtx
, r
);
5399 emit_jump_insn (gen_jump (lab_over
));
5401 emit_label (lab_false
);
5403 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
5404 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5406 emit_move_insn (addr_rtx
, r
);
5410 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_o
,
5411 build_int_2 (rsize
, 0));
5413 emit_cmp_and_jump_insns (expand_expr (tmp
, NULL_RTX
, Pmode
,
5415 expand_expr (next_o_limit
, NULL_RTX
,
5416 Pmode
, EXPAND_NORMAL
),
5417 GT
, const1_rtx
, Pmode
, 1, lab_false
);
5419 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_o
);
5420 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5422 emit_move_insn (addr_rtx
, r
);
5424 emit_jump_insn (gen_jump (lab_over
));
5426 emit_label (lab_false
);
5428 if (size
> 4 && ! TARGET_SH4
)
5430 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, next_o_limit
);
5431 TREE_SIDE_EFFECTS (tmp
) = 1;
5432 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5435 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
5436 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5438 emit_move_insn (addr_rtx
, r
);
5441 emit_label (lab_over
);
5443 tmp
= make_tree (pptr_type_node
, addr_rtx
);
5444 valist
= build1 (INDIRECT_REF
, ptr_type_node
, tmp
);
5447 /* ??? In va-sh.h, there had been code to make values larger than
5448 size 8 indirect. This does not match the FUNCTION_ARG macros. */
5450 result
= std_expand_builtin_va_arg (valist
, type
);
5453 #ifdef POINTERS_EXTEND_UNSIGNED
5454 if (GET_MODE (addr
) != Pmode
)
5455 addr
= convert_memory_address (Pmode
, result
);
5457 result
= gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, result
));
5458 set_mem_alias_set (result
, get_varargs_alias_set ());
5460 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
5461 argument to the varargs alias set. */
5465 /* Define the offset between two registers, one to be eliminated, and
5466 the other its replacement, at the start of a routine. */
5469 initial_elimination_offset (from
, to
)
5474 int regs_saved_rounding
= 0;
5475 int total_saved_regs_space
;
5476 int total_auto_space
;
5477 int save_flags
= target_flags
;
5480 HOST_WIDE_INT live_regs_mask
[(FIRST_PSEUDO_REGISTER
+ 31) / 32];
5481 calc_live_regs (®s_saved
, live_regs_mask
);
5482 regs_saved
+= SHMEDIA_REGS_STACK_ADJUST ();
5483 if (TARGET_SH5
&& regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
5484 regs_saved_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
5485 - regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
5487 total_auto_space
= rounded_frame_size (regs_saved
) - regs_saved_rounding
;
5488 copy_flags
= target_flags
;
5489 target_flags
= save_flags
;
5491 total_saved_regs_space
= regs_saved
+ regs_saved_rounding
;
5493 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
5494 return total_saved_regs_space
+ total_auto_space
5495 + current_function_args_info
.byref_regs
* 8;
5497 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5498 return total_saved_regs_space
+ total_auto_space
5499 + current_function_args_info
.byref_regs
* 8;
5501 /* Initial gap between fp and sp is 0. */
5502 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5505 if (from
== RETURN_ADDRESS_POINTER_REGNUM
5506 && (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
))
5509 int i
, n
= total_saved_regs_space
;
5511 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
5513 n
+= total_auto_space
;
5515 /* If it wasn't saved, there's not much we can do. */
5516 if ((live_regs_mask
[pr_reg
/ 32] & (1 << (pr_reg
% 32))) == 0)
5519 target_flags
= copy_flags
;
5521 /* We loop twice: first, check 8-byte aligned registers,
5522 that are stored in the higher addresses, that are known
5523 to be aligned. Then, check 32-bit registers that don't
5524 need 8-byte alignment. */
5525 for (align
= 1; align
>= 0; align
--)
5526 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
5527 if (live_regs_mask
[i
/32] & (1 << (i
% 32)))
5529 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
5531 if (mode
== SFmode
&& (i
% 2) == 1
5532 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
5533 && (live_regs_mask
[(i
^ 1) / 32]
5534 & (1 << ((i
^ 1) % 32))))
5540 /* If we're doing the aligned pass and this is not aligned,
5541 or we're doing the unaligned pass and this is aligned,
5543 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
5547 n
-= GET_MODE_SIZE (mode
);
5551 target_flags
= save_flags
;
5559 return total_auto_space
;
5564 /* Handle machine specific pragmas to be semi-compatible with Hitachi
5568 sh_pr_interrupt (pfile
)
5569 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
5571 pragma_interrupt
= 1;
5576 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
5578 pragma_interrupt
= pragma_trapa
= 1;
5582 sh_pr_nosave_low_regs (pfile
)
5583 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
5585 pragma_nosave_low_regs
= 1;
5588 /* Generate 'handle_interrupt' attribute for decls */
5591 sh_insert_attributes (node
, attributes
)
5595 if (! pragma_interrupt
5596 || TREE_CODE (node
) != FUNCTION_DECL
)
5599 /* We are only interested in fields. */
5600 if (TREE_CODE_CLASS (TREE_CODE (node
)) != 'd')
5603 /* Add a 'handle_interrupt' attribute. */
5604 * attributes
= tree_cons (get_identifier ("interrupt_handler"), NULL
, * attributes
);
5609 /* Supported attributes:
5611 interrupt_handler -- specifies this function is an interrupt handler.
5613 sp_switch -- specifies an alternate stack for an interrupt handler
5616 trap_exit -- use a trapa to exit an interrupt function instead of
5617 an rte instruction. */
5619 const struct attribute_spec sh_attribute_table
[] =
5621 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5622 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute
},
5623 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute
},
5624 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute
},
5625 { NULL
, 0, 0, false, false, false, NULL
}
5628 /* Handle an "interrupt_handler" attribute; arguments as in
5629 struct attribute_spec.handler. */
5631 sh_handle_interrupt_handler_attribute (node
, name
, args
, flags
, no_add_attrs
)
5634 tree args ATTRIBUTE_UNUSED
;
5635 int flags ATTRIBUTE_UNUSED
;
5638 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5640 warning ("`%s' attribute only applies to functions",
5641 IDENTIFIER_POINTER (name
));
5642 *no_add_attrs
= true;
5648 /* Handle an "sp_switch" attribute; arguments as in
5649 struct attribute_spec.handler. */
5651 sh_handle_sp_switch_attribute (node
, name
, args
, flags
, no_add_attrs
)
5655 int flags ATTRIBUTE_UNUSED
;
5658 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5660 warning ("`%s' attribute only applies to functions",
5661 IDENTIFIER_POINTER (name
));
5662 *no_add_attrs
= true;
5664 else if (!pragma_interrupt
)
5666 /* The sp_switch attribute only has meaning for interrupt functions. */
5667 warning ("`%s' attribute only applies to interrupt functions",
5668 IDENTIFIER_POINTER (name
));
5669 *no_add_attrs
= true;
5671 else if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
5673 /* The argument must be a constant string. */
5674 warning ("`%s' attribute argument not a string constant",
5675 IDENTIFIER_POINTER (name
));
5676 *no_add_attrs
= true;
5680 sp_switch
= gen_rtx_SYMBOL_REF (VOIDmode
,
5681 TREE_STRING_POINTER (TREE_VALUE (args
)));
5687 /* Handle an "trap_exit" attribute; arguments as in
5688 struct attribute_spec.handler. */
5690 sh_handle_trap_exit_attribute (node
, name
, args
, flags
, no_add_attrs
)
5694 int flags ATTRIBUTE_UNUSED
;
5697 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5699 warning ("`%s' attribute only applies to functions",
5700 IDENTIFIER_POINTER (name
));
5701 *no_add_attrs
= true;
5703 else if (!pragma_interrupt
)
5705 /* The trap_exit attribute only has meaning for interrupt functions. */
5706 warning ("`%s' attribute only applies to interrupt functions",
5707 IDENTIFIER_POINTER (name
));
5708 *no_add_attrs
= true;
5710 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
5712 /* The argument must be a constant integer. */
5713 warning ("`%s' attribute argument not an integer constant",
5714 IDENTIFIER_POINTER (name
));
5715 *no_add_attrs
= true;
5719 trap_exit
= TREE_INT_CST_LOW (TREE_VALUE (args
));
5726 /* Predicates used by the templates. */
5728 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
5729 Used only in general_movsrc_operand. */
5732 system_reg_operand (op
, mode
)
5734 enum machine_mode mode ATTRIBUTE_UNUSED
;
5746 /* Returns 1 if OP can be source of a simple move operation.
5747 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
5748 invalid as are subregs of system registers. */
5751 general_movsrc_operand (op
, mode
)
5753 enum machine_mode mode
;
5755 if (GET_CODE (op
) == MEM
)
5757 rtx inside
= XEXP (op
, 0);
5758 if (GET_CODE (inside
) == CONST
)
5759 inside
= XEXP (inside
, 0);
5761 if (GET_CODE (inside
) == LABEL_REF
)
5764 if (GET_CODE (inside
) == PLUS
5765 && GET_CODE (XEXP (inside
, 0)) == LABEL_REF
5766 && GET_CODE (XEXP (inside
, 1)) == CONST_INT
)
5769 /* Only post inc allowed. */
5770 if (GET_CODE (inside
) == PRE_DEC
)
5774 if ((mode
== QImode
|| mode
== HImode
)
5775 && (GET_CODE (op
) == SUBREG
5776 && GET_CODE (XEXP (op
, 0)) == REG
5777 && system_reg_operand (XEXP (op
, 0), mode
)))
5780 return general_operand (op
, mode
);
5783 /* Returns 1 if OP can be a destination of a move.
5784 Same as general_operand, but no preinc allowed. */
5787 general_movdst_operand (op
, mode
)
5789 enum machine_mode mode
;
5791 /* Only pre dec allowed. */
5792 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
5795 return general_operand (op
, mode
);
5798 /* Accept a register, but not a subreg of any kind. This allows us to
5799 avoid pathological cases in reload wrt data movement common in
5800 int->fp conversion. */
5803 reg_no_subreg_operand (op
, mode
)
5805 enum machine_mode mode
;
5807 if (GET_CODE (op
) == SUBREG
)
5809 return register_operand (op
, mode
);
5812 /* Returns 1 if OP is a normal arithmetic register. */
5815 arith_reg_operand (op
, mode
)
5817 enum machine_mode mode
;
5819 if (register_operand (op
, mode
))
5823 if (GET_CODE (op
) == REG
)
5825 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
5826 regno
= REGNO (SUBREG_REG (op
));
5830 return (regno
!= T_REG
&& regno
!= PR_REG
5831 && ! TARGET_REGISTER_P (regno
)
5832 && (regno
!= FPUL_REG
|| TARGET_SH4
)
5833 && regno
!= MACH_REG
&& regno
!= MACL_REG
);
5839 fp_arith_reg_operand (op
, mode
)
5841 enum machine_mode mode
;
5843 if (register_operand (op
, mode
))
5847 if (GET_CODE (op
) == REG
)
5849 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
5850 regno
= REGNO (SUBREG_REG (op
));
5854 return (regno
>= FIRST_PSEUDO_REGISTER
5855 || FP_REGISTER_P (regno
));
5860 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
5863 arith_operand (op
, mode
)
5865 enum machine_mode mode
;
5867 if (arith_reg_operand (op
, mode
))
5872 /* FIXME: We should be checking whether the CONST_INT fits in a
5873 CONST_OK_FOR_J here, but this causes reload_cse to crash when
5874 attempting to transform a sequence of two 64-bit sets of the
5875 same register from literal constants into a set and an add,
5876 when the difference is too wide for an add. */
5877 if (GET_CODE (op
) == CONST_INT
5878 || EXTRA_CONSTRAINT_S (op
))
5883 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
5889 /* Returns 1 if OP is a valid source operand for a compare insn. */
5892 arith_reg_or_0_operand (op
, mode
)
5894 enum machine_mode mode
;
5896 if (arith_reg_operand (op
, mode
))
5899 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_N (INTVAL (op
)))
5905 /* Return 1 if OP is a valid source operand for an SHmedia operation
5906 that takes either a register or a 6-bit immediate. */
5909 shmedia_6bit_operand (op
, mode
)
5911 enum machine_mode mode
;
5913 return (arith_reg_operand (op
, mode
)
5914 || (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_O (INTVAL (op
))));
5917 /* Returns 1 if OP is a valid source operand for a logical operation. */
5920 logical_operand (op
, mode
)
5922 enum machine_mode mode
;
5924 if (arith_reg_operand (op
, mode
))
5929 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_P (INTVAL (op
)))
5934 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
5940 /* Nonzero if OP is a floating point value with value 0.0. */
5943 fp_zero_operand (op
)
5948 if (GET_MODE (op
) != SFmode
)
5951 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
5952 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
5955 /* Nonzero if OP is a floating point value with value 1.0. */
5963 if (GET_MODE (op
) != SFmode
)
5966 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
5967 return REAL_VALUES_EQUAL (r
, dconst1
);
5970 /* For -m4 and -m4-single-only, mode switching is used. If we are
5971 compiling without -mfmovd, movsf_ie isn't taken into account for
5972 mode switching. We could check in machine_dependent_reorg for
5973 cases where we know we are in single precision mode, but there is
5974 interface to find that out during reload, so we must avoid
5975 choosing an fldi alternative during reload and thus failing to
5976 allocate a scratch register for the constant loading. */
5980 return ! TARGET_SH4
|| TARGET_FMOVD
|| reload_completed
;
5984 tertiary_reload_operand (op
, mode
)
5986 enum machine_mode mode ATTRIBUTE_UNUSED
;
5988 enum rtx_code code
= GET_CODE (op
);
5989 return code
== MEM
|| (TARGET_SH4
&& code
== CONST_DOUBLE
);
5993 fpscr_operand (op
, mode
)
5995 enum machine_mode mode ATTRIBUTE_UNUSED
;
5997 return (GET_CODE (op
) == REG
&& REGNO (op
) == FPSCR_REG
5998 && GET_MODE (op
) == PSImode
);
6002 fpul_operand (op
, mode
)
6004 enum machine_mode mode
;
6007 return fp_arith_reg_operand (op
, mode
);
6009 return (GET_CODE (op
) == REG
6010 && (REGNO (op
) == FPUL_REG
|| REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
6011 && GET_MODE (op
) == mode
);
6015 symbol_ref_operand (op
, mode
)
6017 enum machine_mode mode ATTRIBUTE_UNUSED
;
6019 return (GET_CODE (op
) == SYMBOL_REF
);
6023 commutative_float_operator (op
, mode
)
6025 enum machine_mode mode
;
6027 if (GET_MODE (op
) != mode
)
6029 switch (GET_CODE (op
))
6041 noncommutative_float_operator (op
, mode
)
6043 enum machine_mode mode
;
6045 if (GET_MODE (op
) != mode
)
6047 switch (GET_CODE (op
))
6059 binary_float_operator (op
, mode
)
6061 enum machine_mode mode
;
6063 if (GET_MODE (op
) != mode
)
6065 switch (GET_CODE (op
))
6078 /* Accept pseudos and branch target registers. */
6080 target_reg_operand (op
, mode
)
6082 enum machine_mode mode
;
6085 || GET_MODE (op
) != DImode
)
6088 if (GET_CODE (op
) == SUBREG
)
6091 if (GET_CODE (op
) != REG
)
6094 /* We must protect ourselves from matching pseudos that are virtual
6095 register, because they will eventually be replaced with hardware
6096 registers that aren't branch-target registers. */
6097 if (REGNO (op
) > LAST_VIRTUAL_REGISTER
6098 || TARGET_REGISTER_P (REGNO (op
)))
6104 /* Same as target_reg_operand, except that label_refs and symbol_refs
6105 are accepted before reload. */
6107 target_operand (op
, mode
)
6109 enum machine_mode mode
;
6114 if ((GET_MODE (op
) == DImode
|| GET_MODE (op
) == VOIDmode
)
6115 && EXTRA_CONSTRAINT_T (op
))
6116 return ! reload_completed
;
6118 return target_reg_operand (op
, mode
);
6122 /* Return the destination address of a branch. */
6125 branch_dest (branch
)
6128 rtx dest
= SET_SRC (PATTERN (branch
));
6131 if (GET_CODE (dest
) == IF_THEN_ELSE
)
6132 dest
= XEXP (dest
, 1);
6133 dest
= XEXP (dest
, 0);
6134 dest_uid
= INSN_UID (dest
);
6135 return INSN_ADDRESSES (dest_uid
);
6138 /* Return non-zero if REG is not used after INSN.
6139 We assume REG is a reload reg, and therefore does
6140 not live past labels. It may live past calls or jumps though. */
6142 reg_unused_after (reg
, insn
)
6149 /* If the reg is set by this instruction, then it is safe for our
6150 case. Disregard the case where this is a store to memory, since
6151 we are checking a register used in the store address. */
6152 set
= single_set (insn
);
6153 if (set
&& GET_CODE (SET_DEST (set
)) != MEM
6154 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6157 while ((insn
= NEXT_INSN (insn
)))
6159 code
= GET_CODE (insn
);
6162 /* If this is a label that existed before reload, then the register
6163 if dead here. However, if this is a label added by reorg, then
6164 the register may still be live here. We can't tell the difference,
6165 so we just ignore labels completely. */
6166 if (code
== CODE_LABEL
)
6171 if (code
== JUMP_INSN
)
6174 /* If this is a sequence, we must handle them all at once.
6175 We could have for instance a call that sets the target register,
6176 and an insn in a delay slot that uses the register. In this case,
6177 we must return 0. */
6178 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
6183 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
6185 rtx this_insn
= XVECEXP (PATTERN (insn
), 0, i
);
6186 rtx set
= single_set (this_insn
);
6188 if (GET_CODE (this_insn
) == CALL_INSN
)
6190 else if (GET_CODE (this_insn
) == JUMP_INSN
)
6192 if (INSN_ANNULLED_BRANCH_P (this_insn
))
6197 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
6199 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6201 if (GET_CODE (SET_DEST (set
)) != MEM
)
6207 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
6212 else if (code
== JUMP_INSN
)
6215 else if (GET_RTX_CLASS (code
) == 'i')
6217 rtx set
= single_set (insn
);
6219 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
6221 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6222 return GET_CODE (SET_DEST (set
)) != MEM
;
6223 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
6227 if (code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
6238 static rtx fpscr_rtx
;
6242 fpscr_rtx
= gen_rtx (REG
, PSImode
, FPSCR_REG
);
6243 REG_USERVAR_P (fpscr_rtx
) = 1;
6244 ggc_add_rtx_root (&fpscr_rtx
, 1);
6245 mark_user_reg (fpscr_rtx
);
6247 if (! reload_completed
|| mdep_reorg_phase
!= SH_AFTER_MDEP_REORG
)
6248 mark_user_reg (fpscr_rtx
);
6267 expand_sf_unop (fun
, operands
)
6268 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
6271 emit_sf_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
6275 expand_sf_binop (fun
, operands
)
6276 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
6279 emit_sf_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
6284 expand_df_unop (fun
, operands
)
6285 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
6288 emit_df_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
6292 expand_df_binop (fun
, operands
)
6293 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
6296 emit_df_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
6300 /* ??? gcc does flow analysis strictly after common subexpression
6301 elimination. As a result, common subespression elimination fails
6302 when there are some intervening statements setting the same register.
6303 If we did nothing about this, this would hurt the precision switching
6304 for SH4 badly. There is some cse after reload, but it is unable to
6305 undo the extra register pressure from the unused instructions, and
6306 it cannot remove auto-increment loads.
6308 A C code example that shows this flow/cse weakness for (at least) SH
6309 and sparc (as of gcc ss-970706) is this:
6323 So we add another pass before common subexpression elimination, to
6324 remove assignments that are dead due to a following assignment in the
6325 same basic block. */
6328 mark_use (x
, reg_set_block
)
6329 rtx x
, *reg_set_block
;
6335 code
= GET_CODE (x
);
6340 int regno
= REGNO (x
);
6341 int nregs
= (regno
< FIRST_PSEUDO_REGISTER
6342 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
))
6346 reg_set_block
[regno
+ nregs
- 1] = 0;
6353 rtx dest
= SET_DEST (x
);
6355 if (GET_CODE (dest
) == SUBREG
)
6356 dest
= SUBREG_REG (dest
);
6357 if (GET_CODE (dest
) != REG
)
6358 mark_use (dest
, reg_set_block
);
6359 mark_use (SET_SRC (x
), reg_set_block
);
6366 const char *fmt
= GET_RTX_FORMAT (code
);
6368 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6371 mark_use (XEXP (x
, i
), reg_set_block
);
6372 else if (fmt
[i
] == 'E')
6373 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6374 mark_use (XVECEXP (x
, i
, j
), reg_set_block
);
6381 static rtx get_free_reg
PARAMS ((HARD_REG_SET
));
6383 /* This function returns a register to use to load the address to load
6384 the fpscr from. Currently it always returns r1 or r7, but when we are
6385 able to use pseudo registers after combine, or have a better mechanism
6386 for choosing a register, it should be done here. */
6387 /* REGS_LIVE is the liveness information for the point for which we
6388 need this allocation. In some bare-bones exit blocks, r1 is live at the
6389 start. We can even have all of r0..r3 being live:
6390 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
6391 INSN before which new insns are placed with will clobber the register
6392 we return. If a basic block consists only of setting the return value
6393 register to a pseudo and using that register, the return value is not
6394 live before or after this block, yet we we'll insert our insns right in
6398 get_free_reg (regs_live
)
6399 HARD_REG_SET regs_live
;
6401 if (! TEST_HARD_REG_BIT (regs_live
, 1))
6402 return gen_rtx_REG (Pmode
, 1);
6404 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
6405 there shouldn't be anything but a jump before the function end. */
6406 if (! TEST_HARD_REG_BIT (regs_live
, 7))
6407 return gen_rtx_REG (Pmode
, 7);
6412 /* This function will set the fpscr from memory.
6413 MODE is the mode we are setting it to. */
6415 fpscr_set_from_mem (mode
, regs_live
)
6417 HARD_REG_SET regs_live
;
6419 enum attr_fp_mode fp_mode
= mode
;
6420 rtx addr_reg
= get_free_reg (regs_live
);
6422 if (fp_mode
== (enum attr_fp_mode
) NORMAL_MODE (FP_MODE
))
6423 emit_insn (gen_fpu_switch1 (addr_reg
));
6425 emit_insn (gen_fpu_switch0 (addr_reg
));
6428 /* Is the given character a logical line separator for the assembler? */
6429 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
6430 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
6434 sh_insn_length_adjustment (insn
)
6437 /* Instructions with unfilled delay slots take up an extra two bytes for
6438 the nop in the delay slot. */
6439 if (((GET_CODE (insn
) == INSN
6440 && GET_CODE (PATTERN (insn
)) != USE
6441 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6442 || GET_CODE (insn
) == CALL_INSN
6443 || (GET_CODE (insn
) == JUMP_INSN
6444 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
6445 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
))
6446 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
6447 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
6450 /* sh-dsp parallel processing insn take four bytes instead of two. */
6452 if (GET_CODE (insn
) == INSN
)
6455 rtx body
= PATTERN (insn
);
6456 const char *template;
6458 int maybe_label
= 1;
6460 if (GET_CODE (body
) == ASM_INPUT
)
6461 template = XSTR (body
, 0);
6462 else if (asm_noperands (body
) >= 0)
6464 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
);
6473 while (c
== ' ' || c
== '\t');
6474 /* all sh-dsp parallel-processing insns start with p.
6475 The only non-ppi sh insn starting with p is pref.
6476 The only ppi starting with pr is prnd. */
6477 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", template, 2))
6479 /* The repeat pseudo-insn expands two three insns, a total of
6480 six bytes in size. */
6481 else if ((c
== 'r' || c
== 'R')
6482 && ! strncasecmp ("epeat", template, 5))
6484 while (c
&& c
!= '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
))
6486 /* If this is a label, it is obviously not a ppi insn. */
6487 if (c
== ':' && maybe_label
)
6492 else if (c
== '\'' || c
== '"')
6497 maybe_label
= c
!= ':';
6505 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
6506 isn't protected by a PIC unspec. */
6508 nonpic_symbol_mentioned_p (x
)
6511 register const char *fmt
;
6514 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
6515 || GET_CODE (x
) == PC
)
6518 /* We don't want to look into the possible MEM location of a
6519 CONST_DOUBLE, since we're not going to use it, in general. */
6520 if (GET_CODE (x
) == CONST_DOUBLE
)
6523 if (GET_CODE (x
) == UNSPEC
6524 && (XINT (x
, 1) == UNSPEC_PIC
6525 || XINT (x
, 1) == UNSPEC_GOT
6526 || XINT (x
, 1) == UNSPEC_GOTOFF
6527 || XINT (x
, 1) == UNSPEC_GOTPLT
6528 || XINT (x
, 1) == UNSPEC_PLT
))
6531 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6532 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6538 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6539 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
6542 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
6549 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
6550 @GOTOFF in `reg'. */
6552 legitimize_pic_address (orig
, mode
, reg
)
6554 enum machine_mode mode ATTRIBUTE_UNUSED
;
6557 if (GET_CODE (orig
) == LABEL_REF
6558 || (GET_CODE (orig
) == SYMBOL_REF
6559 && (CONSTANT_POOL_ADDRESS_P (orig
)
6560 /* SYMBOL_REF_FLAG is set on static symbols. */
6561 || SYMBOL_REF_FLAG (orig
))))
6564 reg
= gen_reg_rtx (Pmode
);
6566 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
6569 else if (GET_CODE (orig
) == SYMBOL_REF
)
6572 reg
= gen_reg_rtx (Pmode
);
6574 emit_insn (gen_symGOT2reg (reg
, orig
));
6580 /* Mark the use of a constant in the literal table. If the constant
6581 has multiple labels, make it unique. */
6582 static rtx
mark_constant_pool_use (x
)
6585 rtx insn
, lab
, pattern
;
6590 switch (GET_CODE (x
))
6600 /* Get the first label in the list of labels for the same constant
6601 and delete another labels in the list. */
6603 for (insn
= PREV_INSN (x
); insn
; insn
= PREV_INSN (insn
))
6605 if (GET_CODE (insn
) != CODE_LABEL
6606 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
6611 for (insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
6612 INSN_DELETED_P (insn
) = 1;
6614 /* Mark constants in a window. */
6615 for (insn
= NEXT_INSN (x
); insn
; insn
= NEXT_INSN (insn
))
6617 if (GET_CODE (insn
) != INSN
)
6620 pattern
= PATTERN (insn
);
6621 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
6624 switch (XINT (pattern
, 1))
6626 case UNSPECV_CONST2
:
6627 case UNSPECV_CONST4
:
6628 case UNSPECV_CONST8
:
6629 XVECEXP (pattern
, 0, 1) = const1_rtx
;
6631 case UNSPECV_WINDOW_END
:
6632 if (XVECEXP (pattern
, 0, 0) == x
)
6635 case UNSPECV_CONST_END
:
6645 /* Return true if it's possible to redirect BRANCH1 to the destination
6646 of an unconditional jump BRANCH2. We only want to do this if the
6647 resulting branch will have a short displacement. */
6649 sh_can_redirect_branch (branch1
, branch2
)
6653 if (flag_expensive_optimizations
&& simplejump_p (branch2
))
6655 rtx dest
= XEXP (SET_SRC (single_set (branch2
)), 0);
6659 for (distance
= 0, insn
= NEXT_INSN (branch1
);
6660 insn
&& distance
< 256;
6661 insn
= PREV_INSN (insn
))
6666 distance
+= get_attr_length (insn
);
6668 for (distance
= 0, insn
= NEXT_INSN (branch1
);
6669 insn
&& distance
< 256;
6670 insn
= NEXT_INSN (insn
))
6675 distance
+= get_attr_length (insn
);
6681 #ifndef OBJECT_FORMAT_ELF
6683 sh_asm_named_section (name
, flags
)
6685 unsigned int flags ATTRIBUTE_UNUSED
;
6687 /* ??? Perhaps we should be using default_coff_asm_named_section. */
6688 fprintf (asm_out_file
, "\t.section %s\n", name
);
6690 #endif /* ! OBJECT_FORMAT_ELF */
6692 /* A C statement (sans semicolon) to update the integer variable COST
6693 based on the relationship between INSN that is dependent on
6694 DEP_INSN through the dependence LINK. The default is to make no
6695 adjustment to COST. This can be used for example to specify to
6696 the scheduler that an output- or anti-dependence does not incur
6697 the same cost as a data-dependence. */
6699 sh_adjust_cost (insn
, link
, dep_insn
, cost
)
6701 rtx link ATTRIBUTE_UNUSED
;
6707 if (GET_CODE(insn
) == CALL_INSN
)
6709 /* The only input for a call that is timing-critical is the
6710 function's address. */
6711 rtx call
= PATTERN (insn
);
6713 if (GET_CODE (call
) == PARALLEL
)
6714 call
= XVECEXP (call
, 0 ,0);
6715 if (GET_CODE (call
) == SET
)
6716 call
= SET_SRC (call
);
6717 if (GET_CODE (call
) == CALL
&& GET_CODE (XEXP (call
, 0)) == MEM
6718 && ! reg_set_p (XEXP (XEXP (call
, 0), 0), dep_insn
))
6721 /* All sfunc calls are parallels with at least four components.
6722 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
6723 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
6724 && XVECLEN (PATTERN (insn
), 0) >= 4
6725 && (reg
= sfunc_uses_reg (insn
)))
6727 /* Likewise, the most timing critical input for an sfuncs call
6728 is the function address. However, sfuncs typically start
6729 using their arguments pretty quickly.
6730 Assume a four cycle delay before they are needed. */
6731 if (! reg_set_p (reg
, dep_insn
))
6732 cost
-= TARGET_SUPERSCALAR
? 40 : 4;
6734 /* Adjust load_si / pcload_si type insns latency. Use the known
6735 nominal latency and form of the insn to speed up the check. */
6737 && GET_CODE (PATTERN (dep_insn
)) == SET
6738 /* Latency for dmpy type insns is also 3, so check the that
6739 it's actually a move insn. */
6740 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn
)), SImode
))
6743 && GET_CODE (PATTERN (dep_insn
)) == SET
6744 && GET_MODE (SET_SRC (PATTERN (dep_insn
))) == SImode
)
6750 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
6751 'special function' patterns (type sfunc) that clobber pr, but that
6752 do not look like function calls to leaf_function_p. Hence we must
6753 do this extra check. */
6757 return REG_N_SETS (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
6760 /* This Function Returns non zero if DFA based scheduler
6761 interface is to be used.At present supported only for
6764 sh_use_dfa_interface()
6772 /* This function returns "2" that signifies dual issue
6773 for SH4 processor.To be used by DFA pipeline description. */
6783 /* SHmedia requires registers for branches, so we can't generate new
6784 branches past reload. */
6786 sh_cannot_modify_jumps_p ()
6788 return (TARGET_SHMEDIA
&& (reload_in_progress
|| reload_completed
));
6792 sh_ms_bitfield_layout_p (record_type
)
6793 tree record_type ATTRIBUTE_UNUSED
;
6798 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
6799 may access it using GOTOFF instead of GOT. */
6802 sh_encode_section_info (decl
, first
)
6809 rtl
= DECL_RTL (decl
);
6811 rtl
= TREE_CST_RTL (decl
);
6812 if (GET_CODE (rtl
) != MEM
)
6814 symbol
= XEXP (rtl
, 0);
6815 if (GET_CODE (symbol
) != SYMBOL_REF
)
6820 SYMBOL_REF_FLAG (symbol
) =
6821 (TREE_CODE_CLASS (TREE_CODE (decl
)) != 'd'
6822 || MODULE_LOCAL_P (decl
)
6823 || ! TREE_PUBLIC (decl
));
6826 if (TARGET_SH5
&& first
&& TREE_CODE (decl
) != FUNCTION_DECL
)
6827 XEXP (rtl
, 0) = gen_datalabel_ref (symbol
);
6830 /* Undo the effects of the above. */
6833 sh_strip_name_encoding (str
)
6836 STRIP_DATALABEL_ENCODING (str
, str
);