1 /* Output routines for GCC for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
34 #include "hard-reg-set.h"
36 #include "insn-attr.h"
40 #include "integrate.h"
43 #include "target-def.h"
45 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
47 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
48 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
50 /* These are some macros to abstract register modes. */
51 #define CONST_OK_FOR_ADD(size) \
52 (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size))
53 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
54 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
55 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
57 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
58 int current_function_interrupt
;
60 /* ??? The pragma interrupt support will not work for SH3. */
61 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
62 output code for the next function appropriate for an interrupt handler. */
65 /* This is set by the trap_exit attribute for functions. It specifies
66 a trap number to be used in a trapa instruction at function exit
67 (instead of an rte instruction). */
70 /* This is used by the sp_switch attribute for functions. It specifies
71 a variable holding the address of the stack the interrupt function
72 should switch to/from at entry/exit. */
75 /* This is set by #pragma trapa, and is similar to the above, except that
76 the compiler doesn't emit code to preserve all registers. */
77 static int pragma_trapa
;
79 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
80 which has a separate set of low regs for User and Supervisor modes.
81 This should only be used for the lowest level of interrupts. Higher levels
82 of interrupts must save the registers in case they themselves are
84 int pragma_nosave_low_regs
;
86 /* This is used for communication between SETUP_INCOMING_VARARGS and
87 sh_expand_prologue. */
88 int current_function_anonymous_args
;
90 /* Global variables for machine-dependent things. */
92 /* Which cpu are we scheduling for. */
93 enum processor_type sh_cpu
;
95 /* Saved operands from the last compare to use when we generate an scc
101 /* Provides the class number of the smallest class containing
104 int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
106 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
107 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
108 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
109 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
110 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
111 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
112 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
113 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
114 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
115 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
116 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
117 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
118 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
119 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
120 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
121 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
122 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
123 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
124 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
125 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
126 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
127 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
128 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
129 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
130 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
131 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
132 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
133 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
134 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
135 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
136 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
137 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
138 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
139 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
140 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
141 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
142 NO_REGS
, GENERAL_REGS
, PR_REGS
, T_REGS
,
143 MAC_REGS
, MAC_REGS
, FPUL_REGS
, FPSCR_REGS
,
147 char sh_register_names
[FIRST_PSEUDO_REGISTER
] \
148 [MAX_REGISTER_NAME_LENGTH
+ 1] = SH_REGISTER_NAMES_INITIALIZER
;
150 char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
151 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1]
152 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER
;
154 /* Provide reg_class from a letter such as appears in the machine
157 const enum reg_class reg_class_from_letter
[] =
159 /* a */ ALL_REGS
, /* b */ TARGET_REGS
, /* c */ FPSCR_REGS
, /* d */ DF_REGS
,
160 /* e */ NO_REGS
, /* f */ FP_REGS
, /* g */ NO_REGS
, /* h */ NO_REGS
,
161 /* i */ NO_REGS
, /* j */ NO_REGS
, /* k */ SIBCALL_REGS
, /* l */ PR_REGS
,
162 /* m */ NO_REGS
, /* n */ NO_REGS
, /* o */ NO_REGS
, /* p */ NO_REGS
,
163 /* q */ NO_REGS
, /* r */ NO_REGS
, /* s */ NO_REGS
, /* t */ T_REGS
,
164 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ FP0_REGS
, /* x */ MAC_REGS
,
165 /* y */ FPUL_REGS
, /* z */ R0_REGS
168 int assembler_dialect
;
170 static void split_branches
PARAMS ((rtx
));
171 static int branch_dest
PARAMS ((rtx
));
172 static void force_into
PARAMS ((rtx
, rtx
));
173 static void print_slot
PARAMS ((rtx
));
174 static rtx add_constant
PARAMS ((rtx
, enum machine_mode
, rtx
));
175 static void dump_table
PARAMS ((rtx
));
176 static int hi_const
PARAMS ((rtx
));
177 static int broken_move
PARAMS ((rtx
));
178 static int mova_p
PARAMS ((rtx
));
179 static rtx find_barrier
PARAMS ((int, rtx
, rtx
));
180 static int noncall_uses_reg
PARAMS ((rtx
, rtx
, rtx
*));
181 static rtx gen_block_redirect
PARAMS ((rtx
, int, int));
182 static void output_stack_adjust
PARAMS ((int, rtx
, int));
183 static void push
PARAMS ((int));
184 static void pop
PARAMS ((int));
185 static void push_regs
PARAMS ((HOST_WIDE_INT
*));
186 static void calc_live_regs
PARAMS ((int *, HOST_WIDE_INT
*));
187 static void mark_use
PARAMS ((rtx
, rtx
*));
188 static HOST_WIDE_INT rounded_frame_size
PARAMS ((int));
189 static rtx mark_constant_pool_use
PARAMS ((rtx
));
190 const struct attribute_spec sh_attribute_table
[];
191 static tree sh_handle_interrupt_handler_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
192 static tree sh_handle_sp_switch_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
193 static tree sh_handle_trap_exit_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
194 static void sh_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
195 static void sh_insert_attributes
PARAMS ((tree
, tree
*));
196 #ifndef OBJECT_FORMAT_ELF
197 static void sh_asm_named_section
PARAMS ((const char *, unsigned int));
199 static int sh_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
200 static bool sh_cannot_modify_jumps_p
PARAMS ((void));
202 static bool sh_ms_bitfield_layout_p
PARAMS ((tree
));
204 /* Initialize the GCC target structure. */
205 #undef TARGET_ATTRIBUTE_TABLE
206 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
208 /* The next two are used for debug info when compiling with -gdwarf. */
209 #undef TARGET_ASM_UNALIGNED_HI_OP
210 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
211 #undef TARGET_ASM_UNALIGNED_SI_OP
212 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
214 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
215 #undef TARGET_ASM_UNALIGNED_DI_OP
216 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
217 #undef TARGET_ASM_ALIGNED_DI_OP
218 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
220 #undef TARGET_ASM_FUNCTION_EPILOGUE
221 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
223 #undef TARGET_INSERT_ATTRIBUTES
224 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
226 #undef TARGET_SCHED_ADJUST_COST
227 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
229 #undef TARGET_CANNOT_MODIFY_JUMPS_P
230 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
232 #undef TARGET_MS_BITFIELD_LAYOUT_P
233 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
235 struct gcc_target targetm
= TARGET_INITIALIZER
;
237 /* Print the operand address in x to the stream. */
240 print_operand_address (stream
, x
)
244 switch (GET_CODE (x
))
248 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
253 rtx base
= XEXP (x
, 0);
254 rtx index
= XEXP (x
, 1);
256 switch (GET_CODE (index
))
259 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
260 reg_names
[true_regnum (base
)]);
266 int base_num
= true_regnum (base
);
267 int index_num
= true_regnum (index
);
269 fprintf (stream
, "@(r0,%s)",
270 reg_names
[MAX (base_num
, index_num
)]);
282 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
286 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
290 x
= mark_constant_pool_use (x
);
291 output_addr_const (stream
, x
);
296 /* Print operand x (an rtx) in assembler syntax to file stream
297 according to modifier code.
299 '.' print a .s if insn needs delay slot
300 ',' print LOCAL_LABEL_PREFIX
301 '@' print trap, rte or rts depending upon pragma interruptness
302 '#' output a nop if there is nothing to put in the delay slot
303 'O' print a constant without the #
304 'R' print the LSW of a dp value - changes if in little endian
305 'S' print the MSW of a dp value - changes if in little endian
306 'T' print the next word of a dp value - same as 'R' in big endian mode.
307 'M' print an `x' if `m' will print `base,index'.
308 'm' print a pair `base,offset' or `base,index', for LD and ST.
309 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
310 'o' output an operator. */
313 print_operand (stream
, x
, code
)
322 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
323 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
326 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
330 int interrupt_handler
;
332 if ((lookup_attribute
333 ("interrupt_handler",
334 DECL_ATTRIBUTES (current_function_decl
)))
336 interrupt_handler
= 1;
338 interrupt_handler
= 0;
341 fprintf (stream
, "trapa #%d", trap_exit
);
342 else if (interrupt_handler
)
343 fprintf (stream
, "rte");
345 fprintf (stream
, "rts");
349 /* Output a nop if there's nothing in the delay slot. */
350 if (dbr_sequence_length () == 0)
351 fprintf (stream
, "\n\tnop");
354 x
= mark_constant_pool_use (x
);
355 output_addr_const (stream
, x
);
358 fputs (reg_names
[REGNO (x
) + LSW
], (stream
));
361 fputs (reg_names
[REGNO (x
) + MSW
], (stream
));
364 /* Next word of a double. */
365 switch (GET_CODE (x
))
368 fputs (reg_names
[REGNO (x
) + 1], (stream
));
371 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
372 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
373 x
= adjust_address (x
, SImode
, 4);
374 print_operand_address (stream
, XEXP (x
, 0));
381 switch (GET_CODE (x
))
383 case PLUS
: fputs ("add", stream
); break;
384 case MINUS
: fputs ("sub", stream
); break;
385 case MULT
: fputs ("mul", stream
); break;
386 case DIV
: fputs ("div", stream
); break;
392 if (GET_CODE (x
) == MEM
393 && GET_CODE (XEXP (x
, 0)) == PLUS
394 && (GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
395 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == SUBREG
))
400 if (GET_CODE (x
) != MEM
)
403 switch (GET_CODE (x
))
407 print_operand (stream
, x
, 0);
408 fputs (", 0", stream
);
412 print_operand (stream
, XEXP (x
, 0), 0);
413 fputs (", ", stream
);
414 print_operand (stream
, XEXP (x
, 1), 0);
423 if (GET_CODE (x
) == CONST_INT
)
425 fprintf ((stream
), "%u", (unsigned) INTVAL (x
) & (0x10000 - 1));
431 switch (GET_CODE (x
))
433 /* FIXME: We need this on SHmedia32 because reload generates
434 some sign-extended HI or QI loads into DImode registers
435 but, because Pmode is SImode, the address ends up with a
436 subreg:SI of the DImode register. Maybe reload should be
437 fixed so as to apply alter_subreg to such loads? */
439 if (SUBREG_BYTE (x
) != 0
440 || GET_CODE (SUBREG_REG (x
)) != REG
)
447 if (FP_REGISTER_P (REGNO (x
))
448 && GET_MODE (x
) == V16SFmode
)
449 fprintf ((stream
), "mtrx%s", reg_names
[REGNO (x
)] + 2);
450 else if (FP_REGISTER_P (REGNO (x
))
451 && GET_MODE (x
) == V4SFmode
)
452 fprintf ((stream
), "fv%s", reg_names
[REGNO (x
)] + 2);
453 else if (GET_CODE (x
) == REG
454 && GET_MODE (x
) == V2SFmode
)
455 fprintf ((stream
), "fp%s", reg_names
[REGNO (x
)] + 2);
456 else if (FP_REGISTER_P (REGNO (x
))
457 && GET_MODE_SIZE (GET_MODE (x
)) > 4)
458 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)] + 1);
460 fputs (reg_names
[REGNO (x
)], (stream
));
464 output_address (XEXP (x
, 0));
469 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
470 && GET_MODE (XEXP (x
, 0)) == DImode
471 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == TRUNCATE
472 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
)
474 rtx val
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
477 if (GET_CODE (val
) == ASHIFTRT
)
480 if (GET_CODE (XEXP (val
, 0)) == CONST
)
482 output_addr_const (stream
, XEXP (val
, 0));
483 if (GET_CODE (XEXP (val
, 0)) == CONST
)
485 fputs (" >> ", stream
);
486 output_addr_const (stream
, XEXP (val
, 1));
491 if (GET_CODE (val
) == CONST
)
493 output_addr_const (stream
, val
);
494 if (GET_CODE (val
) == CONST
)
497 fputs (" & 65535)", stream
);
505 output_addr_const (stream
, x
);
512 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
514 force_into (value
, target
)
517 value
= force_operand (value
, target
);
518 if (! rtx_equal_p (value
, target
))
519 emit_insn (gen_move_insn (target
, value
));
522 /* Emit code to perform a block move. Choose the best method.
524 OPERANDS[0] is the destination.
525 OPERANDS[1] is the source.
526 OPERANDS[2] is the size.
527 OPERANDS[3] is the alignment safe to use. */
530 expand_block_move (operands
)
533 int align
= INTVAL (operands
[3]);
534 int constp
= (GET_CODE (operands
[2]) == CONST_INT
);
535 int bytes
= (constp
? INTVAL (operands
[2]) : 0);
537 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
538 alignment, or if it isn't a multiple of 4 bytes, then fail. */
539 if (! constp
|| align
< 4 || (bytes
% 4 != 0))
546 else if (bytes
== 12)
551 rtx r4
= gen_rtx (REG
, SImode
, 4);
552 rtx r5
= gen_rtx (REG
, SImode
, 5);
554 entry_name
= get_identifier ("__movstrSI12_i4");
556 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
557 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
558 force_into (XEXP (operands
[0], 0), r4
);
559 force_into (XEXP (operands
[1], 0), r5
);
560 emit_insn (gen_block_move_real_i4 (func_addr_rtx
));
563 else if (! TARGET_SMALLCODE
)
569 rtx r4
= gen_rtx (REG
, SImode
, 4);
570 rtx r5
= gen_rtx (REG
, SImode
, 5);
571 rtx r6
= gen_rtx (REG
, SImode
, 6);
573 entry_name
= get_identifier (bytes
& 4
575 : "__movstr_i4_even");
576 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
577 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
578 force_into (XEXP (operands
[0], 0), r4
);
579 force_into (XEXP (operands
[1], 0), r5
);
582 emit_insn (gen_move_insn (r6
, GEN_INT (dwords
- 1)));
583 emit_insn (gen_block_lump_real_i4 (func_addr_rtx
));
595 rtx r4
= gen_rtx_REG (SImode
, 4);
596 rtx r5
= gen_rtx_REG (SImode
, 5);
598 sprintf (entry
, "__movstrSI%d", bytes
);
599 entry_name
= get_identifier (entry
);
600 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
601 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
602 force_into (XEXP (operands
[0], 0), r4
);
603 force_into (XEXP (operands
[1], 0), r5
);
604 emit_insn (gen_block_move_real (func_addr_rtx
));
608 /* This is the same number of bytes as a memcpy call, but to a different
609 less common function name, so this will occasionally use more space. */
610 if (! TARGET_SMALLCODE
)
615 int final_switch
, while_loop
;
616 rtx r4
= gen_rtx_REG (SImode
, 4);
617 rtx r5
= gen_rtx_REG (SImode
, 5);
618 rtx r6
= gen_rtx_REG (SImode
, 6);
620 entry_name
= get_identifier ("__movstr");
621 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
622 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
623 force_into (XEXP (operands
[0], 0), r4
);
624 force_into (XEXP (operands
[1], 0), r5
);
626 /* r6 controls the size of the move. 16 is decremented from it
627 for each 64 bytes moved. Then the negative bit left over is used
628 as an index into a list of move instructions. e.g., a 72 byte move
629 would be set up with size(r6) = 14, for one iteration through the
630 big while loop, and a switch of -2 for the last part. */
632 final_switch
= 16 - ((bytes
/ 4) % 16);
633 while_loop
= ((bytes
/ 4) / 16 - 1) * 16;
634 emit_insn (gen_move_insn (r6
, GEN_INT (while_loop
+ final_switch
)));
635 emit_insn (gen_block_lump_real (func_addr_rtx
));
642 /* Prepare operands for a move define_expand; specifically, one of the
643 operands must be in a register. */
646 prepare_move_operands (operands
, mode
)
648 enum machine_mode mode
;
650 if ((mode
== SImode
|| mode
== DImode
) && flag_pic
)
653 if (SYMBOLIC_CONST_P (operands
[1]))
655 if (GET_CODE (operands
[0]) == MEM
)
656 operands
[1] = force_reg (Pmode
, operands
[1]);
657 else if (GET_CODE (operands
[1]) == LABEL_REF
658 && target_reg_operand (operands
[0], mode
))
662 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
663 operands
[1] = legitimize_pic_address (operands
[1], mode
, temp
);
666 else if (GET_CODE (operands
[1]) == CONST
667 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
668 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
670 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
671 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
673 operands
[1] = expand_binop (mode
, add_optab
, temp
,
674 XEXP (XEXP (operands
[1], 0), 1),
675 no_new_pseudos
? temp
676 : gen_reg_rtx (Pmode
),
681 if (! reload_in_progress
&& ! reload_completed
)
683 /* Copy the source to a register if both operands aren't registers. */
684 if (! register_operand (operands
[0], mode
)
685 && ! register_operand (operands
[1], mode
))
686 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
688 /* This case can happen while generating code to move the result
689 of a library call to the target. Reject `st r0,@(rX,rY)' because
690 reload will fail to find a spill register for rX, since r0 is already
691 being used for the source. */
692 else if (GET_CODE (operands
[1]) == REG
&& REGNO (operands
[1]) == 0
693 && GET_CODE (operands
[0]) == MEM
694 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
695 && GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == REG
)
696 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
702 /* Prepare the operands for an scc instruction; make sure that the
703 compare has been done. */
705 prepare_scc_operands (code
)
708 rtx t_reg
= gen_rtx_REG (SImode
, T_REG
);
709 enum rtx_code oldcode
= code
;
710 enum machine_mode mode
;
712 /* First need a compare insn. */
716 /* It isn't possible to handle this case. */
735 rtx tmp
= sh_compare_op0
;
736 sh_compare_op0
= sh_compare_op1
;
737 sh_compare_op1
= tmp
;
740 mode
= GET_MODE (sh_compare_op0
);
741 if (mode
== VOIDmode
)
742 mode
= GET_MODE (sh_compare_op1
);
744 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
745 if ((code
!= EQ
&& code
!= NE
746 && (sh_compare_op1
!= const0_rtx
747 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
748 || (mode
== DImode
&& sh_compare_op1
!= const0_rtx
)
749 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
750 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
752 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
753 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
)
754 (gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec (2,
755 gen_rtx (SET
, VOIDmode
, t_reg
,
756 gen_rtx (code
, SImode
,
757 sh_compare_op0
, sh_compare_op1
)),
758 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ()))));
760 emit_insn (gen_rtx (SET
, VOIDmode
, t_reg
,
761 gen_rtx (code
, SImode
, sh_compare_op0
,
767 /* Called from the md file, set up the operands of a compare instruction. */
770 from_compare (operands
, code
)
774 enum machine_mode mode
= GET_MODE (sh_compare_op0
);
776 if (mode
== VOIDmode
)
777 mode
= GET_MODE (sh_compare_op1
);
780 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
782 /* Force args into regs, since we can't use constants here. */
783 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
784 if (sh_compare_op1
!= const0_rtx
785 || code
== GTU
|| code
== GEU
786 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
787 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
789 if (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
&& code
== GE
)
791 from_compare (operands
, GT
);
792 insn
= gen_ieee_ccmpeqsf_t (sh_compare_op0
, sh_compare_op1
);
795 insn
= gen_rtx_SET (VOIDmode
,
796 gen_rtx_REG (SImode
, T_REG
),
797 gen_rtx (code
, SImode
, sh_compare_op0
,
799 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
801 insn
= gen_rtx (PARALLEL
, VOIDmode
,
803 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ())));
804 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
) (insn
);
810 /* Functions to output assembly code. */
812 /* Return a sequence of instructions to perform DI or DF move.
814 Since the SH cannot move a DI or DF in one instruction, we have
815 to take care when we see overlapping source and dest registers. */
818 output_movedouble (insn
, operands
, mode
)
819 rtx insn ATTRIBUTE_UNUSED
;
821 enum machine_mode mode
;
823 rtx dst
= operands
[0];
824 rtx src
= operands
[1];
826 if (GET_CODE (dst
) == MEM
827 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
828 return "mov.l %T1,%0\n\tmov.l %1,%0";
830 if (register_operand (dst
, mode
)
831 && register_operand (src
, mode
))
833 if (REGNO (src
) == MACH_REG
)
834 return "sts mach,%S0\n\tsts macl,%R0";
836 /* When mov.d r1,r2 do r2->r3 then r1->r2;
837 when mov.d r1,r0 do r1->r0 then r2->r1. */
839 if (REGNO (src
) + 1 == REGNO (dst
))
840 return "mov %T1,%T0\n\tmov %1,%0";
842 return "mov %1,%0\n\tmov %T1,%T0";
844 else if (GET_CODE (src
) == CONST_INT
)
846 if (INTVAL (src
) < 0)
847 output_asm_insn ("mov #-1,%S0", operands
);
849 output_asm_insn ("mov #0,%S0", operands
);
853 else if (GET_CODE (src
) == MEM
)
856 int dreg
= REGNO (dst
);
857 rtx inside
= XEXP (src
, 0);
859 if (GET_CODE (inside
) == REG
)
860 ptrreg
= REGNO (inside
);
861 else if (GET_CODE (inside
) == SUBREG
)
862 ptrreg
= subreg_regno (inside
);
863 else if (GET_CODE (inside
) == PLUS
)
865 ptrreg
= REGNO (XEXP (inside
, 0));
866 /* ??? A r0+REG address shouldn't be possible here, because it isn't
867 an offsettable address. Unfortunately, offsettable addresses use
868 QImode to check the offset, and a QImode offsettable address
869 requires r0 for the other operand, which is not currently
870 supported, so we can't use the 'o' constraint.
871 Thus we must check for and handle r0+REG addresses here.
872 We punt for now, since this is likely very rare. */
873 if (GET_CODE (XEXP (inside
, 1)) == REG
)
876 else if (GET_CODE (inside
) == LABEL_REF
)
877 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
878 else if (GET_CODE (inside
) == POST_INC
)
879 return "mov.l %1,%0\n\tmov.l %1,%T0";
883 /* Work out the safe way to copy. Copy into the second half first. */
885 return "mov.l %T1,%T0\n\tmov.l %1,%0";
888 return "mov.l %1,%0\n\tmov.l %T1,%T0";
891 /* Print an instruction which would have gone into a delay slot after
892 another instruction, but couldn't because the other instruction expanded
893 into a sequence where putting the slot insn at the end wouldn't work. */
899 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
, optimize
, 0, 1);
901 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
905 output_far_jump (insn
, op
)
909 struct { rtx lab
, reg
, op
; } this;
910 rtx braf_base_lab
= NULL_RTX
;
913 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
915 this.lab
= gen_label_rtx ();
919 && offset
- get_attr_length (insn
) <= 32766)
922 jump
= "mov.w %O0,%1; braf %1";
930 jump
= "mov.l %O0,%1; braf %1";
932 jump
= "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
935 jump
= "mov.l %O0,%1; jmp @%1";
937 /* If we have a scratch register available, use it. */
938 if (GET_CODE (PREV_INSN (insn
)) == INSN
939 && INSN_CODE (PREV_INSN (insn
)) == CODE_FOR_indirect_jump_scratch
)
941 this.reg
= SET_DEST (PATTERN (PREV_INSN (insn
)));
942 if (REGNO (this.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
943 jump
= "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
944 output_asm_insn (jump
, &this.lab
);
945 if (dbr_sequence_length ())
946 print_slot (final_sequence
);
948 output_asm_insn ("nop", 0);
952 /* Output the delay slot insn first if any. */
953 if (dbr_sequence_length ())
954 print_slot (final_sequence
);
956 this.reg
= gen_rtx_REG (SImode
, 13);
957 /* We must keep the stack aligned to 8-byte boundaries on SH5.
958 Fortunately, MACL is fixed and call-clobbered, and we never
959 need its value across jumps, so save r13 in it instead of in
962 output_asm_insn ("lds r13, macl", 0);
964 output_asm_insn ("mov.l r13,@-r15", 0);
965 output_asm_insn (jump
, &this.lab
);
967 output_asm_insn ("sts macl, r13", 0);
969 output_asm_insn ("mov.l @r15+,r13", 0);
971 if (far
&& flag_pic
&& TARGET_SH2
)
973 braf_base_lab
= gen_label_rtx ();
974 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
975 CODE_LABEL_NUMBER (braf_base_lab
));
978 output_asm_insn (".align 2", 0);
979 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (this.lab
));
984 this.lab
= braf_base_lab
;
985 output_asm_insn (".long %O2-%O0", &this.lab
);
988 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this.lab
);
992 /* Local label counter, used for constants in the pool and inside
997 /* Output code for ordinary branches. */
1000 output_branch (logic
, insn
, operands
)
1005 switch (get_attr_length (insn
))
1008 /* This can happen if filling the delay slot has caused a forward
1009 branch to exceed its range (we could reverse it, but only
1010 when we know we won't overextend other branches; this should
1011 best be handled by relaxation).
1012 It can also happen when other condbranches hoist delay slot insn
1013 from their destination, thus leading to code size increase.
1014 But the branch will still be in the range -4092..+4098 bytes. */
1019 /* The call to print_slot will clobber the operands. */
1020 rtx op0
= operands
[0];
1022 /* If the instruction in the delay slot is annulled (true), then
1023 there is no delay slot where we can put it now. The only safe
1024 place for it is after the label. final will do that by default. */
1027 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
1029 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
1030 ASSEMBLER_DIALECT
? "/" : ".", label
);
1031 print_slot (final_sequence
);
1034 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
1036 output_asm_insn ("bra\t%l0", &op0
);
1037 fprintf (asm_out_file
, "\tnop\n");
1038 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file
, "LF", label
);
1042 /* When relaxing, handle this like a short branch. The linker
1043 will fix it up if it still doesn't fit after relaxation. */
1045 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
1047 /* There should be no longer branches now - that would
1048 indicate that something has destroyed the branches set
1049 up in machine_dependent_reorg. */
1055 output_branchy_insn (code
, template, insn
, operands
)
1057 const char *template;
1061 rtx next_insn
= NEXT_INSN (insn
);
1063 if (next_insn
&& GET_CODE (next_insn
) == JUMP_INSN
&& condjump_p (next_insn
))
1065 rtx src
= SET_SRC (PATTERN (next_insn
));
1066 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
1068 /* Following branch not taken */
1069 operands
[9] = gen_label_rtx ();
1070 emit_label_after (operands
[9], next_insn
);
1071 INSN_ADDRESSES_NEW (operands
[9],
1072 INSN_ADDRESSES (INSN_UID (next_insn
))
1073 + get_attr_length (next_insn
));
1078 int offset
= (branch_dest (next_insn
)
1079 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
1080 if (offset
>= -252 && offset
<= 258)
1082 if (GET_CODE (src
) == IF_THEN_ELSE
)
1084 src
= XEXP (src
, 1);
1090 operands
[9] = gen_label_rtx ();
1091 emit_label_after (operands
[9], insn
);
1092 INSN_ADDRESSES_NEW (operands
[9],
1093 INSN_ADDRESSES (INSN_UID (insn
))
1094 + get_attr_length (insn
));
1099 output_ieee_ccmpeq (insn
, operands
)
1100 rtx insn
, *operands
;
1102 return output_branchy_insn (NE
, "bt\t%l9\\;fcmp/eq\t%1,%0", insn
, operands
);
1105 /* Output to FILE the start of the assembler file. */
1108 output_file_start (file
)
1111 output_file_directive (file
, main_input_filename
);
1113 /* Switch to the data section so that the coffsem symbol
1114 isn't in the text section. */
1117 if (TARGET_LITTLE_ENDIAN
)
1118 fprintf (file
, "\t.little\n");
1120 if (TARGET_SHCOMPACT
)
1121 fprintf (file
, "\t.mode\tSHcompact\n");
1122 else if (TARGET_SHMEDIA
)
1123 fprintf (file
, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1124 TARGET_SHMEDIA64
? 64 : 32);
1127 /* Actual number of instructions used to make a shift by N. */
1128 static const char ashiftrt_insns
[] =
1129 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1131 /* Left shift and logical right shift are the same. */
1132 static const char shift_insns
[] =
1133 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1135 /* Individual shift amounts needed to get the above length sequences.
1136 One bit right shifts clobber the T bit, so when possible, put one bit
1137 shifts in the middle of the sequence, so the ends are eligible for
1138 branch delay slots. */
1139 static const short shift_amounts
[32][5] = {
1140 {0}, {1}, {2}, {2, 1},
1141 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1142 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1143 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1144 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1145 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1146 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1147 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1149 /* Likewise, but for shift amounts < 16, up to three highmost bits
1150 might be clobbered. This is typically used when combined with some
1151 kind of sign or zero extension. */
1153 static const char ext_shift_insns
[] =
1154 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1156 static const short ext_shift_amounts
[32][4] = {
1157 {0}, {1}, {2}, {2, 1},
1158 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1159 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1160 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1161 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1162 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1163 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1164 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1166 /* Assuming we have a value that has been sign-extended by at least one bit,
1167 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1168 to shift it by N without data loss, and quicker than by other means? */
1169 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1171 /* This is used in length attributes in sh.md to help compute the length
1172 of arbitrary constant shift instructions. */
1175 shift_insns_rtx (insn
)
1178 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1179 int shift_count
= INTVAL (XEXP (set_src
, 1));
1180 enum rtx_code shift_code
= GET_CODE (set_src
);
1185 return ashiftrt_insns
[shift_count
];
1188 return shift_insns
[shift_count
];
1194 /* Return the cost of a shift. */
1205 if (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
1207 if (GET_MODE (x
) == DImode
1208 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1209 && INTVAL (XEXP (x
, 1)) == 1)
1212 /* Everything else is invalid, because there is no pattern for it. */
1215 /* If shift by a non constant, then this will be expensive. */
1216 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1217 return SH_DYNAMIC_SHIFT_COST
;
1219 value
= INTVAL (XEXP (x
, 1));
1221 /* Otherwise, return the true cost in instructions. */
1222 if (GET_CODE (x
) == ASHIFTRT
)
1224 int cost
= ashiftrt_insns
[value
];
1225 /* If SH3, then we put the constant in a reg and use shad. */
1226 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
1227 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
1231 return shift_insns
[value
];
1234 /* Return the cost of an AND operation. */
1242 /* Anding with a register is a single cycle and instruction. */
1243 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1246 i
= INTVAL (XEXP (x
, 1));
1250 if ((GET_CODE (XEXP (x
, 1)) == CONST_INT
1251 && CONST_OK_FOR_J (INTVAL (XEXP (x
, 1))))
1252 || EXTRA_CONSTRAINT_S (XEXP (x
, 1)))
1258 /* These constants are single cycle extu.[bw] instructions. */
1259 if (i
== 0xff || i
== 0xffff)
1261 /* Constants that can be used in an and immediate instruction is a single
1262 cycle, but this requires r0, so make it a little more expensive. */
1263 if (CONST_OK_FOR_L (i
))
1265 /* Constants that can be loaded with a mov immediate and an and.
1266 This case is probably unnecessary. */
1267 if (CONST_OK_FOR_I (i
))
1269 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1270 This case is probably unnecessary. */
1274 /* Return the cost of an addition or a subtraction. */
1280 /* Adding a register is a single cycle insn. */
1281 if (GET_CODE (XEXP (x
, 1)) == REG
1282 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1285 /* Likewise for small constants. */
1286 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1287 && CONST_OK_FOR_ADD (INTVAL (XEXP (x
, 1))))
1291 switch (GET_CODE (XEXP (x
, 1)))
1296 return TARGET_SHMEDIA64
? 5 : 3;
1299 if (CONST_OK_FOR_J (INTVAL (XEXP (x
, 1))))
1301 else if (CONST_OK_FOR_J (INTVAL (XEXP (x
, 1)) >> 16))
1303 else if (CONST_OK_FOR_J ((INTVAL (XEXP (x
, 1)) >> 16) >> 16))
1311 /* Any other constant requires a 2 cycle pc-relative load plus an
1316 /* Return the cost of a multiply. */
1319 rtx x ATTRIBUTE_UNUSED
;
1326 /* We have a mul insn, so we can never take more than the mul and the
1327 read of the mac reg, but count more because of the latency and extra
1329 if (TARGET_SMALLCODE
)
1334 /* If we're aiming at small code, then just count the number of
1335 insns in a multiply call sequence. */
1336 if (TARGET_SMALLCODE
)
1339 /* Otherwise count all the insns in the routine we'd be calling too. */
1343 /* Code to expand a shift. */
1346 gen_ashift (type
, n
, reg
)
1351 /* Negative values here come from the shift_amounts array. */
1364 emit_insn (gen_ashrsi3_k (reg
, reg
, GEN_INT (n
)));
1368 emit_insn (gen_lshrsi3_m (reg
, reg
, GEN_INT (n
)));
1370 emit_insn (gen_lshrsi3_k (reg
, reg
, GEN_INT (n
)));
1373 emit_insn (gen_ashlsi3_std (reg
, reg
, GEN_INT (n
)));
1378 /* Same for HImode */
1381 gen_ashift_hi (type
, n
, reg
)
1386 /* Negative values here come from the shift_amounts array. */
1400 /* We don't have HImode right shift operations because using the
1401 ordinary 32 bit shift instructions for that doesn't generate proper
1402 zero/sign extension.
1403 gen_ashift_hi is only called in contexts where we know that the
1404 sign extension works out correctly. */
1407 if (GET_CODE (reg
) == SUBREG
)
1409 offset
= SUBREG_BYTE (reg
);
1410 reg
= SUBREG_REG (reg
);
1412 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
1416 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
1421 /* Output RTL to split a constant shift into its component SH constant
1422 shift instructions. */
1425 gen_shifty_op (code
, operands
)
1429 int value
= INTVAL (operands
[2]);
1432 /* Truncate the shift count in case it is out of bounds. */
1433 value
= value
& 0x1f;
1437 if (code
== LSHIFTRT
)
1439 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
1440 emit_insn (gen_movt (operands
[0]));
1443 else if (code
== ASHIFT
)
1445 /* There is a two instruction sequence for 31 bit left shifts,
1446 but it requires r0. */
1447 if (GET_CODE (operands
[0]) == REG
&& REGNO (operands
[0]) == 0)
1449 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
1450 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
1455 else if (value
== 0)
1457 /* This can happen when not optimizing. We must output something here
1458 to prevent the compiler from aborting in final.c after the try_split
1460 emit_insn (gen_nop ());
1464 max
= shift_insns
[value
];
1465 for (i
= 0; i
< max
; i
++)
1466 gen_ashift (code
, shift_amounts
[value
][i
], operands
[0]);
1469 /* Same as above, but optimized for values where the topmost bits don't
1473 gen_shifty_hi_op (code
, operands
)
1477 int value
= INTVAL (operands
[2]);
1479 void (*gen_fun
) PARAMS ((int, int, rtx
));
1481 /* This operation is used by and_shl for SImode values with a few
1482 high bits known to be cleared. */
1486 emit_insn (gen_nop ());
1490 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
1493 max
= ext_shift_insns
[value
];
1494 for (i
= 0; i
< max
; i
++)
1495 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1498 /* When shifting right, emit the shifts in reverse order, so that
1499 solitary negative values come first. */
1500 for (i
= ext_shift_insns
[value
] - 1; i
>= 0; i
--)
1501 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1504 /* Output RTL for an arithmetic right shift. */
1506 /* ??? Rewrite to use super-optimizer sequences. */
1509 expand_ashiftrt (operands
)
1520 if (GET_CODE (operands
[2]) != CONST_INT
)
1522 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
1523 emit_insn (gen_negsi2 (count
, count
));
1524 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1527 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
1528 > 1 + SH_DYNAMIC_SHIFT_COST
)
1531 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
1532 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1536 if (GET_CODE (operands
[2]) != CONST_INT
)
1539 value
= INTVAL (operands
[2]) & 31;
1543 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
1546 else if (value
>= 16 && value
<= 19)
1548 wrk
= gen_reg_rtx (SImode
);
1549 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
1552 gen_ashift (ASHIFTRT
, 1, wrk
);
1553 emit_move_insn (operands
[0], wrk
);
1556 /* Expand a short sequence inline, longer call a magic routine. */
1557 else if (value
<= 5)
1559 wrk
= gen_reg_rtx (SImode
);
1560 emit_move_insn (wrk
, operands
[1]);
1562 gen_ashift (ASHIFTRT
, 1, wrk
);
1563 emit_move_insn (operands
[0], wrk
);
1567 wrk
= gen_reg_rtx (Pmode
);
1569 /* Load the value into an arg reg and call a helper. */
1570 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
1571 sprintf (func
, "__ashiftrt_r4_%d", value
);
1572 func_name
= get_identifier (func
);
1573 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (func_name
));
1574 emit_move_insn (wrk
, sym
);
1575 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
1576 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
1581 sh_dynamicalize_shift_p (count
)
1584 return shift_insns
[INTVAL (count
)] > 1 + SH_DYNAMIC_SHIFT_COST
;
1587 /* Try to find a good way to implement the combiner pattern
1588 [(set (match_operand:SI 0 "register_operand" "r")
1589 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1590 (match_operand:SI 2 "const_int_operand" "n"))
1591 (match_operand:SI 3 "const_int_operand" "n"))) .
1592 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1593 return 0 for simple right / left or left/right shift combination.
1594 return 1 for a combination of shifts with zero_extend.
1595 return 2 for a combination of shifts with an AND that needs r0.
1596 return 3 for a combination of shifts with an AND that needs an extra
1597 scratch register, when the three highmost bits of the AND mask are clear.
1598 return 4 for a combination of shifts with an AND that needs an extra
1599 scratch register, when any of the three highmost bits of the AND mask
1601 If ATTRP is set, store an initial right shift width in ATTRP[0],
1602 and the instruction length in ATTRP[1] . These values are not valid
1604 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1605 shift_amounts for the last shift value that is to be used before the
1608 shl_and_kind (left_rtx
, mask_rtx
, attrp
)
1609 rtx left_rtx
, mask_rtx
;
1612 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
1613 int left
= INTVAL (left_rtx
), right
;
1615 int cost
, best_cost
= 10000;
1616 int best_right
= 0, best_len
= 0;
1620 if (left
< 0 || left
> 31)
1622 if (GET_CODE (mask_rtx
) == CONST_INT
)
1623 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
1625 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
1626 /* Can this be expressed as a right shift / left shift pair ? */
1627 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
1628 right
= exact_log2 (lsb
);
1629 mask2
= ~(mask
+ lsb
- 1);
1630 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
1631 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1633 best_cost
= shift_insns
[right
] + shift_insns
[right
+ left
];
1634 /* mask has no trailing zeroes <==> ! right */
1635 else if (! right
&& mask2
== ~(lsb2
- 1))
1637 int late_right
= exact_log2 (lsb2
);
1638 best_cost
= shift_insns
[left
+ late_right
] + shift_insns
[late_right
];
1640 /* Try to use zero extend */
1641 if (mask2
== ~(lsb2
- 1))
1645 for (width
= 8; width
<= 16; width
+= 8)
1647 /* Can we zero-extend right away? */
1648 if (lsb2
== (unsigned HOST_WIDE_INT
)1 << width
)
1651 = 1 + ext_shift_insns
[right
] + ext_shift_insns
[left
+ right
];
1652 if (cost
< best_cost
)
1663 /* ??? Could try to put zero extend into initial right shift,
1664 or even shift a bit left before the right shift. */
1665 /* Determine value of first part of left shift, to get to the
1666 zero extend cut-off point. */
1667 first
= width
- exact_log2 (lsb2
) + right
;
1668 if (first
>= 0 && right
+ left
- first
>= 0)
1670 cost
= ext_shift_insns
[right
] + ext_shift_insns
[first
] + 1
1671 + ext_shift_insns
[right
+ left
- first
];
1672 if (cost
< best_cost
)
1684 /* Try to use r0 AND pattern */
1685 for (i
= 0; i
<= 2; i
++)
1689 if (! CONST_OK_FOR_L (mask
>> i
))
1691 cost
= (i
!= 0) + 2 + ext_shift_insns
[left
+ i
];
1692 if (cost
< best_cost
)
1697 best_len
= cost
- 1;
1700 /* Try to use a scratch register to hold the AND operand. */
1701 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
)3 << 30)) == 0;
1702 for (i
= 0; i
<= 2; i
++)
1706 cost
= (i
!= 0) + (CONST_OK_FOR_I (mask
>> i
) ? 2 : 3)
1707 + (can_ext
? ext_shift_insns
: shift_insns
)[left
+ i
];
1708 if (cost
< best_cost
)
1713 best_len
= cost
- 1 - ! CONST_OK_FOR_I (mask
>> i
);
1719 attrp
[0] = best_right
;
1720 attrp
[1] = best_len
;
1725 /* This is used in length attributes of the unnamed instructions
1726 corresponding to shl_and_kind return values of 1 and 2. */
1728 shl_and_length (insn
)
1731 rtx set_src
, left_rtx
, mask_rtx
;
1734 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1735 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
1736 mask_rtx
= XEXP (set_src
, 1);
1737 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1738 return attributes
[1];
1741 /* This is used in length attribute of the and_shl_scratch instruction. */
1744 shl_and_scr_length (insn
)
1747 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1748 int len
= shift_insns
[INTVAL (XEXP (set_src
, 1))];
1749 rtx op
= XEXP (set_src
, 0);
1750 len
+= shift_insns
[INTVAL (XEXP (op
, 1))] + 1;
1751 op
= XEXP (XEXP (op
, 0), 0);
1752 return len
+ shift_insns
[INTVAL (XEXP (op
, 1))];
1755 /* Generating rtl? */
1756 extern int rtx_equal_function_value_matters
;
1758 /* Generate rtl for instructions for which shl_and_kind advised a particular
1759 method of generating them, i.e. returned zero. */
1762 gen_shl_and (dest
, left_rtx
, mask_rtx
, source
)
1763 rtx dest
, left_rtx
, mask_rtx
, source
;
1766 unsigned HOST_WIDE_INT mask
;
1767 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1768 int right
, total_shift
;
1769 void (*shift_gen_fun
) PARAMS ((int, rtx
*)) = gen_shifty_hi_op
;
1771 right
= attributes
[0];
1772 total_shift
= INTVAL (left_rtx
) + right
;
1773 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
1780 int first
= attributes
[2];
1785 emit_insn ((mask
<< right
) <= 0xff
1786 ? gen_zero_extendqisi2(dest
,
1787 gen_lowpart (QImode
, source
))
1788 : gen_zero_extendhisi2(dest
,
1789 gen_lowpart (HImode
, source
)));
1793 emit_insn (gen_movsi (dest
, source
));
1797 operands
[2] = GEN_INT (right
);
1798 gen_shifty_hi_op (LSHIFTRT
, operands
);
1802 operands
[2] = GEN_INT (first
);
1803 gen_shifty_hi_op (ASHIFT
, operands
);
1804 total_shift
-= first
;
1808 emit_insn (mask
<= 0xff
1809 ? gen_zero_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
1810 : gen_zero_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
1811 if (total_shift
> 0)
1813 operands
[2] = GEN_INT (total_shift
);
1814 gen_shifty_hi_op (ASHIFT
, operands
);
1819 shift_gen_fun
= gen_shifty_op
;
1821 /* If the topmost bit that matters is set, set the topmost bits
1822 that don't matter. This way, we might be able to get a shorter
1824 if (mask
& ((HOST_WIDE_INT
)1 << (31 - total_shift
)))
1825 mask
|= (HOST_WIDE_INT
)~0 << (31 - total_shift
);
1827 /* Don't expand fine-grained when combining, because that will
1828 make the pattern fail. */
1829 if (rtx_equal_function_value_matters
1830 || reload_in_progress
|| reload_completed
)
1834 /* Cases 3 and 4 should be handled by this split
1835 only while combining */
1840 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
1843 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
1848 operands
[2] = GEN_INT (total_shift
);
1849 shift_gen_fun (ASHIFT
, operands
);
1856 if (kind
!= 4 && total_shift
< 16)
1858 neg
= -ext_shift_amounts
[total_shift
][1];
1860 neg
-= ext_shift_amounts
[total_shift
][2];
1864 emit_insn (gen_and_shl_scratch (dest
, source
,
1867 GEN_INT (total_shift
+ neg
),
1869 emit_insn (gen_movsi (dest
, dest
));
1876 /* Try to find a good way to implement the combiner pattern
1877 [(set (match_operand:SI 0 "register_operand" "=r")
1878 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1879 (match_operand:SI 2 "const_int_operand" "n")
1880 (match_operand:SI 3 "const_int_operand" "n")
1882 (clobber (reg:SI T_REG))]
1883 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1884 return 0 for simple left / right shift combination.
1885 return 1 for left shift / 8 bit sign extend / left shift.
1886 return 2 for left shift / 16 bit sign extend / left shift.
1887 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1888 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1889 return 5 for left shift / 16 bit sign extend / right shift
1890 return 6 for < 8 bit sign extend / left shift.
1891 return 7 for < 8 bit sign extend / left shift / single right shift.
1892 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1895 shl_sext_kind (left_rtx
, size_rtx
, costp
)
1896 rtx left_rtx
, size_rtx
;
1899 int left
, size
, insize
, ext
;
1900 int cost
, best_cost
;
1903 left
= INTVAL (left_rtx
);
1904 size
= INTVAL (size_rtx
);
1905 insize
= size
- left
;
1908 /* Default to left / right shift. */
1910 best_cost
= shift_insns
[32 - insize
] + ashiftrt_insns
[32 - size
];
1913 /* 16 bit shift / sign extend / 16 bit shift */
1914 cost
= shift_insns
[16 - insize
] + 1 + ashiftrt_insns
[16 - size
];
1915 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1916 below, by alternative 3 or something even better. */
1917 if (cost
< best_cost
)
1923 /* Try a plain sign extend between two shifts. */
1924 for (ext
= 16; ext
>= insize
; ext
-= 8)
1928 cost
= ext_shift_insns
[ext
- insize
] + 1 + shift_insns
[size
- ext
];
1929 if (cost
< best_cost
)
1931 kind
= ext
/ (unsigned) 8;
1935 /* Check if we can do a sloppy shift with a final signed shift
1936 restoring the sign. */
1937 if (EXT_SHIFT_SIGNED (size
- ext
))
1938 cost
= ext_shift_insns
[ext
- insize
] + ext_shift_insns
[size
- ext
] + 1;
1939 /* If not, maybe it's still cheaper to do the second shift sloppy,
1940 and do a final sign extend? */
1941 else if (size
<= 16)
1942 cost
= ext_shift_insns
[ext
- insize
] + 1
1943 + ext_shift_insns
[size
> ext
? size
- ext
: ext
- size
] + 1;
1946 if (cost
< best_cost
)
1948 kind
= ext
/ (unsigned) 8 + 2;
1952 /* Check if we can sign extend in r0 */
1955 cost
= 3 + shift_insns
[left
];
1956 if (cost
< best_cost
)
1961 /* Try the same with a final signed shift. */
1964 cost
= 3 + ext_shift_insns
[left
+ 1] + 1;
1965 if (cost
< best_cost
)
1974 /* Try to use a dynamic shift. */
1975 cost
= shift_insns
[32 - insize
] + 1 + SH_DYNAMIC_SHIFT_COST
;
1976 if (cost
< best_cost
)
1987 /* Function to be used in the length attribute of the instructions
1988 implementing this pattern. */
1991 shl_sext_length (insn
)
1994 rtx set_src
, left_rtx
, size_rtx
;
1997 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1998 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
1999 size_rtx
= XEXP (set_src
, 1);
2000 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2004 /* Generate rtl for this pattern */
2007 gen_shl_sext (dest
, left_rtx
, size_rtx
, source
)
2008 rtx dest
, left_rtx
, size_rtx
, source
;
2011 int left
, size
, insize
, cost
;
2014 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2015 left
= INTVAL (left_rtx
);
2016 size
= INTVAL (size_rtx
);
2017 insize
= size
- left
;
2025 int ext
= kind
& 1 ? 8 : 16;
2026 int shift2
= size
- ext
;
2028 /* Don't expand fine-grained when combining, because that will
2029 make the pattern fail. */
2030 if (! rtx_equal_function_value_matters
2031 && ! reload_in_progress
&& ! reload_completed
)
2033 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2034 emit_insn (gen_movsi (dest
, source
));
2038 emit_insn (gen_movsi (dest
, source
));
2042 operands
[2] = GEN_INT (ext
- insize
);
2043 gen_shifty_hi_op (ASHIFT
, operands
);
2046 ? gen_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
2047 : gen_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
2052 operands
[2] = GEN_INT (shift2
);
2053 gen_shifty_op (ASHIFT
, operands
);
2060 if (EXT_SHIFT_SIGNED (shift2
))
2062 operands
[2] = GEN_INT (shift2
+ 1);
2063 gen_shifty_op (ASHIFT
, operands
);
2064 operands
[2] = GEN_INT (1);
2065 gen_shifty_op (ASHIFTRT
, operands
);
2068 operands
[2] = GEN_INT (shift2
);
2069 gen_shifty_hi_op (ASHIFT
, operands
);
2073 operands
[2] = GEN_INT (-shift2
);
2074 gen_shifty_hi_op (LSHIFTRT
, operands
);
2076 emit_insn (size
<= 8
2077 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
2078 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2085 if (! rtx_equal_function_value_matters
2086 && ! reload_in_progress
&& ! reload_completed
)
2087 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2091 operands
[2] = GEN_INT (16 - insize
);
2092 gen_shifty_hi_op (ASHIFT
, operands
);
2093 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2095 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2097 gen_ashift (ASHIFTRT
, 1, dest
);
2102 /* Don't expand fine-grained when combining, because that will
2103 make the pattern fail. */
2104 if (! rtx_equal_function_value_matters
2105 && ! reload_in_progress
&& ! reload_completed
)
2107 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2108 emit_insn (gen_movsi (dest
, source
));
2111 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
2112 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
2113 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
2115 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
2116 gen_shifty_op (ASHIFT
, operands
);
2118 emit_insn (gen_ashrsi3_k (dest
, dest
, GEN_INT (1)));
2126 /* Prefix a symbol_ref name with "datalabel". */
2129 gen_datalabel_ref (sym
)
2132 if (GET_CODE (sym
) == LABEL_REF
)
2133 return gen_rtx_CONST (GET_MODE (sym
),
2134 gen_rtx_UNSPEC (GET_MODE (sym
),
2138 if (GET_CODE (sym
) != SYMBOL_REF
)
2141 XSTR (sym
, 0) = concat (SH_DATALABEL_ENCODING
, XSTR (sym
, 0), NULL
);
2147 /* The SH cannot load a large constant into a register, constants have to
2148 come from a pc relative load. The reference of a pc relative load
2149 instruction must be less than 1k infront of the instruction. This
2150 means that we often have to dump a constant inside a function, and
2151 generate code to branch around it.
2153 It is important to minimize this, since the branches will slow things
2154 down and make things bigger.
2156 Worst case code looks like:
2174 We fix this by performing a scan before scheduling, which notices which
2175 instructions need to have their operands fetched from the constant table
2176 and builds the table.
2180 scan, find an instruction which needs a pcrel move. Look forward, find the
2181 last barrier which is within MAX_COUNT bytes of the requirement.
2182 If there isn't one, make one. Process all the instructions between
2183 the find and the barrier.
2185 In the above example, we can tell that L3 is within 1k of L1, so
2186 the first move can be shrunk from the 3 insn+constant sequence into
2187 just 1 insn, and the constant moved to L3 to make:
2198 Then the second move becomes the target for the shortening process. */
2202 rtx value
; /* Value in table. */
2203 rtx label
; /* Label of value. */
2204 rtx wend
; /* End of window. */
2205 enum machine_mode mode
; /* Mode of value. */
2208 /* The maximum number of constants that can fit into one pool, since
2209 the pc relative range is 0...1020 bytes and constants are at least 4
2212 #define MAX_POOL_SIZE (1020/4)
2213 static pool_node pool_vector
[MAX_POOL_SIZE
];
2214 static int pool_size
;
2215 static rtx pool_window_label
;
2216 static int pool_window_last
;
2218 /* ??? If we need a constant in HImode which is the truncated value of a
2219 constant we need in SImode, we could combine the two entries thus saving
2220 two bytes. Is this common enough to be worth the effort of implementing
2223 /* ??? This stuff should be done at the same time that we shorten branches.
2224 As it is now, we must assume that all branches are the maximum size, and
2225 this causes us to almost always output constant pools sooner than
2228 /* Add a constant to the pool and return its label. */
2231 add_constant (x
, mode
, last_value
)
2233 enum machine_mode mode
;
2237 rtx lab
, new, ref
, newref
;
2239 /* First see if we've already got it. */
2240 for (i
= 0; i
< pool_size
; i
++)
2242 if (x
->code
== pool_vector
[i
].value
->code
2243 && mode
== pool_vector
[i
].mode
)
2245 if (x
->code
== CODE_LABEL
)
2247 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
2250 if (rtx_equal_p (x
, pool_vector
[i
].value
))
2255 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
2257 new = gen_label_rtx ();
2258 LABEL_REFS (new) = pool_vector
[i
].label
;
2259 pool_vector
[i
].label
= lab
= new;
2261 if (lab
&& pool_window_label
)
2263 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2264 ref
= pool_vector
[pool_window_last
].wend
;
2265 LABEL_NEXTREF (newref
) = ref
;
2266 pool_vector
[pool_window_last
].wend
= newref
;
2269 pool_window_label
= new;
2270 pool_window_last
= i
;
2276 /* Need a new one. */
2277 pool_vector
[pool_size
].value
= x
;
2278 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
2281 lab
= gen_label_rtx ();
2282 pool_vector
[pool_size
].mode
= mode
;
2283 pool_vector
[pool_size
].label
= lab
;
2284 pool_vector
[pool_size
].wend
= NULL_RTX
;
2285 if (lab
&& pool_window_label
)
2287 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2288 ref
= pool_vector
[pool_window_last
].wend
;
2289 LABEL_NEXTREF (newref
) = ref
;
2290 pool_vector
[pool_window_last
].wend
= newref
;
2293 pool_window_label
= lab
;
2294 pool_window_last
= pool_size
;
2299 /* Output the literal table. */
2310 /* Do two passes, first time dump out the HI sized constants. */
2312 for (i
= 0; i
< pool_size
; i
++)
2314 pool_node
*p
= &pool_vector
[i
];
2316 if (p
->mode
== HImode
)
2320 scan
= emit_insn_after (gen_align_2 (), scan
);
2323 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2324 scan
= emit_label_after (lab
, scan
);
2325 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
2327 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2329 lab
= XEXP (ref
, 0);
2330 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2333 else if (p
->mode
== DImode
|| p
->mode
== DFmode
)
2339 if (TARGET_SHCOMPACT
&& have_di
)
2341 rtx align_insn
= NULL_RTX
;
2343 scan
= emit_label_after (gen_label_rtx (), scan
);
2344 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2347 for (i
= 0; i
< pool_size
; i
++)
2349 pool_node
*p
= &pool_vector
[i
];
2359 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2360 emit_label_before (lab
, align_insn
);
2361 emit_insn_before (gen_consttable_4 (p
->value
, const0_rtx
),
2363 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2365 lab
= XEXP (ref
, 0);
2366 emit_insn_before (gen_consttable_window_end (lab
),
2369 delete_insn (align_insn
);
2370 align_insn
= NULL_RTX
;
2375 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2376 scan
= emit_label_after (lab
, scan
);
2377 scan
= emit_insn_after (gen_consttable_4 (p
->value
,
2379 need_align
= ! need_align
;
2386 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2390 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2391 scan
= emit_label_after (lab
, scan
);
2392 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2400 if (p
->mode
!= HImode
)
2402 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2404 lab
= XEXP (ref
, 0);
2405 scan
= emit_insn_after (gen_consttable_window_end (lab
),
2414 for (i
= 0; i
< pool_size
; i
++)
2416 pool_node
*p
= &pool_vector
[i
];
2427 scan
= emit_label_after (gen_label_rtx (), scan
);
2428 scan
= emit_insn_after (gen_align_4 (), scan
);
2430 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2431 scan
= emit_label_after (lab
, scan
);
2432 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
2440 scan
= emit_label_after (gen_label_rtx (), scan
);
2441 scan
= emit_insn_after (gen_align_4 (), scan
);
2443 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2444 scan
= emit_label_after (lab
, scan
);
2445 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2453 if (p
->mode
!= HImode
)
2455 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2457 lab
= XEXP (ref
, 0);
2458 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2463 scan
= emit_insn_after (gen_consttable_end (), scan
);
2464 scan
= emit_barrier_after (scan
);
2466 pool_window_label
= NULL_RTX
;
2467 pool_window_last
= 0;
2470 /* Return non-zero if constant would be an ok source for a
2471 mov.w instead of a mov.l. */
2477 return (GET_CODE (src
) == CONST_INT
2478 && INTVAL (src
) >= -32768
2479 && INTVAL (src
) <= 32767);
2482 /* Non-zero if the insn is a move instruction which needs to be fixed. */
2484 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2485 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2486 need to fix it if the input value is CONST_OK_FOR_I. */
2492 if (GET_CODE (insn
) == INSN
)
2494 rtx pat
= PATTERN (insn
);
2495 if (GET_CODE (pat
) == PARALLEL
)
2496 pat
= XVECEXP (pat
, 0, 0);
2497 if (GET_CODE (pat
) == SET
2498 /* We can load any 8 bit value if we don't care what the high
2499 order bits end up as. */
2500 && GET_MODE (SET_DEST (pat
)) != QImode
2501 && (CONSTANT_P (SET_SRC (pat
))
2502 /* Match mova_const. */
2503 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
2504 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
2505 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
2507 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
2508 && (fp_zero_operand (SET_SRC (pat
))
2509 || fp_one_operand (SET_SRC (pat
)))
2510 /* ??? If this is a -m4 or -m4-single compilation, in general
2511 we don't know the current setting of fpscr, so disable fldi.
2512 There is an exception if this was a register-register move
2513 before reload - and hence it was ascertained that we have
2514 single precision setting - and in a post-reload optimization
2515 we changed this to do a constant load. In that case
2516 we don't have an r0 clobber, hence we must use fldi. */
2517 && (! TARGET_SH4
|| TARGET_FMOVD
2518 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn
), 0, 2), 0))
2520 && GET_CODE (SET_DEST (pat
)) == REG
2521 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
2522 && (GET_CODE (SET_SRC (pat
)) != CONST_INT
2523 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat
)))))
2534 return (GET_CODE (insn
) == INSN
2535 && GET_CODE (PATTERN (insn
)) == SET
2536 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
2537 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
2538 /* Don't match mova_const. */
2539 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn
)), 0, 0)) == LABEL_REF
);
2542 /* Find the last barrier from insn FROM which is close enough to hold the
2543 constant pool. If we can't find one, then create one near the end of
2547 find_barrier (num_mova
, mova
, from
)
2558 int leading_mova
= num_mova
;
2559 rtx barrier_before_mova
, found_barrier
= 0, good_barrier
= 0;
2563 /* For HImode: range is 510, add 4 because pc counts from address of
2564 second instruction after this one, subtract 2 for the jump instruction
2565 that we may need to emit before the table, subtract 2 for the instruction
2566 that fills the jump delay slot (in very rare cases, reorg will take an
2567 instruction from after the constant pool or will leave the delay slot
2568 empty). This gives 510.
2569 For SImode: range is 1020, add 4 because pc counts from address of
2570 second instruction after this one, subtract 2 in case pc is 2 byte
2571 aligned, subtract 2 for the jump instruction that we may need to emit
2572 before the table, subtract 2 for the instruction that fills the jump
2573 delay slot. This gives 1018. */
2575 /* The branch will always be shortened now that the reference address for
2576 forward branches is the successor address, thus we need no longer make
2577 adjustments to the [sh]i_limit for -O0. */
2582 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
2584 int inc
= get_attr_length (from
);
2587 if (GET_CODE (from
) == CODE_LABEL
)
2590 new_align
= 1 << label_to_alignment (from
);
2591 else if (GET_CODE (prev_nonnote_insn (from
)) == BARRIER
)
2592 new_align
= 1 << barrier_align (from
);
2598 if (GET_CODE (from
) == BARRIER
)
2601 found_barrier
= from
;
2603 /* If we are at the end of the function, or in front of an alignment
2604 instruction, we need not insert an extra alignment. We prefer
2605 this kind of barrier. */
2606 if (barrier_align (from
) > 2)
2607 good_barrier
= from
;
2610 if (broken_move (from
))
2613 enum machine_mode mode
;
2615 pat
= PATTERN (from
);
2616 if (GET_CODE (pat
) == PARALLEL
)
2617 pat
= XVECEXP (pat
, 0, 0);
2618 src
= SET_SRC (pat
);
2619 dst
= SET_DEST (pat
);
2620 mode
= GET_MODE (dst
);
2622 /* We must explicitly check the mode, because sometimes the
2623 front end will generate code to load unsigned constants into
2624 HImode targets without properly sign extending them. */
2626 || (mode
== SImode
&& hi_const (src
) && REGNO (dst
) != FPUL_REG
))
2629 /* We put the short constants before the long constants, so
2630 we must count the length of short constants in the range
2631 for the long constants. */
2632 /* ??? This isn't optimal, but is easy to do. */
2637 /* We dump DF/DI constants before SF/SI ones, because
2638 the limit is the same, but the alignment requirements
2639 are higher. We may waste up to 4 additional bytes
2640 for alignment, and the DF/DI constant may have
2641 another SF/SI constant placed before it. */
2642 if (TARGET_SHCOMPACT
2644 && (mode
== DFmode
|| mode
== DImode
))
2649 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
2651 if (found_si
> count_si
)
2652 count_si
= found_si
;
2653 found_si
+= GET_MODE_SIZE (mode
);
2655 si_limit
-= GET_MODE_SIZE (mode
);
2658 /* See the code in machine_dependent_reorg, which has a similar if
2659 statement that generates a new mova insn in many cases. */
2660 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
2670 barrier_before_mova
= good_barrier
? good_barrier
: found_barrier
;
2672 if (found_si
> count_si
)
2673 count_si
= found_si
;
2675 else if (GET_CODE (from
) == JUMP_INSN
2676 && (GET_CODE (PATTERN (from
)) == ADDR_VEC
2677 || GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
))
2681 if (barrier_align (next_real_insn (from
)) == CACHE_LOG
)
2683 /* We have just passed the barrier in front of the
2684 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2685 the ADDR_DIFF_VEC is accessed as data, just like our pool
2686 constants, this is a good opportunity to accommodate what
2687 we have gathered so far.
2688 If we waited any longer, we could end up at a barrier in
2689 front of code, which gives worse cache usage for separated
2690 instruction / data caches. */
2691 good_barrier
= found_barrier
;
2696 rtx body
= PATTERN (from
);
2697 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
2700 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2701 else if (GET_CODE (from
) == JUMP_INSN
2703 && ! TARGET_SMALLCODE
)
2709 if (new_align
> si_align
)
2711 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
2712 si_align
= new_align
;
2714 count_si
= (count_si
+ new_align
- 1) & -new_align
;
2719 if (new_align
> hi_align
)
2721 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
2722 hi_align
= new_align
;
2724 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
2726 from
= NEXT_INSN (from
);
2733 /* Try as we might, the leading mova is out of range. Change
2734 it into a load (which will become a pcload) and retry. */
2735 SET_SRC (PATTERN (mova
)) = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
2736 INSN_CODE (mova
) = -1;
2737 return find_barrier (0, 0, mova
);
2741 /* Insert the constant pool table before the mova instruction,
2742 to prevent the mova label reference from going out of range. */
2744 good_barrier
= found_barrier
= barrier_before_mova
;
2750 if (good_barrier
&& next_real_insn (found_barrier
))
2751 found_barrier
= good_barrier
;
2755 /* We didn't find a barrier in time to dump our stuff,
2756 so we'll make one. */
2757 rtx label
= gen_label_rtx ();
2759 /* If we exceeded the range, then we must back up over the last
2760 instruction we looked at. Otherwise, we just need to undo the
2761 NEXT_INSN at the end of the loop. */
2762 if (count_hi
> hi_limit
|| count_si
> si_limit
)
2763 from
= PREV_INSN (PREV_INSN (from
));
2765 from
= PREV_INSN (from
);
2767 /* Walk back to be just before any jump or label.
2768 Putting it before a label reduces the number of times the branch
2769 around the constant pool table will be hit. Putting it before
2770 a jump makes it more likely that the bra delay slot will be
2772 while (GET_CODE (from
) == JUMP_INSN
|| GET_CODE (from
) == NOTE
2773 || GET_CODE (from
) == CODE_LABEL
)
2774 from
= PREV_INSN (from
);
2776 from
= emit_jump_insn_after (gen_jump (label
), from
);
2777 JUMP_LABEL (from
) = label
;
2778 LABEL_NUSES (label
) = 1;
2779 found_barrier
= emit_barrier_after (from
);
2780 emit_label_after (label
, found_barrier
);
2783 return found_barrier
;
2786 /* If the instruction INSN is implemented by a special function, and we can
2787 positively find the register that is used to call the sfunc, and this
2788 register is not used anywhere else in this instruction - except as the
2789 destination of a set, return this register; else, return 0. */
2791 sfunc_uses_reg (insn
)
2795 rtx pattern
, part
, reg_part
, reg
;
2797 if (GET_CODE (insn
) != INSN
)
2799 pattern
= PATTERN (insn
);
2800 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
2803 for (reg_part
= 0, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2805 part
= XVECEXP (pattern
, 0, i
);
2806 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
2811 reg
= XEXP (reg_part
, 0);
2812 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2814 part
= XVECEXP (pattern
, 0, i
);
2815 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
2817 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
2818 && GET_CODE (SET_DEST (part
)) == REG
)
2819 ? SET_SRC (part
) : part
)))
2825 /* See if the only way in which INSN uses REG is by calling it, or by
2826 setting it while calling it. Set *SET to a SET rtx if the register
2830 noncall_uses_reg (reg
, insn
, set
)
2839 reg2
= sfunc_uses_reg (insn
);
2840 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
2842 pattern
= single_set (insn
);
2844 && GET_CODE (SET_DEST (pattern
)) == REG
2845 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2849 if (GET_CODE (insn
) != CALL_INSN
)
2851 /* We don't use rtx_equal_p because we don't care if the mode is
2853 pattern
= single_set (insn
);
2855 && GET_CODE (SET_DEST (pattern
)) == REG
2856 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2862 par
= PATTERN (insn
);
2863 if (GET_CODE (par
) == PARALLEL
)
2864 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
2866 part
= XVECEXP (par
, 0, i
);
2867 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
2870 return reg_mentioned_p (reg
, SET_SRC (pattern
));
2876 pattern
= PATTERN (insn
);
2878 if (GET_CODE (pattern
) == PARALLEL
)
2882 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2883 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
2885 pattern
= XVECEXP (pattern
, 0, 0);
2888 if (GET_CODE (pattern
) == SET
)
2890 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
2892 /* We don't use rtx_equal_p, because we don't care if the
2893 mode is different. */
2894 if (GET_CODE (SET_DEST (pattern
)) != REG
2895 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
2901 pattern
= SET_SRC (pattern
);
2904 if (GET_CODE (pattern
) != CALL
2905 || GET_CODE (XEXP (pattern
, 0)) != MEM
2906 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
2912 /* Given a X, a pattern of an insn or a part of it, return a mask of used
2913 general registers. Bits 0..15 mean that the respective registers
2914 are used as inputs in the instruction. Bits 16..31 mean that the
2915 registers 0..15, respectively, are used as outputs, or are clobbered.
2916 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
2918 regs_used (x
, is_dest
)
2927 code
= GET_CODE (x
);
2932 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2933 << (REGNO (x
) + is_dest
));
2937 rtx y
= SUBREG_REG (x
);
2939 if (GET_CODE (y
) != REG
)
2942 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2944 subreg_regno_offset (REGNO (y
),
2947 GET_MODE (x
)) + is_dest
));
2951 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
2953 /* If there was a return value, it must have been indicated with USE. */
2968 fmt
= GET_RTX_FORMAT (code
);
2970 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2975 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2976 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
2978 else if (fmt
[i
] == 'e')
2979 used
|= regs_used (XEXP (x
, i
), is_dest
);
2984 /* Create an instruction that prevents redirection of a conditional branch
2985 to the destination of the JUMP with address ADDR.
2986 If the branch needs to be implemented as an indirect jump, try to find
2987 a scratch register for it.
2988 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
2989 If any preceding insn that doesn't fit into a delay slot is good enough,
2990 pass 1. Pass 2 if a definite blocking insn is needed.
2991 -1 is used internally to avoid deep recursion.
2992 If a blocking instruction is made or recognized, return it. */
2995 gen_block_redirect (jump
, addr
, need_block
)
2997 int addr
, need_block
;
3000 rtx prev
= prev_nonnote_insn (jump
);
3003 /* First, check if we already have an instruction that satisfies our need. */
3004 if (prev
&& GET_CODE (prev
) == INSN
&& ! INSN_DELETED_P (prev
))
3006 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
3008 if (GET_CODE (PATTERN (prev
)) == USE
3009 || GET_CODE (PATTERN (prev
)) == CLOBBER
3010 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3012 else if ((need_block
&= ~1) < 0)
3014 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
3017 /* We can't use JUMP_LABEL here because it might be undefined
3018 when not optimizing. */
3019 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
3020 /* If the branch is out of range, try to find a scratch register for it. */
3022 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3026 /* Don't look for the stack pointer as a scratch register,
3027 it would cause trouble if an interrupt occurred. */
3028 unsigned try = 0x7fff, used
;
3029 int jump_left
= flag_expensive_optimizations
+ 1;
3031 /* It is likely that the most recent eligible instruction is wanted for
3032 the delay slot. Therefore, find out which registers it uses, and
3033 try to avoid using them. */
3035 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
3039 if (INSN_DELETED_P (scan
))
3041 code
= GET_CODE (scan
);
3042 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
3045 && GET_CODE (PATTERN (scan
)) != USE
3046 && GET_CODE (PATTERN (scan
)) != CLOBBER
3047 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
3049 try &= ~regs_used (PATTERN (scan
), 0);
3053 for (used
= dead
= 0, scan
= JUMP_LABEL (jump
);
3054 (scan
= NEXT_INSN (scan
)); )
3058 if (INSN_DELETED_P (scan
))
3060 code
= GET_CODE (scan
);
3061 if (GET_RTX_CLASS (code
) == 'i')
3063 used
|= regs_used (PATTERN (scan
), 0);
3064 if (code
== CALL_INSN
)
3065 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
3066 dead
|= (used
>> 16) & ~used
;
3072 if (code
== JUMP_INSN
)
3074 if (jump_left
-- && simplejump_p (scan
))
3075 scan
= JUMP_LABEL (scan
);
3081 /* Mask out the stack pointer again, in case it was
3082 the only 'free' register we have found. */
3085 /* If the immediate destination is still in range, check for possible
3086 threading with a jump beyond the delay slot insn.
3087 Don't check if we are called recursively; the jump has been or will be
3088 checked in a different invocation then. */
3090 else if (optimize
&& need_block
>= 0)
3092 rtx next
= next_active_insn (next_active_insn (dest
));
3093 if (next
&& GET_CODE (next
) == JUMP_INSN
3094 && GET_CODE (PATTERN (next
)) == SET
3095 && recog_memoized (next
) == CODE_FOR_jump
)
3097 dest
= JUMP_LABEL (next
);
3099 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3101 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
3107 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
3109 /* It would be nice if we could convert the jump into an indirect
3110 jump / far branch right now, and thus exposing all constituent
3111 instructions to further optimization. However, reorg uses
3112 simplejump_p to determine if there is an unconditional jump where
3113 it should try to schedule instructions from the target of the
3114 branch; simplejump_p fails for indirect jumps even if they have
3116 rtx insn
= emit_insn_before (gen_indirect_jump_scratch
3117 (reg
, GEN_INT (INSN_UID (JUMP_LABEL (jump
))))
3119 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
3122 else if (need_block
)
3123 /* We can't use JUMP_LABEL here because it might be undefined
3124 when not optimizing. */
3125 return emit_insn_before (gen_block_branch_redirect
3126 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))))
3131 #define CONDJUMP_MIN -252
3132 #define CONDJUMP_MAX 262
3135 /* A label (to be placed) in front of the jump
3136 that jumps to our ultimate destination. */
3138 /* Where we are going to insert it if we cannot move the jump any farther,
3139 or the jump itself if we have picked up an existing jump. */
3141 /* The ultimate destination. */
3143 struct far_branch
*prev
;
3144 /* If the branch has already been created, its address;
3145 else the address of its first prospective user. */
3149 static void gen_far_branch
PARAMS ((struct far_branch
*));
3150 enum mdep_reorg_phase_e mdep_reorg_phase
;
3153 struct far_branch
*bp
;
3155 rtx insn
= bp
->insert_place
;
3157 rtx label
= gen_label_rtx ();
3159 emit_label_after (label
, insn
);
3162 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
3163 LABEL_NUSES (bp
->far_label
)++;
3166 jump
= emit_jump_insn_after (gen_return (), insn
);
3167 /* Emit a barrier so that reorg knows that any following instructions
3168 are not reachable via a fall-through path.
3169 But don't do this when not optimizing, since we wouldn't supress the
3170 alignment for the barrier then, and could end up with out-of-range
3171 pc-relative loads. */
3173 emit_barrier_after (jump
);
3174 emit_label_after (bp
->near_label
, insn
);
3175 JUMP_LABEL (jump
) = bp
->far_label
;
3176 if (! invert_jump (insn
, label
, 1))
3178 /* Prevent reorg from undoing our splits. */
3179 gen_block_redirect (jump
, bp
->address
+= 2, 2);
3182 /* Fix up ADDR_DIFF_VECs. */
3184 fixup_addr_diff_vecs (first
)
3189 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3191 rtx vec_lab
, pat
, prev
, prevpat
, x
, braf_label
;
3193 if (GET_CODE (insn
) != JUMP_INSN
3194 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
3196 pat
= PATTERN (insn
);
3197 vec_lab
= XEXP (XEXP (pat
, 0), 0);
3199 /* Search the matching casesi_jump_2. */
3200 for (prev
= vec_lab
; ; prev
= PREV_INSN (prev
))
3202 if (GET_CODE (prev
) != JUMP_INSN
)
3204 prevpat
= PATTERN (prev
);
3205 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
3207 x
= XVECEXP (prevpat
, 0, 1);
3208 if (GET_CODE (x
) != USE
)
3211 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
3215 /* Emit the reference label of the braf where it belongs, right after
3216 the casesi_jump_2 (i.e. braf). */
3217 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
3218 emit_label_after (braf_label
, prev
);
3220 /* Fix up the ADDR_DIF_VEC to be relative
3221 to the reference address of the braf. */
3222 XEXP (XEXP (pat
, 0), 0) = braf_label
;
3226 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3227 a barrier. Return the base 2 logarithm of the desired alignment. */
3229 barrier_align (barrier_or_label
)
3230 rtx barrier_or_label
;
3232 rtx next
= next_real_insn (barrier_or_label
), pat
, prev
;
3233 int slot
, credit
, jump_to_next
;
3238 pat
= PATTERN (next
);
3240 if (GET_CODE (pat
) == ADDR_DIFF_VEC
)
3243 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
3244 /* This is a barrier in front of a constant table. */
3247 prev
= prev_real_insn (barrier_or_label
);
3248 if (GET_CODE (PATTERN (prev
)) == ADDR_DIFF_VEC
)
3250 pat
= PATTERN (prev
);
3251 /* If this is a very small table, we want to keep the alignment after
3252 the table to the minimum for proper code alignment. */
3253 return ((TARGET_SMALLCODE
3254 || (XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
3255 <= (unsigned)1 << (CACHE_LOG
- 2)))
3256 ? 1 << TARGET_SHMEDIA
: CACHE_LOG
);
3259 if (TARGET_SMALLCODE
)
3262 if (! TARGET_SH2
|| ! optimize
)
3265 /* When fixing up pcloads, a constant table might be inserted just before
3266 the basic block that ends with the barrier. Thus, we can't trust the
3267 instruction lengths before that. */
3268 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
3270 /* Check if there is an immediately preceding branch to the insn beyond
3271 the barrier. We must weight the cost of discarding useful information
3272 from the current cache line when executing this branch and there is
3273 an alignment, against that of fetching unneeded insn in front of the
3274 branch target when there is no alignment. */
3276 /* There are two delay_slot cases to consider. One is the simple case
3277 where the preceding branch is to the insn beyond the barrier (simple
3278 delay slot filling), and the other is where the preceding branch has
3279 a delay slot that is a duplicate of the insn after the barrier
3280 (fill_eager_delay_slots) and the branch is to the insn after the insn
3281 after the barrier. */
3283 /* PREV is presumed to be the JUMP_INSN for the barrier under
3284 investigation. Skip to the insn before it. */
3285 prev
= prev_real_insn (prev
);
3287 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
3288 credit
>= 0 && prev
&& GET_CODE (prev
) == INSN
;
3289 prev
= prev_real_insn (prev
))
3292 if (GET_CODE (PATTERN (prev
)) == USE
3293 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
3295 if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
3297 prev
= XVECEXP (PATTERN (prev
), 0, 1);
3298 if (INSN_UID (prev
) == INSN_UID (next
))
3300 /* Delay slot was filled with insn at jump target. */
3307 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3309 credit
-= get_attr_length (prev
);
3312 && GET_CODE (prev
) == JUMP_INSN
3313 && JUMP_LABEL (prev
))
3317 || next_real_insn (JUMP_LABEL (prev
)) == next
3318 /* If relax_delay_slots() decides NEXT was redundant
3319 with some previous instruction, it will have
3320 redirected PREV's jump to the following insn. */
3321 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
3322 /* There is no upper bound on redundant instructions
3323 that might have been skipped, but we must not put an
3324 alignment where none had been before. */
3325 || (x
= (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
)))),
3327 && (INSN_CODE (x
) == CODE_FOR_block_branch_redirect
3328 || INSN_CODE (x
) == CODE_FOR_indirect_jump_scratch
))))
3330 rtx pat
= PATTERN (prev
);
3331 if (GET_CODE (pat
) == PARALLEL
)
3332 pat
= XVECEXP (pat
, 0, 0);
3333 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
3342 /* If we are inside a phony loop, almost any kind of label can turn up as the
3343 first one in the loop. Aligning a braf label causes incorrect switch
3344 destination addresses; we can detect braf labels because they are
3345 followed by a BARRIER.
3346 Applying loop alignment to small constant or switch tables is a waste
3347 of space, so we suppress this too. */
3349 sh_loop_align (label
)
3355 next
= next_nonnote_insn (next
);
3356 while (next
&& GET_CODE (next
) == CODE_LABEL
);
3360 || GET_CODE (PATTERN (next
)) == ADDR_DIFF_VEC
3361 || recog_memoized (next
) == CODE_FOR_consttable_2
)
3370 /* Exported to toplev.c.
3372 Do a final pass over the function, just before delayed branch
3376 machine_dependent_reorg (first
)
3381 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
3382 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
3384 /* We must split call insns before introducing `mova's. If we're
3385 optimizing, they'll have already been split. Otherwise, make
3386 sure we don't split them too late. */
3388 split_all_insns_noflow ();
3393 /* If relaxing, generate pseudo-ops to associate function calls with
3394 the symbols they call. It does no harm to not generate these
3395 pseudo-ops. However, when we can generate them, it enables to
3396 linker to potentially relax the jsr to a bsr, and eliminate the
3397 register load and, possibly, the constant pool entry. */
3399 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
3402 /* Remove all REG_LABEL notes. We want to use them for our own
3403 purposes. This works because none of the remaining passes
3404 need to look at them.
3406 ??? But it may break in the future. We should use a machine
3407 dependent REG_NOTE, or some other approach entirely. */
3408 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3414 while ((note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
)) != 0)
3415 remove_note (insn
, note
);
3419 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3421 rtx pattern
, reg
, link
, set
, scan
, dies
, label
;
3422 int rescan
= 0, foundinsn
= 0;
3424 if (GET_CODE (insn
) == CALL_INSN
)
3426 pattern
= PATTERN (insn
);
3428 if (GET_CODE (pattern
) == PARALLEL
)
3429 pattern
= XVECEXP (pattern
, 0, 0);
3430 if (GET_CODE (pattern
) == SET
)
3431 pattern
= SET_SRC (pattern
);
3433 if (GET_CODE (pattern
) != CALL
3434 || GET_CODE (XEXP (pattern
, 0)) != MEM
)
3437 reg
= XEXP (XEXP (pattern
, 0), 0);
3441 reg
= sfunc_uses_reg (insn
);
3446 if (GET_CODE (reg
) != REG
)
3449 /* This is a function call via REG. If the only uses of REG
3450 between the time that it is set and the time that it dies
3451 are in function calls, then we can associate all the
3452 function calls with the setting of REG. */
3454 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
3456 if (REG_NOTE_KIND (link
) != 0)
3458 set
= single_set (XEXP (link
, 0));
3459 if (set
&& rtx_equal_p (reg
, SET_DEST (set
)))
3461 link
= XEXP (link
, 0);
3468 /* ??? Sometimes global register allocation will have
3469 deleted the insn pointed to by LOG_LINKS. Try
3470 scanning backward to find where the register is set. */
3471 for (scan
= PREV_INSN (insn
);
3472 scan
&& GET_CODE (scan
) != CODE_LABEL
;
3473 scan
= PREV_INSN (scan
))
3475 if (! INSN_P (scan
))
3478 if (! reg_mentioned_p (reg
, scan
))
3481 if (noncall_uses_reg (reg
, scan
, &set
))
3495 /* The register is set at LINK. */
3497 /* We can only optimize the function call if the register is
3498 being set to a symbol. In theory, we could sometimes
3499 optimize calls to a constant location, but the assembler
3500 and linker do not support that at present. */
3501 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
3502 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
3505 /* Scan forward from LINK to the place where REG dies, and
3506 make sure that the only insns which use REG are
3507 themselves function calls. */
3509 /* ??? This doesn't work for call targets that were allocated
3510 by reload, since there may not be a REG_DEAD note for the
3514 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
3518 /* Don't try to trace forward past a CODE_LABEL if we haven't
3519 seen INSN yet. Ordinarily, we will only find the setting insn
3520 in LOG_LINKS if it is in the same basic block. However,
3521 cross-jumping can insert code labels in between the load and
3522 the call, and can result in situations where a single call
3523 insn may have two targets depending on where we came from. */
3525 if (GET_CODE (scan
) == CODE_LABEL
&& ! foundinsn
)
3528 if (! INSN_P (scan
))
3531 /* Don't try to trace forward past a JUMP. To optimize
3532 safely, we would have to check that all the
3533 instructions at the jump destination did not use REG. */
3535 if (GET_CODE (scan
) == JUMP_INSN
)
3538 if (! reg_mentioned_p (reg
, scan
))
3541 if (noncall_uses_reg (reg
, scan
, &scanset
))
3548 && (GET_CODE (scan
) == CALL_INSN
|| sfunc_uses_reg (scan
)))
3550 /* There is a function call to this register other
3551 than the one we are checking. If we optimize
3552 this call, we need to rescan again below. */
3556 /* ??? We shouldn't have to worry about SCANSET here.
3557 We should just be able to check for a REG_DEAD note
3558 on a function call. However, the REG_DEAD notes are
3559 apparently not dependable around libcalls; c-torture
3560 execute/920501-2 is a test case. If SCANSET is set,
3561 then this insn sets the register, so it must have
3562 died earlier. Unfortunately, this will only handle
3563 the cases in which the register is, in fact, set in a
3566 /* ??? We shouldn't have to use FOUNDINSN here.
3567 However, the LOG_LINKS fields are apparently not
3568 entirely reliable around libcalls;
3569 newlib/libm/math/e_pow.c is a test case. Sometimes
3570 an insn will appear in LOG_LINKS even though it is
3571 not the most recent insn which sets the register. */
3575 || find_reg_note (scan
, REG_DEAD
, reg
)))
3584 /* Either there was a branch, or some insn used REG
3585 other than as a function call address. */
3589 /* Create a code label, and put it in a REG_LABEL note on
3590 the insn which sets the register, and on each call insn
3591 which uses the register. In final_prescan_insn we look
3592 for the REG_LABEL notes, and output the appropriate label
3595 label
= gen_label_rtx ();
3596 REG_NOTES (link
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
3598 REG_NOTES (insn
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
3607 scan
= NEXT_INSN (scan
);
3609 && ((GET_CODE (scan
) == CALL_INSN
3610 && reg_mentioned_p (reg
, scan
))
3611 || ((reg2
= sfunc_uses_reg (scan
))
3612 && REGNO (reg2
) == REGNO (reg
))))
3614 = gen_rtx_INSN_LIST (REG_LABEL
, label
, REG_NOTES (scan
));
3616 while (scan
!= dies
);
3622 fixup_addr_diff_vecs (first
);
3626 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
3627 shorten_branches (first
);
3629 /* Scan the function looking for move instructions which have to be
3630 changed to pc-relative loads and insert the literal tables. */
3632 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
3633 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
3640 else if (GET_CODE (insn
) == JUMP_INSN
3641 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3649 /* Some code might have been inserted between the mova and
3650 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3651 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
3652 total
+= get_attr_length (scan
);
3654 /* range of mova is 1020, add 4 because pc counts from address of
3655 second instruction after this one, subtract 2 in case pc is 2
3656 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3657 cancels out with alignment effects of the mova itself. */
3660 /* Change the mova into a load, and restart scanning
3661 there. broken_move will then return true for mova. */
3662 SET_SRC (PATTERN (mova
))
3663 = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
3664 INSN_CODE (mova
) = -1;
3668 if (broken_move (insn
))
3671 /* Scan ahead looking for a barrier to stick the constant table
3673 rtx barrier
= find_barrier (num_mova
, mova
, insn
);
3674 rtx last_float_move
, last_float
= 0, *last_float_addr
;
3675 int may_need_align
= 1;
3677 if (num_mova
&& ! mova_p (mova
))
3679 /* find_barrier had to change the first mova into a
3680 pcload; thus, we have to start with this new pcload. */
3684 /* Now find all the moves between the points and modify them. */
3685 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
3687 if (GET_CODE (scan
) == CODE_LABEL
)
3689 if (broken_move (scan
))
3691 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
3695 enum machine_mode mode
;
3697 if (GET_CODE (pat
) == PARALLEL
)
3698 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
3699 src
= SET_SRC (pat
);
3700 dst
= SET_DEST (pat
);
3701 mode
= GET_MODE (dst
);
3703 if (mode
== SImode
&& hi_const (src
)
3704 && REGNO (dst
) != FPUL_REG
)
3709 while (GET_CODE (dst
) == SUBREG
)
3711 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
3712 GET_MODE (SUBREG_REG (dst
)),
3715 dst
= SUBREG_REG (dst
);
3717 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
3720 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
3722 /* This must be an insn that clobbers r0. */
3723 rtx clobber
= XVECEXP (PATTERN (scan
), 0,
3724 XVECLEN (PATTERN (scan
), 0) - 1);
3726 if (GET_CODE (clobber
) != CLOBBER
3727 || ! rtx_equal_p (XEXP (clobber
, 0), r0_rtx
))
3731 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
3733 if (TARGET_SHCOMPACT
)
3735 /* The first SFmode constant after a DFmode
3736 constant may be pulled before a sequence
3737 of DFmode constants, so the second SFmode
3738 needs a label, just in case. */
3739 if (GET_MODE_SIZE (mode
) == 4)
3741 if (last_float
&& may_need_align
)
3746 && (GET_MODE_SIZE (GET_MODE (last_float
))
3747 != GET_MODE_SIZE (mode
)))
3750 if (GET_MODE_SIZE (mode
) == 4)
3754 lab
= add_constant (src
, mode
, last_float
);
3756 emit_insn_before (gen_mova (lab
), scan
);
3759 /* There will be a REG_UNUSED note for r0 on
3760 LAST_FLOAT_MOVE; we have to change it to REG_INC,
3761 lest reorg:mark_target_live_regs will not
3762 consider r0 to be used, and we end up with delay
3763 slot insn in front of SCAN that clobbers r0. */
3765 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
3767 /* If we are not optimizing, then there may not be
3770 PUT_MODE (note
, REG_INC
);
3772 *last_float_addr
= r0_inc_rtx
;
3774 last_float_move
= scan
;
3776 newsrc
= gen_rtx (MEM
, mode
,
3777 (((TARGET_SH4
&& ! TARGET_FMOVD
)
3778 || REGNO (dst
) == FPUL_REG
)
3781 last_float_addr
= &XEXP (newsrc
, 0);
3783 /* Remove the clobber of r0. */
3784 XEXP (clobber
, 0) = gen_rtx_SCRATCH (Pmode
);
3786 /* This is a mova needing a label. Create it. */
3787 else if (GET_CODE (src
) == UNSPEC
3788 && XINT (src
, 1) == UNSPEC_MOVA
3789 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
3791 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
3792 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
3793 newsrc
= gen_rtx_UNSPEC (VOIDmode
,
3794 gen_rtvec (1, newsrc
),
3799 lab
= add_constant (src
, mode
, 0);
3800 newsrc
= gen_rtx_MEM (mode
,
3801 gen_rtx_LABEL_REF (VOIDmode
, lab
));
3803 RTX_UNCHANGING_P (newsrc
) = 1;
3804 *patp
= gen_rtx_SET (VOIDmode
, dst
, newsrc
);
3805 INSN_CODE (scan
) = -1;
3808 dump_table (barrier
);
3813 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
3814 INSN_ADDRESSES_FREE ();
3815 split_branches (first
);
3817 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
3818 also has an effect on the register that holds the addres of the sfunc.
3819 Insert an extra dummy insn in front of each sfunc that pretends to
3820 use this register. */
3821 if (flag_delayed_branch
)
3823 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3825 rtx reg
= sfunc_uses_reg (insn
);
3829 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
3833 /* fpscr is not actually a user variable, but we pretend it is for the
3834 sake of the previous optimization passes, since we want it handled like
3835 one. However, we don't have any debugging information for it, so turn
3836 it into a non-user variable now. */
3838 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
3840 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
3844 get_dest_uid (label
, max_uid
)
3848 rtx dest
= next_real_insn (label
);
3851 /* This can happen for an undefined label. */
3853 dest_uid
= INSN_UID (dest
);
3854 /* If this is a newly created branch redirection blocking instruction,
3855 we cannot index the branch_uid or insn_addresses arrays with its
3856 uid. But then, we won't need to, because the actual destination is
3857 the following branch. */
3858 while (dest_uid
>= max_uid
)
3860 dest
= NEXT_INSN (dest
);
3861 dest_uid
= INSN_UID (dest
);
3863 if (GET_CODE (dest
) == JUMP_INSN
&& GET_CODE (PATTERN (dest
)) == RETURN
)
3868 /* Split condbranches that are out of range. Also add clobbers for
3869 scratch registers that are needed in far jumps.
3870 We do this before delay slot scheduling, so that it can take our
3871 newly created instructions into account. It also allows us to
3872 find branches with common targets more easily. */
3875 split_branches (first
)
3879 struct far_branch
**uid_branch
, *far_branch_list
= 0;
3880 int max_uid
= get_max_uid ();
3882 /* Find out which branches are out of range. */
3883 shorten_branches (first
);
3885 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
3886 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
3888 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3889 if (! INSN_P (insn
))
3891 else if (INSN_DELETED_P (insn
))
3893 /* Shorten_branches would split this instruction again,
3894 so transform it into a note. */
3895 PUT_CODE (insn
, NOTE
);
3896 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
3897 NOTE_SOURCE_FILE (insn
) = 0;
3899 else if (GET_CODE (insn
) == JUMP_INSN
3900 /* Don't mess with ADDR_DIFF_VEC */
3901 && (GET_CODE (PATTERN (insn
)) == SET
3902 || GET_CODE (PATTERN (insn
)) == RETURN
))
3904 enum attr_type type
= get_attr_type (insn
);
3905 if (type
== TYPE_CBRANCH
)
3909 if (get_attr_length (insn
) > 4)
3911 rtx src
= SET_SRC (PATTERN (insn
));
3912 rtx olabel
= XEXP (XEXP (src
, 1), 0);
3913 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
3915 int dest_uid
= get_dest_uid (olabel
, max_uid
);
3916 struct far_branch
*bp
= uid_branch
[dest_uid
];
3918 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
3919 the label if the LABEL_NUSES count drops to zero. There is
3920 always a jump_optimize pass that sets these values, but it
3921 proceeds to delete unreferenced code, and then if not
3922 optimizing, to un-delete the deleted instructions, thus
3923 leaving labels with too low uses counts. */
3926 JUMP_LABEL (insn
) = olabel
;
3927 LABEL_NUSES (olabel
)++;
3931 bp
= (struct far_branch
*) alloca (sizeof *bp
);
3932 uid_branch
[dest_uid
] = bp
;
3933 bp
->prev
= far_branch_list
;
3934 far_branch_list
= bp
;
3936 = XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1), 0);
3937 LABEL_NUSES (bp
->far_label
)++;
3941 label
= bp
->near_label
;
3942 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
3944 rtx block
= bp
->insert_place
;
3946 if (GET_CODE (PATTERN (block
)) == RETURN
)
3947 block
= PREV_INSN (block
);
3949 block
= gen_block_redirect (block
,
3951 label
= emit_label_after (gen_label_rtx (),
3953 bp
->near_label
= label
;
3955 else if (label
&& ! NEXT_INSN (label
))
3957 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
3958 bp
->insert_place
= insn
;
3960 gen_far_branch (bp
);
3964 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
3966 bp
->near_label
= label
= gen_label_rtx ();
3967 bp
->insert_place
= insn
;
3970 if (! redirect_jump (insn
, label
, 1))
3975 /* get_attr_length (insn) == 2 */
3976 /* Check if we have a pattern where reorg wants to redirect
3977 the branch to a label from an unconditional branch that
3979 /* We can't use JUMP_LABEL here because it might be undefined
3980 when not optimizing. */
3981 /* A syntax error might cause beyond to be NULL_RTX. */
3983 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
3987 && (GET_CODE (beyond
) == JUMP_INSN
3988 || ((beyond
= next_active_insn (beyond
))
3989 && GET_CODE (beyond
) == JUMP_INSN
))
3990 && GET_CODE (PATTERN (beyond
)) == SET
3991 && recog_memoized (beyond
) == CODE_FOR_jump
3993 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
3994 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
3996 gen_block_redirect (beyond
,
3997 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
4000 next
= next_active_insn (insn
);
4002 if ((GET_CODE (next
) == JUMP_INSN
4003 || GET_CODE (next
= next_active_insn (next
)) == JUMP_INSN
)
4004 && GET_CODE (PATTERN (next
)) == SET
4005 && recog_memoized (next
) == CODE_FOR_jump
4007 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
4008 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
4010 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
4012 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
4014 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
4017 struct far_branch
*bp
;
4019 if (type
== TYPE_JUMP
)
4021 far_label
= XEXP (SET_SRC (PATTERN (insn
)), 0);
4022 dest_uid
= get_dest_uid (far_label
, max_uid
);
4025 /* Parse errors can lead to labels outside
4027 if (! NEXT_INSN (far_label
))
4032 JUMP_LABEL (insn
) = far_label
;
4033 LABEL_NUSES (far_label
)++;
4035 redirect_jump (insn
, NULL_RTX
, 1);
4039 bp
= uid_branch
[dest_uid
];
4042 bp
= (struct far_branch
*) alloca (sizeof *bp
);
4043 uid_branch
[dest_uid
] = bp
;
4044 bp
->prev
= far_branch_list
;
4045 far_branch_list
= bp
;
4047 bp
->far_label
= far_label
;
4049 LABEL_NUSES (far_label
)++;
4051 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
4052 if (addr
- bp
->address
<= CONDJUMP_MAX
)
4053 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
4056 gen_far_branch (bp
);
4062 bp
->insert_place
= insn
;
4064 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
4066 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
4069 /* Generate all pending far branches,
4070 and free our references to the far labels. */
4071 while (far_branch_list
)
4073 if (far_branch_list
->near_label
4074 && ! NEXT_INSN (far_branch_list
->near_label
))
4075 gen_far_branch (far_branch_list
);
4077 && far_branch_list
->far_label
4078 && ! --LABEL_NUSES (far_branch_list
->far_label
))
4079 delete_insn (far_branch_list
->far_label
);
4080 far_branch_list
= far_branch_list
->prev
;
4083 /* Instruction length information is no longer valid due to the new
4084 instructions that have been generated. */
4085 init_insn_lengths ();
4088 /* Dump out instruction addresses, which is useful for debugging the
4089 constant pool table stuff.
4091 If relaxing, output the label and pseudo-ops used to link together
4092 calls and the instruction which set the registers. */
4094 /* ??? This is unnecessary, and probably should be deleted. This makes
4095 the insn_addresses declaration above unnecessary. */
4097 /* ??? The addresses printed by this routine for insns are nonsense for
4098 insns which are inside of a sequence where none of the inner insns have
4099 variable length. This is because the second pass of shorten_branches
4100 does not bother to update them. */
4103 final_prescan_insn (insn
, opvec
, noperands
)
4105 rtx
*opvec ATTRIBUTE_UNUSED
;
4106 int noperands ATTRIBUTE_UNUSED
;
4108 if (TARGET_DUMPISIZE
)
4109 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
4115 note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
);
4120 pattern
= PATTERN (insn
);
4121 if (GET_CODE (pattern
) == PARALLEL
)
4122 pattern
= XVECEXP (pattern
, 0, 0);
4123 if (GET_CODE (pattern
) == CALL
4124 || (GET_CODE (pattern
) == SET
4125 && (GET_CODE (SET_SRC (pattern
)) == CALL
4126 || get_attr_type (insn
) == TYPE_SFUNC
)))
4127 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
4128 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4129 else if (GET_CODE (pattern
) == SET
)
4130 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4131 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4138 /* Dump out any constants accumulated in the final pass. These will
4142 output_jump_label_table ()
4148 fprintf (asm_out_file
, "\t.align 2\n");
4149 for (i
= 0; i
< pool_size
; i
++)
4151 pool_node
*p
= &pool_vector
[i
];
4153 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4154 CODE_LABEL_NUMBER (p
->label
));
4155 output_asm_insn (".long %O0", &p
->value
);
4163 /* A full frame looks like:
4167 [ if current_function_anonymous_args
4180 local-0 <- fp points here. */
4182 /* Number of bytes pushed for anonymous args, used to pass information
4183 between expand_prologue and expand_epilogue. */
4185 static int extra_push
;
4187 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
4188 to be adjusted, and TEMP, if nonnegative, holds the register number
4189 of a general register that we may clobber. */
4192 output_stack_adjust (size
, reg
, temp
)
4199 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4204 if (CONST_OK_FOR_ADD (size
))
4205 emit_insn (GEN_ADD3 (reg
, reg
, GEN_INT (size
)));
4206 /* Try to do it with two partial adjustments; however, we must make
4207 sure that the stack is properly aligned at all times, in case
4208 an interrupt occurs between the two partial adjustments. */
4209 else if (CONST_OK_FOR_ADD (size
/ 2 & -align
)
4210 && CONST_OK_FOR_ADD (size
- (size
/ 2 & -align
)))
4212 emit_insn (GEN_ADD3 (reg
, reg
, GEN_INT (size
/ 2 & -align
)));
4213 emit_insn (GEN_ADD3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -align
))));
4219 /* If TEMP is invalid, we could temporarily save a general
4220 register to MACL. However, there is currently no need
4221 to handle this case, so just abort when we see it. */
4224 const_reg
= gen_rtx_REG (GET_MODE (reg
), temp
);
4226 /* If SIZE is negative, subtract the positive value.
4227 This sometimes allows a constant pool entry to be shared
4228 between prologue and epilogue code. */
4231 emit_insn (GEN_MOV (const_reg
, GEN_INT (-size
)));
4232 emit_insn (GEN_SUB3 (reg
, reg
, const_reg
));
4236 emit_insn (GEN_MOV (const_reg
, GEN_INT (size
)));
4237 emit_insn (GEN_ADD3 (reg
, reg
, const_reg
));
4243 /* Output RTL to push register RN onto the stack. */
4251 x
= gen_push_fpul ();
4252 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4253 && FP_OR_XD_REGISTER_P (rn
))
4255 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4257 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
4259 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
4260 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
4262 x
= gen_push (gen_rtx_REG (SImode
, rn
));
4266 = gen_rtx_EXPR_LIST (REG_INC
,
4267 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4270 /* Output RTL to pop register RN from the stack. */
4278 x
= gen_pop_fpul ();
4279 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4280 && FP_OR_XD_REGISTER_P (rn
))
4282 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4284 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
4286 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
4287 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
4289 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
4293 = gen_rtx_EXPR_LIST (REG_INC
,
4294 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4297 /* Generate code to push the regs specified in the mask. */
4301 HOST_WIDE_INT
*mask
;
4305 /* Push PR last; this gives better latencies after the prologue, and
4306 candidates for the return delay slot when there are no general
4307 registers pushed. */
4308 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4309 if (i
!= PR_REG
&& mask
[i
/ 32] & (1 << (i
% 32)))
4311 if (mask
[PR_REG
/ 32] & (1 << (PR_REG
% 32)))
4315 /* Work out the registers which need to be saved, both as a mask and a
4316 count of saved words.
4318 If doing a pragma interrupt function, then push all regs used by the
4319 function, and if we call another function (we can tell by looking at PR),
4320 make sure that all the regs it clobbers are safe too. */
4323 calc_live_regs (count_ptr
, live_regs_mask
)
4325 HOST_WIDE_INT
*live_regs_mask
;
4329 int interrupt_handler
;
4333 if ((lookup_attribute
4334 ("interrupt_handler",
4335 DECL_ATTRIBUTES (current_function_decl
)))
4337 interrupt_handler
= 1;
4339 interrupt_handler
= 0;
4341 for (count
= 0; 32 * count
< FIRST_PSEUDO_REGISTER
; count
++)
4342 live_regs_mask
[count
] = 0;
4343 /* If we can save a lot of saves by switching to double mode, do that. */
4344 if (TARGET_SH4
&& TARGET_FMOVD
&& TARGET_FPU_SINGLE
)
4345 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
4346 if (regs_ever_live
[reg
] && regs_ever_live
[reg
+1]
4347 && (! call_used_regs
[reg
] || (interrupt_handler
&& ! pragma_trapa
))
4350 target_flags
&= ~FPU_SINGLE_BIT
;
4353 pr_initial
= has_hard_reg_initial_val (Pmode
,
4355 ? PR_MEDIA_REG
: PR_REG
);
4356 pr_live
= (pr_initial
4357 ? REGNO (pr_initial
) != (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
4358 : regs_ever_live
[TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
]);
4359 /* Force PR to be live if the prologue has to call the SHmedia
4360 argument decoder or register saver. */
4361 if (TARGET_SHCOMPACT
4362 && ((current_function_args_info
.call_cookie
4363 & ~ CALL_COOKIE_RET_TRAMP (1))
4364 || current_function_has_nonlocal_label
))
4366 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
- 1; reg
>= 0; reg
--)
4368 if (reg
== (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
4370 : (interrupt_handler
&& ! pragma_trapa
)
4371 ? (/* Need to save all the regs ever live. */
4372 (regs_ever_live
[reg
]
4373 || (call_used_regs
[reg
]
4374 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
)
4376 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
4377 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
4378 && reg
!= T_REG
&& reg
!= GBR_REG
&& reg
!= FPSCR_REG
)
4379 : (/* Only push those regs which are used and need to be saved. */
4380 regs_ever_live
[reg
] && ! call_used_regs
[reg
]))
4382 live_regs_mask
[reg
/ 32] |= 1 << (reg
% 32);
4383 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
4385 if ((TARGET_SH4
|| TARGET_SH5
) && TARGET_FMOVD
4386 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg
)) == MODE_FLOAT
)
4388 if (FP_REGISTER_P (reg
))
4390 if (! TARGET_FPU_SINGLE
&& ! regs_ever_live
[reg
^ 1])
4392 live_regs_mask
[(reg
^ 1) / 32] |= 1 << ((reg
^ 1) % 32);
4393 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
^ 1));
4396 else if (XD_REGISTER_P (reg
))
4398 /* Must switch to double mode to access these registers. */
4399 target_flags
&= ~FPU_SINGLE_BIT
;
4408 /* Code to generate prologue and epilogue sequences */
4410 /* PUSHED is the number of bytes that are bing pushed on the
4411 stack for register saves. Return the frame size, padded
4412 appropriately so that the stack stays properly aligned. */
4413 static HOST_WIDE_INT
4414 rounded_frame_size (pushed
)
4417 HOST_WIDE_INT size
= get_frame_size ();
4418 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4420 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
4423 /* Choose a call-clobbered target-branch register that remains
4424 unchanged along the whole function. We set it up as the return
4425 value in the prologue. */
4427 sh_media_register_for_return ()
4432 if (! current_function_is_leaf
)
4435 tr0_used
= flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
];
4437 for (regno
= FIRST_TARGET_REG
+ tr0_used
; regno
<= LAST_TARGET_REG
; regno
++)
4438 if (call_used_regs
[regno
] && ! regs_ever_live
[regno
])
4445 sh_expand_prologue ()
4447 HOST_WIDE_INT live_regs_mask
[(FIRST_PSEUDO_REGISTER
+ 31) / 32];
4450 int save_flags
= target_flags
;
4452 current_function_interrupt
4453 = lookup_attribute ("interrupt_handler",
4454 DECL_ATTRIBUTES (current_function_decl
))
4457 /* We have pretend args if we had an object sent partially in registers
4458 and partially on the stack, e.g. a large structure. */
4459 output_stack_adjust (-current_function_pretend_args_size
4460 - current_function_args_info
.stack_regs
* 8,
4461 stack_pointer_rtx
, TARGET_SH5
? 0 : 1);
4465 if (TARGET_SHCOMPACT
&& flag_pic
&& current_function_args_info
.call_cookie
)
4466 /* We're going to use the PIC register to load the address of the
4467 incoming-argument decoder and/or of the return trampoline from
4468 the GOT, so make sure the PIC register is preserved and
4470 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
4472 if (TARGET_SHCOMPACT
4473 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
4477 /* First, make all registers with incoming arguments that will
4478 be pushed onto the stack live, so that register renaming
4479 doesn't overwrite them. */
4480 for (reg
= 0; reg
< NPARM_REGS (SImode
); reg
++)
4481 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info
.call_cookie
)
4482 >= NPARM_REGS (SImode
) - reg
)
4483 for (; reg
< NPARM_REGS (SImode
); reg
++)
4484 emit_insn (gen_shcompact_preserve_incoming_args
4485 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
4486 else if (CALL_COOKIE_INT_REG_GET
4487 (current_function_args_info
.call_cookie
, reg
) == 1)
4488 emit_insn (gen_shcompact_preserve_incoming_args
4489 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
4491 emit_move_insn (gen_rtx_REG (Pmode
, MACL_REG
),
4493 emit_move_insn (gen_rtx_REG (SImode
, R0_REG
),
4494 GEN_INT (current_function_args_info
.call_cookie
));
4495 emit_move_insn (gen_rtx_REG (SImode
, MACH_REG
),
4496 gen_rtx_REG (SImode
, R0_REG
));
4498 else if (TARGET_SHMEDIA
)
4500 int tr
= sh_media_register_for_return ();
4504 rtx insn
= emit_move_insn (gen_rtx_REG (DImode
, tr
),
4505 gen_rtx_REG (DImode
, PR_MEDIA_REG
));
4507 /* If this function only exits with sibcalls, this copy
4508 will be flagged as dead. */
4509 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4515 /* Emit the code for SETUP_VARARGS. */
4516 if (current_function_varargs
|| current_function_stdarg
)
4518 /* This is not used by the SH3E calling convention */
4519 if (TARGET_SH1
&& ! TARGET_SH3E
&& ! TARGET_SH5
&& ! TARGET_HITACHI
)
4521 /* Push arg regs as if they'd been provided by caller in stack. */
4522 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
4524 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
4525 if (i
>= (NPARM_REGS(SImode
)
4526 - current_function_args_info
.arg_count
[(int) SH_ARG_INT
]
4535 /* If we're supposed to switch stacks at function entry, do so now. */
4537 emit_insn (gen_sp_switch_1 ());
4539 calc_live_regs (&d
, live_regs_mask
);
4540 /* ??? Maybe we could save some switching if we can move a mode switch
4541 that already happens to be at the function start into the prologue. */
4542 if (target_flags
!= save_flags
)
4543 emit_insn (gen_toggle_sz ());
4550 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
4551 int offset_in_r0
= -1;
4554 if (d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
4555 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
4556 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
4558 offset
= d
+ d_rounding
;
4559 output_stack_adjust (-offset
, stack_pointer_rtx
, 1);
4561 /* We loop twice: first, we save 8-byte aligned registers in the
4562 higher addresses, that are known to be aligned. Then, we
4563 proceed to saving 32-bit registers that don't need 8-byte
4565 for (align
= 1; align
>= 0; align
--)
4566 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
4567 if (live_regs_mask
[i
/32] & (1 << (i
% 32)))
4569 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
4571 rtx reg_rtx
, mem_rtx
, pre_dec
= NULL_RTX
;
4573 if (mode
== SFmode
&& (i
% 2) == 1
4574 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
4575 && (live_regs_mask
[(i
^ 1) / 32] & (1 << ((i
^ 1) % 32))))
4582 /* If we're doing the aligned pass and this is not aligned,
4583 or we're doing the unaligned pass and this is aligned,
4585 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
4589 offset
-= GET_MODE_SIZE (mode
);
4591 reg_rtx
= gen_rtx_REG (mode
, reg
);
4593 mem_rtx
= gen_rtx_MEM (mode
,
4594 gen_rtx_PLUS (Pmode
,
4598 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_pre_dec
);
4604 if (HAVE_PRE_DECREMENT
4605 && (offset_in_r0
- offset
== GET_MODE_SIZE (mode
)
4606 || mem_rtx
== NULL_RTX
4607 || i
== PR_REG
|| SPECIAL_REGISTER_P (i
)))
4609 pre_dec
= gen_rtx_MEM (mode
,
4610 gen_rtx_PRE_DEC (Pmode
, r0
));
4612 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (pre_dec
, 0),
4621 offset
+= GET_MODE_SIZE (mode
);
4625 if (mem_rtx
!= NULL_RTX
)
4628 if (offset_in_r0
== -1)
4630 emit_move_insn (r0
, GEN_INT (offset
));
4631 offset_in_r0
= offset
;
4633 else if (offset
!= offset_in_r0
)
4638 GEN_INT (offset
- offset_in_r0
)));
4639 offset_in_r0
+= offset
- offset_in_r0
;
4642 if (pre_dec
!= NULL_RTX
)
4648 (Pmode
, r0
, stack_pointer_rtx
));
4652 offset
-= GET_MODE_SIZE (mode
);
4653 offset_in_r0
-= GET_MODE_SIZE (mode
);
4658 mem_rtx
= gen_rtx_MEM (mode
, r0
);
4660 mem_rtx
= gen_rtx_MEM (mode
,
4661 gen_rtx_PLUS (Pmode
,
4665 /* We must not use an r0-based address for target-branch
4666 registers or for special registers without pre-dec
4667 memory addresses, since we store their values in r0
4669 if (TARGET_REGISTER_P (i
)
4670 || ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4671 && mem_rtx
!= pre_dec
))
4675 if (TARGET_REGISTER_P (i
)
4676 || ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4677 && mem_rtx
!= pre_dec
))
4679 rtx r0mode
= gen_rtx_REG (GET_MODE (reg_rtx
), R0_REG
);
4681 emit_move_insn (r0mode
, reg_rtx
);
4689 emit_move_insn (mem_rtx
, reg_rtx
);
4692 if (offset
!= d_rounding
)
4696 push_regs (live_regs_mask
);
4698 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
4700 rtx insn
= get_last_insn ();
4701 rtx last
= emit_insn (gen_GOTaddr2picreg ());
4703 /* Mark these insns as possibly dead. Sometimes, flow2 may
4704 delete all uses of the PIC register. In this case, let it
4705 delete the initialization too. */
4708 insn
= NEXT_INSN (insn
);
4710 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4714 while (insn
!= last
);
4717 if (SHMEDIA_REGS_STACK_ADJUST ())
4719 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
4720 gen_rtx_SYMBOL_REF (Pmode
,
4722 ? "__GCC_push_shmedia_regs"
4723 : "__GCC_push_shmedia_regs_nofpu"));
4724 /* This must NOT go through the PLT, otherwise mach and macl
4725 may be clobbered. */
4726 emit_insn (gen_shmedia_save_restore_regs_compact
4727 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
4730 if (target_flags
!= save_flags
)
4732 rtx insn
= emit_insn (gen_toggle_sz ());
4734 /* If we're lucky, a mode switch in the function body will
4735 overwrite fpscr, turning this insn dead. Tell flow this
4736 insn is ok to delete. */
4737 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4742 target_flags
= save_flags
;
4744 output_stack_adjust (-rounded_frame_size (d
) + d_rounding
,
4745 stack_pointer_rtx
, TARGET_SH5
? 0 : 1);
4747 if (frame_pointer_needed
)
4748 emit_insn (GEN_MOV (frame_pointer_rtx
, stack_pointer_rtx
));
4750 if (TARGET_SHCOMPACT
4751 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
4753 /* This must NOT go through the PLT, otherwise mach and macl
4754 may be clobbered. */
4755 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
4756 gen_rtx_SYMBOL_REF (Pmode
,
4757 "__GCC_shcompact_incoming_args"));
4758 emit_insn (gen_shcompact_incoming_args ());
4763 sh_expand_epilogue ()
4765 HOST_WIDE_INT live_regs_mask
[(FIRST_PSEUDO_REGISTER
+ 31) / 32];
4769 int save_flags
= target_flags
;
4772 calc_live_regs (&d
, live_regs_mask
);
4774 if (TARGET_SH5
&& d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
4775 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
4776 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
4778 frame_size
= rounded_frame_size (d
) - d_rounding
;
4780 if (frame_pointer_needed
)
4782 output_stack_adjust (frame_size
, frame_pointer_rtx
, 7);
4784 /* We must avoid moving the stack pointer adjustment past code
4785 which reads from the local frame, else an interrupt could
4786 occur after the SP adjustment and clobber data in the local
4788 emit_insn (gen_blockage ());
4789 emit_insn (GEN_MOV (stack_pointer_rtx
, frame_pointer_rtx
));
4791 else if (frame_size
)
4793 /* We must avoid moving the stack pointer adjustment past code
4794 which reads from the local frame, else an interrupt could
4795 occur after the SP adjustment and clobber data in the local
4797 emit_insn (gen_blockage ());
4798 output_stack_adjust (frame_size
, stack_pointer_rtx
, 7);
4801 if (SHMEDIA_REGS_STACK_ADJUST ())
4803 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
4804 gen_rtx_SYMBOL_REF (Pmode
,
4806 ? "__GCC_pop_shmedia_regs"
4807 : "__GCC_pop_shmedia_regs_nofpu"));
4808 /* This must NOT go through the PLT, otherwise mach and macl
4809 may be clobbered. */
4810 emit_insn (gen_shmedia_save_restore_regs_compact
4811 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
4814 /* Pop all the registers. */
4816 if (target_flags
!= save_flags
)
4817 emit_insn (gen_toggle_sz ());
4820 int offset
= d_rounding
;
4821 int offset_in_r0
= -1;
4824 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
4826 /* We loop twice: first, we save 8-byte aligned registers in the
4827 higher addresses, that are known to be aligned. Then, we
4828 proceed to saving 32-bit registers that don't need 8-byte
4830 for (align
= 0; align
<= 1; align
++)
4831 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4832 if (live_regs_mask
[i
/32] & (1 << (i
% 32)))
4834 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
4836 rtx reg_rtx
, mem_rtx
, post_inc
= NULL_RTX
, insn
;
4838 if (mode
== SFmode
&& (i
% 2) == 0
4839 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
4840 && (live_regs_mask
[(i
^ 1) / 32] & (1 << ((i
^ 1) % 32))))
4846 /* If we're doing the aligned pass and this is not aligned,
4847 or we're doing the unaligned pass and this is aligned,
4849 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
4853 reg_rtx
= gen_rtx_REG (mode
, reg
);
4855 mem_rtx
= gen_rtx_MEM (mode
,
4856 gen_rtx_PLUS (Pmode
,
4860 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_post_inc
);
4866 if (HAVE_POST_INCREMENT
4867 && (offset
== offset_in_r0
4868 || (offset
+ GET_MODE_SIZE (mode
) != d
+ d_rounding
4869 && mem_rtx
== NULL_RTX
)
4870 || i
== PR_REG
|| SPECIAL_REGISTER_P (i
)))
4872 post_inc
= gen_rtx_MEM (mode
,
4873 gen_rtx_POST_INC (Pmode
, r0
));
4875 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (post_inc
, 0),
4878 post_inc
= NULL_RTX
;
4887 if (mem_rtx
!= NULL_RTX
)
4890 if (offset_in_r0
== -1)
4892 emit_move_insn (r0
, GEN_INT (offset
));
4893 offset_in_r0
= offset
;
4895 else if (offset
!= offset_in_r0
)
4900 GEN_INT (offset
- offset_in_r0
)));
4901 offset_in_r0
+= offset
- offset_in_r0
;
4904 if (post_inc
!= NULL_RTX
)
4910 (Pmode
, r0
, stack_pointer_rtx
));
4916 offset_in_r0
+= GET_MODE_SIZE (mode
);
4919 mem_rtx
= gen_rtx_MEM (mode
, r0
);
4921 mem_rtx
= gen_rtx_MEM (mode
,
4922 gen_rtx_PLUS (Pmode
,
4926 if ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4927 && mem_rtx
!= post_inc
)
4931 if ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4932 && mem_rtx
!= post_inc
)
4934 insn
= emit_move_insn (r0
, mem_rtx
);
4937 else if (TARGET_REGISTER_P (i
))
4939 rtx r1
= gen_rtx_REG (mode
, R1_REG
);
4941 insn
= emit_move_insn (r1
, mem_rtx
);
4945 insn
= emit_move_insn (reg_rtx
, mem_rtx
);
4947 offset
+= GET_MODE_SIZE (mode
);
4950 if (offset
!= d
+ d_rounding
)
4957 if (live_regs_mask
[PR_REG
/ 32] & (1 << (PR_REG
% 32)))
4959 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4961 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
4963 if (j
!= PR_REG
&& live_regs_mask
[j
/ 32] & (1 << (j
% 32)))
4967 if (target_flags
!= save_flags
)
4968 emit_insn (gen_toggle_sz ());
4969 target_flags
= save_flags
;
4971 output_stack_adjust (extra_push
+ current_function_pretend_args_size
4973 + current_function_args_info
.stack_regs
* 8,
4974 stack_pointer_rtx
, 7);
4976 /* Switch back to the normal stack if necessary. */
4978 emit_insn (gen_sp_switch_2 ());
4980 /* Tell flow the insn that pops PR isn't dead. */
4981 /* PR_REG will never be live in SHmedia mode, and we don't need to
4982 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
4983 by the return pattern. */
4984 if (live_regs_mask
[PR_REG
/ 32] & (1 << (PR_REG
% 32)))
4985 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, PR_REG
)));
4988 static int sh_need_epilogue_known
= 0;
4993 if (! sh_need_epilogue_known
)
4998 sh_expand_epilogue ();
4999 epilogue
= gen_sequence ();
5001 sh_need_epilogue_known
5002 = (GET_CODE (epilogue
) == SEQUENCE
&& XVECLEN (epilogue
, 0) == 0
5005 return sh_need_epilogue_known
> 0;
5008 /* Clear variables at function end. */
5011 sh_output_function_epilogue (file
, size
)
5012 FILE *file ATTRIBUTE_UNUSED
;
5013 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
5015 trap_exit
= pragma_interrupt
= pragma_trapa
= pragma_nosave_low_regs
= 0;
5016 sh_need_epilogue_known
= 0;
5017 sp_switch
= NULL_RTX
;
5021 sh_builtin_saveregs ()
5023 /* First unnamed integer register. */
5024 int first_intreg
= current_function_args_info
.arg_count
[(int) SH_ARG_INT
];
5025 /* Number of integer registers we need to save. */
5026 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
5027 /* First unnamed SFmode float reg */
5028 int first_floatreg
= current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
5029 /* Number of SFmode float regs to save. */
5030 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
5033 HOST_WIDE_INT alias_set
;
5039 int pushregs
= n_intregs
;
5041 while (pushregs
< NPARM_REGS (SImode
) - 1
5042 && (CALL_COOKIE_INT_REG_GET
5043 (current_function_args_info
.call_cookie
,
5044 NPARM_REGS (SImode
) - pushregs
)
5047 current_function_args_info
.call_cookie
5048 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
5053 if (pushregs
== NPARM_REGS (SImode
))
5054 current_function_args_info
.call_cookie
5055 |= (CALL_COOKIE_INT_REG (0, 1)
5056 | CALL_COOKIE_STACKSEQ (pushregs
- 1));
5058 current_function_args_info
.call_cookie
5059 |= CALL_COOKIE_STACKSEQ (pushregs
);
5061 current_function_pretend_args_size
+= 8 * n_intregs
;
5063 if (TARGET_SHCOMPACT
)
5067 if (! TARGET_SH3E
&& ! TARGET_SH4
&& ! TARGET_SH5
)
5069 error ("__builtin_saveregs not supported by this subtarget");
5076 /* Allocate block of memory for the regs. */
5077 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5078 Or can assign_stack_local accept a 0 SIZE argument? */
5079 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
5082 regbuf
= gen_rtx_MEM (BLKmode
,
5083 gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
));
5085 regbuf
= assign_stack_local (BLKmode
, bufsize
, 0);
5086 alias_set
= get_varargs_alias_set ();
5087 set_mem_alias_set (regbuf
, alias_set
);
5090 This is optimized to only save the regs that are necessary. Explicitly
5091 named args need not be saved. */
5093 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
5094 adjust_address (regbuf
, BLKmode
,
5095 n_floatregs
* UNITS_PER_WORD
),
5096 n_intregs
, n_intregs
* UNITS_PER_WORD
);
5099 /* Return the address of the regbuf. */
5100 return XEXP (regbuf
, 0);
5103 This is optimized to only save the regs that are necessary. Explicitly
5104 named args need not be saved.
5105 We explicitly build a pointer to the buffer because it halves the insn
5106 count when not optimizing (otherwise the pointer is built for each reg
5108 We emit the moves in reverse order so that we can use predecrement. */
5110 fpregs
= gen_reg_rtx (Pmode
);
5111 emit_move_insn (fpregs
, XEXP (regbuf
, 0));
5112 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5113 GEN_INT (n_floatregs
* UNITS_PER_WORD
)));
5117 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
5119 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5120 GEN_INT (-2 * UNITS_PER_WORD
)));
5121 mem
= gen_rtx_MEM (DFmode
, fpregs
);
5122 set_mem_alias_set (mem
, alias_set
);
5123 emit_move_insn (mem
,
5124 gen_rtx (REG
, DFmode
, BASE_ARG_REG (DFmode
) + regno
));
5126 regno
= first_floatreg
;
5129 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5130 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5131 set_mem_alias_set (mem
, alias_set
);
5132 emit_move_insn (mem
,
5133 gen_rtx (REG
, SFmode
, BASE_ARG_REG (SFmode
) + regno
5134 - (TARGET_LITTLE_ENDIAN
!= 0)));
5138 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
5142 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5143 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5144 set_mem_alias_set (mem
, alias_set
);
5145 emit_move_insn (mem
,
5146 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
5149 /* Return the address of the regbuf. */
5150 return XEXP (regbuf
, 0);
5153 /* Define the `__builtin_va_list' type for the ABI. */
5158 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5161 if (TARGET_SH5
|| (! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
5162 return ptr_type_node
;
5164 record
= make_node (RECORD_TYPE
);
5166 f_next_o
= build_decl (FIELD_DECL
, get_identifier ("__va_next_o"),
5168 f_next_o_limit
= build_decl (FIELD_DECL
,
5169 get_identifier ("__va_next_o_limit"),
5171 f_next_fp
= build_decl (FIELD_DECL
, get_identifier ("__va_next_fp"),
5173 f_next_fp_limit
= build_decl (FIELD_DECL
,
5174 get_identifier ("__va_next_fp_limit"),
5176 f_next_stack
= build_decl (FIELD_DECL
, get_identifier ("__va_next_stack"),
5179 DECL_FIELD_CONTEXT (f_next_o
) = record
;
5180 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
5181 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
5182 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
5183 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
5185 TYPE_FIELDS (record
) = f_next_o
;
5186 TREE_CHAIN (f_next_o
) = f_next_o_limit
;
5187 TREE_CHAIN (f_next_o_limit
) = f_next_fp
;
5188 TREE_CHAIN (f_next_fp
) = f_next_fp_limit
;
5189 TREE_CHAIN (f_next_fp_limit
) = f_next_stack
;
5191 layout_type (record
);
5196 /* Implement `va_start' for varargs and stdarg. */
5199 sh_va_start (stdarg_p
, valist
, nextarg
)
5204 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5205 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
5211 expand_builtin_saveregs ();
5212 /* When the varargs dummy argument is ``passed'' on a register,
5213 we don't want std_expand_builtin_va_start() to apply any
5214 correction for it, so set stdarg_p so as to pretend there's
5215 no such dummy argument. */
5216 if (current_function_args_info
.arg_count
[(int) SH_ARG_INT
]
5217 < NPARM_REGS (SImode
))
5219 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
5223 if ((! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
5225 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
5229 f_next_o
= TYPE_FIELDS (va_list_type_node
);
5230 f_next_o_limit
= TREE_CHAIN (f_next_o
);
5231 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
5232 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
5233 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
5235 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
5236 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
5237 valist
, f_next_o_limit
);
5238 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
);
5239 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
5240 valist
, f_next_fp_limit
);
5241 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
5242 valist
, f_next_stack
);
5244 /* Call __builtin_saveregs. */
5245 u
= make_tree (ptr_type_node
, expand_builtin_saveregs ());
5246 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
5247 TREE_SIDE_EFFECTS (t
) = 1;
5248 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5250 nfp
= current_function_args_info
.arg_count
[SH_ARG_FLOAT
];
5255 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5256 build_int_2 (UNITS_PER_WORD
* nfp
, 0)));
5257 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
5258 TREE_SIDE_EFFECTS (t
) = 1;
5259 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5261 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
5262 TREE_SIDE_EFFECTS (t
) = 1;
5263 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5265 nint
= current_function_args_info
.arg_count
[SH_ARG_INT
];
5270 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5271 build_int_2 (UNITS_PER_WORD
* nint
, 0)));
5272 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
5273 TREE_SIDE_EFFECTS (t
) = 1;
5274 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5276 u
= make_tree (ptr_type_node
, nextarg
);
5277 if (! stdarg_p
&& (nint
== 0 || nfp
== 0))
5279 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5280 build_int_2 (-UNITS_PER_WORD
, -1)));
5282 t
= build (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
5283 TREE_SIDE_EFFECTS (t
) = 1;
5284 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5287 /* Implement `va_arg'. */
5290 sh_va_arg (valist
, type
)
5293 HOST_WIDE_INT size
, rsize
;
5294 tree tmp
, pptr_type_node
;
5297 size
= int_size_in_bytes (type
);
5298 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5299 pptr_type_node
= build_pointer_type (ptr_type_node
);
5301 if (! TARGET_SH5
&& (TARGET_SH3E
|| TARGET_SH4
) && ! TARGET_HITACHI
)
5303 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5304 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
5306 rtx lab_false
, lab_over
;
5308 f_next_o
= TYPE_FIELDS (va_list_type_node
);
5309 f_next_o_limit
= TREE_CHAIN (f_next_o
);
5310 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
5311 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
5312 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
5314 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
5315 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
5316 valist
, f_next_o_limit
);
5317 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
5319 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
5320 valist
, f_next_fp_limit
);
5321 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
5322 valist
, f_next_stack
);
5326 pass_as_float
= ((TREE_CODE (type
) == REAL_TYPE
&& size
<= 8)
5327 || (TREE_CODE (type
) == COMPLEX_TYPE
5328 && TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
5333 pass_as_float
= (TREE_CODE (type
) == REAL_TYPE
&& size
== 4);
5336 addr_rtx
= gen_reg_rtx (Pmode
);
5337 lab_false
= gen_label_rtx ();
5338 lab_over
= gen_label_rtx ();
5342 emit_cmp_and_jump_insns (expand_expr (next_fp
, NULL_RTX
, Pmode
,
5344 expand_expr (next_fp_limit
, NULL_RTX
,
5345 Pmode
, EXPAND_NORMAL
),
5346 GE
, const1_rtx
, Pmode
, 1, lab_false
);
5348 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
5350 tmp
= build (BIT_AND_EXPR
, ptr_type_node
, next_fp
,
5351 build_int_2 (UNITS_PER_WORD
, 0));
5352 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_fp
, tmp
);
5353 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, tmp
);
5354 TREE_SIDE_EFFECTS (tmp
) = 1;
5355 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5358 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_fp
);
5359 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5361 emit_move_insn (addr_rtx
, r
);
5363 emit_jump_insn (gen_jump (lab_over
));
5365 emit_label (lab_false
);
5367 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
5368 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5370 emit_move_insn (addr_rtx
, r
);
5374 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_o
,
5375 build_int_2 (rsize
, 0));
5377 emit_cmp_and_jump_insns (expand_expr (tmp
, NULL_RTX
, Pmode
,
5379 expand_expr (next_o_limit
, NULL_RTX
,
5380 Pmode
, EXPAND_NORMAL
),
5381 GT
, const1_rtx
, Pmode
, 1, lab_false
);
5383 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_o
);
5384 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5386 emit_move_insn (addr_rtx
, r
);
5388 emit_jump_insn (gen_jump (lab_over
));
5390 emit_label (lab_false
);
5392 if (size
> 4 && ! TARGET_SH4
)
5394 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, next_o_limit
);
5395 TREE_SIDE_EFFECTS (tmp
) = 1;
5396 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5399 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
5400 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5402 emit_move_insn (addr_rtx
, r
);
5405 emit_label (lab_over
);
5407 tmp
= make_tree (pptr_type_node
, addr_rtx
);
5408 valist
= build1 (INDIRECT_REF
, ptr_type_node
, tmp
);
5411 /* ??? In va-sh.h, there had been code to make values larger than
5412 size 8 indirect. This does not match the FUNCTION_ARG macros. */
5414 return std_expand_builtin_va_arg (valist
, type
);
5417 /* Define the offset between two registers, one to be eliminated, and
5418 the other its replacement, at the start of a routine. */
5421 initial_elimination_offset (from
, to
)
5426 int regs_saved_rounding
= 0;
5427 int total_saved_regs_space
;
5428 int total_auto_space
;
5429 int save_flags
= target_flags
;
5432 HOST_WIDE_INT live_regs_mask
[(FIRST_PSEUDO_REGISTER
+ 31) / 32];
5433 calc_live_regs (®s_saved
, live_regs_mask
);
5434 regs_saved
+= SHMEDIA_REGS_STACK_ADJUST ();
5435 if (TARGET_SH5
&& regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
5436 regs_saved_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
5437 - regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
5439 total_auto_space
= rounded_frame_size (regs_saved
) - regs_saved_rounding
;
5440 copy_flags
= target_flags
;
5441 target_flags
= save_flags
;
5443 total_saved_regs_space
= regs_saved
+ regs_saved_rounding
;
5445 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
5446 return total_saved_regs_space
+ total_auto_space
5447 + current_function_args_info
.byref_regs
* 8;
5449 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5450 return total_saved_regs_space
+ total_auto_space
5451 + current_function_args_info
.byref_regs
* 8;
5453 /* Initial gap between fp and sp is 0. */
5454 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5457 if (from
== RETURN_ADDRESS_POINTER_REGNUM
5458 && (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
))
5461 int i
, n
= total_saved_regs_space
;
5463 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
5465 n
+= total_auto_space
;
5467 /* If it wasn't saved, there's not much we can do. */
5468 if ((live_regs_mask
[pr_reg
/ 32] & (1 << (pr_reg
% 32))) == 0)
5471 target_flags
= copy_flags
;
5473 /* We loop twice: first, check 8-byte aligned registers,
5474 that are stored in the higher addresses, that are known
5475 to be aligned. Then, check 32-bit registers that don't
5476 need 8-byte alignment. */
5477 for (align
= 1; align
>= 0; align
--)
5478 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
5479 if (live_regs_mask
[i
/32] & (1 << (i
% 32)))
5481 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
5483 if (mode
== SFmode
&& (i
% 2) == 1
5484 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
5485 && (live_regs_mask
[(i
^ 1) / 32]
5486 & (1 << ((i
^ 1) % 32))))
5492 /* If we're doing the aligned pass and this is not aligned,
5493 or we're doing the unaligned pass and this is aligned,
5495 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
5499 n
-= GET_MODE_SIZE (mode
);
5503 target_flags
= save_flags
;
5511 return total_auto_space
;
5516 /* Handle machine specific pragmas to be semi-compatible with Hitachi
5520 sh_pr_interrupt (pfile
)
5521 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
5523 pragma_interrupt
= 1;
5528 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
5530 pragma_interrupt
= pragma_trapa
= 1;
5534 sh_pr_nosave_low_regs (pfile
)
5535 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
5537 pragma_nosave_low_regs
= 1;
5540 /* Generate 'handle_interrupt' attribute for decls */
5543 sh_insert_attributes (node
, attributes
)
5547 if (! pragma_interrupt
5548 || TREE_CODE (node
) != FUNCTION_DECL
)
5551 /* We are only interested in fields. */
5552 if (TREE_CODE_CLASS (TREE_CODE (node
)) != 'd')
5555 /* Add a 'handle_interrupt' attribute. */
5556 * attributes
= tree_cons (get_identifier ("interrupt_handler"), NULL
, * attributes
);
5561 /* Supported attributes:
5563 interrupt_handler -- specifies this function is an interrupt handler.
5565 sp_switch -- specifies an alternate stack for an interrupt handler
5568 trap_exit -- use a trapa to exit an interrupt function instead of
5569 an rte instruction. */
5571 const struct attribute_spec sh_attribute_table
[] =
5573 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5574 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute
},
5575 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute
},
5576 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute
},
5577 { NULL
, 0, 0, false, false, false, NULL
}
5580 /* Handle an "interrupt_handler" attribute; arguments as in
5581 struct attribute_spec.handler. */
5583 sh_handle_interrupt_handler_attribute (node
, name
, args
, flags
, no_add_attrs
)
5586 tree args ATTRIBUTE_UNUSED
;
5587 int flags ATTRIBUTE_UNUSED
;
5590 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5592 warning ("`%s' attribute only applies to functions",
5593 IDENTIFIER_POINTER (name
));
5594 *no_add_attrs
= true;
5600 /* Handle an "sp_switch" attribute; arguments as in
5601 struct attribute_spec.handler. */
5603 sh_handle_sp_switch_attribute (node
, name
, args
, flags
, no_add_attrs
)
5607 int flags ATTRIBUTE_UNUSED
;
5610 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5612 warning ("`%s' attribute only applies to functions",
5613 IDENTIFIER_POINTER (name
));
5614 *no_add_attrs
= true;
5616 else if (!pragma_interrupt
)
5618 /* The sp_switch attribute only has meaning for interrupt functions. */
5619 warning ("`%s' attribute only applies to interrupt functions",
5620 IDENTIFIER_POINTER (name
));
5621 *no_add_attrs
= true;
5623 else if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
5625 /* The argument must be a constant string. */
5626 warning ("`%s' attribute argument not a string constant",
5627 IDENTIFIER_POINTER (name
));
5628 *no_add_attrs
= true;
5632 sp_switch
= gen_rtx_SYMBOL_REF (VOIDmode
,
5633 TREE_STRING_POINTER (TREE_VALUE (args
)));
5639 /* Handle an "trap_exit" attribute; arguments as in
5640 struct attribute_spec.handler. */
5642 sh_handle_trap_exit_attribute (node
, name
, args
, flags
, no_add_attrs
)
5646 int flags ATTRIBUTE_UNUSED
;
5649 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5651 warning ("`%s' attribute only applies to functions",
5652 IDENTIFIER_POINTER (name
));
5653 *no_add_attrs
= true;
5655 else if (!pragma_interrupt
)
5657 /* The trap_exit attribute only has meaning for interrupt functions. */
5658 warning ("`%s' attribute only applies to interrupt functions",
5659 IDENTIFIER_POINTER (name
));
5660 *no_add_attrs
= true;
5662 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
5664 /* The argument must be a constant integer. */
5665 warning ("`%s' attribute argument not an integer constant",
5666 IDENTIFIER_POINTER (name
));
5667 *no_add_attrs
= true;
5671 trap_exit
= TREE_INT_CST_LOW (TREE_VALUE (args
));
5678 /* Predicates used by the templates. */
5680 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
5681 Used only in general_movsrc_operand. */
5684 system_reg_operand (op
, mode
)
5686 enum machine_mode mode ATTRIBUTE_UNUSED
;
5698 /* Returns 1 if OP can be source of a simple move operation.
5699 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
5700 invalid as are subregs of system registers. */
5703 general_movsrc_operand (op
, mode
)
5705 enum machine_mode mode
;
5707 if (GET_CODE (op
) == MEM
)
5709 rtx inside
= XEXP (op
, 0);
5710 if (GET_CODE (inside
) == CONST
)
5711 inside
= XEXP (inside
, 0);
5713 if (GET_CODE (inside
) == LABEL_REF
)
5716 if (GET_CODE (inside
) == PLUS
5717 && GET_CODE (XEXP (inside
, 0)) == LABEL_REF
5718 && GET_CODE (XEXP (inside
, 1)) == CONST_INT
)
5721 /* Only post inc allowed. */
5722 if (GET_CODE (inside
) == PRE_DEC
)
5726 if ((mode
== QImode
|| mode
== HImode
)
5727 && (GET_CODE (op
) == SUBREG
5728 && GET_CODE (XEXP (op
, 0)) == REG
5729 && system_reg_operand (XEXP (op
, 0), mode
)))
5732 return general_operand (op
, mode
);
5735 /* Returns 1 if OP can be a destination of a move.
5736 Same as general_operand, but no preinc allowed. */
5739 general_movdst_operand (op
, mode
)
5741 enum machine_mode mode
;
5743 /* Only pre dec allowed. */
5744 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
5747 return general_operand (op
, mode
);
5750 /* Accept a register, but not a subreg of any kind. This allows us to
5751 avoid pathological cases in reload wrt data movement common in
5752 int->fp conversion. */
5755 reg_no_subreg_operand (op
, mode
)
5757 enum machine_mode mode
;
5759 if (GET_CODE (op
) == SUBREG
)
5761 return register_operand (op
, mode
);
5764 /* Returns 1 if OP is a normal arithmetic register. */
5767 arith_reg_operand (op
, mode
)
5769 enum machine_mode mode
;
5771 if (register_operand (op
, mode
))
5775 if (GET_CODE (op
) == REG
)
5777 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
5778 regno
= REGNO (SUBREG_REG (op
));
5782 return (regno
!= T_REG
&& regno
!= PR_REG
5783 && ! TARGET_REGISTER_P (regno
)
5784 && (regno
!= FPUL_REG
|| TARGET_SH4
)
5785 && regno
!= MACH_REG
&& regno
!= MACL_REG
);
5791 fp_arith_reg_operand (op
, mode
)
5793 enum machine_mode mode
;
5795 if (register_operand (op
, mode
))
5799 if (GET_CODE (op
) == REG
)
5801 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
5802 regno
= REGNO (SUBREG_REG (op
));
5806 return (regno
>= FIRST_PSEUDO_REGISTER
5807 || FP_REGISTER_P (regno
));
5812 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
5815 arith_operand (op
, mode
)
5817 enum machine_mode mode
;
5819 if (arith_reg_operand (op
, mode
))
5824 /* FIXME: We should be checking whether the CONST_INT fits in a
5825 CONST_OK_FOR_J here, but this causes reload_cse to crash when
5826 attempting to transform a sequence of two 64-bit sets of the
5827 same register from literal constants into a set and an add,
5828 when the difference is too wide for an add. */
5829 if (GET_CODE (op
) == CONST_INT
5830 || EXTRA_CONSTRAINT_S (op
))
5835 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
5841 /* Returns 1 if OP is a valid source operand for a compare insn. */
5844 arith_reg_or_0_operand (op
, mode
)
5846 enum machine_mode mode
;
5848 if (arith_reg_operand (op
, mode
))
5851 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_N (INTVAL (op
)))
5857 /* Return 1 if OP is a valid source operand for an SHmedia operation
5858 that takes either a register or a 6-bit immediate. */
5861 shmedia_6bit_operand (op
, mode
)
5863 enum machine_mode mode
;
5865 return (arith_reg_operand (op
, mode
)
5866 || (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_O (INTVAL (op
))));
5869 /* Returns 1 if OP is a valid source operand for a logical operation. */
5872 logical_operand (op
, mode
)
5874 enum machine_mode mode
;
5876 if (arith_reg_operand (op
, mode
))
5881 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_P (INTVAL (op
)))
5886 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
5892 /* Nonzero if OP is a floating point value with value 0.0. */
5895 fp_zero_operand (op
)
5900 if (GET_MODE (op
) != SFmode
)
5903 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
5904 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
5907 /* Nonzero if OP is a floating point value with value 1.0. */
5915 if (GET_MODE (op
) != SFmode
)
5918 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
5919 return REAL_VALUES_EQUAL (r
, dconst1
);
5922 /* For -m4 and -m4-single-only, mode switching is used. If we are
5923 compiling without -mfmovd, movsf_ie isn't taken into account for
5924 mode switching. We could check in machine_dependent_reorg for
5925 cases where we know we are in single precision mode, but there is
5926 interface to find that out during reload, so we must avoid
5927 choosing an fldi alternative during reload and thus failing to
5928 allocate a scratch register for the constant loading. */
5932 return ! TARGET_SH4
|| TARGET_FMOVD
|| reload_completed
;
5936 tertiary_reload_operand (op
, mode
)
5938 enum machine_mode mode ATTRIBUTE_UNUSED
;
5940 enum rtx_code code
= GET_CODE (op
);
5941 return code
== MEM
|| (TARGET_SH4
&& code
== CONST_DOUBLE
);
5945 fpscr_operand (op
, mode
)
5947 enum machine_mode mode ATTRIBUTE_UNUSED
;
5949 return (GET_CODE (op
) == REG
&& REGNO (op
) == FPSCR_REG
5950 && GET_MODE (op
) == PSImode
);
5954 fpul_operand (op
, mode
)
5956 enum machine_mode mode
;
5959 return fp_arith_reg_operand (op
, mode
);
5961 return (GET_CODE (op
) == REG
5962 && (REGNO (op
) == FPUL_REG
|| REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
5963 && GET_MODE (op
) == mode
);
5967 symbol_ref_operand (op
, mode
)
5969 enum machine_mode mode ATTRIBUTE_UNUSED
;
5971 return (GET_CODE (op
) == SYMBOL_REF
);
5975 commutative_float_operator (op
, mode
)
5977 enum machine_mode mode
;
5979 if (GET_MODE (op
) != mode
)
5981 switch (GET_CODE (op
))
5993 noncommutative_float_operator (op
, mode
)
5995 enum machine_mode mode
;
5997 if (GET_MODE (op
) != mode
)
5999 switch (GET_CODE (op
))
6011 binary_float_operator (op
, mode
)
6013 enum machine_mode mode
;
6015 if (GET_MODE (op
) != mode
)
6017 switch (GET_CODE (op
))
6030 /* Accept pseudos and branch target registers. */
6032 target_reg_operand (op
, mode
)
6034 enum machine_mode mode
;
6037 || GET_MODE (op
) != DImode
)
6040 if (GET_CODE (op
) == SUBREG
)
6043 if (GET_CODE (op
) != REG
)
6046 /* We must protect ourselves from matching pseudos that are virtual
6047 register, because they will eventually be replaced with hardware
6048 registers that aren't branch-target registers. */
6049 if (REGNO (op
) > LAST_VIRTUAL_REGISTER
6050 || TARGET_REGISTER_P (REGNO (op
)))
6056 /* Same as target_reg_operand, except that label_refs and symbol_refs
6057 are accepted before reload. */
6059 target_operand (op
, mode
)
6061 enum machine_mode mode
;
6066 if ((GET_MODE (op
) == DImode
|| GET_MODE (op
) == VOIDmode
)
6067 && EXTRA_CONSTRAINT_T (op
))
6068 return ! reload_completed
;
6070 return target_reg_operand (op
, mode
);
6074 /* Return the destination address of a branch. */
6077 branch_dest (branch
)
6080 rtx dest
= SET_SRC (PATTERN (branch
));
6083 if (GET_CODE (dest
) == IF_THEN_ELSE
)
6084 dest
= XEXP (dest
, 1);
6085 dest
= XEXP (dest
, 0);
6086 dest_uid
= INSN_UID (dest
);
6087 return INSN_ADDRESSES (dest_uid
);
6090 /* Return non-zero if REG is not used after INSN.
6091 We assume REG is a reload reg, and therefore does
6092 not live past labels. It may live past calls or jumps though. */
6094 reg_unused_after (reg
, insn
)
6101 /* If the reg is set by this instruction, then it is safe for our
6102 case. Disregard the case where this is a store to memory, since
6103 we are checking a register used in the store address. */
6104 set
= single_set (insn
);
6105 if (set
&& GET_CODE (SET_DEST (set
)) != MEM
6106 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6109 while ((insn
= NEXT_INSN (insn
)))
6111 code
= GET_CODE (insn
);
6114 /* If this is a label that existed before reload, then the register
6115 if dead here. However, if this is a label added by reorg, then
6116 the register may still be live here. We can't tell the difference,
6117 so we just ignore labels completely. */
6118 if (code
== CODE_LABEL
)
6123 if (code
== JUMP_INSN
)
6126 /* If this is a sequence, we must handle them all at once.
6127 We could have for instance a call that sets the target register,
6128 and an insn in a delay slot that uses the register. In this case,
6129 we must return 0. */
6130 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
6135 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
6137 rtx this_insn
= XVECEXP (PATTERN (insn
), 0, i
);
6138 rtx set
= single_set (this_insn
);
6140 if (GET_CODE (this_insn
) == CALL_INSN
)
6142 else if (GET_CODE (this_insn
) == JUMP_INSN
)
6144 if (INSN_ANNULLED_BRANCH_P (this_insn
))
6149 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
6151 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6153 if (GET_CODE (SET_DEST (set
)) != MEM
)
6159 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
6164 else if (code
== JUMP_INSN
)
6167 else if (GET_RTX_CLASS (code
) == 'i')
6169 rtx set
= single_set (insn
);
6171 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
6173 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6174 return GET_CODE (SET_DEST (set
)) != MEM
;
6175 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
6179 if (code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
6190 static rtx fpscr_rtx
;
6194 fpscr_rtx
= gen_rtx (REG
, PSImode
, FPSCR_REG
);
6195 REG_USERVAR_P (fpscr_rtx
) = 1;
6196 ggc_add_rtx_root (&fpscr_rtx
, 1);
6197 mark_user_reg (fpscr_rtx
);
6199 if (! reload_completed
|| mdep_reorg_phase
!= SH_AFTER_MDEP_REORG
)
6200 mark_user_reg (fpscr_rtx
);
6219 expand_sf_unop (fun
, operands
)
6220 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
6223 emit_sf_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
6227 expand_sf_binop (fun
, operands
)
6228 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
6231 emit_sf_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
6236 expand_df_unop (fun
, operands
)
6237 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
6240 emit_df_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
6244 expand_df_binop (fun
, operands
)
6245 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
6248 emit_df_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
6252 /* ??? gcc does flow analysis strictly after common subexpression
6253 elimination. As a result, common subespression elimination fails
6254 when there are some intervening statements setting the same register.
6255 If we did nothing about this, this would hurt the precision switching
6256 for SH4 badly. There is some cse after reload, but it is unable to
6257 undo the extra register pressure from the unused instructions, and
6258 it cannot remove auto-increment loads.
6260 A C code example that shows this flow/cse weakness for (at least) SH
6261 and sparc (as of gcc ss-970706) is this:
6275 So we add another pass before common subexpression elimination, to
6276 remove assignments that are dead due to a following assignment in the
6277 same basic block. */
6280 mark_use (x
, reg_set_block
)
6281 rtx x
, *reg_set_block
;
6287 code
= GET_CODE (x
);
6292 int regno
= REGNO (x
);
6293 int nregs
= (regno
< FIRST_PSEUDO_REGISTER
6294 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
))
6298 reg_set_block
[regno
+ nregs
- 1] = 0;
6305 rtx dest
= SET_DEST (x
);
6307 if (GET_CODE (dest
) == SUBREG
)
6308 dest
= SUBREG_REG (dest
);
6309 if (GET_CODE (dest
) != REG
)
6310 mark_use (dest
, reg_set_block
);
6311 mark_use (SET_SRC (x
), reg_set_block
);
6318 const char *fmt
= GET_RTX_FORMAT (code
);
6320 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6323 mark_use (XEXP (x
, i
), reg_set_block
);
6324 else if (fmt
[i
] == 'E')
6325 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6326 mark_use (XVECEXP (x
, i
, j
), reg_set_block
);
6333 static rtx get_free_reg
PARAMS ((HARD_REG_SET
));
6335 /* This function returns a register to use to load the address to load
6336 the fpscr from. Currently it always returns r1 or r7, but when we are
6337 able to use pseudo registers after combine, or have a better mechanism
6338 for choosing a register, it should be done here. */
6339 /* REGS_LIVE is the liveness information for the point for which we
6340 need this allocation. In some bare-bones exit blocks, r1 is live at the
6341 start. We can even have all of r0..r3 being live:
6342 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
6343 INSN before which new insns are placed with will clobber the register
6344 we return. If a basic block consists only of setting the return value
6345 register to a pseudo and using that register, the return value is not
6346 live before or after this block, yet we we'll insert our insns right in
6350 get_free_reg (regs_live
)
6351 HARD_REG_SET regs_live
;
6353 if (! TEST_HARD_REG_BIT (regs_live
, 1))
6354 return gen_rtx_REG (Pmode
, 1);
6356 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
6357 there shouldn't be anything but a jump before the function end. */
6358 if (! TEST_HARD_REG_BIT (regs_live
, 7))
6359 return gen_rtx_REG (Pmode
, 7);
6364 /* This function will set the fpscr from memory.
6365 MODE is the mode we are setting it to. */
6367 fpscr_set_from_mem (mode
, regs_live
)
6369 HARD_REG_SET regs_live
;
6371 enum attr_fp_mode fp_mode
= mode
;
6372 rtx addr_reg
= get_free_reg (regs_live
);
6374 if (fp_mode
== (enum attr_fp_mode
) NORMAL_MODE (FP_MODE
))
6375 emit_insn (gen_fpu_switch1 (addr_reg
));
6377 emit_insn (gen_fpu_switch0 (addr_reg
));
6380 /* Is the given character a logical line separator for the assembler? */
6381 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
6382 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
6386 sh_insn_length_adjustment (insn
)
6389 /* Instructions with unfilled delay slots take up an extra two bytes for
6390 the nop in the delay slot. */
6391 if (((GET_CODE (insn
) == INSN
6392 && GET_CODE (PATTERN (insn
)) != USE
6393 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6394 || GET_CODE (insn
) == CALL_INSN
6395 || (GET_CODE (insn
) == JUMP_INSN
6396 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
6397 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
))
6398 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
6399 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
6402 /* sh-dsp parallel processing insn take four bytes instead of two. */
6404 if (GET_CODE (insn
) == INSN
)
6407 rtx body
= PATTERN (insn
);
6408 const char *template;
6410 int maybe_label
= 1;
6412 if (GET_CODE (body
) == ASM_INPUT
)
6413 template = XSTR (body
, 0);
6414 else if (asm_noperands (body
) >= 0)
6416 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
);
6425 while (c
== ' ' || c
== '\t');
6426 /* all sh-dsp parallel-processing insns start with p.
6427 The only non-ppi sh insn starting with p is pref.
6428 The only ppi starting with pr is prnd. */
6429 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", template, 2))
6431 /* The repeat pseudo-insn expands two three insns, a total of
6432 six bytes in size. */
6433 else if ((c
== 'r' || c
== 'R')
6434 && ! strncasecmp ("epeat", template, 5))
6436 while (c
&& c
!= '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
))
6438 /* If this is a label, it is obviously not a ppi insn. */
6439 if (c
== ':' && maybe_label
)
6444 else if (c
== '\'' || c
== '"')
6449 maybe_label
= c
!= ':';
6457 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
6458 isn't protected by a PIC unspec. */
6460 nonpic_symbol_mentioned_p (x
)
6463 register const char *fmt
;
6466 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
6467 || GET_CODE (x
) == PC
)
6470 /* We don't want to look into the possible MEM location of a
6471 CONST_DOUBLE, since we're not going to use it, in general. */
6472 if (GET_CODE (x
) == CONST_DOUBLE
)
6475 if (GET_CODE (x
) == UNSPEC
6476 && (XINT (x
, 1) == UNSPEC_PIC
6477 || XINT (x
, 1) == UNSPEC_GOT
6478 || XINT (x
, 1) == UNSPEC_GOTOFF
6479 || XINT (x
, 1) == UNSPEC_GOTPLT
6480 || XINT (x
, 1) == UNSPEC_PLT
))
6483 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6484 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6490 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6491 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
6494 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
6501 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
6502 @GOTOFF in `reg'. */
6504 legitimize_pic_address (orig
, mode
, reg
)
6506 enum machine_mode mode ATTRIBUTE_UNUSED
;
6509 if (GET_CODE (orig
) == LABEL_REF
6510 || (GET_CODE (orig
) == SYMBOL_REF
6511 && (CONSTANT_POOL_ADDRESS_P (orig
)
6512 /* SYMBOL_REF_FLAG is set on static symbols. */
6513 || SYMBOL_REF_FLAG (orig
))))
6516 reg
= gen_reg_rtx (Pmode
);
6518 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
6521 else if (GET_CODE (orig
) == SYMBOL_REF
)
6524 reg
= gen_reg_rtx (Pmode
);
6526 emit_insn (gen_symGOT2reg (reg
, orig
));
6532 /* Mark the use of a constant in the literal table. If the constant
6533 has multiple labels, make it unique. */
6534 static rtx
mark_constant_pool_use (x
)
6537 rtx insn
, lab
, pattern
;
6542 switch (GET_CODE (x
))
6552 /* Get the first label in the list of labels for the same constant
6553 and delete another labels in the list. */
6555 for (insn
= PREV_INSN (x
); insn
; insn
= PREV_INSN (insn
))
6557 if (GET_CODE (insn
) != CODE_LABEL
6558 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
6563 for (insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
6564 INSN_DELETED_P (insn
) = 1;
6566 /* Mark constants in a window. */
6567 for (insn
= NEXT_INSN (x
); insn
; insn
= NEXT_INSN (insn
))
6569 if (GET_CODE (insn
) != INSN
)
6572 pattern
= PATTERN (insn
);
6573 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
6576 switch (XINT (pattern
, 1))
6578 case UNSPECV_CONST2
:
6579 case UNSPECV_CONST4
:
6580 case UNSPECV_CONST8
:
6581 XVECEXP (pattern
, 0, 1) = const1_rtx
;
6583 case UNSPECV_WINDOW_END
:
6584 if (XVECEXP (pattern
, 0, 0) == x
)
6587 case UNSPECV_CONST_END
:
6597 /* Return true if it's possible to redirect BRANCH1 to the destination
6598 of an unconditional jump BRANCH2. We only want to do this if the
6599 resulting branch will have a short displacement. */
6601 sh_can_redirect_branch (branch1
, branch2
)
6605 if (flag_expensive_optimizations
&& simplejump_p (branch2
))
6607 rtx dest
= XEXP (SET_SRC (single_set (branch2
)), 0);
6611 for (distance
= 0, insn
= NEXT_INSN (branch1
);
6612 insn
&& distance
< 256;
6613 insn
= PREV_INSN (insn
))
6618 distance
+= get_attr_length (insn
);
6620 for (distance
= 0, insn
= NEXT_INSN (branch1
);
6621 insn
&& distance
< 256;
6622 insn
= NEXT_INSN (insn
))
6627 distance
+= get_attr_length (insn
);
6633 #ifndef OBJECT_FORMAT_ELF
6635 sh_asm_named_section (name
, flags
)
6637 unsigned int flags ATTRIBUTE_UNUSED
;
6639 /* ??? Perhaps we should be using default_coff_asm_named_section. */
6640 fprintf (asm_out_file
, "\t.section %s\n", name
);
6642 #endif /* ! OBJECT_FORMAT_ELF */
6644 /* A C statement (sans semicolon) to update the integer variable COST
6645 based on the relationship between INSN that is dependent on
6646 DEP_INSN through the dependence LINK. The default is to make no
6647 adjustment to COST. This can be used for example to specify to
6648 the scheduler that an output- or anti-dependence does not incur
6649 the same cost as a data-dependence. */
6651 sh_adjust_cost (insn
, link
, dep_insn
, cost
)
6653 rtx link ATTRIBUTE_UNUSED
;
6659 if (GET_CODE(insn
) == CALL_INSN
)
6661 /* The only input for a call that is timing-critical is the
6662 function's address. */
6663 rtx call
= PATTERN (insn
);
6665 if (GET_CODE (call
) == PARALLEL
)
6666 call
= XVECEXP (call
, 0 ,0);
6667 if (GET_CODE (call
) == SET
)
6668 call
= SET_SRC (call
);
6669 if (GET_CODE (call
) == CALL
&& GET_CODE (XEXP (call
, 0)) == MEM
6670 && ! reg_set_p (XEXP (XEXP (call
, 0), 0), dep_insn
))
6673 /* All sfunc calls are parallels with at least four components.
6674 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
6675 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
6676 && XVECLEN (PATTERN (insn
), 0) >= 4
6677 && (reg
= sfunc_uses_reg (insn
)))
6679 /* Likewise, the most timing critical input for an sfuncs call
6680 is the function address. However, sfuncs typically start
6681 using their arguments pretty quickly.
6682 Assume a four cycle delay before they are needed. */
6683 if (! reg_set_p (reg
, dep_insn
))
6684 cost
-= TARGET_SUPERSCALAR
? 40 : 4;
6686 /* Adjust load_si / pcload_si type insns latency. Use the known
6687 nominal latency and form of the insn to speed up the check. */
6689 && GET_CODE (PATTERN (dep_insn
)) == SET
6690 /* Latency for dmpy type insns is also 3, so check the that
6691 it's actually a move insn. */
6692 && general_movsrc_operand (SET_SRC (PATTERN (dep_insn
)), SImode
))
6695 && GET_CODE (PATTERN (dep_insn
)) == SET
6696 && GET_MODE (SET_SRC (PATTERN (dep_insn
))) == SImode
)
6702 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
6703 'special function' patterns (type sfunc) that clobber pr, but that
6704 do not look like function calls to leaf_function_p. Hence we must
6705 do this extra check. */
6709 return REG_N_SETS (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
6712 /* SHmedia requires registers for branches, so we can't generate new
6713 branches past reload. */
6715 sh_cannot_modify_jumps_p ()
6717 return (TARGET_SHMEDIA
&& (reload_in_progress
|| reload_completed
));
6721 sh_ms_bitfield_layout_p (record_type
)
6722 tree record_type ATTRIBUTE_UNUSED
;