1 /* Output routines for GCC for Hitachi Super-H.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
33 #include "hard-reg-set.h"
35 #include "insn-attr.h"
41 #include "target-def.h"
43 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
45 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
46 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
48 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
49 int current_function_interrupt
;
51 /* ??? The pragma interrupt support will not work for SH3. */
52 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
53 output code for the next function appropriate for an interrupt handler. */
56 /* This is set by the trap_exit attribute for functions. It specifies
57 a trap number to be used in a trapa instruction at function exit
58 (instead of an rte instruction). */
61 /* This is used by the sp_switch attribute for functions. It specifies
62 a variable holding the address of the stack the interrupt function
63 should switch to/from at entry/exit. */
66 /* This is set by #pragma trapa, and is similar to the above, except that
67 the compiler doesn't emit code to preserve all registers. */
68 static int pragma_trapa
;
70 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
71 which has a separate set of low regs for User and Supervisor modes.
72 This should only be used for the lowest level of interrupts. Higher levels
73 of interrupts must save the registers in case they themselves are
75 int pragma_nosave_low_regs
;
77 /* This is used for communication between SETUP_INCOMING_VARARGS and
78 sh_expand_prologue. */
79 int current_function_anonymous_args
;
81 /* Global variables for machine-dependent things. */
83 /* Which cpu are we scheduling for. */
84 enum processor_type sh_cpu
;
86 /* Saved operands from the last compare to use when we generate an scc
92 /* Provides the class number of the smallest class containing
95 int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
97 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
98 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
99 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
100 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
101 GENERAL_REGS
, PR_REGS
, T_REGS
, NO_REGS
,
102 MAC_REGS
, MAC_REGS
, FPUL_REGS
, GENERAL_REGS
,
103 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
104 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
105 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
106 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
107 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
108 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
112 char fp_reg_names
[][5] =
114 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
115 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
117 "xd0","xd2","xd4", "xd6", "xd8", "xd10", "xd12", "xd14",
120 /* Provide reg_class from a letter such as appears in the machine
123 enum reg_class reg_class_from_letter
[] =
125 /* a */ ALL_REGS
, /* b */ NO_REGS
, /* c */ FPSCR_REGS
, /* d */ DF_REGS
,
126 /* e */ NO_REGS
, /* f */ FP_REGS
, /* g */ NO_REGS
, /* h */ NO_REGS
,
127 /* i */ NO_REGS
, /* j */ NO_REGS
, /* k */ SIBCALL_REGS
, /* l */ PR_REGS
,
128 /* m */ NO_REGS
, /* n */ NO_REGS
, /* o */ NO_REGS
, /* p */ NO_REGS
,
129 /* q */ NO_REGS
, /* r */ NO_REGS
, /* s */ NO_REGS
, /* t */ T_REGS
,
130 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ FP0_REGS
, /* x */ MAC_REGS
,
131 /* y */ FPUL_REGS
, /* z */ R0_REGS
134 int assembler_dialect
;
136 static void split_branches
PARAMS ((rtx
));
137 static int branch_dest
PARAMS ((rtx
));
138 static void force_into
PARAMS ((rtx
, rtx
));
139 static void print_slot
PARAMS ((rtx
));
140 static rtx add_constant
PARAMS ((rtx
, enum machine_mode
, rtx
));
141 static void dump_table
PARAMS ((rtx
));
142 static int hi_const
PARAMS ((rtx
));
143 static int broken_move
PARAMS ((rtx
));
144 static int mova_p
PARAMS ((rtx
));
145 static rtx find_barrier
PARAMS ((int, rtx
, rtx
));
146 static int noncall_uses_reg
PARAMS ((rtx
, rtx
, rtx
*));
147 static rtx gen_block_redirect
PARAMS ((rtx
, int, int));
148 static void output_stack_adjust
PARAMS ((int, rtx
, int));
149 static void push
PARAMS ((int));
150 static void pop
PARAMS ((int));
151 static void push_regs
PARAMS ((int, int));
152 static int calc_live_regs
PARAMS ((int *, int *));
153 static void mark_use
PARAMS ((rtx
, rtx
*));
154 static HOST_WIDE_INT rounded_frame_size
PARAMS ((int));
155 static rtx mark_constant_pool_use
PARAMS ((rtx
));
156 static int sh_valid_decl_attribute
PARAMS ((tree
, tree
, tree
, tree
));
157 static void sh_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
158 static void sh_insert_attributes
PARAMS ((tree
, tree
*));
160 /* Initialize the GCC target structure. */
161 #undef TARGET_VALID_DECL_ATTRIBUTE
162 #define TARGET_VALID_DECL_ATTRIBUTE sh_valid_decl_attribute
164 #undef TARGET_ASM_FUNCTION_EPILOGUE
165 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
167 #undef TARGET_INSERT_ATTRIBUTES
168 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
170 struct gcc_target targetm
= TARGET_INITIALIZER
;
172 /* Print the operand address in x to the stream. */
175 print_operand_address (stream
, x
)
179 switch (GET_CODE (x
))
183 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
188 rtx base
= XEXP (x
, 0);
189 rtx index
= XEXP (x
, 1);
191 switch (GET_CODE (index
))
194 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
195 reg_names
[true_regnum (base
)]);
201 int base_num
= true_regnum (base
);
202 int index_num
= true_regnum (index
);
204 fprintf (stream
, "@(r0,%s)",
205 reg_names
[MAX (base_num
, index_num
)]);
217 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
221 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
225 x
= mark_constant_pool_use (x
);
226 output_addr_const (stream
, x
);
231 /* Print operand x (an rtx) in assembler syntax to file stream
232 according to modifier code.
234 '.' print a .s if insn needs delay slot
235 ',' print LOCAL_LABEL_PREFIX
236 '@' print trap, rte or rts depending upon pragma interruptness
237 '#' output a nop if there is nothing to put in the delay slot
238 'O' print a constant without the #
239 'R' print the LSW of a dp value - changes if in little endian
240 'S' print the MSW of a dp value - changes if in little endian
241 'T' print the next word of a dp value - same as 'R' in big endian mode.
242 'o' output an operator. */
245 print_operand (stream
, x
, code
)
254 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
255 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
258 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
262 int interrupt_handler
;
264 if ((lookup_attribute
265 ("interrupt_handler",
266 DECL_MACHINE_ATTRIBUTES (current_function_decl
)))
268 interrupt_handler
= 1;
270 interrupt_handler
= 0;
273 fprintf (stream
, "trapa #%d", trap_exit
);
274 else if (interrupt_handler
)
275 fprintf (stream
, "rte");
277 fprintf (stream
, "rts");
281 /* Output a nop if there's nothing in the delay slot. */
282 if (dbr_sequence_length () == 0)
283 fprintf (stream
, "\n\tnop");
286 x
= mark_constant_pool_use (x
);
287 output_addr_const (stream
, x
);
290 fputs (reg_names
[REGNO (x
) + LSW
], (stream
));
293 fputs (reg_names
[REGNO (x
) + MSW
], (stream
));
296 /* Next word of a double. */
297 switch (GET_CODE (x
))
300 fputs (reg_names
[REGNO (x
) + 1], (stream
));
303 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
304 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
305 x
= adjust_address (x
, SImode
, 4);
306 print_operand_address (stream
, XEXP (x
, 0));
313 switch (GET_CODE (x
))
315 case PLUS
: fputs ("add", stream
); break;
316 case MINUS
: fputs ("sub", stream
); break;
317 case MULT
: fputs ("mul", stream
); break;
318 case DIV
: fputs ("div", stream
); break;
324 switch (GET_CODE (x
))
327 if (FP_REGISTER_P (REGNO (x
))
328 && GET_MODE_SIZE (GET_MODE (x
)) > 4)
329 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)]+1);
331 fputs (reg_names
[REGNO (x
)], (stream
));
334 output_address (XEXP (x
, 0));
338 output_addr_const (stream
, x
);
345 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
347 force_into (value
, target
)
350 value
= force_operand (value
, target
);
351 if (! rtx_equal_p (value
, target
))
352 emit_insn (gen_move_insn (target
, value
));
355 /* Emit code to perform a block move. Choose the best method.
357 OPERANDS[0] is the destination.
358 OPERANDS[1] is the source.
359 OPERANDS[2] is the size.
360 OPERANDS[3] is the alignment safe to use. */
363 expand_block_move (operands
)
366 int align
= INTVAL (operands
[3]);
367 int constp
= (GET_CODE (operands
[2]) == CONST_INT
);
368 int bytes
= (constp
? INTVAL (operands
[2]) : 0);
370 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
371 alignment, or if it isn't a multiple of 4 bytes, then fail. */
372 if (! constp
|| align
< 4 || (bytes
% 4 != 0))
379 else if (bytes
== 12)
384 rtx r4
= gen_rtx (REG
, SImode
, 4);
385 rtx r5
= gen_rtx (REG
, SImode
, 5);
387 entry_name
= get_identifier ("__movstrSI12_i4");
389 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
390 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
391 force_into (XEXP (operands
[0], 0), r4
);
392 force_into (XEXP (operands
[1], 0), r5
);
393 emit_insn (gen_block_move_real_i4 (func_addr_rtx
));
396 else if (! TARGET_SMALLCODE
)
402 rtx r4
= gen_rtx (REG
, SImode
, 4);
403 rtx r5
= gen_rtx (REG
, SImode
, 5);
404 rtx r6
= gen_rtx (REG
, SImode
, 6);
406 entry_name
= get_identifier (bytes
& 4
408 : "__movstr_i4_even");
409 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
410 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
411 force_into (XEXP (operands
[0], 0), r4
);
412 force_into (XEXP (operands
[1], 0), r5
);
415 emit_insn (gen_move_insn (r6
, GEN_INT (dwords
- 1)));
416 emit_insn (gen_block_lump_real_i4 (func_addr_rtx
));
428 rtx r4
= gen_rtx_REG (SImode
, 4);
429 rtx r5
= gen_rtx_REG (SImode
, 5);
431 sprintf (entry
, "__movstrSI%d", bytes
);
432 entry_name
= get_identifier (entry
);
433 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
434 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
435 force_into (XEXP (operands
[0], 0), r4
);
436 force_into (XEXP (operands
[1], 0), r5
);
437 emit_insn (gen_block_move_real (func_addr_rtx
));
441 /* This is the same number of bytes as a memcpy call, but to a different
442 less common function name, so this will occasionally use more space. */
443 if (! TARGET_SMALLCODE
)
448 int final_switch
, while_loop
;
449 rtx r4
= gen_rtx_REG (SImode
, 4);
450 rtx r5
= gen_rtx_REG (SImode
, 5);
451 rtx r6
= gen_rtx_REG (SImode
, 6);
453 entry_name
= get_identifier ("__movstr");
454 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
455 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
456 force_into (XEXP (operands
[0], 0), r4
);
457 force_into (XEXP (operands
[1], 0), r5
);
459 /* r6 controls the size of the move. 16 is decremented from it
460 for each 64 bytes moved. Then the negative bit left over is used
461 as an index into a list of move instructions. e.g., a 72 byte move
462 would be set up with size(r6) = 14, for one iteration through the
463 big while loop, and a switch of -2 for the last part. */
465 final_switch
= 16 - ((bytes
/ 4) % 16);
466 while_loop
= ((bytes
/ 4) / 16 - 1) * 16;
467 emit_insn (gen_move_insn (r6
, GEN_INT (while_loop
+ final_switch
)));
468 emit_insn (gen_block_lump_real (func_addr_rtx
));
475 /* Prepare operands for a move define_expand; specifically, one of the
476 operands must be in a register. */
479 prepare_move_operands (operands
, mode
)
481 enum machine_mode mode
;
483 if (mode
== SImode
&& flag_pic
)
486 if (SYMBOLIC_CONST_P (operands
[1]))
488 if (GET_CODE (operands
[0]) == MEM
)
489 operands
[1] = force_reg (Pmode
, operands
[1]);
492 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
493 operands
[1] = legitimize_pic_address (operands
[1], SImode
, temp
);
496 else if (GET_CODE (operands
[1]) == CONST
497 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
498 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
500 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
501 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
503 operands
[1] = expand_binop (SImode
, add_optab
, temp
,
504 XEXP (XEXP (operands
[1], 0), 1),
505 no_new_pseudos
? temp
506 : gen_reg_rtx (Pmode
),
511 if (! reload_in_progress
&& ! reload_completed
)
513 /* Copy the source to a register if both operands aren't registers. */
514 if (! register_operand (operands
[0], mode
)
515 && ! register_operand (operands
[1], mode
))
516 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
518 /* This case can happen while generating code to move the result
519 of a library call to the target. Reject `st r0,@(rX,rY)' because
520 reload will fail to find a spill register for rX, since r0 is already
521 being used for the source. */
522 else if (GET_CODE (operands
[1]) == REG
&& REGNO (operands
[1]) == 0
523 && GET_CODE (operands
[0]) == MEM
524 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
525 && GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == REG
)
526 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
532 /* Prepare the operands for an scc instruction; make sure that the
533 compare has been done. */
535 prepare_scc_operands (code
)
538 rtx t_reg
= gen_rtx_REG (SImode
, T_REG
);
539 enum rtx_code oldcode
= code
;
540 enum machine_mode mode
;
542 /* First need a compare insn. */
546 /* It isn't possible to handle this case. */
565 rtx tmp
= sh_compare_op0
;
566 sh_compare_op0
= sh_compare_op1
;
567 sh_compare_op1
= tmp
;
570 mode
= GET_MODE (sh_compare_op0
);
571 if (mode
== VOIDmode
)
572 mode
= GET_MODE (sh_compare_op1
);
574 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
575 if ((code
!= EQ
&& code
!= NE
576 && (sh_compare_op1
!= const0_rtx
577 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
578 || (mode
== DImode
&& sh_compare_op1
!= const0_rtx
)
579 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
580 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
582 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
583 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
)
584 (gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec (2,
585 gen_rtx (SET
, VOIDmode
, t_reg
,
586 gen_rtx (code
, SImode
,
587 sh_compare_op0
, sh_compare_op1
)),
588 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ()))));
590 emit_insn (gen_rtx (SET
, VOIDmode
, t_reg
,
591 gen_rtx (code
, SImode
, sh_compare_op0
,
597 /* Called from the md file, set up the operands of a compare instruction. */
600 from_compare (operands
, code
)
604 enum machine_mode mode
= GET_MODE (sh_compare_op0
);
606 if (mode
== VOIDmode
)
607 mode
= GET_MODE (sh_compare_op1
);
610 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
612 /* Force args into regs, since we can't use constants here. */
613 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
614 if (sh_compare_op1
!= const0_rtx
615 || code
== GTU
|| code
== GEU
616 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
617 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
619 if (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
&& code
== GE
)
621 from_compare (operands
, GT
);
622 insn
= gen_ieee_ccmpeqsf_t (sh_compare_op0
, sh_compare_op1
);
625 insn
= gen_rtx_SET (VOIDmode
,
626 gen_rtx_REG (SImode
, T_REG
),
627 gen_rtx (code
, SImode
, sh_compare_op0
,
629 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
631 insn
= gen_rtx (PARALLEL
, VOIDmode
,
633 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ())));
634 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
) (insn
);
640 /* Functions to output assembly code. */
642 /* Return a sequence of instructions to perform DI or DF move.
644 Since the SH cannot move a DI or DF in one instruction, we have
645 to take care when we see overlapping source and dest registers. */
648 output_movedouble (insn
, operands
, mode
)
649 rtx insn ATTRIBUTE_UNUSED
;
651 enum machine_mode mode
;
653 rtx dst
= operands
[0];
654 rtx src
= operands
[1];
656 if (GET_CODE (dst
) == MEM
657 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
658 return "mov.l %T1,%0\n\tmov.l %1,%0";
660 if (register_operand (dst
, mode
)
661 && register_operand (src
, mode
))
663 if (REGNO (src
) == MACH_REG
)
664 return "sts mach,%S0\n\tsts macl,%R0";
666 /* When mov.d r1,r2 do r2->r3 then r1->r2;
667 when mov.d r1,r0 do r1->r0 then r2->r1. */
669 if (REGNO (src
) + 1 == REGNO (dst
))
670 return "mov %T1,%T0\n\tmov %1,%0";
672 return "mov %1,%0\n\tmov %T1,%T0";
674 else if (GET_CODE (src
) == CONST_INT
)
676 if (INTVAL (src
) < 0)
677 output_asm_insn ("mov #-1,%S0", operands
);
679 output_asm_insn ("mov #0,%S0", operands
);
683 else if (GET_CODE (src
) == MEM
)
686 int dreg
= REGNO (dst
);
687 rtx inside
= XEXP (src
, 0);
689 if (GET_CODE (inside
) == REG
)
690 ptrreg
= REGNO (inside
);
691 else if (GET_CODE (inside
) == SUBREG
)
692 ptrreg
= subreg_regno (inside
);
693 else if (GET_CODE (inside
) == PLUS
)
695 ptrreg
= REGNO (XEXP (inside
, 0));
696 /* ??? A r0+REG address shouldn't be possible here, because it isn't
697 an offsettable address. Unfortunately, offsettable addresses use
698 QImode to check the offset, and a QImode offsettable address
699 requires r0 for the other operand, which is not currently
700 supported, so we can't use the 'o' constraint.
701 Thus we must check for and handle r0+REG addresses here.
702 We punt for now, since this is likely very rare. */
703 if (GET_CODE (XEXP (inside
, 1)) == REG
)
706 else if (GET_CODE (inside
) == LABEL_REF
)
707 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
708 else if (GET_CODE (inside
) == POST_INC
)
709 return "mov.l %1,%0\n\tmov.l %1,%T0";
713 /* Work out the safe way to copy. Copy into the second half first. */
715 return "mov.l %T1,%T0\n\tmov.l %1,%0";
718 return "mov.l %1,%0\n\tmov.l %T1,%T0";
721 /* Print an instruction which would have gone into a delay slot after
722 another instruction, but couldn't because the other instruction expanded
723 into a sequence where putting the slot insn at the end wouldn't work. */
729 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
, optimize
, 0, 1);
731 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
735 output_far_jump (insn
, op
)
739 struct { rtx lab
, reg
, op
; } this;
743 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
745 this.lab
= gen_label_rtx ();
749 && offset
- get_attr_length (insn
) <= 32766)
752 jump
= "mov.w %O0,%1; braf %1";
760 jump
= "mov.l %O0,%1; braf %1";
762 jump
= "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
765 jump
= "mov.l %O0,%1; jmp @%1";
767 /* If we have a scratch register available, use it. */
768 if (GET_CODE (PREV_INSN (insn
)) == INSN
769 && INSN_CODE (PREV_INSN (insn
)) == CODE_FOR_indirect_jump_scratch
)
771 this.reg
= SET_DEST (PATTERN (PREV_INSN (insn
)));
772 if (REGNO (this.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
773 jump
= "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
774 output_asm_insn (jump
, &this.lab
);
775 if (dbr_sequence_length ())
776 print_slot (final_sequence
);
778 output_asm_insn ("nop", 0);
782 /* Output the delay slot insn first if any. */
783 if (dbr_sequence_length ())
784 print_slot (final_sequence
);
786 this.reg
= gen_rtx_REG (SImode
, 13);
787 output_asm_insn ("mov.l r13,@-r15", 0);
788 output_asm_insn (jump
, &this.lab
);
789 output_asm_insn ("mov.l @r15+,r13", 0);
791 if (far
&& flag_pic
&& TARGET_SH2
)
793 braf_base_lab
= gen_label_rtx ();
794 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
795 CODE_LABEL_NUMBER (braf_base_lab
));
798 output_asm_insn (".align 2", 0);
799 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (this.lab
));
804 this.lab
= braf_base_lab
;
805 output_asm_insn (".long %O2-%O0", &this.lab
);
808 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this.lab
);
812 /* Local label counter, used for constants in the pool and inside
817 /* Output code for ordinary branches. */
820 output_branch (logic
, insn
, operands
)
825 switch (get_attr_length (insn
))
828 /* This can happen if filling the delay slot has caused a forward
829 branch to exceed its range (we could reverse it, but only
830 when we know we won't overextend other branches; this should
831 best be handled by relaxation).
832 It can also happen when other condbranches hoist delay slot insn
833 from their destination, thus leading to code size increase.
834 But the branch will still be in the range -4092..+4098 bytes. */
839 /* The call to print_slot will clobber the operands. */
840 rtx op0
= operands
[0];
842 /* If the instruction in the delay slot is annulled (true), then
843 there is no delay slot where we can put it now. The only safe
844 place for it is after the label. final will do that by default. */
847 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
849 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
850 ASSEMBLER_DIALECT
? "/" : ".", label
);
851 print_slot (final_sequence
);
854 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
856 output_asm_insn ("bra\t%l0", &op0
);
857 fprintf (asm_out_file
, "\tnop\n");
858 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file
, "LF", label
);
862 /* When relaxing, handle this like a short branch. The linker
863 will fix it up if it still doesn't fit after relaxation. */
865 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
867 /* There should be no longer branches now - that would
868 indicate that something has destroyed the branches set
869 up in machine_dependent_reorg. */
875 output_branchy_insn (code
, template, insn
, operands
)
877 const char *template;
881 rtx next_insn
= NEXT_INSN (insn
);
883 if (next_insn
&& GET_CODE (next_insn
) == JUMP_INSN
&& condjump_p (next_insn
))
885 rtx src
= SET_SRC (PATTERN (next_insn
));
886 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
888 /* Following branch not taken */
889 operands
[9] = gen_label_rtx ();
890 emit_label_after (operands
[9], next_insn
);
891 INSN_ADDRESSES_NEW (operands
[9],
892 INSN_ADDRESSES (INSN_UID (next_insn
))
893 + get_attr_length (next_insn
));
898 int offset
= (branch_dest (next_insn
)
899 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
900 if (offset
>= -252 && offset
<= 258)
902 if (GET_CODE (src
) == IF_THEN_ELSE
)
910 operands
[9] = gen_label_rtx ();
911 emit_label_after (operands
[9], insn
);
912 INSN_ADDRESSES_NEW (operands
[9],
913 INSN_ADDRESSES (INSN_UID (insn
))
914 + get_attr_length (insn
));
919 output_ieee_ccmpeq (insn
, operands
)
922 return output_branchy_insn (NE
, "bt\t%l9\\;fcmp/eq\t%1,%0", insn
, operands
);
925 /* Output to FILE the start of the assembler file. */
928 output_file_start (file
)
931 output_file_directive (file
, main_input_filename
);
933 /* Switch to the data section so that the coffsem symbol
934 isn't in the text section. */
937 if (TARGET_LITTLE_ENDIAN
)
938 fprintf (file
, "\t.little\n");
941 /* Actual number of instructions used to make a shift by N. */
942 static char ashiftrt_insns
[] =
943 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
945 /* Left shift and logical right shift are the same. */
946 static char shift_insns
[] =
947 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
949 /* Individual shift amounts needed to get the above length sequences.
950 One bit right shifts clobber the T bit, so when possible, put one bit
951 shifts in the middle of the sequence, so the ends are eligible for
952 branch delay slots. */
953 static short shift_amounts
[32][5] = {
954 {0}, {1}, {2}, {2, 1},
955 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
956 {8}, {8, 1}, {8, 2}, {8, 1, 2},
957 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
958 {16}, {16, 1}, {16, 2}, {16, 1, 2},
959 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
960 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
961 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
963 /* Likewise, but for shift amounts < 16, up to three highmost bits
964 might be clobbered. This is typically used when combined with some
965 kind of sign or zero extension. */
967 static char ext_shift_insns
[] =
968 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
970 static short ext_shift_amounts
[32][4] = {
971 {0}, {1}, {2}, {2, 1},
972 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
973 {8}, {8, 1}, {8, 2}, {8, 1, 2},
974 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
975 {16}, {16, 1}, {16, 2}, {16, 1, 2},
976 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
977 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
978 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
980 /* Assuming we have a value that has been sign-extended by at least one bit,
981 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
982 to shift it by N without data loss, and quicker than by other means? */
983 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
985 /* This is used in length attributes in sh.md to help compute the length
986 of arbitrary constant shift instructions. */
989 shift_insns_rtx (insn
)
992 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
993 int shift_count
= INTVAL (XEXP (set_src
, 1));
994 enum rtx_code shift_code
= GET_CODE (set_src
);
999 return ashiftrt_insns
[shift_count
];
1002 return shift_insns
[shift_count
];
1008 /* Return the cost of a shift. */
1016 /* If shift by a non constant, then this will be expensive. */
1017 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1018 return SH_DYNAMIC_SHIFT_COST
;
1020 value
= INTVAL (XEXP (x
, 1));
1022 /* Otherwise, return the true cost in instructions. */
1023 if (GET_CODE (x
) == ASHIFTRT
)
1025 int cost
= ashiftrt_insns
[value
];
1026 /* If SH3, then we put the constant in a reg and use shad. */
1027 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
1028 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
1032 return shift_insns
[value
];
1035 /* Return the cost of an AND operation. */
1043 /* Anding with a register is a single cycle and instruction. */
1044 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1047 i
= INTVAL (XEXP (x
, 1));
1048 /* These constants are single cycle extu.[bw] instructions. */
1049 if (i
== 0xff || i
== 0xffff)
1051 /* Constants that can be used in an and immediate instruction is a single
1052 cycle, but this requires r0, so make it a little more expensive. */
1053 if (CONST_OK_FOR_L (i
))
1055 /* Constants that can be loaded with a mov immediate and an and.
1056 This case is probably unnecessary. */
1057 if (CONST_OK_FOR_I (i
))
1059 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1060 This case is probably unnecessary. */
1064 /* Return the cost of an addition or a subtraction. */
1070 /* Adding a register is a single cycle insn. */
1071 if (GET_CODE (XEXP (x
, 1)) == REG
1072 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1075 /* Likewise for small constants. */
1076 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1077 && CONST_OK_FOR_I (INTVAL (XEXP (x
, 1))))
1080 /* Any other constant requires a 2 cycle pc-relative load plus an
1085 /* Return the cost of a multiply. */
1088 rtx x ATTRIBUTE_UNUSED
;
1092 /* We have a mul insn, so we can never take more than the mul and the
1093 read of the mac reg, but count more because of the latency and extra
1095 if (TARGET_SMALLCODE
)
1100 /* If we're aiming at small code, then just count the number of
1101 insns in a multiply call sequence. */
1102 if (TARGET_SMALLCODE
)
1105 /* Otherwise count all the insns in the routine we'd be calling too. */
1109 /* Code to expand a shift. */
1112 gen_ashift (type
, n
, reg
)
1117 /* Negative values here come from the shift_amounts array. */
1130 emit_insn (gen_ashrsi3_k (reg
, reg
, GEN_INT (n
)));
1134 emit_insn (gen_lshrsi3_m (reg
, reg
, GEN_INT (n
)));
1136 emit_insn (gen_lshrsi3_k (reg
, reg
, GEN_INT (n
)));
1139 emit_insn (gen_ashlsi3_std (reg
, reg
, GEN_INT (n
)));
1144 /* Same for HImode */
1147 gen_ashift_hi (type
, n
, reg
)
1152 /* Negative values here come from the shift_amounts array. */
1166 /* We don't have HImode right shift operations because using the
1167 ordinary 32 bit shift instructions for that doesn't generate proper
1168 zero/sign extension.
1169 gen_ashift_hi is only called in contexts where we know that the
1170 sign extension works out correctly. */
1173 if (GET_CODE (reg
) == SUBREG
)
1175 offset
= SUBREG_BYTE (reg
);
1176 reg
= SUBREG_REG (reg
);
1178 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
1182 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
1187 /* Output RTL to split a constant shift into its component SH constant
1188 shift instructions. */
1191 gen_shifty_op (code
, operands
)
1195 int value
= INTVAL (operands
[2]);
1198 /* Truncate the shift count in case it is out of bounds. */
1199 value
= value
& 0x1f;
1203 if (code
== LSHIFTRT
)
1205 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
1206 emit_insn (gen_movt (operands
[0]));
1209 else if (code
== ASHIFT
)
1211 /* There is a two instruction sequence for 31 bit left shifts,
1212 but it requires r0. */
1213 if (GET_CODE (operands
[0]) == REG
&& REGNO (operands
[0]) == 0)
1215 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
1216 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
1221 else if (value
== 0)
1223 /* This can happen when not optimizing. We must output something here
1224 to prevent the compiler from aborting in final.c after the try_split
1226 emit_insn (gen_nop ());
1230 max
= shift_insns
[value
];
1231 for (i
= 0; i
< max
; i
++)
1232 gen_ashift (code
, shift_amounts
[value
][i
], operands
[0]);
1235 /* Same as above, but optimized for values where the topmost bits don't
1239 gen_shifty_hi_op (code
, operands
)
1243 int value
= INTVAL (operands
[2]);
1245 void (*gen_fun
) PARAMS ((int, int, rtx
));
1247 /* This operation is used by and_shl for SImode values with a few
1248 high bits known to be cleared. */
1252 emit_insn (gen_nop ());
1256 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
1259 max
= ext_shift_insns
[value
];
1260 for (i
= 0; i
< max
; i
++)
1261 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1264 /* When shifting right, emit the shifts in reverse order, so that
1265 solitary negative values come first. */
1266 for (i
= ext_shift_insns
[value
] - 1; i
>= 0; i
--)
1267 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1270 /* Output RTL for an arithmetic right shift. */
1272 /* ??? Rewrite to use super-optimizer sequences. */
1275 expand_ashiftrt (operands
)
1286 if (GET_CODE (operands
[2]) != CONST_INT
)
1288 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
1289 emit_insn (gen_negsi2 (count
, count
));
1290 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1293 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
1294 > 1 + SH_DYNAMIC_SHIFT_COST
)
1297 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
1298 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1302 if (GET_CODE (operands
[2]) != CONST_INT
)
1305 value
= INTVAL (operands
[2]) & 31;
1309 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
1312 else if (value
>= 16 && value
<= 19)
1314 wrk
= gen_reg_rtx (SImode
);
1315 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
1318 gen_ashift (ASHIFTRT
, 1, wrk
);
1319 emit_move_insn (operands
[0], wrk
);
1322 /* Expand a short sequence inline, longer call a magic routine. */
1323 else if (value
<= 5)
1325 wrk
= gen_reg_rtx (SImode
);
1326 emit_move_insn (wrk
, operands
[1]);
1328 gen_ashift (ASHIFTRT
, 1, wrk
);
1329 emit_move_insn (operands
[0], wrk
);
1333 wrk
= gen_reg_rtx (Pmode
);
1335 /* Load the value into an arg reg and call a helper. */
1336 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
1337 sprintf (func
, "__ashiftrt_r4_%d", value
);
1338 func_name
= get_identifier (func
);
1339 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (func_name
));
1340 emit_move_insn (wrk
, sym
);
1341 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
1342 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
1347 sh_dynamicalize_shift_p (count
)
1350 return shift_insns
[INTVAL (count
)] > 1 + SH_DYNAMIC_SHIFT_COST
;
1353 /* Try to find a good way to implement the combiner pattern
1354 [(set (match_operand:SI 0 "register_operand" "r")
1355 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1356 (match_operand:SI 2 "const_int_operand" "n"))
1357 (match_operand:SI 3 "const_int_operand" "n"))) .
1358 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1359 return 0 for simple right / left or left/right shift combination.
1360 return 1 for a combination of shifts with zero_extend.
1361 return 2 for a combination of shifts with an AND that needs r0.
1362 return 3 for a combination of shifts with an AND that needs an extra
1363 scratch register, when the three highmost bits of the AND mask are clear.
1364 return 4 for a combination of shifts with an AND that needs an extra
1365 scratch register, when any of the three highmost bits of the AND mask
1367 If ATTRP is set, store an initial right shift width in ATTRP[0],
1368 and the instruction length in ATTRP[1] . These values are not valid
1370 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1371 shift_amounts for the last shift value that is to be used before the
1374 shl_and_kind (left_rtx
, mask_rtx
, attrp
)
1375 rtx left_rtx
, mask_rtx
;
1378 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
1379 int left
= INTVAL (left_rtx
), right
;
1381 int cost
, best_cost
= 10000;
1382 int best_right
= 0, best_len
= 0;
1386 if (left
< 0 || left
> 31)
1388 if (GET_CODE (mask_rtx
) == CONST_INT
)
1389 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
1391 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
1392 /* Can this be expressed as a right shift / left shift pair ? */
1393 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
1394 right
= exact_log2 (lsb
);
1395 mask2
= ~(mask
+ lsb
- 1);
1396 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
1397 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1399 best_cost
= shift_insns
[right
] + shift_insns
[right
+ left
];
1400 /* mask has no trailing zeroes <==> ! right */
1401 else if (! right
&& mask2
== ~(lsb2
- 1))
1403 int late_right
= exact_log2 (lsb2
);
1404 best_cost
= shift_insns
[left
+ late_right
] + shift_insns
[late_right
];
1406 /* Try to use zero extend */
1407 if (mask2
== ~(lsb2
- 1))
1411 for (width
= 8; width
<= 16; width
+= 8)
1413 /* Can we zero-extend right away? */
1414 if (lsb2
== (unsigned HOST_WIDE_INT
)1 << width
)
1417 = 1 + ext_shift_insns
[right
] + ext_shift_insns
[left
+ right
];
1418 if (cost
< best_cost
)
1429 /* ??? Could try to put zero extend into initial right shift,
1430 or even shift a bit left before the right shift. */
1431 /* Determine value of first part of left shift, to get to the
1432 zero extend cut-off point. */
1433 first
= width
- exact_log2 (lsb2
) + right
;
1434 if (first
>= 0 && right
+ left
- first
>= 0)
1436 cost
= ext_shift_insns
[right
] + ext_shift_insns
[first
] + 1
1437 + ext_shift_insns
[right
+ left
- first
];
1438 if (cost
< best_cost
)
1450 /* Try to use r0 AND pattern */
1451 for (i
= 0; i
<= 2; i
++)
1455 if (! CONST_OK_FOR_L (mask
>> i
))
1457 cost
= (i
!= 0) + 2 + ext_shift_insns
[left
+ i
];
1458 if (cost
< best_cost
)
1463 best_len
= cost
- 1;
1466 /* Try to use a scratch register to hold the AND operand. */
1467 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
)3 << 30)) == 0;
1468 for (i
= 0; i
<= 2; i
++)
1472 cost
= (i
!= 0) + (CONST_OK_FOR_I (mask
>> i
) ? 2 : 3)
1473 + (can_ext
? ext_shift_insns
: shift_insns
)[left
+ i
];
1474 if (cost
< best_cost
)
1479 best_len
= cost
- 1 - ! CONST_OK_FOR_I (mask
>> i
);
1485 attrp
[0] = best_right
;
1486 attrp
[1] = best_len
;
1491 /* This is used in length attributes of the unnamed instructions
1492 corresponding to shl_and_kind return values of 1 and 2. */
1494 shl_and_length (insn
)
1497 rtx set_src
, left_rtx
, mask_rtx
;
1500 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1501 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
1502 mask_rtx
= XEXP (set_src
, 1);
1503 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1504 return attributes
[1];
1507 /* This is used in length attribute of the and_shl_scratch instruction. */
1510 shl_and_scr_length (insn
)
1513 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1514 int len
= shift_insns
[INTVAL (XEXP (set_src
, 1))];
1515 rtx op
= XEXP (set_src
, 0);
1516 len
+= shift_insns
[INTVAL (XEXP (op
, 1))] + 1;
1517 op
= XEXP (XEXP (op
, 0), 0);
1518 return len
+ shift_insns
[INTVAL (XEXP (op
, 1))];
1521 /* Generating rtl? */
1522 extern int rtx_equal_function_value_matters
;
1524 /* Generate rtl for instructions for which shl_and_kind advised a particular
1525 method of generating them, i.e. returned zero. */
1528 gen_shl_and (dest
, left_rtx
, mask_rtx
, source
)
1529 rtx dest
, left_rtx
, mask_rtx
, source
;
1532 unsigned HOST_WIDE_INT mask
;
1533 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1534 int right
, total_shift
;
1535 void (*shift_gen_fun
) PARAMS ((int, rtx
*)) = gen_shifty_hi_op
;
1537 right
= attributes
[0];
1538 total_shift
= INTVAL (left_rtx
) + right
;
1539 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
1546 int first
= attributes
[2];
1551 emit_insn ((mask
<< right
) <= 0xff
1552 ? gen_zero_extendqisi2(dest
,
1553 gen_lowpart (QImode
, source
))
1554 : gen_zero_extendhisi2(dest
,
1555 gen_lowpart (HImode
, source
)));
1559 emit_insn (gen_movsi (dest
, source
));
1563 operands
[2] = GEN_INT (right
);
1564 gen_shifty_hi_op (LSHIFTRT
, operands
);
1568 operands
[2] = GEN_INT (first
);
1569 gen_shifty_hi_op (ASHIFT
, operands
);
1570 total_shift
-= first
;
1574 emit_insn (mask
<= 0xff
1575 ? gen_zero_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
1576 : gen_zero_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
1577 if (total_shift
> 0)
1579 operands
[2] = GEN_INT (total_shift
);
1580 gen_shifty_hi_op (ASHIFT
, operands
);
1585 shift_gen_fun
= gen_shifty_op
;
1587 /* If the topmost bit that matters is set, set the topmost bits
1588 that don't matter. This way, we might be able to get a shorter
1590 if (mask
& ((HOST_WIDE_INT
)1 << (31 - total_shift
)))
1591 mask
|= (HOST_WIDE_INT
)~0 << (31 - total_shift
);
1593 /* Don't expand fine-grained when combining, because that will
1594 make the pattern fail. */
1595 if (rtx_equal_function_value_matters
1596 || reload_in_progress
|| reload_completed
)
1600 /* Cases 3 and 4 should be handled by this split
1601 only while combining */
1606 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
1609 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
1614 operands
[2] = GEN_INT (total_shift
);
1615 shift_gen_fun (ASHIFT
, operands
);
1622 if (kind
!= 4 && total_shift
< 16)
1624 neg
= -ext_shift_amounts
[total_shift
][1];
1626 neg
-= ext_shift_amounts
[total_shift
][2];
1630 emit_insn (gen_and_shl_scratch (dest
, source
,
1633 GEN_INT (total_shift
+ neg
),
1635 emit_insn (gen_movsi (dest
, dest
));
1642 /* Try to find a good way to implement the combiner pattern
1643 [(set (match_operand:SI 0 "register_operand" "=r")
1644 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1645 (match_operand:SI 2 "const_int_operand" "n")
1646 (match_operand:SI 3 "const_int_operand" "n")
1648 (clobber (reg:SI T_REG))]
1649 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1650 return 0 for simple left / right shift combination.
1651 return 1 for left shift / 8 bit sign extend / left shift.
1652 return 2 for left shift / 16 bit sign extend / left shift.
1653 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1654 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1655 return 5 for left shift / 16 bit sign extend / right shift
1656 return 6 for < 8 bit sign extend / left shift.
1657 return 7 for < 8 bit sign extend / left shift / single right shift.
1658 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1661 shl_sext_kind (left_rtx
, size_rtx
, costp
)
1662 rtx left_rtx
, size_rtx
;
1665 int left
, size
, insize
, ext
;
1666 int cost
, best_cost
;
1669 left
= INTVAL (left_rtx
);
1670 size
= INTVAL (size_rtx
);
1671 insize
= size
- left
;
1674 /* Default to left / right shift. */
1676 best_cost
= shift_insns
[32 - insize
] + ashiftrt_insns
[32 - size
];
1679 /* 16 bit shift / sign extend / 16 bit shift */
1680 cost
= shift_insns
[16 - insize
] + 1 + ashiftrt_insns
[16 - size
];
1681 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1682 below, by alternative 3 or something even better. */
1683 if (cost
< best_cost
)
1689 /* Try a plain sign extend between two shifts. */
1690 for (ext
= 16; ext
>= insize
; ext
-= 8)
1694 cost
= ext_shift_insns
[ext
- insize
] + 1 + shift_insns
[size
- ext
];
1695 if (cost
< best_cost
)
1701 /* Check if we can do a sloppy shift with a final signed shift
1702 restoring the sign. */
1703 if (EXT_SHIFT_SIGNED (size
- ext
))
1704 cost
= ext_shift_insns
[ext
- insize
] + ext_shift_insns
[size
- ext
] + 1;
1705 /* If not, maybe it's still cheaper to do the second shift sloppy,
1706 and do a final sign extend? */
1707 else if (size
<= 16)
1708 cost
= ext_shift_insns
[ext
- insize
] + 1
1709 + ext_shift_insns
[size
> ext
? size
- ext
: ext
- size
] + 1;
1712 if (cost
< best_cost
)
1714 kind
= ext
/ 8U + 2;
1718 /* Check if we can sign extend in r0 */
1721 cost
= 3 + shift_insns
[left
];
1722 if (cost
< best_cost
)
1727 /* Try the same with a final signed shift. */
1730 cost
= 3 + ext_shift_insns
[left
+ 1] + 1;
1731 if (cost
< best_cost
)
1740 /* Try to use a dynamic shift. */
1741 cost
= shift_insns
[32 - insize
] + 1 + SH_DYNAMIC_SHIFT_COST
;
1742 if (cost
< best_cost
)
1753 /* Function to be used in the length attribute of the instructions
1754 implementing this pattern. */
1757 shl_sext_length (insn
)
1760 rtx set_src
, left_rtx
, size_rtx
;
1763 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1764 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
1765 size_rtx
= XEXP (set_src
, 1);
1766 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
1770 /* Generate rtl for this pattern */
1773 gen_shl_sext (dest
, left_rtx
, size_rtx
, source
)
1774 rtx dest
, left_rtx
, size_rtx
, source
;
1777 int left
, size
, insize
, cost
;
1780 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
1781 left
= INTVAL (left_rtx
);
1782 size
= INTVAL (size_rtx
);
1783 insize
= size
- left
;
1791 int ext
= kind
& 1 ? 8 : 16;
1792 int shift2
= size
- ext
;
1794 /* Don't expand fine-grained when combining, because that will
1795 make the pattern fail. */
1796 if (! rtx_equal_function_value_matters
1797 && ! reload_in_progress
&& ! reload_completed
)
1799 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
1800 emit_insn (gen_movsi (dest
, source
));
1804 emit_insn (gen_movsi (dest
, source
));
1808 operands
[2] = GEN_INT (ext
- insize
);
1809 gen_shifty_hi_op (ASHIFT
, operands
);
1812 ? gen_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
1813 : gen_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
1818 operands
[2] = GEN_INT (shift2
);
1819 gen_shifty_op (ASHIFT
, operands
);
1826 if (EXT_SHIFT_SIGNED (shift2
))
1828 operands
[2] = GEN_INT (shift2
+ 1);
1829 gen_shifty_op (ASHIFT
, operands
);
1830 operands
[2] = GEN_INT (1);
1831 gen_shifty_op (ASHIFTRT
, operands
);
1834 operands
[2] = GEN_INT (shift2
);
1835 gen_shifty_hi_op (ASHIFT
, operands
);
1839 operands
[2] = GEN_INT (-shift2
);
1840 gen_shifty_hi_op (LSHIFTRT
, operands
);
1842 emit_insn (size
<= 8
1843 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
1844 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
1851 if (! rtx_equal_function_value_matters
1852 && ! reload_in_progress
&& ! reload_completed
)
1853 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
1857 operands
[2] = GEN_INT (16 - insize
);
1858 gen_shifty_hi_op (ASHIFT
, operands
);
1859 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
1861 /* Don't use gen_ashrsi3 because it generates new pseudos. */
1863 gen_ashift (ASHIFTRT
, 1, dest
);
1868 /* Don't expand fine-grained when combining, because that will
1869 make the pattern fail. */
1870 if (! rtx_equal_function_value_matters
1871 && ! reload_in_progress
&& ! reload_completed
)
1873 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
1874 emit_insn (gen_movsi (dest
, source
));
1877 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
1878 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
1879 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
1881 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
1882 gen_shifty_op (ASHIFT
, operands
);
1884 emit_insn (gen_ashrsi3_k (dest
, dest
, GEN_INT (1)));
1892 /* The SH cannot load a large constant into a register, constants have to
1893 come from a pc relative load. The reference of a pc relative load
1894 instruction must be less than 1k infront of the instruction. This
1895 means that we often have to dump a constant inside a function, and
1896 generate code to branch around it.
1898 It is important to minimize this, since the branches will slow things
1899 down and make things bigger.
1901 Worst case code looks like:
1919 We fix this by performing a scan before scheduling, which notices which
1920 instructions need to have their operands fetched from the constant table
1921 and builds the table.
1925 scan, find an instruction which needs a pcrel move. Look forward, find the
1926 last barrier which is within MAX_COUNT bytes of the requirement.
1927 If there isn't one, make one. Process all the instructions between
1928 the find and the barrier.
1930 In the above example, we can tell that L3 is within 1k of L1, so
1931 the first move can be shrunk from the 3 insn+constant sequence into
1932 just 1 insn, and the constant moved to L3 to make:
1943 Then the second move becomes the target for the shortening process. */
1947 rtx value
; /* Value in table. */
1948 rtx label
; /* Label of value. */
1949 rtx wend
; /* End of window. */
1950 enum machine_mode mode
; /* Mode of value. */
1953 /* The maximum number of constants that can fit into one pool, since
1954 the pc relative range is 0...1020 bytes and constants are at least 4
1957 #define MAX_POOL_SIZE (1020/4)
1958 static pool_node pool_vector
[MAX_POOL_SIZE
];
1959 static int pool_size
;
1960 static rtx pool_window_label
;
1961 static int pool_window_last
;
1963 /* ??? If we need a constant in HImode which is the truncated value of a
1964 constant we need in SImode, we could combine the two entries thus saving
1965 two bytes. Is this common enough to be worth the effort of implementing
1968 /* ??? This stuff should be done at the same time that we shorten branches.
1969 As it is now, we must assume that all branches are the maximum size, and
1970 this causes us to almost always output constant pools sooner than
1973 /* Add a constant to the pool and return its label. */
1976 add_constant (x
, mode
, last_value
)
1978 enum machine_mode mode
;
1982 rtx lab
, new, ref
, newref
;
1984 /* First see if we've already got it. */
1985 for (i
= 0; i
< pool_size
; i
++)
1987 if (x
->code
== pool_vector
[i
].value
->code
1988 && mode
== pool_vector
[i
].mode
)
1990 if (x
->code
== CODE_LABEL
)
1992 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
1995 if (rtx_equal_p (x
, pool_vector
[i
].value
))
2000 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
2002 new = gen_label_rtx ();
2003 LABEL_REFS (new) = pool_vector
[i
].label
;
2004 pool_vector
[i
].label
= lab
= new;
2006 if (lab
&& pool_window_label
)
2008 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2009 ref
= pool_vector
[pool_window_last
].wend
;
2010 LABEL_NEXTREF (newref
) = ref
;
2011 pool_vector
[pool_window_last
].wend
= newref
;
2014 pool_window_label
= new;
2015 pool_window_last
= i
;
2021 /* Need a new one. */
2022 pool_vector
[pool_size
].value
= x
;
2023 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
2026 lab
= gen_label_rtx ();
2027 pool_vector
[pool_size
].mode
= mode
;
2028 pool_vector
[pool_size
].label
= lab
;
2029 pool_vector
[pool_size
].wend
= NULL_RTX
;
2030 if (lab
&& pool_window_label
)
2032 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2033 ref
= pool_vector
[pool_window_last
].wend
;
2034 LABEL_NEXTREF (newref
) = ref
;
2035 pool_vector
[pool_window_last
].wend
= newref
;
2038 pool_window_label
= lab
;
2039 pool_window_last
= pool_size
;
2044 /* Output the literal table. */
2054 /* Do two passes, first time dump out the HI sized constants. */
2056 for (i
= 0; i
< pool_size
; i
++)
2058 pool_node
*p
= &pool_vector
[i
];
2060 if (p
->mode
== HImode
)
2064 scan
= emit_insn_after (gen_align_2 (), scan
);
2067 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2068 scan
= emit_label_after (lab
, scan
);
2069 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
2071 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2073 lab
= XEXP (ref
, 0);
2074 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2081 for (i
= 0; i
< pool_size
; i
++)
2083 pool_node
*p
= &pool_vector
[i
];
2094 scan
= emit_label_after (gen_label_rtx (), scan
);
2095 scan
= emit_insn_after (gen_align_4 (), scan
);
2097 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2098 scan
= emit_label_after (lab
, scan
);
2099 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
2107 scan
= emit_label_after (gen_label_rtx (), scan
);
2108 scan
= emit_insn_after (gen_align_4 (), scan
);
2110 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2111 scan
= emit_label_after (lab
, scan
);
2112 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2120 if (p
->mode
!= HImode
)
2122 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2124 lab
= XEXP (ref
, 0);
2125 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2130 scan
= emit_insn_after (gen_consttable_end (), scan
);
2131 scan
= emit_barrier_after (scan
);
2133 pool_window_label
= NULL_RTX
;
2134 pool_window_last
= 0;
2137 /* Return non-zero if constant would be an ok source for a
2138 mov.w instead of a mov.l. */
2144 return (GET_CODE (src
) == CONST_INT
2145 && INTVAL (src
) >= -32768
2146 && INTVAL (src
) <= 32767);
2149 /* Non-zero if the insn is a move instruction which needs to be fixed. */
2151 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2152 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2153 need to fix it if the input value is CONST_OK_FOR_I. */
2159 if (GET_CODE (insn
) == INSN
)
2161 rtx pat
= PATTERN (insn
);
2162 if (GET_CODE (pat
) == PARALLEL
)
2163 pat
= XVECEXP (pat
, 0, 0);
2164 if (GET_CODE (pat
) == SET
2165 /* We can load any 8 bit value if we don't care what the high
2166 order bits end up as. */
2167 && GET_MODE (SET_DEST (pat
)) != QImode
2168 && (CONSTANT_P (SET_SRC (pat
))
2169 /* Match mova_const. */
2170 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
2171 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
2172 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
2174 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
2175 && (fp_zero_operand (SET_SRC (pat
))
2176 || fp_one_operand (SET_SRC (pat
)))
2177 /* ??? If this is a -m4 or -m4-single compilation, we don't
2178 know the current setting of fpscr, so disable fldi. */
2179 && (! TARGET_SH4
|| TARGET_FMOVD
)
2180 && GET_CODE (SET_DEST (pat
)) == REG
2181 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
2182 && (GET_CODE (SET_SRC (pat
)) != CONST_INT
2183 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat
)))))
2194 return (GET_CODE (insn
) == INSN
2195 && GET_CODE (PATTERN (insn
)) == SET
2196 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
2197 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
2198 /* Don't match mova_const. */
2199 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn
)), 0, 0)) == LABEL_REF
);
2202 /* Find the last barrier from insn FROM which is close enough to hold the
2203 constant pool. If we can't find one, then create one near the end of
2207 find_barrier (num_mova
, mova
, from
)
2217 int leading_mova
= num_mova
;
2218 rtx barrier_before_mova
, found_barrier
= 0, good_barrier
= 0;
2222 /* For HImode: range is 510, add 4 because pc counts from address of
2223 second instruction after this one, subtract 2 for the jump instruction
2224 that we may need to emit before the table, subtract 2 for the instruction
2225 that fills the jump delay slot (in very rare cases, reorg will take an
2226 instruction from after the constant pool or will leave the delay slot
2227 empty). This gives 510.
2228 For SImode: range is 1020, add 4 because pc counts from address of
2229 second instruction after this one, subtract 2 in case pc is 2 byte
2230 aligned, subtract 2 for the jump instruction that we may need to emit
2231 before the table, subtract 2 for the instruction that fills the jump
2232 delay slot. This gives 1018. */
2234 /* The branch will always be shortened now that the reference address for
2235 forward branches is the successor address, thus we need no longer make
2236 adjustments to the [sh]i_limit for -O0. */
2241 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
2243 int inc
= get_attr_length (from
);
2246 if (GET_CODE (from
) == CODE_LABEL
)
2249 new_align
= 1 << label_to_alignment (from
);
2250 else if (GET_CODE (prev_nonnote_insn (from
)) == BARRIER
)
2251 new_align
= 1 << barrier_align (from
);
2257 if (GET_CODE (from
) == BARRIER
)
2260 found_barrier
= from
;
2262 /* If we are at the end of the function, or in front of an alignment
2263 instruction, we need not insert an extra alignment. We prefer
2264 this kind of barrier. */
2265 if (barrier_align (from
) > 2)
2266 good_barrier
= from
;
2269 if (broken_move (from
))
2272 enum machine_mode mode
;
2274 pat
= PATTERN (from
);
2275 if (GET_CODE (pat
) == PARALLEL
)
2276 pat
= XVECEXP (pat
, 0, 0);
2277 src
= SET_SRC (pat
);
2278 dst
= SET_DEST (pat
);
2279 mode
= GET_MODE (dst
);
2281 /* We must explicitly check the mode, because sometimes the
2282 front end will generate code to load unsigned constants into
2283 HImode targets without properly sign extending them. */
2285 || (mode
== SImode
&& hi_const (src
) && REGNO (dst
) != FPUL_REG
))
2288 /* We put the short constants before the long constants, so
2289 we must count the length of short constants in the range
2290 for the long constants. */
2291 /* ??? This isn't optimal, but is easy to do. */
2296 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
2298 if (found_si
> count_si
)
2299 count_si
= found_si
;
2300 found_si
+= GET_MODE_SIZE (mode
);
2302 si_limit
-= GET_MODE_SIZE (mode
);
2305 /* See the code in machine_dependent_reorg, which has a similar if
2306 statement that generates a new mova insn in many cases. */
2307 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
2317 barrier_before_mova
= good_barrier
? good_barrier
: found_barrier
;
2319 if (found_si
> count_si
)
2320 count_si
= found_si
;
2322 else if (GET_CODE (from
) == JUMP_INSN
2323 && (GET_CODE (PATTERN (from
)) == ADDR_VEC
2324 || GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
))
2328 if (barrier_align (next_real_insn (from
)) == CACHE_LOG
)
2330 /* We have just passed the barrier in front of the
2331 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2332 the ADDR_DIFF_VEC is accessed as data, just like our pool
2333 constants, this is a good opportunity to accommodate what
2334 we have gathered so far.
2335 If we waited any longer, we could end up at a barrier in
2336 front of code, which gives worse cache usage for separated
2337 instruction / data caches. */
2338 good_barrier
= found_barrier
;
2343 rtx body
= PATTERN (from
);
2344 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
2347 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2348 else if (GET_CODE (from
) == JUMP_INSN
2350 && ! TARGET_SMALLCODE
)
2356 if (new_align
> si_align
)
2358 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
2359 si_align
= new_align
;
2361 count_si
= (count_si
+ new_align
- 1) & -new_align
;
2366 if (new_align
> hi_align
)
2368 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
2369 hi_align
= new_align
;
2371 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
2373 from
= NEXT_INSN (from
);
2380 /* Try as we might, the leading mova is out of range. Change
2381 it into a load (which will become a pcload) and retry. */
2382 SET_SRC (PATTERN (mova
)) = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
2383 INSN_CODE (mova
) = -1;
2384 return find_barrier (0, 0, mova
);
2388 /* Insert the constant pool table before the mova instruction,
2389 to prevent the mova label reference from going out of range. */
2391 good_barrier
= found_barrier
= barrier_before_mova
;
2397 if (good_barrier
&& next_real_insn (found_barrier
))
2398 found_barrier
= good_barrier
;
2402 /* We didn't find a barrier in time to dump our stuff,
2403 so we'll make one. */
2404 rtx label
= gen_label_rtx ();
2406 /* If we exceeded the range, then we must back up over the last
2407 instruction we looked at. Otherwise, we just need to undo the
2408 NEXT_INSN at the end of the loop. */
2409 if (count_hi
> hi_limit
|| count_si
> si_limit
)
2410 from
= PREV_INSN (PREV_INSN (from
));
2412 from
= PREV_INSN (from
);
2414 /* Walk back to be just before any jump or label.
2415 Putting it before a label reduces the number of times the branch
2416 around the constant pool table will be hit. Putting it before
2417 a jump makes it more likely that the bra delay slot will be
2419 while (GET_CODE (from
) == JUMP_INSN
|| GET_CODE (from
) == NOTE
2420 || GET_CODE (from
) == CODE_LABEL
)
2421 from
= PREV_INSN (from
);
2423 from
= emit_jump_insn_after (gen_jump (label
), from
);
2424 JUMP_LABEL (from
) = label
;
2425 LABEL_NUSES (label
) = 1;
2426 found_barrier
= emit_barrier_after (from
);
2427 emit_label_after (label
, found_barrier
);
2430 return found_barrier
;
2433 /* If the instruction INSN is implemented by a special function, and we can
2434 positively find the register that is used to call the sfunc, and this
2435 register is not used anywhere else in this instruction - except as the
2436 destination of a set, return this register; else, return 0. */
2438 sfunc_uses_reg (insn
)
2442 rtx pattern
, part
, reg_part
, reg
;
2444 if (GET_CODE (insn
) != INSN
)
2446 pattern
= PATTERN (insn
);
2447 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
2450 for (reg_part
= 0, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2452 part
= XVECEXP (pattern
, 0, i
);
2453 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
2458 reg
= XEXP (reg_part
, 0);
2459 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2461 part
= XVECEXP (pattern
, 0, i
);
2462 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
2464 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
2465 && GET_CODE (SET_DEST (part
)) == REG
)
2466 ? SET_SRC (part
) : part
)))
2472 /* See if the only way in which INSN uses REG is by calling it, or by
2473 setting it while calling it. Set *SET to a SET rtx if the register
2477 noncall_uses_reg (reg
, insn
, set
)
2486 reg2
= sfunc_uses_reg (insn
);
2487 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
2489 pattern
= single_set (insn
);
2491 && GET_CODE (SET_DEST (pattern
)) == REG
2492 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2496 if (GET_CODE (insn
) != CALL_INSN
)
2498 /* We don't use rtx_equal_p because we don't care if the mode is
2500 pattern
= single_set (insn
);
2502 && GET_CODE (SET_DEST (pattern
)) == REG
2503 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2509 par
= PATTERN (insn
);
2510 if (GET_CODE (par
) == PARALLEL
)
2511 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
2513 part
= XVECEXP (par
, 0, i
);
2514 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
2517 return reg_mentioned_p (reg
, SET_SRC (pattern
));
2523 pattern
= PATTERN (insn
);
2525 if (GET_CODE (pattern
) == PARALLEL
)
2529 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2530 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
2532 pattern
= XVECEXP (pattern
, 0, 0);
2535 if (GET_CODE (pattern
) == SET
)
2537 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
2539 /* We don't use rtx_equal_p, because we don't care if the
2540 mode is different. */
2541 if (GET_CODE (SET_DEST (pattern
)) != REG
2542 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
2548 pattern
= SET_SRC (pattern
);
2551 if (GET_CODE (pattern
) != CALL
2552 || GET_CODE (XEXP (pattern
, 0)) != MEM
2553 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
2559 /* Given a X, a pattern of an insn or a part of it, return a mask of used
2560 general registers. Bits 0..15 mean that the respective registers
2561 are used as inputs in the instruction. Bits 16..31 mean that the
2562 registers 0..15, respectively, are used as outputs, or are clobbered.
2563 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
2565 regs_used (x
, is_dest
)
2574 code
= GET_CODE (x
);
2579 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2580 << (REGNO (x
) + is_dest
));
2584 rtx y
= SUBREG_REG (x
);
2586 if (GET_CODE (y
) != REG
)
2589 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2591 subreg_regno_offset (REGNO (y
),
2594 GET_MODE (x
)) + is_dest
));
2598 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
2600 /* If there was a return value, it must have been indicated with USE. */
2615 fmt
= GET_RTX_FORMAT (code
);
2617 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2622 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2623 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
2625 else if (fmt
[i
] == 'e')
2626 used
|= regs_used (XEXP (x
, i
), is_dest
);
2631 /* Create an instruction that prevents redirection of a conditional branch
2632 to the destination of the JUMP with address ADDR.
2633 If the branch needs to be implemented as an indirect jump, try to find
2634 a scratch register for it.
2635 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
2636 If any preceding insn that doesn't fit into a delay slot is good enough,
2637 pass 1. Pass 2 if a definite blocking insn is needed.
2638 -1 is used internally to avoid deep recursion.
2639 If a blocking instruction is made or recognized, return it. */
2642 gen_block_redirect (jump
, addr
, need_block
)
2644 int addr
, need_block
;
2647 rtx prev
= prev_nonnote_insn (jump
);
2650 /* First, check if we already have an instruction that satisfies our need. */
2651 if (prev
&& GET_CODE (prev
) == INSN
&& ! INSN_DELETED_P (prev
))
2653 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
2655 if (GET_CODE (PATTERN (prev
)) == USE
2656 || GET_CODE (PATTERN (prev
)) == CLOBBER
2657 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
2659 else if ((need_block
&= ~1) < 0)
2661 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
2664 /* We can't use JUMP_LABEL here because it might be undefined
2665 when not optimizing. */
2666 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
2667 /* If the branch is out of range, try to find a scratch register for it. */
2669 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ 4092U > 4092 + 4098))
2672 /* Don't look for the stack pointer as a scratch register,
2673 it would cause trouble if an interrupt occurred. */
2674 unsigned try = 0x7fff, used
;
2675 int jump_left
= flag_expensive_optimizations
+ 1;
2677 /* It is likely that the most recent eligible instruction is wanted for
2678 the delay slot. Therefore, find out which registers it uses, and
2679 try to avoid using them. */
2681 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
2685 if (INSN_DELETED_P (scan
))
2687 code
= GET_CODE (scan
);
2688 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
2691 && GET_CODE (PATTERN (scan
)) != USE
2692 && GET_CODE (PATTERN (scan
)) != CLOBBER
2693 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
2695 try &= ~regs_used (PATTERN (scan
), 0);
2699 for (used
= dead
= 0, scan
= JUMP_LABEL (jump
);
2700 (scan
= NEXT_INSN (scan
)); )
2704 if (INSN_DELETED_P (scan
))
2706 code
= GET_CODE (scan
);
2707 if (GET_RTX_CLASS (code
) == 'i')
2709 used
|= regs_used (PATTERN (scan
), 0);
2710 if (code
== CALL_INSN
)
2711 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
2712 dead
|= (used
>> 16) & ~used
;
2718 if (code
== JUMP_INSN
)
2720 if (jump_left
-- && simplejump_p (scan
))
2721 scan
= JUMP_LABEL (scan
);
2727 /* Mask out the stack pointer again, in case it was
2728 the only 'free' register we have found. */
2731 /* If the immediate destination is still in range, check for possible
2732 threading with a jump beyond the delay slot insn.
2733 Don't check if we are called recursively; the jump has been or will be
2734 checked in a different invocation then. */
2736 else if (optimize
&& need_block
>= 0)
2738 rtx next
= next_active_insn (next_active_insn (dest
));
2739 if (next
&& GET_CODE (next
) == JUMP_INSN
2740 && GET_CODE (PATTERN (next
)) == SET
2741 && recog_memoized (next
) == CODE_FOR_jump
)
2743 dest
= JUMP_LABEL (next
);
2745 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ 4092U
2747 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
2753 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
2755 /* It would be nice if we could convert the jump into an indirect
2756 jump / far branch right now, and thus exposing all constituent
2757 instructions to further optimization. However, reorg uses
2758 simplejump_p to determine if there is an unconditional jump where
2759 it should try to schedule instructions from the target of the
2760 branch; simplejump_p fails for indirect jumps even if they have
2762 rtx insn
= emit_insn_before (gen_indirect_jump_scratch
2763 (reg
, GEN_INT (INSN_UID (JUMP_LABEL (jump
))))
2765 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
2768 else if (need_block
)
2769 /* We can't use JUMP_LABEL here because it might be undefined
2770 when not optimizing. */
2771 return emit_insn_before (gen_block_branch_redirect
2772 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))))
2777 #define CONDJUMP_MIN -252
2778 #define CONDJUMP_MAX 262
2781 /* A label (to be placed) in front of the jump
2782 that jumps to our ultimate destination. */
2784 /* Where we are going to insert it if we cannot move the jump any farther,
2785 or the jump itself if we have picked up an existing jump. */
2787 /* The ultimate destination. */
2789 struct far_branch
*prev
;
2790 /* If the branch has already been created, its address;
2791 else the address of its first prospective user. */
2795 static void gen_far_branch
PARAMS ((struct far_branch
*));
2796 enum mdep_reorg_phase_e mdep_reorg_phase
;
2799 struct far_branch
*bp
;
2801 rtx insn
= bp
->insert_place
;
2803 rtx label
= gen_label_rtx ();
2805 emit_label_after (label
, insn
);
2808 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
2809 LABEL_NUSES (bp
->far_label
)++;
2812 jump
= emit_jump_insn_after (gen_return (), insn
);
2813 /* Emit a barrier so that reorg knows that any following instructions
2814 are not reachable via a fall-through path.
2815 But don't do this when not optimizing, since we wouldn't supress the
2816 alignment for the barrier then, and could end up with out-of-range
2817 pc-relative loads. */
2819 emit_barrier_after (jump
);
2820 emit_label_after (bp
->near_label
, insn
);
2821 JUMP_LABEL (jump
) = bp
->far_label
;
2822 if (! invert_jump (insn
, label
, 1))
2824 /* Prevent reorg from undoing our splits. */
2825 gen_block_redirect (jump
, bp
->address
+= 2, 2);
2828 /* Fix up ADDR_DIFF_VECs. */
2830 fixup_addr_diff_vecs (first
)
2835 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2837 rtx vec_lab
, pat
, prev
, prevpat
, x
, braf_label
;
2839 if (GET_CODE (insn
) != JUMP_INSN
2840 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
2842 pat
= PATTERN (insn
);
2843 vec_lab
= XEXP (XEXP (pat
, 0), 0);
2845 /* Search the matching casesi_jump_2. */
2846 for (prev
= vec_lab
; ; prev
= PREV_INSN (prev
))
2848 if (GET_CODE (prev
) != JUMP_INSN
)
2850 prevpat
= PATTERN (prev
);
2851 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
2853 x
= XVECEXP (prevpat
, 0, 1);
2854 if (GET_CODE (x
) != USE
)
2857 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
2861 /* Emit the reference label of the braf where it belongs, right after
2862 the casesi_jump_2 (i.e. braf). */
2863 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
2864 emit_label_after (braf_label
, prev
);
2866 /* Fix up the ADDR_DIF_VEC to be relative
2867 to the reference address of the braf. */
2868 XEXP (XEXP (pat
, 0), 0) = braf_label
;
2872 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
2873 a barrier. Return the base 2 logarithm of the desired alignment. */
2875 barrier_align (barrier_or_label
)
2876 rtx barrier_or_label
;
2878 rtx next
= next_real_insn (barrier_or_label
), pat
, prev
;
2879 int slot
, credit
, jump_to_next
;
2884 pat
= PATTERN (next
);
2886 if (GET_CODE (pat
) == ADDR_DIFF_VEC
)
2889 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
2890 /* This is a barrier in front of a constant table. */
2893 prev
= prev_real_insn (barrier_or_label
);
2894 if (GET_CODE (PATTERN (prev
)) == ADDR_DIFF_VEC
)
2896 pat
= PATTERN (prev
);
2897 /* If this is a very small table, we want to keep the alignment after
2898 the table to the minimum for proper code alignment. */
2899 return ((TARGET_SMALLCODE
2900 || (XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
2901 <= (unsigned)1 << (CACHE_LOG
- 2)))
2905 if (TARGET_SMALLCODE
)
2908 if (! TARGET_SH2
|| ! optimize
)
2911 /* When fixing up pcloads, a constant table might be inserted just before
2912 the basic block that ends with the barrier. Thus, we can't trust the
2913 instruction lengths before that. */
2914 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
2916 /* Check if there is an immediately preceding branch to the insn beyond
2917 the barrier. We must weight the cost of discarding useful information
2918 from the current cache line when executing this branch and there is
2919 an alignment, against that of fetching unneeded insn in front of the
2920 branch target when there is no alignment. */
2922 /* There are two delay_slot cases to consider. One is the simple case
2923 where the preceding branch is to the insn beyond the barrier (simple
2924 delay slot filling), and the other is where the preceding branch has
2925 a delay slot that is a duplicate of the insn after the barrier
2926 (fill_eager_delay_slots) and the branch is to the insn after the insn
2927 after the barrier. */
2929 /* PREV is presumed to be the JUMP_INSN for the barrier under
2930 investigation. Skip to the insn before it. */
2931 prev
= prev_real_insn (prev
);
2933 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
2934 credit
>= 0 && prev
&& GET_CODE (prev
) == INSN
;
2935 prev
= prev_real_insn (prev
))
2938 if (GET_CODE (PATTERN (prev
)) == USE
2939 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
2941 if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
2943 prev
= XVECEXP (PATTERN (prev
), 0, 1);
2944 if (INSN_UID (prev
) == INSN_UID (next
))
2946 /* Delay slot was filled with insn at jump target. */
2953 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
2955 credit
-= get_attr_length (prev
);
2958 && GET_CODE (prev
) == JUMP_INSN
2959 && JUMP_LABEL (prev
)
2960 && (jump_to_next
|| next_real_insn (JUMP_LABEL (prev
)) == next
2961 /* If relax_delay_slots() decides NEXT was redundant
2962 with some previous instruction, it will have
2963 redirected PREV's jump to the following insn. */
2964 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
2965 /* There is no upper bound on redundant instructions that
2966 might have been skipped, but we must not put an alignment
2967 where none had been before. */
2968 || (INSN_CODE (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
))))
2969 == CODE_FOR_block_branch_redirect
)
2970 || (INSN_CODE (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
))))
2971 == CODE_FOR_indirect_jump_scratch
)))
2973 rtx pat
= PATTERN (prev
);
2974 if (GET_CODE (pat
) == PARALLEL
)
2975 pat
= XVECEXP (pat
, 0, 0);
2976 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
2984 /* If we are inside a phony loop, almost any kind of label can turn up as the
2985 first one in the loop. Aligning a braf label causes incorrect switch
2986 destination addresses; we can detect braf labels because they are
2987 followed by a BARRIER.
2988 Applying loop alignment to small constant or switch tables is a waste
2989 of space, so we suppress this too. */
2991 sh_loop_align (label
)
2997 next
= next_nonnote_insn (next
);
2998 while (next
&& GET_CODE (next
) == CODE_LABEL
);
3002 || GET_CODE (PATTERN (next
)) == ADDR_DIFF_VEC
3003 || recog_memoized (next
) == CODE_FOR_consttable_2
)
3008 /* Exported to toplev.c.
3010 Do a final pass over the function, just before delayed branch
3014 machine_dependent_reorg (first
)
3019 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
3020 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
3022 /* We must split call insns before introducing `mova's. If we're
3023 optimizing, they'll have already been split. Otherwise, make
3024 sure we don't split them too late. */
3026 split_all_insns (0);
3028 /* If relaxing, generate pseudo-ops to associate function calls with
3029 the symbols they call. It does no harm to not generate these
3030 pseudo-ops. However, when we can generate them, it enables to
3031 linker to potentially relax the jsr to a bsr, and eliminate the
3032 register load and, possibly, the constant pool entry. */
3034 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
3037 /* Remove all REG_LABEL notes. We want to use them for our own
3038 purposes. This works because none of the remaining passes
3039 need to look at them.
3041 ??? But it may break in the future. We should use a machine
3042 dependent REG_NOTE, or some other approach entirely. */
3043 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3049 while ((note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
)) != 0)
3050 remove_note (insn
, note
);
3054 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3056 rtx pattern
, reg
, link
, set
, scan
, dies
, label
;
3057 int rescan
= 0, foundinsn
= 0;
3059 if (GET_CODE (insn
) == CALL_INSN
)
3061 pattern
= PATTERN (insn
);
3063 if (GET_CODE (pattern
) == PARALLEL
)
3064 pattern
= XVECEXP (pattern
, 0, 0);
3065 if (GET_CODE (pattern
) == SET
)
3066 pattern
= SET_SRC (pattern
);
3068 if (GET_CODE (pattern
) != CALL
3069 || GET_CODE (XEXP (pattern
, 0)) != MEM
)
3072 reg
= XEXP (XEXP (pattern
, 0), 0);
3076 reg
= sfunc_uses_reg (insn
);
3081 if (GET_CODE (reg
) != REG
)
3084 /* This is a function call via REG. If the only uses of REG
3085 between the time that it is set and the time that it dies
3086 are in function calls, then we can associate all the
3087 function calls with the setting of REG. */
3089 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
3091 if (REG_NOTE_KIND (link
) != 0)
3093 set
= single_set (XEXP (link
, 0));
3094 if (set
&& rtx_equal_p (reg
, SET_DEST (set
)))
3096 link
= XEXP (link
, 0);
3103 /* ??? Sometimes global register allocation will have
3104 deleted the insn pointed to by LOG_LINKS. Try
3105 scanning backward to find where the register is set. */
3106 for (scan
= PREV_INSN (insn
);
3107 scan
&& GET_CODE (scan
) != CODE_LABEL
;
3108 scan
= PREV_INSN (scan
))
3110 if (! INSN_P (scan
))
3113 if (! reg_mentioned_p (reg
, scan
))
3116 if (noncall_uses_reg (reg
, scan
, &set
))
3130 /* The register is set at LINK. */
3132 /* We can only optimize the function call if the register is
3133 being set to a symbol. In theory, we could sometimes
3134 optimize calls to a constant location, but the assembler
3135 and linker do not support that at present. */
3136 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
3137 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
3140 /* Scan forward from LINK to the place where REG dies, and
3141 make sure that the only insns which use REG are
3142 themselves function calls. */
3144 /* ??? This doesn't work for call targets that were allocated
3145 by reload, since there may not be a REG_DEAD note for the
3149 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
3153 /* Don't try to trace forward past a CODE_LABEL if we haven't
3154 seen INSN yet. Ordinarily, we will only find the setting insn
3155 in LOG_LINKS if it is in the same basic block. However,
3156 cross-jumping can insert code labels in between the load and
3157 the call, and can result in situations where a single call
3158 insn may have two targets depending on where we came from. */
3160 if (GET_CODE (scan
) == CODE_LABEL
&& ! foundinsn
)
3163 if (! INSN_P (scan
))
3166 /* Don't try to trace forward past a JUMP. To optimize
3167 safely, we would have to check that all the
3168 instructions at the jump destination did not use REG. */
3170 if (GET_CODE (scan
) == JUMP_INSN
)
3173 if (! reg_mentioned_p (reg
, scan
))
3176 if (noncall_uses_reg (reg
, scan
, &scanset
))
3183 && (GET_CODE (scan
) == CALL_INSN
|| sfunc_uses_reg (scan
)))
3185 /* There is a function call to this register other
3186 than the one we are checking. If we optimize
3187 this call, we need to rescan again below. */
3191 /* ??? We shouldn't have to worry about SCANSET here.
3192 We should just be able to check for a REG_DEAD note
3193 on a function call. However, the REG_DEAD notes are
3194 apparently not dependable around libcalls; c-torture
3195 execute/920501-2 is a test case. If SCANSET is set,
3196 then this insn sets the register, so it must have
3197 died earlier. Unfortunately, this will only handle
3198 the cases in which the register is, in fact, set in a
3201 /* ??? We shouldn't have to use FOUNDINSN here.
3202 However, the LOG_LINKS fields are apparently not
3203 entirely reliable around libcalls;
3204 newlib/libm/math/e_pow.c is a test case. Sometimes
3205 an insn will appear in LOG_LINKS even though it is
3206 not the most recent insn which sets the register. */
3210 || find_reg_note (scan
, REG_DEAD
, reg
)))
3219 /* Either there was a branch, or some insn used REG
3220 other than as a function call address. */
3224 /* Create a code label, and put it in a REG_LABEL note on
3225 the insn which sets the register, and on each call insn
3226 which uses the register. In final_prescan_insn we look
3227 for the REG_LABEL notes, and output the appropriate label
3230 label
= gen_label_rtx ();
3231 REG_NOTES (link
) = gen_rtx_EXPR_LIST (REG_LABEL
, label
,
3233 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_LABEL
, label
,
3242 scan
= NEXT_INSN (scan
);
3244 && ((GET_CODE (scan
) == CALL_INSN
3245 && reg_mentioned_p (reg
, scan
))
3246 || ((reg2
= sfunc_uses_reg (scan
))
3247 && REGNO (reg2
) == REGNO (reg
))))
3249 = gen_rtx_EXPR_LIST (REG_LABEL
, label
, REG_NOTES (scan
));
3251 while (scan
!= dies
);
3257 fixup_addr_diff_vecs (first
);
3261 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
3262 shorten_branches (first
);
3264 /* Scan the function looking for move instructions which have to be
3265 changed to pc-relative loads and insert the literal tables. */
3267 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
3268 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
3275 else if (GET_CODE (insn
) == JUMP_INSN
3276 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3284 /* Some code might have been inserted between the mova and
3285 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3286 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
3287 total
+= get_attr_length (scan
);
3289 /* range of mova is 1020, add 4 because pc counts from address of
3290 second instruction after this one, subtract 2 in case pc is 2
3291 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3292 cancels out with alignment effects of the mova itself. */
3295 /* Change the mova into a load, and restart scanning
3296 there. broken_move will then return true for mova. */
3297 SET_SRC (PATTERN (mova
))
3298 = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
3299 INSN_CODE (mova
) = -1;
3303 if (broken_move (insn
))
3306 /* Scan ahead looking for a barrier to stick the constant table
3308 rtx barrier
= find_barrier (num_mova
, mova
, insn
);
3309 rtx last_float_move
, last_float
= 0, *last_float_addr
;
3311 if (num_mova
&& ! mova_p (mova
))
3313 /* find_barrier had to change the first mova into a
3314 pcload; thus, we have to start with this new pcload. */
3318 /* Now find all the moves between the points and modify them. */
3319 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
3321 if (GET_CODE (scan
) == CODE_LABEL
)
3323 if (broken_move (scan
))
3325 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
3329 enum machine_mode mode
;
3331 if (GET_CODE (pat
) == PARALLEL
)
3332 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
3333 src
= SET_SRC (pat
);
3334 dst
= SET_DEST (pat
);
3335 mode
= GET_MODE (dst
);
3337 if (mode
== SImode
&& hi_const (src
)
3338 && REGNO (dst
) != FPUL_REG
)
3343 while (GET_CODE (dst
) == SUBREG
)
3345 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
3346 GET_MODE (SUBREG_REG (dst
)),
3349 dst
= SUBREG_REG (dst
);
3351 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
3354 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
3356 /* This must be an insn that clobbers r0. */
3357 rtx clobber
= XVECEXP (PATTERN (scan
), 0,
3358 XVECLEN (PATTERN (scan
), 0) - 1);
3360 if (GET_CODE (clobber
) != CLOBBER
3361 || ! rtx_equal_p (XEXP (clobber
, 0), r0_rtx
))
3365 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
3367 lab
= add_constant (src
, mode
, last_float
);
3369 emit_insn_before (gen_mova (lab
), scan
);
3372 /* There will be a REG_UNUSED note for r0 on
3373 LAST_FLOAT_MOVE; we have to change it to REG_INC,
3374 lest reorg:mark_target_live_regs will not
3375 consider r0 to be used, and we end up with delay
3376 slot insn in front of SCAN that clobbers r0. */
3378 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
3380 /* If we are not optimizing, then there may not be
3383 PUT_MODE (note
, REG_INC
);
3385 *last_float_addr
= r0_inc_rtx
;
3387 last_float_move
= scan
;
3389 newsrc
= gen_rtx (MEM
, mode
,
3390 (((TARGET_SH4
&& ! TARGET_FMOVD
)
3391 || REGNO (dst
) == FPUL_REG
)
3394 last_float_addr
= &XEXP (newsrc
, 0);
3396 /* Remove the clobber of r0. */
3397 XEXP (clobber
, 0) = gen_rtx_SCRATCH (Pmode
);
3399 /* This is a mova needing a label. Create it. */
3400 else if (GET_CODE (src
) == UNSPEC
3401 && XINT (src
, 1) == UNSPEC_MOVA
3402 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
3404 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
3405 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
3406 newsrc
= gen_rtx_UNSPEC (VOIDmode
,
3407 gen_rtvec (1, newsrc
),
3412 lab
= add_constant (src
, mode
, 0);
3413 newsrc
= gen_rtx_MEM (mode
,
3414 gen_rtx_LABEL_REF (VOIDmode
, lab
));
3416 RTX_UNCHANGING_P (newsrc
) = 1;
3417 *patp
= gen_rtx_SET (VOIDmode
, dst
, newsrc
);
3418 INSN_CODE (scan
) = -1;
3421 dump_table (barrier
);
3426 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
3427 INSN_ADDRESSES_FREE ();
3428 split_branches (first
);
3430 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
3431 also has an effect on the register that holds the addres of the sfunc.
3432 Insert an extra dummy insn in front of each sfunc that pretends to
3433 use this register. */
3434 if (flag_delayed_branch
)
3436 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3438 rtx reg
= sfunc_uses_reg (insn
);
3442 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
3446 /* fpscr is not actually a user variable, but we pretend it is for the
3447 sake of the previous optimization passes, since we want it handled like
3448 one. However, we don't have any debugging information for it, so turn
3449 it into a non-user variable now. */
3451 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
3453 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
3457 get_dest_uid (label
, max_uid
)
3461 rtx dest
= next_real_insn (label
);
3464 /* This can happen for an undefined label. */
3466 dest_uid
= INSN_UID (dest
);
3467 /* If this is a newly created branch redirection blocking instruction,
3468 we cannot index the branch_uid or insn_addresses arrays with its
3469 uid. But then, we won't need to, because the actual destination is
3470 the following branch. */
3471 while (dest_uid
>= max_uid
)
3473 dest
= NEXT_INSN (dest
);
3474 dest_uid
= INSN_UID (dest
);
3476 if (GET_CODE (dest
) == JUMP_INSN
&& GET_CODE (PATTERN (dest
)) == RETURN
)
3481 /* Split condbranches that are out of range. Also add clobbers for
3482 scratch registers that are needed in far jumps.
3483 We do this before delay slot scheduling, so that it can take our
3484 newly created instructions into account. It also allows us to
3485 find branches with common targets more easily. */
3488 split_branches (first
)
3492 struct far_branch
**uid_branch
, *far_branch_list
= 0;
3493 int max_uid
= get_max_uid ();
3495 /* Find out which branches are out of range. */
3496 shorten_branches (first
);
3498 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
3499 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
3501 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3502 if (! INSN_P (insn
))
3504 else if (INSN_DELETED_P (insn
))
3506 /* Shorten_branches would split this instruction again,
3507 so transform it into a note. */
3508 PUT_CODE (insn
, NOTE
);
3509 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
3510 NOTE_SOURCE_FILE (insn
) = 0;
3512 else if (GET_CODE (insn
) == JUMP_INSN
3513 /* Don't mess with ADDR_DIFF_VEC */
3514 && (GET_CODE (PATTERN (insn
)) == SET
3515 || GET_CODE (PATTERN (insn
)) == RETURN
))
3517 enum attr_type type
= get_attr_type (insn
);
3518 if (type
== TYPE_CBRANCH
)
3522 if (get_attr_length (insn
) > 4)
3524 rtx src
= SET_SRC (PATTERN (insn
));
3525 rtx olabel
= XEXP (XEXP (src
, 1), 0);
3526 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
3528 int dest_uid
= get_dest_uid (olabel
, max_uid
);
3529 struct far_branch
*bp
= uid_branch
[dest_uid
];
3531 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
3532 the label if the LABEL_NUSES count drops to zero. There is
3533 always a jump_optimize pass that sets these values, but it
3534 proceeds to delete unreferenced code, and then if not
3535 optimizing, to un-delete the deleted instructions, thus
3536 leaving labels with too low uses counts. */
3539 JUMP_LABEL (insn
) = olabel
;
3540 LABEL_NUSES (olabel
)++;
3544 bp
= (struct far_branch
*) alloca (sizeof *bp
);
3545 uid_branch
[dest_uid
] = bp
;
3546 bp
->prev
= far_branch_list
;
3547 far_branch_list
= bp
;
3549 = XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1), 0);
3550 LABEL_NUSES (bp
->far_label
)++;
3554 label
= bp
->near_label
;
3555 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
3557 rtx block
= bp
->insert_place
;
3559 if (GET_CODE (PATTERN (block
)) == RETURN
)
3560 block
= PREV_INSN (block
);
3562 block
= gen_block_redirect (block
,
3564 label
= emit_label_after (gen_label_rtx (),
3566 bp
->near_label
= label
;
3568 else if (label
&& ! NEXT_INSN (label
))
3570 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
3571 bp
->insert_place
= insn
;
3573 gen_far_branch (bp
);
3577 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
3579 bp
->near_label
= label
= gen_label_rtx ();
3580 bp
->insert_place
= insn
;
3583 if (! redirect_jump (insn
, label
, 1))
3588 /* get_attr_length (insn) == 2 */
3589 /* Check if we have a pattern where reorg wants to redirect
3590 the branch to a label from an unconditional branch that
3592 /* We can't use JUMP_LABEL here because it might be undefined
3593 when not optimizing. */
3594 /* A syntax error might cause beyond to be NULL_RTX. */
3596 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
3600 && (GET_CODE (beyond
) == JUMP_INSN
3601 || ((beyond
= next_active_insn (beyond
))
3602 && GET_CODE (beyond
) == JUMP_INSN
))
3603 && GET_CODE (PATTERN (beyond
)) == SET
3604 && recog_memoized (beyond
) == CODE_FOR_jump
3606 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
3607 - INSN_ADDRESSES (INSN_UID (insn
)) + 252U)
3609 gen_block_redirect (beyond
,
3610 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
3613 next
= next_active_insn (insn
);
3615 if ((GET_CODE (next
) == JUMP_INSN
3616 || GET_CODE (next
= next_active_insn (next
)) == JUMP_INSN
)
3617 && GET_CODE (PATTERN (next
)) == SET
3618 && recog_memoized (next
) == CODE_FOR_jump
3620 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
3621 - INSN_ADDRESSES (INSN_UID (insn
)) + 252U)
3623 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
3625 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
3627 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
3630 struct far_branch
*bp
;
3632 if (type
== TYPE_JUMP
)
3634 far_label
= XEXP (SET_SRC (PATTERN (insn
)), 0);
3635 dest_uid
= get_dest_uid (far_label
, max_uid
);
3638 /* Parse errors can lead to labels outside
3640 if (! NEXT_INSN (far_label
))
3645 JUMP_LABEL (insn
) = far_label
;
3646 LABEL_NUSES (far_label
)++;
3648 redirect_jump (insn
, NULL_RTX
, 1);
3652 bp
= uid_branch
[dest_uid
];
3655 bp
= (struct far_branch
*) alloca (sizeof *bp
);
3656 uid_branch
[dest_uid
] = bp
;
3657 bp
->prev
= far_branch_list
;
3658 far_branch_list
= bp
;
3660 bp
->far_label
= far_label
;
3662 LABEL_NUSES (far_label
)++;
3664 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
3665 if (addr
- bp
->address
<= CONDJUMP_MAX
)
3666 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
3669 gen_far_branch (bp
);
3675 bp
->insert_place
= insn
;
3677 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
3679 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
3682 /* Generate all pending far branches,
3683 and free our references to the far labels. */
3684 while (far_branch_list
)
3686 if (far_branch_list
->near_label
3687 && ! NEXT_INSN (far_branch_list
->near_label
))
3688 gen_far_branch (far_branch_list
);
3690 && far_branch_list
->far_label
3691 && ! --LABEL_NUSES (far_branch_list
->far_label
))
3692 delete_insn (far_branch_list
->far_label
);
3693 far_branch_list
= far_branch_list
->prev
;
3696 /* Instruction length information is no longer valid due to the new
3697 instructions that have been generated. */
3698 init_insn_lengths ();
3701 /* Dump out instruction addresses, which is useful for debugging the
3702 constant pool table stuff.
3704 If relaxing, output the label and pseudo-ops used to link together
3705 calls and the instruction which set the registers. */
3707 /* ??? This is unnecessary, and probably should be deleted. This makes
3708 the insn_addresses declaration above unnecessary. */
3710 /* ??? The addresses printed by this routine for insns are nonsense for
3711 insns which are inside of a sequence where none of the inner insns have
3712 variable length. This is because the second pass of shorten_branches
3713 does not bother to update them. */
3716 final_prescan_insn (insn
, opvec
, noperands
)
3718 rtx
*opvec ATTRIBUTE_UNUSED
;
3719 int noperands ATTRIBUTE_UNUSED
;
3721 if (TARGET_DUMPISIZE
)
3722 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
3728 note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
);
3733 pattern
= PATTERN (insn
);
3734 if (GET_CODE (pattern
) == PARALLEL
)
3735 pattern
= XVECEXP (pattern
, 0, 0);
3736 if (GET_CODE (pattern
) == CALL
3737 || (GET_CODE (pattern
) == SET
3738 && (GET_CODE (SET_SRC (pattern
)) == CALL
3739 || get_attr_type (insn
) == TYPE_SFUNC
)))
3740 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
3741 CODE_LABEL_NUMBER (XEXP (note
, 0)));
3742 else if (GET_CODE (pattern
) == SET
)
3743 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
3744 CODE_LABEL_NUMBER (XEXP (note
, 0)));
3751 /* Dump out any constants accumulated in the final pass. These will
3755 output_jump_label_table ()
3761 fprintf (asm_out_file
, "\t.align 2\n");
3762 for (i
= 0; i
< pool_size
; i
++)
3764 pool_node
*p
= &pool_vector
[i
];
3766 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
3767 CODE_LABEL_NUMBER (p
->label
));
3768 output_asm_insn (".long %O0", &p
->value
);
3776 /* A full frame looks like:
3780 [ if current_function_anonymous_args
3793 local-0 <- fp points here. */
3795 /* Number of bytes pushed for anonymous args, used to pass information
3796 between expand_prologue and expand_epilogue. */
3798 static int extra_push
;
3800 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
3801 to be adjusted, and TEMP, if nonnegative, holds the register number
3802 of a general register that we may clobber. */
3805 output_stack_adjust (size
, reg
, temp
)
3812 if (CONST_OK_FOR_I (size
))
3813 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
3814 /* Try to do it with two partial adjustments; however, we must make
3815 sure that the stack is properly aligned at all times, in case
3816 an interrupt occurs between the two partial adjustments. */
3817 else if (CONST_OK_FOR_I (size
/ 2 & -4)
3818 && CONST_OK_FOR_I (size
- (size
/ 2 & -4)))
3820 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
/ 2 & -4)));
3821 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -4))));
3827 /* If TEMP is invalid, we could temporarily save a general
3828 register to MACL. However, there is currently no need
3829 to handle this case, so just abort when we see it. */
3832 const_reg
= gen_rtx_REG (SImode
, temp
);
3834 /* If SIZE is negative, subtract the positive value.
3835 This sometimes allows a constant pool entry to be shared
3836 between prologue and epilogue code. */
3839 emit_insn (gen_movsi (const_reg
, GEN_INT (-size
)));
3840 emit_insn (gen_subsi3 (reg
, reg
, const_reg
));
3844 emit_insn (gen_movsi (const_reg
, GEN_INT (size
)));
3845 emit_insn (gen_addsi3 (reg
, reg
, const_reg
));
3851 /* Output RTL to push register RN onto the stack. */
3859 x
= gen_push_fpul ();
3860 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
3861 && FP_OR_XD_REGISTER_P (rn
))
3863 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
3865 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
3867 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
3868 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
3870 x
= gen_push (gen_rtx_REG (SImode
, rn
));
3874 = gen_rtx_EXPR_LIST (REG_INC
,
3875 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
3878 /* Output RTL to pop register RN from the stack. */
3886 x
= gen_pop_fpul ();
3887 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
3888 && FP_OR_XD_REGISTER_P (rn
))
3890 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
3892 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
3894 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
3895 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
3897 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
3901 = gen_rtx_EXPR_LIST (REG_INC
,
3902 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
3905 /* Generate code to push the regs specified in the mask. */
3908 push_regs (mask
, mask2
)
3913 /* Push PR last; this gives better latencies after the prologue, and
3914 candidates for the return delay slot when there are no general
3915 registers pushed. */
3916 for (i
= 0; i
< 32; i
++)
3917 if (mask
& (1 << i
) && i
!= PR_REG
)
3919 for (i
= 32; i
< FIRST_PSEUDO_REGISTER
; i
++)
3920 if (mask2
& (1 << (i
- 32)))
3922 if (mask
& (1 << PR_REG
))
3926 /* Work out the registers which need to be saved, both as a mask and a
3927 count of saved words.
3929 If doing a pragma interrupt function, then push all regs used by the
3930 function, and if we call another function (we can tell by looking at PR),
3931 make sure that all the regs it clobbers are safe too. */
3934 calc_live_regs (count_ptr
, live_regs_mask2
)
3936 int *live_regs_mask2
;
3939 int live_regs_mask
= 0;
3941 int interrupt_handler
;
3943 if ((lookup_attribute
3944 ("interrupt_handler",
3945 DECL_MACHINE_ATTRIBUTES (current_function_decl
)))
3947 interrupt_handler
= 1;
3949 interrupt_handler
= 0;
3951 *live_regs_mask2
= 0;
3952 /* If we can save a lot of saves by switching to double mode, do that. */
3953 if (TARGET_SH4
&& TARGET_FMOVD
&& TARGET_FPU_SINGLE
)
3954 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
3955 if (regs_ever_live
[reg
] && regs_ever_live
[reg
+1]
3956 && (! call_used_regs
[reg
] || (interrupt_handler
&& ! pragma_trapa
))
3959 target_flags
&= ~FPU_SINGLE_BIT
;
3962 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
- 1; reg
>= 0; reg
--)
3964 if ((interrupt_handler
&& ! pragma_trapa
)
3965 ? (/* Need to save all the regs ever live. */
3966 (regs_ever_live
[reg
]
3967 || (call_used_regs
[reg
]
3968 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
)
3969 && regs_ever_live
[PR_REG
]))
3970 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
3971 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
3972 && reg
!= T_REG
&& reg
!= GBR_REG
&& reg
!= FPSCR_REG
)
3973 : (/* Only push those regs which are used and need to be saved. */
3974 regs_ever_live
[reg
] && ! call_used_regs
[reg
]))
3977 *live_regs_mask2
|= 1 << (reg
- 32);
3979 live_regs_mask
|= 1 << reg
;
3981 if (TARGET_SH4
&& TARGET_FMOVD
&& FP_OR_XD_REGISTER_P (reg
))
3983 if (FP_REGISTER_P (reg
))
3985 if (! TARGET_FPU_SINGLE
&& ! regs_ever_live
[reg
^ 1])
3988 *live_regs_mask2
|= 1 << ((reg
^ 1) - 32);
3990 live_regs_mask
|= 1 << (reg
^ 1);
3994 else /* if (XD_REGISTER_P (reg)) */
3996 /* Must switch to double mode to access these registers. */
3997 target_flags
&= ~FPU_SINGLE_BIT
;
4004 *count_ptr
= count
* UNITS_PER_WORD
;
4005 return live_regs_mask
;
4008 /* Code to generate prologue and epilogue sequences */
4010 /* PUSHED is the number of bytes that are bing pushed on the
4011 stack for register saves. Return the frame size, padded
4012 appropriately so that the stack stays properly aligned. */
4013 static HOST_WIDE_INT
4014 rounded_frame_size (pushed
)
4017 HOST_WIDE_INT size
= get_frame_size ();
4018 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4020 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
4024 sh_expand_prologue ()
4028 int live_regs_mask2
;
4029 int save_flags
= target_flags
;
4031 current_function_interrupt
4032 = lookup_attribute ("interrupt_handler",
4033 DECL_MACHINE_ATTRIBUTES (current_function_decl
))
4036 /* We have pretend args if we had an object sent partially in registers
4037 and partially on the stack, e.g. a large structure. */
4038 output_stack_adjust (-current_function_pretend_args_size
,
4039 stack_pointer_rtx
, 1);
4043 /* This is set by SETUP_VARARGS to indicate that this is a varargs
4044 routine. Clear it here so that the next function isn't affected. */
4045 if (current_function_anonymous_args
)
4047 current_function_anonymous_args
= 0;
4049 /* This is not used by the SH3E calling convention */
4050 if (! TARGET_SH3E
&& ! TARGET_HITACHI
)
4052 /* Push arg regs as if they'd been provided by caller in stack. */
4053 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
4055 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
4056 if (i
>= (NPARM_REGS(SImode
)
4057 - current_function_args_info
.arg_count
[(int) SH_ARG_INT
]
4066 /* If we're supposed to switch stacks at function entry, do so now. */
4068 emit_insn (gen_sp_switch_1 ());
4070 live_regs_mask
= calc_live_regs (&d
, &live_regs_mask2
);
4071 /* ??? Maybe we could save some switching if we can move a mode switch
4072 that already happens to be at the function start into the prologue. */
4073 if (target_flags
!= save_flags
)
4074 emit_insn (gen_toggle_sz ());
4076 push_regs (live_regs_mask
, live_regs_mask2
);
4078 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
4080 rtx insn
= get_last_insn ();
4081 rtx last
= emit_insn (gen_GOTaddr2picreg ());
4083 /* Mark these insns as possibly dead. Sometimes, flow2 may
4084 delete all uses of the PIC register. In this case, let it
4085 delete the initialization too. */
4088 insn
= NEXT_INSN (insn
);
4090 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4094 while (insn
!= last
);
4097 if (target_flags
!= save_flags
)
4099 rtx insn
= emit_insn (gen_toggle_sz ());
4101 /* If we're lucky, a mode switch in the function body will
4102 overwrite fpscr, turning this insn dead. Tell flow this
4103 insn is ok to delete. */
4104 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4109 target_flags
= save_flags
;
4111 output_stack_adjust (-rounded_frame_size (d
),
4112 stack_pointer_rtx
, 1);
4114 if (frame_pointer_needed
)
4115 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
4119 sh_expand_epilogue ()
4124 int live_regs_mask2
;
4125 int save_flags
= target_flags
;
4128 live_regs_mask
= calc_live_regs (&d
, &live_regs_mask2
);
4130 frame_size
= rounded_frame_size (d
);
4132 if (frame_pointer_needed
)
4134 output_stack_adjust (frame_size
, frame_pointer_rtx
, 7);
4136 /* We must avoid moving the stack pointer adjustment past code
4137 which reads from the local frame, else an interrupt could
4138 occur after the SP adjustment and clobber data in the local
4140 emit_insn (gen_blockage ());
4141 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
4143 else if (frame_size
)
4145 /* We must avoid moving the stack pointer adjustment past code
4146 which reads from the local frame, else an interrupt could
4147 occur after the SP adjustment and clobber data in the local
4149 emit_insn (gen_blockage ());
4150 output_stack_adjust (frame_size
, stack_pointer_rtx
, 7);
4153 /* Pop all the registers. */
4155 if (target_flags
!= save_flags
)
4156 emit_insn (gen_toggle_sz ());
4157 if (live_regs_mask
& (1 << PR_REG
))
4159 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4161 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
4162 if (j
< 32 && (live_regs_mask
& (1 << j
)) && j
!= PR_REG
)
4164 else if (j
>= 32 && (live_regs_mask2
& (1 << (j
- 32))))
4167 if (target_flags
!= save_flags
)
4168 emit_insn (gen_toggle_sz ());
4169 target_flags
= save_flags
;
4171 output_stack_adjust (extra_push
+ current_function_pretend_args_size
,
4172 stack_pointer_rtx
, 7);
4174 /* Switch back to the normal stack if necessary. */
4176 emit_insn (gen_sp_switch_2 ());
4178 /* Tell flow the insn that pops PR isn't dead. */
4179 if (live_regs_mask
& (1 << PR_REG
))
4180 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, PR_REG
)));
4183 static int sh_need_epilogue_known
= 0;
4188 if (! sh_need_epilogue_known
)
4193 sh_expand_epilogue ();
4194 epilogue
= gen_sequence ();
4196 sh_need_epilogue_known
4197 = (GET_CODE (epilogue
) == SEQUENCE
&& XVECLEN (epilogue
, 0) == 0
4200 return sh_need_epilogue_known
> 0;
4203 /* Clear variables at function end. */
4206 sh_output_function_epilogue (file
, size
)
4207 FILE *file ATTRIBUTE_UNUSED
;
4208 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
4210 trap_exit
= pragma_interrupt
= pragma_trapa
= pragma_nosave_low_regs
= 0;
4211 sh_need_epilogue_known
= 0;
4212 sp_switch
= NULL_RTX
;
4216 sh_builtin_saveregs ()
4218 /* First unnamed integer register. */
4219 int first_intreg
= current_function_args_info
.arg_count
[(int) SH_ARG_INT
];
4220 /* Number of integer registers we need to save. */
4221 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
4222 /* First unnamed SFmode float reg */
4223 int first_floatreg
= current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
4224 /* Number of SFmode float regs to save. */
4225 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
4227 int bufsize
, regno
, alias_set
;
4229 /* Allocate block of memory for the regs. */
4230 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
4231 Or can assign_stack_local accept a 0 SIZE argument? */
4232 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
4234 regbuf
= assign_stack_local (BLKmode
, bufsize
, 0);
4235 alias_set
= get_varargs_alias_set ();
4236 MEM_ALIAS_SET (regbuf
) = alias_set
;
4239 This is optimized to only save the regs that are necessary. Explicitly
4240 named args need not be saved. */
4242 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
4243 adjust_address (regbuf
, BLKmode
,
4244 n_floatregs
* UNITS_PER_WORD
),
4245 n_intregs
, n_intregs
* UNITS_PER_WORD
);
4248 This is optimized to only save the regs that are necessary. Explicitly
4249 named args need not be saved.
4250 We explicitly build a pointer to the buffer because it halves the insn
4251 count when not optimizing (otherwise the pointer is built for each reg
4253 We emit the moves in reverse order so that we can use predecrement. */
4255 fpregs
= gen_reg_rtx (Pmode
);
4256 emit_move_insn (fpregs
, XEXP (regbuf
, 0));
4257 emit_insn (gen_addsi3 (fpregs
, fpregs
,
4258 GEN_INT (n_floatregs
* UNITS_PER_WORD
)));
4262 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
4264 emit_insn (gen_addsi3 (fpregs
, fpregs
,
4265 GEN_INT (-2 * UNITS_PER_WORD
)));
4266 mem
= gen_rtx_MEM (DFmode
, fpregs
);
4267 MEM_ALIAS_SET (mem
) = alias_set
;
4268 emit_move_insn (mem
,
4269 gen_rtx (REG
, DFmode
, BASE_ARG_REG (DFmode
) + regno
));
4271 regno
= first_floatreg
;
4274 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
4275 mem
= gen_rtx_MEM (SFmode
, fpregs
);
4276 MEM_ALIAS_SET (mem
) = alias_set
;
4277 emit_move_insn (mem
,
4278 gen_rtx (REG
, SFmode
, BASE_ARG_REG (SFmode
) + regno
4279 - (TARGET_LITTLE_ENDIAN
!= 0)));
4283 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
4286 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
4287 mem
= gen_rtx_MEM (SFmode
, fpregs
);
4288 MEM_ALIAS_SET (mem
) = alias_set
;
4289 emit_move_insn (mem
,
4290 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
4293 /* Return the address of the regbuf. */
4294 return XEXP (regbuf
, 0);
4297 /* Define the `__builtin_va_list' type for the ABI. */
4302 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
4305 if ((! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
4306 return ptr_type_node
;
4308 record
= make_node (RECORD_TYPE
);
4310 f_next_o
= build_decl (FIELD_DECL
, get_identifier ("__va_next_o"),
4312 f_next_o_limit
= build_decl (FIELD_DECL
,
4313 get_identifier ("__va_next_o_limit"),
4315 f_next_fp
= build_decl (FIELD_DECL
, get_identifier ("__va_next_fp"),
4317 f_next_fp_limit
= build_decl (FIELD_DECL
,
4318 get_identifier ("__va_next_fp_limit"),
4320 f_next_stack
= build_decl (FIELD_DECL
, get_identifier ("__va_next_stack"),
4323 DECL_FIELD_CONTEXT (f_next_o
) = record
;
4324 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
4325 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
4326 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
4327 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
4329 TYPE_FIELDS (record
) = f_next_o
;
4330 TREE_CHAIN (f_next_o
) = f_next_o_limit
;
4331 TREE_CHAIN (f_next_o_limit
) = f_next_fp
;
4332 TREE_CHAIN (f_next_fp
) = f_next_fp_limit
;
4333 TREE_CHAIN (f_next_fp_limit
) = f_next_stack
;
4335 layout_type (record
);
4340 /* Implement `va_start' for varargs and stdarg. */
4343 sh_va_start (stdarg_p
, valist
, nextarg
)
4348 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
4349 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
4353 if ((! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
4355 std_expand_builtin_va_start (stdarg_p
, valist
, nextarg
);
4359 f_next_o
= TYPE_FIELDS (va_list_type_node
);
4360 f_next_o_limit
= TREE_CHAIN (f_next_o
);
4361 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
4362 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
4363 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
4365 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
4366 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
4367 valist
, f_next_o_limit
);
4368 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
);
4369 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
4370 valist
, f_next_fp_limit
);
4371 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
4372 valist
, f_next_stack
);
4374 /* Call __builtin_saveregs. */
4375 u
= make_tree (ptr_type_node
, expand_builtin_saveregs ());
4376 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
4377 TREE_SIDE_EFFECTS (t
) = 1;
4378 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4380 nfp
= current_function_args_info
.arg_count
[SH_ARG_FLOAT
];
4385 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
4386 build_int_2 (UNITS_PER_WORD
* nfp
, 0)));
4387 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
4388 TREE_SIDE_EFFECTS (t
) = 1;
4389 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4391 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
4392 TREE_SIDE_EFFECTS (t
) = 1;
4393 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4395 nint
= current_function_args_info
.arg_count
[SH_ARG_INT
];
4400 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
4401 build_int_2 (UNITS_PER_WORD
* nint
, 0)));
4402 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
4403 TREE_SIDE_EFFECTS (t
) = 1;
4404 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4406 u
= make_tree (ptr_type_node
, nextarg
);
4407 if (! stdarg_p
&& (nint
== 0 || nfp
== 0))
4409 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
4410 build_int_2 (-UNITS_PER_WORD
, -1)));
4412 t
= build (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
4413 TREE_SIDE_EFFECTS (t
) = 1;
4414 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4417 /* Implement `va_arg'. */
4420 sh_va_arg (valist
, type
)
4423 HOST_WIDE_INT size
, rsize
;
4424 tree tmp
, pptr_type_node
;
4427 size
= int_size_in_bytes (type
);
4428 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
4429 pptr_type_node
= build_pointer_type (ptr_type_node
);
4431 if ((TARGET_SH3E
|| TARGET_SH4
) && ! TARGET_HITACHI
)
4433 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
4434 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
4436 rtx lab_false
, lab_over
;
4438 f_next_o
= TYPE_FIELDS (va_list_type_node
);
4439 f_next_o_limit
= TREE_CHAIN (f_next_o
);
4440 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
4441 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
4442 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
4444 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
4445 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
4446 valist
, f_next_o_limit
);
4447 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
4449 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
4450 valist
, f_next_fp_limit
);
4451 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
4452 valist
, f_next_stack
);
4456 pass_as_float
= ((TREE_CODE (type
) == REAL_TYPE
&& size
<= 8)
4457 || (TREE_CODE (type
) == COMPLEX_TYPE
4458 && TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
4463 pass_as_float
= (TREE_CODE (type
) == REAL_TYPE
&& size
== 4);
4466 addr_rtx
= gen_reg_rtx (Pmode
);
4467 lab_false
= gen_label_rtx ();
4468 lab_over
= gen_label_rtx ();
4472 emit_cmp_and_jump_insns (expand_expr (next_fp
, NULL_RTX
, Pmode
,
4474 expand_expr (next_fp_limit
, NULL_RTX
,
4475 Pmode
, EXPAND_NORMAL
),
4476 GE
, const1_rtx
, Pmode
, 1, 1, lab_false
);
4478 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
4480 tmp
= build (BIT_AND_EXPR
, ptr_type_node
, next_fp
,
4481 build_int_2 (UNITS_PER_WORD
, 0));
4482 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_fp
, tmp
);
4483 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, tmp
);
4484 TREE_SIDE_EFFECTS (tmp
) = 1;
4485 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4488 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_fp
);
4489 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4491 emit_move_insn (addr_rtx
, r
);
4493 emit_jump_insn (gen_jump (lab_over
));
4495 emit_label (lab_false
);
4497 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
4498 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4500 emit_move_insn (addr_rtx
, r
);
4504 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_o
,
4505 build_int_2 (rsize
, 0));
4507 emit_cmp_and_jump_insns (expand_expr (tmp
, NULL_RTX
, Pmode
,
4509 expand_expr (next_o_limit
, NULL_RTX
,
4510 Pmode
, EXPAND_NORMAL
),
4511 GT
, const1_rtx
, Pmode
, 1, 1, lab_false
);
4513 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_o
);
4514 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4516 emit_move_insn (addr_rtx
, r
);
4518 emit_jump_insn (gen_jump (lab_over
));
4520 emit_label (lab_false
);
4522 if (size
> 4 && ! TARGET_SH4
)
4524 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, next_o_limit
);
4525 TREE_SIDE_EFFECTS (tmp
) = 1;
4526 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
4529 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
4530 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
4532 emit_move_insn (addr_rtx
, r
);
4535 emit_label (lab_over
);
4537 tmp
= make_tree (pptr_type_node
, addr_rtx
);
4538 valist
= build1 (INDIRECT_REF
, ptr_type_node
, tmp
);
4541 /* ??? In va-sh.h, there had been code to make values larger than
4542 size 8 indirect. This does not match the FUNCTION_ARG macros. */
4544 return std_expand_builtin_va_arg (valist
, type
);
4547 /* Define the offset between two registers, one to be eliminated, and
4548 the other its replacement, at the start of a routine. */
4551 initial_elimination_offset (from
, to
)
4556 int total_saved_regs_space
;
4557 int total_auto_space
;
4558 int save_flags
= target_flags
;
4560 int live_regs_mask
, live_regs_mask2
;
4561 live_regs_mask
= calc_live_regs (®s_saved
, &live_regs_mask2
);
4562 total_auto_space
= rounded_frame_size (regs_saved
);
4563 target_flags
= save_flags
;
4565 total_saved_regs_space
= regs_saved
;
4567 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
4568 return total_saved_regs_space
+ total_auto_space
;
4570 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
4571 return total_saved_regs_space
+ total_auto_space
;
4573 /* Initial gap between fp and sp is 0. */
4574 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
4577 if (from
== RETURN_ADDRESS_POINTER_REGNUM
4578 && (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
))
4579 return UNITS_PER_WORD
+ total_auto_space
;
4584 /* Handle machine specific pragmas to be semi-compatible with Hitachi
4588 sh_pr_interrupt (pfile
)
4589 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
4591 pragma_interrupt
= 1;
4596 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
4598 pragma_interrupt
= pragma_trapa
= 1;
4602 sh_pr_nosave_low_regs (pfile
)
4603 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
4605 pragma_nosave_low_regs
= 1;
4608 /* Generate 'handle_interrupt' attribute for decls */
4611 sh_insert_attributes (node
, attributes
)
4615 if (! pragma_interrupt
4616 || TREE_CODE (node
) != FUNCTION_DECL
)
4619 /* We are only interested in fields. */
4620 if (TREE_CODE_CLASS (TREE_CODE (node
)) != 'd')
4623 /* Add a 'handle_interrupt' attribute. */
4624 * attributes
= tree_cons (get_identifier ("interrupt_handler"), NULL
, * attributes
);
4629 /* Return nonzero if ATTR is a valid attribute for DECL.
4630 ATTRIBUTES are any existing attributes and ARGS are the arguments
4633 Supported attributes:
4635 interrupt_handler -- specifies this function is an interrupt handler.
4637 sp_switch -- specifies an alternate stack for an interrupt handler
4640 trap_exit -- use a trapa to exit an interrupt function instead of
4641 an rte instruction. */
4644 sh_valid_decl_attribute (decl
, attributes
, attr
, args
)
4646 tree attributes ATTRIBUTE_UNUSED
;
4650 if (TREE_CODE (decl
) != FUNCTION_DECL
)
4653 if (is_attribute_p ("interrupt_handler", attr
))
4658 if (is_attribute_p ("sp_switch", attr
))
4660 /* The sp_switch attribute only has meaning for interrupt functions. */
4661 if (!pragma_interrupt
)
4664 /* sp_switch must have an argument. */
4665 if (!args
|| TREE_CODE (args
) != TREE_LIST
)
4668 /* The argument must be a constant string. */
4669 if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
4672 sp_switch
= gen_rtx_SYMBOL_REF (VOIDmode
,
4673 TREE_STRING_POINTER (TREE_VALUE (args
)));
4677 if (is_attribute_p ("trap_exit", attr
))
4679 /* The trap_exit attribute only has meaning for interrupt functions. */
4680 if (!pragma_interrupt
)
4683 /* trap_exit must have an argument. */
4684 if (!args
|| TREE_CODE (args
) != TREE_LIST
)
4687 /* The argument must be a constant integer. */
4688 if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
4691 trap_exit
= TREE_INT_CST_LOW (TREE_VALUE (args
));
4699 /* Predicates used by the templates. */
4701 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
4702 Used only in general_movsrc_operand. */
4705 system_reg_operand (op
, mode
)
4707 enum machine_mode mode ATTRIBUTE_UNUSED
;
4719 /* Returns 1 if OP can be source of a simple move operation.
4720 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
4721 invalid as are subregs of system registers. */
4724 general_movsrc_operand (op
, mode
)
4726 enum machine_mode mode
;
4728 if (GET_CODE (op
) == MEM
)
4730 rtx inside
= XEXP (op
, 0);
4731 if (GET_CODE (inside
) == CONST
)
4732 inside
= XEXP (inside
, 0);
4734 if (GET_CODE (inside
) == LABEL_REF
)
4737 if (GET_CODE (inside
) == PLUS
4738 && GET_CODE (XEXP (inside
, 0)) == LABEL_REF
4739 && GET_CODE (XEXP (inside
, 1)) == CONST_INT
)
4742 /* Only post inc allowed. */
4743 if (GET_CODE (inside
) == PRE_DEC
)
4747 if ((mode
== QImode
|| mode
== HImode
)
4748 && (GET_CODE (op
) == SUBREG
4749 && GET_CODE (XEXP (op
, 0)) == REG
4750 && system_reg_operand (XEXP (op
, 0), mode
)))
4753 return general_operand (op
, mode
);
4756 /* Returns 1 if OP can be a destination of a move.
4757 Same as general_operand, but no preinc allowed. */
4760 general_movdst_operand (op
, mode
)
4762 enum machine_mode mode
;
4764 /* Only pre dec allowed. */
4765 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
4768 return general_operand (op
, mode
);
4771 /* Returns 1 if OP is a normal arithmetic register. */
4774 arith_reg_operand (op
, mode
)
4776 enum machine_mode mode
;
4778 if (register_operand (op
, mode
))
4782 if (GET_CODE (op
) == REG
)
4784 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
4785 regno
= REGNO (SUBREG_REG (op
));
4789 return (regno
!= T_REG
&& regno
!= PR_REG
4790 && (regno
!= FPUL_REG
|| TARGET_SH4
)
4791 && regno
!= MACH_REG
&& regno
!= MACL_REG
);
4797 fp_arith_reg_operand (op
, mode
)
4799 enum machine_mode mode
;
4801 if (register_operand (op
, mode
))
4805 if (GET_CODE (op
) == REG
)
4807 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
4808 regno
= REGNO (SUBREG_REG (op
));
4812 return (regno
>= FIRST_PSEUDO_REGISTER
4813 || FP_REGISTER_P (regno
));
4818 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
4821 arith_operand (op
, mode
)
4823 enum machine_mode mode
;
4825 if (arith_reg_operand (op
, mode
))
4828 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
4834 /* Returns 1 if OP is a valid source operand for a compare insn. */
4837 arith_reg_or_0_operand (op
, mode
)
4839 enum machine_mode mode
;
4841 if (arith_reg_operand (op
, mode
))
4844 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_N (INTVAL (op
)))
4850 /* Returns 1 if OP is a valid source operand for a logical operation. */
4853 logical_operand (op
, mode
)
4855 enum machine_mode mode
;
4857 if (arith_reg_operand (op
, mode
))
4860 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
4866 /* Nonzero if OP is a floating point value with value 0.0. */
4869 fp_zero_operand (op
)
4874 if (GET_MODE (op
) != SFmode
)
4877 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4878 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
4881 /* Nonzero if OP is a floating point value with value 1.0. */
4889 if (GET_MODE (op
) != SFmode
)
4892 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4893 return REAL_VALUES_EQUAL (r
, dconst1
);
4896 /* For -m4 and -m4-single-only, mode switching is used. If we are
4897 compiling without -mfmovd, movsf_ie isn't taken into account for
4898 mode switching. We could check in machine_dependent_reorg for
4899 cases where we know we are in single precision mode, but there is
4900 interface to find that out during reload, so we must avoid
4901 choosing an fldi alternative during reload and thus failing to
4902 allocate a scratch register for the constant loading. */
4906 return ! TARGET_SH4
|| TARGET_FMOVD
|| reload_completed
;
4910 tertiary_reload_operand (op
, mode
)
4912 enum machine_mode mode ATTRIBUTE_UNUSED
;
4914 enum rtx_code code
= GET_CODE (op
);
4915 return code
== MEM
|| (TARGET_SH4
&& code
== CONST_DOUBLE
);
4919 fpscr_operand (op
, mode
)
4921 enum machine_mode mode ATTRIBUTE_UNUSED
;
4923 return (GET_CODE (op
) == REG
&& REGNO (op
) == FPSCR_REG
4924 && GET_MODE (op
) == PSImode
);
4928 fpul_operand (op
, mode
)
4930 enum machine_mode mode
;
4932 return (GET_CODE (op
) == REG
4933 && (REGNO (op
) == FPUL_REG
|| REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
4934 && GET_MODE (op
) == mode
);
4938 symbol_ref_operand (op
, mode
)
4940 enum machine_mode mode ATTRIBUTE_UNUSED
;
4942 return (GET_CODE (op
) == SYMBOL_REF
);
4946 commutative_float_operator (op
, mode
)
4948 enum machine_mode mode
;
4950 if (GET_MODE (op
) != mode
)
4952 switch (GET_CODE (op
))
4964 noncommutative_float_operator (op
, mode
)
4966 enum machine_mode mode
;
4968 if (GET_MODE (op
) != mode
)
4970 switch (GET_CODE (op
))
4982 binary_float_operator (op
, mode
)
4984 enum machine_mode mode
;
4986 if (GET_MODE (op
) != mode
)
4988 switch (GET_CODE (op
))
5001 /* Return the destination address of a branch. */
5004 branch_dest (branch
)
5007 rtx dest
= SET_SRC (PATTERN (branch
));
5010 if (GET_CODE (dest
) == IF_THEN_ELSE
)
5011 dest
= XEXP (dest
, 1);
5012 dest
= XEXP (dest
, 0);
5013 dest_uid
= INSN_UID (dest
);
5014 return INSN_ADDRESSES (dest_uid
);
5017 /* Return non-zero if REG is not used after INSN.
5018 We assume REG is a reload reg, and therefore does
5019 not live past labels. It may live past calls or jumps though. */
5021 reg_unused_after (reg
, insn
)
5028 /* If the reg is set by this instruction, then it is safe for our
5029 case. Disregard the case where this is a store to memory, since
5030 we are checking a register used in the store address. */
5031 set
= single_set (insn
);
5032 if (set
&& GET_CODE (SET_DEST (set
)) != MEM
5033 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
5036 while ((insn
= NEXT_INSN (insn
)))
5038 code
= GET_CODE (insn
);
5041 /* If this is a label that existed before reload, then the register
5042 if dead here. However, if this is a label added by reorg, then
5043 the register may still be live here. We can't tell the difference,
5044 so we just ignore labels completely. */
5045 if (code
== CODE_LABEL
)
5050 if (code
== JUMP_INSN
)
5053 /* If this is a sequence, we must handle them all at once.
5054 We could have for instance a call that sets the target register,
5055 and a insn in a delay slot that uses the register. In this case,
5056 we must return 0. */
5057 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
5062 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
5064 rtx this_insn
= XVECEXP (PATTERN (insn
), 0, i
);
5065 rtx set
= single_set (this_insn
);
5067 if (GET_CODE (this_insn
) == CALL_INSN
)
5069 else if (GET_CODE (this_insn
) == JUMP_INSN
)
5071 if (INSN_ANNULLED_BRANCH_P (this_insn
))
5076 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
5078 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
5080 if (GET_CODE (SET_DEST (set
)) != MEM
)
5086 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
5091 else if (code
== JUMP_INSN
)
5094 else if (GET_RTX_CLASS (code
) == 'i')
5096 rtx set
= single_set (insn
);
5098 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
5100 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
5101 return GET_CODE (SET_DEST (set
)) != MEM
;
5102 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
5106 if (code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
5117 static rtx fpscr_rtx
;
5121 fpscr_rtx
= gen_rtx (REG
, PSImode
, FPSCR_REG
);
5122 REG_USERVAR_P (fpscr_rtx
) = 1;
5123 ggc_add_rtx_root (&fpscr_rtx
, 1);
5124 mark_user_reg (fpscr_rtx
);
5126 if (! reload_completed
|| mdep_reorg_phase
!= SH_AFTER_MDEP_REORG
)
5127 mark_user_reg (fpscr_rtx
);
5146 expand_sf_unop (fun
, operands
)
5147 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
5150 emit_sf_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
5154 expand_sf_binop (fun
, operands
)
5155 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
5158 emit_sf_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
5163 expand_df_unop (fun
, operands
)
5164 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
5167 emit_df_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
5171 expand_df_binop (fun
, operands
)
5172 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
5175 emit_df_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
5179 /* ??? gcc does flow analysis strictly after common subexpression
5180 elimination. As a result, common subespression elimination fails
5181 when there are some intervening statements setting the same register.
5182 If we did nothing about this, this would hurt the precision switching
5183 for SH4 badly. There is some cse after reload, but it is unable to
5184 undo the extra register pressure from the unused instructions, and
5185 it cannot remove auto-increment loads.
5187 A C code example that shows this flow/cse weakness for (at least) SH
5188 and sparc (as of gcc ss-970706) is this:
5202 So we add another pass before common subexpression elimination, to
5203 remove assignments that are dead due to a following assignment in the
5204 same basic block. */
5207 mark_use (x
, reg_set_block
)
5208 rtx x
, *reg_set_block
;
5214 code
= GET_CODE (x
);
5219 int regno
= REGNO (x
);
5220 int nregs
= (regno
< FIRST_PSEUDO_REGISTER
5221 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
))
5225 reg_set_block
[regno
+ nregs
- 1] = 0;
5232 rtx dest
= SET_DEST (x
);
5234 if (GET_CODE (dest
) == SUBREG
)
5235 dest
= SUBREG_REG (dest
);
5236 if (GET_CODE (dest
) != REG
)
5237 mark_use (dest
, reg_set_block
);
5238 mark_use (SET_SRC (x
), reg_set_block
);
5245 const char *fmt
= GET_RTX_FORMAT (code
);
5247 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5250 mark_use (XEXP (x
, i
), reg_set_block
);
5251 else if (fmt
[i
] == 'E')
5252 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5253 mark_use (XVECEXP (x
, i
, j
), reg_set_block
);
5260 static rtx get_free_reg
PARAMS ((HARD_REG_SET
));
5262 /* This function returns a register to use to load the address to load
5263 the fpscr from. Currently it always returns r1 or r7, but when we are
5264 able to use pseudo registers after combine, or have a better mechanism
5265 for choosing a register, it should be done here. */
5266 /* REGS_LIVE is the liveness information for the point for which we
5267 need this allocation. In some bare-bones exit blocks, r1 is live at the
5268 start. We can even have all of r0..r3 being live:
5269 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
5270 INSN before which new insns are placed with will clobber the register
5271 we return. If a basic block consists only of setting the return value
5272 register to a pseudo and using that register, the return value is not
5273 live before or after this block, yet we we'll insert our insns right in
5277 get_free_reg (regs_live
)
5278 HARD_REG_SET regs_live
;
5280 if (! TEST_HARD_REG_BIT (regs_live
, 1))
5281 return gen_rtx_REG (Pmode
, 1);
5283 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
5284 there shouldn't be anything but a jump before the function end. */
5285 if (! TEST_HARD_REG_BIT (regs_live
, 7))
5286 return gen_rtx_REG (Pmode
, 7);
5291 /* This function will set the fpscr from memory.
5292 MODE is the mode we are setting it to. */
5294 fpscr_set_from_mem (mode
, regs_live
)
5296 HARD_REG_SET regs_live
;
5298 enum attr_fp_mode fp_mode
= mode
;
5299 rtx addr_reg
= get_free_reg (regs_live
);
5301 if (fp_mode
== (enum attr_fp_mode
) NORMAL_MODE (FP_MODE
))
5302 emit_insn (gen_fpu_switch1 (addr_reg
));
5304 emit_insn (gen_fpu_switch0 (addr_reg
));
5307 /* Is the given character a logical line separator for the assembler? */
5308 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
5309 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
5313 sh_insn_length_adjustment (insn
)
5316 /* Instructions with unfilled delay slots take up an extra two bytes for
5317 the nop in the delay slot. */
5318 if (((GET_CODE (insn
) == INSN
5319 && GET_CODE (PATTERN (insn
)) != USE
5320 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
5321 || GET_CODE (insn
) == CALL_INSN
5322 || (GET_CODE (insn
) == JUMP_INSN
5323 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
5324 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
))
5325 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
5326 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
5329 /* sh-dsp parallel processing insn take four bytes instead of two. */
5331 if (GET_CODE (insn
) == INSN
)
5334 rtx body
= PATTERN (insn
);
5335 const char *template;
5337 int maybe_label
= 1;
5339 if (GET_CODE (body
) == ASM_INPUT
)
5340 template = XSTR (body
, 0);
5341 else if (asm_noperands (body
) >= 0)
5343 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
);
5352 while (c
== ' ' || c
== '\t');
5353 /* all sh-dsp parallel-processing insns start with p.
5354 The only non-ppi sh insn starting with p is pref.
5355 The only ppi starting with pr is prnd. */
5356 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", template, 2))
5358 /* The repeat pseudo-insn expands two three insns, a total of
5359 six bytes in size. */
5360 else if ((c
== 'r' || c
== 'R')
5361 && ! strncasecmp ("epeat", template, 5))
5363 while (c
&& c
!= '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
))
5365 /* If this is a label, it is obviously not a ppi insn. */
5366 if (c
== ':' && maybe_label
)
5371 else if (c
== '\'' || c
== '"')
5376 maybe_label
= c
!= ':';
5384 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
5385 isn't protected by a PIC unspec. */
5387 nonpic_symbol_mentioned_p (x
)
5390 register const char *fmt
;
5393 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
5396 if (GET_CODE (x
) == UNSPEC
5397 && (XINT (x
, 1) == UNSPEC_PIC
5398 || XINT (x
, 1) == UNSPEC_GOT
5399 || XINT (x
, 1) == UNSPEC_GOTOFF
5400 || XINT (x
, 1) == UNSPEC_PLT
))
5403 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5404 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5410 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5411 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
5414 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
5421 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
5422 @GOTOFF in `reg'. */
5424 legitimize_pic_address (orig
, mode
, reg
)
5426 enum machine_mode mode ATTRIBUTE_UNUSED
;
5429 if (GET_CODE (orig
) == LABEL_REF
5430 || (GET_CODE (orig
) == SYMBOL_REF
5431 && (CONSTANT_POOL_ADDRESS_P (orig
)
5432 /* SYMBOL_REF_FLAG is set on static symbols. */
5433 || SYMBOL_REF_FLAG (orig
))))
5436 reg
= gen_reg_rtx (Pmode
);
5438 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
5441 else if (GET_CODE (orig
) == SYMBOL_REF
)
5444 reg
= gen_reg_rtx (Pmode
);
5446 emit_insn (gen_symGOT2reg (reg
, orig
));
5452 /* Mark the use of a constant in the literal table. If the constant
5453 has multiple labels, make it unique. */
5454 static rtx
mark_constant_pool_use (x
)
5457 rtx insn
, lab
, pattern
;
5462 switch (GET_CODE (x
))
5472 /* Get the first label in the list of labels for the same constant
5473 and delete another labels in the list. */
5475 for (insn
= PREV_INSN (x
); insn
; insn
= PREV_INSN (insn
))
5477 if (GET_CODE (insn
) != CODE_LABEL
5478 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
5483 for (insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
5484 INSN_DELETED_P (insn
) = 1;
5486 /* Mark constants in a window. */
5487 for (insn
= NEXT_INSN (x
); insn
; insn
= NEXT_INSN (insn
))
5489 if (GET_CODE (insn
) != INSN
)
5492 pattern
= PATTERN (insn
);
5493 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
5496 switch (XINT (pattern
, 1))
5498 case UNSPECV_CONST2
:
5499 case UNSPECV_CONST4
:
5500 case UNSPECV_CONST8
:
5501 XVECEXP (pattern
, 0, 1) = const1_rtx
;
5503 case UNSPECV_WINDOW_END
:
5504 if (XVECEXP (pattern
, 0, 0) == x
)
5507 case UNSPECV_CONST_END
: