1 /* Output routines for GCC for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
28 #include "insn-config.h"
36 #include "hard-reg-set.h"
38 #include "insn-attr.h"
42 #include "integrate.h"
45 #include "target-def.h"
47 #include "langhooks.h"
48 #include "basic-block.h"
50 #include "cfglayout.h"
52 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
54 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
55 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
57 /* These are some macros to abstract register modes. */
58 #define CONST_OK_FOR_ADD(size) \
59 (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size))
60 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
61 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
62 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
64 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
65 int current_function_interrupt
;
67 /* ??? The pragma interrupt support will not work for SH3. */
68 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
69 output code for the next function appropriate for an interrupt handler. */
72 /* This is set by the trap_exit attribute for functions. It specifies
73 a trap number to be used in a trapa instruction at function exit
74 (instead of an rte instruction). */
77 /* This is used by the sp_switch attribute for functions. It specifies
78 a variable holding the address of the stack the interrupt function
79 should switch to/from at entry/exit. */
82 /* This is set by #pragma trapa, and is similar to the above, except that
83 the compiler doesn't emit code to preserve all registers. */
84 static int pragma_trapa
;
86 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
87 which has a separate set of low regs for User and Supervisor modes.
88 This should only be used for the lowest level of interrupts. Higher levels
89 of interrupts must save the registers in case they themselves are
91 int pragma_nosave_low_regs
;
93 /* This is used for communication between SETUP_INCOMING_VARARGS and
94 sh_expand_prologue. */
95 int current_function_anonymous_args
;
97 /* Global variables for machine-dependent things. */
99 /* Which cpu are we scheduling for. */
100 enum processor_type sh_cpu
;
102 /* Saved operands from the last compare to use when we generate an scc
108 /* Provides the class number of the smallest class containing
111 int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
113 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
114 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
115 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
116 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
117 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
118 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
119 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
120 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
121 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
122 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
123 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
124 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
125 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
126 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
127 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
128 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
129 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
130 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
131 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
132 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
133 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
134 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
135 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
136 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
137 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
138 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
139 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
140 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
141 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
142 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
143 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
144 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
145 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
146 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
147 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
148 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
149 NO_REGS
, GENERAL_REGS
, PR_REGS
, T_REGS
,
150 MAC_REGS
, MAC_REGS
, FPUL_REGS
, FPSCR_REGS
,
154 char sh_register_names
[FIRST_PSEUDO_REGISTER
] \
155 [MAX_REGISTER_NAME_LENGTH
+ 1] = SH_REGISTER_NAMES_INITIALIZER
;
157 char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
158 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1]
159 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER
;
161 /* Provide reg_class from a letter such as appears in the machine
162 description. *: target independently reserved letter.
163 reg_class_from_letter['e' - 'a'] is set to NO_REGS for TARGET_FMOVD. */
165 enum reg_class reg_class_from_letter
[] =
167 /* a */ ALL_REGS
, /* b */ TARGET_REGS
, /* c */ FPSCR_REGS
, /* d */ DF_REGS
,
168 /* e */ FP_REGS
, /* f */ FP_REGS
, /* g **/ NO_REGS
, /* h */ NO_REGS
,
169 /* i **/ NO_REGS
, /* j */ NO_REGS
, /* k */ SIBCALL_REGS
, /* l */ PR_REGS
,
170 /* m **/ NO_REGS
, /* n **/ NO_REGS
, /* o **/ NO_REGS
, /* p **/ NO_REGS
,
171 /* q */ NO_REGS
, /* r **/ NO_REGS
, /* s **/ NO_REGS
, /* t */ T_REGS
,
172 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ FP0_REGS
, /* x */ MAC_REGS
,
173 /* y */ FPUL_REGS
, /* z */ R0_REGS
176 int assembler_dialect
;
178 static void split_branches
PARAMS ((rtx
));
179 static int branch_dest
PARAMS ((rtx
));
180 static void force_into
PARAMS ((rtx
, rtx
));
181 static void print_slot
PARAMS ((rtx
));
182 static rtx add_constant
PARAMS ((rtx
, enum machine_mode
, rtx
));
183 static void dump_table
PARAMS ((rtx
));
184 static int hi_const
PARAMS ((rtx
));
185 static int broken_move
PARAMS ((rtx
));
186 static int mova_p
PARAMS ((rtx
));
187 static rtx find_barrier
PARAMS ((int, rtx
, rtx
));
188 static int noncall_uses_reg
PARAMS ((rtx
, rtx
, rtx
*));
189 static rtx gen_block_redirect
PARAMS ((rtx
, int, int));
190 static void sh_reorg
PARAMS ((void));
191 static void output_stack_adjust
PARAMS ((int, rtx
, int, rtx (*) (rtx
)));
192 static rtx frame_insn
PARAMS ((rtx
));
193 static rtx push
PARAMS ((int));
194 static void pop
PARAMS ((int));
195 static void push_regs
PARAMS ((HARD_REG_SET
*, int));
196 static int calc_live_regs
PARAMS ((HARD_REG_SET
*));
197 static void mark_use
PARAMS ((rtx
, rtx
*));
198 static HOST_WIDE_INT rounded_frame_size
PARAMS ((int));
199 static rtx mark_constant_pool_use
PARAMS ((rtx
));
200 const struct attribute_spec sh_attribute_table
[];
201 static tree sh_handle_interrupt_handler_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
202 static tree sh_handle_sp_switch_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
203 static tree sh_handle_trap_exit_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
204 static void sh_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
205 static void sh_insert_attributes
PARAMS ((tree
, tree
*));
206 static int sh_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
207 static int sh_use_dfa_interface
PARAMS ((void));
208 static int sh_issue_rate
PARAMS ((void));
209 static bool sh_function_ok_for_sibcall
PARAMS ((tree
, tree
));
211 static bool sh_cannot_modify_jumps_p
PARAMS ((void));
212 static bool sh_ms_bitfield_layout_p
PARAMS ((tree
));
214 static void sh_init_builtins
PARAMS ((void));
215 static void sh_media_init_builtins
PARAMS ((void));
216 static rtx sh_expand_builtin
PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
217 static void sh_output_mi_thunk
PARAMS ((FILE *, tree
, HOST_WIDE_INT
,
218 HOST_WIDE_INT
, tree
));
219 static int flow_dependent_p
PARAMS ((rtx
, rtx
));
220 static void flow_dependent_p_1
PARAMS ((rtx
, rtx
, void *));
221 static int shiftcosts
PARAMS ((rtx
));
222 static int andcosts
PARAMS ((rtx
));
223 static int addsubcosts
PARAMS ((rtx
));
224 static int multcosts
PARAMS ((rtx
));
225 static bool unspec_caller_rtx_p
PARAMS ((rtx
));
226 static bool sh_cannot_copy_insn_p
PARAMS ((rtx
));
227 static bool sh_rtx_costs
PARAMS ((rtx
, int, int, int *));
228 static int sh_address_cost
PARAMS ((rtx
));
230 /* Initialize the GCC target structure. */
231 #undef TARGET_ATTRIBUTE_TABLE
232 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
234 /* The next two are used for debug info when compiling with -gdwarf. */
235 #undef TARGET_ASM_UNALIGNED_HI_OP
236 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
237 #undef TARGET_ASM_UNALIGNED_SI_OP
238 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
240 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
241 #undef TARGET_ASM_UNALIGNED_DI_OP
242 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
243 #undef TARGET_ASM_ALIGNED_DI_OP
244 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
246 #undef TARGET_ASM_FUNCTION_EPILOGUE
247 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
249 #undef TARGET_ASM_OUTPUT_MI_THUNK
250 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
252 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
253 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
255 #undef TARGET_INSERT_ATTRIBUTES
256 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
258 #undef TARGET_SCHED_ADJUST_COST
259 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
261 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
262 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
264 #undef TARGET_SCHED_ISSUE_RATE
265 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
267 #undef TARGET_CANNOT_MODIFY_JUMPS_P
268 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
270 #undef TARGET_MS_BITFIELD_LAYOUT_P
271 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
273 #undef TARGET_INIT_BUILTINS
274 #define TARGET_INIT_BUILTINS sh_init_builtins
275 #undef TARGET_EXPAND_BUILTIN
276 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
278 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
279 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
281 #undef TARGET_CANNOT_COPY_INSN_P
282 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
283 #undef TARGET_RTX_COSTS
284 #define TARGET_RTX_COSTS sh_rtx_costs
285 #undef TARGET_ADDRESS_COST
286 #define TARGET_ADDRESS_COST sh_address_cost
288 #undef TARGET_MACHINE_DEPENDENT_REORG
289 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
292 #undef TARGET_HAVE_TLS
293 #define TARGET_HAVE_TLS true
296 struct gcc_target targetm
= TARGET_INITIALIZER
;
298 /* Print the operand address in x to the stream. */
301 print_operand_address (stream
, x
)
305 switch (GET_CODE (x
))
309 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
314 rtx base
= XEXP (x
, 0);
315 rtx index
= XEXP (x
, 1);
317 switch (GET_CODE (index
))
320 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
321 reg_names
[true_regnum (base
)]);
327 int base_num
= true_regnum (base
);
328 int index_num
= true_regnum (index
);
330 fprintf (stream
, "@(r0,%s)",
331 reg_names
[MAX (base_num
, index_num
)]);
343 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
347 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
351 x
= mark_constant_pool_use (x
);
352 output_addr_const (stream
, x
);
357 /* Print operand x (an rtx) in assembler syntax to file stream
358 according to modifier code.
360 '.' print a .s if insn needs delay slot
361 ',' print LOCAL_LABEL_PREFIX
362 '@' print trap, rte or rts depending upon pragma interruptness
363 '#' output a nop if there is nothing to put in the delay slot
364 ''' print likelyhood suffix (/u for unlikely).
365 'O' print a constant without the #
366 'R' print the LSW of a dp value - changes if in little endian
367 'S' print the MSW of a dp value - changes if in little endian
368 'T' print the next word of a dp value - same as 'R' in big endian mode.
369 'M' print an `x' if `m' will print `base,index'.
370 'N' print 'r63' if the operand is (const_int 0).
371 'm' print a pair `base,offset' or `base,index', for LD and ST.
372 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
373 'o' output an operator. */
376 print_operand (stream
, x
, code
)
385 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))
386 && get_attr_length (XVECEXP (final_sequence
, 0, 1)))
387 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
390 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
394 fprintf (stream
, "trapa #%d", trap_exit
);
395 else if (sh_cfun_interrupt_handler_p ())
396 fprintf (stream
, "rte");
398 fprintf (stream
, "rts");
401 /* Output a nop if there's nothing in the delay slot. */
402 if (dbr_sequence_length () == 0)
403 fprintf (stream
, "\n\tnop");
407 rtx note
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
409 if (note
&& INTVAL (XEXP (note
, 0)) * 2 < REG_BR_PROB_BASE
)
410 fputs ("/u", stream
);
414 x
= mark_constant_pool_use (x
);
415 output_addr_const (stream
, x
);
418 fputs (reg_names
[REGNO (x
) + LSW
], (stream
));
421 fputs (reg_names
[REGNO (x
) + MSW
], (stream
));
424 /* Next word of a double. */
425 switch (GET_CODE (x
))
428 fputs (reg_names
[REGNO (x
) + 1], (stream
));
431 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
432 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
433 x
= adjust_address (x
, SImode
, 4);
434 print_operand_address (stream
, XEXP (x
, 0));
441 switch (GET_CODE (x
))
443 case PLUS
: fputs ("add", stream
); break;
444 case MINUS
: fputs ("sub", stream
); break;
445 case MULT
: fputs ("mul", stream
); break;
446 case DIV
: fputs ("div", stream
); break;
447 case EQ
: fputs ("eq", stream
); break;
448 case NE
: fputs ("ne", stream
); break;
449 case GT
: case LT
: fputs ("gt", stream
); break;
450 case GE
: case LE
: fputs ("ge", stream
); break;
451 case GTU
: case LTU
: fputs ("gtu", stream
); break;
452 case GEU
: case LEU
: fputs ("geu", stream
); break;
458 if (GET_CODE (x
) == MEM
459 && GET_CODE (XEXP (x
, 0)) == PLUS
460 && (GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
461 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == SUBREG
))
466 if (GET_CODE (x
) != MEM
)
469 switch (GET_CODE (x
))
473 print_operand (stream
, x
, 0);
474 fputs (", 0", stream
);
478 print_operand (stream
, XEXP (x
, 0), 0);
479 fputs (", ", stream
);
480 print_operand (stream
, XEXP (x
, 1), 0);
489 if (x
== CONST0_RTX (GET_MODE (x
)))
491 fprintf ((stream
), "r63");
496 if (GET_CODE (x
) == CONST_INT
)
498 fprintf ((stream
), "%u", (unsigned) INTVAL (x
) & (0x10000 - 1));
505 switch (GET_CODE (x
))
507 /* FIXME: We need this on SHmedia32 because reload generates
508 some sign-extended HI or QI loads into DImode registers
509 but, because Pmode is SImode, the address ends up with a
510 subreg:SI of the DImode register. Maybe reload should be
511 fixed so as to apply alter_subreg to such loads? */
513 if (SUBREG_BYTE (x
) != 0
514 || GET_CODE (SUBREG_REG (x
)) != REG
)
521 if (FP_REGISTER_P (REGNO (x
))
522 && GET_MODE (x
) == V16SFmode
)
523 fprintf ((stream
), "mtrx%s", reg_names
[REGNO (x
)] + 2);
524 else if (FP_REGISTER_P (REGNO (x
))
525 && GET_MODE (x
) == V4SFmode
)
526 fprintf ((stream
), "fv%s", reg_names
[REGNO (x
)] + 2);
527 else if (GET_CODE (x
) == REG
528 && GET_MODE (x
) == V2SFmode
)
529 fprintf ((stream
), "fp%s", reg_names
[REGNO (x
)] + 2);
530 else if (FP_REGISTER_P (REGNO (x
))
531 && GET_MODE_SIZE (GET_MODE (x
)) > 4)
532 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)] + 1);
534 fputs (reg_names
[REGNO (x
)], (stream
));
538 output_address (XEXP (x
, 0));
543 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
544 && GET_MODE (XEXP (x
, 0)) == DImode
545 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == TRUNCATE
546 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
)
548 rtx val
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
551 if (GET_CODE (val
) == ASHIFTRT
)
554 if (GET_CODE (XEXP (val
, 0)) == CONST
)
556 output_addr_const (stream
, XEXP (val
, 0));
557 if (GET_CODE (XEXP (val
, 0)) == CONST
)
559 fputs (" >> ", stream
);
560 output_addr_const (stream
, XEXP (val
, 1));
565 if (GET_CODE (val
) == CONST
)
567 output_addr_const (stream
, val
);
568 if (GET_CODE (val
) == CONST
)
571 fputs (" & 65535)", stream
);
579 output_addr_const (stream
, x
);
586 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
588 force_into (value
, target
)
591 value
= force_operand (value
, target
);
592 if (! rtx_equal_p (value
, target
))
593 emit_insn (gen_move_insn (target
, value
));
596 /* Emit code to perform a block move. Choose the best method.
598 OPERANDS[0] is the destination.
599 OPERANDS[1] is the source.
600 OPERANDS[2] is the size.
601 OPERANDS[3] is the alignment safe to use. */
604 expand_block_move (operands
)
607 int align
= INTVAL (operands
[3]);
608 int constp
= (GET_CODE (operands
[2]) == CONST_INT
);
609 int bytes
= (constp
? INTVAL (operands
[2]) : 0);
611 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
612 alignment, or if it isn't a multiple of 4 bytes, then fail. */
613 if (! constp
|| align
< 4 || (bytes
% 4 != 0))
620 else if (bytes
== 12)
625 rtx r4
= gen_rtx (REG
, SImode
, 4);
626 rtx r5
= gen_rtx (REG
, SImode
, 5);
628 entry_name
= get_identifier ("__movstrSI12_i4");
630 sym
= function_symbol (IDENTIFIER_POINTER (entry_name
));
631 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
632 force_into (XEXP (operands
[0], 0), r4
);
633 force_into (XEXP (operands
[1], 0), r5
);
634 emit_insn (gen_block_move_real_i4 (func_addr_rtx
));
637 else if (! TARGET_SMALLCODE
)
643 rtx r4
= gen_rtx (REG
, SImode
, 4);
644 rtx r5
= gen_rtx (REG
, SImode
, 5);
645 rtx r6
= gen_rtx (REG
, SImode
, 6);
647 entry_name
= get_identifier (bytes
& 4
649 : "__movstr_i4_even");
650 sym
= function_symbol (IDENTIFIER_POINTER (entry_name
));
651 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
652 force_into (XEXP (operands
[0], 0), r4
);
653 force_into (XEXP (operands
[1], 0), r5
);
656 emit_insn (gen_move_insn (r6
, GEN_INT (dwords
- 1)));
657 emit_insn (gen_block_lump_real_i4 (func_addr_rtx
));
669 rtx r4
= gen_rtx_REG (SImode
, 4);
670 rtx r5
= gen_rtx_REG (SImode
, 5);
672 sprintf (entry
, "__movstrSI%d", bytes
);
673 entry_name
= get_identifier (entry
);
674 sym
= function_symbol (IDENTIFIER_POINTER (entry_name
));
675 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
676 force_into (XEXP (operands
[0], 0), r4
);
677 force_into (XEXP (operands
[1], 0), r5
);
678 emit_insn (gen_block_move_real (func_addr_rtx
));
682 /* This is the same number of bytes as a memcpy call, but to a different
683 less common function name, so this will occasionally use more space. */
684 if (! TARGET_SMALLCODE
)
689 int final_switch
, while_loop
;
690 rtx r4
= gen_rtx_REG (SImode
, 4);
691 rtx r5
= gen_rtx_REG (SImode
, 5);
692 rtx r6
= gen_rtx_REG (SImode
, 6);
694 entry_name
= get_identifier ("__movstr");
695 sym
= function_symbol (IDENTIFIER_POINTER (entry_name
));
696 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
697 force_into (XEXP (operands
[0], 0), r4
);
698 force_into (XEXP (operands
[1], 0), r5
);
700 /* r6 controls the size of the move. 16 is decremented from it
701 for each 64 bytes moved. Then the negative bit left over is used
702 as an index into a list of move instructions. e.g., a 72 byte move
703 would be set up with size(r6) = 14, for one iteration through the
704 big while loop, and a switch of -2 for the last part. */
706 final_switch
= 16 - ((bytes
/ 4) % 16);
707 while_loop
= ((bytes
/ 4) / 16 - 1) * 16;
708 emit_insn (gen_move_insn (r6
, GEN_INT (while_loop
+ final_switch
)));
709 emit_insn (gen_block_lump_real (func_addr_rtx
));
716 /* Prepare operands for a move define_expand; specifically, one of the
717 operands must be in a register. */
720 prepare_move_operands (operands
, mode
)
722 enum machine_mode mode
;
724 if ((mode
== SImode
|| mode
== DImode
)
726 && ! ((mode
== Pmode
|| mode
== ptr_mode
)
727 && tls_symbolic_operand (operands
[1], Pmode
) != 0))
730 if (SYMBOLIC_CONST_P (operands
[1]))
732 if (GET_CODE (operands
[0]) == MEM
)
733 operands
[1] = force_reg (Pmode
, operands
[1]);
734 else if (TARGET_SHMEDIA
735 && GET_CODE (operands
[1]) == LABEL_REF
736 && target_reg_operand (operands
[0], mode
))
740 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
741 operands
[1] = legitimize_pic_address (operands
[1], mode
, temp
);
744 else if (GET_CODE (operands
[1]) == CONST
745 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
746 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
748 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
749 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
751 operands
[1] = expand_binop (mode
, add_optab
, temp
,
752 XEXP (XEXP (operands
[1], 0), 1),
753 no_new_pseudos
? temp
754 : gen_reg_rtx (Pmode
),
759 if (! reload_in_progress
&& ! reload_completed
)
761 /* Copy the source to a register if both operands aren't registers. */
762 if (! register_operand (operands
[0], mode
)
763 && ! sh_register_operand (operands
[1], mode
))
764 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
766 /* This case can happen while generating code to move the result
767 of a library call to the target. Reject `st r0,@(rX,rY)' because
768 reload will fail to find a spill register for rX, since r0 is already
769 being used for the source. */
770 else if (GET_CODE (operands
[1]) == REG
&& REGNO (operands
[1]) == 0
771 && GET_CODE (operands
[0]) == MEM
772 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
773 && GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == REG
)
774 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
777 if (mode
== Pmode
|| mode
== ptr_mode
)
780 enum tls_model tls_kind
;
784 if ((tls_kind
= tls_symbolic_operand (op1
, Pmode
)))
786 rtx tga_op1
, tga_ret
, tmp
, tmp2
;
791 case TLS_MODEL_GLOBAL_DYNAMIC
:
792 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
793 emit_insn (gen_tls_global_dynamic (tga_ret
, op1
));
797 case TLS_MODEL_LOCAL_DYNAMIC
:
798 tga_ret
= gen_rtx_REG (Pmode
, R0_REG
);
799 emit_insn (gen_tls_local_dynamic (tga_ret
, op1
));
801 tmp
= gen_reg_rtx (Pmode
);
802 emit_move_insn (tmp
, tga_ret
);
804 if (register_operand (op0
, Pmode
))
807 tmp2
= gen_reg_rtx (Pmode
);
809 emit_insn (gen_symDTPOFF2reg (tmp2
, op1
, tmp
));
813 case TLS_MODEL_INITIAL_EXEC
:
815 emit_insn (gen_GOTaddr2picreg ());
816 tga_op1
= gen_reg_rtx (Pmode
);
817 tmp
= gen_sym2GOTTPOFF (op1
);
818 emit_insn (gen_tls_initial_exec (tga_op1
, tmp
));
822 case TLS_MODEL_LOCAL_EXEC
:
823 tmp2
= gen_reg_rtx (Pmode
);
824 emit_insn (gen_load_gbr (tmp2
));
825 tmp
= gen_reg_rtx (Pmode
);
826 emit_insn (gen_symTPOFF2reg (tmp
, op1
));
827 RTX_UNCHANGING_P (tmp
) = 1;
829 if (register_operand (op0
, Pmode
))
832 op1
= gen_reg_rtx (Pmode
);
834 emit_insn (gen_addsi3 (op1
, tmp
, tmp2
));
847 /* Prepare the operands for an scc instruction; make sure that the
848 compare has been done. */
850 prepare_scc_operands (code
)
853 rtx t_reg
= gen_rtx_REG (SImode
, T_REG
);
854 enum rtx_code oldcode
= code
;
855 enum machine_mode mode
;
857 /* First need a compare insn. */
861 /* It isn't possible to handle this case. */
880 rtx tmp
= sh_compare_op0
;
881 sh_compare_op0
= sh_compare_op1
;
882 sh_compare_op1
= tmp
;
885 mode
= GET_MODE (sh_compare_op0
);
886 if (mode
== VOIDmode
)
887 mode
= GET_MODE (sh_compare_op1
);
889 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
890 if ((code
!= EQ
&& code
!= NE
891 && (sh_compare_op1
!= const0_rtx
892 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
893 || (mode
== DImode
&& sh_compare_op1
!= const0_rtx
)
894 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
895 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
897 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
898 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
)
899 (gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec (2,
900 gen_rtx (SET
, VOIDmode
, t_reg
,
901 gen_rtx (code
, SImode
,
902 sh_compare_op0
, sh_compare_op1
)),
903 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ()))));
905 emit_insn (gen_rtx (SET
, VOIDmode
, t_reg
,
906 gen_rtx (code
, SImode
, sh_compare_op0
,
912 /* Called from the md file, set up the operands of a compare instruction. */
915 from_compare (operands
, code
)
919 enum machine_mode mode
= GET_MODE (sh_compare_op0
);
921 if (mode
== VOIDmode
)
922 mode
= GET_MODE (sh_compare_op1
);
925 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
927 /* Force args into regs, since we can't use constants here. */
928 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
929 if (sh_compare_op1
!= const0_rtx
930 || code
== GTU
|| code
== GEU
931 || (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
932 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
934 if (TARGET_SH2E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
&& code
== GE
)
936 from_compare (operands
, GT
);
937 insn
= gen_ieee_ccmpeqsf_t (sh_compare_op0
, sh_compare_op1
);
940 insn
= gen_rtx_SET (VOIDmode
,
941 gen_rtx_REG (SImode
, T_REG
),
942 gen_rtx (code
, SImode
, sh_compare_op0
,
944 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
946 insn
= gen_rtx (PARALLEL
, VOIDmode
,
948 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ())));
949 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
) (insn
);
955 /* Functions to output assembly code. */
957 /* Return a sequence of instructions to perform DI or DF move.
959 Since the SH cannot move a DI or DF in one instruction, we have
960 to take care when we see overlapping source and dest registers. */
963 output_movedouble (insn
, operands
, mode
)
964 rtx insn ATTRIBUTE_UNUSED
;
966 enum machine_mode mode
;
968 rtx dst
= operands
[0];
969 rtx src
= operands
[1];
971 if (GET_CODE (dst
) == MEM
972 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
973 return "mov.l %T1,%0\n\tmov.l %1,%0";
975 if (register_operand (dst
, mode
)
976 && register_operand (src
, mode
))
978 if (REGNO (src
) == MACH_REG
)
979 return "sts mach,%S0\n\tsts macl,%R0";
981 /* When mov.d r1,r2 do r2->r3 then r1->r2;
982 when mov.d r1,r0 do r1->r0 then r2->r1. */
984 if (REGNO (src
) + 1 == REGNO (dst
))
985 return "mov %T1,%T0\n\tmov %1,%0";
987 return "mov %1,%0\n\tmov %T1,%T0";
989 else if (GET_CODE (src
) == CONST_INT
)
991 if (INTVAL (src
) < 0)
992 output_asm_insn ("mov #-1,%S0", operands
);
994 output_asm_insn ("mov #0,%S0", operands
);
998 else if (GET_CODE (src
) == MEM
)
1001 int dreg
= REGNO (dst
);
1002 rtx inside
= XEXP (src
, 0);
1004 if (GET_CODE (inside
) == REG
)
1005 ptrreg
= REGNO (inside
);
1006 else if (GET_CODE (inside
) == SUBREG
)
1007 ptrreg
= subreg_regno (inside
);
1008 else if (GET_CODE (inside
) == PLUS
)
1010 ptrreg
= REGNO (XEXP (inside
, 0));
1011 /* ??? A r0+REG address shouldn't be possible here, because it isn't
1012 an offsettable address. Unfortunately, offsettable addresses use
1013 QImode to check the offset, and a QImode offsettable address
1014 requires r0 for the other operand, which is not currently
1015 supported, so we can't use the 'o' constraint.
1016 Thus we must check for and handle r0+REG addresses here.
1017 We punt for now, since this is likely very rare. */
1018 if (GET_CODE (XEXP (inside
, 1)) == REG
)
1021 else if (GET_CODE (inside
) == LABEL_REF
)
1022 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
1023 else if (GET_CODE (inside
) == POST_INC
)
1024 return "mov.l %1,%0\n\tmov.l %1,%T0";
1028 /* Work out the safe way to copy. Copy into the second half first. */
1030 return "mov.l %T1,%T0\n\tmov.l %1,%0";
1033 return "mov.l %1,%0\n\tmov.l %T1,%T0";
1036 /* Print an instruction which would have gone into a delay slot after
1037 another instruction, but couldn't because the other instruction expanded
1038 into a sequence where putting the slot insn at the end wouldn't work. */
1044 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
, optimize
, 0, 1);
1046 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
1050 output_far_jump (insn
, op
)
1054 struct { rtx lab
, reg
, op
; } this;
1055 rtx braf_base_lab
= NULL_RTX
;
1058 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
1061 this.lab
= gen_label_rtx ();
1065 && offset
- get_attr_length (insn
) <= 32766)
1068 jump
= "mov.w %O0,%1; braf %1";
1076 jump
= "mov.l %O0,%1; braf %1";
1078 jump
= "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
1081 jump
= "mov.l %O0,%1; jmp @%1";
1083 /* If we have a scratch register available, use it. */
1084 if (GET_CODE ((prev
= prev_nonnote_insn (insn
))) == INSN
1085 && INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
1087 this.reg
= SET_DEST (XVECEXP (PATTERN (prev
), 0, 0));
1088 if (REGNO (this.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
1089 jump
= "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
1090 output_asm_insn (jump
, &this.lab
);
1091 if (dbr_sequence_length ())
1092 print_slot (final_sequence
);
1094 output_asm_insn ("nop", 0);
1098 /* Output the delay slot insn first if any. */
1099 if (dbr_sequence_length ())
1100 print_slot (final_sequence
);
1102 this.reg
= gen_rtx_REG (SImode
, 13);
1103 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1104 Fortunately, MACL is fixed and call-clobbered, and we never
1105 need its value across jumps, so save r13 in it instead of in
1108 output_asm_insn ("lds r13, macl", 0);
1110 output_asm_insn ("mov.l r13,@-r15", 0);
1111 output_asm_insn (jump
, &this.lab
);
1113 output_asm_insn ("sts macl, r13", 0);
1115 output_asm_insn ("mov.l @r15+,r13", 0);
1117 if (far
&& flag_pic
&& TARGET_SH2
)
1119 braf_base_lab
= gen_label_rtx ();
1120 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1121 CODE_LABEL_NUMBER (braf_base_lab
));
1124 output_asm_insn (".align 2", 0);
1125 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (this.lab
));
1127 if (far
&& flag_pic
)
1130 this.lab
= braf_base_lab
;
1131 output_asm_insn (".long %O2-%O0", &this.lab
);
1134 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this.lab
);
1138 /* Local label counter, used for constants in the pool and inside
1139 pattern branches. */
1141 static int lf
= 100;
1143 /* Output code for ordinary branches. */
1146 output_branch (logic
, insn
, operands
)
1151 switch (get_attr_length (insn
))
1154 /* This can happen if filling the delay slot has caused a forward
1155 branch to exceed its range (we could reverse it, but only
1156 when we know we won't overextend other branches; this should
1157 best be handled by relaxation).
1158 It can also happen when other condbranches hoist delay slot insn
1159 from their destination, thus leading to code size increase.
1160 But the branch will still be in the range -4092..+4098 bytes. */
1165 /* The call to print_slot will clobber the operands. */
1166 rtx op0
= operands
[0];
1168 /* If the instruction in the delay slot is annulled (true), then
1169 there is no delay slot where we can put it now. The only safe
1170 place for it is after the label. final will do that by default. */
1173 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
1175 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
1176 ASSEMBLER_DIALECT
? "/" : ".", label
);
1177 print_slot (final_sequence
);
1180 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
1182 output_asm_insn ("bra\t%l0", &op0
);
1183 fprintf (asm_out_file
, "\tnop\n");
1184 (*targetm
.asm_out
.internal_label
)(asm_out_file
, "LF", label
);
1188 /* When relaxing, handle this like a short branch. The linker
1189 will fix it up if it still doesn't fit after relaxation. */
1191 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
1193 /* These are for SH2e, in which we have to account for the
1194 extra nop because of the hardware bug in annulled branches. */
1201 && INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
1203 asm_fprintf (asm_out_file
, "b%s%ss\t%LLF%d\n",
1205 ASSEMBLER_DIALECT
? "/" : ".", label
);
1206 fprintf (asm_out_file
, "\tnop\n");
1207 output_asm_insn ("bra\t%l0", operands
);
1208 fprintf (asm_out_file
, "\tnop\n");
1209 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LF", label
);
1213 /* When relaxing, fall through. */
1218 sprintf (buffer
, "b%s%ss\t%%l0",
1220 ASSEMBLER_DIALECT
? "/" : ".");
1221 output_asm_insn (buffer
, &operands
[0]);
1226 /* There should be no longer branches now - that would
1227 indicate that something has destroyed the branches set
1228 up in machine_dependent_reorg. */
1234 output_branchy_insn (code
, template, insn
, operands
)
1236 const char *template;
1240 rtx next_insn
= NEXT_INSN (insn
);
1242 if (next_insn
&& GET_CODE (next_insn
) == JUMP_INSN
&& condjump_p (next_insn
))
1244 rtx src
= SET_SRC (PATTERN (next_insn
));
1245 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
1247 /* Following branch not taken */
1248 operands
[9] = gen_label_rtx ();
1249 emit_label_after (operands
[9], next_insn
);
1250 INSN_ADDRESSES_NEW (operands
[9],
1251 INSN_ADDRESSES (INSN_UID (next_insn
))
1252 + get_attr_length (next_insn
));
1257 int offset
= (branch_dest (next_insn
)
1258 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
1259 if (offset
>= -252 && offset
<= 258)
1261 if (GET_CODE (src
) == IF_THEN_ELSE
)
1263 src
= XEXP (src
, 1);
1269 operands
[9] = gen_label_rtx ();
1270 emit_label_after (operands
[9], insn
);
1271 INSN_ADDRESSES_NEW (operands
[9],
1272 INSN_ADDRESSES (INSN_UID (insn
))
1273 + get_attr_length (insn
));
1278 output_ieee_ccmpeq (insn
, operands
)
1279 rtx insn
, *operands
;
1281 return output_branchy_insn (NE
, "bt\t%l9\\;fcmp/eq\t%1,%0", insn
, operands
);
1284 /* Output to FILE the start of the assembler file. */
1287 output_file_start (file
)
1290 output_file_directive (file
, main_input_filename
);
1292 /* Switch to the data section so that the coffsem symbol
1293 isn't in the text section. */
1296 if (TARGET_LITTLE_ENDIAN
)
1297 fprintf (file
, "\t.little\n");
1299 if (TARGET_SHCOMPACT
)
1300 fprintf (file
, "\t.mode\tSHcompact\n");
1301 else if (TARGET_SHMEDIA
)
1302 fprintf (file
, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1303 TARGET_SHMEDIA64
? 64 : 32);
1306 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
1309 unspec_caller_rtx_p (pat
)
1312 switch (GET_CODE (pat
))
1315 return unspec_caller_rtx_p (XEXP (pat
, 0));
1318 if (unspec_caller_rtx_p (XEXP (pat
, 0)))
1320 return unspec_caller_rtx_p (XEXP (pat
, 1));
1322 if (XINT (pat
, 1) == UNSPEC_CALLER
)
1331 /* Indicate that INSN cannot be duplicated. This is true for insn
1332 that generates an unique label. */
1335 sh_cannot_copy_insn_p (insn
)
1340 if (!reload_completed
|| !flag_pic
)
1343 if (GET_CODE (insn
) != INSN
)
1345 if (asm_noperands (insn
) >= 0)
1348 pat
= PATTERN (insn
);
1349 if (GET_CODE (pat
) != SET
)
1351 pat
= SET_SRC (pat
);
1353 if (unspec_caller_rtx_p (pat
))
1359 /* Actual number of instructions used to make a shift by N. */
1360 static const char ashiftrt_insns
[] =
1361 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1363 /* Left shift and logical right shift are the same. */
1364 static const char shift_insns
[] =
1365 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1367 /* Individual shift amounts needed to get the above length sequences.
1368 One bit right shifts clobber the T bit, so when possible, put one bit
1369 shifts in the middle of the sequence, so the ends are eligible for
1370 branch delay slots. */
1371 static const short shift_amounts
[32][5] = {
1372 {0}, {1}, {2}, {2, 1},
1373 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1374 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1375 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1376 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1377 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1378 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1379 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1381 /* Likewise, but for shift amounts < 16, up to three highmost bits
1382 might be clobbered. This is typically used when combined with some
1383 kind of sign or zero extension. */
1385 static const char ext_shift_insns
[] =
1386 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1388 static const short ext_shift_amounts
[32][4] = {
1389 {0}, {1}, {2}, {2, 1},
1390 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1391 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1392 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1393 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1394 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1395 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1396 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1398 /* Assuming we have a value that has been sign-extended by at least one bit,
1399 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1400 to shift it by N without data loss, and quicker than by other means? */
1401 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1403 /* This is used in length attributes in sh.md to help compute the length
1404 of arbitrary constant shift instructions. */
1407 shift_insns_rtx (insn
)
1410 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1411 int shift_count
= INTVAL (XEXP (set_src
, 1));
1412 enum rtx_code shift_code
= GET_CODE (set_src
);
1417 return ashiftrt_insns
[shift_count
];
1420 return shift_insns
[shift_count
];
1426 /* Return the cost of a shift. */
1437 if (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
1439 if (GET_MODE (x
) == DImode
1440 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1441 && INTVAL (XEXP (x
, 1)) == 1)
1444 /* Everything else is invalid, because there is no pattern for it. */
1447 /* If shift by a non constant, then this will be expensive. */
1448 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1449 return SH_DYNAMIC_SHIFT_COST
;
1451 value
= INTVAL (XEXP (x
, 1));
1453 /* Otherwise, return the true cost in instructions. */
1454 if (GET_CODE (x
) == ASHIFTRT
)
1456 int cost
= ashiftrt_insns
[value
];
1457 /* If SH3, then we put the constant in a reg and use shad. */
1458 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
1459 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
1463 return shift_insns
[value
];
1466 /* Return the cost of an AND operation. */
1474 /* Anding with a register is a single cycle and instruction. */
1475 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1478 i
= INTVAL (XEXP (x
, 1));
1482 if ((GET_CODE (XEXP (x
, 1)) == CONST_INT
1483 && CONST_OK_FOR_J (INTVAL (XEXP (x
, 1))))
1484 || EXTRA_CONSTRAINT_S (XEXP (x
, 1)))
1490 /* These constants are single cycle extu.[bw] instructions. */
1491 if (i
== 0xff || i
== 0xffff)
1493 /* Constants that can be used in an and immediate instruction is a single
1494 cycle, but this requires r0, so make it a little more expensive. */
1495 if (CONST_OK_FOR_L (i
))
1497 /* Constants that can be loaded with a mov immediate and an and.
1498 This case is probably unnecessary. */
1499 if (CONST_OK_FOR_I (i
))
1501 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1502 This case is probably unnecessary. */
1506 /* Return the cost of an addition or a subtraction. */
1512 /* Adding a register is a single cycle insn. */
1513 if (GET_CODE (XEXP (x
, 1)) == REG
1514 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1517 /* Likewise for small constants. */
1518 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1519 && CONST_OK_FOR_ADD (INTVAL (XEXP (x
, 1))))
1523 switch (GET_CODE (XEXP (x
, 1)))
1528 return TARGET_SHMEDIA64
? 5 : 3;
1531 if (CONST_OK_FOR_J (INTVAL (XEXP (x
, 1))))
1533 else if (CONST_OK_FOR_J (INTVAL (XEXP (x
, 1)) >> 16))
1535 else if (CONST_OK_FOR_J ((INTVAL (XEXP (x
, 1)) >> 16) >> 16))
1543 /* Any other constant requires a 2 cycle pc-relative load plus an
1548 /* Return the cost of a multiply. */
1551 rtx x ATTRIBUTE_UNUSED
;
1558 /* We have a mul insn, so we can never take more than the mul and the
1559 read of the mac reg, but count more because of the latency and extra
1561 if (TARGET_SMALLCODE
)
1566 /* If we're aiming at small code, then just count the number of
1567 insns in a multiply call sequence. */
1568 if (TARGET_SMALLCODE
)
1571 /* Otherwise count all the insns in the routine we'd be calling too. */
1575 /* Compute a (partial) cost for rtx X. Return true if the complete
1576 cost has been computed, and false if subexpressions should be
1577 scanned. In either case, *TOTAL contains the cost result. */
1580 sh_rtx_costs (x
, code
, outer_code
, total
)
1582 int code
, outer_code
, *total
;
1589 if (INTVAL (x
) == 0)
1591 else if (outer_code
== AND
&& and_operand ((x
), DImode
))
1593 else if ((outer_code
== IOR
|| outer_code
== XOR
1594 || outer_code
== PLUS
)
1595 && CONST_OK_FOR_P (INTVAL (x
)))
1597 else if (CONST_OK_FOR_J (INTVAL (x
)))
1598 *total
= COSTS_N_INSNS (outer_code
!= SET
);
1599 else if (CONST_OK_FOR_J (INTVAL (x
) >> 16))
1600 *total
= COSTS_N_INSNS (2);
1601 else if (CONST_OK_FOR_J ((INTVAL (x
) >> 16) >> 16))
1602 *total
= COSTS_N_INSNS (3);
1604 *total
= COSTS_N_INSNS (4);
1607 if (CONST_OK_FOR_I (INTVAL (x
)))
1609 else if ((outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
1610 && CONST_OK_FOR_L (INTVAL (x
)))
1619 if (TARGET_SHMEDIA64
)
1620 *total
= COSTS_N_INSNS (4);
1621 else if (TARGET_SHMEDIA32
)
1622 *total
= COSTS_N_INSNS (2);
1629 *total
= COSTS_N_INSNS (4);
1635 *total
= COSTS_N_INSNS (addsubcosts (x
));
1639 *total
= COSTS_N_INSNS (andcosts (x
));
1643 *total
= COSTS_N_INSNS (multcosts (x
));
1649 *total
= COSTS_N_INSNS (shiftcosts (x
));
1656 *total
= COSTS_N_INSNS (20);
1669 /* Compute the cost of an address. For the SH, all valid addresses are
1670 the same cost. Use a slightly higher cost for reg + reg addressing,
1671 since it increases pressure on r0. */
1677 return (GET_CODE (X
) == PLUS
1678 && ! CONSTANT_P (XEXP (X
, 1))
1679 && ! TARGET_SHMEDIA
? 1 : 0);
1682 /* Code to expand a shift. */
1685 gen_ashift (type
, n
, reg
)
1690 /* Negative values here come from the shift_amounts array. */
1703 emit_insn (gen_ashrsi3_k (reg
, reg
, GEN_INT (n
)));
1707 emit_insn (gen_lshrsi3_m (reg
, reg
, GEN_INT (n
)));
1709 emit_insn (gen_lshrsi3_k (reg
, reg
, GEN_INT (n
)));
1712 emit_insn (gen_ashlsi3_std (reg
, reg
, GEN_INT (n
)));
1717 /* Same for HImode */
1720 gen_ashift_hi (type
, n
, reg
)
1725 /* Negative values here come from the shift_amounts array. */
1739 /* We don't have HImode right shift operations because using the
1740 ordinary 32 bit shift instructions for that doesn't generate proper
1741 zero/sign extension.
1742 gen_ashift_hi is only called in contexts where we know that the
1743 sign extension works out correctly. */
1746 if (GET_CODE (reg
) == SUBREG
)
1748 offset
= SUBREG_BYTE (reg
);
1749 reg
= SUBREG_REG (reg
);
1751 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
1755 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
1760 /* Output RTL to split a constant shift into its component SH constant
1761 shift instructions. */
1764 gen_shifty_op (code
, operands
)
1768 int value
= INTVAL (operands
[2]);
1771 /* Truncate the shift count in case it is out of bounds. */
1772 value
= value
& 0x1f;
1776 if (code
== LSHIFTRT
)
1778 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
1779 emit_insn (gen_movt (operands
[0]));
1782 else if (code
== ASHIFT
)
1784 /* There is a two instruction sequence for 31 bit left shifts,
1785 but it requires r0. */
1786 if (GET_CODE (operands
[0]) == REG
&& REGNO (operands
[0]) == 0)
1788 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
1789 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
1794 else if (value
== 0)
1796 /* This can happen when not optimizing. We must output something here
1797 to prevent the compiler from aborting in final.c after the try_split
1799 emit_insn (gen_nop ());
1803 max
= shift_insns
[value
];
1804 for (i
= 0; i
< max
; i
++)
1805 gen_ashift (code
, shift_amounts
[value
][i
], operands
[0]);
1808 /* Same as above, but optimized for values where the topmost bits don't
1812 gen_shifty_hi_op (code
, operands
)
1816 int value
= INTVAL (operands
[2]);
1818 void (*gen_fun
) PARAMS ((int, int, rtx
));
1820 /* This operation is used by and_shl for SImode values with a few
1821 high bits known to be cleared. */
1825 emit_insn (gen_nop ());
1829 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
1832 max
= ext_shift_insns
[value
];
1833 for (i
= 0; i
< max
; i
++)
1834 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1837 /* When shifting right, emit the shifts in reverse order, so that
1838 solitary negative values come first. */
1839 for (i
= ext_shift_insns
[value
] - 1; i
>= 0; i
--)
1840 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1843 /* Output RTL for an arithmetic right shift. */
1845 /* ??? Rewrite to use super-optimizer sequences. */
1848 expand_ashiftrt (operands
)
1859 if (GET_CODE (operands
[2]) != CONST_INT
)
1861 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
1862 emit_insn (gen_negsi2 (count
, count
));
1863 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1866 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
1867 > 1 + SH_DYNAMIC_SHIFT_COST
)
1870 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
1871 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1875 if (GET_CODE (operands
[2]) != CONST_INT
)
1878 value
= INTVAL (operands
[2]) & 31;
1882 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
1885 else if (value
>= 16 && value
<= 19)
1887 wrk
= gen_reg_rtx (SImode
);
1888 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
1891 gen_ashift (ASHIFTRT
, 1, wrk
);
1892 emit_move_insn (operands
[0], wrk
);
1895 /* Expand a short sequence inline, longer call a magic routine. */
1896 else if (value
<= 5)
1898 wrk
= gen_reg_rtx (SImode
);
1899 emit_move_insn (wrk
, operands
[1]);
1901 gen_ashift (ASHIFTRT
, 1, wrk
);
1902 emit_move_insn (operands
[0], wrk
);
1906 wrk
= gen_reg_rtx (Pmode
);
1908 /* Load the value into an arg reg and call a helper. */
1909 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
1910 sprintf (func
, "__ashiftrt_r4_%d", value
);
1911 func_name
= get_identifier (func
);
1912 sym
= function_symbol (IDENTIFIER_POINTER (func_name
));
1913 emit_move_insn (wrk
, sym
);
1914 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
1915 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
1920 sh_dynamicalize_shift_p (count
)
1923 return shift_insns
[INTVAL (count
)] > 1 + SH_DYNAMIC_SHIFT_COST
;
1926 /* Try to find a good way to implement the combiner pattern
1927 [(set (match_operand:SI 0 "register_operand" "r")
1928 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1929 (match_operand:SI 2 "const_int_operand" "n"))
1930 (match_operand:SI 3 "const_int_operand" "n"))) .
1931 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1932 return 0 for simple right / left or left/right shift combination.
1933 return 1 for a combination of shifts with zero_extend.
1934 return 2 for a combination of shifts with an AND that needs r0.
1935 return 3 for a combination of shifts with an AND that needs an extra
1936 scratch register, when the three highmost bits of the AND mask are clear.
1937 return 4 for a combination of shifts with an AND that needs an extra
1938 scratch register, when any of the three highmost bits of the AND mask
1940 If ATTRP is set, store an initial right shift width in ATTRP[0],
1941 and the instruction length in ATTRP[1] . These values are not valid
1943 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1944 shift_amounts for the last shift value that is to be used before the
1947 shl_and_kind (left_rtx
, mask_rtx
, attrp
)
1948 rtx left_rtx
, mask_rtx
;
1951 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
1952 int left
= INTVAL (left_rtx
), right
;
1954 int cost
, best_cost
= 10000;
1955 int best_right
= 0, best_len
= 0;
1959 if (left
< 0 || left
> 31)
1961 if (GET_CODE (mask_rtx
) == CONST_INT
)
1962 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
1964 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
1965 /* Can this be expressed as a right shift / left shift pair ? */
1966 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
1967 right
= exact_log2 (lsb
);
1968 mask2
= ~(mask
+ lsb
- 1);
1969 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
1970 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1972 best_cost
= shift_insns
[right
] + shift_insns
[right
+ left
];
1973 /* mask has no trailing zeroes <==> ! right */
1974 else if (! right
&& mask2
== ~(lsb2
- 1))
1976 int late_right
= exact_log2 (lsb2
);
1977 best_cost
= shift_insns
[left
+ late_right
] + shift_insns
[late_right
];
1979 /* Try to use zero extend */
1980 if (mask2
== ~(lsb2
- 1))
1984 for (width
= 8; width
<= 16; width
+= 8)
1986 /* Can we zero-extend right away? */
1987 if (lsb2
== (unsigned HOST_WIDE_INT
)1 << width
)
1990 = 1 + ext_shift_insns
[right
] + ext_shift_insns
[left
+ right
];
1991 if (cost
< best_cost
)
2002 /* ??? Could try to put zero extend into initial right shift,
2003 or even shift a bit left before the right shift. */
2004 /* Determine value of first part of left shift, to get to the
2005 zero extend cut-off point. */
2006 first
= width
- exact_log2 (lsb2
) + right
;
2007 if (first
>= 0 && right
+ left
- first
>= 0)
2009 cost
= ext_shift_insns
[right
] + ext_shift_insns
[first
] + 1
2010 + ext_shift_insns
[right
+ left
- first
];
2011 if (cost
< best_cost
)
2023 /* Try to use r0 AND pattern */
2024 for (i
= 0; i
<= 2; i
++)
2028 if (! CONST_OK_FOR_L (mask
>> i
))
2030 cost
= (i
!= 0) + 2 + ext_shift_insns
[left
+ i
];
2031 if (cost
< best_cost
)
2036 best_len
= cost
- 1;
2039 /* Try to use a scratch register to hold the AND operand. */
2040 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
)3 << 30)) == 0;
2041 for (i
= 0; i
<= 2; i
++)
2045 cost
= (i
!= 0) + (CONST_OK_FOR_I (mask
>> i
) ? 2 : 3)
2046 + (can_ext
? ext_shift_insns
: shift_insns
)[left
+ i
];
2047 if (cost
< best_cost
)
2052 best_len
= cost
- 1 - ! CONST_OK_FOR_I (mask
>> i
);
2058 attrp
[0] = best_right
;
2059 attrp
[1] = best_len
;
2064 /* This is used in length attributes of the unnamed instructions
2065 corresponding to shl_and_kind return values of 1 and 2. */
2067 shl_and_length (insn
)
2070 rtx set_src
, left_rtx
, mask_rtx
;
2073 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
2074 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
2075 mask_rtx
= XEXP (set_src
, 1);
2076 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
2077 return attributes
[1];
2080 /* This is used in length attribute of the and_shl_scratch instruction. */
2083 shl_and_scr_length (insn
)
2086 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
2087 int len
= shift_insns
[INTVAL (XEXP (set_src
, 1))];
2088 rtx op
= XEXP (set_src
, 0);
2089 len
+= shift_insns
[INTVAL (XEXP (op
, 1))] + 1;
2090 op
= XEXP (XEXP (op
, 0), 0);
2091 return len
+ shift_insns
[INTVAL (XEXP (op
, 1))];
2094 /* Generating rtl? */
2095 extern int rtx_equal_function_value_matters
;
2097 /* Generate rtl for instructions for which shl_and_kind advised a particular
2098 method of generating them, i.e. returned zero. */
2101 gen_shl_and (dest
, left_rtx
, mask_rtx
, source
)
2102 rtx dest
, left_rtx
, mask_rtx
, source
;
2105 unsigned HOST_WIDE_INT mask
;
2106 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
2107 int right
, total_shift
;
2108 void (*shift_gen_fun
) PARAMS ((int, rtx
*)) = gen_shifty_hi_op
;
2110 right
= attributes
[0];
2111 total_shift
= INTVAL (left_rtx
) + right
;
2112 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
2119 int first
= attributes
[2];
2124 emit_insn ((mask
<< right
) <= 0xff
2125 ? gen_zero_extendqisi2(dest
,
2126 gen_lowpart (QImode
, source
))
2127 : gen_zero_extendhisi2(dest
,
2128 gen_lowpart (HImode
, source
)));
2132 emit_insn (gen_movsi (dest
, source
));
2136 operands
[2] = GEN_INT (right
);
2137 gen_shifty_hi_op (LSHIFTRT
, operands
);
2141 operands
[2] = GEN_INT (first
);
2142 gen_shifty_hi_op (ASHIFT
, operands
);
2143 total_shift
-= first
;
2147 emit_insn (mask
<= 0xff
2148 ? gen_zero_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
2149 : gen_zero_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
2150 if (total_shift
> 0)
2152 operands
[2] = GEN_INT (total_shift
);
2153 gen_shifty_hi_op (ASHIFT
, operands
);
2158 shift_gen_fun
= gen_shifty_op
;
2160 /* If the topmost bit that matters is set, set the topmost bits
2161 that don't matter. This way, we might be able to get a shorter
2163 if (mask
& ((HOST_WIDE_INT
)1 << (31 - total_shift
)))
2164 mask
|= (HOST_WIDE_INT
)~0 << (31 - total_shift
);
2166 /* Don't expand fine-grained when combining, because that will
2167 make the pattern fail. */
2168 if (rtx_equal_function_value_matters
2169 || reload_in_progress
|| reload_completed
)
2173 /* Cases 3 and 4 should be handled by this split
2174 only while combining */
2179 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
2182 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
2187 operands
[2] = GEN_INT (total_shift
);
2188 shift_gen_fun (ASHIFT
, operands
);
2195 if (kind
!= 4 && total_shift
< 16)
2197 neg
= -ext_shift_amounts
[total_shift
][1];
2199 neg
-= ext_shift_amounts
[total_shift
][2];
2203 emit_insn (gen_and_shl_scratch (dest
, source
,
2206 GEN_INT (total_shift
+ neg
),
2208 emit_insn (gen_movsi (dest
, dest
));
2215 /* Try to find a good way to implement the combiner pattern
2216 [(set (match_operand:SI 0 "register_operand" "=r")
2217 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
2218 (match_operand:SI 2 "const_int_operand" "n")
2219 (match_operand:SI 3 "const_int_operand" "n")
2221 (clobber (reg:SI T_REG))]
2222 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
2223 return 0 for simple left / right shift combination.
2224 return 1 for left shift / 8 bit sign extend / left shift.
2225 return 2 for left shift / 16 bit sign extend / left shift.
2226 return 3 for left shift / 8 bit sign extend / shift / sign extend.
2227 return 4 for left shift / 16 bit sign extend / shift / sign extend.
2228 return 5 for left shift / 16 bit sign extend / right shift
2229 return 6 for < 8 bit sign extend / left shift.
2230 return 7 for < 8 bit sign extend / left shift / single right shift.
2231 If COSTP is nonzero, assign the calculated cost to *COSTP. */
2234 shl_sext_kind (left_rtx
, size_rtx
, costp
)
2235 rtx left_rtx
, size_rtx
;
2238 int left
, size
, insize
, ext
;
2239 int cost
= 0, best_cost
;
2242 left
= INTVAL (left_rtx
);
2243 size
= INTVAL (size_rtx
);
2244 insize
= size
- left
;
2247 /* Default to left / right shift. */
2249 best_cost
= shift_insns
[32 - insize
] + ashiftrt_insns
[32 - size
];
2252 /* 16 bit shift / sign extend / 16 bit shift */
2253 cost
= shift_insns
[16 - insize
] + 1 + ashiftrt_insns
[16 - size
];
2254 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
2255 below, by alternative 3 or something even better. */
2256 if (cost
< best_cost
)
2262 /* Try a plain sign extend between two shifts. */
2263 for (ext
= 16; ext
>= insize
; ext
-= 8)
2267 cost
= ext_shift_insns
[ext
- insize
] + 1 + shift_insns
[size
- ext
];
2268 if (cost
< best_cost
)
2270 kind
= ext
/ (unsigned) 8;
2274 /* Check if we can do a sloppy shift with a final signed shift
2275 restoring the sign. */
2276 if (EXT_SHIFT_SIGNED (size
- ext
))
2277 cost
= ext_shift_insns
[ext
- insize
] + ext_shift_insns
[size
- ext
] + 1;
2278 /* If not, maybe it's still cheaper to do the second shift sloppy,
2279 and do a final sign extend? */
2280 else if (size
<= 16)
2281 cost
= ext_shift_insns
[ext
- insize
] + 1
2282 + ext_shift_insns
[size
> ext
? size
- ext
: ext
- size
] + 1;
2285 if (cost
< best_cost
)
2287 kind
= ext
/ (unsigned) 8 + 2;
2291 /* Check if we can sign extend in r0 */
2294 cost
= 3 + shift_insns
[left
];
2295 if (cost
< best_cost
)
2300 /* Try the same with a final signed shift. */
2303 cost
= 3 + ext_shift_insns
[left
+ 1] + 1;
2304 if (cost
< best_cost
)
2313 /* Try to use a dynamic shift. */
2314 cost
= shift_insns
[32 - insize
] + 1 + SH_DYNAMIC_SHIFT_COST
;
2315 if (cost
< best_cost
)
2326 /* Function to be used in the length attribute of the instructions
2327 implementing this pattern. */
2330 shl_sext_length (insn
)
2333 rtx set_src
, left_rtx
, size_rtx
;
2336 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
2337 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
2338 size_rtx
= XEXP (set_src
, 1);
2339 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2343 /* Generate rtl for this pattern */
2346 gen_shl_sext (dest
, left_rtx
, size_rtx
, source
)
2347 rtx dest
, left_rtx
, size_rtx
, source
;
2350 int left
, size
, insize
, cost
;
2353 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2354 left
= INTVAL (left_rtx
);
2355 size
= INTVAL (size_rtx
);
2356 insize
= size
- left
;
2364 int ext
= kind
& 1 ? 8 : 16;
2365 int shift2
= size
- ext
;
2367 /* Don't expand fine-grained when combining, because that will
2368 make the pattern fail. */
2369 if (! rtx_equal_function_value_matters
2370 && ! reload_in_progress
&& ! reload_completed
)
2372 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2373 emit_insn (gen_movsi (dest
, source
));
2377 emit_insn (gen_movsi (dest
, source
));
2381 operands
[2] = GEN_INT (ext
- insize
);
2382 gen_shifty_hi_op (ASHIFT
, operands
);
2385 ? gen_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
2386 : gen_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
2391 operands
[2] = GEN_INT (shift2
);
2392 gen_shifty_op (ASHIFT
, operands
);
2399 if (EXT_SHIFT_SIGNED (shift2
))
2401 operands
[2] = GEN_INT (shift2
+ 1);
2402 gen_shifty_op (ASHIFT
, operands
);
2403 operands
[2] = GEN_INT (1);
2404 gen_shifty_op (ASHIFTRT
, operands
);
2407 operands
[2] = GEN_INT (shift2
);
2408 gen_shifty_hi_op (ASHIFT
, operands
);
2412 operands
[2] = GEN_INT (-shift2
);
2413 gen_shifty_hi_op (LSHIFTRT
, operands
);
2415 emit_insn (size
<= 8
2416 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
2417 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2424 if (! rtx_equal_function_value_matters
2425 && ! reload_in_progress
&& ! reload_completed
)
2426 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2430 operands
[2] = GEN_INT (16 - insize
);
2431 gen_shifty_hi_op (ASHIFT
, operands
);
2432 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2434 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2436 gen_ashift (ASHIFTRT
, 1, dest
);
2441 /* Don't expand fine-grained when combining, because that will
2442 make the pattern fail. */
2443 if (! rtx_equal_function_value_matters
2444 && ! reload_in_progress
&& ! reload_completed
)
2446 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2447 emit_insn (gen_movsi (dest
, source
));
2450 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
2451 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
2452 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
2454 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
2455 gen_shifty_op (ASHIFT
, operands
);
2457 emit_insn (gen_ashrsi3_k (dest
, dest
, GEN_INT (1)));
2465 /* Prefix a symbol_ref name with "datalabel". */
2468 gen_datalabel_ref (sym
)
2471 if (GET_CODE (sym
) == LABEL_REF
)
2472 return gen_rtx_CONST (GET_MODE (sym
),
2473 gen_rtx_UNSPEC (GET_MODE (sym
),
2477 if (GET_CODE (sym
) != SYMBOL_REF
)
2484 /* The SH cannot load a large constant into a register, constants have to
2485 come from a pc relative load. The reference of a pc relative load
2486 instruction must be less than 1k infront of the instruction. This
2487 means that we often have to dump a constant inside a function, and
2488 generate code to branch around it.
2490 It is important to minimize this, since the branches will slow things
2491 down and make things bigger.
2493 Worst case code looks like:
2511 We fix this by performing a scan before scheduling, which notices which
2512 instructions need to have their operands fetched from the constant table
2513 and builds the table.
2517 scan, find an instruction which needs a pcrel move. Look forward, find the
2518 last barrier which is within MAX_COUNT bytes of the requirement.
2519 If there isn't one, make one. Process all the instructions between
2520 the find and the barrier.
2522 In the above example, we can tell that L3 is within 1k of L1, so
2523 the first move can be shrunk from the 3 insn+constant sequence into
2524 just 1 insn, and the constant moved to L3 to make:
2535 Then the second move becomes the target for the shortening process. */
2539 rtx value
; /* Value in table. */
2540 rtx label
; /* Label of value. */
2541 rtx wend
; /* End of window. */
2542 enum machine_mode mode
; /* Mode of value. */
2544 /* True if this constant is accessed as part of a post-increment
2545 sequence. Note that HImode constants are never accessed in this way. */
2546 bool part_of_sequence_p
;
2549 /* The maximum number of constants that can fit into one pool, since
2550 the pc relative range is 0...1020 bytes and constants are at least 4
2553 #define MAX_POOL_SIZE (1020/4)
2554 static pool_node pool_vector
[MAX_POOL_SIZE
];
2555 static int pool_size
;
2556 static rtx pool_window_label
;
2557 static int pool_window_last
;
2559 /* ??? If we need a constant in HImode which is the truncated value of a
2560 constant we need in SImode, we could combine the two entries thus saving
2561 two bytes. Is this common enough to be worth the effort of implementing
2564 /* ??? This stuff should be done at the same time that we shorten branches.
2565 As it is now, we must assume that all branches are the maximum size, and
2566 this causes us to almost always output constant pools sooner than
2569 /* Add a constant to the pool and return its label. */
2572 add_constant (x
, mode
, last_value
)
2574 enum machine_mode mode
;
2578 rtx lab
, new, ref
, newref
;
2580 /* First see if we've already got it. */
2581 for (i
= 0; i
< pool_size
; i
++)
2583 if (x
->code
== pool_vector
[i
].value
->code
2584 && mode
== pool_vector
[i
].mode
)
2586 if (x
->code
== CODE_LABEL
)
2588 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
2591 if (rtx_equal_p (x
, pool_vector
[i
].value
))
2596 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
2598 new = gen_label_rtx ();
2599 LABEL_REFS (new) = pool_vector
[i
].label
;
2600 pool_vector
[i
].label
= lab
= new;
2602 if (lab
&& pool_window_label
)
2604 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2605 ref
= pool_vector
[pool_window_last
].wend
;
2606 LABEL_NEXTREF (newref
) = ref
;
2607 pool_vector
[pool_window_last
].wend
= newref
;
2610 pool_window_label
= new;
2611 pool_window_last
= i
;
2617 /* Need a new one. */
2618 pool_vector
[pool_size
].value
= x
;
2619 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
2622 pool_vector
[pool_size
- 1].part_of_sequence_p
= true;
2625 lab
= gen_label_rtx ();
2626 pool_vector
[pool_size
].mode
= mode
;
2627 pool_vector
[pool_size
].label
= lab
;
2628 pool_vector
[pool_size
].wend
= NULL_RTX
;
2629 pool_vector
[pool_size
].part_of_sequence_p
= (lab
== 0);
2630 if (lab
&& pool_window_label
)
2632 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2633 ref
= pool_vector
[pool_window_last
].wend
;
2634 LABEL_NEXTREF (newref
) = ref
;
2635 pool_vector
[pool_window_last
].wend
= newref
;
2638 pool_window_label
= lab
;
2639 pool_window_last
= pool_size
;
2644 /* Output the literal table. */
2655 /* Do two passes, first time dump out the HI sized constants. */
2657 for (i
= 0; i
< pool_size
; i
++)
2659 pool_node
*p
= &pool_vector
[i
];
2661 if (p
->mode
== HImode
)
2665 scan
= emit_insn_after (gen_align_2 (), scan
);
2668 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2669 scan
= emit_label_after (lab
, scan
);
2670 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
2672 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2674 lab
= XEXP (ref
, 0);
2675 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2678 else if (p
->mode
== DFmode
)
2684 if (TARGET_FMOVD
&& TARGET_ALIGN_DOUBLE
&& have_df
)
2686 rtx align_insn
= NULL_RTX
;
2688 scan
= emit_label_after (gen_label_rtx (), scan
);
2689 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2692 for (i
= 0; i
< pool_size
; i
++)
2694 pool_node
*p
= &pool_vector
[i
];
2702 if (align_insn
&& !p
->part_of_sequence_p
)
2704 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2705 emit_label_before (lab
, align_insn
);
2706 emit_insn_before (gen_consttable_4 (p
->value
, const0_rtx
),
2708 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2710 lab
= XEXP (ref
, 0);
2711 emit_insn_before (gen_consttable_window_end (lab
),
2714 delete_insn (align_insn
);
2715 align_insn
= NULL_RTX
;
2720 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2721 scan
= emit_label_after (lab
, scan
);
2722 scan
= emit_insn_after (gen_consttable_4 (p
->value
,
2724 need_align
= ! need_align
;
2730 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2735 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2736 scan
= emit_label_after (lab
, scan
);
2737 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2745 if (p
->mode
!= HImode
)
2747 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2749 lab
= XEXP (ref
, 0);
2750 scan
= emit_insn_after (gen_consttable_window_end (lab
),
2759 for (i
= 0; i
< pool_size
; i
++)
2761 pool_node
*p
= &pool_vector
[i
];
2772 scan
= emit_label_after (gen_label_rtx (), scan
);
2773 scan
= emit_insn_after (gen_align_4 (), scan
);
2775 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2776 scan
= emit_label_after (lab
, scan
);
2777 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
2785 scan
= emit_label_after (gen_label_rtx (), scan
);
2786 scan
= emit_insn_after (gen_align_4 (), scan
);
2788 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2789 scan
= emit_label_after (lab
, scan
);
2790 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2798 if (p
->mode
!= HImode
)
2800 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2802 lab
= XEXP (ref
, 0);
2803 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2808 scan
= emit_insn_after (gen_consttable_end (), scan
);
2809 scan
= emit_barrier_after (scan
);
2811 pool_window_label
= NULL_RTX
;
2812 pool_window_last
= 0;
2815 /* Return nonzero if constant would be an ok source for a
2816 mov.w instead of a mov.l. */
2822 return (GET_CODE (src
) == CONST_INT
2823 && INTVAL (src
) >= -32768
2824 && INTVAL (src
) <= 32767);
2827 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2829 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2830 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2831 need to fix it if the input value is CONST_OK_FOR_I. */
2837 if (GET_CODE (insn
) == INSN
)
2839 rtx pat
= PATTERN (insn
);
2840 if (GET_CODE (pat
) == PARALLEL
)
2841 pat
= XVECEXP (pat
, 0, 0);
2842 if (GET_CODE (pat
) == SET
2843 /* We can load any 8 bit value if we don't care what the high
2844 order bits end up as. */
2845 && GET_MODE (SET_DEST (pat
)) != QImode
2846 && (CONSTANT_P (SET_SRC (pat
))
2847 /* Match mova_const. */
2848 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
2849 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
2850 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
2852 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
2853 && (fp_zero_operand (SET_SRC (pat
))
2854 || fp_one_operand (SET_SRC (pat
)))
2855 /* ??? If this is a -m4 or -m4-single compilation, in general
2856 we don't know the current setting of fpscr, so disable fldi.
2857 There is an exception if this was a register-register move
2858 before reload - and hence it was ascertained that we have
2859 single precision setting - and in a post-reload optimization
2860 we changed this to do a constant load. In that case
2861 we don't have an r0 clobber, hence we must use fldi. */
2862 && (! TARGET_SH4
|| TARGET_FMOVD
2863 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn
), 0, 2), 0))
2865 && GET_CODE (SET_DEST (pat
)) == REG
2866 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
2867 && (GET_CODE (SET_SRC (pat
)) != CONST_INT
2868 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat
)))))
2879 return (GET_CODE (insn
) == INSN
2880 && GET_CODE (PATTERN (insn
)) == SET
2881 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
2882 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
2883 /* Don't match mova_const. */
2884 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn
)), 0, 0)) == LABEL_REF
);
2887 /* Find the last barrier from insn FROM which is close enough to hold the
2888 constant pool. If we can't find one, then create one near the end of
2892 find_barrier (num_mova
, mova
, from
)
2903 int leading_mova
= num_mova
;
2904 rtx barrier_before_mova
= 0, found_barrier
= 0, good_barrier
= 0;
2908 /* For HImode: range is 510, add 4 because pc counts from address of
2909 second instruction after this one, subtract 2 for the jump instruction
2910 that we may need to emit before the table, subtract 2 for the instruction
2911 that fills the jump delay slot (in very rare cases, reorg will take an
2912 instruction from after the constant pool or will leave the delay slot
2913 empty). This gives 510.
2914 For SImode: range is 1020, add 4 because pc counts from address of
2915 second instruction after this one, subtract 2 in case pc is 2 byte
2916 aligned, subtract 2 for the jump instruction that we may need to emit
2917 before the table, subtract 2 for the instruction that fills the jump
2918 delay slot. This gives 1018. */
2920 /* The branch will always be shortened now that the reference address for
2921 forward branches is the successor address, thus we need no longer make
2922 adjustments to the [sh]i_limit for -O0. */
2927 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
2929 int inc
= get_attr_length (from
);
2932 if (GET_CODE (from
) == CODE_LABEL
)
2935 new_align
= 1 << label_to_alignment (from
);
2936 else if (GET_CODE (prev_nonnote_insn (from
)) == BARRIER
)
2937 new_align
= 1 << barrier_align (from
);
2943 if (GET_CODE (from
) == BARRIER
)
2946 found_barrier
= from
;
2948 /* If we are at the end of the function, or in front of an alignment
2949 instruction, we need not insert an extra alignment. We prefer
2950 this kind of barrier. */
2951 if (barrier_align (from
) > 2)
2952 good_barrier
= from
;
2955 if (broken_move (from
))
2958 enum machine_mode mode
;
2960 pat
= PATTERN (from
);
2961 if (GET_CODE (pat
) == PARALLEL
)
2962 pat
= XVECEXP (pat
, 0, 0);
2963 src
= SET_SRC (pat
);
2964 dst
= SET_DEST (pat
);
2965 mode
= GET_MODE (dst
);
2967 /* We must explicitly check the mode, because sometimes the
2968 front end will generate code to load unsigned constants into
2969 HImode targets without properly sign extending them. */
2971 || (mode
== SImode
&& hi_const (src
) && REGNO (dst
) != FPUL_REG
))
2974 /* We put the short constants before the long constants, so
2975 we must count the length of short constants in the range
2976 for the long constants. */
2977 /* ??? This isn't optimal, but is easy to do. */
2982 /* We dump DF/DI constants before SF/SI ones, because
2983 the limit is the same, but the alignment requirements
2984 are higher. We may waste up to 4 additional bytes
2985 for alignment, and the DF/DI constant may have
2986 another SF/SI constant placed before it. */
2987 if (TARGET_SHCOMPACT
2989 && (mode
== DFmode
|| mode
== DImode
))
2994 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
2996 if (found_si
> count_si
)
2997 count_si
= found_si
;
2998 found_si
+= GET_MODE_SIZE (mode
);
3000 si_limit
-= GET_MODE_SIZE (mode
);
3003 /* See the code in machine_dependent_reorg, which has a similar if
3004 statement that generates a new mova insn in many cases. */
3005 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
3015 barrier_before_mova
= good_barrier
? good_barrier
: found_barrier
;
3017 if (found_si
> count_si
)
3018 count_si
= found_si
;
3020 else if (GET_CODE (from
) == JUMP_INSN
3021 && (GET_CODE (PATTERN (from
)) == ADDR_VEC
3022 || GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
))
3026 if (barrier_align (next_real_insn (from
)) == align_jumps_log
)
3028 /* We have just passed the barrier in front of the
3029 ADDR_DIFF_VEC, which is stored in found_barrier. Since
3030 the ADDR_DIFF_VEC is accessed as data, just like our pool
3031 constants, this is a good opportunity to accommodate what
3032 we have gathered so far.
3033 If we waited any longer, we could end up at a barrier in
3034 front of code, which gives worse cache usage for separated
3035 instruction / data caches. */
3036 good_barrier
= found_barrier
;
3041 rtx body
= PATTERN (from
);
3042 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
3045 /* For the SH1, we generate alignments even after jumps-around-jumps. */
3046 else if (GET_CODE (from
) == JUMP_INSN
3048 && ! TARGET_SMALLCODE
)
3054 if (new_align
> si_align
)
3056 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
3057 si_align
= new_align
;
3059 count_si
= (count_si
+ new_align
- 1) & -new_align
;
3064 if (new_align
> hi_align
)
3066 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
3067 hi_align
= new_align
;
3069 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
3071 from
= NEXT_INSN (from
);
3078 /* Try as we might, the leading mova is out of range. Change
3079 it into a load (which will become a pcload) and retry. */
3080 SET_SRC (PATTERN (mova
)) = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
3081 INSN_CODE (mova
) = -1;
3082 return find_barrier (0, 0, mova
);
3086 /* Insert the constant pool table before the mova instruction,
3087 to prevent the mova label reference from going out of range. */
3089 good_barrier
= found_barrier
= barrier_before_mova
;
3095 if (good_barrier
&& next_real_insn (found_barrier
))
3096 found_barrier
= good_barrier
;
3100 /* We didn't find a barrier in time to dump our stuff,
3101 so we'll make one. */
3102 rtx label
= gen_label_rtx ();
3104 /* If we exceeded the range, then we must back up over the last
3105 instruction we looked at. Otherwise, we just need to undo the
3106 NEXT_INSN at the end of the loop. */
3107 if (count_hi
> hi_limit
|| count_si
> si_limit
)
3108 from
= PREV_INSN (PREV_INSN (from
));
3110 from
= PREV_INSN (from
);
3112 /* Walk back to be just before any jump or label.
3113 Putting it before a label reduces the number of times the branch
3114 around the constant pool table will be hit. Putting it before
3115 a jump makes it more likely that the bra delay slot will be
3117 while (GET_CODE (from
) == JUMP_INSN
|| GET_CODE (from
) == NOTE
3118 || GET_CODE (from
) == CODE_LABEL
)
3119 from
= PREV_INSN (from
);
3121 from
= emit_jump_insn_after (gen_jump (label
), from
);
3122 JUMP_LABEL (from
) = label
;
3123 LABEL_NUSES (label
) = 1;
3124 found_barrier
= emit_barrier_after (from
);
3125 emit_label_after (label
, found_barrier
);
3128 return found_barrier
;
3131 /* If the instruction INSN is implemented by a special function, and we can
3132 positively find the register that is used to call the sfunc, and this
3133 register is not used anywhere else in this instruction - except as the
3134 destination of a set, return this register; else, return 0. */
3136 sfunc_uses_reg (insn
)
3140 rtx pattern
, part
, reg_part
, reg
;
3142 if (GET_CODE (insn
) != INSN
)
3144 pattern
= PATTERN (insn
);
3145 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
3148 for (reg_part
= 0, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
3150 part
= XVECEXP (pattern
, 0, i
);
3151 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
3156 reg
= XEXP (reg_part
, 0);
3157 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
3159 part
= XVECEXP (pattern
, 0, i
);
3160 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
3162 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
3163 && GET_CODE (SET_DEST (part
)) == REG
)
3164 ? SET_SRC (part
) : part
)))
3170 /* See if the only way in which INSN uses REG is by calling it, or by
3171 setting it while calling it. Set *SET to a SET rtx if the register
3175 noncall_uses_reg (reg
, insn
, set
)
3184 reg2
= sfunc_uses_reg (insn
);
3185 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
3187 pattern
= single_set (insn
);
3189 && GET_CODE (SET_DEST (pattern
)) == REG
3190 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
3194 if (GET_CODE (insn
) != CALL_INSN
)
3196 /* We don't use rtx_equal_p because we don't care if the mode is
3198 pattern
= single_set (insn
);
3200 && GET_CODE (SET_DEST (pattern
)) == REG
3201 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
3207 par
= PATTERN (insn
);
3208 if (GET_CODE (par
) == PARALLEL
)
3209 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
3211 part
= XVECEXP (par
, 0, i
);
3212 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
3215 return reg_mentioned_p (reg
, SET_SRC (pattern
));
3221 pattern
= PATTERN (insn
);
3223 if (GET_CODE (pattern
) == PARALLEL
)
3227 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
3228 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
3230 pattern
= XVECEXP (pattern
, 0, 0);
3233 if (GET_CODE (pattern
) == SET
)
3235 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
3237 /* We don't use rtx_equal_p, because we don't care if the
3238 mode is different. */
3239 if (GET_CODE (SET_DEST (pattern
)) != REG
3240 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
3246 pattern
= SET_SRC (pattern
);
3249 if (GET_CODE (pattern
) != CALL
3250 || GET_CODE (XEXP (pattern
, 0)) != MEM
3251 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
3257 /* Given a X, a pattern of an insn or a part of it, return a mask of used
3258 general registers. Bits 0..15 mean that the respective registers
3259 are used as inputs in the instruction. Bits 16..31 mean that the
3260 registers 0..15, respectively, are used as outputs, or are clobbered.
3261 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
3263 regs_used (x
, is_dest
)
3272 code
= GET_CODE (x
);
3277 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
3278 << (REGNO (x
) + is_dest
));
3282 rtx y
= SUBREG_REG (x
);
3284 if (GET_CODE (y
) != REG
)
3287 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
3289 subreg_regno_offset (REGNO (y
),
3292 GET_MODE (x
)) + is_dest
));
3296 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
3298 /* If there was a return value, it must have been indicated with USE. */
3313 fmt
= GET_RTX_FORMAT (code
);
3315 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3320 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3321 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
3323 else if (fmt
[i
] == 'e')
3324 used
|= regs_used (XEXP (x
, i
), is_dest
);
3329 /* Create an instruction that prevents redirection of a conditional branch
3330 to the destination of the JUMP with address ADDR.
3331 If the branch needs to be implemented as an indirect jump, try to find
3332 a scratch register for it.
3333 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3334 If any preceding insn that doesn't fit into a delay slot is good enough,
3335 pass 1. Pass 2 if a definite blocking insn is needed.
3336 -1 is used internally to avoid deep recursion.
3337 If a blocking instruction is made or recognized, return it. */
3340 gen_block_redirect (jump
, addr
, need_block
)
3342 int addr
, need_block
;
3345 rtx prev
= prev_nonnote_insn (jump
);
3348 /* First, check if we already have an instruction that satisfies our need. */
3349 if (prev
&& GET_CODE (prev
) == INSN
&& ! INSN_DELETED_P (prev
))
3351 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
3353 if (GET_CODE (PATTERN (prev
)) == USE
3354 || GET_CODE (PATTERN (prev
)) == CLOBBER
3355 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3357 else if ((need_block
&= ~1) < 0)
3359 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
3362 /* We can't use JUMP_LABEL here because it might be undefined
3363 when not optimizing. */
3364 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
3365 /* If the branch is out of range, try to find a scratch register for it. */
3367 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3371 /* Don't look for the stack pointer as a scratch register,
3372 it would cause trouble if an interrupt occurred. */
3373 unsigned try = 0x7fff, used
;
3374 int jump_left
= flag_expensive_optimizations
+ 1;
3376 /* It is likely that the most recent eligible instruction is wanted for
3377 the delay slot. Therefore, find out which registers it uses, and
3378 try to avoid using them. */
3380 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
3384 if (INSN_DELETED_P (scan
))
3386 code
= GET_CODE (scan
);
3387 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
3390 && GET_CODE (PATTERN (scan
)) != USE
3391 && GET_CODE (PATTERN (scan
)) != CLOBBER
3392 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
3394 try &= ~regs_used (PATTERN (scan
), 0);
3398 for (used
= dead
= 0, scan
= JUMP_LABEL (jump
);
3399 (scan
= NEXT_INSN (scan
)); )
3403 if (INSN_DELETED_P (scan
))
3405 code
= GET_CODE (scan
);
3406 if (GET_RTX_CLASS (code
) == 'i')
3408 used
|= regs_used (PATTERN (scan
), 0);
3409 if (code
== CALL_INSN
)
3410 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
3411 dead
|= (used
>> 16) & ~used
;
3417 if (code
== JUMP_INSN
)
3419 if (jump_left
-- && simplejump_p (scan
))
3420 scan
= JUMP_LABEL (scan
);
3426 /* Mask out the stack pointer again, in case it was
3427 the only 'free' register we have found. */
3430 /* If the immediate destination is still in range, check for possible
3431 threading with a jump beyond the delay slot insn.
3432 Don't check if we are called recursively; the jump has been or will be
3433 checked in a different invocation then. */
3435 else if (optimize
&& need_block
>= 0)
3437 rtx next
= next_active_insn (next_active_insn (dest
));
3438 if (next
&& GET_CODE (next
) == JUMP_INSN
3439 && GET_CODE (PATTERN (next
)) == SET
3440 && recog_memoized (next
) == CODE_FOR_jump_compact
)
3442 dest
= JUMP_LABEL (next
);
3444 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3446 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
3452 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
3454 /* It would be nice if we could convert the jump into an indirect
3455 jump / far branch right now, and thus exposing all constituent
3456 instructions to further optimization. However, reorg uses
3457 simplejump_p to determine if there is an unconditional jump where
3458 it should try to schedule instructions from the target of the
3459 branch; simplejump_p fails for indirect jumps even if they have
3461 rtx insn
= emit_insn_before (gen_indirect_jump_scratch
3462 (reg
, GEN_INT (INSN_UID (JUMP_LABEL (jump
))))
3464 /* ??? We would like this to have the scope of the jump, but that
3465 scope will change when a delay slot insn of an inner scope is added.
3466 Hence, after delay slot scheduling, we'll have to expect
3467 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
3470 INSN_LOCATOR (insn
) = INSN_LOCATOR (jump
);
3471 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
3474 else if (need_block
)
3475 /* We can't use JUMP_LABEL here because it might be undefined
3476 when not optimizing. */
3477 return emit_insn_before (gen_block_branch_redirect
3478 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))))
3483 #define CONDJUMP_MIN -252
3484 #define CONDJUMP_MAX 262
3487 /* A label (to be placed) in front of the jump
3488 that jumps to our ultimate destination. */
3490 /* Where we are going to insert it if we cannot move the jump any farther,
3491 or the jump itself if we have picked up an existing jump. */
3493 /* The ultimate destination. */
3495 struct far_branch
*prev
;
3496 /* If the branch has already been created, its address;
3497 else the address of its first prospective user. */
3501 static void gen_far_branch
PARAMS ((struct far_branch
*));
3502 enum mdep_reorg_phase_e mdep_reorg_phase
;
3505 struct far_branch
*bp
;
3507 rtx insn
= bp
->insert_place
;
3509 rtx label
= gen_label_rtx ();
3511 emit_label_after (label
, insn
);
3514 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
3515 LABEL_NUSES (bp
->far_label
)++;
3518 jump
= emit_jump_insn_after (gen_return (), insn
);
3519 /* Emit a barrier so that reorg knows that any following instructions
3520 are not reachable via a fall-through path.
3521 But don't do this when not optimizing, since we wouldn't supress the
3522 alignment for the barrier then, and could end up with out-of-range
3523 pc-relative loads. */
3525 emit_barrier_after (jump
);
3526 emit_label_after (bp
->near_label
, insn
);
3527 JUMP_LABEL (jump
) = bp
->far_label
;
3528 if (! invert_jump (insn
, label
, 1))
3531 (gen_stuff_delay_slot
3532 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))),
3533 GEN_INT (recog_memoized (insn
) == CODE_FOR_branch_false
)),
3535 /* Prevent reorg from undoing our splits. */
3536 gen_block_redirect (jump
, bp
->address
+= 2, 2);
3539 /* Fix up ADDR_DIFF_VECs. */
3541 fixup_addr_diff_vecs (first
)
3546 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3548 rtx vec_lab
, pat
, prev
, prevpat
, x
, braf_label
;
3550 if (GET_CODE (insn
) != JUMP_INSN
3551 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
3553 pat
= PATTERN (insn
);
3554 vec_lab
= XEXP (XEXP (pat
, 0), 0);
3556 /* Search the matching casesi_jump_2. */
3557 for (prev
= vec_lab
; ; prev
= PREV_INSN (prev
))
3559 if (GET_CODE (prev
) != JUMP_INSN
)
3561 prevpat
= PATTERN (prev
);
3562 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
3564 x
= XVECEXP (prevpat
, 0, 1);
3565 if (GET_CODE (x
) != USE
)
3568 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
3572 /* Emit the reference label of the braf where it belongs, right after
3573 the casesi_jump_2 (i.e. braf). */
3574 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
3575 emit_label_after (braf_label
, prev
);
3577 /* Fix up the ADDR_DIF_VEC to be relative
3578 to the reference address of the braf. */
3579 XEXP (XEXP (pat
, 0), 0) = braf_label
;
3583 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3584 a barrier. Return the base 2 logarithm of the desired alignment. */
3586 barrier_align (barrier_or_label
)
3587 rtx barrier_or_label
;
3589 rtx next
= next_real_insn (barrier_or_label
), pat
, prev
;
3590 int slot
, credit
, jump_to_next
= 0;
3595 pat
= PATTERN (next
);
3597 if (GET_CODE (pat
) == ADDR_DIFF_VEC
)
3600 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
3601 /* This is a barrier in front of a constant table. */
3604 prev
= prev_real_insn (barrier_or_label
);
3605 if (GET_CODE (PATTERN (prev
)) == ADDR_DIFF_VEC
)
3607 pat
= PATTERN (prev
);
3608 /* If this is a very small table, we want to keep the alignment after
3609 the table to the minimum for proper code alignment. */
3610 return ((TARGET_SMALLCODE
3611 || ((unsigned) XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
3612 <= (unsigned)1 << (CACHE_LOG
- 2)))
3613 ? 1 << TARGET_SHMEDIA
: align_jumps_log
);
3616 if (TARGET_SMALLCODE
)
3619 if (! TARGET_SH2
|| ! optimize
)
3620 return align_jumps_log
;
3622 /* When fixing up pcloads, a constant table might be inserted just before
3623 the basic block that ends with the barrier. Thus, we can't trust the
3624 instruction lengths before that. */
3625 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
3627 /* Check if there is an immediately preceding branch to the insn beyond
3628 the barrier. We must weight the cost of discarding useful information
3629 from the current cache line when executing this branch and there is
3630 an alignment, against that of fetching unneeded insn in front of the
3631 branch target when there is no alignment. */
3633 /* There are two delay_slot cases to consider. One is the simple case
3634 where the preceding branch is to the insn beyond the barrier (simple
3635 delay slot filling), and the other is where the preceding branch has
3636 a delay slot that is a duplicate of the insn after the barrier
3637 (fill_eager_delay_slots) and the branch is to the insn after the insn
3638 after the barrier. */
3640 /* PREV is presumed to be the JUMP_INSN for the barrier under
3641 investigation. Skip to the insn before it. */
3642 prev
= prev_real_insn (prev
);
3644 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
3645 credit
>= 0 && prev
&& GET_CODE (prev
) == INSN
;
3646 prev
= prev_real_insn (prev
))
3649 if (GET_CODE (PATTERN (prev
)) == USE
3650 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
3652 if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
3654 prev
= XVECEXP (PATTERN (prev
), 0, 1);
3655 if (INSN_UID (prev
) == INSN_UID (next
))
3657 /* Delay slot was filled with insn at jump target. */
3664 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3666 credit
-= get_attr_length (prev
);
3669 && GET_CODE (prev
) == JUMP_INSN
3670 && JUMP_LABEL (prev
))
3674 || next_real_insn (JUMP_LABEL (prev
)) == next
3675 /* If relax_delay_slots() decides NEXT was redundant
3676 with some previous instruction, it will have
3677 redirected PREV's jump to the following insn. */
3678 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
3679 /* There is no upper bound on redundant instructions
3680 that might have been skipped, but we must not put an
3681 alignment where none had been before. */
3682 || (x
= (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
)))),
3684 && (INSN_CODE (x
) == CODE_FOR_block_branch_redirect
3685 || INSN_CODE (x
) == CODE_FOR_indirect_jump_scratch
3686 || INSN_CODE (x
) == CODE_FOR_stuff_delay_slot
))))
3688 rtx pat
= PATTERN (prev
);
3689 if (GET_CODE (pat
) == PARALLEL
)
3690 pat
= XVECEXP (pat
, 0, 0);
3691 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
3697 return align_jumps_log
;
3700 /* If we are inside a phony loop, almost any kind of label can turn up as the
3701 first one in the loop. Aligning a braf label causes incorrect switch
3702 destination addresses; we can detect braf labels because they are
3703 followed by a BARRIER.
3704 Applying loop alignment to small constant or switch tables is a waste
3705 of space, so we suppress this too. */
3707 sh_loop_align (label
)
3713 next
= next_nonnote_insn (next
);
3714 while (next
&& GET_CODE (next
) == CODE_LABEL
);
3718 || GET_CODE (PATTERN (next
)) == ADDR_DIFF_VEC
3719 || recog_memoized (next
) == CODE_FOR_consttable_2
)
3722 return align_loops_log
;
3725 /* Do a final pass over the function, just before delayed branch
3731 rtx first
, insn
, mova
= NULL_RTX
;
3733 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
3734 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
3736 first
= get_insns ();
3738 /* We must split call insns before introducing `mova's. If we're
3739 optimizing, they'll have already been split. Otherwise, make
3740 sure we don't split them too late. */
3742 split_all_insns_noflow ();
3747 /* If relaxing, generate pseudo-ops to associate function calls with
3748 the symbols they call. It does no harm to not generate these
3749 pseudo-ops. However, when we can generate them, it enables to
3750 linker to potentially relax the jsr to a bsr, and eliminate the
3751 register load and, possibly, the constant pool entry. */
3753 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
3756 /* Remove all REG_LABEL notes. We want to use them for our own
3757 purposes. This works because none of the remaining passes
3758 need to look at them.
3760 ??? But it may break in the future. We should use a machine
3761 dependent REG_NOTE, or some other approach entirely. */
3762 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3768 while ((note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
)) != 0)
3769 remove_note (insn
, note
);
3773 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3775 rtx pattern
, reg
, link
, set
, scan
, dies
, label
;
3776 int rescan
= 0, foundinsn
= 0;
3778 if (GET_CODE (insn
) == CALL_INSN
)
3780 pattern
= PATTERN (insn
);
3782 if (GET_CODE (pattern
) == PARALLEL
)
3783 pattern
= XVECEXP (pattern
, 0, 0);
3784 if (GET_CODE (pattern
) == SET
)
3785 pattern
= SET_SRC (pattern
);
3787 if (GET_CODE (pattern
) != CALL
3788 || GET_CODE (XEXP (pattern
, 0)) != MEM
)
3791 reg
= XEXP (XEXP (pattern
, 0), 0);
3795 reg
= sfunc_uses_reg (insn
);
3800 if (GET_CODE (reg
) != REG
)
3803 /* This is a function call via REG. If the only uses of REG
3804 between the time that it is set and the time that it dies
3805 are in function calls, then we can associate all the
3806 function calls with the setting of REG. */
3808 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
3810 if (REG_NOTE_KIND (link
) != 0)
3812 set
= single_set (XEXP (link
, 0));
3813 if (set
&& rtx_equal_p (reg
, SET_DEST (set
)))
3815 link
= XEXP (link
, 0);
3822 /* ??? Sometimes global register allocation will have
3823 deleted the insn pointed to by LOG_LINKS. Try
3824 scanning backward to find where the register is set. */
3825 for (scan
= PREV_INSN (insn
);
3826 scan
&& GET_CODE (scan
) != CODE_LABEL
;
3827 scan
= PREV_INSN (scan
))
3829 if (! INSN_P (scan
))
3832 if (! reg_mentioned_p (reg
, scan
))
3835 if (noncall_uses_reg (reg
, scan
, &set
))
3849 /* The register is set at LINK. */
3851 /* We can only optimize the function call if the register is
3852 being set to a symbol. In theory, we could sometimes
3853 optimize calls to a constant location, but the assembler
3854 and linker do not support that at present. */
3855 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
3856 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
3859 /* Scan forward from LINK to the place where REG dies, and
3860 make sure that the only insns which use REG are
3861 themselves function calls. */
3863 /* ??? This doesn't work for call targets that were allocated
3864 by reload, since there may not be a REG_DEAD note for the
3868 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
3872 /* Don't try to trace forward past a CODE_LABEL if we haven't
3873 seen INSN yet. Ordinarily, we will only find the setting insn
3874 in LOG_LINKS if it is in the same basic block. However,
3875 cross-jumping can insert code labels in between the load and
3876 the call, and can result in situations where a single call
3877 insn may have two targets depending on where we came from. */
3879 if (GET_CODE (scan
) == CODE_LABEL
&& ! foundinsn
)
3882 if (! INSN_P (scan
))
3885 /* Don't try to trace forward past a JUMP. To optimize
3886 safely, we would have to check that all the
3887 instructions at the jump destination did not use REG. */
3889 if (GET_CODE (scan
) == JUMP_INSN
)
3892 if (! reg_mentioned_p (reg
, scan
))
3895 if (noncall_uses_reg (reg
, scan
, &scanset
))
3902 && (GET_CODE (scan
) == CALL_INSN
|| sfunc_uses_reg (scan
)))
3904 /* There is a function call to this register other
3905 than the one we are checking. If we optimize
3906 this call, we need to rescan again below. */
3910 /* ??? We shouldn't have to worry about SCANSET here.
3911 We should just be able to check for a REG_DEAD note
3912 on a function call. However, the REG_DEAD notes are
3913 apparently not dependable around libcalls; c-torture
3914 execute/920501-2 is a test case. If SCANSET is set,
3915 then this insn sets the register, so it must have
3916 died earlier. Unfortunately, this will only handle
3917 the cases in which the register is, in fact, set in a
3920 /* ??? We shouldn't have to use FOUNDINSN here.
3921 However, the LOG_LINKS fields are apparently not
3922 entirely reliable around libcalls;
3923 newlib/libm/math/e_pow.c is a test case. Sometimes
3924 an insn will appear in LOG_LINKS even though it is
3925 not the most recent insn which sets the register. */
3929 || find_reg_note (scan
, REG_DEAD
, reg
)))
3938 /* Either there was a branch, or some insn used REG
3939 other than as a function call address. */
3943 /* Create a code label, and put it in a REG_LABEL note on
3944 the insn which sets the register, and on each call insn
3945 which uses the register. In final_prescan_insn we look
3946 for the REG_LABEL notes, and output the appropriate label
3949 label
= gen_label_rtx ();
3950 REG_NOTES (link
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
3952 REG_NOTES (insn
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
3961 scan
= NEXT_INSN (scan
);
3963 && ((GET_CODE (scan
) == CALL_INSN
3964 && reg_mentioned_p (reg
, scan
))
3965 || ((reg2
= sfunc_uses_reg (scan
))
3966 && REGNO (reg2
) == REGNO (reg
))))
3968 = gen_rtx_INSN_LIST (REG_LABEL
, label
, REG_NOTES (scan
));
3970 while (scan
!= dies
);
3976 fixup_addr_diff_vecs (first
);
3980 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
3981 shorten_branches (first
);
3983 /* Scan the function looking for move instructions which have to be
3984 changed to pc-relative loads and insert the literal tables. */
3986 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
3987 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
3994 else if (GET_CODE (insn
) == JUMP_INSN
3995 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
4003 /* Some code might have been inserted between the mova and
4004 its ADDR_DIFF_VEC. Check if the mova is still in range. */
4005 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
4006 total
+= get_attr_length (scan
);
4008 /* range of mova is 1020, add 4 because pc counts from address of
4009 second instruction after this one, subtract 2 in case pc is 2
4010 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
4011 cancels out with alignment effects of the mova itself. */
4014 /* Change the mova into a load, and restart scanning
4015 there. broken_move will then return true for mova. */
4016 SET_SRC (PATTERN (mova
))
4017 = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
4018 INSN_CODE (mova
) = -1;
4022 if (broken_move (insn
))
4025 /* Scan ahead looking for a barrier to stick the constant table
4027 rtx barrier
= find_barrier (num_mova
, mova
, insn
);
4028 rtx last_float_move
= NULL_RTX
, last_float
= 0, *last_float_addr
= NULL
;
4030 if (num_mova
&& ! mova_p (mova
))
4032 /* find_barrier had to change the first mova into a
4033 pcload; thus, we have to start with this new pcload. */
4037 /* Now find all the moves between the points and modify them. */
4038 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
4040 if (GET_CODE (scan
) == CODE_LABEL
)
4042 if (broken_move (scan
))
4044 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
4048 enum machine_mode mode
;
4050 if (GET_CODE (pat
) == PARALLEL
)
4051 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
4052 src
= SET_SRC (pat
);
4053 dst
= SET_DEST (pat
);
4054 mode
= GET_MODE (dst
);
4056 if (mode
== SImode
&& hi_const (src
)
4057 && REGNO (dst
) != FPUL_REG
)
4062 while (GET_CODE (dst
) == SUBREG
)
4064 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
4065 GET_MODE (SUBREG_REG (dst
)),
4068 dst
= SUBREG_REG (dst
);
4070 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
4073 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
4075 /* This must be an insn that clobbers r0. */
4076 rtx clobber
= XVECEXP (PATTERN (scan
), 0,
4077 XVECLEN (PATTERN (scan
), 0) - 1);
4079 if (GET_CODE (clobber
) != CLOBBER
4080 || ! rtx_equal_p (XEXP (clobber
, 0), r0_rtx
))
4084 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
4088 && GET_MODE_SIZE (mode
) != 4
4089 && GET_MODE_SIZE (GET_MODE (last_float
)) == 4)
4091 lab
= add_constant (src
, mode
, last_float
);
4093 emit_insn_before (gen_mova (lab
), scan
);
4096 /* There will be a REG_UNUSED note for r0 on
4097 LAST_FLOAT_MOVE; we have to change it to REG_INC,
4098 lest reorg:mark_target_live_regs will not
4099 consider r0 to be used, and we end up with delay
4100 slot insn in front of SCAN that clobbers r0. */
4102 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
4104 /* If we are not optimizing, then there may not be
4107 PUT_MODE (note
, REG_INC
);
4109 *last_float_addr
= r0_inc_rtx
;
4111 last_float_move
= scan
;
4113 newsrc
= gen_rtx (MEM
, mode
,
4114 (((TARGET_SH4
&& ! TARGET_FMOVD
)
4115 || REGNO (dst
) == FPUL_REG
)
4118 last_float_addr
= &XEXP (newsrc
, 0);
4120 /* Remove the clobber of r0. */
4121 XEXP (clobber
, 0) = gen_rtx_SCRATCH (Pmode
);
4122 RTX_UNCHANGING_P (newsrc
) = 1;
4124 /* This is a mova needing a label. Create it. */
4125 else if (GET_CODE (src
) == UNSPEC
4126 && XINT (src
, 1) == UNSPEC_MOVA
4127 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
4129 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
4130 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
4131 newsrc
= gen_rtx_UNSPEC (SImode
,
4132 gen_rtvec (1, newsrc
),
4137 lab
= add_constant (src
, mode
, 0);
4138 newsrc
= gen_rtx_MEM (mode
,
4139 gen_rtx_LABEL_REF (VOIDmode
, lab
));
4140 RTX_UNCHANGING_P (newsrc
) = 1;
4142 *patp
= gen_rtx_SET (VOIDmode
, dst
, newsrc
);
4143 INSN_CODE (scan
) = -1;
4146 dump_table (barrier
);
4151 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
4152 INSN_ADDRESSES_FREE ();
4153 split_branches (first
);
4155 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
4156 also has an effect on the register that holds the address of the sfunc.
4157 Insert an extra dummy insn in front of each sfunc that pretends to
4158 use this register. */
4159 if (flag_delayed_branch
)
4161 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4163 rtx reg
= sfunc_uses_reg (insn
);
4167 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
4171 /* fpscr is not actually a user variable, but we pretend it is for the
4172 sake of the previous optimization passes, since we want it handled like
4173 one. However, we don't have any debugging information for it, so turn
4174 it into a non-user variable now. */
4176 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
4178 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
4182 get_dest_uid (label
, max_uid
)
4186 rtx dest
= next_real_insn (label
);
4189 /* This can happen for an undefined label. */
4191 dest_uid
= INSN_UID (dest
);
4192 /* If this is a newly created branch redirection blocking instruction,
4193 we cannot index the branch_uid or insn_addresses arrays with its
4194 uid. But then, we won't need to, because the actual destination is
4195 the following branch. */
4196 while (dest_uid
>= max_uid
)
4198 dest
= NEXT_INSN (dest
);
4199 dest_uid
= INSN_UID (dest
);
4201 if (GET_CODE (dest
) == JUMP_INSN
&& GET_CODE (PATTERN (dest
)) == RETURN
)
4206 /* Split condbranches that are out of range. Also add clobbers for
4207 scratch registers that are needed in far jumps.
4208 We do this before delay slot scheduling, so that it can take our
4209 newly created instructions into account. It also allows us to
4210 find branches with common targets more easily. */
4213 split_branches (first
)
4217 struct far_branch
**uid_branch
, *far_branch_list
= 0;
4218 int max_uid
= get_max_uid ();
4220 /* Find out which branches are out of range. */
4221 shorten_branches (first
);
4223 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
4224 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
4226 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4227 if (! INSN_P (insn
))
4229 else if (INSN_DELETED_P (insn
))
4231 /* Shorten_branches would split this instruction again,
4232 so transform it into a note. */
4233 PUT_CODE (insn
, NOTE
);
4234 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
4235 NOTE_SOURCE_FILE (insn
) = 0;
4237 else if (GET_CODE (insn
) == JUMP_INSN
4238 /* Don't mess with ADDR_DIFF_VEC */
4239 && (GET_CODE (PATTERN (insn
)) == SET
4240 || GET_CODE (PATTERN (insn
)) == RETURN
))
4242 enum attr_type type
= get_attr_type (insn
);
4243 if (type
== TYPE_CBRANCH
)
4247 if (get_attr_length (insn
) > 4)
4249 rtx src
= SET_SRC (PATTERN (insn
));
4250 rtx olabel
= XEXP (XEXP (src
, 1), 0);
4251 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
4253 int dest_uid
= get_dest_uid (olabel
, max_uid
);
4254 struct far_branch
*bp
= uid_branch
[dest_uid
];
4256 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
4257 the label if the LABEL_NUSES count drops to zero. There is
4258 always a jump_optimize pass that sets these values, but it
4259 proceeds to delete unreferenced code, and then if not
4260 optimizing, to un-delete the deleted instructions, thus
4261 leaving labels with too low uses counts. */
4264 JUMP_LABEL (insn
) = olabel
;
4265 LABEL_NUSES (olabel
)++;
4269 bp
= (struct far_branch
*) alloca (sizeof *bp
);
4270 uid_branch
[dest_uid
] = bp
;
4271 bp
->prev
= far_branch_list
;
4272 far_branch_list
= bp
;
4274 = XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1), 0);
4275 LABEL_NUSES (bp
->far_label
)++;
4279 label
= bp
->near_label
;
4280 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
4282 rtx block
= bp
->insert_place
;
4284 if (GET_CODE (PATTERN (block
)) == RETURN
)
4285 block
= PREV_INSN (block
);
4287 block
= gen_block_redirect (block
,
4289 label
= emit_label_after (gen_label_rtx (),
4291 bp
->near_label
= label
;
4293 else if (label
&& ! NEXT_INSN (label
))
4295 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
4296 bp
->insert_place
= insn
;
4298 gen_far_branch (bp
);
4302 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
4304 bp
->near_label
= label
= gen_label_rtx ();
4305 bp
->insert_place
= insn
;
4308 if (! redirect_jump (insn
, label
, 1))
4313 /* get_attr_length (insn) == 2 */
4314 /* Check if we have a pattern where reorg wants to redirect
4315 the branch to a label from an unconditional branch that
4317 /* We can't use JUMP_LABEL here because it might be undefined
4318 when not optimizing. */
4319 /* A syntax error might cause beyond to be NULL_RTX. */
4321 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
4325 && (GET_CODE (beyond
) == JUMP_INSN
4326 || ((beyond
= next_active_insn (beyond
))
4327 && GET_CODE (beyond
) == JUMP_INSN
))
4328 && GET_CODE (PATTERN (beyond
)) == SET
4329 && recog_memoized (beyond
) == CODE_FOR_jump_compact
4331 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
4332 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
4334 gen_block_redirect (beyond
,
4335 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
4338 next
= next_active_insn (insn
);
4340 if ((GET_CODE (next
) == JUMP_INSN
4341 || GET_CODE (next
= next_active_insn (next
)) == JUMP_INSN
)
4342 && GET_CODE (PATTERN (next
)) == SET
4343 && recog_memoized (next
) == CODE_FOR_jump_compact
4345 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
4346 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
4348 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
4350 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
4352 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
4355 struct far_branch
*bp
;
4357 if (type
== TYPE_JUMP
)
4359 far_label
= XEXP (SET_SRC (PATTERN (insn
)), 0);
4360 dest_uid
= get_dest_uid (far_label
, max_uid
);
4363 /* Parse errors can lead to labels outside
4365 if (! NEXT_INSN (far_label
))
4370 JUMP_LABEL (insn
) = far_label
;
4371 LABEL_NUSES (far_label
)++;
4373 redirect_jump (insn
, NULL_RTX
, 1);
4377 bp
= uid_branch
[dest_uid
];
4380 bp
= (struct far_branch
*) alloca (sizeof *bp
);
4381 uid_branch
[dest_uid
] = bp
;
4382 bp
->prev
= far_branch_list
;
4383 far_branch_list
= bp
;
4385 bp
->far_label
= far_label
;
4387 LABEL_NUSES (far_label
)++;
4389 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
4390 if (addr
- bp
->address
<= CONDJUMP_MAX
)
4391 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
4394 gen_far_branch (bp
);
4400 bp
->insert_place
= insn
;
4402 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
4404 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
4407 /* Generate all pending far branches,
4408 and free our references to the far labels. */
4409 while (far_branch_list
)
4411 if (far_branch_list
->near_label
4412 && ! NEXT_INSN (far_branch_list
->near_label
))
4413 gen_far_branch (far_branch_list
);
4415 && far_branch_list
->far_label
4416 && ! --LABEL_NUSES (far_branch_list
->far_label
))
4417 delete_insn (far_branch_list
->far_label
);
4418 far_branch_list
= far_branch_list
->prev
;
4421 /* Instruction length information is no longer valid due to the new
4422 instructions that have been generated. */
4423 init_insn_lengths ();
4426 /* Dump out instruction addresses, which is useful for debugging the
4427 constant pool table stuff.
4429 If relaxing, output the label and pseudo-ops used to link together
4430 calls and the instruction which set the registers. */
4432 /* ??? The addresses printed by this routine for insns are nonsense for
4433 insns which are inside of a sequence where none of the inner insns have
4434 variable length. This is because the second pass of shorten_branches
4435 does not bother to update them. */
4438 final_prescan_insn (insn
, opvec
, noperands
)
4440 rtx
*opvec ATTRIBUTE_UNUSED
;
4441 int noperands ATTRIBUTE_UNUSED
;
4443 if (TARGET_DUMPISIZE
)
4444 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
4450 note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
);
4455 pattern
= PATTERN (insn
);
4456 if (GET_CODE (pattern
) == PARALLEL
)
4457 pattern
= XVECEXP (pattern
, 0, 0);
4458 if (GET_CODE (pattern
) == CALL
4459 || (GET_CODE (pattern
) == SET
4460 && (GET_CODE (SET_SRC (pattern
)) == CALL
4461 || get_attr_type (insn
) == TYPE_SFUNC
)))
4462 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
4463 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4464 else if (GET_CODE (pattern
) == SET
)
4465 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
4466 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4473 /* Dump out any constants accumulated in the final pass. These will
4477 output_jump_label_table ()
4483 fprintf (asm_out_file
, "\t.align 2\n");
4484 for (i
= 0; i
< pool_size
; i
++)
4486 pool_node
*p
= &pool_vector
[i
];
4488 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
4489 CODE_LABEL_NUMBER (p
->label
));
4490 output_asm_insn (".long %O0", &p
->value
);
4498 /* A full frame looks like:
4502 [ if current_function_anonymous_args
4515 local-0 <- fp points here. */
4517 /* Number of bytes pushed for anonymous args, used to pass information
4518 between expand_prologue and expand_epilogue. */
4520 static int extra_push
;
4522 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
4523 to be adjusted, and TEMP, if nonnegative, holds the register number
4524 of a general register that we may clobber. */
4527 output_stack_adjust (size
, reg
, temp
, emit_fn
)
4531 rtx (*emit_fn
) PARAMS ((rtx
));
4535 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4540 if (CONST_OK_FOR_ADD (size
))
4541 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
)));
4542 /* Try to do it with two partial adjustments; however, we must make
4543 sure that the stack is properly aligned at all times, in case
4544 an interrupt occurs between the two partial adjustments. */
4545 else if (CONST_OK_FOR_ADD (size
/ 2 & -align
)
4546 && CONST_OK_FOR_ADD (size
- (size
/ 2 & -align
)))
4548 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
/ 2 & -align
)));
4549 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -align
))));
4556 /* If TEMP is invalid, we could temporarily save a general
4557 register to MACL. However, there is currently no need
4558 to handle this case, so just abort when we see it. */
4561 const_reg
= gen_rtx_REG (GET_MODE (reg
), temp
);
4563 /* If SIZE is negative, subtract the positive value.
4564 This sometimes allows a constant pool entry to be shared
4565 between prologue and epilogue code. */
4568 emit_insn (GEN_MOV (const_reg
, GEN_INT (-size
)));
4569 insn
= emit_fn (GEN_SUB3 (reg
, reg
, const_reg
));
4573 emit_insn (GEN_MOV (const_reg
, GEN_INT (size
)));
4574 insn
= emit_fn (GEN_ADD3 (reg
, reg
, const_reg
));
4576 if (emit_fn
== frame_insn
)
4578 = (gen_rtx_EXPR_LIST
4579 (REG_FRAME_RELATED_EXPR
,
4580 gen_rtx_SET (VOIDmode
, reg
,
4581 gen_rtx_PLUS (SImode
, reg
, GEN_INT (size
))),
4592 RTX_FRAME_RELATED_P (x
) = 1;
4596 /* Output RTL to push register RN onto the stack. */
4604 x
= gen_push_fpul ();
4605 else if (rn
== FPSCR_REG
)
4606 x
= gen_push_fpscr ();
4607 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4608 && FP_OR_XD_REGISTER_P (rn
))
4610 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4612 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
4614 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
4615 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
4617 x
= gen_push (gen_rtx_REG (SImode
, rn
));
4621 = gen_rtx_EXPR_LIST (REG_INC
,
4622 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4626 /* Output RTL to pop register RN from the stack. */
4634 x
= gen_pop_fpul ();
4635 else if (rn
== FPSCR_REG
)
4636 x
= gen_pop_fpscr ();
4637 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4638 && FP_OR_XD_REGISTER_P (rn
))
4640 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4642 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
4644 else if (TARGET_SH2E
&& FP_REGISTER_P (rn
))
4645 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
4647 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
4651 = gen_rtx_EXPR_LIST (REG_INC
,
4652 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4655 /* Generate code to push the regs specified in the mask. */
4658 push_regs (mask
, interrupt_handler
)
4660 int interrupt_handler
;
4665 /* Push PR last; this gives better latencies after the prologue, and
4666 candidates for the return delay slot when there are no general
4667 registers pushed. */
4668 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4670 /* If this is an interrupt handler, and the SZ bit varies,
4671 and we have to push any floating point register, we need
4672 to switch to the correct precision first. */
4673 if (i
== FIRST_FP_REG
&& interrupt_handler
&& TARGET_FMOVD
4674 && hard_regs_intersect_p (mask
, ®_class_contents
[DF_REGS
]))
4676 HARD_REG_SET unsaved
;
4679 COMPL_HARD_REG_SET(unsaved
, *mask
);
4680 fpscr_set_from_mem (NORMAL_MODE (FP_MODE
), unsaved
);
4684 && (i
!= FPSCR_REG
|| ! skip_fpscr
)
4685 && TEST_HARD_REG_BIT (*mask
, i
))
4688 if (TEST_HARD_REG_BIT (*mask
, PR_REG
))
4692 /* Work out the registers which need to be saved, both as a mask and a
4693 count of saved words. Return the count.
4695 If doing a pragma interrupt function, then push all regs used by the
4696 function, and if we call another function (we can tell by looking at PR),
4697 make sure that all the regs it clobbers are safe too. */
4700 calc_live_regs (live_regs_mask
)
4701 HARD_REG_SET
*live_regs_mask
;
4705 int interrupt_handler
;
4708 interrupt_handler
= sh_cfun_interrupt_handler_p ();
4710 for (count
= 0; 32 * count
< FIRST_PSEUDO_REGISTER
; count
++)
4711 CLEAR_HARD_REG_SET (*live_regs_mask
);
4712 if (TARGET_SH4
&& TARGET_FMOVD
&& interrupt_handler
4713 && regs_ever_live
[FPSCR_REG
])
4714 target_flags
&= ~FPU_SINGLE_BIT
;
4715 /* If we can save a lot of saves by switching to double mode, do that. */
4716 else if (TARGET_SH4
&& TARGET_FMOVD
&& TARGET_FPU_SINGLE
)
4717 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
4718 if (regs_ever_live
[reg
] && regs_ever_live
[reg
+1]
4719 && (! call_used_regs
[reg
] || (interrupt_handler
&& ! pragma_trapa
))
4722 target_flags
&= ~FPU_SINGLE_BIT
;
4725 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4726 knows how to use it. That means the pseudo originally allocated for
4727 the initial value can become the PR_MEDIA_REG hard register, as seen for
4728 execute/20010122-1.c:test9. */
4730 pr_live
= regs_ever_live
[PR_MEDIA_REG
];
4733 rtx pr_initial
= has_hard_reg_initial_val (Pmode
, PR_REG
);
4734 pr_live
= (pr_initial
4735 ? (GET_CODE (pr_initial
) != REG
4736 || REGNO (pr_initial
) != (PR_REG
))
4737 : regs_ever_live
[PR_REG
]);
4739 /* Force PR to be live if the prologue has to call the SHmedia
4740 argument decoder or register saver. */
4741 if (TARGET_SHCOMPACT
4742 && ((current_function_args_info
.call_cookie
4743 & ~ CALL_COOKIE_RET_TRAMP (1))
4744 || current_function_has_nonlocal_label
))
4746 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
- 1; reg
>= 0; reg
--)
4748 if (reg
== (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
4750 : (interrupt_handler
&& ! pragma_trapa
)
4751 ? (/* Need to save all the regs ever live. */
4752 (regs_ever_live
[reg
]
4753 || (call_used_regs
[reg
]
4754 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
)
4756 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
4757 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
4758 && reg
!= T_REG
&& reg
!= GBR_REG
4759 /* Push fpscr only on targets which have FPU */
4760 && (reg
!= FPSCR_REG
|| TARGET_FPU_ANY
))
4761 : (/* Only push those regs which are used and need to be saved. */
4764 && current_function_args_info
.call_cookie
4765 && reg
== PIC_OFFSET_TABLE_REGNUM
)
4766 || (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
4767 || (current_function_calls_eh_return
4768 && (reg
== EH_RETURN_DATA_REGNO (0)
4769 || reg
== EH_RETURN_DATA_REGNO (1)
4770 || reg
== EH_RETURN_DATA_REGNO (2)
4771 || reg
== EH_RETURN_DATA_REGNO (3)))))
4773 SET_HARD_REG_BIT (*live_regs_mask
, reg
);
4774 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
4776 if ((TARGET_SH4
|| TARGET_SH5
) && TARGET_FMOVD
4777 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg
)) == MODE_FLOAT
)
4779 if (FP_REGISTER_P (reg
))
4781 if (! TARGET_FPU_SINGLE
&& ! regs_ever_live
[reg
^ 1])
4783 SET_HARD_REG_BIT (*live_regs_mask
, (reg
^ 1));
4784 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
^ 1));
4787 else if (XD_REGISTER_P (reg
))
4789 /* Must switch to double mode to access these registers. */
4790 target_flags
&= ~FPU_SINGLE_BIT
;
4799 /* Code to generate prologue and epilogue sequences */
4801 /* PUSHED is the number of bytes that are being pushed on the
4802 stack for register saves. Return the frame size, padded
4803 appropriately so that the stack stays properly aligned. */
4804 static HOST_WIDE_INT
4805 rounded_frame_size (pushed
)
4808 HOST_WIDE_INT size
= get_frame_size ();
4809 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4811 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
4814 /* Choose a call-clobbered target-branch register that remains
4815 unchanged along the whole function. We set it up as the return
4816 value in the prologue. */
4818 sh_media_register_for_return ()
4823 if (! current_function_is_leaf
)
4826 tr0_used
= flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
];
4828 for (regno
= FIRST_TARGET_REG
+ tr0_used
; regno
<= LAST_TARGET_REG
; regno
++)
4829 if (call_used_regs
[regno
] && ! regs_ever_live
[regno
])
4836 sh_expand_prologue ()
4838 HARD_REG_SET live_regs_mask
;
4841 int save_flags
= target_flags
;
4843 current_function_interrupt
= sh_cfun_interrupt_handler_p ();
4845 /* We have pretend args if we had an object sent partially in registers
4846 and partially on the stack, e.g. a large structure. */
4847 output_stack_adjust (-current_function_pretend_args_size
4848 - current_function_args_info
.stack_regs
* 8,
4849 stack_pointer_rtx
, TARGET_SH5
? 0 : 1, frame_insn
);
4853 if (TARGET_SHCOMPACT
&& flag_pic
&& current_function_args_info
.call_cookie
)
4854 /* We're going to use the PIC register to load the address of the
4855 incoming-argument decoder and/or of the return trampoline from
4856 the GOT, so make sure the PIC register is preserved and
4858 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
4860 if (TARGET_SHCOMPACT
4861 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
4865 /* First, make all registers with incoming arguments that will
4866 be pushed onto the stack live, so that register renaming
4867 doesn't overwrite them. */
4868 for (reg
= 0; reg
< NPARM_REGS (SImode
); reg
++)
4869 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info
.call_cookie
)
4870 >= NPARM_REGS (SImode
) - reg
)
4871 for (; reg
< NPARM_REGS (SImode
); reg
++)
4872 emit_insn (gen_shcompact_preserve_incoming_args
4873 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
4874 else if (CALL_COOKIE_INT_REG_GET
4875 (current_function_args_info
.call_cookie
, reg
) == 1)
4876 emit_insn (gen_shcompact_preserve_incoming_args
4877 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
4879 emit_move_insn (gen_rtx_REG (Pmode
, MACL_REG
),
4881 emit_move_insn (gen_rtx_REG (SImode
, R0_REG
),
4882 GEN_INT (current_function_args_info
.call_cookie
));
4883 emit_move_insn (gen_rtx_REG (SImode
, MACH_REG
),
4884 gen_rtx_REG (SImode
, R0_REG
));
4886 else if (TARGET_SHMEDIA
)
4888 int tr
= sh_media_register_for_return ();
4892 rtx insn
= emit_move_insn (gen_rtx_REG (DImode
, tr
),
4893 gen_rtx_REG (DImode
, PR_MEDIA_REG
));
4895 /* If this function only exits with sibcalls, this copy
4896 will be flagged as dead. */
4897 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4903 /* Emit the code for SETUP_VARARGS. */
4904 if (current_function_stdarg
)
4906 /* This is not used by the SH2E calling convention */
4907 if (TARGET_SH1
&& ! TARGET_SH2E
&& ! TARGET_SH5
&& ! TARGET_HITACHI
)
4909 /* Push arg regs as if they'd been provided by caller in stack. */
4910 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
4912 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
4915 if (i
>= (NPARM_REGS(SImode
)
4916 - current_function_args_info
.arg_count
[(int) SH_ARG_INT
]
4920 RTX_FRAME_RELATED_P (insn
) = 0;
4926 /* If we're supposed to switch stacks at function entry, do so now. */
4928 emit_insn (gen_sp_switch_1 ());
4930 d
= calc_live_regs (&live_regs_mask
);
4931 /* ??? Maybe we could save some switching if we can move a mode switch
4932 that already happens to be at the function start into the prologue. */
4933 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
4934 emit_insn (gen_toggle_sz ());
4941 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
4942 int offset_in_r0
= -1;
4945 if (d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
4946 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
4947 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
4949 offset
= d
+ d_rounding
;
4950 output_stack_adjust (-offset
, stack_pointer_rtx
, 1, frame_insn
);
4952 /* We loop twice: first, we save 8-byte aligned registers in the
4953 higher addresses, that are known to be aligned. Then, we
4954 proceed to saving 32-bit registers that don't need 8-byte
4956 /* Note that if you change this code in a way that affects where
4957 the return register is saved, you have to update not only
4958 sh_expand_epilogue, but also sh_set_return_address. */
4959 for (align
= 1; align
>= 0; align
--)
4960 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
4961 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
4963 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
4965 rtx reg_rtx
, mem_rtx
, pre_dec
= NULL_RTX
;
4967 if (mode
== SFmode
&& (i
% 2) == 1
4968 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
4969 && (TEST_HARD_REG_BIT (live_regs_mask
, (i
^ 1))))
4976 /* If we're doing the aligned pass and this is not aligned,
4977 or we're doing the unaligned pass and this is aligned,
4979 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
4983 offset
-= GET_MODE_SIZE (mode
);
4985 reg_rtx
= gen_rtx_REG (mode
, reg
);
4987 mem_rtx
= gen_rtx_MEM (mode
,
4988 gen_rtx_PLUS (Pmode
,
4992 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_pre_dec
);
4998 if (HAVE_PRE_DECREMENT
4999 && (offset_in_r0
- offset
== GET_MODE_SIZE (mode
)
5000 || mem_rtx
== NULL_RTX
5001 || i
== PR_REG
|| SPECIAL_REGISTER_P (i
)))
5003 pre_dec
= gen_rtx_MEM (mode
,
5004 gen_rtx_PRE_DEC (Pmode
, r0
));
5006 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (pre_dec
, 0),
5015 offset
+= GET_MODE_SIZE (mode
);
5019 if (mem_rtx
!= NULL_RTX
)
5022 if (offset_in_r0
== -1)
5024 emit_move_insn (r0
, GEN_INT (offset
));
5025 offset_in_r0
= offset
;
5027 else if (offset
!= offset_in_r0
)
5032 GEN_INT (offset
- offset_in_r0
)));
5033 offset_in_r0
+= offset
- offset_in_r0
;
5036 if (pre_dec
!= NULL_RTX
)
5042 (Pmode
, r0
, stack_pointer_rtx
));
5046 offset
-= GET_MODE_SIZE (mode
);
5047 offset_in_r0
-= GET_MODE_SIZE (mode
);
5052 mem_rtx
= gen_rtx_MEM (mode
, r0
);
5054 mem_rtx
= gen_rtx_MEM (mode
,
5055 gen_rtx_PLUS (Pmode
,
5059 /* We must not use an r0-based address for target-branch
5060 registers or for special registers without pre-dec
5061 memory addresses, since we store their values in r0
5063 if (TARGET_REGISTER_P (i
)
5064 || ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
5065 && mem_rtx
!= pre_dec
))
5069 if (TARGET_REGISTER_P (i
)
5070 || ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
5071 && mem_rtx
!= pre_dec
))
5073 rtx r0mode
= gen_rtx_REG (GET_MODE (reg_rtx
), R0_REG
);
5075 emit_move_insn (r0mode
, reg_rtx
);
5083 emit_move_insn (mem_rtx
, reg_rtx
);
5086 if (offset
!= d_rounding
)
5090 push_regs (&live_regs_mask
, current_function_interrupt
);
5092 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
5094 rtx insn
= get_last_insn ();
5095 rtx last
= emit_insn (gen_GOTaddr2picreg ());
5097 /* Mark these insns as possibly dead. Sometimes, flow2 may
5098 delete all uses of the PIC register. In this case, let it
5099 delete the initialization too. */
5102 insn
= NEXT_INSN (insn
);
5104 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
5108 while (insn
!= last
);
5111 if (SHMEDIA_REGS_STACK_ADJUST ())
5113 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
5114 function_symbol (TARGET_FPU_ANY
5115 ? "__GCC_push_shmedia_regs"
5116 : "__GCC_push_shmedia_regs_nofpu"));
5117 /* This must NOT go through the PLT, otherwise mach and macl
5118 may be clobbered. */
5119 emit_insn (gen_shmedia_save_restore_regs_compact
5120 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
5123 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
5125 rtx insn
= emit_insn (gen_toggle_sz ());
5127 /* If we're lucky, a mode switch in the function body will
5128 overwrite fpscr, turning this insn dead. Tell flow this
5129 insn is ok to delete. */
5130 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
5135 target_flags
= save_flags
;
5137 output_stack_adjust (-rounded_frame_size (d
) + d_rounding
,
5138 stack_pointer_rtx
, TARGET_SH5
? 0 : 1, frame_insn
);
5140 if (frame_pointer_needed
)
5141 frame_insn (GEN_MOV (frame_pointer_rtx
, stack_pointer_rtx
));
5143 if (TARGET_SHCOMPACT
5144 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
5146 /* This must NOT go through the PLT, otherwise mach and macl
5147 may be clobbered. */
5148 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
5149 function_symbol ("__GCC_shcompact_incoming_args"));
5150 emit_insn (gen_shcompact_incoming_args ());
5155 sh_expand_epilogue ()
5157 HARD_REG_SET live_regs_mask
;
5161 int save_flags
= target_flags
;
5163 int fpscr_deferred
= 0;
5165 d
= calc_live_regs (&live_regs_mask
);
5167 if (TARGET_SH5
&& d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
5168 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
5169 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
5171 frame_size
= rounded_frame_size (d
) - d_rounding
;
5173 if (frame_pointer_needed
)
5175 output_stack_adjust (frame_size
, frame_pointer_rtx
, 7, emit_insn
);
5177 /* We must avoid moving the stack pointer adjustment past code
5178 which reads from the local frame, else an interrupt could
5179 occur after the SP adjustment and clobber data in the local
5181 emit_insn (gen_blockage ());
5182 emit_insn (GEN_MOV (stack_pointer_rtx
, frame_pointer_rtx
));
5184 else if (frame_size
)
5186 /* We must avoid moving the stack pointer adjustment past code
5187 which reads from the local frame, else an interrupt could
5188 occur after the SP adjustment and clobber data in the local
5190 emit_insn (gen_blockage ());
5191 output_stack_adjust (frame_size
, stack_pointer_rtx
, 7, emit_insn
);
5194 if (SHMEDIA_REGS_STACK_ADJUST ())
5196 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
5197 function_symbol (TARGET_FPU_ANY
5198 ? "__GCC_pop_shmedia_regs"
5199 : "__GCC_pop_shmedia_regs_nofpu"));
5200 /* This must NOT go through the PLT, otherwise mach and macl
5201 may be clobbered. */
5202 emit_insn (gen_shmedia_save_restore_regs_compact
5203 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
5206 /* Pop all the registers. */
5208 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
5209 emit_insn (gen_toggle_sz ());
5212 int offset
= d_rounding
;
5213 int offset_in_r0
= -1;
5216 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
5217 int tmp_regno
= R20_REG
;
5219 /* We loop twice: first, we save 8-byte aligned registers in the
5220 higher addresses, that are known to be aligned. Then, we
5221 proceed to saving 32-bit registers that don't need 8-byte
5223 for (align
= 0; align
<= 1; align
++)
5224 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5225 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
5227 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
5229 rtx reg_rtx
, mem_rtx
, post_inc
= NULL_RTX
, insn
;
5231 if (mode
== SFmode
&& (i
% 2) == 0
5232 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
5233 && (TEST_HARD_REG_BIT (live_regs_mask
, (i
^ 1))))
5239 /* If we're doing the aligned pass and this is not aligned,
5240 or we're doing the unaligned pass and this is aligned,
5242 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
5246 reg_rtx
= gen_rtx_REG (mode
, reg
);
5248 mem_rtx
= gen_rtx_MEM (mode
,
5249 gen_rtx_PLUS (Pmode
,
5253 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_post_inc
);
5259 if (HAVE_POST_INCREMENT
5260 && (offset
== offset_in_r0
5261 || (offset
+ GET_MODE_SIZE (mode
) != d
+ d_rounding
5262 && mem_rtx
== NULL_RTX
)
5263 || i
== PR_REG
|| SPECIAL_REGISTER_P (i
)))
5265 post_inc
= gen_rtx_MEM (mode
,
5266 gen_rtx_POST_INC (Pmode
, r0
));
5268 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (post_inc
, 0),
5271 post_inc
= NULL_RTX
;
5280 if (mem_rtx
!= NULL_RTX
)
5283 if (offset_in_r0
== -1)
5285 emit_move_insn (r0
, GEN_INT (offset
));
5286 offset_in_r0
= offset
;
5288 else if (offset
!= offset_in_r0
)
5293 GEN_INT (offset
- offset_in_r0
)));
5294 offset_in_r0
+= offset
- offset_in_r0
;
5297 if (post_inc
!= NULL_RTX
)
5303 (Pmode
, r0
, stack_pointer_rtx
));
5309 offset_in_r0
+= GET_MODE_SIZE (mode
);
5312 mem_rtx
= gen_rtx_MEM (mode
, r0
);
5314 mem_rtx
= gen_rtx_MEM (mode
,
5315 gen_rtx_PLUS (Pmode
,
5319 if ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
5320 && mem_rtx
!= post_inc
)
5324 if ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
5325 && mem_rtx
!= post_inc
)
5327 insn
= emit_move_insn (r0
, mem_rtx
);
5330 else if (TARGET_REGISTER_P (i
))
5332 rtx tmp_reg
= gen_rtx_REG (mode
, tmp_regno
);
5334 /* Give the scheduler a bit of freedom by using R20..R23
5335 in a round-robin fashion. Don't use R1 here because
5336 we want to use it for EH_RETURN_STACKADJ_RTX. */
5337 insn
= emit_move_insn (tmp_reg
, mem_rtx
);
5339 if (++tmp_regno
> R23_REG
)
5340 tmp_regno
= R20_REG
;
5343 insn
= emit_move_insn (reg_rtx
, mem_rtx
);
5345 offset
+= GET_MODE_SIZE (mode
);
5348 if (offset
!= d
+ d_rounding
)
5355 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
))
5357 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5359 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
5361 if (j
== FPSCR_REG
&& current_function_interrupt
&& TARGET_FMOVD
5362 && hard_regs_intersect_p (&live_regs_mask
,
5363 ®_class_contents
[DF_REGS
]))
5365 else if (j
!= PR_REG
&& TEST_HARD_REG_BIT (live_regs_mask
, j
))
5367 if (j
== FIRST_FP_REG
&& fpscr_deferred
)
5371 if (target_flags
!= save_flags
&& ! current_function_interrupt
)
5372 emit_insn (gen_toggle_sz ());
5373 target_flags
= save_flags
;
5375 output_stack_adjust (extra_push
+ current_function_pretend_args_size
5377 + current_function_args_info
.stack_regs
* 8,
5378 stack_pointer_rtx
, 7, emit_insn
);
5380 if (current_function_calls_eh_return
)
5381 emit_insn (GEN_ADD3 (stack_pointer_rtx
, stack_pointer_rtx
,
5382 EH_RETURN_STACKADJ_RTX
));
5384 /* Switch back to the normal stack if necessary. */
5386 emit_insn (gen_sp_switch_2 ());
5388 /* Tell flow the insn that pops PR isn't dead. */
5389 /* PR_REG will never be live in SHmedia mode, and we don't need to
5390 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5391 by the return pattern. */
5392 if (TEST_HARD_REG_BIT (live_regs_mask
, PR_REG
))
5393 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, PR_REG
)));
5396 static int sh_need_epilogue_known
= 0;
5401 if (! sh_need_epilogue_known
)
5406 sh_expand_epilogue ();
5407 epilogue
= get_insns ();
5409 sh_need_epilogue_known
= (epilogue
== NULL
? -1 : 1);
5411 return sh_need_epilogue_known
> 0;
5414 /* Emit code to change the current function's return address to RA.
5415 TEMP is available as a scratch register, if needed. */
5418 sh_set_return_address (ra
, tmp
)
5421 HARD_REG_SET live_regs_mask
;
5424 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
5427 d
= calc_live_regs (&live_regs_mask
);
5429 /* If pr_reg isn't life, we can set it (or the register given in
5430 sh_media_register_for_return) directly. */
5431 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
5437 int rr_regno
= sh_media_register_for_return ();
5442 rr
= gen_rtx_REG (DImode
, rr_regno
);
5445 rr
= gen_rtx_REG (SImode
, pr_reg
);
5447 emit_insn (GEN_MOV (rr
, ra
));
5448 /* Tell flow the register for return isn't dead. */
5449 emit_insn (gen_rtx_USE (VOIDmode
, rr
));
5459 if (d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
5460 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
5461 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
5465 /* We loop twice: first, we save 8-byte aligned registers in the
5466 higher addresses, that are known to be aligned. Then, we
5467 proceed to saving 32-bit registers that don't need 8-byte
5469 for (align
= 0; align
<= 1; align
++)
5470 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5471 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
5473 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
5475 if (mode
== SFmode
&& (i
% 2) == 0
5476 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
5477 && (TEST_HARD_REG_BIT (live_regs_mask
, (i
^ 1))))
5483 /* If we're doing the aligned pass and this is not aligned,
5484 or we're doing the unaligned pass and this is aligned,
5486 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
5493 offset
+= GET_MODE_SIZE (mode
);
5496 /* We can't find pr register. */
5500 pr_offset
= (rounded_frame_size (d
) - d_rounding
+ offset
5501 + SHMEDIA_REGS_STACK_ADJUST ());
5504 pr_offset
= rounded_frame_size (d
) - d_rounding
;
5506 emit_insn (GEN_MOV (tmp
, GEN_INT (pr_offset
)));
5507 emit_insn (GEN_ADD3 (tmp
, tmp
, frame_pointer_rtx
));
5509 tmp
= gen_rtx_MEM (Pmode
, tmp
);
5510 emit_insn (GEN_MOV (tmp
, ra
));
5513 /* Clear variables at function end. */
5516 sh_output_function_epilogue (file
, size
)
5517 FILE *file ATTRIBUTE_UNUSED
;
5518 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
5520 trap_exit
= pragma_interrupt
= pragma_trapa
= pragma_nosave_low_regs
= 0;
5521 sh_need_epilogue_known
= 0;
5522 sp_switch
= NULL_RTX
;
5526 sh_builtin_saveregs ()
5528 /* First unnamed integer register. */
5529 int first_intreg
= current_function_args_info
.arg_count
[(int) SH_ARG_INT
];
5530 /* Number of integer registers we need to save. */
5531 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
5532 /* First unnamed SFmode float reg */
5533 int first_floatreg
= current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
5534 /* Number of SFmode float regs to save. */
5535 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
5538 HOST_WIDE_INT alias_set
;
5544 int pushregs
= n_intregs
;
5546 while (pushregs
< NPARM_REGS (SImode
) - 1
5547 && (CALL_COOKIE_INT_REG_GET
5548 (current_function_args_info
.call_cookie
,
5549 NPARM_REGS (SImode
) - pushregs
)
5552 current_function_args_info
.call_cookie
5553 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
5558 if (pushregs
== NPARM_REGS (SImode
))
5559 current_function_args_info
.call_cookie
5560 |= (CALL_COOKIE_INT_REG (0, 1)
5561 | CALL_COOKIE_STACKSEQ (pushregs
- 1));
5563 current_function_args_info
.call_cookie
5564 |= CALL_COOKIE_STACKSEQ (pushregs
);
5566 current_function_pretend_args_size
+= 8 * n_intregs
;
5568 if (TARGET_SHCOMPACT
)
5572 if (! TARGET_SH2E
&& ! TARGET_SH4
&& ! TARGET_SH5
)
5574 error ("__builtin_saveregs not supported by this subtarget");
5581 /* Allocate block of memory for the regs. */
5582 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5583 Or can assign_stack_local accept a 0 SIZE argument? */
5584 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
5587 regbuf
= gen_rtx_MEM (BLKmode
,
5588 gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
));
5589 else if (n_floatregs
& 1)
5593 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
5594 addr
= copy_to_mode_reg (Pmode
, XEXP (regbuf
, 0));
5595 emit_insn (gen_iorsi3 (addr
, addr
, GEN_INT (UNITS_PER_WORD
)));
5596 regbuf
= change_address (regbuf
, BLKmode
, addr
);
5599 regbuf
= assign_stack_local (BLKmode
, bufsize
, 0);
5600 alias_set
= get_varargs_alias_set ();
5601 set_mem_alias_set (regbuf
, alias_set
);
5604 This is optimized to only save the regs that are necessary. Explicitly
5605 named args need not be saved. */
5607 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
5608 adjust_address (regbuf
, BLKmode
,
5609 n_floatregs
* UNITS_PER_WORD
),
5613 /* Return the address of the regbuf. */
5614 return XEXP (regbuf
, 0);
5617 This is optimized to only save the regs that are necessary. Explicitly
5618 named args need not be saved.
5619 We explicitly build a pointer to the buffer because it halves the insn
5620 count when not optimizing (otherwise the pointer is built for each reg
5622 We emit the moves in reverse order so that we can use predecrement. */
5624 fpregs
= gen_reg_rtx (Pmode
);
5625 emit_move_insn (fpregs
, XEXP (regbuf
, 0));
5626 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5627 GEN_INT (n_floatregs
* UNITS_PER_WORD
)));
5631 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
5633 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5634 GEN_INT (-2 * UNITS_PER_WORD
)));
5635 mem
= gen_rtx_MEM (DFmode
, fpregs
);
5636 set_mem_alias_set (mem
, alias_set
);
5637 emit_move_insn (mem
,
5638 gen_rtx (REG
, DFmode
, BASE_ARG_REG (DFmode
) + regno
));
5640 regno
= first_floatreg
;
5643 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5644 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5645 set_mem_alias_set (mem
, alias_set
);
5646 emit_move_insn (mem
,
5647 gen_rtx (REG
, SFmode
, BASE_ARG_REG (SFmode
) + regno
5648 - (TARGET_LITTLE_ENDIAN
!= 0)));
5652 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
5656 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5657 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5658 set_mem_alias_set (mem
, alias_set
);
5659 emit_move_insn (mem
,
5660 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
5663 /* Return the address of the regbuf. */
5664 return XEXP (regbuf
, 0);
5667 /* Define the `__builtin_va_list' type for the ABI. */
5672 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5675 if (TARGET_SH5
|| (! TARGET_SH2E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
5676 return ptr_type_node
;
5678 record
= make_node (RECORD_TYPE
);
5680 f_next_o
= build_decl (FIELD_DECL
, get_identifier ("__va_next_o"),
5682 f_next_o_limit
= build_decl (FIELD_DECL
,
5683 get_identifier ("__va_next_o_limit"),
5685 f_next_fp
= build_decl (FIELD_DECL
, get_identifier ("__va_next_fp"),
5687 f_next_fp_limit
= build_decl (FIELD_DECL
,
5688 get_identifier ("__va_next_fp_limit"),
5690 f_next_stack
= build_decl (FIELD_DECL
, get_identifier ("__va_next_stack"),
5693 DECL_FIELD_CONTEXT (f_next_o
) = record
;
5694 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
5695 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
5696 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
5697 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
5699 TYPE_FIELDS (record
) = f_next_o
;
5700 TREE_CHAIN (f_next_o
) = f_next_o_limit
;
5701 TREE_CHAIN (f_next_o_limit
) = f_next_fp
;
5702 TREE_CHAIN (f_next_fp
) = f_next_fp_limit
;
5703 TREE_CHAIN (f_next_fp_limit
) = f_next_stack
;
5705 layout_type (record
);
5710 /* Implement `va_start' for varargs and stdarg. */
5713 sh_va_start (valist
, nextarg
)
5717 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5718 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
5724 expand_builtin_saveregs ();
5725 std_expand_builtin_va_start (valist
, nextarg
);
5729 if ((! TARGET_SH2E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
5731 std_expand_builtin_va_start (valist
, nextarg
);
5735 f_next_o
= TYPE_FIELDS (va_list_type_node
);
5736 f_next_o_limit
= TREE_CHAIN (f_next_o
);
5737 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
5738 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
5739 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
5741 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
5742 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
5743 valist
, f_next_o_limit
);
5744 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
);
5745 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
5746 valist
, f_next_fp_limit
);
5747 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
5748 valist
, f_next_stack
);
5750 /* Call __builtin_saveregs. */
5751 u
= make_tree (ptr_type_node
, expand_builtin_saveregs ());
5752 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
5753 TREE_SIDE_EFFECTS (t
) = 1;
5754 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5756 nfp
= current_function_args_info
.arg_count
[SH_ARG_FLOAT
];
5761 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5762 build_int_2 (UNITS_PER_WORD
* nfp
, 0)));
5763 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
5764 TREE_SIDE_EFFECTS (t
) = 1;
5765 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5767 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
5768 TREE_SIDE_EFFECTS (t
) = 1;
5769 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5771 nint
= current_function_args_info
.arg_count
[SH_ARG_INT
];
5776 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5777 build_int_2 (UNITS_PER_WORD
* nint
, 0)));
5778 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
5779 TREE_SIDE_EFFECTS (t
) = 1;
5780 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5782 u
= make_tree (ptr_type_node
, nextarg
);
5783 t
= build (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
5784 TREE_SIDE_EFFECTS (t
) = 1;
5785 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5788 /* Implement `va_arg'. */
5791 sh_va_arg (valist
, type
)
5794 HOST_WIDE_INT size
, rsize
;
5795 tree tmp
, pptr_type_node
;
5798 int pass_by_ref
= MUST_PASS_IN_STACK (TYPE_MODE (type
), type
);
5800 size
= int_size_in_bytes (type
);
5801 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5802 pptr_type_node
= build_pointer_type (ptr_type_node
);
5805 type
= build_pointer_type (type
);
5807 if (! TARGET_SH5
&& (TARGET_SH2E
|| TARGET_SH4
) && ! TARGET_HITACHI
)
5809 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5810 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
5812 rtx lab_false
, lab_over
;
5814 f_next_o
= TYPE_FIELDS (va_list_type_node
);
5815 f_next_o_limit
= TREE_CHAIN (f_next_o
);
5816 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
5817 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
5818 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
5820 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
5821 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
5822 valist
, f_next_o_limit
);
5823 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
5825 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
5826 valist
, f_next_fp_limit
);
5827 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
5828 valist
, f_next_stack
);
5832 pass_as_float
= ((TREE_CODE (type
) == REAL_TYPE
&& size
<= 8)
5833 || (TREE_CODE (type
) == COMPLEX_TYPE
5834 && TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
5839 pass_as_float
= (TREE_CODE (type
) == REAL_TYPE
&& size
== 4);
5842 addr_rtx
= gen_reg_rtx (Pmode
);
5843 lab_false
= gen_label_rtx ();
5844 lab_over
= gen_label_rtx ();
5849 = current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
5850 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
5852 emit_cmp_and_jump_insns (expand_expr (next_fp
, NULL_RTX
, Pmode
,
5854 expand_expr (next_fp_limit
, NULL_RTX
,
5855 Pmode
, EXPAND_NORMAL
),
5856 GE
, const1_rtx
, Pmode
, 1, lab_false
);
5858 if (TYPE_ALIGN (type
) > BITS_PER_WORD
5859 || (((TREE_CODE (type
) == REAL_TYPE
&& size
== 8) || size
== 16)
5860 && (n_floatregs
& 1)))
5862 tmp
= build (BIT_AND_EXPR
, ptr_type_node
, next_fp
,
5863 build_int_2 (UNITS_PER_WORD
, 0));
5864 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_fp
, tmp
);
5865 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, tmp
);
5866 TREE_SIDE_EFFECTS (tmp
) = 1;
5867 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5870 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_fp
);
5871 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5873 emit_move_insn (addr_rtx
, r
);
5875 emit_jump_insn (gen_jump (lab_over
));
5877 emit_label (lab_false
);
5879 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
5880 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5882 emit_move_insn (addr_rtx
, r
);
5886 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_o
,
5887 build_int_2 (rsize
, 0));
5889 emit_cmp_and_jump_insns (expand_expr (tmp
, NULL_RTX
, Pmode
,
5891 expand_expr (next_o_limit
, NULL_RTX
,
5892 Pmode
, EXPAND_NORMAL
),
5893 GT
, const1_rtx
, Pmode
, 1, lab_false
);
5895 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_o
);
5896 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5898 emit_move_insn (addr_rtx
, r
);
5900 emit_jump_insn (gen_jump (lab_over
));
5902 emit_label (lab_false
);
5904 if (size
> 4 && ! TARGET_SH4
)
5906 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, next_o_limit
);
5907 TREE_SIDE_EFFECTS (tmp
) = 1;
5908 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5911 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
5912 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5914 emit_move_insn (addr_rtx
, r
);
5917 emit_label (lab_over
);
5919 tmp
= make_tree (pptr_type_node
, addr_rtx
);
5920 valist
= build1 (INDIRECT_REF
, ptr_type_node
, tmp
);
5923 /* ??? In va-sh.h, there had been code to make values larger than
5924 size 8 indirect. This does not match the FUNCTION_ARG macros. */
5926 result
= std_expand_builtin_va_arg (valist
, type
);
5929 #ifdef POINTERS_EXTEND_UNSIGNED
5930 if (GET_MODE (addr
) != Pmode
)
5931 addr
= convert_memory_address (Pmode
, result
);
5933 result
= gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, result
));
5934 set_mem_alias_set (result
, get_varargs_alias_set ());
5936 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
5937 argument to the varargs alias set. */
5941 /* Define the offset between two registers, one to be eliminated, and
5942 the other its replacement, at the start of a routine. */
5945 initial_elimination_offset (from
, to
)
5950 int regs_saved_rounding
= 0;
5951 int total_saved_regs_space
;
5952 int total_auto_space
;
5953 int save_flags
= target_flags
;
5956 HARD_REG_SET live_regs_mask
;
5957 regs_saved
= calc_live_regs (&live_regs_mask
);
5958 regs_saved
+= SHMEDIA_REGS_STACK_ADJUST ();
5959 if (TARGET_SH5
&& regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
5960 regs_saved_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
5961 - regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
5963 total_auto_space
= rounded_frame_size (regs_saved
) - regs_saved_rounding
;
5964 copy_flags
= target_flags
;
5965 target_flags
= save_flags
;
5967 total_saved_regs_space
= regs_saved
+ regs_saved_rounding
;
5969 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
5970 return total_saved_regs_space
+ total_auto_space
5971 + current_function_args_info
.byref_regs
* 8;
5973 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5974 return total_saved_regs_space
+ total_auto_space
5975 + current_function_args_info
.byref_regs
* 8;
5977 /* Initial gap between fp and sp is 0. */
5978 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5981 if (from
== RETURN_ADDRESS_POINTER_REGNUM
5982 && (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
))
5986 int i
, n
= total_saved_regs_space
;
5988 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
5990 n
+= total_auto_space
;
5992 /* If it wasn't saved, there's not much we can do. */
5993 if (! TEST_HARD_REG_BIT (live_regs_mask
, pr_reg
))
5996 target_flags
= copy_flags
;
5998 /* We loop twice: first, check 8-byte aligned registers,
5999 that are stored in the higher addresses, that are known
6000 to be aligned. Then, check 32-bit registers that don't
6001 need 8-byte alignment. */
6002 for (align
= 1; align
>= 0; align
--)
6003 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
6004 if (TEST_HARD_REG_BIT (live_regs_mask
, i
))
6006 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
6008 if (mode
== SFmode
&& (i
% 2) == 1
6009 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
6010 && TEST_HARD_REG_BIT (live_regs_mask
, (i
^ 1)))
6016 /* If we're doing the aligned pass and this is not aligned,
6017 or we're doing the unaligned pass and this is aligned,
6019 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
6023 n
-= GET_MODE_SIZE (mode
);
6027 target_flags
= save_flags
;
6035 return total_auto_space
;
6041 /* Handle machine specific pragmas to be semi-compatible with Hitachi
6045 sh_pr_interrupt (pfile
)
6046 struct cpp_reader
*pfile ATTRIBUTE_UNUSED
;
6048 pragma_interrupt
= 1;
6053 struct cpp_reader
*pfile ATTRIBUTE_UNUSED
;
6055 pragma_interrupt
= pragma_trapa
= 1;
6059 sh_pr_nosave_low_regs (pfile
)
6060 struct cpp_reader
*pfile ATTRIBUTE_UNUSED
;
6062 pragma_nosave_low_regs
= 1;
6065 /* Generate 'handle_interrupt' attribute for decls */
6068 sh_insert_attributes (node
, attributes
)
6072 if (! pragma_interrupt
6073 || TREE_CODE (node
) != FUNCTION_DECL
)
6076 /* We are only interested in fields. */
6077 if (TREE_CODE_CLASS (TREE_CODE (node
)) != 'd')
6080 /* Add a 'handle_interrupt' attribute. */
6081 * attributes
= tree_cons (get_identifier ("interrupt_handler"), NULL
, * attributes
);
6086 /* Supported attributes:
6088 interrupt_handler -- specifies this function is an interrupt handler.
6090 sp_switch -- specifies an alternate stack for an interrupt handler
6093 trap_exit -- use a trapa to exit an interrupt function instead of
6094 an rte instruction. */
6096 const struct attribute_spec sh_attribute_table
[] =
6098 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
6099 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute
},
6100 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute
},
6101 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute
},
6102 { NULL
, 0, 0, false, false, false, NULL
}
6105 /* Handle an "interrupt_handler" attribute; arguments as in
6106 struct attribute_spec.handler. */
6108 sh_handle_interrupt_handler_attribute (node
, name
, args
, flags
, no_add_attrs
)
6111 tree args ATTRIBUTE_UNUSED
;
6112 int flags ATTRIBUTE_UNUSED
;
6115 if (TREE_CODE (*node
) != FUNCTION_DECL
)
6117 warning ("`%s' attribute only applies to functions",
6118 IDENTIFIER_POINTER (name
));
6119 *no_add_attrs
= true;
6121 else if (TARGET_SHCOMPACT
)
6123 error ("attribute interrupt_handler is not compatible with -m5-compact");
6124 *no_add_attrs
= true;
6130 /* Handle an "sp_switch" attribute; arguments as in
6131 struct attribute_spec.handler. */
6133 sh_handle_sp_switch_attribute (node
, name
, args
, flags
, no_add_attrs
)
6137 int flags ATTRIBUTE_UNUSED
;
6140 if (TREE_CODE (*node
) != FUNCTION_DECL
)
6142 warning ("`%s' attribute only applies to functions",
6143 IDENTIFIER_POINTER (name
));
6144 *no_add_attrs
= true;
6146 else if (!pragma_interrupt
)
6148 /* The sp_switch attribute only has meaning for interrupt functions. */
6149 warning ("`%s' attribute only applies to interrupt functions",
6150 IDENTIFIER_POINTER (name
));
6151 *no_add_attrs
= true;
6153 else if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
6155 /* The argument must be a constant string. */
6156 warning ("`%s' attribute argument not a string constant",
6157 IDENTIFIER_POINTER (name
));
6158 *no_add_attrs
= true;
6162 sp_switch
= gen_rtx_SYMBOL_REF (VOIDmode
,
6163 TREE_STRING_POINTER (TREE_VALUE (args
)));
6169 /* Handle an "trap_exit" attribute; arguments as in
6170 struct attribute_spec.handler. */
6172 sh_handle_trap_exit_attribute (node
, name
, args
, flags
, no_add_attrs
)
6176 int flags ATTRIBUTE_UNUSED
;
6179 if (TREE_CODE (*node
) != FUNCTION_DECL
)
6181 warning ("`%s' attribute only applies to functions",
6182 IDENTIFIER_POINTER (name
));
6183 *no_add_attrs
= true;
6185 else if (!pragma_interrupt
)
6187 /* The trap_exit attribute only has meaning for interrupt functions. */
6188 warning ("`%s' attribute only applies to interrupt functions",
6189 IDENTIFIER_POINTER (name
));
6190 *no_add_attrs
= true;
6192 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
6194 /* The argument must be a constant integer. */
6195 warning ("`%s' attribute argument not an integer constant",
6196 IDENTIFIER_POINTER (name
));
6197 *no_add_attrs
= true;
6201 trap_exit
= TREE_INT_CST_LOW (TREE_VALUE (args
));
6208 sh_cfun_interrupt_handler_p ()
6210 return (lookup_attribute ("interrupt_handler",
6211 DECL_ATTRIBUTES (current_function_decl
))
6215 /* Predicates used by the templates. */
6217 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
6218 Used only in general_movsrc_operand. */
6221 system_reg_operand (op
, mode
)
6223 enum machine_mode mode ATTRIBUTE_UNUSED
;
6235 /* Returns 1 if OP can be source of a simple move operation.
6236 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
6237 invalid as are subregs of system registers. */
6240 general_movsrc_operand (op
, mode
)
6242 enum machine_mode mode
;
6244 if (GET_CODE (op
) == MEM
)
6246 rtx inside
= XEXP (op
, 0);
6247 if (GET_CODE (inside
) == CONST
)
6248 inside
= XEXP (inside
, 0);
6250 if (GET_CODE (inside
) == LABEL_REF
)
6253 if (GET_CODE (inside
) == PLUS
6254 && GET_CODE (XEXP (inside
, 0)) == LABEL_REF
6255 && GET_CODE (XEXP (inside
, 1)) == CONST_INT
)
6258 /* Only post inc allowed. */
6259 if (GET_CODE (inside
) == PRE_DEC
)
6263 if ((mode
== QImode
|| mode
== HImode
)
6264 && (GET_CODE (op
) == SUBREG
6265 && GET_CODE (XEXP (op
, 0)) == REG
6266 && system_reg_operand (XEXP (op
, 0), mode
)))
6269 return general_operand (op
, mode
);
6272 /* Returns 1 if OP can be a destination of a move.
6273 Same as general_operand, but no preinc allowed. */
6276 general_movdst_operand (op
, mode
)
6278 enum machine_mode mode
;
6280 /* Only pre dec allowed. */
6281 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
6284 return general_operand (op
, mode
);
6287 /* Returns 1 if OP is a normal arithmetic register. */
6290 arith_reg_operand (op
, mode
)
6292 enum machine_mode mode
;
6294 if (register_operand (op
, mode
))
6298 if (GET_CODE (op
) == REG
)
6300 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
6301 regno
= REGNO (SUBREG_REG (op
));
6305 return (regno
!= T_REG
&& regno
!= PR_REG
6306 && ! TARGET_REGISTER_P (regno
)
6307 && (regno
!= FPUL_REG
|| TARGET_SH4
)
6308 && regno
!= MACH_REG
&& regno
!= MACL_REG
);
6313 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
6314 because this would lead to missing sign extensions when truncating from
6315 DImode to SImode. */
6317 arith_reg_dest (op
, mode
)
6319 enum machine_mode mode
;
6321 if (mode
== DImode
&& GET_CODE (op
) == SUBREG
6322 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))) < 8)
6324 return arith_reg_operand (op
, mode
);
6328 int_gpr_dest (op
, mode
)
6330 enum machine_mode mode ATTRIBUTE_UNUSED
;
6332 enum machine_mode op_mode
= GET_MODE (op
);
6334 if (GET_MODE_CLASS (op_mode
) != MODE_INT
6335 || GET_MODE_SIZE (op_mode
) >= UNITS_PER_WORD
)
6337 if (! reload_completed
)
6339 return true_regnum (op
) <= LAST_GENERAL_REG
;
6343 fp_arith_reg_operand (op
, mode
)
6345 enum machine_mode mode
;
6347 if (register_operand (op
, mode
))
6351 if (GET_CODE (op
) == REG
)
6353 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
6354 regno
= REGNO (SUBREG_REG (op
));
6358 return (regno
>= FIRST_PSEUDO_REGISTER
6359 || FP_REGISTER_P (regno
));
6364 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
6367 arith_operand (op
, mode
)
6369 enum machine_mode mode
;
6371 if (arith_reg_operand (op
, mode
))
6376 /* FIXME: We should be checking whether the CONST_INT fits in a
6377 CONST_OK_FOR_J here, but this causes reload_cse to crash when
6378 attempting to transform a sequence of two 64-bit sets of the
6379 same register from literal constants into a set and an add,
6380 when the difference is too wide for an add. */
6381 if (GET_CODE (op
) == CONST_INT
6382 || EXTRA_CONSTRAINT_S (op
))
6387 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
6393 /* Returns 1 if OP is a valid source operand for a compare insn. */
6396 arith_reg_or_0_operand (op
, mode
)
6398 enum machine_mode mode
;
6400 if (arith_reg_operand (op
, mode
))
6403 if (EXTRA_CONSTRAINT_U (op
))
6409 /* Return 1 if OP is a valid source operand for an SHmedia operation
6410 that takes either a register or a 6-bit immediate. */
6413 shmedia_6bit_operand (op
, mode
)
6415 enum machine_mode mode
;
6417 return (arith_reg_operand (op
, mode
)
6418 || (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_O (INTVAL (op
))));
6421 /* Returns 1 if OP is a valid source operand for a logical operation. */
6424 logical_operand (op
, mode
)
6426 enum machine_mode mode
;
6428 if (arith_reg_operand (op
, mode
))
6433 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_P (INTVAL (op
)))
6438 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
6445 and_operand (op
, mode
)
6447 enum machine_mode mode
;
6449 if (logical_operand (op
, mode
))
6452 /* Check mshflo.l / mshflhi.l opportunities. */
6455 && GET_CODE (op
) == CONST_INT
6456 && (INTVAL (op
) == (unsigned) 0xffffffff
6457 || INTVAL (op
) == (HOST_WIDE_INT
) -1 << 32))
6463 /* Nonzero if OP is a floating point value with value 0.0. */
6466 fp_zero_operand (op
)
6471 if (GET_MODE (op
) != SFmode
)
6474 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
6475 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
6478 /* Nonzero if OP is a floating point value with value 1.0. */
6486 if (GET_MODE (op
) != SFmode
)
6489 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
6490 return REAL_VALUES_EQUAL (r
, dconst1
);
6493 /* For -m4 and -m4-single-only, mode switching is used. If we are
6494 compiling without -mfmovd, movsf_ie isn't taken into account for
6495 mode switching. We could check in machine_dependent_reorg for
6496 cases where we know we are in single precision mode, but there is
6497 interface to find that out during reload, so we must avoid
6498 choosing an fldi alternative during reload and thus failing to
6499 allocate a scratch register for the constant loading. */
6503 return ! TARGET_SH4
|| TARGET_FMOVD
|| reload_completed
;
6507 tertiary_reload_operand (op
, mode
)
6509 enum machine_mode mode ATTRIBUTE_UNUSED
;
6511 enum rtx_code code
= GET_CODE (op
);
6512 return code
== MEM
|| (TARGET_SH4
&& code
== CONST_DOUBLE
);
6516 fpscr_operand (op
, mode
)
6518 enum machine_mode mode ATTRIBUTE_UNUSED
;
6520 return (GET_CODE (op
) == REG
&& REGNO (op
) == FPSCR_REG
6521 && GET_MODE (op
) == PSImode
);
6525 fpul_operand (op
, mode
)
6527 enum machine_mode mode
;
6530 return fp_arith_reg_operand (op
, mode
);
6532 return (GET_CODE (op
) == REG
6533 && (REGNO (op
) == FPUL_REG
|| REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
6534 && GET_MODE (op
) == mode
);
6538 symbol_ref_operand (op
, mode
)
6540 enum machine_mode mode ATTRIBUTE_UNUSED
;
6542 return (GET_CODE (op
) == SYMBOL_REF
);
6545 /* Return the TLS type for TLS symbols, 0 for otherwise. */
6547 tls_symbolic_operand (op
, mode
)
6549 enum machine_mode mode ATTRIBUTE_UNUSED
;
6551 if (GET_CODE (op
) != SYMBOL_REF
)
6553 return SYMBOL_REF_TLS_MODEL (op
);
6557 commutative_float_operator (op
, mode
)
6559 enum machine_mode mode
;
6561 if (GET_MODE (op
) != mode
)
6563 switch (GET_CODE (op
))
6575 noncommutative_float_operator (op
, mode
)
6577 enum machine_mode mode
;
6579 if (GET_MODE (op
) != mode
)
6581 switch (GET_CODE (op
))
6593 unary_float_operator (op
, mode
)
6595 enum machine_mode mode
;
6597 if (GET_MODE (op
) != mode
)
6599 switch (GET_CODE (op
))
6612 binary_float_operator (op
, mode
)
6614 enum machine_mode mode
;
6616 if (GET_MODE (op
) != mode
)
6618 switch (GET_CODE (op
))
6632 binary_logical_operator (op
, mode
)
6634 enum machine_mode mode
;
6636 if (GET_MODE (op
) != mode
)
6638 switch (GET_CODE (op
))
6651 equality_comparison_operator (op
, mode
)
6653 enum machine_mode mode
;
6655 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
6656 && (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
));
6659 int greater_comparison_operator (op
, mode
)
6661 enum machine_mode mode
;
6663 if (mode
!= VOIDmode
&& GET_MODE (op
) == mode
)
6665 switch (GET_CODE (op
))
6677 int less_comparison_operator (op
, mode
)
6679 enum machine_mode mode
;
6681 if (mode
!= VOIDmode
&& GET_MODE (op
) == mode
)
6683 switch (GET_CODE (op
))
6695 /* Accept pseudos and branch target registers. */
6697 target_reg_operand (op
, mode
)
6699 enum machine_mode mode
;
6702 || GET_MODE (op
) != DImode
)
6705 if (GET_CODE (op
) == SUBREG
)
6708 if (GET_CODE (op
) != REG
)
6711 /* We must protect ourselves from matching pseudos that are virtual
6712 register, because they will eventually be replaced with hardware
6713 registers that aren't branch-target registers. */
6714 if (REGNO (op
) > LAST_VIRTUAL_REGISTER
6715 || TARGET_REGISTER_P (REGNO (op
)))
6721 /* Same as target_reg_operand, except that label_refs and symbol_refs
6722 are accepted before reload. */
6724 target_operand (op
, mode
)
6726 enum machine_mode mode
;
6731 if ((GET_MODE (op
) == DImode
|| GET_MODE (op
) == VOIDmode
)
6732 && EXTRA_CONSTRAINT_T (op
))
6733 return ! reload_completed
;
6735 return target_reg_operand (op
, mode
);
6739 mextr_bit_offset (op
, mode
)
6741 enum machine_mode mode ATTRIBUTE_UNUSED
;
6745 if (GET_CODE (op
) != CONST_INT
)
6748 return i
>= 1*8 && i
<= 7*8 && (i
& 7) == 0;
6752 extend_reg_operand (op
, mode
)
6754 enum machine_mode mode
;
6756 return (GET_CODE (op
) == TRUNCATE
6758 : arith_reg_operand
) (op
, mode
);
6762 trunc_hi_operand (op
, mode
)
6764 enum machine_mode mode
;
6766 enum machine_mode op_mode
= GET_MODE (op
);
6768 if (op_mode
!= SImode
&& op_mode
!= DImode
6769 && op_mode
!= V4HImode
&& op_mode
!= V2SImode
)
6771 return extend_reg_operand (op
, mode
);
6775 extend_reg_or_0_operand (op
, mode
)
6777 enum machine_mode mode
;
6779 return (GET_CODE (op
) == TRUNCATE
6781 : arith_reg_or_0_operand
) (op
, mode
);
6785 general_extend_operand (op
, mode
)
6787 enum machine_mode mode
;
6789 return (GET_CODE (op
) == TRUNCATE
6791 : nonimmediate_operand
) (op
, mode
);
6795 inqhi_operand (op
, mode
)
6797 enum machine_mode mode
;
6799 if (GET_CODE (op
) != TRUNCATE
|| mode
!= GET_MODE (op
))
6802 /* Can't use true_regnum here because copy_cost wants to know about
6803 SECONDARY_INPUT_RELOAD_CLASS. */
6804 return GET_CODE (op
) == REG
&& FP_REGISTER_P (REGNO (op
));
6808 sh_rep_vec (v
, mode
)
6810 enum machine_mode mode
;
6815 if ((GET_CODE (v
) != CONST_VECTOR
&& GET_CODE (v
) != PARALLEL
)
6816 || (GET_MODE (v
) != mode
&& mode
!= VOIDmode
))
6818 i
= XVECLEN (v
, 0) - 2;
6819 x
= XVECEXP (v
, 0, i
+ 1);
6820 if (GET_MODE_UNIT_SIZE (mode
) == 1)
6822 y
= XVECEXP (v
, 0, i
);
6823 for (i
-= 2 ; i
>= 0; i
-= 2)
6824 if (! rtx_equal_p (XVECEXP (v
, 0, i
+ 1), x
)
6825 || ! rtx_equal_p (XVECEXP (v
, 0, i
), y
))
6830 if (XVECEXP (v
, 0, i
) != x
)
6835 /* Determine if V is a constant vector matching MODE with only one element
6836 that is not a sign extension. Two byte-sized elements count as one. */
6838 sh_1el_vec (v
, mode
)
6840 enum machine_mode mode
;
6843 int i
, last
, least
, sign_ix
;
6846 if (GET_CODE (v
) != CONST_VECTOR
6847 || (GET_MODE (v
) != mode
&& mode
!= VOIDmode
))
6849 /* Determine numbers of last and of least significant elements. */
6850 last
= XVECLEN (v
, 0) - 1;
6851 least
= TARGET_LITTLE_ENDIAN
? 0 : last
;
6852 if (GET_CODE (XVECEXP (v
, 0, least
)) != CONST_INT
)
6855 if (GET_MODE_UNIT_SIZE (mode
) == 1)
6856 sign_ix
= TARGET_LITTLE_ENDIAN
? 1 : last
- 1;
6857 if (GET_CODE (XVECEXP (v
, 0, sign_ix
)) != CONST_INT
)
6859 unit_size
= GET_MODE_UNIT_SIZE (GET_MODE (v
));
6860 sign
= (INTVAL (XVECEXP (v
, 0, sign_ix
)) >> (unit_size
* BITS_PER_UNIT
- 1)
6861 ? constm1_rtx
: const0_rtx
);
6862 i
= XVECLEN (v
, 0) - 1;
6864 if (i
!= least
&& i
!= sign_ix
&& XVECEXP (v
, 0, i
) != sign
)
6871 sh_const_vec (v
, mode
)
6873 enum machine_mode mode
;
6877 if (GET_CODE (v
) != CONST_VECTOR
6878 || (GET_MODE (v
) != mode
&& mode
!= VOIDmode
))
6880 i
= XVECLEN (v
, 0) - 1;
6882 if (GET_CODE (XVECEXP (v
, 0, i
)) != CONST_INT
)
6887 /* Return the destination address of a branch. */
6890 branch_dest (branch
)
6893 rtx dest
= SET_SRC (PATTERN (branch
));
6896 if (GET_CODE (dest
) == IF_THEN_ELSE
)
6897 dest
= XEXP (dest
, 1);
6898 dest
= XEXP (dest
, 0);
6899 dest_uid
= INSN_UID (dest
);
6900 return INSN_ADDRESSES (dest_uid
);
6903 /* Return nonzero if REG is not used after INSN.
6904 We assume REG is a reload reg, and therefore does
6905 not live past labels. It may live past calls or jumps though. */
6907 reg_unused_after (reg
, insn
)
6914 /* If the reg is set by this instruction, then it is safe for our
6915 case. Disregard the case where this is a store to memory, since
6916 we are checking a register used in the store address. */
6917 set
= single_set (insn
);
6918 if (set
&& GET_CODE (SET_DEST (set
)) != MEM
6919 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6922 while ((insn
= NEXT_INSN (insn
)))
6924 code
= GET_CODE (insn
);
6927 /* If this is a label that existed before reload, then the register
6928 if dead here. However, if this is a label added by reorg, then
6929 the register may still be live here. We can't tell the difference,
6930 so we just ignore labels completely. */
6931 if (code
== CODE_LABEL
)
6936 if (code
== JUMP_INSN
)
6939 /* If this is a sequence, we must handle them all at once.
6940 We could have for instance a call that sets the target register,
6941 and an insn in a delay slot that uses the register. In this case,
6942 we must return 0. */
6943 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
6948 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
6950 rtx this_insn
= XVECEXP (PATTERN (insn
), 0, i
);
6951 rtx set
= single_set (this_insn
);
6953 if (GET_CODE (this_insn
) == CALL_INSN
)
6955 else if (GET_CODE (this_insn
) == JUMP_INSN
)
6957 if (INSN_ANNULLED_BRANCH_P (this_insn
))
6962 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
6964 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6966 if (GET_CODE (SET_DEST (set
)) != MEM
)
6972 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
6977 else if (code
== JUMP_INSN
)
6980 else if (GET_RTX_CLASS (code
) == 'i')
6982 rtx set
= single_set (insn
);
6984 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
6986 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6987 return GET_CODE (SET_DEST (set
)) != MEM
;
6988 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
6992 if (code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
7000 static GTY(()) rtx fpscr_rtx
;
7006 fpscr_rtx
= gen_rtx (REG
, PSImode
, FPSCR_REG
);
7007 REG_USERVAR_P (fpscr_rtx
) = 1;
7008 mark_user_reg (fpscr_rtx
);
7010 if (! reload_completed
|| mdep_reorg_phase
!= SH_AFTER_MDEP_REORG
)
7011 mark_user_reg (fpscr_rtx
);
7030 expand_sf_unop (fun
, operands
)
7031 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
7034 emit_sf_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
7038 expand_sf_binop (fun
, operands
)
7039 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
7042 emit_sf_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
7047 expand_df_unop (fun
, operands
)
7048 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
7051 emit_df_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
7055 expand_df_binop (fun
, operands
)
7056 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
7059 emit_df_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
7063 /* ??? gcc does flow analysis strictly after common subexpression
7064 elimination. As a result, common subexpression elimination fails
7065 when there are some intervening statements setting the same register.
7066 If we did nothing about this, this would hurt the precision switching
7067 for SH4 badly. There is some cse after reload, but it is unable to
7068 undo the extra register pressure from the unused instructions, and
7069 it cannot remove auto-increment loads.
7071 A C code example that shows this flow/cse weakness for (at least) SH
7072 and sparc (as of gcc ss-970706) is this:
7086 So we add another pass before common subexpression elimination, to
7087 remove assignments that are dead due to a following assignment in the
7088 same basic block. */
7091 mark_use (x
, reg_set_block
)
7092 rtx x
, *reg_set_block
;
7098 code
= GET_CODE (x
);
7103 int regno
= REGNO (x
);
7104 int nregs
= (regno
< FIRST_PSEUDO_REGISTER
7105 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
))
7109 reg_set_block
[regno
+ nregs
- 1] = 0;
7116 rtx dest
= SET_DEST (x
);
7118 if (GET_CODE (dest
) == SUBREG
)
7119 dest
= SUBREG_REG (dest
);
7120 if (GET_CODE (dest
) != REG
)
7121 mark_use (dest
, reg_set_block
);
7122 mark_use (SET_SRC (x
), reg_set_block
);
7129 const char *fmt
= GET_RTX_FORMAT (code
);
7131 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7134 mark_use (XEXP (x
, i
), reg_set_block
);
7135 else if (fmt
[i
] == 'E')
7136 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7137 mark_use (XVECEXP (x
, i
, j
), reg_set_block
);
7144 static rtx get_free_reg
PARAMS ((HARD_REG_SET
));
7146 /* This function returns a register to use to load the address to load
7147 the fpscr from. Currently it always returns r1 or r7, but when we are
7148 able to use pseudo registers after combine, or have a better mechanism
7149 for choosing a register, it should be done here. */
7150 /* REGS_LIVE is the liveness information for the point for which we
7151 need this allocation. In some bare-bones exit blocks, r1 is live at the
7152 start. We can even have all of r0..r3 being live:
7153 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
7154 INSN before which new insns are placed with will clobber the register
7155 we return. If a basic block consists only of setting the return value
7156 register to a pseudo and using that register, the return value is not
7157 live before or after this block, yet we we'll insert our insns right in
7161 get_free_reg (regs_live
)
7162 HARD_REG_SET regs_live
;
7164 if (! TEST_HARD_REG_BIT (regs_live
, 1))
7165 return gen_rtx_REG (Pmode
, 1);
7167 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
7168 there shouldn't be anything but a jump before the function end. */
7169 if (! TEST_HARD_REG_BIT (regs_live
, 7))
7170 return gen_rtx_REG (Pmode
, 7);
7175 /* This function will set the fpscr from memory.
7176 MODE is the mode we are setting it to. */
7178 fpscr_set_from_mem (mode
, regs_live
)
7180 HARD_REG_SET regs_live
;
7182 enum attr_fp_mode fp_mode
= mode
;
7183 rtx addr_reg
= get_free_reg (regs_live
);
7185 if (fp_mode
== (enum attr_fp_mode
) ACTUAL_NORMAL_MODE (FP_MODE
))
7186 emit_insn (gen_fpu_switch1 (addr_reg
));
7188 emit_insn (gen_fpu_switch0 (addr_reg
));
7191 /* Is the given character a logical line separator for the assembler? */
7192 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
7193 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
7197 sh_insn_length_adjustment (insn
)
7200 /* Instructions with unfilled delay slots take up an extra two bytes for
7201 the nop in the delay slot. */
7202 if (((GET_CODE (insn
) == INSN
7203 && GET_CODE (PATTERN (insn
)) != USE
7204 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
7205 || GET_CODE (insn
) == CALL_INSN
7206 || (GET_CODE (insn
) == JUMP_INSN
7207 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
7208 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
))
7209 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
7210 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
7213 /* SH2e has a bug that prevents the use of annulled branches, so if
7214 the delay slot is not filled, we'll have to put a NOP in it. */
7215 if (sh_cpu
== CPU_SH2E
7216 && GET_CODE (insn
) == JUMP_INSN
7217 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
7218 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
7219 && get_attr_type (insn
) == TYPE_CBRANCH
7220 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
)
7223 /* sh-dsp parallel processing insn take four bytes instead of two. */
7225 if (GET_CODE (insn
) == INSN
)
7228 rtx body
= PATTERN (insn
);
7229 const char *template;
7231 int maybe_label
= 1;
7233 if (GET_CODE (body
) == ASM_INPUT
)
7234 template = XSTR (body
, 0);
7235 else if (asm_noperands (body
) >= 0)
7237 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
);
7246 while (c
== ' ' || c
== '\t');
7247 /* all sh-dsp parallel-processing insns start with p.
7248 The only non-ppi sh insn starting with p is pref.
7249 The only ppi starting with pr is prnd. */
7250 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", template, 2))
7252 /* The repeat pseudo-insn expands two three insns, a total of
7253 six bytes in size. */
7254 else if ((c
== 'r' || c
== 'R')
7255 && ! strncasecmp ("epeat", template, 5))
7257 while (c
&& c
!= '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
))
7259 /* If this is a label, it is obviously not a ppi insn. */
7260 if (c
== ':' && maybe_label
)
7265 else if (c
== '\'' || c
== '"')
7270 maybe_label
= c
!= ':';
7278 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
7279 isn't protected by a PIC unspec. */
7281 nonpic_symbol_mentioned_p (x
)
7284 register const char *fmt
;
7287 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
7288 || GET_CODE (x
) == PC
)
7291 /* We don't want to look into the possible MEM location of a
7292 CONST_DOUBLE, since we're not going to use it, in general. */
7293 if (GET_CODE (x
) == CONST_DOUBLE
)
7296 if (GET_CODE (x
) == UNSPEC
7297 && (XINT (x
, 1) == UNSPEC_PIC
7298 || XINT (x
, 1) == UNSPEC_GOT
7299 || XINT (x
, 1) == UNSPEC_GOTOFF
7300 || XINT (x
, 1) == UNSPEC_GOTPLT
7301 || XINT (x
, 1) == UNSPEC_GOTTPOFF
7302 || XINT (x
, 1) == UNSPEC_DTPOFF
7303 || XINT (x
, 1) == UNSPEC_PLT
))
7306 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
7307 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
7313 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7314 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
7317 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
7324 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
7325 @GOTOFF in `reg'. */
7327 legitimize_pic_address (orig
, mode
, reg
)
7329 enum machine_mode mode ATTRIBUTE_UNUSED
;
7332 if (tls_symbolic_operand (orig
, Pmode
))
7335 if (GET_CODE (orig
) == LABEL_REF
7336 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
7339 reg
= gen_reg_rtx (Pmode
);
7341 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
7344 else if (GET_CODE (orig
) == SYMBOL_REF
)
7347 reg
= gen_reg_rtx (Pmode
);
7349 emit_insn (gen_symGOT2reg (reg
, orig
));
7355 /* Mark the use of a constant in the literal table. If the constant
7356 has multiple labels, make it unique. */
7358 mark_constant_pool_use (x
)
7361 rtx insn
, lab
, pattern
;
7366 switch (GET_CODE (x
))
7376 /* Get the first label in the list of labels for the same constant
7377 and delete another labels in the list. */
7379 for (insn
= PREV_INSN (x
); insn
; insn
= PREV_INSN (insn
))
7381 if (GET_CODE (insn
) != CODE_LABEL
7382 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
7387 for (insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
7388 INSN_DELETED_P (insn
) = 1;
7390 /* Mark constants in a window. */
7391 for (insn
= NEXT_INSN (x
); insn
; insn
= NEXT_INSN (insn
))
7393 if (GET_CODE (insn
) != INSN
)
7396 pattern
= PATTERN (insn
);
7397 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
7400 switch (XINT (pattern
, 1))
7402 case UNSPECV_CONST2
:
7403 case UNSPECV_CONST4
:
7404 case UNSPECV_CONST8
:
7405 XVECEXP (pattern
, 0, 1) = const1_rtx
;
7407 case UNSPECV_WINDOW_END
:
7408 if (XVECEXP (pattern
, 0, 0) == x
)
7411 case UNSPECV_CONST_END
:
7421 /* Return true if it's possible to redirect BRANCH1 to the destination
7422 of an unconditional jump BRANCH2. We only want to do this if the
7423 resulting branch will have a short displacement. */
7425 sh_can_redirect_branch (branch1
, branch2
)
7429 if (flag_expensive_optimizations
&& simplejump_p (branch2
))
7431 rtx dest
= XEXP (SET_SRC (single_set (branch2
)), 0);
7435 for (distance
= 0, insn
= NEXT_INSN (branch1
);
7436 insn
&& distance
< 256;
7437 insn
= PREV_INSN (insn
))
7442 distance
+= get_attr_length (insn
);
7444 for (distance
= 0, insn
= NEXT_INSN (branch1
);
7445 insn
&& distance
< 256;
7446 insn
= NEXT_INSN (insn
))
7451 distance
+= get_attr_length (insn
);
7457 /* Return nonzero if register old_reg can be renamed to register new_reg. */
7459 sh_hard_regno_rename_ok (old_reg
, new_reg
)
7460 unsigned int old_reg ATTRIBUTE_UNUSED
;
7461 unsigned int new_reg
;
7464 /* Interrupt functions can only use registers that have already been
7465 saved by the prologue, even if they would normally be
7468 if (sh_cfun_interrupt_handler_p () && !regs_ever_live
[new_reg
])
7474 /* Function to update the integer COST
7475 based on the relationship between INSN that is dependent on
7476 DEP_INSN through the dependence LINK. The default is to make no
7477 adjustment to COST. This can be used for example to specify to
7478 the scheduler that an output- or anti-dependence does not incur
7479 the same cost as a data-dependence. The return value should be
7480 the new value for COST. */
7482 sh_adjust_cost (insn
, link
, dep_insn
, cost
)
7484 rtx link ATTRIBUTE_UNUSED
;
7492 /* On SHmedia, if the dependence is an anti-dependence or
7493 output-dependence, there is no cost. */
7494 if (REG_NOTE_KIND (link
) != 0)
7497 if (get_attr_is_mac_media (insn
)
7498 && get_attr_is_mac_media (dep_insn
))
7501 else if (REG_NOTE_KIND (link
) == 0)
7503 enum attr_type dep_type
, type
;
7505 if (recog_memoized (insn
) < 0
7506 || recog_memoized (dep_insn
) < 0)
7509 dep_type
= get_attr_type (dep_insn
);
7510 if (dep_type
== TYPE_FLOAD
|| dep_type
== TYPE_PCFLOAD
)
7512 if ((dep_type
== TYPE_LOAD_SI
|| dep_type
== TYPE_PCLOAD_SI
)
7513 && (type
= get_attr_type (insn
)) != TYPE_CALL
7514 && type
!= TYPE_SFUNC
)
7517 /* The only input for a call that is timing-critical is the
7518 function's address. */
7519 if (GET_CODE(insn
) == CALL_INSN
)
7521 rtx call
= PATTERN (insn
);
7523 if (GET_CODE (call
) == PARALLEL
)
7524 call
= XVECEXP (call
, 0 ,0);
7525 if (GET_CODE (call
) == SET
)
7526 call
= SET_SRC (call
);
7527 if (GET_CODE (call
) == CALL
&& GET_CODE (XEXP (call
, 0)) == MEM
7528 && ! reg_set_p (XEXP (XEXP (call
, 0), 0), dep_insn
))
7531 /* Likewise, the most timing critical input for an sfuncs call
7532 is the function address. However, sfuncs typically start
7533 using their arguments pretty quickly.
7534 Assume a four cycle delay before they are needed. */
7535 /* All sfunc calls are parallels with at least four components.
7536 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
7537 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
7538 && XVECLEN (PATTERN (insn
), 0) >= 4
7539 && (reg
= sfunc_uses_reg (insn
)))
7541 if (! reg_set_p (reg
, dep_insn
))
7544 /* When the preceding instruction loads the shift amount of
7545 the following SHAD/SHLD, the latency of the load is increased
7548 && get_attr_type (insn
) == TYPE_DYN_SHIFT
7549 && get_attr_any_int_load (dep_insn
) == ANY_INT_LOAD_YES
7550 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn
)),
7551 XEXP (SET_SRC (single_set(insn
)),
7554 /* When an LS group instruction with a latency of less than
7555 3 cycles is followed by a double-precision floating-point
7556 instruction, FIPR, or FTRV, the latency of the first
7557 instruction is increased to 3 cycles. */
7559 && get_attr_insn_class (dep_insn
) == INSN_CLASS_LS_GROUP
7560 && get_attr_dfp_comp (insn
) == DFP_COMP_YES
)
7562 /* The lsw register of a double-precision computation is ready one
7564 else if (reload_completed
7565 && get_attr_dfp_comp (dep_insn
) == DFP_COMP_YES
7566 && (use_pat
= single_set (insn
))
7567 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn
))),
7571 if (get_attr_any_fp_comp (dep_insn
) == ANY_FP_COMP_YES
7572 && get_attr_late_fp_use (insn
) == LATE_FP_USE_YES
)
7575 /* An anti-dependence penalty of two applies if the first insn is a double
7576 precision fadd / fsub / fmul. */
7577 else if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
7578 && recog_memoized (dep_insn
) >= 0
7579 && get_attr_type (dep_insn
) == TYPE_DFP_ARITH
7580 /* A lot of alleged anti-flow dependences are fake,
7581 so check this one is real. */
7582 && flow_dependent_p (dep_insn
, insn
))
7589 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
7590 if DEP_INSN is anti-flow dependent on INSN. */
7592 flow_dependent_p (insn
, dep_insn
)
7595 rtx tmp
= PATTERN (insn
);
7597 note_stores (PATTERN (dep_insn
), flow_dependent_p_1
, &tmp
);
7598 return tmp
== NULL_RTX
;
7601 /* A helper function for flow_dependent_p called through note_stores. */
7603 flow_dependent_p_1 (x
, pat
, data
)
7605 rtx pat ATTRIBUTE_UNUSED
;
7608 rtx
* pinsn
= (rtx
*) data
;
7610 if (*pinsn
&& reg_referenced_p (x
, *pinsn
))
7614 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
7615 'special function' patterns (type sfunc) that clobber pr, but that
7616 do not look like function calls to leaf_function_p. Hence we must
7617 do this extra check. */
7621 return REG_N_SETS (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
7624 /* This Function returns nonzero if the DFA based scheduler interface
7625 is to be used. At present this is supported for the SH4 only. */
7627 sh_use_dfa_interface()
7629 if (TARGET_HARD_SH4
)
7635 /* This function returns "2" to indicate dual issue for the SH4
7636 processor. To be used by the DFA pipeline description. */
7640 if (TARGET_SUPERSCALAR
)
7646 /* SHmedia requires registers for branches, so we can't generate new
7647 branches past reload. */
7649 sh_cannot_modify_jumps_p ()
7651 return (TARGET_SHMEDIA
&& (reload_in_progress
|| reload_completed
));
7655 sh_ms_bitfield_layout_p (record_type
)
7656 tree record_type ATTRIBUTE_UNUSED
;
7662 On the SH1..SH4, the trampoline looks like
7663 2 0002 D202 mov.l l2,r2
7664 1 0000 D301 mov.l l1,r3
7667 5 0008 00000000 l1: .long area
7668 6 000c 00000000 l2: .long function
7670 SH5 (compact) uses r1 instead of r3 for the static chain. */
7673 /* Emit RTL insns to initialize the variable parts of a trampoline.
7674 FNADDR is an RTX for the address of the function's pure code.
7675 CXT is an RTX for the static chain value for the function. */
7678 sh_initialize_trampoline (tramp
, fnaddr
, cxt
)
7679 rtx tramp
, fnaddr
, cxt
;
7681 if (TARGET_SHMEDIA64
)
7686 rtx movi1
= GEN_INT (0xcc000010);
7687 rtx shori1
= GEN_INT (0xc8000010);
7690 /* The following trampoline works within a +- 128 KB range for cxt:
7691 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
7692 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
7693 gettr tr1,r1; blink tr0,r63 */
7694 /* Address rounding makes it hard to compute the exact bounds of the
7695 offset for this trampoline, but we have a rather generous offset
7696 range, so frame_offset should do fine as an upper bound. */
7697 if (cxt
== virtual_stack_vars_rtx
&& frame_offset
< 0x20000)
7699 /* ??? could optimize this trampoline initialization
7700 by writing DImode words with two insns each. */
7701 rtx mask
= force_reg (DImode
, GEN_INT (0x3fffc00));
7702 rtx insn
= gen_rtx_MINUS (DImode
, cxt
, tramp
);
7703 insn
= gen_rtx_ASHIFT (DImode
, insn
, GEN_INT (10-2));
7704 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7705 /* Or in ptb/u .,tr1 pattern */
7706 insn
= gen_rtx_IOR (DImode
, insn
, gen_int_mode (0xec000010, SImode
));
7707 insn
= force_operand (insn
, NULL_RTX
);
7708 insn
= gen_lowpart (SImode
, insn
);
7709 emit_move_insn (gen_rtx_MEM (SImode
, tramp
), insn
);
7710 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (38));
7711 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7712 insn
= force_operand (gen_rtx_IOR (DImode
, movi1
, insn
), NULL_RTX
);
7713 insn
= gen_lowpart (SImode
, insn
);
7714 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)), insn
);
7715 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (22));
7716 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7717 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
7718 insn
= gen_lowpart (SImode
, insn
);
7719 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)), insn
);
7720 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (6));
7721 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7722 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
7723 insn
= gen_lowpart (SImode
, insn
);
7724 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7726 insn
= gen_rtx_ASHIFT (DImode
, fnaddr
, GEN_INT (10));
7727 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7728 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
7729 insn
= gen_lowpart (SImode
, insn
);
7730 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 16)),
7732 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 20)),
7733 GEN_INT (0x6bf10600));
7734 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 24)),
7735 GEN_INT (0x4415fc10));
7736 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 28)),
7737 GEN_INT (0x4401fff0));
7738 emit_insn (gen_ic_invalidate_line (tramp
));
7741 tramp_templ
= gen_rtx_SYMBOL_REF (Pmode
,"__GCC_nested_trampoline");
7742 fixed_len
= TRAMPOLINE_SIZE
- 2 * GET_MODE_SIZE (Pmode
);
7744 tramp_templ
= gen_datalabel_ref (tramp_templ
);
7745 dst
= gen_rtx_MEM (BLKmode
, tramp
);
7746 src
= gen_rtx_MEM (BLKmode
, tramp_templ
);
7747 set_mem_align (dst
, 256);
7748 set_mem_align (src
, 64);
7749 emit_block_move (dst
, src
, GEN_INT (fixed_len
), BLOCK_OP_NORMAL
);
7751 emit_move_insn (gen_rtx_MEM (Pmode
, plus_constant (tramp
, fixed_len
)),
7753 emit_move_insn (gen_rtx_MEM (Pmode
,
7754 plus_constant (tramp
,
7756 + GET_MODE_SIZE (Pmode
))),
7758 emit_insn (gen_ic_invalidate_line (tramp
));
7761 else if (TARGET_SHMEDIA
)
7763 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
7764 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
7765 rtx quad0
= gen_reg_rtx (DImode
), cxtload
= gen_reg_rtx (DImode
);
7766 rtx quad1
= gen_reg_rtx (DImode
), quad2
= gen_reg_rtx (DImode
);
7767 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
7768 rotated 10 right, and higher 16 bit of every 32 selected. */
7770 = force_reg (V2HImode
, (simplify_gen_subreg
7771 (V2HImode
, GEN_INT (0x4330432), SImode
, 0)));
7772 rtx ptabs
= force_reg (DImode
, GEN_INT (0x6bf10600));
7773 rtx blink
= force_reg (DImode
, GEN_INT (0x4401fff0));
7775 tramp
= force_reg (Pmode
, tramp
);
7776 fnaddr
= force_reg (SImode
, fnaddr
);
7777 cxt
= force_reg (SImode
, cxt
);
7778 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, quad0
, 0),
7779 gen_rtx_SUBREG (V2HImode
, fnaddr
, 0),
7781 emit_insn (gen_rotrdi3_mextr (quad0
, quad0
,
7782 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
7783 emit_insn (gen_ashldi3_media (quad0
, quad0
, GEN_INT (2)));
7784 emit_move_insn (gen_rtx_MEM (DImode
, tramp
), quad0
);
7785 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, cxtload
, 0),
7786 gen_rtx_SUBREG (V2HImode
, cxt
, 0),
7788 emit_insn (gen_rotrdi3_mextr (cxtload
, cxtload
,
7789 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
7790 emit_insn (gen_ashldi3_media (cxtload
, cxtload
, GEN_INT (2)));
7791 if (TARGET_LITTLE_ENDIAN
)
7793 emit_insn (gen_mshflo_l_di (quad1
, ptabs
, cxtload
));
7794 emit_insn (gen_mextr4 (quad2
, cxtload
, blink
));
7798 emit_insn (gen_mextr4 (quad1
, cxtload
, ptabs
));
7799 emit_insn (gen_mshflo_l_di (quad2
, blink
, cxtload
));
7801 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)), quad1
);
7802 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), quad2
);
7803 emit_insn (gen_ic_invalidate_line (tramp
));
7806 else if (TARGET_SHCOMPACT
)
7808 emit_insn (gen_initialize_trampoline (tramp
, cxt
, fnaddr
));
7811 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
7812 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0xd301d202 : 0xd202d301,
7814 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7815 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0x0009422b : 0x422b0009,
7817 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7819 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7823 if (TARGET_USERMODE
)
7824 emit_library_call (function_symbol ("__ic_invalidate"),
7825 0, VOIDmode
, 1, tramp
, SImode
);
7827 emit_insn (gen_ic_invalidate_line (tramp
));
7831 /* FIXME: This is overly conservative. A SHcompact function that
7832 receives arguments ``by reference'' will have them stored in its
7833 own stack frame, so it must not pass pointers or references to
7834 these arguments to other functions by means of sibling calls. */
7836 sh_function_ok_for_sibcall (decl
, exp
)
7838 tree exp ATTRIBUTE_UNUSED
;
7841 && (! TARGET_SHCOMPACT
7842 || current_function_args_info
.stack_regs
== 0)
7843 && ! sh_cfun_interrupt_handler_p ());
7846 /* Machine specific built-in functions. */
7848 struct builtin_description
7850 const enum insn_code icode
;
7851 const char *const name
;
7855 /* describe number and signedness of arguments; arg[0] == result
7856 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
7857 static const char signature_args
[][4] =
7859 #define SH_BLTIN_V2SI2 0
7861 #define SH_BLTIN_V4HI2 1
7863 #define SH_BLTIN_V2SI3 2
7865 #define SH_BLTIN_V4HI3 3
7867 #define SH_BLTIN_V8QI3 4
7869 #define SH_BLTIN_MAC_HISI 5
7871 #define SH_BLTIN_SH_HI 6
7873 #define SH_BLTIN_SH_SI 7
7875 #define SH_BLTIN_V4HI2V2SI 8
7877 #define SH_BLTIN_V4HI2V8QI 9
7879 #define SH_BLTIN_SISF 10
7881 #define SH_BLTIN_LDUA_L 11
7883 #define SH_BLTIN_LDUA_Q 12
7885 #define SH_BLTIN_STUA_L 13
7887 #define SH_BLTIN_STUA_Q 14
7889 #define SH_BLTIN_UDI 15
7891 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
7892 #define SH_BLTIN_2 16
7893 #define SH_BLTIN_SU 16
7895 #define SH_BLTIN_3 17
7896 #define SH_BLTIN_SUS 17
7898 #define SH_BLTIN_PSSV 18
7900 #define SH_BLTIN_XXUU 19
7901 #define SH_BLTIN_UUUU 19
7903 #define SH_BLTIN_PV 20
7906 /* mcmv: operands considered unsigned. */
7907 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
7908 /* mperm: control value considered unsigned int. */
7909 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
7910 /* mshards_q: returns signed short. */
7911 /* nsb: takes long long arg, returns unsigned char. */
7912 static const struct builtin_description bdesc
[] =
7914 { CODE_FOR_absv2si2
, "__builtin_absv2si2", SH_BLTIN_V2SI2
},
7915 { CODE_FOR_absv4hi2
, "__builtin_absv4hi2", SH_BLTIN_V4HI2
},
7916 { CODE_FOR_addv2si3
, "__builtin_addv2si3", SH_BLTIN_V2SI3
},
7917 { CODE_FOR_addv4hi3
, "__builtin_addv4hi3", SH_BLTIN_V4HI3
},
7918 { CODE_FOR_ssaddv2si3
,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3
},
7919 { CODE_FOR_usaddv8qi3
,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3
},
7920 { CODE_FOR_ssaddv4hi3
,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3
},
7922 { CODE_FOR_alloco32
, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV
},
7923 { CODE_FOR_alloco64
, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV
},
7925 { CODE_FOR_negcmpeqv8qi
,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3
},
7926 { CODE_FOR_negcmpeqv2si
,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3
},
7927 { CODE_FOR_negcmpeqv4hi
,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3
},
7928 { CODE_FOR_negcmpgtuv8qi
,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3
},
7929 { CODE_FOR_negcmpgtv2si
,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3
},
7930 { CODE_FOR_negcmpgtv4hi
,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3
},
7931 { CODE_FOR_mcmv
, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU
},
7932 { CODE_FOR_mcnvs_lw
, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3
},
7933 { CODE_FOR_mcnvs_wb
, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI
},
7934 { CODE_FOR_mcnvs_wub
, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI
},
7935 { CODE_FOR_mextr1
, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI
},
7936 { CODE_FOR_mextr2
, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI
},
7937 { CODE_FOR_mextr3
, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI
},
7938 { CODE_FOR_mextr4
, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI
},
7939 { CODE_FOR_mextr5
, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI
},
7940 { CODE_FOR_mextr6
, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI
},
7941 { CODE_FOR_mextr7
, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI
},
7942 { CODE_FOR_mmacfx_wl
, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI
},
7943 { CODE_FOR_mmacnfx_wl
,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI
},
7944 { CODE_FOR_mulv2si3
, "__builtin_mulv2si3", SH_BLTIN_V2SI3
, },
7945 { CODE_FOR_mulv4hi3
, "__builtin_mulv4hi3", SH_BLTIN_V4HI3
},
7946 { CODE_FOR_mmulfx_l
, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3
},
7947 { CODE_FOR_mmulfx_w
, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3
},
7948 { CODE_FOR_mmulfxrp_w
,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3
},
7949 { CODE_FOR_mmulhi_wl
, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI
},
7950 { CODE_FOR_mmullo_wl
, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI
},
7951 { CODE_FOR_mmulsum_wq
,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU
},
7952 { CODE_FOR_mperm_w
, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI
},
7953 { CODE_FOR_msad_ubq
, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU
},
7954 { CODE_FOR_mshalds_l
, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI
},
7955 { CODE_FOR_mshalds_w
, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI
},
7956 { CODE_FOR_ashrv2si3
, "__builtin_ashrv2si3", SH_BLTIN_SH_SI
},
7957 { CODE_FOR_ashrv4hi3
, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI
},
7958 { CODE_FOR_mshards_q
, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS
},
7959 { CODE_FOR_mshfhi_b
, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3
},
7960 { CODE_FOR_mshfhi_l
, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3
},
7961 { CODE_FOR_mshfhi_w
, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3
},
7962 { CODE_FOR_mshflo_b
, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3
},
7963 { CODE_FOR_mshflo_l
, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3
},
7964 { CODE_FOR_mshflo_w
, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3
},
7965 { CODE_FOR_ashlv2si3
, "__builtin_ashlv2si3", SH_BLTIN_SH_SI
},
7966 { CODE_FOR_ashlv4hi3
, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI
},
7967 { CODE_FOR_lshrv2si3
, "__builtin_lshrv2si3", SH_BLTIN_SH_SI
},
7968 { CODE_FOR_lshrv4hi3
, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI
},
7969 { CODE_FOR_subv2si3
, "__builtin_subv2si3", SH_BLTIN_V2SI3
},
7970 { CODE_FOR_subv4hi3
, "__builtin_subv4hi3", SH_BLTIN_V4HI3
},
7971 { CODE_FOR_sssubv2si3
,"__builtin_sssubv2si3", SH_BLTIN_V2SI3
},
7972 { CODE_FOR_ussubv8qi3
,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3
},
7973 { CODE_FOR_sssubv4hi3
,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3
},
7974 { CODE_FOR_fcosa_s
, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF
},
7975 { CODE_FOR_fsina_s
, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF
},
7976 { CODE_FOR_fipr
, "__builtin_sh_media_FIPR_S", SH_BLTIN_3
},
7977 { CODE_FOR_ftrv
, "__builtin_sh_media_FTRV_S", SH_BLTIN_3
},
7978 { CODE_FOR_fsrra_s
, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2
},
7980 { CODE_FOR_ldhi_l
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L
},
7981 { CODE_FOR_ldhi_q
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q
},
7982 { CODE_FOR_ldlo_l
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L
},
7983 { CODE_FOR_ldlo_q
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q
},
7984 { CODE_FOR_sthi_l
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L
},
7985 { CODE_FOR_sthi_q
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q
},
7986 { CODE_FOR_stlo_l
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L
},
7987 { CODE_FOR_stlo_q
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q
},
7988 { CODE_FOR_ldhi_l64
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L
},
7989 { CODE_FOR_ldhi_q64
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q
},
7990 { CODE_FOR_ldlo_l64
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L
},
7991 { CODE_FOR_ldlo_q64
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q
},
7992 { CODE_FOR_sthi_l64
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L
},
7993 { CODE_FOR_sthi_q64
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q
},
7994 { CODE_FOR_stlo_l64
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L
},
7995 { CODE_FOR_stlo_q64
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q
},
7997 { CODE_FOR_nsb
, "__builtin_sh_media_NSB", SH_BLTIN_SU
},
7998 { CODE_FOR_byterev
, "__builtin_sh_media_BYTEREV", SH_BLTIN_2
},
8000 { CODE_FOR_prefetch32
,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV
},
8001 { CODE_FOR_prefetch64
,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV
}
8006 sh_media_init_builtins ()
8008 tree shared
[SH_BLTIN_NUM_SHARED_SIGNATURES
];
8009 const struct builtin_description
*d
;
8011 memset (shared
, 0, sizeof shared
);
8012 for (d
= bdesc
; d
- bdesc
< (int) (sizeof bdesc
/ sizeof bdesc
[0]); d
++)
8014 tree type
, arg_type
;
8015 int signature
= d
->signature
;
8018 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
&& shared
[signature
])
8019 type
= shared
[signature
];
8022 int has_result
= signature_args
[signature
][0] != 0;
8024 if (signature_args
[signature
][1] == 8
8025 && (insn_data
[d
->icode
].operand
[has_result
].mode
!= Pmode
))
8027 if (! TARGET_FPU_ANY
8028 && FLOAT_MODE_P (insn_data
[d
->icode
].operand
[0].mode
))
8030 type
= void_list_node
;
8033 int arg
= signature_args
[signature
][i
];
8034 int opno
= i
- 1 + has_result
;
8037 arg_type
= ptr_type_node
;
8039 arg_type
= ((*lang_hooks
.types
.type_for_mode
)
8040 (insn_data
[d
->icode
].operand
[opno
].mode
,
8045 arg_type
= void_type_node
;
8048 type
= tree_cons (NULL_TREE
, arg_type
, type
);
8050 type
= build_function_type (arg_type
, type
);
8051 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
)
8052 shared
[signature
] = type
;
8054 builtin_function (d
->name
, type
, d
- bdesc
, BUILT_IN_MD
,
8063 sh_media_init_builtins ();
8066 /* Expand an expression EXP that calls a built-in function,
8067 with result going to TARGET if that's convenient
8068 (and in mode MODE if that's convenient).
8069 SUBTARGET may be used as the target for computing one of EXP's operands.
8070 IGNORE is nonzero if the value is to be ignored. */
8073 sh_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
8076 rtx subtarget ATTRIBUTE_UNUSED
;
8077 enum machine_mode mode ATTRIBUTE_UNUSED
;
8080 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8081 tree arglist
= TREE_OPERAND (exp
, 1);
8082 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8083 const struct builtin_description
*d
= &bdesc
[fcode
];
8084 enum insn_code icode
= d
->icode
;
8085 int signature
= d
->signature
;
8086 enum machine_mode tmode
= VOIDmode
;
8091 if (signature_args
[signature
][0])
8096 tmode
= insn_data
[icode
].operand
[0].mode
;
8098 || GET_MODE (target
) != tmode
8099 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8100 target
= gen_reg_rtx (tmode
);
8106 for (i
= 1; i
<= 3; i
++, nop
++)
8109 enum machine_mode opmode
, argmode
;
8111 if (! signature_args
[signature
][i
])
8113 arg
= TREE_VALUE (arglist
);
8114 if (arg
== error_mark_node
)
8116 arglist
= TREE_CHAIN (arglist
);
8117 opmode
= insn_data
[icode
].operand
[nop
].mode
;
8118 argmode
= TYPE_MODE (TREE_TYPE (arg
));
8119 if (argmode
!= opmode
)
8120 arg
= build1 (NOP_EXPR
,
8121 (*lang_hooks
.types
.type_for_mode
) (opmode
, 0), arg
);
8122 op
[nop
] = expand_expr (arg
, NULL_RTX
, opmode
, 0);
8123 if (! (*insn_data
[icode
].operand
[nop
].predicate
) (op
[nop
], opmode
))
8124 op
[nop
] = copy_to_mode_reg (opmode
, op
[nop
]);
8130 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0]);
8133 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1]);
8136 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2]);
8139 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2], op
[3]);
8151 sh_expand_unop_v2sf (code
, op0
, op1
)
8155 rtx sel0
= const0_rtx
;
8156 rtx sel1
= const1_rtx
;
8157 rtx (*fn
) PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
)) = gen_unary_sf_op
;
8158 rtx op
= gen_rtx_fmt_e (code
, SFmode
, op1
);
8160 emit_insn ((*fn
) (op0
, op1
, op
, sel0
, sel0
));
8161 emit_insn ((*fn
) (op0
, op1
, op
, sel1
, sel1
));
8165 sh_expand_binop_v2sf (code
, op0
, op1
, op2
)
8169 rtx sel0
= const0_rtx
;
8170 rtx sel1
= const1_rtx
;
8171 rtx (*fn
) PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
))
8173 rtx op
= gen_rtx_fmt_ee (code
, SFmode
, op1
, op2
);
8175 emit_insn ((*fn
) (op0
, op1
, op2
, op
, sel0
, sel0
, sel0
, sel1
));
8176 emit_insn ((*fn
) (op0
, op1
, op2
, op
, sel1
, sel1
, sel1
, sel0
));
8179 /* Return the class of registers for which a mode change from FROM to TO
8182 sh_cannot_change_mode_class (from
, to
, class)
8183 enum machine_mode from
, to
;
8184 enum reg_class
class;
8186 if (GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
8188 if (TARGET_LITTLE_ENDIAN
)
8190 if (GET_MODE_SIZE (to
) < 8 || GET_MODE_SIZE (from
) < 8)
8191 return reg_classes_intersect_p (DF_REGS
, class);
8195 if (GET_MODE_SIZE (from
) < 8)
8196 return reg_classes_intersect_p (DF_HI_REGS
, class);
8203 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
8204 that label is used. */
8207 sh_mark_label (address
, nuses
)
8211 if (GOTOFF_P (address
))
8213 /* Extract the label or symbol. */
8214 address
= XEXP (address
, 0);
8215 if (GET_CODE (address
) == PLUS
)
8216 address
= XEXP (address
, 0);
8217 address
= XVECEXP (address
, 0, 0);
8219 if (GET_CODE (address
) == LABEL_REF
8220 && GET_CODE (XEXP (address
, 0)) == CODE_LABEL
)
8221 LABEL_NUSES (XEXP (address
, 0)) += nuses
;
8224 /* Compute extra cost of moving data between one register class
8227 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
8228 uses this information. Hence, the general register <-> floating point
8229 register information here is not used for SFmode. */
8232 sh_register_move_cost (mode
, srcclass
, dstclass
)
8233 enum machine_mode mode
;
8234 enum reg_class srcclass
, dstclass
;
8236 if (dstclass
== T_REGS
|| dstclass
== PR_REGS
)
8239 if (mode
== SImode
&& ! TARGET_SHMEDIA
&& TARGET_FMOVD
8240 && REGCLASS_HAS_FP_REG (srcclass
)
8241 && REGCLASS_HAS_FP_REG (dstclass
))
8244 if ((REGCLASS_HAS_FP_REG (dstclass
) && srcclass
== MAC_REGS
)
8245 || (dstclass
== MAC_REGS
&& REGCLASS_HAS_FP_REG (srcclass
)))
8248 if ((REGCLASS_HAS_FP_REG (dstclass
)
8249 && REGCLASS_HAS_GENERAL_REG (srcclass
))
8250 || (REGCLASS_HAS_GENERAL_REG (dstclass
)
8251 && REGCLASS_HAS_FP_REG (srcclass
)))
8252 return ((TARGET_SHMEDIA
? 4 : TARGET_FMOVD
? 8 : 12)
8253 * ((GET_MODE_SIZE (mode
) + 7) / 8U));
8255 if ((dstclass
== FPUL_REGS
8256 && REGCLASS_HAS_GENERAL_REG (srcclass
))
8257 || (srcclass
== FPUL_REGS
8258 && REGCLASS_HAS_GENERAL_REG (dstclass
)))
8261 if ((dstclass
== FPUL_REGS
8262 && (srcclass
== PR_REGS
|| srcclass
== MAC_REGS
|| srcclass
== T_REGS
))
8263 || (srcclass
== FPUL_REGS
8264 && (dstclass
== PR_REGS
|| dstclass
== MAC_REGS
)))
8267 if ((srcclass
== TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
8268 || ((dstclass
) == TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
8271 if ((srcclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
8272 || (dstclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
8277 && ! REGCLASS_HAS_GENERAL_REG (srcclass
)
8278 && ! REGCLASS_HAS_GENERAL_REG (dstclass
)))
8279 return 2 * ((GET_MODE_SIZE (mode
) + 7) / 8U);
8281 return 2 * ((GET_MODE_SIZE (mode
) + 3) / 4U);
8284 /* Like register_operand, but take into account that SHMEDIA can use
8285 the constant zero like a general register. */
8287 sh_register_operand (op
, mode
)
8289 enum machine_mode mode
;
8291 if (op
== CONST0_RTX (mode
) && TARGET_SHMEDIA
)
8293 return register_operand (op
, mode
);
8296 static rtx emit_load_ptr
PARAMS ((rtx
, rtx
));
8299 emit_load_ptr (reg
, addr
)
8302 rtx mem
= gen_rtx_MEM (ptr_mode
, addr
);
8304 if (Pmode
!= ptr_mode
)
8305 mem
= gen_rtx_SIGN_EXTEND (Pmode
, mem
);
8306 return emit_move_insn (reg
, mem
);
8310 sh_output_mi_thunk (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
8312 tree thunk_fndecl ATTRIBUTE_UNUSED
;
8313 HOST_WIDE_INT delta
;
8314 HOST_WIDE_INT vcall_offset
;
8317 CUMULATIVE_ARGS cum
;
8318 int structure_value_byref
= 0;
8319 rtx
this, this_value
, sibcall
, insns
, funexp
;
8320 tree funtype
= TREE_TYPE (function
);
8322 = (TARGET_SHMEDIA
? CONST_OK_FOR_J (delta
) : CONST_OK_FOR_I (delta
));
8324 rtx scratch0
, scratch1
, scratch2
;
8326 reload_completed
= 1;
8328 current_function_uses_only_leaf_regs
= 1;
8330 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
8332 /* Find the "this" pointer. We have such a wide range of ABIs for the
8333 SH that it's best to do this completely machine independently.
8334 "this" is passed as first argument, unless a structure return pointer
8335 comes first, in which case "this" comes second. */
8336 INIT_CUMULATIVE_ARGS (cum
, funtype
, NULL_RTX
, 0);
8337 #ifndef PCC_STATIC_STRUCT_RETURN
8338 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
8339 structure_value_byref
= 1;
8340 #endif /* not PCC_STATIC_STRUCT_RETURN */
8341 if (structure_value_byref
&& struct_value_rtx
== 0)
8343 tree ptype
= build_pointer_type (TREE_TYPE (funtype
));
8345 FUNCTION_ARG_ADVANCE (cum
, Pmode
, ptype
, 1);
8347 this = FUNCTION_ARG (cum
, Pmode
, ptr_type_node
, 1);
8349 /* For SHcompact, we only have r0 for a scratch register: r1 is the
8350 static chain pointer (even if you can't have nested virtual functions
8351 right now, someone might implement them sometime), and the rest of the
8352 registers are used for argument passing, are callee-saved, or reserved. */
8353 scratch0
= scratch1
= scratch2
= gen_rtx_REG (Pmode
, 0);
8356 scratch1
= gen_rtx_REG (ptr_mode
, 1);
8357 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
8358 pointing where to return struct values. */
8359 scratch2
= gen_rtx_REG (Pmode
, 3);
8361 else if (TARGET_SHMEDIA
)
8363 scratch1
= gen_rtx_REG (ptr_mode
, 21);
8364 scratch2
= gen_rtx_REG (Pmode
, TR0_REG
);
8367 this_value
= plus_constant (this, delta
);
8369 && (simple_add
|| scratch0
!= scratch1
)
8370 && strict_memory_address_p (ptr_mode
, this_value
))
8372 emit_load_ptr (scratch0
, this_value
);
8378 else if (simple_add
)
8379 emit_move_insn (this, this_value
);
8382 emit_move_insn (scratch1
, GEN_INT (delta
));
8383 emit_insn (gen_add2_insn (this, scratch1
));
8391 emit_load_ptr (scratch0
, this);
8393 offset_addr
= plus_constant (scratch0
, vcall_offset
);
8394 if (strict_memory_address_p (ptr_mode
, offset_addr
))
8396 else if (! TARGET_SH5
)
8398 /* scratch0 != scratch1, and we have indexed loads. Get better
8399 schedule by loading the offset into r1 and using an indexed
8400 load - then the load of r1 can issue before the load from
8401 (this + delta) finishes. */
8402 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
8403 offset_addr
= gen_rtx_PLUS (Pmode
, scratch0
, scratch1
);
8405 else if (TARGET_SHMEDIA
8406 ? CONST_OK_FOR_J (vcall_offset
)
8407 : CONST_OK_FOR_I (vcall_offset
))
8409 emit_insn (gen_add2_insn (scratch0
, GEN_INT (vcall_offset
)));
8410 offset_addr
= scratch0
;
8412 else if (scratch0
!= scratch1
)
8414 emit_move_insn (scratch1
, GEN_INT (vcall_offset
));
8415 emit_insn (gen_add2_insn (scratch0
, scratch1
));
8416 offset_addr
= scratch0
;
8419 abort (); /* FIXME */
8420 emit_load_ptr (scratch0
, offset_addr
);
8422 if (Pmode
!= ptr_mode
)
8423 scratch0
= gen_rtx_TRUNCATE (ptr_mode
, scratch0
);
8424 emit_insn (gen_add2_insn (this, scratch0
));
8427 /* Generate a tail call to the target function. */
8428 if (! TREE_USED (function
))
8430 assemble_external (function
);
8431 TREE_USED (function
) = 1;
8433 funexp
= XEXP (DECL_RTL (function
), 0);
8434 emit_move_insn (scratch2
, funexp
);
8435 funexp
= gen_rtx_MEM (FUNCTION_MODE
, scratch2
);
8436 sibcall
= emit_call_insn (gen_sibcall (funexp
, const0_rtx
, NULL_RTX
));
8437 SIBLING_CALL_P (sibcall
) = 1;
8438 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall
), this);
8441 /* Run just enough of rest_of_compilation to do scheduling and get
8442 the insns emitted. Note that use_thunk calls
8443 assemble_start_function and assemble_end_function. */
8445 insn_locators_initialize ();
8446 insns
= get_insns ();
8448 if (optimize
> 0 && flag_schedule_insns_after_reload
)
8451 find_basic_blocks (insns
, max_reg_num (), rtl_dump_file
);
8452 life_analysis (insns
, rtl_dump_file
, PROP_FINAL
);
8454 split_all_insns (1);
8456 schedule_insns (rtl_dump_file
);
8461 if (optimize
> 0 && flag_delayed_branch
)
8462 dbr_schedule (insns
, rtl_dump_file
);
8463 shorten_branches (insns
);
8464 final_start_function (insns
, file
, 1);
8465 final (insns
, file
, 1, 0);
8466 final_end_function ();
8468 if (optimize
> 0 && flag_schedule_insns_after_reload
)
8470 /* Release all memory allocated by flow. */
8471 free_basic_block_vars (0);
8473 /* Release all memory held by regsets now. */
8474 regset_release_memory ();
8477 reload_completed
= 0;
8482 function_symbol (const char *name
)
8484 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8485 SYMBOL_REF_FLAGS (sym
) = SYMBOL_FLAG_FUNCTION
;