gcc/config/sh/predicates.md

   1 ;; Predicate definitions for Renesas / SuperH SH.
   2 ;; Copyright (C) 2005-2015 Free Software Foundation, Inc.
   3 ;;
   4 ;; This file is part of GCC.
   5 ;;
   6 ;; GCC is free software; you can redistribute it and/or modify
   7 ;; it under the terms of the GNU General Public License as published by
   8 ;; the Free Software Foundation; either version 3, or (at your option)
   9 ;; any later version.
  10 ;;
  11 ;; GCC is distributed in the hope that it will be useful,
  12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ;; GNU General Public License for more details.
  15 ;;
  16 ;; You should have received a copy of the GNU General Public License
  17 ;; along with GCC; see the file COPYING3.  If not see
  18 ;; <http://www.gnu.org/licenses/>.
  19
  20 ;; TODO: Add a comment here.
  21 (define_predicate "trapping_target_operand"
  22   (match_code "if_then_else")
  23 {
  24   rtx cond, mem, res, tar, and_expr;
  25
  26   if (GET_MODE (op) != PDImode)
  27     return 0;
  28   cond = XEXP (op, 0);
  29   mem = XEXP (op, 1);
  30   res = XEXP (op, 2);
  31   if (!MEM_P (mem)
  32       || (GET_CODE (res) != SIGN_EXTEND && GET_CODE (res) != TRUNCATE))
  33     return 0;
  34   tar = XEXP (res, 0);
  35   if (!rtx_equal_p (XEXP (mem, 0), tar)
  36       || GET_MODE (tar) != Pmode)
  37     return 0;
  38   if (GET_CODE (cond) == CONST)
  39     {
  40       cond = XEXP (cond, 0);
  41       if (!satisfies_constraint_Csy (tar))
  42         return 0;
  43       if (GET_CODE (tar) == CONST)
  44         tar = XEXP (tar, 0);
  45     }
  46   else if (!arith_reg_operand (tar, VOIDmode)
  47            && ! satisfies_constraint_Csy (tar))
  48     return 0;
  49   if (GET_CODE (cond) != EQ)
  50     return 0;
  51   and_expr = XEXP (cond, 0);
  52   return (GET_CODE (and_expr) == AND
  53           && rtx_equal_p (XEXP (and_expr, 0), tar)
  54           && CONST_INT_P (XEXP (and_expr, 1))
  55           && CONST_INT_P (XEXP (cond, 1))
  56           && INTVAL (XEXP (and_expr, 1)) == 3
  57           && INTVAL (XEXP (cond, 1)) == 3);
  58 })
  59
  60 ;; A logical operand that can be used in an shmedia and insn.
  61 (define_predicate "and_operand"
  62   (match_code "subreg,reg,const_int")
  63 {
  64   if (logical_operand (op, mode))
  65     return 1;
  66
  67   /* Check mshflo.l / mshflhi.l opportunities.  */
  68   if (TARGET_SHMEDIA
  69       && mode == DImode
  70       && satisfies_constraint_J16 (op))
  71     return 1;
  72
  73   return 0;
  74 })
  75
  76 ;; Like arith_reg_dest, but this predicate is defined with
  77 ;; define_special_predicate, not define_predicate.
  78 (define_special_predicate "any_arith_reg_dest"
  79   (match_code "subreg,reg")
  80 {
  81   return arith_reg_dest (op, mode);
  82 })
  83
  84 ;; Like register_operand, but this predicate is defined with
  85 ;; define_special_predicate, not define_predicate.
  86 (define_special_predicate "any_register_operand"
  87   (match_code "subreg,reg")
  88 {
  89   return register_operand (op, mode);
  90 })
  91
  92 ;; Returns 1 if OP is a valid source operand for an arithmetic insn.
  93 (define_predicate "arith_operand"
  94   (match_code "subreg,reg,const_int,truncate")
  95 {
  96   if (arith_reg_operand (op, mode))
  97     return 1;
  98
  99   if (TARGET_SHMEDIA)
 100     {
 101       /* FIXME: We should be checking whether the CONST_INT fits in a
 102          signed 16-bit here, but this causes reload_cse to crash when
 103          attempting to transform a sequence of two 64-bit sets of the
 104          same register from literal constants into a set and an add,
 105          when the difference is too wide for an add.  */
 106       if (CONST_INT_P (op)
 107           || satisfies_constraint_Css (op))
 108         return 1;
 109       else if (GET_CODE (op) == TRUNCATE
 110                && REG_P (XEXP (op, 0))
 111                && ! system_reg_operand (XEXP (op, 0), VOIDmode)
 112                && (mode == VOIDmode || mode == GET_MODE (op))
 113                && (GET_MODE_SIZE (GET_MODE (op))
 114                    < GET_MODE_SIZE (GET_MODE (XEXP (op, 0))))
 115                && (! FP_REGISTER_P (REGNO (XEXP (op, 0)))
 116                    || GET_MODE_SIZE (GET_MODE (op)) == 4))
 117         return register_operand (XEXP (op, 0), VOIDmode);
 118       else
 119         return 0;
 120     }
 121   else if (satisfies_constraint_I08 (op))
 122     return 1;
 123
 124   return 0;
 125 })
 126
 127 ;; Like above, but for DImode destinations: forbid paradoxical DImode
 128 ;; subregs, because this would lead to missing sign extensions when
 129 ;; truncating from DImode to SImode.
 130 (define_predicate "arith_reg_dest"
 131   (match_code "subreg,reg")
 132 {
 133   if (mode == DImode && GET_CODE (op) == SUBREG
 134       && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
 135       && TARGET_SHMEDIA)
 136     return 0;
 137   return arith_reg_operand (op, mode);
 138 })
 139
 140 ;; Returns 1 if OP is a normal arithmetic register.
 141 (define_predicate "arith_reg_operand"
 142   (match_code "subreg,reg,sign_extend")
 143 {
 144   if (register_operand (op, mode))
 145     {
 146       int regno;
 147
 148       if (REG_P (op))
 149         regno = REGNO (op);
 150       else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
 151         regno = REGNO (SUBREG_REG (op));
 152       else
 153         return 1;
 154
 155       return (regno != T_REG && regno != PR_REG
 156               && ! TARGET_REGISTER_P (regno)
 157               && regno != FPUL_REG && regno != FPSCR_REG
 158               && regno != MACH_REG && regno != MACL_REG);
 159     }
 160   /* Allow a no-op sign extension - compare LOAD_EXTEND_OP.
 161      We allow SImode here, as not using an FP register is just a matter of
 162      proper register allocation.  */
 163   if (TARGET_SHMEDIA
 164       && GET_MODE (op) == DImode && GET_CODE (op) == SIGN_EXTEND
 165       && GET_MODE (XEXP (op, 0)) == SImode
 166       && GET_CODE (XEXP (op, 0)) != SUBREG)
 167     return register_operand (XEXP (op, 0), VOIDmode);
 168 #if 0 /* Can't do this because of PROMOTE_MODE for unsigned vars.  */
 169   if (GET_MODE (op) == SImode && GET_CODE (op) == SIGN_EXTEND
 170       && GET_MODE (XEXP (op, 0)) == HImode
 171       && REG_P (XEXP (op, 0))
 172       && REGNO (XEXP (op, 0)) <= LAST_GENERAL_REG)
 173     return register_operand (XEXP (op, 0), VOIDmode);
 174 #endif
 175   if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
 176       && GET_CODE (op) == SUBREG
 177       && GET_MODE (SUBREG_REG (op)) == DImode
 178       && GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
 179       && GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
 180       && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
 181     return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
 182   return 0;
 183 })
 184
 185 ;; Likewise arith_operand but always permits const_int.
 186 (define_predicate "arith_or_int_operand"
 187   (match_code "subreg,reg,const_int,const_vector")
 188 {
 189   if (arith_operand (op, mode))
 190     return 1;
 191
 192   if (CONST_INT_P (op))
 193     return 1;
 194
 195   return 0;
 196 })
 197
 198 ;; Returns 1 if OP is a valid source operand for a compare insn.
 199 (define_predicate "arith_reg_or_0_operand"
 200   (match_code "subreg,reg,const_int,const_vector")
 201 {
 202   if (arith_reg_operand (op, mode))
 203     return 1;
 204
 205   if (satisfies_constraint_Z (op))
 206     return 1;
 207
 208   return 0;
 209 })
 210
 211 ;; Returns true if OP is either a register or constant 0 or constant 1.
 212 (define_predicate "arith_reg_or_0_or_1_operand"
 213   (match_code "subreg,reg,const_int,const_vector")
 214 {
 215   return arith_reg_or_0_operand (op, mode) || satisfies_constraint_M (op);
 216 })
 217
 218 ;; Returns true if OP is a suitable constant for the minimum value of a
 219 ;; clips.b or clips.w insn.
 220 (define_predicate "clips_min_const_int"
 221   (and (match_code "const_int")
 222        (ior (match_test "INTVAL (op) == -128")
 223             (match_test "INTVAL (op) == -32768"))))
 224
 225 ;; Returns true if OP is a suitable constant for the maximum value of a
 226 ;; clips.b or clips.w insn.
 227 (define_predicate "clips_max_const_int"
 228   (and (match_code "const_int")
 229        (ior (match_test "INTVAL (op) == 127")
 230             (match_test "INTVAL (op) == 32767"))))
 231
 232 ;; Returns true if OP is a suitable constant for the maximum value of a
 233 ;; clipu.b or clipu.w insn.
 234 (define_predicate "clipu_max_const_int"
 235   (and (match_code "const_int")
 236        (ior (match_test "INTVAL (op) == 255")
 237             (match_test "INTVAL (op) == 65535"))))
 238
 239 ;; Returns 1 if OP is a floating point operator with two operands.
 240 (define_predicate "binary_float_operator"
 241   (and (match_code "plus,minus,mult,div")
 242        (match_test "GET_MODE (op) == mode")))
 243
 244 ;; Returns 1 if OP is a logical operator with two operands.
 245 (define_predicate "binary_logical_operator"
 246   (and (match_code "and,ior,xor")
 247        (match_test "GET_MODE (op) == mode")))
 248
 249 ;; Return 1 if OP is an address suitable for a cache manipulation operation.
 250 ;; MODE has the meaning as in address_operand.
 251 (define_special_predicate "cache_address_operand"
 252   (match_code "plus,reg")
 253 {
 254   if (GET_CODE (op) == PLUS)
 255     {
 256       if (!REG_P (XEXP (op, 0)))
 257         return 0;
 258       if (!CONST_INT_P (XEXP (op, 1))
 259           || (INTVAL (XEXP (op, 1)) & 31))
 260         return 0;
 261     }
 262   else if (!REG_P (op))
 263     return 0;
 264   return address_operand (op, mode);
 265 })
 266
 267 ;; Returns 1 if OP is a valid source operand for shmedia cmpgt / cmpgtu.
 268 (define_predicate "cmp_operand"
 269   (match_code "subreg,reg,const_int")
 270 {
 271   if (satisfies_constraint_N (op))
 272     return 1;
 273   if (TARGET_SHMEDIA
 274       && mode != DImode && GET_CODE (op) == SUBREG
 275       && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
 276     return 0;
 277   return arith_reg_operand (op, mode);
 278 })
 279
 280 ;; Returns true if OP is an operand that can be used as the first operand in
 281 ;; the cstoresi4 expander pattern.
 282 (define_predicate "cmpsi_operand"
 283   (match_code "subreg,reg,const_int")
 284 {
 285   if (REG_P (op) && REGNO (op) == T_REG
 286       && GET_MODE (op) == SImode
 287       && TARGET_SH1)
 288     return 1;
 289   return arith_operand (op, mode);
 290 })
 291
 292 ;; Returns true if OP is a comutative float operator.
 293 ;; This predicate is currently unused.
 294 ;;(define_predicate "commutative_float_operator"
 295 ;;  (and (match_code "plus,mult")
 296 ;;       (match_test "GET_MODE (op) == mode")))
 297
 298 ;; Returns true if OP is a equal or not equal operator.
 299 (define_predicate "equality_comparison_operator"
 300   (match_code "eq,ne"))
 301
 302 ;; Returns true if OP is an arithmetic operand that is zero extended during
 303 ;; an operation.
 304 (define_predicate "extend_reg_operand"
 305   (match_code "subreg,reg,truncate")
 306 {
 307   return (GET_CODE (op) == TRUNCATE
 308           ? arith_operand
 309           : arith_reg_operand) (op, mode);
 310 })
 311
 312 ;; Like extend_reg_operand, but also allow a constant 0.
 313 (define_predicate "extend_reg_or_0_operand"
 314   (match_code "subreg,reg,truncate,const_int")
 315 {
 316   return (GET_CODE (op) == TRUNCATE
 317           ? arith_operand
 318           : arith_reg_or_0_operand) (op, mode);
 319 })
 320
 321 ;; Like arith_reg_operand, but this predicate does not accept SIGN_EXTEND.
 322 (define_predicate "ext_dest_operand"
 323   (match_code "subreg,reg")
 324 {
 325   return arith_reg_operand (op, mode);
 326 })
 327
 328 ;; Returns true if OP can be used as a destination register for shmedia floating
 329 ;; point to integer conversions.
 330 (define_predicate "fp_arith_reg_dest"
 331   (match_code "subreg,reg")
 332 {
 333   if (mode == DImode && GET_CODE (op) == SUBREG
 334       && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8)
 335     return 0;
 336   return fp_arith_reg_operand (op, mode);
 337 })
 338
 339 ;; Returns true if OP is a floating point register that can be used in floating
 340 ;; point arithmetic operations.
 341 (define_predicate "fp_arith_reg_operand"
 342   (match_code "subreg,reg")
 343 {
 344   if (register_operand (op, mode))
 345     {
 346       int regno;
 347
 348       if (REG_P (op))
 349         regno = REGNO (op);
 350       else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
 351         regno = REGNO (SUBREG_REG (op));
 352       else
 353         return 1;
 354
 355       return (regno >= FIRST_PSEUDO_REGISTER
 356               || FP_REGISTER_P (regno));
 357     }
 358   return 0;
 359 })
 360
 361 ;; Returns true if OP is the FPSCR.
 362 (define_predicate "fpscr_operand"
 363   (and (match_code "reg")
 364        (match_test "REGNO (op) == FPSCR_REG")))
 365
 366 ;; Returns true if OP is a valid source operand for a FPSCR move insn.
 367 (define_predicate "fpscr_movsrc_operand"
 368   (match_code "reg,subreg,mem")
 369 {
 370   if (arith_reg_operand (op, mode))
 371     return true;
 372
 373   return MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC;
 374 })
 375
 376 ;; Returns true if OP is a valid destination operand for a FPSCR move insn.
 377 (define_predicate "fpscr_movdst_operand"
 378   (match_code "reg,subreg,mem")
 379 {
 380   if (arith_reg_dest (op, mode))
 381     return true;
 382
 383   return MEM_P (op) && GET_CODE (XEXP (op, 0)) == PRE_DEC;
 384 })
 385
 386 ;; Returns true if OP is an operand that is either the fpul hard reg or
 387 ;; a pseudo.  This prevents combine from propagating function arguments
 388 ;; in hard regs into insns that need the operand in fpul.  If it's a pseudo
 389 ;; reload can fix it up.
 390 (define_predicate "fpul_operand"
 391   (match_code "reg")
 392 {
 393   if (TARGET_SHMEDIA)
 394     return fp_arith_reg_operand (op, mode);
 395
 396   return (REG_P (op)
 397           && (REGNO (op) == FPUL_REG || REGNO (op) >= FIRST_PSEUDO_REGISTER)
 398           && GET_MODE (op) == mode);
 399 })
 400
 401 ;; Returns true if OP is a valid fpul input operand for the fsca insn.
 402 ;; The value in fpul is a fixed-point value and its scaling is described
 403 ;; in the fsca insn by a mult:SF.  To allow pre-scaled fixed-point inputs
 404 ;; in fpul we have to permit things like
 405 ;;   (reg:SI)
 406 ;;   (fix:SF (float:SF (reg:SI)))
 407 (define_predicate "fpul_fsca_operand"
 408   (match_code "fix,reg")
 409 {
 410   if (fpul_operand (op, SImode))
 411     return true;
 412   if (GET_CODE (op) == FIX && GET_MODE (op) == SImode
 413       && GET_CODE (XEXP (op, 0)) == FLOAT && GET_MODE (XEXP (op, 0)) == SFmode)
 414     return fpul_fsca_operand (XEXP (XEXP (op, 0), 0),
 415                               GET_MODE (XEXP (XEXP (op, 0), 0)));
 416   return false;
 417 })
 418
 419 ;; Returns true if OP is a valid constant scale factor for the fsca insn.
 420 (define_predicate "fsca_scale_factor"
 421   (and (match_code "const_double")
 422        (match_test "op == sh_fsca_int2sf ()")))
 423
 424 ;; Returns true if OP is an operand that is zero extended during an operation.
 425 (define_predicate "general_extend_operand"
 426   (match_code "subreg,reg,mem,truncate")
 427 {
 428   if (reload_completed && GET_CODE (op) == TRUNCATE)
 429     return arith_operand (op, mode);
 430
 431   if (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))
 432     return general_movsrc_operand (op, mode);
 433
 434   return nonimmediate_operand (op, mode);
 435 })
 436
 437 ;; Returns 1 if OP is a simple register address.
 438 (define_predicate "simple_mem_operand"
 439   (and (match_code "mem")
 440        (match_test "arith_reg_operand (XEXP (op, 0), SImode)")))
 441
 442 ;; Returns 1 if OP is a valid displacement address.
 443 (define_predicate "displacement_mem_operand"
 444   (and (match_code "mem")
 445        (match_test "GET_CODE (XEXP (op, 0)) == PLUS")
 446        (match_test "arith_reg_operand (XEXP (XEXP (op, 0), 0), SImode)")
 447        (match_test "sh_legitimate_index_p (GET_MODE (op),
 448                                            XEXP (XEXP (op, 0), 1),
 449                                            TARGET_SH2A, true)")))
 450
 451 ;; Returns true if OP is a displacement address that can fit into a
 452 ;; 16 bit (non-SH2A) memory load / store insn.
 453 (define_predicate "short_displacement_mem_operand"
 454   (match_test "sh_disp_addr_displacement (op)
 455                <= sh_max_mov_insn_displacement (GET_MODE (op), false)"))
 456
 457 ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn.
 458 (define_predicate "zero_extend_movu_operand"
 459   (and (match_operand 0 "displacement_mem_operand")
 460        (match_test "GET_MODE (op) == QImode || GET_MODE (op) == HImode")))
 461
 462 ;; Returns 1 if the operand can be used in a zero_extend.
 463 (define_predicate "zero_extend_operand"
 464   (ior (and (match_test "TARGET_SHMEDIA")
 465             (match_operand 0 "general_extend_operand"))
 466        (and (match_test "! TARGET_SHMEDIA")
 467             (match_operand 0 "arith_reg_operand"))
 468        (and (match_test "TARGET_SH2A")
 469             (match_operand 0 "zero_extend_movu_operand"))))
 470
 471 ;; Returns 1 if OP can be source of a simple move operation. Same as
 472 ;; general_operand, but a LABEL_REF is valid, PRE_DEC is invalid as
 473 ;; are subregs of system registers.
 474 (define_predicate "general_movsrc_operand"
 475   (match_code "subreg,reg,const_int,const_double,mem,symbol_ref,label_ref,
 476                const,const_vector")
 477 {
 478   if (t_reg_operand (op, mode))
 479     return 0;
 480
 481   if (fpscr_operand (op, mode))
 482     return false;
 483
 484   /* Disallow PC relative QImode loads, since these is no insn to do that
 485      and an imm8 load should be used instead.  */
 486   if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode)
 487     return false;
 488
 489   if (MEM_P (op))
 490     {
 491       rtx inside = XEXP (op, 0);
 492
 493       /* Disallow mems with GBR address here.  They have to go through
 494          separate special patterns.  */
 495       if ((REG_P (inside) && REGNO (inside) == GBR_REG)
 496           || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
 497               && REGNO (XEXP (inside, 0)) == GBR_REG))
 498         return 0;
 499
 500       if (GET_CODE (inside) == CONST)
 501         inside = XEXP (inside, 0);
 502
 503       if (GET_CODE (inside) == LABEL_REF)
 504         return 1;
 505
 506       if (GET_CODE (inside) == PLUS
 507           && GET_CODE (XEXP (inside, 0)) == LABEL_REF
 508           && CONST_INT_P (XEXP (inside, 1)))
 509         return 1;
 510
 511       /* Only post inc allowed.  */
 512       if (GET_CODE (inside) == PRE_DEC)
 513         return 0;
 514     }
 515
 516   if (mode == GET_MODE (op)
 517       && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
 518     {
 519       rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
 520       rtx x = XEXP (mem_rtx, 0);
 521
 522       if (! ALLOW_INDEXED_ADDRESS
 523           && GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
 524         return false;
 525
 526       if (GET_CODE (x) == PLUS)
 527         {
 528           rtx y = XEXP (x, 0);
 529
 530           if (! REG_P (y)
 531               && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))
 532             return false;
 533           y = XEXP (x, 1);
 534           if (! REG_P (y)
 535               && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))
 536               && ! CONST_INT_P (y))
 537             return false;
 538         }
 539
 540       /* LRA will try to satisfy the constraints for the memory displacements
 541          and thus we must not reject invalid displacements in the predicate,
 542          or else LRA will bail out.
 543          FIXME: maybe remove this check completely?  */
 544       if (!lra_in_progress && (mode == QImode || mode == HImode)
 545           && GET_CODE (x) == PLUS
 546           && REG_P (XEXP (x, 0))
 547           && CONST_INT_P (XEXP (x, 1)))
 548         return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
 549
 550       /* Allow reg+reg addressing here without validating the register
 551          numbers.  Usually one of the regs must be R0 or a pseudo reg.
 552          In some cases it can happen that arguments from hard regs are
 553          propagated directly into address expressions.  In this cases reload
 554          will have to fix it up later.  However, allow this only for native
 555          1, 2 or 4 byte addresses.  */
 556       if (can_create_pseudo_p () && GET_CODE (x) == PLUS
 557           && GET_MODE_SIZE (mode) <= 4
 558           && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
 559         return true;
 560
 561       /* 'general_operand' does not allow volatile mems during RTL expansion to
 562          avoid matching arithmetic that operates on mems, it seems.
 563          On SH this leads to redundant sign extensions for QImode or HImode
 564          loads.  Thus we mimic the behavior but allow volatile mems.  */
 565         if (memory_address_addr_space_p (GET_MODE (mem_rtx), x,
 566                                          MEM_ADDR_SPACE (mem_rtx)))
 567           return true;
 568     }
 569
 570   if (TARGET_SHMEDIA
 571       && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
 572       && sh_rep_vec (op, mode))
 573     return 1;
 574   if (TARGET_SHMEDIA && 1
 575       && GET_CODE (op) == SUBREG && GET_MODE (op) == mode
 576       && SUBREG_REG (op) == const0_rtx && subreg_lowpart_p (op))
 577     /* FIXME */ abort (); /* return 1; */
 578
 579   return general_operand (op, mode);
 580 })
 581
 582 ;; Returns 1 if OP is a MEM that does not use displacement addressing.
 583 (define_predicate "movsrc_no_disp_mem_operand"
 584   (match_code "mem")
 585 {
 586   return general_movsrc_operand (op, mode) && satisfies_constraint_Snd (op);
 587 })
 588
 589 ;; Returns 1 if OP can be a destination of a move. Same as
 590 ;; general_operand, but no preinc allowed.
 591 (define_predicate "general_movdst_operand"
 592   (match_code "subreg,reg,mem")
 593 {
 594   if (t_reg_operand (op, mode))
 595     return 0;
 596
 597   if (fpscr_operand (op, mode))
 598     return false;
 599
 600   if (MEM_P (op))
 601     {
 602       rtx inside = XEXP (op, 0);
 603       /* Disallow mems with GBR address here.  They have to go through
 604          separate special patterns.  */
 605       if ((REG_P (inside) && REGNO (inside) == GBR_REG)
 606           || (GET_CODE (inside) == PLUS && REG_P (XEXP (inside, 0))
 607               && REGNO (XEXP (inside, 0)) == GBR_REG))
 608         return 0;
 609     }
 610
 611   /* Only pre dec allowed.  */
 612   if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == POST_INC)
 613     return 0;
 614   if (mode == DImode && TARGET_SHMEDIA && GET_CODE (op) == SUBREG
 615       && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) < 8
 616       && ! (reload_in_progress || reload_completed))
 617     return 0;
 618
 619   if (mode == GET_MODE (op)
 620       && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
 621     {
 622       rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
 623       rtx x = XEXP (mem_rtx, 0);
 624
 625       if (! ALLOW_INDEXED_ADDRESS
 626           && GET_CODE (x) == PLUS && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
 627         return false;
 628
 629       if (GET_CODE (x) == PLUS)
 630         {
 631           rtx y = XEXP (x, 0);
 632
 633           if (! REG_P (y)
 634               && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))
 635             return false;
 636           y = XEXP (x, 1);
 637           if (! REG_P (y)
 638               && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))
 639               && ! CONST_INT_P (y))
 640             return false;
 641         }
 642
 643       /* LRA will try to satisfy the constraints for the memory displacements
 644          and thus we must not reject invalid displacements in the predicate,
 645          or else LRA will bail out.
 646          FIXME: maybe remove this check completely?  */
 647       if (!lra_in_progress && (mode == QImode || mode == HImode)
 648           && GET_CODE (x) == PLUS
 649           && REG_P (XEXP (x, 0))
 650           && CONST_INT_P (XEXP (x, 1)))
 651         return sh_legitimate_index_p (mode, XEXP (x, 1), TARGET_SH2A, false);
 652
 653       /* Allow reg+reg addressing here without validating the register
 654          numbers.  Usually one of the regs must be R0 or a pseudo reg.
 655          In some cases it can happen that arguments from hard regs are
 656          propagated directly into address expressions.  In this cases reload
 657          will have to fix it up later.  However, allow this only for native
 658          1, 2 or 4 byte addresses.  */
 659       if (can_create_pseudo_p () && GET_CODE (x) == PLUS
 660           && GET_MODE_SIZE (mode) <= 4
 661           && REG_P (XEXP (x, 0)) && REG_P (XEXP (x, 1)))
 662         return true;
 663
 664       /* 'general_operand' does not allow volatile mems during RTL expansion to
 665          avoid matching arithmetic that operates on mems, it seems.
 666          On SH this leads to redundant sign extensions for QImode or HImode
 667          stores.  Thus we mimic the behavior but allow volatile mems.  */
 668         if (memory_address_addr_space_p (GET_MODE (mem_rtx), x,
 669                                          MEM_ADDR_SPACE (mem_rtx)))
 670           return true;
 671     }
 672
 673   return general_operand (op, mode);
 674 })
 675
 676 ;; Returns 1 if OP is a POST_INC on stack pointer register.
 677 (define_predicate "sh_no_delay_pop_operand"
 678   (match_code "mem")
 679 {
 680   rtx inside;
 681   inside = XEXP (op, 0);
 682
 683   if (GET_CODE (op) == MEM && GET_MODE (op) == SImode
 684       && GET_CODE (inside) == POST_INC
 685       && GET_CODE (XEXP (inside, 0)) == REG
 686       && REGNO (XEXP (inside, 0)) == SP_REG)
 687     return 1;
 688
 689   return 0;
 690 })
 691
 692 ;; Returns 1 if OP is a MEM that can be source of a simple move operation.
 693 (define_predicate "unaligned_load_operand"
 694   (match_code "mem")
 695 {
 696   rtx inside;
 697
 698   if (!MEM_P (op) || GET_MODE (op) != mode)
 699     return 0;
 700
 701   inside = XEXP (op, 0);
 702
 703   if (GET_CODE (inside) == POST_INC)
 704     inside = XEXP (inside, 0);
 705
 706   if (REG_P (inside))
 707     return 1;
 708
 709   return 0;
 710 })
 711
 712 ;; Returns 1 if OP is a MEM that can be used in "index_disp" combiner
 713 ;; patterns.
 714 (define_predicate "mem_index_disp_operand"
 715   (match_code "mem")
 716 {
 717   rtx plus0_rtx, plus1_rtx, mult_rtx;
 718
 719   plus0_rtx = XEXP (op, 0);
 720   if (GET_CODE (plus0_rtx) != PLUS)
 721     return 0;
 722
 723   plus1_rtx = XEXP (plus0_rtx, 0);
 724   if (GET_CODE (plus1_rtx) != PLUS)
 725     return 0;
 726   if (! arith_reg_operand (XEXP (plus1_rtx, 1), GET_MODE (XEXP (plus1_rtx, 1))))
 727     return 0;
 728
 729   mult_rtx = XEXP (plus1_rtx, 0);
 730   if (GET_CODE (mult_rtx) != MULT)
 731     return 0;
 732   if (! arith_reg_operand (XEXP (mult_rtx, 0), GET_MODE (XEXP (mult_rtx, 0)))
 733       || ! CONST_INT_P (XEXP (mult_rtx, 1)))
 734     return 0;
 735
 736   return exact_log2 (INTVAL (XEXP (mult_rtx, 1))) > 0
 737          && sh_legitimate_index_p (mode, XEXP (plus0_rtx, 1), TARGET_SH2A, true);
 738 })
 739
 740 ;; Returns true if OP is some kind of greater comparision.
 741 (define_predicate "greater_comparison_operator"
 742   (match_code "gt,ge,gtu,geu"))
 743
 744 ;; Returns true if OP is an operand suitable for shmedia reload_inqi and
 745 ;; reload_inhi insns.
 746 (define_predicate "inqhi_operand"
 747   (match_code "truncate")
 748 {
 749   if (GET_CODE (op) != TRUNCATE || mode != GET_MODE (op))
 750     return 0;
 751   op = XEXP (op, 0);
 752   /* Can't use true_regnum here because copy_cost wants to know about
 753      SECONDARY_INPUT_RELOAD_CLASS.  */
 754   return REG_P (op) && FP_REGISTER_P (REGNO (op));
 755 })
 756
 757 ;; Returns true if OP is a general purpose integer register.
 758 ;; This predicate is currently unused.
 759 ;;(define_special_predicate "int_gpr_dest"
 760 ;;  (match_code "subreg,reg")
 761 ;;{
 762 ;;  machine_mode op_mode = GET_MODE (op);
 763 ;;
 764 ;;  if (GET_MODE_CLASS (op_mode) != MODE_INT
 765 ;;      || GET_MODE_SIZE (op_mode) >= UNITS_PER_WORD)
 766 ;;    return 0;
 767 ;;  if (! reload_completed)
 768 ;;    return 0;
 769 ;;  return true_regnum (op) <= LAST_GENERAL_REG;
 770 ;;})
 771
 772 ;; Returns true if OP is some kind of less comparison.
 773 (define_predicate "less_comparison_operator"
 774   (match_code "lt,le,ltu,leu"))
 775
 776 ;; Returns 1 if OP is a valid source operand for a logical operation.
 777 (define_predicate "logical_operand"
 778   (match_code "subreg,reg,const_int")
 779 {
 780   if (TARGET_SHMEDIA
 781       && mode != DImode && GET_CODE (op) == SUBREG
 782       && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
 783     return 0;
 784
 785   if (arith_reg_operand (op, mode))
 786     return 1;
 787
 788   if (TARGET_SHMEDIA)
 789     {
 790       if (satisfies_constraint_I10 (op))
 791         return 1;
 792       else
 793         return 0;
 794     }
 795   else if (satisfies_constraint_K08 (op))
 796     return 1;
 797
 798   return 0;
 799 })
 800
 801 ;; Like logical_operand but allows additional constant values which can be
 802 ;; done with zero extensions.  Used for the second operand of and insns.
 803 (define_predicate "logical_and_operand"
 804   (match_code "subreg,reg,const_int")
 805 {
 806   if (logical_operand (op, mode))
 807     return 1;
 808
 809   if (! TARGET_SHMEDIA
 810       && (satisfies_constraint_Jmb (op) || satisfies_constraint_Jmw (op)))
 811     return 1;
 812
 813   return 0;
 814 })
 815
 816 ;; Returns true if OP is a logical operator.
 817 (define_predicate "logical_operator"
 818   (match_code "and,ior,xor"))
 819
 820 ;; Like arith_reg_operand, but for register source operands of narrow
 821 ;; logical SHMEDIA operations: forbid subregs of DImode / TImode regs.
 822 (define_predicate "logical_reg_operand"
 823   (match_code "subreg,reg")
 824 {
 825   if (TARGET_SHMEDIA
 826       && GET_CODE (op) == SUBREG
 827       && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4
 828       && mode != DImode)
 829     return 0;
 830   return arith_reg_operand (op, mode);
 831 })
 832
 833 ;; Returns true if OP is a valid bit offset value for the shmedia mextr insns.
 834 (define_predicate "mextr_bit_offset"
 835   (match_code "const_int")
 836 {
 837   HOST_WIDE_INT i;
 838
 839   if (!CONST_INT_P (op))
 840     return 0;
 841   i = INTVAL (op);
 842   return i >= 1 * 8 && i <= 7 * 8 && (i & 7) == 0;
 843 })
 844
 845 ;; Returns true if OP is a constant -1, 0 or an zero extended register that
 846 ;; can be used as an operator in the *subsi3_media insn.
 847 (define_predicate "minuend_operand"
 848   (match_code "subreg,reg,truncate,const_int")
 849 {
 850   return op == constm1_rtx || extend_reg_or_0_operand (op, mode);
 851 })
 852
 853 ;; Returns true if OP is a noncommutative floating point operator.
 854 ;; This predicate is currently unused.
 855 ;;(define_predicate "noncommutative_float_operator"
 856 ;;  (and (match_code "minus,div")
 857 ;;       (match_test "GET_MODE (op) == mode")))
 858
 859 ;; UNORDERED is only supported on SHMEDIA.
 860
 861 (define_predicate "sh_float_comparison_operator"
 862   (ior (match_operand 0 "ordered_comparison_operator")
 863        (and (match_test "TARGET_SHMEDIA")
 864             (match_code "unordered"))))
 865
 866 (define_predicate "shmedia_cbranch_comparison_operator"
 867   (ior (match_operand 0 "equality_comparison_operator")
 868        (match_operand 0 "greater_comparison_operator")))
 869
 870 ;; Returns true if OP is a constant vector.
 871 (define_predicate "sh_const_vec"
 872   (match_code "const_vector")
 873 {
 874   int i;
 875
 876   if (GET_CODE (op) != CONST_VECTOR
 877       || (GET_MODE (op) != mode && mode != VOIDmode))
 878     return 0;
 879   i = XVECLEN (op, 0) - 1;
 880   for (; i >= 0; i--)
 881     if (!CONST_INT_P (XVECEXP (op, 0, i)))
 882       return 0;
 883   return 1;
 884 })
 885
 886 ;; Determine if OP is a constant vector matching MODE with only one
 887 ;; element that is not a sign extension.  Two byte-sized elements
 888 ;; count as one.
 889 (define_predicate "sh_1el_vec"
 890   (match_code "const_vector")
 891 {
 892   int unit_size;
 893   int i, last, least, sign_ix;
 894   rtx sign;
 895
 896   if (GET_CODE (op) != CONST_VECTOR
 897       || (GET_MODE (op) != mode && mode != VOIDmode))
 898     return 0;
 899   /* Determine numbers of last and of least significant elements.  */
 900   last = XVECLEN (op, 0) - 1;
 901   least = TARGET_LITTLE_ENDIAN ? 0 : last;
 902   if (!CONST_INT_P (XVECEXP (op, 0, least)))
 903     return 0;
 904   sign_ix = least;
 905   if (GET_MODE_UNIT_SIZE (mode) == 1)
 906     sign_ix = TARGET_LITTLE_ENDIAN ? 1 : last - 1;
 907   if (!CONST_INT_P (XVECEXP (op, 0, sign_ix)))
 908     return 0;
 909   unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op));
 910   sign = (INTVAL (XVECEXP (op, 0, sign_ix)) >> (unit_size * BITS_PER_UNIT - 1)
 911           ? constm1_rtx : const0_rtx);
 912   i = XVECLEN (op, 0) - 1;
 913   do
 914     if (i != least && i != sign_ix && XVECEXP (op, 0, i) != sign)
 915       return 0;
 916   while (--i);
 917   return 1;
 918 })
 919
 920 ;; Like register_operand, but take into account that SHMEDIA can use
 921 ;; the constant zero like a general register.
 922 (define_predicate "sh_register_operand"
 923   (match_code "reg,subreg,const_int,const_double")
 924 {
 925   if (op == CONST0_RTX (mode) && TARGET_SHMEDIA)
 926     return 1;
 927   return register_operand (op, mode);
 928 })
 929
 930 ;; Returns true if OP is a vector which is composed of one element that is
 931 ;; repeated.
 932 (define_predicate "sh_rep_vec"
 933   (match_code "const_vector,parallel")
 934 {
 935   int i;
 936   rtx x, y;
 937
 938   if ((GET_CODE (op) != CONST_VECTOR && GET_CODE (op) != PARALLEL)
 939       || (GET_MODE (op) != mode && mode != VOIDmode))
 940     return 0;
 941   i = XVECLEN (op, 0) - 2;
 942   x = XVECEXP (op, 0, i + 1);
 943   if (GET_MODE_UNIT_SIZE (mode) == 1)
 944     {
 945       y = XVECEXP (op, 0, i);
 946       for (i -= 2; i >= 0; i -= 2)
 947         if (! rtx_equal_p (XVECEXP (op, 0, i + 1), x)
 948             || ! rtx_equal_p (XVECEXP (op, 0, i), y))
 949           return 0;
 950     }
 951   else
 952     for (; i >= 0; i--)
 953       if (XVECEXP (op, 0, i) != x)
 954         return 0;
 955   return 1;
 956 })
 957
 958 ;; Returns true if OP is a valid shift count operand for shift operations.
 959 (define_predicate "shift_count_operand"
 960   (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,
 961                zero_extend,sign_extend")
 962 {
 963   /* Allow T_REG as shift count for dynamic shifts, although it is not
 964      really possible.  It will then be copied to a general purpose reg.  */
 965   if (! TARGET_SHMEDIA)
 966     return const_int_operand (op, mode) || arith_reg_operand (op, mode)
 967            || (TARGET_DYNSHIFT && t_reg_operand (op, mode));
 968
 969   return (CONSTANT_P (op)
 970           ? (CONST_INT_P (op)
 971              ? (unsigned) INTVAL (op) < GET_MODE_BITSIZE (mode)
 972              : nonmemory_operand (op, mode))
 973           : shift_count_reg_operand (op, mode));
 974 })
 975
 976 ;; Returns true if OP is a valid shift count operand in a register which can
 977 ;; be used by shmedia shift insns.
 978 (define_predicate "shift_count_reg_operand"
 979   (match_code "subreg,reg,zero_extend,sign_extend")
 980 {
 981   if ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
 982        || (GET_CODE (op) == SUBREG && SUBREG_BYTE (op) == 0))
 983       && (mode == VOIDmode || mode == GET_MODE (op))
 984       && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
 985       && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT)
 986     {
 987       mode = VOIDmode;
 988       do
 989         op = XEXP (op, 0);
 990       while ((GET_CODE (op) == ZERO_EXTEND || GET_CODE (op) == SIGN_EXTEND
 991               || GET_CODE (op) == TRUNCATE)
 992              && GET_MODE_BITSIZE (GET_MODE (XEXP (op, 0))) >= 6
 993              && GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_INT);
 994
 995     }
 996   return arith_reg_operand (op, mode);
 997 })
 998
 999 ;; Predicates for matching operands that are constant shift
1000 ;; amounts 1, 2, 8, 16.
1001 (define_predicate "p27_shift_count_operand"
1002   (and (match_code "const_int")
1003        (match_test "satisfies_constraint_P27 (op)")))
1004
1005 (define_predicate "not_p27_shift_count_operand"
1006   (and (match_code "const_int")
1007        (match_test "! satisfies_constraint_P27 (op)")))
1008
1009 ;; For right shifts the constant 1 is a special case because the shlr insn
1010 ;; clobbers the T_REG and is handled by the T_REG clobbering version of the
1011 ;; insn, which is also used for non-P27 shift sequences.
1012 (define_predicate "p27_rshift_count_operand"
1013   (and (match_code "const_int")
1014        (match_test "satisfies_constraint_P27 (op)")
1015        (match_test "! satisfies_constraint_M (op)")))
1016
1017 (define_predicate "not_p27_rshift_count_operand"
1018   (and (match_code "const_int")
1019        (ior (match_test "! satisfies_constraint_P27 (op)")
1020             (match_test "satisfies_constraint_M (op)"))))
1021
1022 ;; Returns true if OP is some kind of a shift operator.
1023 (define_predicate "shift_operator"
1024   (match_code "ashift,ashiftrt,lshiftrt"))
1025
1026 ;; Returns true if OP is a symbol reference.
1027 (define_predicate "symbol_ref_operand"
1028   (match_code "symbol_ref"))
1029
1030 ;; Same as target_reg_operand, except that label_refs and symbol_refs
1031 ;; are accepted before reload.
1032 (define_special_predicate "target_operand"
1033   (match_code "subreg,reg,label_ref,symbol_ref,const,unspec")
1034 {
1035   if (mode != VOIDmode && mode != Pmode)
1036     return 0;
1037
1038   if ((GET_MODE (op) == Pmode || GET_MODE (op) == VOIDmode)
1039       && satisfies_constraint_Csy (op))
1040     return ! reload_completed;
1041
1042   return target_reg_operand (op, mode);
1043 })
1044
1045 ;; A predicate that accepts pseudos and branch target registers.
1046 (define_special_predicate "target_reg_operand"
1047   (match_code "subreg,reg")
1048 {
1049   if (mode == VOIDmode
1050      ? GET_MODE (op) != Pmode && GET_MODE (op) != PDImode
1051      : mode != GET_MODE (op))
1052     return 0;
1053
1054   if (GET_CODE (op) == SUBREG)
1055     op = XEXP (op, 0);
1056
1057   if (!REG_P (op))
1058     return 0;
1059
1060   /* We must protect ourselves from matching pseudos that are virtual
1061      register, because they will eventually be replaced with hardware
1062      registers that aren't branch-target registers.  */
1063   if (REGNO (op) > LAST_VIRTUAL_REGISTER
1064       || TARGET_REGISTER_P (REGNO (op)))
1065     return 1;
1066
1067   return 0;
1068 })
1069
1070 ;; Returns true if OP is a valid operand for the shmedia mperm.w insn.
1071 (define_special_predicate "trunc_hi_operand"
1072   (match_code "subreg,reg,truncate")
1073 {
1074   machine_mode op_mode = GET_MODE (op);
1075
1076   if (op_mode != SImode && op_mode != DImode
1077       && op_mode != V4HImode && op_mode != V2SImode)
1078     return 0;
1079   return extend_reg_operand (op, mode);
1080 })
1081
1082 ;; Returns true if OP is an address suitable for an unaligned access
1083 ;; instruction.
1084 (define_special_predicate "ua_address_operand"
1085   (match_code "subreg,reg,plus")
1086 {
1087   if (GET_CODE (op) == PLUS
1088       && (! satisfies_constraint_I06 (XEXP (op, 1))))
1089     return 0;
1090   return address_operand (op, QImode);
1091 })
1092
1093 ;; Returns true if OP is a valid offset for an unaligned memory address.
1094 (define_predicate "ua_offset"
1095   (match_code "const_int")
1096 {
1097   return satisfies_constraint_I06 (op);
1098 })
1099
1100 ;; Returns true if OP is a floating point operator with one operand.
1101 (define_predicate "unary_float_operator"
1102   (and (match_code "abs,neg,sqrt")
1103        (match_test "GET_MODE (op) == mode")))
1104
1105 ;; Return 1 if OP is a valid source operand for xor.
1106 (define_predicate "xor_operand"
1107   (match_code "subreg,reg,const_int")
1108 {
1109   if (CONST_INT_P (op))
1110     return (TARGET_SHMEDIA
1111             ? (satisfies_constraint_I06 (op)
1112                || (!can_create_pseudo_p () && INTVAL (op) == 0xff))
1113             : satisfies_constraint_K08 (op));
1114   if (TARGET_SHMEDIA
1115       && mode != DImode && GET_CODE (op) == SUBREG
1116       && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op))) > 4)
1117     return 0;
1118   return arith_reg_operand (op, mode);
1119 })
1120
1121 (define_predicate "bitwise_memory_operand"
1122   (match_code "mem")
1123 {
1124   if (MEM_P (op))
1125     {
1126       if (REG_P (XEXP (op, 0)))
1127         return 1;
1128
1129       if (GET_CODE (XEXP (op, 0)) == PLUS
1130           && REG_P (XEXP (XEXP (op, 0), 0))
1131           && satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1)))
1132         return 1;
1133     }
1134   return 0;
1135 })
1136
1137 ;; The atomic_* operand predicates are used for the atomic patterns.
1138 ;; Depending on the particular pattern some operands can be immediate
1139 ;; values.  Using these predicates avoids the usage of 'force_reg' in the
1140 ;; expanders.
1141 (define_predicate "atomic_arith_operand"
1142   (ior (match_code "subreg,reg")
1143        (and (match_test "satisfies_constraint_I08 (op)")
1144             (match_test "mode != QImode")
1145             (match_test "mode != HImode")
1146             (match_test "TARGET_SH4A"))))
1147
1148 (define_predicate "atomic_logical_operand"
1149   (ior (match_code "subreg,reg")
1150        (and (match_test "satisfies_constraint_K08 (op)")
1151             (match_test "mode != QImode")
1152             (match_test "mode != HImode")
1153             (match_test "TARGET_SH4A"))))
1154
1155 ;; A predicate describing the T bit register in any form.
1156 (define_predicate "t_reg_operand"
1157   (match_code "reg,subreg,sign_extend,zero_extend")
1158 {
1159   switch (GET_CODE (op))
1160     {
1161       case REG:
1162         return REGNO (op) == T_REG;
1163
1164       case SUBREG:
1165         return REG_P (SUBREG_REG (op)) && REGNO (SUBREG_REG (op)) == T_REG;
1166
1167       case ZERO_EXTEND:
1168       case SIGN_EXTEND:
1169         if (REG_P (XEXP (op, 0)) && REGNO (XEXP (op, 0)) == T_REG)
1170           return true;
1171         return GET_CODE (XEXP (op, 0)) == SUBREG
1172                && REG_P (SUBREG_REG (XEXP (op, 0)))
1173                && REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG;
1174
1175       default:
1176         return 0;
1177     }
1178 })
1179
1180 ;; A predicate describing a negated T bit register.
1181 (define_predicate "negt_reg_operand"
1182   (match_code "subreg,xor")
1183 {
1184   switch (GET_CODE (op))
1185     {
1186       case XOR:
1187         return t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))
1188                && satisfies_constraint_M (XEXP (op, 1));
1189
1190       case SUBREG:
1191         return negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)));
1192
1193       default:
1194         return 0;
1195     }
1196 })
1197
1198 ;; A predicate that returns true if OP is a valid construct around the T bit
1199 ;; that can be used as an operand for conditional branches.
1200 (define_predicate "cbranch_treg_value"
1201   (and (match_code "eq,ne,reg,subreg,xor,sign_extend,zero_extend")
1202        (match_test "sh_eval_treg_value (op) >= 0")))
1203
1204 ;; Returns true if OP is arith_reg_operand or t_reg_operand.
1205 (define_predicate "arith_reg_or_t_reg_operand"
1206   (ior (match_operand 0 "arith_reg_operand")
1207        (match_operand 0 "t_reg_operand")))
1208
1209 ;; A predicate describing the negated value of the T bit register shifted
1210 ;; left by 31.
1211 (define_predicate "negt_reg_shl31_operand"
1212   (match_code "plus,minus,if_then_else")
1213 {
1214   /* (minus:SI (const_int -2147483648)  ;; 0xffffffff80000000
1215                (ashift:SI (match_operand:SI 1 "t_reg_operand")
1216                           (const_int 31)))
1217   */
1218   if (GET_CODE (op) == MINUS && satisfies_constraint_Jhb (XEXP (op, 0))
1219       && GET_CODE (XEXP (op, 1)) == ASHIFT
1220       && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode)
1221       && CONST_INT_P (XEXP (XEXP (op, 1), 1))
1222       && INTVAL (XEXP (XEXP (op, 1), 1)) == 31)
1223     return true;
1224
1225   /* (plus:SI (ashift:SI (match_operand:SI 1 "t_reg_operand")
1226                          (const_int 31))
1227               (const_int -2147483648))  ;; 0xffffffff80000000
1228   */
1229   if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1))
1230       && GET_CODE (XEXP (op, 0)) == ASHIFT
1231       && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode)
1232       && CONST_INT_P (XEXP (XEXP (op, 0), 1))
1233       && INTVAL (XEXP (XEXP (op, 0), 1)) == 31)
1234     return true;
1235
1236   /* (plus:SI (mult:SI (match_operand:SI 1 "t_reg_operand")
1237                        (const_int -2147483648))  ;; 0xffffffff80000000
1238               (const_int -2147483648))
1239   */
1240   if (GET_CODE (op) == PLUS && satisfies_constraint_Jhb (XEXP (op, 1))
1241       && GET_CODE (XEXP (op, 0)) == MULT
1242       && t_reg_operand (XEXP (XEXP (op, 0), 0), SImode)
1243       && satisfies_constraint_Jhb (XEXP (XEXP (op, 0), 1)))
1244     return true;
1245
1246   /* (minus:SI (const_int -2147483648)  ;; 0xffffffff80000000
1247                (mult:SI (match_operand:SI 1 "t_reg_operand")
1248                         (const_int -2147483648)))
1249   */
1250   if (GET_CODE (op) == MINUS
1251       && satisfies_constraint_Jhb (XEXP (op, 0))
1252       && GET_CODE (XEXP (op, 1)) == MULT
1253       && t_reg_operand (XEXP (XEXP (op, 1), 0), SImode)
1254       && satisfies_constraint_Jhb (XEXP (XEXP (op, 1), 1)))
1255     return true;
1256
1257   /*  (if_then_else:SI (match_operand:SI 1 "t_reg_operand")
1258                        (const_int 0)
1259                        (const_int -2147483648))  ;; 0xffffffff80000000
1260   */
1261   if (GET_CODE (op) == IF_THEN_ELSE && t_reg_operand (XEXP (op, 0), SImode)
1262       && satisfies_constraint_Z (XEXP (op, 1))
1263       && satisfies_constraint_Jhb (XEXP (op, 2)))
1264     return true;
1265
1266   return false;
1267 })
1268
1269 ;; A predicate that determines whether a given constant is a valid
1270 ;; displacement for a GBR load/store of the specified mode.
1271 (define_predicate "gbr_displacement"
1272   (match_code "const_int")
1273 {
1274   const int mode_sz = GET_MODE_SIZE (mode);
1275   const int move_sz = mode_sz > GET_MODE_SIZE (SImode)
1276                                 ? GET_MODE_SIZE (SImode)
1277                                 : mode_sz;
1278   int max_disp = 255 * move_sz;
1279   if (mode_sz > move_sz)
1280     max_disp -= mode_sz - move_sz;
1281
1282   return INTVAL (op) >= 0 && INTVAL (op) <= max_disp;
1283 })
1284
1285 ;; A predicate that determines whether OP is a valid GBR addressing mode
1286 ;; memory reference.
1287 (define_predicate "gbr_address_mem"
1288   (match_code "mem")
1289 {
1290   rtx addr = XEXP (op, 0);
1291
1292   if (REG_P (addr) && REGNO (addr) == GBR_REG)
1293     return true;
1294   if (GET_CODE (addr) == PLUS
1295       && REG_P (XEXP (addr, 0)) && REGNO (XEXP (addr, 0)) == GBR_REG
1296       && gbr_displacement (XEXP (addr, 1), mode))
1297     return true;
1298
1299   return false;
1300 })