gcc/config/sh/lib1funcs.asm

   1 /* Copyright (C) 1994 Free Software Foundation, Inc.
   2
   3 This file is free software; you can redistribute it and/or modify it
   4 under the terms of the GNU General Public License as published by the
   5 Free Software Foundation; either version 2, or (at your option) any
   6 later version.
   7
   8 In addition to the permissions in the GNU General Public License, the
   9 Free Software Foundation gives you unlimited permission to link the
  10 compiled version of this file with other programs, and to distribute
  11 those programs without any restriction coming from the use of this
  12 file.  (The General Public License restrictions do apply in other
  13 respects; for example, they cover modification of the file, and
  14 distribution when not linked into another program.)
  15
  16 This file is distributed in the hope that it will be useful, but
  17 WITHOUT ANY WARRANTY; without even the implied warranty of
  18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19 General Public License for more details.
  20
  21 You should have received a copy of the GNU General Public License
  22 along with this program; see the file COPYING.  If not, write to
  23 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  24
  25 /* As a special exception, if you link this library with other files,
  26    some of which are compiled with GCC, to produce an executable,
  27    this library does not by itself cause the resulting executable
  28    to be covered by the GNU General Public License.
  29    This exception does not however invalidate any other reasons why
  30    the executable file might be covered by the GNU General Public License.  */
  31
  32
  33 !! libgcc1 routines for the Hitachi SH cpu.
  34 !! Contributed by Steve Chamberlain.
  35 !! sac@cygnus.com
  36
  37 !! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines
  38 !! recoded in assembly by Toshiyasu Morita
  39 !! tm@netcom.com
  40
  41 #ifdef L_ashiftrt
  42         .global ___ashiftrt_r4_0
  43         .global ___ashiftrt_r4_1
  44         .global ___ashiftrt_r4_2
  45         .global ___ashiftrt_r4_3
  46         .global ___ashiftrt_r4_4
  47         .global ___ashiftrt_r4_5
  48         .global ___ashiftrt_r4_6
  49         .global ___ashiftrt_r4_7
  50         .global ___ashiftrt_r4_8
  51         .global ___ashiftrt_r4_9
  52         .global ___ashiftrt_r4_10
  53         .global ___ashiftrt_r4_11
  54         .global ___ashiftrt_r4_12
  55         .global ___ashiftrt_r4_13
  56         .global ___ashiftrt_r4_14
  57         .global ___ashiftrt_r4_15
  58         .global ___ashiftrt_r4_16
  59         .global ___ashiftrt_r4_17
  60         .global ___ashiftrt_r4_18
  61         .global ___ashiftrt_r4_19
  62         .global ___ashiftrt_r4_20
  63         .global ___ashiftrt_r4_21
  64         .global ___ashiftrt_r4_22
  65         .global ___ashiftrt_r4_23
  66         .global ___ashiftrt_r4_24
  67         .global ___ashiftrt_r4_25
  68         .global ___ashiftrt_r4_26
  69         .global ___ashiftrt_r4_27
  70         .global ___ashiftrt_r4_28
  71         .global ___ashiftrt_r4_29
  72         .global ___ashiftrt_r4_30
  73         .global ___ashiftrt_r4_31
  74         .global ___ashiftrt_r4_32
  75
  76         .align  1
  77 ___ashiftrt_r4_32:
  78 ___ashiftrt_r4_31:
  79         rotcl   r4
  80         rts
  81         subc    r4,r4
  82
  83 ___ashiftrt_r4_30:
  84         shar    r4
  85 ___ashiftrt_r4_29:
  86         shar    r4
  87 ___ashiftrt_r4_28:
  88         shar    r4
  89 ___ashiftrt_r4_27:
  90         shar    r4
  91 ___ashiftrt_r4_26:
  92         shar    r4
  93 ___ashiftrt_r4_25:
  94         shar    r4
  95 ___ashiftrt_r4_24:
  96         shlr16  r4
  97         shlr8   r4
  98         rts
  99         exts.b  r4,r4
 100
 101 ___ashiftrt_r4_23:
 102         shar    r4
 103 ___ashiftrt_r4_22:
 104         shar    r4
 105 ___ashiftrt_r4_21:
 106         shar    r4
 107 ___ashiftrt_r4_20:
 108         shar    r4
 109 ___ashiftrt_r4_19:
 110         shar    r4
 111 ___ashiftrt_r4_18:
 112         shar    r4
 113 ___ashiftrt_r4_17:
 114         shar    r4
 115 ___ashiftrt_r4_16:
 116         shlr16  r4
 117         rts
 118         exts.w  r4,r4
 119
 120 ___ashiftrt_r4_15:
 121         shar    r4
 122 ___ashiftrt_r4_14:
 123         shar    r4
 124 ___ashiftrt_r4_13:
 125         shar    r4
 126 ___ashiftrt_r4_12:
 127         shar    r4
 128 ___ashiftrt_r4_11:
 129         shar    r4
 130 ___ashiftrt_r4_10:
 131         shar    r4
 132 ___ashiftrt_r4_9:
 133         shar    r4
 134 ___ashiftrt_r4_8:
 135         shar    r4
 136 ___ashiftrt_r4_7:
 137         shar    r4
 138 ___ashiftrt_r4_6:
 139         shar    r4
 140 ___ashiftrt_r4_5:
 141         shar    r4
 142 ___ashiftrt_r4_4:
 143         shar    r4
 144 ___ashiftrt_r4_3:
 145         shar    r4
 146 ___ashiftrt_r4_2:
 147         shar    r4
 148 ___ashiftrt_r4_1:
 149         rts
 150         shar    r4
 151
 152 ___ashiftrt_r4_0:
 153         rts
 154         nop
 155 #endif
 156
 157 #ifdef L_ashiftrt_n
 158
 159 !
 160 ! ___ashrsi3
 161 !
 162 ! Entry:
 163 !
 164 ! r4: Value to shift
 165 ! r5: Shifts
 166 !
 167 ! Exit:
 168 !
 169 ! r0: Result
 170 !
 171 ! Destroys:
 172 !
 173 ! r1
 174 !
 175
 176         .global ___ashrsi3
 177         .align  2
 178 ___ashrsi3:
 179         mov     #31,r0
 180         cmp/hi  r0,r5
 181         bt      L_ashrsi3_31
 182         mov     r5,r1                   ! Remove later
 183         mova    L_ashrsi3_table,r0
 184         shll    r1                      ! Remove later
 185         mov.w   @(r0,r1),r1             ! Change to mov.b @(r0,r5),r1
 186         add     r1,r0
 187         jmp     @r0
 188         mov     r4,r0
 189
 190 L_ashrsi3_table:
 191         .word           L_ashrsi3_0-L_ashrsi3_table     ! Change to .bytes
 192         .word           L_ashrsi3_1-L_ashrsi3_table
 193         .word           L_ashrsi3_2-L_ashrsi3_table
 194         .word           L_ashrsi3_3-L_ashrsi3_table
 195         .word           L_ashrsi3_4-L_ashrsi3_table
 196         .word           L_ashrsi3_5-L_ashrsi3_table
 197         .word           L_ashrsi3_6-L_ashrsi3_table
 198         .word           L_ashrsi3_7-L_ashrsi3_table
 199         .word           L_ashrsi3_8-L_ashrsi3_table
 200         .word           L_ashrsi3_9-L_ashrsi3_table
 201         .word           L_ashrsi3_10-L_ashrsi3_table
 202         .word           L_ashrsi3_11-L_ashrsi3_table
 203         .word           L_ashrsi3_12-L_ashrsi3_table
 204         .word           L_ashrsi3_13-L_ashrsi3_table
 205         .word           L_ashrsi3_14-L_ashrsi3_table
 206         .word           L_ashrsi3_15-L_ashrsi3_table
 207         .word           L_ashrsi3_16-L_ashrsi3_table
 208         .word           L_ashrsi3_17-L_ashrsi3_table
 209         .word           L_ashrsi3_18-L_ashrsi3_table
 210         .word           L_ashrsi3_19-L_ashrsi3_table
 211         .word           L_ashrsi3_20-L_ashrsi3_table
 212         .word           L_ashrsi3_21-L_ashrsi3_table
 213         .word           L_ashrsi3_22-L_ashrsi3_table
 214         .word           L_ashrsi3_23-L_ashrsi3_table
 215         .word           L_ashrsi3_24-L_ashrsi3_table
 216         .word           L_ashrsi3_25-L_ashrsi3_table
 217         .word           L_ashrsi3_26-L_ashrsi3_table
 218         .word           L_ashrsi3_27-L_ashrsi3_table
 219         .word           L_ashrsi3_28-L_ashrsi3_table
 220         .word           L_ashrsi3_29-L_ashrsi3_table
 221         .word           L_ashrsi3_30-L_ashrsi3_table
 222         .word           L_ashrsi3_31-L_ashrsi3_table
 223
 224 L_ashrsi3_31:
 225         rotcl   r0
 226         rts
 227         subc    r0,r0
 228
 229 L_ashrsi3_30:
 230         shar    r0
 231 L_ashrsi3_29:
 232         shar    r0
 233 L_ashrsi3_28:
 234         shar    r0
 235 L_ashrsi3_27:
 236         shar    r0
 237 L_ashrsi3_26:
 238         shar    r0
 239 L_ashrsi3_25:
 240         shar    r0
 241 L_ashrsi3_24:
 242         shlr16  r0
 243         shlr8   r0
 244         rts
 245         exts.b  r0,r0
 246
 247 L_ashrsi3_23:
 248         shar    r0
 249 L_ashrsi3_22:
 250         shar    r0
 251 L_ashrsi3_21:
 252         shar    r0
 253 L_ashrsi3_20:
 254         shar    r0
 255 L_ashrsi3_19:
 256         shar    r0
 257 L_ashrsi3_18:
 258         shar    r0
 259 L_ashrsi3_17:
 260         shar    r0
 261 L_ashrsi3_16:
 262         shlr16  r0
 263         rts
 264         exts.w  r0,r0
 265
 266 L_ashrsi3_15:
 267         shar    r0
 268 L_ashrsi3_14:
 269         shar    r0
 270 L_ashrsi3_13:
 271         shar    r0
 272 L_ashrsi3_12:
 273         shar    r0
 274 L_ashrsi3_11:
 275         shar    r0
 276 L_ashrsi3_10:
 277         shar    r0
 278 L_ashrsi3_9:
 279         shar    r0
 280 L_ashrsi3_8:
 281         shar    r0
 282 L_ashrsi3_7:
 283         shar    r0
 284 L_ashrsi3_6:
 285         shar    r0
 286 L_ashrsi3_5:
 287         shar    r0
 288 L_ashrsi3_4:
 289         shar    r0
 290 L_ashrsi3_3:
 291         shar    r0
 292 L_ashrsi3_2:
 293         shar    r0
 294 L_ashrsi3_1:
 295         rts
 296         shar    r0
 297
 298 L_ashrsi3_0:
 299         rts
 300         nop
 301
 302 #endif
 303
 304 #ifdef L_ashiftlt
 305
 306 !
 307 ! ___ashlsi3
 308 !
 309 ! Entry:
 310 !
 311 ! r4: Value to shift
 312 ! r5: Shifts
 313 !
 314 ! Exit:
 315 !
 316 ! r0: Result
 317 !
 318 ! Destroys:
 319 !
 320 ! r1
 321 !
 322         .global ___ashlsi3
 323         .align  2
 324 ___ashlsi3:
 325         mov     #31,r0
 326         cmp/hi  r0,r5
 327         bt      L_ashlsi3_32
 328         mov     r5,r1                   ! Remove later
 329         mova    L_ashlsi3_table,r0
 330         shll    r1                      ! Remove later
 331         mov.w   @(r0,r1),r1             ! Change to mov.b @(r0,r5),r1
 332         add     r1,r0
 333         jmp     @r0
 334         mov     r4,r0
 335
 336 L_ashlsi3_table:
 337         .word           L_ashlsi3_0-L_ashlsi3_table     ! Change to .bytes
 338         .word           L_ashlsi3_1-L_ashlsi3_table
 339         .word           L_ashlsi3_2-L_ashlsi3_table
 340         .word           L_ashlsi3_3-L_ashlsi3_table
 341         .word           L_ashlsi3_4-L_ashlsi3_table
 342         .word           L_ashlsi3_5-L_ashlsi3_table
 343         .word           L_ashlsi3_6-L_ashlsi3_table
 344         .word           L_ashlsi3_7-L_ashlsi3_table
 345         .word           L_ashlsi3_8-L_ashlsi3_table
 346         .word           L_ashlsi3_9-L_ashlsi3_table
 347         .word           L_ashlsi3_10-L_ashlsi3_table
 348         .word           L_ashlsi3_11-L_ashlsi3_table
 349         .word           L_ashlsi3_12-L_ashlsi3_table
 350         .word           L_ashlsi3_13-L_ashlsi3_table
 351         .word           L_ashlsi3_14-L_ashlsi3_table
 352         .word           L_ashlsi3_15-L_ashlsi3_table
 353         .word           L_ashlsi3_16-L_ashlsi3_table
 354         .word           L_ashlsi3_17-L_ashlsi3_table
 355         .word           L_ashlsi3_18-L_ashlsi3_table
 356         .word           L_ashlsi3_19-L_ashlsi3_table
 357         .word           L_ashlsi3_20-L_ashlsi3_table
 358         .word           L_ashlsi3_21-L_ashlsi3_table
 359         .word           L_ashlsi3_22-L_ashlsi3_table
 360         .word           L_ashlsi3_23-L_ashlsi3_table
 361         .word           L_ashlsi3_24-L_ashlsi3_table
 362         .word           L_ashlsi3_25-L_ashlsi3_table
 363         .word           L_ashlsi3_26-L_ashlsi3_table
 364         .word           L_ashlsi3_27-L_ashlsi3_table
 365         .word           L_ashlsi3_28-L_ashlsi3_table
 366         .word           L_ashlsi3_29-L_ashlsi3_table
 367         .word           L_ashlsi3_30-L_ashlsi3_table
 368         .word           L_ashlsi3_31-L_ashlsi3_table
 369
 370 L_ashlsi3_6:
 371         shll2   r0
 372 L_ashlsi3_4:
 373         shll2   r0
 374 L_ashlsi3_2:
 375         rts
 376         shll2   r0
 377
 378 L_ashlsi3_7:
 379         shll2   r0
 380 L_ashlsi3_5:
 381         shll2   r0
 382 L_ashlsi3_3:
 383         shll2   r0
 384 L_ashlsi3_1:
 385         rts
 386         shll    r0
 387
 388 L_ashlsi3_14:
 389         shll2   r0
 390 L_ashlsi3_12:
 391         shll2   r0
 392 L_ashlsi3_10:
 393         shll2   r0
 394 L_ashlsi3_8:
 395         rts
 396         shll8   r0
 397
 398 L_ashlsi3_15:
 399         shll2   r0
 400 L_ashlsi3_13:
 401         shll2   r0
 402 L_ashlsi3_11:
 403         shll2   r0
 404 L_ashlsi3_9:
 405         shll8   r0
 406         rts
 407         shll    r0
 408
 409 L_ashlsi3_22:
 410         shll2   r0
 411 L_ashlsi3_20:
 412         shll2   r0
 413 L_ashlsi3_18:
 414         shll2   r0
 415 L_ashlsi3_16:
 416         rts
 417         shll16  r0
 418
 419 L_ashlsi3_23:
 420         shll2   r0
 421 L_ashlsi3_21:
 422         shll2   r0
 423 L_ashlsi3_19:
 424         shll2   r0
 425 L_ashlsi3_17:
 426         shll16  r0
 427         rts
 428         shll    r0
 429
 430 L_ashlsi3_30:
 431         shll2   r0
 432 L_ashlsi3_28:
 433         shll2   r0
 434 L_ashlsi3_26:
 435         shll2   r0
 436 L_ashlsi3_24:
 437         shll16  r0
 438         rts
 439         shll8   r0
 440
 441 L_ashlsi3_31:
 442         shll2   r0
 443 L_ashlsi3_29:
 444         shll2   r0
 445 L_ashlsi3_27:
 446         shll2   r0
 447 L_ashlsi3_25:
 448         shll16  r0
 449         shll8   r0
 450         rts
 451         shll    r0
 452
 453 L_ashlsi3_32:
 454         rts
 455         mov     #0,r0
 456
 457 L_ashlsi3_0:
 458         rts
 459         nop
 460
 461 #endif
 462
 463 #ifdef L_lshiftrt
 464
 465 !
 466 ! ___lshrsi3
 467 !
 468 ! Entry:
 469 !
 470 ! r4: Value to shift
 471 ! r5: Shifts
 472 !
 473 ! Exit:
 474 !
 475 ! r0: Result
 476 !
 477 ! Destroys:
 478 !
 479 ! r1
 480 !
 481         .global ___lshrsi3
 482         .align  2
 483 ___lshrsi3:
 484         mov     #31,r0
 485         cmp/hi  r0,r5
 486         bt      L_lshrsi3_32
 487         mov     r5,r1                   ! Remove later
 488         mova    L_lshrsi3_table,r0
 489         shll    r1                      ! Remove later
 490         mov.w   @(r0,r1),r1             ! Change to mov.b @(r0,r5),r1
 491         add     r1,r0
 492         jmp     @r0
 493         mov     r4,r0
 494
 495 L_lshrsi3_table:
 496         .word           L_lshrsi3_0-L_lshrsi3_table     ! Change to .bytes
 497         .word           L_lshrsi3_1-L_lshrsi3_table
 498         .word           L_lshrsi3_2-L_lshrsi3_table
 499         .word           L_lshrsi3_3-L_lshrsi3_table
 500         .word           L_lshrsi3_4-L_lshrsi3_table
 501         .word           L_lshrsi3_5-L_lshrsi3_table
 502         .word           L_lshrsi3_6-L_lshrsi3_table
 503         .word           L_lshrsi3_7-L_lshrsi3_table
 504         .word           L_lshrsi3_8-L_lshrsi3_table
 505         .word           L_lshrsi3_9-L_lshrsi3_table
 506         .word           L_lshrsi3_10-L_lshrsi3_table
 507         .word           L_lshrsi3_11-L_lshrsi3_table
 508         .word           L_lshrsi3_12-L_lshrsi3_table
 509         .word           L_lshrsi3_13-L_lshrsi3_table
 510         .word           L_lshrsi3_14-L_lshrsi3_table
 511         .word           L_lshrsi3_15-L_lshrsi3_table
 512         .word           L_lshrsi3_16-L_lshrsi3_table
 513         .word           L_lshrsi3_17-L_lshrsi3_table
 514         .word           L_lshrsi3_18-L_lshrsi3_table
 515         .word           L_lshrsi3_19-L_lshrsi3_table
 516         .word           L_lshrsi3_20-L_lshrsi3_table
 517         .word           L_lshrsi3_21-L_lshrsi3_table
 518         .word           L_lshrsi3_22-L_lshrsi3_table
 519         .word           L_lshrsi3_23-L_lshrsi3_table
 520         .word           L_lshrsi3_24-L_lshrsi3_table
 521         .word           L_lshrsi3_25-L_lshrsi3_table
 522         .word           L_lshrsi3_26-L_lshrsi3_table
 523         .word           L_lshrsi3_27-L_lshrsi3_table
 524         .word           L_lshrsi3_28-L_lshrsi3_table
 525         .word           L_lshrsi3_29-L_lshrsi3_table
 526         .word           L_lshrsi3_30-L_lshrsi3_table
 527         .word           L_lshrsi3_31-L_lshrsi3_table
 528
 529 L_lshrsi3_6:
 530         shlr2   r0
 531 L_lshrsi3_4:
 532         shlr2   r0
 533 L_lshrsi3_2:
 534         rts
 535         shlr2   r0
 536
 537 L_lshrsi3_7:
 538         shlr2   r0
 539 L_lshrsi3_5:
 540         shlr2   r0
 541 L_lshrsi3_3:
 542         shlr2   r0
 543 L_lshrsi3_1:
 544         rts
 545         shlr    r0
 546
 547 L_lshrsi3_14:
 548         shlr2   r0
 549 L_lshrsi3_12:
 550         shlr2   r0
 551 L_lshrsi3_10:
 552         shlr2   r0
 553 L_lshrsi3_8:
 554         rts
 555         shlr8   r0
 556
 557 L_lshrsi3_15:
 558         shlr2   r0
 559 L_lshrsi3_13:
 560         shlr2   r0
 561 L_lshrsi3_11:
 562         shlr2   r0
 563 L_lshrsi3_9:
 564         shlr8   r0
 565         rts
 566         shlr    r0
 567
 568 L_lshrsi3_22:
 569         shlr2   r0
 570 L_lshrsi3_20:
 571         shlr2   r0
 572 L_lshrsi3_18:
 573         shlr2   r0
 574 L_lshrsi3_16:
 575         rts
 576         shlr16  r0
 577
 578 L_lshrsi3_23:
 579         shlr2   r0
 580 L_lshrsi3_21:
 581         shlr2   r0
 582 L_lshrsi3_19:
 583         shlr2   r0
 584 L_lshrsi3_17:
 585         shlr16  r0
 586         rts
 587         shlr    r0
 588
 589 L_lshrsi3_30:
 590         shlr2   r0
 591 L_lshrsi3_28:
 592         shlr2   r0
 593 L_lshrsi3_26:
 594         shlr2   r0
 595 L_lshrsi3_24:
 596         shlr16  r0
 597         rts
 598         shlr8   r0
 599
 600 L_lshrsi3_31:
 601         shlr2   r0
 602 L_lshrsi3_29:
 603         shlr2   r0
 604 L_lshrsi3_27:
 605         shlr2   r0
 606 L_lshrsi3_25:
 607         shlr16  r0
 608         shlr8   r0
 609         rts
 610         shlr    r0
 611
 612 L_lshrsi3_32:
 613         rts
 614         mov     #0,r0
 615
 616 L_lshrsi3_0:
 617         rts
 618         nop
 619
 620 #endif
 621
 622 #ifdef L_movstr
 623         .text
 624 ! done all the large groups, do the remainder
 625
 626 ! jump to movstr+
 627 done:
 628         add     #64,r5
 629         mova    ___movstrSI0,r0
 630         shll2   r6
 631         add     r6,r0
 632         jmp     @r0
 633         add     #64,r4
 634         .align  4
 635         .global ___movstrSI64
 636 ___movstrSI64:
 637         mov.l   @(60,r5),r0
 638         mov.l   r0,@(60,r4)
 639         .global ___movstrSI60
 640 ___movstrSI60:
 641         mov.l   @(56,r5),r0
 642         mov.l   r0,@(56,r4)
 643         .global ___movstrSI56
 644 ___movstrSI56:
 645         mov.l   @(52,r5),r0
 646         mov.l   r0,@(52,r4)
 647         .global ___movstrSI52
 648 ___movstrSI52:
 649         mov.l   @(48,r5),r0
 650         mov.l   r0,@(48,r4)
 651         .global ___movstrSI48
 652 ___movstrSI48:
 653         mov.l   @(44,r5),r0
 654         mov.l   r0,@(44,r4)
 655         .global ___movstrSI44
 656 ___movstrSI44:
 657         mov.l   @(40,r5),r0
 658         mov.l   r0,@(40,r4)
 659         .global ___movstrSI40
 660 ___movstrSI40:
 661         mov.l   @(36,r5),r0
 662         mov.l   r0,@(36,r4)
 663         .global ___movstrSI36
 664 ___movstrSI36:
 665         mov.l   @(32,r5),r0
 666         mov.l   r0,@(32,r4)
 667         .global ___movstrSI32
 668 ___movstrSI32:
 669         mov.l   @(28,r5),r0
 670         mov.l   r0,@(28,r4)
 671         .global ___movstrSI28
 672 ___movstrSI28:
 673         mov.l   @(24,r5),r0
 674         mov.l   r0,@(24,r4)
 675         .global ___movstrSI24
 676 ___movstrSI24:
 677         mov.l   @(20,r5),r0
 678         mov.l   r0,@(20,r4)
 679         .global ___movstrSI20
 680 ___movstrSI20:
 681         mov.l   @(16,r5),r0
 682         mov.l   r0,@(16,r4)
 683         .global ___movstrSI16
 684 ___movstrSI16:
 685         mov.l   @(12,r5),r0
 686         mov.l   r0,@(12,r4)
 687         .global ___movstrSI12
 688 ___movstrSI12:
 689         mov.l   @(8,r5),r0
 690         mov.l   r0,@(8,r4)
 691         .global ___movstrSI8
 692 ___movstrSI8:
 693         mov.l   @(4,r5),r0
 694         mov.l   r0,@(4,r4)
 695         .global ___movstrSI4
 696 ___movstrSI4:
 697         mov.l   @(0,r5),r0
 698         mov.l   r0,@(0,r4)
 699 ___movstrSI0:
 700         rts
 701         or      r0,r0,r0
 702
 703         .align  4
 704
 705         .global ___movstr
 706 ___movstr:
 707         mov.l   @(60,r5),r0
 708         mov.l   r0,@(60,r4)
 709
 710         mov.l   @(56,r5),r0
 711         mov.l   r0,@(56,r4)
 712
 713         mov.l   @(52,r5),r0
 714         mov.l   r0,@(52,r4)
 715
 716         mov.l   @(48,r5),r0
 717         mov.l   r0,@(48,r4)
 718
 719         mov.l   @(44,r5),r0
 720         mov.l   r0,@(44,r4)
 721
 722         mov.l   @(40,r5),r0
 723         mov.l   r0,@(40,r4)
 724
 725         mov.l   @(36,r5),r0
 726         mov.l   r0,@(36,r4)
 727
 728         mov.l   @(32,r5),r0
 729         mov.l   r0,@(32,r4)
 730
 731         mov.l   @(28,r5),r0
 732         mov.l   r0,@(28,r4)
 733
 734         mov.l   @(24,r5),r0
 735         mov.l   r0,@(24,r4)
 736
 737         mov.l   @(20,r5),r0
 738         mov.l   r0,@(20,r4)
 739
 740         mov.l   @(16,r5),r0
 741         mov.l   r0,@(16,r4)
 742
 743         mov.l   @(12,r5),r0
 744         mov.l   r0,@(12,r4)
 745
 746         mov.l   @(8,r5),r0
 747         mov.l   r0,@(8,r4)
 748
 749         mov.l   @(4,r5),r0
 750         mov.l   r0,@(4,r4)
 751
 752         mov.l   @(0,r5),r0
 753         mov.l   r0,@(0,r4)
 754
 755         add     #-16,r6
 756         cmp/pl  r6
 757         bf      done
 758
 759         add     #64,r5
 760         bra     ___movstr
 761         add     #64,r4
 762 #endif
 763
 764 #ifdef L_mulsi3
 765
 766
 767         .global ___mulsi3
 768
 769 ! r4 =       aabb
 770 ! r5 =       ccdd
 771 ! r0 = aabb*ccdd  via partial products
 772 !
 773 ! if aa == 0 and cc = 0
 774 ! r0 = bb*dd
 775 !
 776 ! else
 777 ! aa = bb*dd + (aa*dd*65536) + (cc*bb*65536)
 778 !
 779
 780 ___mulsi3:
 781         mulu    r4,r5           ! multiply the lsws  macl=bb*dd
 782         mov     r5,r3           ! r3 = ccdd
 783         swap.w  r4,r2           ! r2 = bbaa
 784         xtrct   r2,r3           ! r3 = aacc
 785         tst     r3,r3           ! msws zero ?
 786         bf      hiset
 787         rts                     ! yes - then weve got the answer
 788         sts     macl,r0
 789
 790 hiset:  sts     macl,r0         ! r0 = bb*dd
 791         mulu    r2,r5           | brewing macl = aa*dd
 792         sts     macl,r1
 793         mulu    r3,r4           | brewing macl = cc*bb
 794         sts     macl,r2
 795         add     r1,r2
 796         shll16  r2
 797         rts
 798         add     r2,r0
 799
 800
 801 #endif
 802 #ifdef L_sdivsi3
 803         .title "SH DIVIDE"
 804 !! 4 byte integer Divide code for the Hitachi SH
 805 !!
 806 !! Steve Chamberlain
 807 !! sac@cygnus.com
 808 !!
 809 !!
 810
 811 !! args in r4 and r5, result in r0 clobber r1,r2,r3
 812
 813         .global ___sdivsi3
 814 ___sdivsi3:
 815         mov     r4,r1
 816         mov     r5,r0
 817
 818         tst     r0,r0
 819         bt      div0
 820         mov     #0,r2
 821         div0s   r2,r1
 822         subc    r3,r3
 823         subc    r2,r1
 824         div0s   r0,r3
 825         rotcl   r1
 826         div1    r0,r3
 827         rotcl   r1
 828         div1    r0,r3
 829         rotcl   r1
 830         div1    r0,r3
 831         rotcl   r1
 832         div1    r0,r3
 833         rotcl   r1
 834         div1    r0,r3
 835         rotcl   r1
 836         div1    r0,r3
 837         rotcl   r1
 838         div1    r0,r3
 839         rotcl   r1
 840         div1    r0,r3
 841         rotcl   r1
 842         div1    r0,r3
 843         rotcl   r1
 844         div1    r0,r3
 845         rotcl   r1
 846         div1    r0,r3
 847         rotcl   r1
 848         div1    r0,r3
 849         rotcl   r1
 850         div1    r0,r3
 851         rotcl   r1
 852         div1    r0,r3
 853         rotcl   r1
 854         div1    r0,r3
 855         rotcl   r1
 856         div1    r0,r3
 857         rotcl   r1
 858         div1    r0,r3
 859         rotcl   r1
 860         div1    r0,r3
 861         rotcl   r1
 862         div1    r0,r3
 863         rotcl   r1
 864         div1    r0,r3
 865         rotcl   r1
 866         div1    r0,r3
 867         rotcl   r1
 868         div1    r0,r3
 869         rotcl   r1
 870         div1    r0,r3
 871         rotcl   r1
 872         div1    r0,r3
 873         rotcl   r1
 874         div1    r0,r3
 875         rotcl   r1
 876         div1    r0,r3
 877         rotcl   r1
 878         div1    r0,r3
 879         rotcl   r1
 880         div1    r0,r3
 881         rotcl   r1
 882         div1    r0,r3
 883         rotcl   r1
 884         div1    r0,r3
 885         rotcl   r1
 886         div1    r0,r3
 887         rotcl   r1
 888         div1    r0,r3
 889         rotcl   r1
 890         addc    r2,r1
 891         rts
 892         mov     r1,r0
 893
 894
 895 div0:   rts
 896         mov     #0,r0
 897
 898 #endif
 899 #ifdef L_udivsi3
 900
 901         .title "SH DIVIDE"
 902 !! 4 byte integer Divide code for the Hitachi SH
 903 !!
 904 !! Steve Chamberlain
 905 !! sac@cygnus.com
 906 !!
 907 !!
 908
 909 !! args in r4 and r5, result in r0, clobbers r4, pr, and t bit
 910         .global ___udivsi3
 911
 912 ___udivsi3:
 913 longway:
 914         mov     #0,r0
 915         div0u
 916         ! get one bit from the msb of the numerator into the T
 917         ! bit and divide it by whats in r5.  Put the answer bit
 918         ! into the T bit so it can come out again at the bottom
 919
 920         rotcl   r4 ; div1 r5,r0
 921         rotcl   r4 ; div1 r5,r0
 922         rotcl   r4 ; div1 r5,r0
 923         rotcl   r4 ; div1 r5,r0
 924         rotcl   r4 ; div1 r5,r0
 925         rotcl   r4 ; div1 r5,r0
 926         rotcl   r4 ; div1 r5,r0
 927         rotcl   r4 ; div1 r5,r0
 928
 929         rotcl   r4 ; div1 r5,r0
 930         rotcl   r4 ; div1 r5,r0
 931         rotcl   r4 ; div1 r5,r0
 932         rotcl   r4 ; div1 r5,r0
 933         rotcl   r4 ; div1 r5,r0
 934         rotcl   r4 ; div1 r5,r0
 935         rotcl   r4 ; div1 r5,r0
 936         rotcl   r4 ; div1 r5,r0
 937 shortway:
 938         rotcl   r4 ; div1 r5,r0
 939         rotcl   r4 ; div1 r5,r0
 940         rotcl   r4 ; div1 r5,r0
 941         rotcl   r4 ; div1 r5,r0
 942         rotcl   r4 ; div1 r5,r0
 943         rotcl   r4 ; div1 r5,r0
 944         rotcl   r4 ; div1 r5,r0
 945         rotcl   r4 ; div1 r5,r0
 946
 947 vshortway:
 948         rotcl   r4 ; div1 r5,r0
 949         rotcl   r4 ; div1 r5,r0
 950         rotcl   r4 ; div1 r5,r0
 951         rotcl   r4 ; div1 r5,r0
 952         rotcl   r4 ; div1 r5,r0
 953         rotcl   r4 ; div1 r5,r0
 954         rotcl   r4 ; div1 r5,r0
 955         rotcl   r4 ; div1 r5,r0
 956         rotcl   r4
 957 ret:    rts
 958         mov     r4,r0
 959
 960 #endif