1 ;;- Machine description for GNU compiler -- S/
390 / zSeries version.
2 ;; Copyright (C)
1999,
2000,
2001 Free Software Foundation, Inc.
3 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 ;; Ulrich Weigand (uweigand@de.ibm.com).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version
2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
20 ;; Boston, MA
02111-
1307, USA.
23 ;; Special constraints for s/
390 machine description:
25 ;; a -- Any address register from
1 to
15.
26 ;; d -- Any register from
0 to
15.
27 ;; I -- An
8-bit constant (
0.
.255).
28 ;; J -- A
12-bit constant (
0.
.4095).
29 ;; K -- A
16-bit constant (-
32768.
.32767).
30 ;; Q -- A memory reference without index-register.
31 ;; S -- Valid operand for the LARL instruction.
33 ;; Special formats used for outputting
390 instructions.
35 ;; %b -- Print a constant byte integer. xy
36 ;; %h -- Print a signed
16-bit. wxyz
37 ;; %N -- Print next register (second word of a DImode reg) or next word.
38 ;; %M -- Print next register (second word of a TImode reg) or next word.
39 ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)).
40 ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)).
42 ;; We have a special constraint for pattern matching.
44 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
46 ;; r_or_s_operand -- Matches a register or a valid S operand in a RS, SI
47 ;; or SS type instruction or a register
50 ;; Insn type. Used to default other attribute values.
53 ; Insn are devide in two classes:
54 ; mem: Use of base and/or index register for address generation
55 ; reg: Use of second and third register not for address generation
58 (define_attr "atype" "mem,reg" (const_string "reg"))
61 ; Insn may take
1,
2,
3 or many cycles
62 ; For the scheduling it does not matter, if a instruction has
63 ; a issue_delay from
4 or more cycles, since the address dependency
64 ; between two insns needs at least
4 cycles.
67 (define_attr "cycle" "
1,
2,
3,n" (const_string "
1"))
70 ; There are three classes of insns:
71 ; set: instruction setting a (potential) address relevant register
72 ; xset: instruction setting no address relevant register
73 ; la: instruction setting a (potential) address relevant register,
74 ; but behave 'better' on the pipeline
77 (define_attr "type" "set,xset,la" (const_string "xset"))
80 ; Set operations changing a target register, which could be used for
81 ; address generation. Adjust cost will check, if realy applicable.
84 (define_function_unit "memory"
1 0
85 (and (eq_attr "type" "set")
86 (eq_attr "cycle" "
1"))
87 5 1 [(eq_attr "atype" "mem")] )
89 (define_function_unit "memory"
1 0
90 (and (eq_attr "type" "set")
91 (eq_attr "cycle" "
2"))
5 2)
93 (define_function_unit "memory"
1 0
94 (and (eq_attr "type" "set")
95 (eq_attr "cycle" "
3"))
5 3)
97 (define_function_unit "memory"
1 0
98 (and (eq_attr "type" "set")
99 (eq_attr "cycle" "n"))
5 4)
101 (define_function_unit "memory"
1 0
102 (eq_attr "type" "la")
2 1)
105 ; xset insns, which don't set any valid address register.
106 ; Only the issue delay matters.
109 (define_function_unit "memory"
1 0
110 (and (eq_attr "type" "xset")
111 (eq_attr "cycle" "
1"))
1 1)
113 (define_function_unit "memory"
1 0
114 (and (eq_attr "type" "xset")
115 (eq_attr "cycle" "
2"))
1 2)
117 (define_function_unit "memory"
1 0
118 (and (eq_attr "type" "xset")
119 (eq_attr "cycle" "
3"))
1 3)
121 (define_function_unit "memory"
1 0
122 (and (eq_attr "type" "xset")
123 (eq_attr "cycle" "n"))
1 4)
125 ; Operand type. Used to default length attribute values
127 (define_attr "op_type"
128 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
133 (define_attr "length" ""
134 (cond [ (eq_attr "op_type" "E") (const_int
2)
135 (eq_attr "op_type" "RR") (const_int
2)
136 (eq_attr "op_type" "RX") (const_int
4)
137 (eq_attr "op_type" "RI") (const_int
4)
138 (eq_attr "op_type" "RRE") (const_int
4)
139 (eq_attr "op_type" "RS") (const_int
4)
140 (eq_attr "op_type" "RSI") (const_int
4)
141 (eq_attr "op_type" "RX") (const_int
4)
142 (eq_attr "op_type" "S") (const_int
4)
143 (eq_attr "op_type" "SI") (const_int
4)
144 (eq_attr "op_type" "SS") (const_int
6)
145 (eq_attr "op_type" "SSE") (const_int
6)
146 (eq_attr "op_type" "RXE") (const_int
6)
147 (eq_attr "op_type" "RSE") (const_int
6)
148 (eq_attr "op_type" "RIL") (const_int
6)]
151 ;; Define attributes for
`asm' insns.
153 (define_asm_attributes [(set_attr "type" "xset")
154 (set_attr "op_type" "NN")])
160 ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR)
161 ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA)
162 ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM)
163 ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM)
164 ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML)
167 ; CCZ1 -> CCA/CCU/CCS/CCT
170 ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST
171 ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT
175 ;;- Compare instructions.
178 (define_expand "cmpdi"
180 (compare:CC (match_operand:DI 0 "register_operand" "")
181 (match_operand:DI 1 "general_operand" "")))]
185 s390_compare_op0 = operands[0];
186 s390_compare_op1 = operands[1];
190 (define_expand "cmpsi"
192 (compare:CC (match_operand:SI 0 "register_operand" "")
193 (match_operand:SI 1 "general_operand" "")))]
197 s390_compare_op0 = operands[0];
198 s390_compare_op1 = operands[1];
202 ;(define_expand "cmphi"
204 ; (compare:CC (match_operand:HI 0 "register_operand" "")
205 ; (match_operand:HI 1 "general_operand" "")))]
209 ; s390_compare_op0 = operands[0];
210 ; s390_compare_op1 = operands[1];
214 ;(define_expand "cmpqi"
216 ; (compare:CC (match_operand:QI 0 "register_operand" "")
217 ; (match_operand:QI 1 "general_operand" "")))]
221 ; s390_compare_op0 = operands[0];
222 ; s390_compare_op1 = operands[1];
226 (define_expand "cmpdf"
228 (compare:CC (match_operand:DF 0 "register_operand" "")
229 (match_operand:DF 1 "general_operand" "")))]
233 s390_compare_op0 = operands[0];
234 s390_compare_op1 = operands[1];
238 (define_expand "cmpsf"
240 (compare:CC (match_operand:SF 0 "register_operand" "")
241 (match_operand:SF 1 "general_operand" "")))]
245 s390_compare_op0 = operands[0];
246 s390_compare_op1 = operands[1];
253 (define_insn "*cmpdi_tm2"
255 (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d")
256 (match_operand:DI 1 "const1_operand" "")
257 (match_operand:DI 2 "immediate_operand" "I"))
259 "s390_match_ccmode(insn, CCTmode) &&
260 INTVAL(operands[2]) >= 0 && INTVAL(operands[2]) < 64"
263 if (INTVAL (operands[2]) > 47)
265 operands[1] = GEN_INT (1 << (63 - INTVAL(operands[2])));
266 return \"tmll\\t%0,%x1\";
268 else if (INTVAL (operands[2]) > 31)
270 operands[1] = GEN_INT (1 << (47 - INTVAL(operands[2])));
271 return \"tmlh\\t%0,%x1\";
273 else if (INTVAL (operands[2]) > 15)
275 operands[1] = GEN_INT (1 << (31 - INTVAL(operands[2])));
276 return \"tmhl\\t%0,%x1\";
278 operands[1] = GEN_INT (1 << (15 - INTVAL(operands[2])));
279 return \"tmhh\\t%0,%x1\";
281 [(set_attr "op_type" "RX")
282 (set_attr "type" "xset")])
285 (define_insn "*cmpdi_tm"
287 (compare (and:DI (match_operand:DI 0 "register_operand" "%d")
288 (match_operand:DI 1 "tmxx_operand" "Lm"))
290 "s390_match_ccmode(insn, CCTmode)"
293 unsigned HOST_WIDEST_INT i;
294 if (GET_CODE (operands[1]) == MEM &&
295 GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF &&
296 CONSTANT_POOL_ADDRESS_P (XEXP (operands[1],0)))
298 operands[1] = get_pool_constant (XEXP (operands[1],0));
301 i = (unsigned HOST_WIDEST_INT) INTVAL (operands[1]);
303 if (i >= 0x1000000000000ULL)
305 operands[1] = GEN_INT (i >> 48);
306 return \"tmhh\\t%0,%x1\";
308 else if (i > 0x100000000ULL)
310 operands[1] = GEN_INT (i >> 32);
311 return \"tmhl\\t%0,%x1\";
313 else if (i >= 0x10000ULL)
315 operands[1] = GEN_INT (i >> 16);
316 return \"tmlh\\t%0,%x1\";
319 return \"tmll\\t%0,%x1\";
321 [(set_attr "op_type" "RX")
322 (set_attr "type" "xset")])
327 (compare (match_operand:DI 0 "register_operand" "d")
328 (match_operand:DI 1 "const0_operand" "")))
329 (set (match_operand:DI 2 "register_operand" "=d")
331 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
333 [(set_attr "op_type" "RRE")
334 (set_attr "type" "set")])
336 (define_insn "*cmpdi_ccs_0_64"
338 (compare (match_operand:DI 0 "register_operand" "d")
339 (match_operand:DI 1 "const0_operand" "")))]
340 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
342 [(set_attr "op_type" "RRE")
343 (set_attr "type" "set")])
345 (define_insn "*cmpdi_ccs_0_31"
347 (compare (match_operand:DI 0 "register_operand" "d")
348 (match_operand:DI 1 "const0_operand" "")))]
349 "s390_match_ccmode(insn, CCSmode)"
351 [(set_attr "op_type" "RS")
352 (set_attr "type" "set")])
354 (define_insn "*cmpdi_ccs"
356 (compare (match_operand:DI 0 "register_operand" "d,d,d")
357 (match_operand:DI 1 "general_operand" "d,K,m")))]
358 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
363 [(set_attr "op_type" "RRE,RI,RXE")
364 (set_attr "atype" "reg,reg,mem")])
366 (define_insn "*cmpdi_ccu"
368 (compare (match_operand:DI 0 "register_operand" "d,d")
369 (match_operand:DI 1 "general_operand" "d,m")))]
370 "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT"
374 [(set_attr "op_type" "RRE,RXE")
375 (set_attr "atype" "reg,mem")])
377 (define_insn "*cmpdi_ccu_mem"
379 (compare (match_operand:DI 0 "s_operand" "oQ")
380 (match_operand:DI 1 "s_operand" "oQ")))]
381 "s390_match_ccmode(insn, CCUmode)"
382 "clc\\t%O0(8,%R0),%1"
383 [(set_attr "op_type" "SS")
384 (set_attr "atype" "mem")])
388 (define_insn "*cmpsi_cct"
390 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "%d")
391 (match_operand:SI 1 "const1_operand" "")
392 (match_operand:SI 2 "immediate_operand" "I"))
394 "s390_match_ccmode(insn, CCTmode) &&
395 INTVAL(operands[2]) >= 0 && INTVAL(operands[2]) < 32"
398 if (INTVAL (operands[2]) > 15)
400 operands[1] = GEN_INT (1 << (31 - INTVAL(operands[2])));
401 return \"tml\\t%0,%x1\";
403 operands[1] = GEN_INT (1 << (15 - INTVAL(operands[2])));
404 return \"tmh\\t%0,%x1\";
406 [(set_attr "op_type" "RI")
407 (set_attr "type" "xset")])
409 (define_insn "*cmpsi_tm"
411 (compare (and:SI (match_operand:SI 0 "register_operand" "%d")
412 (match_operand:SI 1 "tmxx_operand" "Lm"))
414 "s390_match_ccmode(insn, CCTmode)"
418 if (GET_CODE (operands[1]) == MEM &&
419 GET_CODE (XEXP (operands[1],0)) == SYMBOL_REF &&
420 CONSTANT_POOL_ADDRESS_P (XEXP (operands[1],0)))
422 operands[1] = get_pool_constant (XEXP (operands[1],0));
425 i = (unsigned long) INTVAL (operands[1]);
428 operands[1] = GEN_INT (i / 0x10000);
429 return \"tmh\\t%0,%x1\";
431 return \"tml\\t%0,%x1\";
433 [(set_attr "op_type" "RX")
434 (set_attr "type" "xset")])
439 (compare (match_operand:SI 0 "register_operand" "d")
440 (match_operand:SI 1 "const0_operand" "")))
441 (set (match_operand:SI 2 "register_operand" "=d")
443 "s390_match_ccmode(insn, CCSmode)"
445 [(set_attr "op_type" "RR")
446 (set_attr "type" "set")])
448 (define_insn "*icm15"
450 (compare (match_operand:SI 0 "s_operand" "Qo")
451 (match_operand:SI 1 "const0_operand" "")))
452 (set (match_operand:SI 2 "register_operand" "=d")
454 "s390_match_ccmode(insn, CCSmode)"
456 [(set_attr "op_type" "RS")
457 (set_attr "atype" "mem")
458 (set_attr "type" "set")])
460 (define_insn "*icm15_cconly"
462 (compare (match_operand:SI 0 "s_operand" "Qo")
463 (match_operand:SI 1 "const0_operand" "")))
464 (clobber (match_scratch:SI 2 "=d"))]
465 "s390_match_ccmode(insn, CCSmode)"
467 [(set_attr "op_type" "RS")
468 (set_attr "atype" "mem")
469 (set_attr "type" "set")])
471 (define_insn "*cmpsi_ccs_0"
473 (compare (match_operand:SI 0 "register_operand" "d")
474 (match_operand:SI 1 "const0_operand" "")))]
475 "s390_match_ccmode(insn, CCSmode)"
477 [(set_attr "op_type" "RR")
478 (set_attr "type" "set")])
480 (define_insn "*cmpsidi_ccs"
482 (compare (match_operand:SI 0 "register_operand" "d")
483 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
484 "s390_match_ccmode(insn, CCSmode)"
486 [(set_attr "op_type" "RR")
487 (set_attr "atype" "mem")
488 (set_attr "type" "xset")])
490 (define_insn "*cmpsi_ccs"
492 (compare (match_operand:SI 0 "register_operand" "d,d,d")
493 (match_operand:SI 1 "general_operand" "d,K,m")))]
494 "s390_match_ccmode(insn, CCSmode)"
499 [(set_attr "op_type" "RR,RI,RX")
500 (set_attr "atype" "reg,reg,mem")
501 (set_attr "type" "xset,xset,xset")])
503 (define_insn "*cmpsi_ccu"
505 (compare (match_operand:SI 0 "register_operand" "d,d")
506 (match_operand:SI 1 "general_operand" "d,m")))]
507 "s390_match_ccmode(insn, CCUmode)"
511 [(set_attr "op_type" "RR,RX")
512 (set_attr "atype" "reg,mem")])
514 (define_insn "*cmpsi_ccu_mem"
516 (compare (match_operand:SI 0 "s_operand" "oQ")
517 (match_operand:SI 1 "s_operand" "oQ")))]
518 "s390_match_ccmode(insn, CCUmode)"
519 "clc\\t%O0(4,%R0),%1"
520 [(set_attr "op_type" "SS")
521 (set_attr "atype" "mem")
522 (set_attr "type" "xset")])
529 (compare (match_operand:HI 0 "s_operand" "Qo")
530 (match_operand:HI 1 "const0_operand" "")))
531 (set (match_operand:HI 2 "register_operand" "=d")
533 "s390_match_ccmode(insn, CCSmode)"
535 [(set_attr "op_type" "RS")
536 (set_attr "atype" "mem")
537 (set_attr "type" "set")])
539 (define_insn "*cmphi_cct_0"
541 (compare (match_operand:HI 0 "register_operand" "d")
542 (match_operand:HI 1 "const0_operand" "")))]
543 "s390_match_ccmode(insn, CCTmode)"
545 [(set_attr "op_type" "RX")
546 (set_attr "type" "xset")])
548 (define_insn "*cmphi_ccs_0"
550 (compare (match_operand:HI 0 "s_operand" "Qo")
551 (match_operand:HI 1 "const0_operand" "")))
552 (clobber (match_scratch:HI 2 "=d"))]
553 "s390_match_ccmode(insn, CCSmode)"
555 [(set_attr "op_type" "RS")
556 (set_attr "atype" "mem")
557 (set_attr "type" "set")])
559 (define_insn "*cmphi_ccu"
561 (compare (match_operand:HI 0 "register_operand" "d")
562 (match_operand:HI 1 "s_operand" "Qo")))]
563 "s390_match_ccmode(insn, CCUmode)"
565 [(set_attr "op_type" "RS")
566 (set_attr "atype" "mem")
567 (set_attr "type" "xset")])
569 (define_insn "*cmphi_ccu_mem"
571 (compare (match_operand:HI 0 "s_operand" "oQ")
572 (match_operand:HI 1 "s_operand" "oQ")))]
573 "s390_match_ccmode(insn, CCUmode)"
574 "clc\\t%O0(2,%R0),%1"
575 [(set_attr "op_type" "SS")
576 (set_attr "atype" "mem")
577 (set_attr "type" "xset")])
584 (compare (match_operand:QI 0 "s_operand" "Qo")
585 (match_operand:QI 1 "const0_operand" "")))
586 (set (match_operand:QI 2 "register_operand" "=d")
588 "s390_match_ccmode(insn, CCSmode)"
590 [(set_attr "op_type" "RS")
591 (set_attr "atype" "mem")
592 (set_attr "type" "set")])
596 (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo")
597 (match_operand:QI 1 "immediate_operand" "")))
599 "s390_match_ccmode(insn, CCTmode) &&
600 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
602 [(set_attr "op_type" "RI")
603 (set_attr "atype" "mem")
604 (set_attr "type" "xset")])
606 (define_insn "*cmpqi_cct_0"
608 (compare (match_operand:QI 0 "register_operand" "d")
609 (match_operand:QI 1 "const0_operand" "")))]
610 "s390_match_ccmode(insn, CCTmode)"
612 [(set_attr "op_type" "RI")
613 (set_attr "type" "xset")])
615 (define_insn "*cmpqi_ccs_0"
617 (compare (match_operand:QI 0 "s_operand" "Qo")
618 (match_operand:QI 1 "const0_operand" "")))
619 (clobber (match_scratch:QI 2 "=d"))]
620 "s390_match_ccmode(insn, CCSmode)"
622 [(set_attr "op_type" "RS")
623 (set_attr "type" "xset")])
625 (define_insn "*cmpqi_ccu_0"
627 (compare (match_operand:QI 0 "s_operand" "Qo")
628 (match_operand:QI 1 "const0_operand" "")))]
629 "s390_match_ccmode(insn, CCUmode)"
631 [(set_attr "op_type" "SI")
632 (set_attr "atype" "mem")
633 (set_attr "type" "xset")])
635 (define_insn "*cmpqi_ccu"
637 (compare (match_operand:QI 0 "register_operand" "d")
638 (match_operand:QI 1 "s_operand" "Qo")))]
639 "s390_match_ccmode(insn, CCUmode)"
641 [(set_attr "op_type" "RS")
642 (set_attr "atype" "mem")
643 (set_attr "type" "xset")])
645 (define_insn "*cmpqi_ccu_immed"
647 (compare (match_operand:QI 0 "s_operand" "Qo")
648 (match_operand:QI 1 "immediate_operand" "")))]
649 "s390_match_ccmode(insn, CCUmode) &&
650 INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
652 [(set_attr "op_type" "SI")
653 (set_attr "atype" "mem")
654 (set_attr "type" "xset")])
656 (define_insn "*cmpqi_ccu_mem"
658 (compare (match_operand:QI 0 "s_operand" "oQ")
659 (match_operand:QI 1 "s_operand" "oQ")))]
660 "s390_match_ccmode(insn, CCUmode)"
661 "clc\\t%O0(1,%R0),%1"
662 [(set_attr "op_type" "SS")
663 (set_attr "atype" "mem")
664 (set_attr "type" "xset")])
669 (define_insn "*cmpdf_ccs_0"
671 (compare (match_operand:DF 0 "register_operand" "f")
672 (match_operand:DF 1 "const0_operand" "")))]
673 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
675 [(set_attr "op_type" "RR")
676 (set_attr "type" "set")])
678 (define_insn "*cmpdf_ccs_0_ibm"
680 (compare (match_operand:DF 0 "register_operand" "f")
681 (match_operand:DF 1 "const0_operand" "")))]
682 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
684 [(set_attr "op_type" "RR")
685 (set_attr "type" "set")])
687 (define_insn "*cmpdf_ccs"
689 (compare (match_operand:DF 0 "register_operand" "f,f")
690 (match_operand:DF 1 "nonimmediate_operand" "f,m")))]
691 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
695 [(set_attr "op_type" "RR,RX")
696 (set_attr "atype" "reg,mem")
697 (set_attr "type" "xset,xset")])
699 (define_insn "*cmpdf_ccs_ibm"
701 (compare (match_operand:DF 0 "register_operand" "f,f")
702 (match_operand:DF 1 "nonimmediate_operand" "f,m")))]
703 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
707 [(set_attr "op_type" "RR,RX")
708 (set_attr "atype" "reg,mem")
709 (set_attr "type" "xset,xset")])
714 (define_insn "*cmpsf_ccs_0"
716 (compare (match_operand:SF 0 "register_operand" "f")
717 (match_operand:SF 1 "const0_operand" "")))]
718 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
720 [(set_attr "op_type" "RR")
721 (set_attr "type" "set")])
723 (define_insn "*cmpsf_ccs_0_ibm"
725 (compare (match_operand:SF 0 "register_operand" "f")
726 (match_operand:SF 1 "const0_operand" "")))]
727 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
729 [(set_attr "op_type" "RR")
730 (set_attr "type" "set")])
732 (define_insn "*cmpsf_ccs"
734 (compare (match_operand:SF 0 "register_operand" "f,f")
735 (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
736 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
740 [(set_attr "op_type" "RR,RX")
741 (set_attr "atype" "reg,mem")
742 (set_attr "type" "xset,xset")])
744 (define_insn "*cmpsf_ccs"
746 (compare (match_operand:SF 0 "register_operand" "f,f")
747 (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
748 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
752 [(set_attr "op_type" "RR,RX")
753 (set_attr "atype" "reg,mem")
754 (set_attr "type" "xset,xset")])
758 ;;- Move instructions.
762 ; movti instruction pattern(s).
766 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,d,d,m,Q")
767 (match_operand:TI 1 "general_operand" "d,K,m,d,Q"))]
771 switch (which_alternative)
774 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
775 return \"lgr\\t%M0,%M1\;lgr\\t%0,%1\";
777 return \"lgr\\t%0,%1\;lgr\\t%M0,%M1\";
780 if (INTVAL(operands[1]) < 0)
781 return \"lghi\\t%0,-1\;lghi\\t%M0,%h1\";
783 return \"lghi\\t%0,0\;lghi\\t%M0,%h1\";
786 if (s_operand (operands[1], GET_MODE (operands[1])))
787 return \"lmg\\t%0,%M0,%1\";
789 return \"la\\t%M0,%1\;lmg\\t%0,%M0,0(%M0)\";
792 if (!s_operand (operands[0], GET_MODE (operands[0])))
793 return \"stg\\t%1,%0\;stg\\t%M1,%M0\";
795 return \"stmg\\t%1,%M1,%0\";
798 return \"mvc\\t%O0(16,%R0),%1\";
804 [(set_attr "op_type" "NN,NN,RS,RS,SS")
805 (set_attr "atype" "reg,reg,mem,mem,mem")
806 (set_attr "type" "set")
807 (set_attr "length" "12,8,10,10,*")])
810 ; movdi instruction pattern(s).
813 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
814 ;; move to get the address of the symbolic object from the GOT.
816 (define_expand "movdi"
817 [(set (match_operand:DI 0 "general_operand" "")
818 (match_operand:DI 1 "general_operand" ""))]
822 if (CONSTANT_P (operands[1])
823 && !LEGITIMATE_CONSTANT_P (operands[1]))
824 operands[1] = force_const_mem (DImode, operands[1]);
826 if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1]))
827 emit_pic_move (operands, DImode);
830 (define_insn "*movdi_64"
831 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,m,Q")
832 (match_operand:DI 1 "general_operand" "d,K,S,m,d,Q"))]
841 [(set_attr "op_type" "RRE,RI,RIL,RXE,RXE,SS")
842 (set_attr "atype" "reg,reg,reg,mem,mem,mem")
843 (set_attr "type" "set,set,la,set,set,set")])
845 (define_insn "*movdi_31"
846 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,Q")
847 (match_operand:DI 1 "general_operand" "d,K,m,d,Q"))]
851 switch (which_alternative)
854 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
855 return \"lr\\t%N0,%N1\;lr\\t%0,%1\";
857 return \"lr\\t%0,%1\;lr\\t%N0,%N1\";
860 if (INTVAL (operands[1]) < 0)
861 return \"lhi\\t%0,-1\;lhi\\t%N0,%h1\";
863 return \"lhi\\t%0,0\;lhi\\t%N0,%h1\";
866 if (s_operand (operands[1], GET_MODE (operands[1])))
867 return \"lm\\t%0,%N0,%1\";
869 return \"la\\t%N0,%1\;lm\\t%0,%N0,0(%N0)\";
872 if (s_operand (operands[0], GET_MODE (operands[0])))
873 return \"stm\\t%1,%N1,%0\";
875 return \"st\\t%1,%0\;st\\t%N1,%N0\";
878 return \"mvc\\t%O0(8,%R0),%1\";
884 [(set_attr "op_type" "NN,NN,RS,RS,SS")
885 (set_attr "atype" "reg,reg,mem,mem,mem")
886 (set_attr "type" "set")
887 (set_attr "length" "4,8,8,8,*")])
891 ; movsi instruction pattern(s).
894 ;; If generating PIC code and operands[1] is a symbolic CONST, emit a
895 ;; move to get the address of the symbolic object from the GOT.
897 (define_expand "movsi"
898 [(set (match_operand:SI 0 "general_operand" "")
899 (match_operand:SI 1 "general_operand" ""))]
903 if (CONSTANT_P (operands[1])
904 && !LEGITIMATE_CONSTANT_P (operands[1]))
905 operands[1] = force_const_mem (SImode, operands[1]);
907 if (flag_pic && SYMBOLIC_CONST (operands[1]))
908 emit_pic_move (operands, SImode);
911 (define_insn "*movsi"
912 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,Q")
913 (match_operand:SI 1 "general_operand" "d,K,m,d,Q"))]
921 [(set_attr "op_type" "RR,RI,RX,RX,SS")
922 (set_attr "atype" "reg,reg,mem,mem,mem")
923 (set_attr "type" "set")])
927 ; movhi instruction pattern(s).
931 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m")
932 (match_operand:HI 1 "r_or_x_or_im16_operand" "d,K,m,d"))]
939 [(set_attr "op_type" "RR,RI,RX,RX")
940 (set_attr "atype" "reg,reg,mem,mem")
941 (set_attr "type" "xset")])
945 ; movqi instruction pattern(s).
948 (define_insn "movqi_64"
949 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
950 (match_operand:QI 1 "general_operand" "d,K,m,d,n"))]
958 [(set_attr "op_type" "RR,RI,RXE,RX,SI")
959 (set_attr "atype" "reg,reg,mem,mem,mem")
960 (set_attr "type" "xset")])
964 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q")
965 (match_operand:QI 1 "r_or_x_or_im16_operand" "d,n,m,d,n"))]
973 [(set_attr "op_type" "RR,RX,RX,RX,SI")
974 (set_attr "atype" "reg,reg,mem,mem,mem")
975 (set_attr "type" "xset")])
979 ; moveqstrictqi instruction pattern(s).
982 (define_insn "*movstrictqi"
983 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d,m"))
984 (match_operand:QI 1 "nonimmediate_operand" "m,d"))]
989 [(set_attr "op_type" "RX,RX")
990 (set_attr "atype" "mem,mem")])
994 ; movstricthi instruction pattern(s).
997 (define_insn "*movstricthi"
998 [(set (strict_low_part (match_operand:HI 0 "r_or_s_operand" "+d,Q"))
999 (match_operand:HI 1 "r_or_s_operand" "Q,d"))
1000 (clobber (reg:CC 33))]
1005 [(set_attr "op_type" "RS,RS")
1006 (set_attr "atype" "mem")
1007 (set_attr "type" "xset")])
1011 ; movstrictsi instruction pattern(s).
1014 (define_insn "movestrictsi"
1015 [(set (strict_low_part (match_operand:SI 0 "nonimmediate_operand" "+d,d,m"))
1016 (match_operand:SI 1 "nonimmediate_operand" "d,m,d"))]
1022 [(set_attr "op_type" "RR,RS,RS")
1023 (set_attr "atype" "reg,mem,mem")
1024 (set_attr "type" "xset")])
1028 ; movdf instruction pattern(s).
1031 (define_expand "movdf"
1032 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1033 (match_operand:DF 1 "general_operand" ""))]
1037 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1038 operands[1] = force_const_mem (DFmode, operands[1]);
1041 (define_insn "*movdf_64"
1042 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,m,d,Q")
1043 (match_operand:DF 1 "general_operand" "f,m,f,m,d,d,Q"))]
1044 "TARGET_64BIT && TARGET_HARD_FLOAT"
1052 mvc\\t%O0(8,%R0),%1"
1053 [(set_attr "op_type" "RR,RX,RX,RXE,RXE,RR,SS")
1054 (set_attr "atype" "reg,mem,mem,mem,mem,mem,mem")
1055 (set_attr "type" "xset")])
1057 (define_insn "*movdf_31"
1058 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,m,d,Q")
1059 (match_operand:DF 1 "general_operand" "f,m,f,m,d,d,Q"))]
1063 switch (which_alternative)
1065 case 0: /* f <- f */
1066 return \"ldr\\t%0,%1\";
1068 case 1: /* f <- m */
1069 return \"ld\\t%0,%1\";
1071 case 2: /* m <- f */
1072 return \"std\\t%1,%0\";
1074 case 3: /* d <- m */
1075 if (s_operand (operands[1], GET_MODE (operands[1])))
1076 return \"lm\\t%0,%N0,%1\";
1078 return \"la\\t%N0,%1\;lm\\t%0,%N0,0(%N0)\";
1080 case 4: /* m <- d */
1081 if (s_operand (operands[0], GET_MODE (operands[0])))
1082 return \"stm\\t%1,%N1,%0\";
1084 return \"st\\t%1,%0\;st\\t%N1,%N0\";
1086 case 5: /* d <- d */
1087 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
1088 return \"lr\\t%N0,%N1\;lr\\t%0,%1\";
1090 return \"lr\\t%0,%1\;lr\\t%N0,%N1\";
1092 case 6: /* m <- m */
1093 return \"mvc\\t%O0(8,%R0),%1\";
1099 [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,SS")
1100 (set_attr "atype" "reg,mem,mem,mem,mem,reg,mem")
1101 (set_attr "length" "*,*,*,*,*,4,*")])
1103 (define_insn "*movdf_soft_64"
1104 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,m,d,Q")
1105 (match_operand:DF 1 "general_operand" "m,d,d,Q"))]
1106 "TARGET_64BIT && TARGET_SOFT_FLOAT"
1111 mvc\\t%O0(8,%R0),%1"
1112 [(set_attr "op_type" "RXE,RXE,RR,SS")
1113 (set_attr "atype" "mem,mem,mem,mem")
1114 (set_attr "type" "xset")])
1116 (define_insn "*movdf_soft_31"
1117 [(set (match_operand:DF 0 "nonimmediate_operand" "=!d,d,m,Q")
1118 (match_operand:DF 1 "general_operand" "!d,m,d,Q"))]
1122 switch (which_alternative)
1124 case 0: /* d <- d */
1125 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
1126 return \"lr\\t%N0,%N1\;lr\\t%0,%1\";
1128 return \"lr\\t%0,%1\;lr\\t%N0,%N1\";
1130 case 1: /* d <- m */
1131 if (s_operand (operands[1], GET_MODE (operands[1])))
1132 return \"lm\\t%0,%N0,%1\";
1134 return \"la\\t%N0,%1\;lm\\t%0,%N0,0(%N0)\";
1136 case 2: /* m <- d */
1137 if (s_operand (operands[0], GET_MODE (operands[0])))
1138 return \"stm\\t%1,%N1,%0\";
1140 return \"st\\t%1,%0\;st\\t%N1,%N0\";
1142 case 3: /* m <- m */
1143 return \"mvc\\t%O0(8,%R0),%1\";
1149 [(set_attr "op_type" "NN,RS,RS,SS")
1150 (set_attr "atype" "reg,mem,mem,mem")
1151 (set_attr "length" "8,*,*,*")])
1155 ; movsf instruction pattern(s).
1158 (define_expand "movsf"
1159 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1160 (match_operand:SF 1 "general_operand" ""))]
1164 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1165 operands[1] = force_const_mem (SFmode, operands[1]);
1168 (define_insn "*movsf_64"
1169 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,m,d,Q")
1170 (match_operand:SF 1 "general_operand" "f,m,f,m,d,d,Q"))]
1171 "TARGET_64BIT && TARGET_HARD_FLOAT"
1179 mvc\\t%O0(4,%R0),%1"
1180 [(set_attr "op_type" "RR,RX,RX,RXE,RX,RR,SS")
1181 (set_attr "atype" "reg,mem,mem,mem,mem,reg,mem")])
1183 (define_insn "*movsf_31"
1184 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,m,d,Q")
1185 (match_operand:SF 1 "general_operand" "f,m,f,m,d,d,Q"))]
1194 mvc\\t%O0(4,%R0),%1"
1195 [(set_attr "op_type" "RR,RX,RX,RX,RX,RR,SS")
1196 (set_attr "atype" "reg,mem,mem,mem,mem,reg,mem")])
1198 (define_insn "*movsf_soft"
1199 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m,Q")
1200 (match_operand:SF 1 "general_operand" "d,m,d,Q"))]
1206 mvc\\t%O0(4,%R0),%1"
1207 [(set_attr "op_type" "RR,RX,RX,SS")
1208 (set_attr "atype" "reg,mem,mem,mem")])
1210 ; load_multiple pattern(s).
1213 (define_expand "load_multiple"
1214 [(match_par_dup 3 [(set (match_operand 0 "" "")
1215 (match_operand 1 "" ""))
1216 (use (match_operand 2 "" ""))])]
1225 /* Support only loading a constant number of fixed-point registers from
1226 memory and only bother with this if more than two */
1227 if (GET_CODE (operands[2]) != CONST_INT
1228 || INTVAL (operands[2]) <= 2
1229 || INTVAL (operands[2]) > 16
1230 || GET_CODE (operands[1]) != MEM
1231 || GET_CODE (operands[0]) != REG
1232 || REGNO (operands[0]) >= 16)
1235 count = INTVAL (operands[2]);
1236 regno = REGNO (operands[0]);
1238 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1239 from = force_reg (Pmode, XEXP (operands[1], 0));
1241 for (i = 0; i < count; i++)
1242 XVECEXP (operands[3], 0, i)
1243 = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i),
1244 change_address (operands[1], Pmode,
1245 plus_constant (from, i * 4)));
1248 (define_insn "*load_multiple_di"
1249 [(match_parallel 0 "load_multiple_operation"
1250 [(set (match_operand:DI 1 "register_operand" "=r")
1251 (match_operand:DI 2 "s_operand" "oQ"))])]
1255 int words = XVECLEN (operands[0], 0);
1257 if (XVECLEN (operands[0], 0) == 1)
1258 return \"lg\\t%1,0(%2)\";
1260 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1261 return \"lmg\\t%1,%0,%2\";
1263 [(set_attr "op_type" "RXE")
1264 (set_attr "atype" "mem")
1265 (set_attr "type" "set")])
1267 (define_insn "*load_multiple_si"
1268 [(match_parallel 0 "load_multiple_operation"
1269 [(set (match_operand:SI 1 "register_operand" "=r")
1270 (match_operand:SI 2 "s_operand" "oQ"))])]
1274 int words = XVECLEN (operands[0], 0);
1276 if (XVECLEN (operands[0], 0) == 1)
1277 return \"l\\t%1,0(%2)\";
1279 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1280 return \"lm\\t%1,%0,%2\";
1282 [(set_attr "op_type" "RXE")
1283 (set_attr "atype" "mem")
1284 (set_attr "type" "set")])
1287 ; store multiple pattern(s).
1290 (define_expand "store_multiple"
1291 [(match_par_dup 3 [(set (match_operand 0 "" "")
1292 (match_operand 1 "" ""))
1293 (use (match_operand 2 "" ""))])]
1302 /* Support only storing a constant number of fixed-point registers to
1303 memory and only bother with this if more than two. */
1304 if (GET_CODE (operands[2]) != CONST_INT
1305 || INTVAL (operands[2]) <= 2
1306 || INTVAL (operands[2]) > 16
1307 || GET_CODE (operands[0]) != MEM
1308 || GET_CODE (operands[1]) != REG
1309 || REGNO (operands[1]) >= 16)
1312 count = INTVAL (operands[2]);
1313 regno = REGNO (operands[1]);
1315 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1316 to = force_reg (Pmode, XEXP (operands[0], 0));
1318 for (i = 0; i < count; i++)
1319 XVECEXP (operands[3], 0, i)
1320 = gen_rtx_SET (VOIDmode,
1321 change_address (operands[0], Pmode,
1322 plus_constant (to, i * 4)),
1323 gen_rtx_REG (Pmode, regno + i));
1326 (define_insn "*store_multiple_di"
1327 [(match_parallel 0 "store_multiple_operation"
1328 [(set (match_operand:DI 1 "s_operand" "=oQ")
1329 (match_operand:DI 2 "register_operand" "r"))])]
1333 int words = XVECLEN (operands[0], 0);
1335 if (XVECLEN (operands[0], 0) == 1)
1336 return \"stg\\t%1,0(%2)\";
1338 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1339 return \"stmg\\t%2,%0,%1\";
1341 [(set_attr "op_type" "RXE")
1342 (set_attr "atype" "mem")
1343 (set_attr "type" "xset")])
1346 (define_insn "*store_multiple_si"
1347 [(match_parallel 0 "store_multiple_operation"
1348 [(set (match_operand:SI 1 "s_operand" "=oQ")
1349 (match_operand:SI 2 "register_operand" "r"))])]
1353 int words = XVECLEN (operands[0], 0);
1355 if (XVECLEN (operands[0], 0) == 1)
1356 return \"st\\t%1,0(%2)\";
1358 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1359 return \"stm\\t%2,%0,%1\";
1361 [(set_attr "op_type" "RXE")
1362 (set_attr "atype" "mem")
1363 (set_attr "type" "xset")])
1366 ;; String instructions.
1370 ; movstrdi instruction pattern(s).
1373 (define_expand "movstrdi"
1374 [(set (match_operand:BLK 0 "general_operand" "")
1375 (match_operand:BLK 1 "general_operand" ""))
1376 (use (match_operand:DI 2 "general_operand" ""))
1377 (match_operand 3 "" "")]
1383 addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1384 addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1386 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1388 operands[0] = change_address (operands[0], VOIDmode, addr0);
1389 operands[1] = change_address (operands[1], VOIDmode, addr1);
1390 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1392 emit_insn (gen_movstrsico (operands[0], operands[1], operands[2]));
1399 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1400 rtx reg0 = gen_reg_rtx (TImode);
1401 rtx reg1 = gen_reg_rtx (TImode);
1402 rtx len = operands[2];
1404 if (! CONSTANT_P (len))
1405 len = force_reg (DImode, len);
1407 /* Load up the address+length pairs. */
1409 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 0), addr0);
1410 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 8), len);
1412 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 0), addr1);
1413 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 8), len);
1416 emit_insn (gen_movstrdi_64 (reg0, reg1));
1421 rtx label = gen_label_rtx ();
1422 rtx reg0, reg1, len;
1424 reg0 = gen_reg_rtx (DImode);
1425 reg1 = gen_reg_rtx (DImode);
1426 len = gen_reg_rtx (DImode);
1428 emit_move_insn (len, operands[2]);
1429 emit_insn (gen_cmpdi (len, const0_rtx));
1430 emit_jump_insn (gen_beq (label));
1431 emit_move_insn (reg0, addr0);
1432 emit_move_insn (reg1, addr1);
1433 emit_insn (gen_adddi3 (len, len, constm1_rtx));
1434 emit_insn (gen_movstrdix_64 (reg0, reg1, len));
1442 ; movstrsi instruction pattern(s).
1445 (define_expand "movstrsi"
1446 [(set (match_operand:BLK 0 "general_operand" "")
1447 (match_operand:BLK 1 "general_operand" ""))
1448 (use (match_operand:SI 2 "general_operand" ""))
1449 (match_operand 3 "" "")]
1453 rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX);
1454 rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1456 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256)
1458 operands[0] = change_address (operands[0], VOIDmode, addr0);
1459 operands[1] = change_address (operands[1], VOIDmode, addr1);
1460 operands[2] = GEN_INT (INTVAL (operands[2]) - 1);
1462 emit_insn (gen_movstrsico (operands[0], operands[1], operands[2]));
1472 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1473 rtx reg0 = gen_reg_rtx (DImode);
1474 rtx reg1 = gen_reg_rtx (DImode);
1475 rtx len = operands[2];
1478 if (! CONSTANT_P (len))
1479 len = force_reg (SImode, len);
1481 /* Load up the address+length pairs. */
1483 emit_move_insn (gen_rtx_SUBREG (SImode, reg0, 0), addr0);
1484 emit_move_insn (gen_rtx_SUBREG (SImode, reg0, 4), len);
1486 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 0), addr1);
1487 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 4), len);
1490 emit_insn (gen_movstrsi_31 (reg0, reg1));
1495 rtx label = gen_label_rtx ();
1496 rtx reg0, reg1, len;
1498 reg0 = gen_reg_rtx (SImode);
1499 reg1 = gen_reg_rtx (SImode);
1500 len = gen_reg_rtx (SImode);
1502 emit_move_insn (len, operands[2]);
1503 emit_insn (gen_cmpsi (len, const0_rtx));
1504 emit_jump_insn (gen_beq (label));
1505 emit_move_insn (reg0, addr0);
1506 emit_move_insn (reg1, addr1);
1507 emit_insn (gen_addsi3 (len, len, constm1_rtx));
1508 emit_insn (gen_movstrsix_31 (reg0, reg1, len));
1515 ; Move a block that is less than 256 bytes in length.
1517 (define_insn "movstrsico"
1518 [(set (match_operand:BLK 0 "s_operand" "=oQ")
1519 (match_operand:BLK 1 "s_operand" "oQ"))
1520 (use (match_operand 2 "const_int_operand" "I"))]
1521 "((unsigned) INTVAL (operands[2]) < 256)"
1522 "mvc\\t%O0(%c2+1,%R0),%1"
1523 [(set_attr "op_type" "SS")
1524 (set_attr "atype" "mem")])
1526 ; Move a block that is more than 256 bytes in lenght or length in register
1528 (define_insn "movstrdix_64"
1529 [(set (mem:BLK (match_operand:DI 0 "register_operand" "a"))
1530 (mem:BLK (match_operand:DI 1 "register_operand" "a")))
1531 (use (match_operand:DI 2 "register_operand" "a"))
1532 (clobber (match_dup 0))
1533 (clobber (match_dup 1))
1534 (clobber (match_scratch:DI 3 "=&a"))
1535 (clobber (reg:CC 33))]
1540 xop[0] = gen_label_rtx ();
1541 xop[1] = gen_label_rtx ();
1542 xop[2] = gen_label_rtx ();
1543 xop[3] = operands[3];
1544 output_asm_insn (\"srag\\t%3,%2,8\",operands);
1545 output_asm_insn (\"jz\\t%l1\",xop);
1546 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1547 CODE_LABEL_NUMBER (xop[0]));
1548 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\",operands);
1549 output_asm_insn (\"la\\t%0,256(%0)\",operands);
1550 output_asm_insn (\"la\\t%1,256(%1)\",operands);
1551 xop[3] = operands[3];
1552 output_asm_insn (\"brct\\t%3,%l0\",xop);
1553 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1554 CODE_LABEL_NUMBER (xop[1]));
1555 xop[3] = operands[3];
1556 output_asm_insn (\"bras\\t%3,%l2\",xop);
1557 output_asm_insn (\"mvc\\t0(1,%0),0(%1)\",operands);
1558 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1559 CODE_LABEL_NUMBER (xop[2]));
1560 return \"ex\\t%2,0(%3)\";
1562 [(set_attr "op_type" "NN")
1563 (set_attr "atype" "mem")
1564 (set_attr "length" "44")])
1566 (define_insn "movstrsix_31"
1567 [(set (mem:BLK (match_operand:SI 0 "register_operand" "a"))
1568 (mem:BLK (match_operand:SI 1 "register_operand" "a")))
1569 (use (match_operand:SI 2 "register_operand" "a"))
1570 (clobber (match_dup 0))
1571 (clobber (match_dup 1))
1572 (clobber (match_scratch:SI 3 "=&a"))
1573 (clobber (reg:CC 33))]
1578 xop[0] = gen_label_rtx ();
1579 xop[1] = gen_label_rtx ();
1580 xop[2] = gen_label_rtx ();
1581 xop[3] = operands[3];
1582 output_asm_insn (\"lr\\t%3,%2\",operands);
1583 output_asm_insn (\"sra\\t%3,8\",operands);
1584 output_asm_insn (\"jz\\t%l1\",xop);
1585 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1586 CODE_LABEL_NUMBER (xop[0]));
1587 output_asm_insn (\"mvc\\t0(256,%0),0(%1)\",operands);
1588 output_asm_insn (\"la\\t%0,256(%0)\",operands);
1589 output_asm_insn (\"la\\t%1,256(%1)\",operands);
1590 xop[3] = operands[3];
1591 output_asm_insn (\"brct\\t%3,%l0\",xop);
1592 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1593 CODE_LABEL_NUMBER (xop[1]));
1594 xop[3] = operands[3];
1595 output_asm_insn (\"bras\\t%3,%l2\",xop);
1596 output_asm_insn (\"mvc\\t0(1,%0),0(%1)\",operands);
1597 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
1598 CODE_LABEL_NUMBER (xop[2]));
1599 return \"ex\\t%2,0(%3)\";
1601 [(set_attr "op_type" "NN")
1602 (set_attr "length" "42")
1603 (set_attr "atype" "mem")])
1605 ; Move a block that is larger than 255 bytes in length.
1607 (define_insn "movstrdi_64"
1608 [(set (mem:BLK (subreg:DI (match_operand:TI 0 "register_operand" "d") 0))
1609 (mem:BLK (subreg:DI (match_operand:TI 1 "register_operand" "d") 0)))
1610 (clobber (match_dup 0))
1611 (clobber (match_dup 1))
1612 (clobber (reg:CC 33))]
1614 "mvcle\\t%0,%1,0\;jo\\t.-4"
1615 [(set_attr "op_type" "NN")
1616 (set_attr "atype" "mem")
1617 (set_attr "length" "8")])
1619 (define_insn "movstrsi_31"
1620 [(set (mem:BLK (subreg:SI (match_operand:DI 0 "register_operand" "d") 0))
1621 (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "d") 0)))
1622 (clobber (match_dup 0))
1623 (clobber (match_dup 1))
1624 (clobber (reg:CC 33))]
1626 "mvcle\\t%0,%1,0\;jo\\t.-4"
1627 [(set_attr "op_type" "NN")
1628 (set_attr "atype" "mem")
1629 (set_attr "length" "8")])
1632 ; clrstrdi instruction pattern(s).
1635 (define_expand "clrstrdi"
1636 [(set (match_operand:BLK 0 "general_operand" "")
1638 (use (match_operand:DI 1 "general_operand" ""))
1639 (match_operand 2 "" "")]
1643 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1645 operands[0] = change_address (operands[0], VOIDmode, addr);
1647 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1649 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1654 rtx reg0 = gen_reg_rtx (TImode);
1655 rtx reg1 = gen_reg_rtx (TImode);
1656 rtx len = operands[1];
1658 if (! CONSTANT_P (len))
1659 len = force_reg (DImode, len);
1661 /* Load up the address+length pairs. */
1663 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 0), addr);
1664 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 8), len);
1666 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 8), const0_rtx);
1669 emit_insn (gen_clrstrsi_64 (reg0, reg1));
1675 ; clrstrsi instruction pattern(s).
1678 (define_expand "clrstrsi"
1679 [(set (match_operand:BLK 0 "general_operand" "")
1681 (use (match_operand:SI 1 "general_operand" ""))
1682 (match_operand 2 "" "")]
1686 rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX);
1688 operands[0] = change_address (operands[0], VOIDmode, addr);
1690 if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256)
1692 emit_insn (gen_clrstrsico (operands[0], operands[1]));
1697 rtx reg0 = gen_reg_rtx (DImode);
1698 rtx reg1 = gen_reg_rtx (DImode);
1699 rtx len = operands[1];
1701 if (! CONSTANT_P (len))
1702 len = force_reg (SImode, len);
1704 /* Load up the address+length pairs. */
1706 emit_move_insn (gen_rtx_SUBREG (SImode, reg0, 0), addr);
1707 emit_move_insn (gen_rtx_SUBREG (SImode, reg0, 4), len);
1709 emit_move_insn (gen_rtx_SUBREG (SImode, reg1, 4), const0_rtx);
1712 emit_insn (gen_clrstrsi_31 (reg0, reg1));
1717 ; Clear memory with length less than 256 bytes
1719 (define_insn "clrstrsico"
1720 [(set (match_operand:BLK 0 "s_operand" "=Qo")
1722 (use (match_operand 1 "immediate_operand" "I"))
1723 (clobber (reg:CC 33))]
1725 "xc\\t%O0(%1,%R0),%0"
1726 [(set_attr "op_type" "RS")
1727 (set_attr "atype" "mem")])
1729 ; Clear memory with length greater 256 bytes or lenght not constant
1731 (define_insn "clrstrsi_64"
1732 [(set (mem:BLK (subreg:DI (match_operand:TI 0 "register_operand" "d") 0))
1734 (use (match_operand:TI 1 "register_operand" "d"))
1735 (clobber (match_dup 0))
1736 (clobber (match_dup 1))
1737 (clobber (reg:CC 33))]
1739 "mvcle\\t%0,%1,0\;jo\\t.-4"
1740 [(set_attr "op_type" "NN")
1741 (set_attr "atype" "mem")
1742 (set_attr "cycle" "n")
1743 (set_attr "length" "8")])
1745 (define_insn "clrstrsi_31"
1746 [(set (mem:BLK (subreg:SI (match_operand:DI 0 "register_operand" "d") 0))
1748 (use (match_operand:DI 1 "register_operand" "d"))
1749 (clobber (match_dup 0))
1750 (clobber (match_dup 1))
1751 (clobber (reg:CC 33))]
1753 "mvcle\\t%0,%1,0\;jo\\t.-4"
1754 [(set_attr "op_type" "NN")
1755 (set_attr "atype" "mem")
1756 (set_attr "cycle" "n")
1757 (set_attr "length" "8")])
1760 ; cmpstrdi instruction pattern(s).
1763 (define_expand "cmpstrdi"
1764 [(set (match_operand:DI 0 "register_operand" "")
1765 (compare:DI (match_operand:BLK 1 "s_operand" "")
1766 (match_operand:BLK 2 "s_operand" "") ) )
1767 (use (match_operand:DI 3 "general_operand" ""))
1768 (use (match_operand:DI 4 "" ""))]
1774 /* for pre/post increment */
1775 operands[1] = protect_from_queue (operands[1], 0);
1776 operands[2] = protect_from_queue (operands[2], 0);
1777 operands[3] = protect_from_queue (operands[3], 0);
1779 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1780 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
1782 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
1784 if (INTVAL (operands[3]) == 0) {
1785 emit_move_insn (operands[0], operands[3]);
1789 operands[1] = change_address (operands[1], VOIDmode, addr0);
1790 operands[2] = change_address (operands[2], VOIDmode, addr1);
1792 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
1793 emit_insn (gen_cmpint_di (operands[0]));
1798 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1799 rtx reg0 = gen_reg_rtx (TImode);
1800 rtx reg1 = gen_reg_rtx (TImode);
1801 rtx len = operands[3];
1803 if (! CONSTANT_P (len))
1804 len = force_reg (DImode, len);
1806 /* Load up the address+length pairs. */
1807 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 0), addr0);
1808 emit_move_insn (gen_rtx_SUBREG (DImode, reg0, 8), len);
1810 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 0), addr1);
1811 emit_move_insn (gen_rtx_SUBREG (DImode, reg1, 8), len);
1814 emit_insn (gen_cmpstr_64 (reg0, reg1));
1815 emit_insn (gen_cmpint_di (operands[0]));
1821 ; cmpstrsi instruction pattern(s).
1824 (define_expand "cmpstrsi"
1825 [(set (match_operand:SI 0 "register_operand" "")
1826 (compare:SI (match_operand:BLK 1 "s_operand" "")
1827 (match_operand:BLK 2 "s_operand" "") ) )
1828 (use (match_operand:SI 3 "general_operand" ""))
1829 (use (match_operand:SI 4 "" ""))]
1835 /* for pre/post increment */
1836 operands[1] = protect_from_queue (operands[1], 0);
1837 operands[2] = protect_from_queue (operands[2], 0);
1838 operands[3] = protect_from_queue (operands[3], 0);
1840 addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX);
1841 addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX);
1843 if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256)
1845 if (INTVAL (operands[3]) == 0) {
1846 emit_move_insn (operands[0], operands[3]);
1850 operands[1] = change_address (operands[1], VOIDmode, addr0);
1851 operands[2] = change_address (operands[2], VOIDmode, addr1);
1853 emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3]));
1854 emit_insn (gen_cmpint_si (operands[0]));
1859 /* implementation suggested by Richard Henderson <rth@cygnus.com> */
1861 rtx len = operands[3];
1865 reg0 = gen_reg_rtx (TImode);
1866 reg1 = gen_reg_rtx (TImode);
1870 reg0 = gen_reg_rtx (DImode);
1871 reg1 = gen_reg_rtx (DImode);
1874 if (! CONSTANT_P (len))
1875 len = force_reg (Pmode, len);
1877 /* Load up the address+length pairs. */
1878 emit_move_insn (gen_rtx_SUBREG (Pmode, reg0, 0), addr0);
1879 emit_move_insn (gen_rtx_SUBREG (Pmode, reg0,
1880 GET_MODE_SIZE (Pmode)), len);
1882 emit_move_insn (gen_rtx_SUBREG (Pmode, reg1, 0), addr1);
1883 emit_move_insn (gen_rtx_SUBREG (Pmode, reg1,
1884 GET_MODE_SIZE (Pmode)), len);
1888 emit_insn (gen_cmpstr_64 (reg0, reg1));
1890 emit_insn (gen_cmpstr_31 (reg0, reg1));
1892 emit_insn (gen_cmpint_si (operands[0]));
1897 ; Compare a block that is less than 256 bytes in length.
1899 (define_insn "cmpstr_const"
1901 (compare:CCU (match_operand:BLK 0 "s_operand" "oQ")
1902 (match_operand:BLK 1 "s_operand" "oQ")))
1903 (use (match_operand 2 "immediate_operand" "I"))]
1904 "(unsigned) INTVAL (operands[2]) < 256"
1905 "clc\\t%O0(%c2,%R0),%1"
1906 [(set_attr "op_type" "SS")
1907 (set_attr "atype" "mem")
1908 (set_attr "type" "xset")])
1910 ; Compare a block that is larger than 255 bytes in length.
1912 (define_insn "cmpstr_64"
1914 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 0 "register_operand" "d") 0))
1915 (mem:BLK (subreg:DI (match_operand:TI 1 "register_operand" "d") 0))))
1916 (clobber (subreg:DI (match_dup 0) 0))
1917 (clobber (subreg:DI (match_dup 0) 8))
1918 (clobber (subreg:DI (match_dup 1) 0))
1919 (clobber (subreg:DI (match_dup 1) 8))]
1922 [(set_attr "op_type" "RR")
1923 (set_attr "atype" "mem")
1924 (set_attr "type" "xset")])
1926 (define_insn "cmpstr_31"
1928 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 0 "register_operand" "d") 0))
1929 (mem:BLK (subreg:SI (match_operand:DI 1 "register_operand" "d") 0))))
1930 (clobber (subreg:SI (match_dup 0) 0))
1931 (clobber (subreg:SI (match_dup 0) 4))
1932 (clobber (subreg:SI (match_dup 1) 0))
1933 (clobber (subreg:SI (match_dup 1) 4))]
1936 [(set_attr "op_type" "RR")
1937 (set_attr "atype" "mem")
1938 (set_attr "type" "xset")])
1940 ; Convert condition code to integer in range (-1, 0, 1)
1942 (define_insn "cmpint_si"
1943 [(set (match_operand:SI 0 "register_operand" "=d")
1944 (compare:SI (reg:CCU 33) (const_int 0)))]
1948 output_asm_insn (\"lhi\\t%0,1\", operands);
1949 output_asm_insn (\"jh\\t.+12\", operands);
1950 output_asm_insn (\"jl\\t.+6\", operands);
1951 output_asm_insn (\"sr\\t%0,%0\", operands);
1952 return \"lcr\\t%0,%0\";
1954 [(set_attr "op_type" "NN")
1955 (set_attr "length" "16")
1956 (set_attr "atype" "reg")
1957 (set_attr "type" "xset")])
1959 (define_insn "cmpint_di"
1960 [(set (match_operand:DI 0 "register_operand" "=d")
1961 (compare:DI (reg:CCU 33) (const_int 0)))]
1965 output_asm_insn (\"lghi\\t%0,1\", operands);
1966 output_asm_insn (\"jh\\t.+12\", operands);
1967 output_asm_insn (\"jl\\t.+6\", operands);
1968 output_asm_insn (\"sgr\\t%0,%0\", operands);
1969 return \"lcgr\\t%0,%0\";
1971 [(set_attr "op_type" "NN")
1972 (set_attr "length" "22")
1973 (set_attr "atype" "reg")
1974 (set_attr "type" "xset")])
1977 ;;- Conversion instructions.
1981 ; extendsidi2 instruction pattern(s).
1984 (define_insn "extendsidi2"
1985 [(set (match_operand:DI 0 "register_operand" "=d,d")
1986 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
1991 [(set_attr "op_type" "RRE,RXE")
1992 (set_attr "atype" "reg,mem")
1993 (set_attr "type" "set")])
1997 ; extendhidi2 instruction pattern(s).
2000 (define_insn "extendhidi2"
2001 [(set (match_operand:DI 0 "register_operand" "=d")
2002 (sign_extend:DI (match_operand:HI 1 "register_operand" "d")))
2003 (clobber (reg:CC 33))]
2005 "sllg\\t%0,%1,48\;srag\\t%0,%0,48"
2006 [(set_attr "op_type" "NN")
2007 (set_attr "length" "12")
2008 (set_attr "cycle" "2")
2009 (set_attr "type" "set")])
2013 ; extendqidi2 instruction pattern(s).
2016 (define_insn "extendqidi2"
2017 [(set (match_operand:DI 0 "register_operand" "=d")
2018 (sign_extend:DI (match_operand:QI 1 "register_operand" "d")))
2019 (clobber (reg:CC 33))]
2021 "sllg\\t%0,%1,56\;srag\\t%0,%0,56"
2022 [(set_attr "op_type" "NN")
2023 (set_attr "length" "12")
2024 (set_attr "cycle" "2")
2025 (set_attr "type" "set")])
2029 ; extendhisi2 instruction pattern(s).
2032 (define_insn "extendhisi2"
2033 [(set (match_operand:SI 0 "register_operand" "=d,!d,d")
2034 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,d,m")))
2035 (clobber (reg:CC 33))]
2038 sll\\t%1,16\;sra\\t%1,16
2039 lr\\t%0,%1\;sll\\t%0,16\;sra\\t%0,16
2041 [(set_attr "op_type" "NN,NN,RX")
2042 (set_attr "cycle" "2,3,1")
2043 (set_attr "atype" "reg,reg,mem")
2044 (set_attr "type" "set")
2045 (set_attr "length" "8,10,*")])
2049 ; extendqisi2 instruction pattern(s).
2052 (define_insn "extendqisi2"
2053 [(set (match_operand:SI 0 "register_operand" "=d,d")
2054 (sign_extend:SI (match_operand:QI 1 "r_or_s_operand" "0,Q")))
2055 (clobber (reg:CC 33))]
2058 sll\\t%0,24\;sra\\t%0,24
2059 icm\\t%0,8,%1\;sra\\t%0,24"
2060 [(set_attr "op_type" "NN,NN")
2061 (set_attr "cycle" "2")
2062 (set_attr "atype" "reg,mem")
2063 (set_attr "type" "set")
2064 (set_attr "length" "8,8")])
2068 ; extendqihi2 instruction pattern(s).
2071 (define_insn "extendqihi2"
2072 [(set (match_operand:HI 0 "register_operand" "=d,d")
2073 (sign_extend:HI (match_operand:QI 1 "r_or_s_operand" "0,Q")))
2074 (clobber (reg:CC 33))]
2077 sll\\t%0,24\;sra\\t%0,24
2078 icm\\t%0,8,%1\;sra\\t%0,24"
2079 [(set_attr "op_type" "NN,NN")
2080 (set_attr "cycle" "2")
2081 (set_attr "atype" "reg,mem")
2082 (set_attr "type" "set")
2083 (set_attr "length" "8,8")])
2087 ; zero_extendsidi2 instruction pattern(s).
2090 (define_insn "zero_extendsidi2"
2091 [(set (match_operand:DI 0 "register_operand" "=d,d")
2092 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2097 [(set_attr "op_type" "RRE,RXE")
2098 (set_attr "atype" "reg,mem")
2099 (set_attr "type" "set")])
2103 ; zero_extendhidi2 instruction pattern(s).
2106 (define_insn "zero_extendhidi2"
2107 [(set (match_operand:DI 0 "register_operand" "=!d,d")
2108 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
2111 llgfr\\t%0,%1\;iilh\\t%0,0
2113 [(set_attr "op_type" "NN,RXE")
2114 (set_attr "cycle" "2,1")
2115 (set_attr "atype" "reg,mem")
2116 (set_attr "length" "12,*")
2117 (set_attr "type" "set")])
2121 ; zero_extendqidi2 instruction pattern(s)
2124 (define_insn "zero_extendqidi2"
2125 [(set (match_operand:DI 0 "register_operand" "=!d,d")
2126 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,m")))
2127 (clobber (reg:CC 33))]
2130 sllg\\t%0,%1,56\;srlg\\t%0,%0,56
2132 [(set_attr "op_type" "NN,RXE")
2133 (set_attr "cycle" "2,1")
2134 (set_attr "atype" "reg,mem")
2135 (set_attr "type" "set")
2136 (set_attr "length" "12,*")])
2140 ; zero_extendhisi2 instruction pattern(s).
2143 (define_expand "zero_extendhisi2"
2144 [(set (match_operand:SI 0 "register_operand" "")
2145 (zero_extend:SI (match_operand:HI 1 "r_or_s_operand" "")))]
2151 emit_insn (gen_zero_extendhisi2_31 (operands[0], operands[1],
2152 force_const_mem (SImode, const0_rtx)));
2157 (define_insn "*zero_extendhisi2_64"
2158 [(set (match_operand:SI 0 "register_operand" "=d,d")
2159 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,m")))]
2164 [(set_attr "op_type" "RI,RXE")
2165 (set_attr "atype" "reg,mem")])
2167 (define_insn "zero_extendhisi2_31"
2168 [(set (match_operand:SI 0 "register_operand" "=d,d")
2169 (zero_extend:SI (match_operand:HI 1 "r_or_s_operand" "0,Q")))
2170 (use (match_operand:SI 2 "memory_operand" "m,m"))
2171 (clobber (reg:CC 33))]
2175 icm\\t%0,12,%1\;srl\\t%0,16"
2176 [(set_attr "op_type" "RX,NN")
2177 (set_attr "cycle" "1,2")
2178 (set_attr "atype" "reg,mem")
2179 (set_attr "type" "set")
2180 (set_attr "length" "*,8")])
2184 ; zero_extendqisi2 instruction pattern(s).
2187 (define_insn "*zero_extendqisi2_mem_31"
2188 [(set (match_operand:SI 0 "register_operand" "=&d")
2189 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))
2190 (use (match_operand:SI 2 "memory_operand" "m" ))
2191 (clobber (reg:CC 33))]
2193 "sr\\t%0,%0\;ic\\t%0,%1"
2194 [(set_attr "op_type" "NN")
2195 (set_attr "cycle" "2")
2196 (set_attr "atype" "mem")
2197 (set_attr "type" "set")
2198 (set_attr "length" "6")])
2200 (define_insn "zero_extendqisi2_reg_31"
2201 [(set (match_operand:SI 0 "register_operand" "=d")
2202 (zero_extend:SI (match_operand:QI 1 "register_operand" "0")))
2203 (use (match_operand:SI 2 "memory_operand" "m" ))
2204 (clobber (reg:CC 33))]
2207 [(set_attr "op_type" "RX")
2208 (set_attr "atype" "mem")
2209 (set_attr "type" "set")])
2211 (define_insn "*zero_extendqisi2_64"
2212 [(set (match_operand:SI 0 "register_operand" "=!d,d")
2213 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2216 sllg\\t%0,%1,56\;srlg\\t%0,%0,56
2218 [(set_attr "op_type" "NN,RXE")
2219 (set_attr "cycle" "2,1")
2220 (set_attr "atype" "reg,mem")
2221 (set_attr "length" "12,*")])
2223 (define_expand "zero_extendqisi2"
2224 [(set (match_operand:SI 0 "register_operand" "")
2225 (zero_extend:SI (match_operand:QI 1 "r_or_s_operand" "")))]
2231 emit_insn (gen_zero_extendqisi2_reg_31 (operands[0], operands[1],
2232 force_const_mem (SImode, const0_rtx)));
2239 ; zero_extendqihi2 instruction pattern(s).
2242 (define_insn "zero_extendqihi2_64"
2243 [(set (match_operand:HI 0 "register_operand" "=d,d")
2244 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))
2245 (clobber (reg:CC 33))]
2250 [(set_attr "op_type" "RI,RXE")
2251 (set_attr "atype" "reg,mem")])
2253 (define_insn "zero_extendqihi2_31"
2254 [(set (match_operand:HI 0 "register_operand" "=d,&d")
2255 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,m")))
2256 (use (match_operand:SI 2 "memory_operand" "m,m"))
2257 (clobber (reg:CC 33))]
2261 sr\\t%0,%0\;ic\\t%0,%1"
2262 [(set_attr "op_type" "RX,NN")
2263 (set_attr "atype" "reg,mem")
2264 (set_attr "length" "*,8")])
2266 (define_expand "zero_extendqihi2"
2267 [(set (match_operand:HI 0 "register_operand" "")
2268 (zero_extend:HI (match_operand:QI 1 "general_operand" "")))]
2274 emit_insn (gen_zero_extendqihi2_31 (operands[0], operands[1],
2275 force_const_mem (SImode, const0_rtx)));
2280 emit_insn (gen_zero_extendqihi2_64 (operands[0], operands[1]));
2287 ; truncdisi2 instruction pattern(s).
2290 (define_insn "truncdisi2"
2291 [(set (match_operand:SI 0 "register_operand" "=d")
2292 (truncate:SI (match_operand:DI 1 "register_operand" "d")))]
2295 [(set_attr "op_type" "RRE")])
2299 ; truncdihi2 instruction pattern(s).
2302 (define_insn "truncdihi2"
2303 [(set (match_operand:HI 0 "register_operand" "=d")
2304 (truncate:HI (match_operand:DI 1 "register_operand" "d")))]
2306 "llgfr\\t%0,%1\;iilh\\t%0,0"
2307 [(set_attr "op_type" "NN")
2308 (set_attr "length" "10")])
2312 ; truncdiqi2 instruction pattern(s).
2315 (define_insn "truncdiqi2"
2316 [(set (match_operand:QI 0 "register_operand" "=d")
2317 (truncate:QI (match_operand:DI 1 "register_operand" "d")))
2318 (clobber (reg:CC 33))]
2320 "sllg\\t%0,%1,56\;srlg\\t%0,%0,56"
2321 [(set_attr "op_type" "NN")
2322 (set_attr "cycle" "2")
2323 (set_attr "length" "12")])
2327 ; truncsihi2 instruction pattern(s).
2330 (define_expand "truncsihi2"
2331 [(set (match_operand:HI 0 "register_operand" "")
2332 (truncate:HI (match_operand:SI 1 "register_operand" "")))]
2338 emit_insn (gen_do_truncsihi2 (operands[0], operands[1],
2339 force_const_mem (SImode, const0_rtx)));
2345 (define_insn "do_truncsihi2"
2346 [(set (match_operand:HI 0 "register_operand" "=d")
2347 (truncate:HI (match_operand:SI 1 "register_operand" "0")))
2348 (use (match_operand:SI 2 "memory_operand" "m"))
2349 (clobber (reg:CC 33))]
2352 [(set_attr "op_type" "RX")])
2354 (define_insn "*truncsihi2_64"
2355 [(set (match_operand:HI 0 "register_operand" "=d")
2356 (truncate:HI (match_operand:SI 1 "register_operand" "0")))]
2359 [(set_attr "op_type" "RI")])
2363 ; truncsiqi2 instruction pattern(s).
2366 (define_insn "truncsiqi2"
2367 [(set (match_operand:QI 0 "register_operand" "=d")
2368 (truncate:QI (match_operand:SI 1 "register_operand" "0")))
2369 (clobber (reg:CC 33))]
2371 "iilh\\t%0,0\;nill\\t%0,0x00FF"
2372 [(set_attr "op_type" "NN")
2373 (set_attr "cycle" "2")
2374 (set_attr "length" "8")])
2378 ; trunchiqi2 instruction pattern(s).
2381 (define_insn "trunchiqi2"
2382 [(set (match_operand:QI 0 "register_operand" "=d")
2383 (truncate:QI (match_operand:HI 1 "register_operand" "0")))
2384 (clobber (reg:CC 33))]
2387 [(set_attr "op_type" "RI")])
2391 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2394 (define_expand "fixuns_truncdfdi2"
2395 [(set (match_operand:DI 0 "register_operand" "")
2396 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2397 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2400 rtx label1 = gen_label_rtx ();
2401 rtx label2 = gen_label_rtx ();
2402 rtx temp = gen_reg_rtx (DFmode);
2403 operands[1] = force_reg (DFmode, operands[1]);
2405 emit_insn (gen_cmpdf (operands[1], force_const_mem (DFmode,
2406 CONST_DOUBLE_FROM_REAL_VALUE (0x8000000000000000ULL, DFmode))));
2407 emit_jump_insn (gen_blt (label1));
2409 emit_insn (gen_subdf3 (temp, operands[1], force_const_mem (DFmode,
2410 CONST_DOUBLE_FROM_REAL_VALUE (0x10000000000000000ULL, DFmode))));
2411 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2414 emit_label (label1);
2415 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2416 emit_label (label2);
2420 (define_expand "fix_truncdfdi2"
2421 [(set (match_operand:DI 0 "register_operand" "")
2422 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2423 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2426 operands[1] = force_reg (DFmode, operands[1]);
2427 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2431 (define_insn "fix_truncdfdi2_ieee"
2432 [(set (match_operand:DI 0 "register_operand" "=d")
2433 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2434 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2435 (clobber (reg:CC 33))]
2436 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2438 [(set_attr "op_type" "RRE")
2439 (set_attr "cycle" "n")])
2442 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2445 (define_expand "fixuns_truncdfsi2"
2446 [(set (match_operand:SI 0 "register_operand" "")
2447 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2448 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2451 rtx label1 = gen_label_rtx ();
2452 rtx label2 = gen_label_rtx ();
2453 rtx temp = gen_reg_rtx (DFmode);
2455 operands[1] = force_reg (DFmode,operands[1]);
2456 emit_insn (gen_cmpdf (operands[1], force_const_mem (DFmode,
2457 CONST_DOUBLE_FROM_REAL_VALUE (0x80000000ULL, DFmode))));
2458 emit_jump_insn (gen_blt (label1));
2459 emit_insn (gen_subdf3 (temp, operands[1], force_const_mem (DFmode,
2460 CONST_DOUBLE_FROM_REAL_VALUE (0x100000000ULL, DFmode))));
2461 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2464 emit_label (label1);
2465 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2466 emit_label (label2);
2470 (define_expand "fix_truncdfsi2"
2471 [(set (match_operand:SI 0 "register_operand" "")
2472 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2476 if (TARGET_IBM_FLOAT)
2478 /* This is the algorithm from POP chapter A.5.7.2. */
2480 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2481 rtx two31r = force_const_mem (DFmode,
2482 gen_rtx (CONST_DOUBLE, VOIDmode, cc0_rtx,
2483 0x08000000, 0x4F000000));
2484 rtx two32 = force_const_mem (DFmode,
2485 gen_rtx (CONST_DOUBLE, VOIDmode, cc0_rtx,
2488 operands[1] = force_reg (DFmode, operands[1]);
2489 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2490 two31r, two32, temp));
2494 operands[1] = force_reg (DFmode, operands[1]);
2495 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2501 (define_insn "fix_truncdfsi2_ieee"
2502 [(set (match_operand:SI 0 "register_operand" "=d")
2503 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2504 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2505 (clobber (reg:CC 33))]
2506 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2508 [(set_attr "op_type" "RRE")
2509 (set_attr "cycle" "n" )])
2511 (define_insn "fix_truncdfsi2_ibm"
2512 [(set (match_operand:SI 0 "register_operand" "=d")
2513 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2514 (use (match_operand:DF 2 "memory_operand" "m"))
2515 (use (match_operand:DF 3 "memory_operand" "m"))
2516 (use (match_operand:BLK 4 "memory_operand" "m"))
2517 (clobber (reg:CC 33))]
2518 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2521 output_asm_insn (\"sd\\t%1,%2\", operands);
2522 output_asm_insn (\"aw\\t%1,%3\", operands);
2523 output_asm_insn (\"std\\t%1,%4\", operands);
2524 output_asm_insn (\"xi\\t%N4,128\", operands);
2525 return \"l\\t%0,%N4\";
2527 [(set_attr "op_type" "NN")
2528 (set_attr "cycle" "n")
2529 (set_attr "length" "20")])
2532 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
2535 (define_expand "fixuns_truncsfdi2"
2536 [(set (match_operand:DI 0 "register_operand" "")
2537 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
2538 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2541 rtx label1 = gen_label_rtx ();
2542 rtx label2 = gen_label_rtx ();
2543 rtx temp = gen_reg_rtx (SFmode);
2545 operands[1] = force_reg (SFmode, operands[1]);
2546 emit_insn (gen_cmpsf (operands[1], force_const_mem (SFmode,
2547 CONST_DOUBLE_FROM_REAL_VALUE (0x8000000000000000ULL, SFmode))));
2548 emit_jump_insn (gen_blt (label1));
2550 emit_insn (gen_subsf3 (temp, operands[1], force_const_mem (SFmode,
2551 CONST_DOUBLE_FROM_REAL_VALUE (0x10000000000000000ULL, SFmode))));
2552 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
2555 emit_label (label1);
2556 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2557 emit_label (label2);
2561 (define_expand "fix_truncsfdi2"
2562 [(set (match_operand:DI 0 "register_operand" "")
2563 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
2564 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2567 operands[1] = force_reg (SFmode, operands[1]);
2568 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2572 (define_insn "fix_truncsfdi2_ieee"
2573 [(set (match_operand:DI 0 "register_operand" "=d")
2574 (fix:DI (match_operand:SF 1 "register_operand" "f")))
2575 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1)
2576 (clobber (reg:CC 33))]
2577 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2579 [(set_attr "op_type" "RRE")
2580 (set_attr "cycle" "n")])
2583 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
2586 (define_expand "fixuns_truncsfsi2"
2587 [(set (match_operand:SI 0 "register_operand" "")
2588 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2589 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2592 rtx label1 = gen_label_rtx ();
2593 rtx label2 = gen_label_rtx ();
2594 rtx temp = gen_reg_rtx (SFmode);
2596 operands[1] = force_reg (SFmode, operands[1]);
2597 emit_insn (gen_cmpsf (operands[1], force_const_mem (SFmode,
2598 CONST_DOUBLE_FROM_REAL_VALUE (0x80000000ULL, SFmode))));
2599 emit_jump_insn (gen_blt (label1));
2600 emit_insn (gen_subsf3 (temp, operands[1], force_const_mem (SFmode,
2601 CONST_DOUBLE_FROM_REAL_VALUE (0x100000000ULL, SFmode))));
2602 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
2605 emit_label (label1);
2606 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2607 emit_label (label2);
2611 (define_expand "fix_truncsfsi2"
2612 [(set (match_operand:SI 0 "register_operand" "")
2613 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
2617 if (TARGET_IBM_FLOAT)
2619 /* Convert to DFmode and then use the POP algorithm. */
2620 rtx temp = gen_reg_rtx (DFmode);
2621 emit_insn (gen_extendsfdf2 (temp, operands[1]));
2622 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
2626 operands[1] = force_reg (SFmode, operands[1]);
2627 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2633 (define_insn "fix_truncsfsi2_ieee"
2634 [(set (match_operand:SI 0 "register_operand" "=d")
2635 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2636 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1)
2637 (clobber (reg:CC 33))]
2638 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2640 [(set_attr "op_type" "RRE")
2641 (set_attr "cycle" "n")])
2644 ; floatdidf2 instruction pattern(s).
2647 (define_insn "floatdidf2"
2648 [(set (match_operand:DF 0 "register_operand" "=f")
2649 (float:DF (match_operand:DI 1 "register_operand" "d")))]
2650 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2652 [(set_attr "op_type" "RRE")
2653 (set_attr "cycle" "n" )])
2656 ; floatdisf2 instruction pattern(s).
2659 (define_insn "floatdisf2"
2660 [(set (match_operand:SF 0 "register_operand" "=f")
2661 (float:SF (match_operand:DI 1 "register_operand" "d")))]
2662 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2664 [(set_attr "op_type" "RRE")
2665 (set_attr "cycle" "n" )])
2668 ; floatsidf2 instruction pattern(s).
2671 (define_expand "floatsidf2"
2672 [(set (match_operand:DF 0 "register_operand" "")
2673 (float:DF (match_operand:SI 1 "register_operand" "")))]
2677 if (TARGET_IBM_FLOAT)
2679 /* This is the algorithm from POP chapter A.5.7.1. */
2681 rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD);
2682 rtx two31 = force_const_mem (DFmode,
2683 gen_rtx (CONST_DOUBLE, VOIDmode, cc0_rtx,
2684 0x80000000U, 0x4E000000U));
2686 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
2691 (define_insn "floatsidf2_ieee"
2692 [(set (match_operand:DF 0 "register_operand" "=f")
2693 (float:DF (match_operand:SI 1 "register_operand" "d")))]
2694 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2696 [(set_attr "op_type" "RRE")
2697 (set_attr "cycle" "n" )])
2699 (define_insn "floatsidf2_ibm"
2700 [(set (match_operand:DF 0 "register_operand" "=f")
2701 (float:DF (match_operand:SI 1 "register_operand" "d")))
2702 (use (match_operand:DF 2 "memory_operand" "m"))
2703 (use (match_operand:BLK 3 "memory_operand" "m"))
2704 (clobber (reg:CC 33))]
2705 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2708 output_asm_insn (\"st\\t%0,%N3\", operands);
2709 output_asm_insn (\"xi\\t%N3,128\", operands);
2710 output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands);
2711 output_asm_insn (\"ld\\t%0,%3\", operands);
2712 return \"sd\\t%0,%2\";
2714 [(set_attr "op_type" "NN")
2715 (set_attr "cycle" "n" )
2716 (set_attr "length" "20")])
2719 ; floatsisf2 instruction pattern(s).
2722 (define_expand "floatsisf2"
2723 [(set (match_operand:SF 0 "register_operand" "")
2724 (float:SF (match_operand:SI 1 "register_operand" "")))]
2728 if (TARGET_IBM_FLOAT)
2730 /* Use the POP algorithm to convert to DFmode and then truncate. */
2731 rtx temp = gen_reg_rtx (DFmode);
2732 emit_insn (gen_floatsidf2 (temp, operands[1]));
2733 emit_insn (gen_truncdfsf2 (operands[0], temp));
2738 (define_insn "floatsisf2_ieee"
2739 [(set (match_operand:SF 0 "register_operand" "=f")
2740 (float:SF (match_operand:SI 1 "register_operand" "d")))]
2741 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2743 [(set_attr "op_type" "RRE")
2744 (set_attr "cycle" "n" )])
2747 ; truncdfsf2 instruction pattern(s).
2750 (define_expand "truncdfsf2"
2751 [(set (match_operand:SF 0 "register_operand" "")
2752 (float_truncate:SF (match_operand:DF 1 "general_operand" "")))]
2756 if (CONSTANT_P(operands[1]))
2757 operands[1] = force_const_mem (DFmode, operands[1]);
2760 (define_insn "truncdfsf2_ieee"
2761 [(set (match_operand:SF 0 "register_operand" "=f")
2762 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f")))]
2763 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2765 [(set_attr "op_type" "RR")])
2767 (define_insn "truncdfsf2_ibm"
2768 [(set (match_operand:SF 0 "register_operand" "=f,f")
2769 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,m")))]
2770 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2774 [(set_attr "op_type" "RR,RX")])
2777 ; extendsfdf2 instruction pattern(s).
2780 (define_expand "extendsfdf2"
2781 [(set (match_operand:DF 0 "register_operand" "")
2782 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2786 if (TARGET_IBM_FLOAT)
2788 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
2793 (define_insn "extendsfdf2_ieee"
2794 [(set (match_operand:DF 0 "register_operand" "=f,f")
2795 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))]
2796 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2800 [(set_attr "op_type" "RRE,RXE")])
2802 (define_insn "extendsfdf2_ibm"
2803 [(set (match_operand:DF 0 "register_operand" "=f,f")
2804 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))
2805 (clobber (reg:CC 33))]
2806 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2808 sdr\\t%0,%0\;ler\\t%0,%1
2809 sdr\\t%0,%0\;le\\t%0,%1"
2810 [(set_attr "op_type" "RRE,RXE")])
2814 ;; ARITHMETRIC OPERATIONS
2816 ; arithmetric operations set the ConditionCode,
2817 ; because of unpredictable Bits in Register for Halfword and Byte
2818 ; the ConditionCode can be set wrong in operations for Halfword and Byte
2821 ;;- Add instructions.
2825 ; adddi3 instruction pattern(s).
2828 (define_insn "addaddr_esame"
2829 [(set (match_operand:DI 0 "register_operand" "=a,a")
2830 (plus:DI (match_operand:DI 1 "register_operand" "%a,a")
2831 (match_operand:DI 2 "nonmemory_operand" "J,a")))]
2832 "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
2833 (REGNO (operands[1]) == BASE_REGISTER)) &&
2834 (GET_CODE (operands[2]) == REG ||
2835 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
2839 [(set_attr "op_type" "RX")
2840 (set_attr "atype" "mem")
2841 (set_attr "type" "la")])
2843 (define_insn "adddi3_64"
2844 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2845 (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
2846 (match_operand:DI 2 "general_operand" "d,K,m") ) )
2847 (clobber (reg:CC 33))]
2853 [(set_attr "op_type" "RRE,RI,RXE")
2854 (set_attr "atype" "reg,reg,mem")
2855 (set_attr "type" "set")])
2858 ; For weakness of reload, need (set (reg x) (plus (reg y) (reg x)))
2861 (define_insn "adddi3_inv_64"
2862 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2863 (plus:DI (match_operand:DI 1 "general_operand" "%d,K,m")
2864 (match_operand:DI 2 "register_operand" "0,0,0") ) )
2865 (clobber (reg:CC 33))]
2871 [(set_attr "op_type" "RRE,RI,RXE")
2872 (set_attr "atype" "reg,reg,mem")
2873 (set_attr "type" "set")])
2875 (define_insn "adddi3_31"
2876 [(set (match_operand:DI 0 "register_operand" "=d,d")
2877 (plus:DI (match_operand:DI 1 "register_operand" "0,0")
2878 (match_operand:DI 2 "general_operand" "d,m") ) )
2879 (clobber (reg:CC 33))]
2883 switch(which_alternative)
2885 case 0: /* d <- d */
2886 output_asm_insn (\"ar\\t%0,%2\", operands);
2887 output_asm_insn (\"alr\\t%N0,%N2\", operands);
2890 case 1: /* d <- m */
2891 output_asm_insn (\"a\\t%0,%2\", operands);
2892 output_asm_insn (\"al\\t%N0,%N2\", operands);
2896 output_asm_insn (\"brc\\t12,.+8\", operands);
2897 return \"ahi\\t%0,1\";
2899 [(set_attr "op_type" "NN,NN")
2900 (set_attr "atype" "reg,mem")
2901 (set_attr "length" "12,16")])
2903 (define_expand "adddi3"
2904 [(set (match_operand:DI 0 "register_operand" "")
2905 (plus:DI (match_operand:DI 1 "register_operand" "")
2906 (match_operand:DI 2 "general_operand" "")))]
2911 emit_insn(gen_adddi3_64 (operands[0],operands[1],operands[2]));
2913 emit_insn(gen_adddi3_31 (operands[0],operands[1],operands[2]));
2917 (define_insn "reload_load_address"
2918 [(set (match_operand:DI 0 "register_operand" "=a")
2919 (match_operand:QI 1 "address_operand" "p"))]
2922 [(set_attr "op_type" "RX")
2923 (set_attr "atype" "mem")
2924 (set_attr "type" "la")])
2926 (define_insn "*reload_load_address_reg_0"
2927 [(set (match_operand:DI 0 "register_operand" "=d")
2928 (plus:DI (match_operand:DI 1 "register_operand" "%0")
2929 (match_operand:DI 2 "register_operand" "d")))]
2932 [(set_attr "op_type" "RIE")
2933 (set_attr "atype" "reg")
2934 (set_attr "type" "set")])
2936 (define_insn "*reload_la_64"
2937 [(set (match_operand:DI 0 "register_operand" "=d")
2938 (plus:DI (match_operand:DI 1 "general_operand" "g")
2939 (match_operand:DI 2 "general_operand" "g")))]
2940 "TARGET_64BIT && reload_in_progress"
2944 [(set (match_operand:DI 0 "register_operand" "")
2945 (plus:DI (match_operand:DI 1 "general_operand" "")
2946 (match_operand:DI 2 "register_operand" "")))]
2947 "TARGET_64BIT && reload_completed
2948 && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode)
2949 && !rtx_equal_p (operands[0], operands[1])
2950 && !rtx_equal_p (operands[0], operands[2])"
2951 [(set (match_dup 0) (match_dup 1))
2952 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
2956 [(set (match_operand:DI 0 "register_operand" "")
2957 (plus:DI (match_operand:DI 1 "register_operand" "")
2958 (match_operand:DI 2 "general_operand" "")))]
2959 "TARGET_64BIT && reload_completed
2960 && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode)
2961 && !rtx_equal_p (operands[0], operands[1])
2962 && !rtx_equal_p (operands[0], operands[2])"
2963 [(set (match_dup 0) (match_dup 2))
2964 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))]
2968 ; addsi3 instruction pattern(s).
2970 ; The following insn is used when it is known that operand one is the stack pointer,
2971 ; and operand two is small enough to fit in the displacement field
2972 ; In this case, the result will be a address
2975 (define_insn "addaddr"
2976 [(set (match_operand:SI 0 "register_operand" "=d,d")
2977 (plus:SI (match_operand:SI 1 "register_operand" "%a,a")
2978 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
2979 "(((REGNO (operands[1]) == STACK_POINTER_REGNUM ) ||
2980 (REGNO (operands[1]) == BASE_REGISTER)) &&
2981 (GET_CODE (operands[2]) == REG ||
2982 CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))"
2986 [(set_attr "op_type" "RX")
2987 (set_attr "atype" "mem")
2988 (set_attr "type" "la")])
2990 (define_insn "*addaddr_picR"
2991 [(set (match_operand:SI 0 "register_operand" "=d")
2992 (plus:SI (match_operand:SI 1 "register_operand" "a")
2993 (unspec:SI [(match_operand:SI 2 "register_operand" "a")] 101)))]
2996 [(set_attr "op_type" "RX")
2997 (set_attr "atype" "mem")
2998 (set_attr "type" "la")])
3000 (define_insn "*addaddr_picL"
3001 [(set (match_operand:SI 0 "register_operand" "=d")
3002 (plus:SI (unspec:SI [(match_operand:SI 2 "register_operand" "a")] 101)
3003 (match_operand:SI 1 "register_operand" "a")))]
3006 [(set_attr "op_type" "RX")
3007 (set_attr "atype" "mem")
3008 (set_attr "type" "la")])
3010 (define_insn "*addaddr_picN"
3011 [(set (match_operand:SI 0 "register_operand" "=d")
3012 (unspec:SI [(match_operand:SI 1 "register_operand" "a")] 101))]
3015 [(set_attr "op_type" "RX")
3016 (set_attr "atype" "mem")
3017 (set_attr "type" "la")])
3019 (define_insn "*addsi3_cc"
3021 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3022 (match_operand:SI 2 "general_operand" "d,K,m"))
3024 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3025 (plus:SI (match_dup 1) (match_dup 2)))]
3026 "s390_match_ccmode(insn, CCSmode)"
3031 [(set_attr "op_type" "RR,RI,RX")
3032 (set_attr "atype" "reg,reg,mem")
3033 (set_attr "type" "set")])
3035 (define_insn "*addsi3_cconly"
3037 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3038 (match_operand:SI 2 "general_operand" "d,K,m"))
3040 (clobber (match_scratch:SI 0 "=d,d,d"))]
3041 "s390_match_ccmode(insn, CCSmode)"
3046 [(set_attr "op_type" "RR,RI,RX")
3047 (set_attr "atype" "reg,reg,mem")
3048 (set_attr "type" "set")])
3050 (define_insn "*addsi3_cconly2"
3052 (compare (match_operand:SI 1 "register_operand" "%0,0,0")
3053 (neg:SI (match_operand:SI 2 "general_operand" "d,K,m"))))
3054 (clobber (match_scratch:SI 0 "=d,d,d"))]
3055 "s390_match_ccmode(insn, CCSmode)"
3060 [(set_attr "op_type" "RR,RI,RX")
3061 (set_attr "atype" "reg,reg,mem")
3062 (set_attr "type" "set")])
3064 (define_insn "addsi3"
3065 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3066 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3067 (match_operand:SI 2 "general_operand" "d,K,m")))
3068 (clobber (reg:CC 33))]
3074 [(set_attr "op_type" "RR,RI,RX")
3075 (set_attr "atype" "reg,reg,mem")
3076 (set_attr "type" "set")])
3078 (define_insn "do_la"
3079 [(set (match_operand:SI 0 "register_operand" "=a")
3080 (match_operand:QI 1 "address_operand" "p"))]
3083 [(set_attr "op_type" "RX")
3084 (set_attr "atype" "mem")
3085 (set_attr "type" "la")])
3087 (define_insn "*do_la_reg_0"
3088 [(set (match_operand:SI 0 "register_operand" "=d")
3089 (plus:SI (match_operand:SI 1 "register_operand" "%0")
3090 (match_operand:SI 2 "register_operand" "d")))]
3093 [(set_attr "op_type" "RSI")
3094 (set_attr "atype" "reg")
3095 (set_attr "type" "set")])
3097 (define_insn "*reload_la_31"
3098 [(set (match_operand:SI 0 "register_operand" "=d")
3099 (plus:SI (match_operand:SI 1 "general_operand" "g")
3100 (match_operand:SI 2 "general_operand" "g")))]
3101 "reload_in_progress"
3105 [(set (match_operand:SI 0 "register_operand" "")
3106 (plus:SI (match_operand:SI 1 "general_operand" "")
3107 (match_operand:SI 2 "register_operand" "")))]
3109 && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode)
3110 && !rtx_equal_p (operands[0], operands[1])
3111 && !rtx_equal_p (operands[0], operands[2])"
3112 [(set (match_dup 0) (match_dup 1))
3113 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3117 [(set (match_operand:SI 0 "register_operand" "")
3118 (plus:SI (match_operand:SI 1 "register_operand" "")
3119 (match_operand:SI 2 "general_operand" "")))]
3121 && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode)
3122 && !rtx_equal_p (operands[0], operands[1])
3123 && !rtx_equal_p (operands[0], operands[2])"
3124 [(set (match_dup 0) (match_dup 2))
3125 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
3128 (define_insn "addsi_64"
3129 [(set (match_operand:SI 0 "register_operand" "=d,d")
3130 (plus:SI (match_operand:SI 1 "register_operand" "%a,a")
3131 (match_operand:SI 2 "nonmemory_operand" "J,a")))]
3136 [(set_attr "op_type" "RX")
3137 (set_attr "atype" "mem")
3138 (set_attr "type" "la")])
3141 ; addhi3 instruction pattern(s).
3144 (define_insn "addhi3"
3145 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3146 (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0")
3147 (match_operand:HI 2 "general_operand" "d,K,m")))
3148 (clobber (reg:CC 33))]
3154 [(set_attr "op_type" "RR,RI,RX")
3155 (set_attr "atype" "reg,reg,mem")])
3159 ; addqi3 instruction pattern(s).
3162 (define_insn "addqi3"
3163 [(set (match_operand:QI 0 "register_operand" "=d,d")
3164 (plus:QI (match_operand:QI 1 "register_operand" "%0,0")
3165 (match_operand:QI 2 "general_operand" "a,n")))
3166 (clobber (reg:CC 33))]
3171 [(set_attr "op_type" "RX,RX")
3172 (set_attr "atype" "reg,mem")])
3176 ; adddf3 instruction pattern(s).
3179 (define_expand "adddf3"
3181 [(set (match_operand:DF 0 "register_operand" "=f,f")
3182 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3183 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3184 (clobber (reg:CC 33))])]
3188 (define_insn "*adddf3"
3189 [(set (match_operand:DF 0 "register_operand" "=f,f")
3190 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3191 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3192 (clobber (reg:CC 33))]
3193 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3197 [(set_attr "op_type" "RR,RX")
3198 (set_attr "atype" "reg,mem")])
3200 (define_insn "*adddf3_ibm"
3201 [(set (match_operand:DF 0 "register_operand" "=f,f")
3202 (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
3203 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3204 (clobber (reg:CC 33))]
3205 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3209 [(set_attr "op_type" "RR,RX")
3210 (set_attr "atype" "reg,mem")])
3213 ; addsf3 instruction pattern(s).
3216 (define_expand "addsf3"
3218 [(set (match_operand:SF 0 "register_operand" "=f,f")
3219 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3220 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3221 (clobber (reg:CC 33))])]
3225 (define_insn "*addsf3"
3226 [(set (match_operand:SF 0 "register_operand" "=f,f")
3227 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3228 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3229 (clobber (reg:CC 33))]
3230 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3234 [(set_attr "op_type" "RR,RX")
3235 (set_attr "atype" "reg,mem")])
3237 (define_insn "*addsf3"
3238 [(set (match_operand:SF 0 "register_operand" "=f,f")
3239 (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
3240 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3241 (clobber (reg:CC 33))]
3242 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3246 [(set_attr "op_type" "RR,RX")
3247 (set_attr "atype" "reg,mem")])
3251 ;;- Subtract instructions.
3255 ; subdi3 instruction pattern(s).
3258 (define_insn "*subdi3_64"
3259 [(set (match_operand:DI 0 "register_operand" "=d,d")
3260 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3261 (match_operand:DI 2 "general_operand" "d,m") ) )
3262 (clobber (reg:CC 33))]
3267 [(set_attr "op_type" "RRE,RRE")
3268 (set_attr "atype" "reg,mem")
3269 (set_attr "type" "set")])
3271 (define_insn "subdi3"
3272 [(set (match_operand:DI 0 "register_operand" "=d,d")
3273 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3274 (match_operand:DI 2 "nonimmediate_operand" "d,m")))
3275 (clobber (reg:CC 33))]
3279 switch (which_alternative)
3281 case 0: /* d <- d */
3282 output_asm_insn (\"sr\\t%0,%2\", operands);
3283 output_asm_insn (\"slr\\t%N0,%N2\", operands);
3285 case 1: /* d <- m */
3286 output_asm_insn (\"s\\t%0,%2\", operands);
3287 output_asm_insn (\"sl\\t%N0,%N2\", operands);
3291 output_asm_insn (\"brc\\t11,.+8\", operands);
3292 return \"ahi\\t%0,-1\";
3294 [(set_attr "op_type" "NN,NN")
3295 (set_attr "atype" "reg,mem")
3296 (set_attr "length" "12,16")])
3299 ; subsi3 instruction pattern(s).
3302 (define_insn "*subsi3_cc"
3304 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3305 (match_operand:SI 2 "general_operand" "d,m"))
3307 (set (match_operand:SI 0 "register_operand" "=d,d")
3308 (minus:SI (match_dup 1) (match_dup 2)))]
3309 "s390_match_ccmode(insn, CCSmode)"
3313 [(set_attr "op_type" "RR,RX")
3314 (set_attr "atype" "reg,mem")
3315 (set_attr "type" "set")])
3317 (define_insn "*subsi3_cconly"
3319 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3320 (match_operand:SI 2 "general_operand" "d,m"))
3322 (clobber (match_scratch:SI 0 "=d,d"))]
3323 "s390_match_ccmode(insn, CCSmode)"
3327 [(set_attr "op_type" "RR,RX")
3328 (set_attr "atype" "reg,mem")
3329 (set_attr "type" "set")])
3331 (define_insn "subsi3"
3332 [(set (match_operand:SI 0 "register_operand" "=d,d")
3333 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
3334 (match_operand:SI 2 "general_operand" "d,m")))
3335 (clobber (reg:CC 33))]
3340 [(set_attr "op_type" "RR,RX")
3341 (set_attr "atype" "reg,mem")
3342 (set_attr "type" "set")])
3345 ; subhi3 instruction pattern(s).
3348 (define_insn "subhi3"
3349 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
3350 (minus:HI (match_operand:HI 1 "register_operand" "0,0,0")
3351 (match_operand:HI 2 "nonimmediate_operand" "d,K,m")))
3352 (clobber (reg:CC 33))]
3358 [(set_attr "op_type" "RR,RI,RX")
3359 (set_attr "atype" "reg,reg,mem")])
3362 ; subqi3 instruction pattern(s).
3365 (define_insn "subqi3"
3366 [(set (match_operand:QI 0 "register_operand" "=d")
3367 (minus:QI (match_operand:QI 1 "register_operand" "0")
3368 (match_operand:QI 2 "register_operand" "d")))
3369 (clobber (reg:CC 33))]
3372 [(set_attr "op_type" "RR")])
3375 ; subdf3 instruction pattern(s).
3378 (define_expand "subdf3"
3380 [(set (match_operand:DF 0 "register_operand" "=f,f")
3381 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3382 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3383 (clobber (reg:CC 33))])]
3387 (define_insn "*subdf3"
3388 [(set (match_operand:DF 0 "register_operand" "=f,f")
3389 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3390 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3391 (clobber (reg:CC 33))]
3392 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3396 [(set_attr "op_type" "RR,RX")
3397 (set_attr "atype" "reg,mem")])
3399 (define_insn "*subdf3_ibm"
3400 [(set (match_operand:DF 0 "register_operand" "=f,f")
3401 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
3402 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3403 (clobber (reg:CC 33))]
3404 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3408 [(set_attr "op_type" "RR,RX")
3409 (set_attr "atype" "reg,mem")])
3412 ; subsf3 instruction pattern(s).
3415 (define_expand "subsf3"
3417 [(set (match_operand:SF 0 "register_operand" "=f,f")
3418 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3419 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3420 (clobber (reg:CC 33))])]
3424 (define_insn "*subsf3"
3425 [(set (match_operand:SF 0 "register_operand" "=f,f")
3426 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3427 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3428 (clobber (reg:CC 33))]
3429 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3433 [(set_attr "op_type" "RR,RX")
3434 (set_attr "atype" "reg,mem")])
3436 (define_insn "*subsf3_ibm"
3437 [(set (match_operand:SF 0 "register_operand" "=f,f")
3438 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
3439 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3440 (clobber (reg:CC 33))]
3441 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3445 [(set_attr "op_type" "RR,RX")
3446 (set_attr "atype" "reg,mem")])
3450 ;;- Multiply instructions.
3453 (define_expand "muldi3"
3455 [(set (match_operand:DI 0 "register_operand" "")
3456 (mult:DI (match_operand:DI 1 "register_operand" "")
3457 (match_operand:DI 2 "register_operand" "")))
3458 (clobber (reg:CC 33))])]
3464 rtx label1 = gen_label_rtx ();
3465 rtx label2 = gen_label_rtx ();
3466 rtx op0_0 = operand_subword (operands[0], 0 ,1, DImode);
3467 rtx op0_1 = operand_subword (operands[0], 1 ,1, DImode);
3468 rtx temp1_0 = gen_reg_rtx (SImode);
3469 rtx temp1_1 = gen_reg_rtx (SImode);
3470 rtx temp2_0 = gen_reg_rtx (SImode);
3471 rtx temp2_1 = gen_reg_rtx (SImode);
3473 emit_move_insn (temp1_0, operand_subword (operands[1], 0 ,1, DImode));
3474 emit_move_insn (temp1_1, operand_subword (operands[1], 1 ,1, DImode));
3475 emit_move_insn (temp2_0, operand_subword (operands[2], 0 ,1, DImode));
3476 emit_move_insn (temp2_1, operand_subword (operands[2], 1 ,1, DImode));
3477 emit_move_insn (op0_1, temp1_1);
3478 emit_insn (gen_mulsi_6432 (operands[0], operands[0], temp2_1));
3480 emit_insn (gen_cmpsi (temp1_1, const0_rtx));
3481 emit_jump_insn (gen_bge (label1));
3482 emit_insn (gen_addsi3 (op0_0, op0_0, temp2_1));
3483 emit_label (label1);
3484 emit_insn (gen_cmpsi (temp2_1, const0_rtx));
3485 emit_jump_insn (gen_bge (label2));
3486 emit_insn (gen_addsi3 (op0_0, op0_0, temp1_1));
3487 emit_label (label2);
3489 emit_insn (gen_mulsi3 (temp2_1, temp2_1, temp1_0));
3490 emit_insn (gen_addsi3 (op0_0, op0_0, temp2_1));
3492 emit_insn (gen_mulsi3 (temp1_1, temp1_1, temp2_0));
3493 emit_insn (gen_addsi3 (op0_0, op0_0, temp1_1));
3499 (define_insn "*muldi3_64"
3500 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3501 (mult:DI (match_operand:DI 1 "register_operand" "%0,0,0")
3502 (match_operand:DI 2 "general_operand" "d,K,m")))
3503 (clobber (reg:CC 33))]
3509 [(set_attr "op_type" "RRE,RI,RX")
3510 (set_attr "cycle" "n")
3511 (set_attr "atype" "reg,reg,mem")
3512 (set_attr "type" "set")])
3515 ; mulsi3 instruction pattern(s).
3518 (define_insn "mulsi3"
3519 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
3520 (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0")
3521 (match_operand:SI 2 "general_operand" "d,K,m")))
3522 (clobber (reg:CC 33))]
3528 [(set_attr "op_type" "RRE,RI,RX")
3529 (set_attr "cycle" "n")
3530 (set_attr "atype" "reg,reg,mem")
3531 (set_attr "type" "set")])
3533 (define_insn "mulsi_6432"
3534 [(set (match_operand:DI 0 "register_operand" "=d,d")
3535 (mult:DI (sign_extend:DI
3536 (subreg:SI (match_operand:DI 1 "register_operand" "0,0") 4))
3538 (match_operand:SI 2 "general_operand" "d,m"))))
3539 (clobber (reg:CC 33))]
3544 [(set_attr "op_type" "RR,RX")
3545 (set_attr "cycle" "n")
3546 (set_attr "atype" "reg,mem")
3547 (set_attr "type" "set")])
3551 ; muldf3 instruction pattern(s).
3554 (define_expand "muldf3"
3556 [(set (match_operand:DF 0 "register_operand" "=f,f")
3557 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3558 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3559 (clobber (reg:CC 33))])]
3563 (define_insn "*muldf3"
3564 [(set (match_operand:DF 0 "register_operand" "=f,f")
3565 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3566 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3567 (clobber (reg:CC 33))]
3568 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3572 [(set_attr "op_type" "RR,RX")
3573 (set_attr "cycle" "n")
3574 (set_attr "atype" "reg,mem")])
3576 (define_insn "*muldf3_ibm"
3577 [(set (match_operand:DF 0 "register_operand" "=f,f")
3578 (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
3579 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3580 (clobber (reg:CC 33))]
3581 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3585 [(set_attr "op_type" "RR,RX")
3586 (set_attr "cycle" "n")
3587 (set_attr "atype" "reg,mem")])
3590 ; mulsf3 instruction pattern(s).
3593 (define_expand "mulsf3"
3595 [(set (match_operand:SF 0 "register_operand" "=f,f")
3596 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3597 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3598 (clobber (reg:CC 33))])]
3602 (define_insn "*mulsf3"
3603 [(set (match_operand:SF 0 "register_operand" "=f,f")
3604 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3605 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3606 (clobber (reg:CC 33))]
3607 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3611 [(set_attr "op_type" "RR,RX")
3612 (set_attr "cycle" "n")
3613 (set_attr "atype" "reg,mem")])
3615 (define_insn "*mulsf3_ibm"
3616 [(set (match_operand:SF 0 "register_operand" "=f,f")
3617 (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
3618 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
3619 (clobber (reg:CC 33))]
3620 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3624 [(set_attr "op_type" "RR,RX")
3625 (set_attr "cycle" "n")
3626 (set_attr "atype" "reg,mem")])
3630 ;;- Divide and modulo instructions.
3634 ; divdi3 and moddi3 instruction pattern(s).
3637 (define_expand "divdi3"
3638 [(set (match_operand:DI 0 "register_operand" "=d")
3639 (div:DI (match_operand:DI 1 "register_operand" "d")
3640 (match_operand:DI 2 "general_operand" "")))]
3644 rtx op3 = gen_reg_rtx (TImode);
3646 if (CONSTANT_P (operands[2]))
3647 operands[2] = force_const_mem (DImode, operands[2]);
3649 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 0), const0_rtx);
3650 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 8), operands[1]);
3651 emit_insn (gen_divmodtidi3 (op3, op3, operands[2]));
3652 emit_move_insn (operands[0], gen_rtx_SUBREG (DImode, op3, 8));
3656 (define_expand "moddi3"
3657 [(set (match_operand:DI 0 "register_operand" "=d")
3658 (mod:DI (match_operand:DI 1 "register_operand" "d")
3659 (match_operand:DI 2 "general_operand" "")))]
3663 rtx op3 = gen_reg_rtx (TImode);
3665 if (CONSTANT_P (operands[2]))
3666 operands[2] = force_const_mem (DImode, operands[2]);
3668 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 0), const0_rtx);
3669 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 8), operands[1]);
3670 emit_insn (gen_divmodtidi3 (op3, op3, operands[2]));
3671 emit_move_insn (operands[0], gen_rtx_SUBREG (DImode, op3, 0));
3675 (define_insn "divmodtidi3"
3676 [(set (subreg:DI (match_operand:TI 0 "register_operand" "=d,d") 0)
3678 (mod:TI (match_operand:TI 1 "register_operand" "0,0")
3680 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3681 (set (subreg:DI (match_dup 0) 8)
3682 (truncate:DI (div:TI (match_dup 1) (sign_extend:TI (match_dup 2)))))
3683 (clobber (reg:CC 33))]
3688 [(set_attr "op_type" "RRE,RXE")
3689 (set_attr "cycle" "n")
3690 (set_attr "atype" "reg,mem")])
3693 ; udivdi3 and umoddi3 instruction pattern(s).
3696 (define_expand "udivdi3"
3697 [(set (match_operand:DI 0 "register_operand" "=d")
3698 (udiv:DI (match_operand:DI 1 "register_operand" "d")
3699 (match_operand:DI 2 "general_operand" "")))]
3703 rtx op3 = gen_reg_rtx(TImode);
3705 if (CONSTANT_P (operands[2]))
3706 operands[2] = force_const_mem (DImode, operands[2]);
3708 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 0), const0_rtx);
3709 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 8), operands[1]);
3710 emit_insn (gen_udivmodtidi3 (op3, op3, operands[2]));
3711 emit_move_insn (operands[0], gen_rtx_SUBREG (DImode, op3, 8));
3715 (define_expand "umoddi3"
3716 [(set (match_operand:DI 0 "register_operand" "=d")
3717 (umod:DI (match_operand:DI 1 "register_operand" "d")
3718 (match_operand:DI 2 "general_operand" "")))]
3722 rtx op3 = gen_reg_rtx (TImode);
3724 if (CONSTANT_P (operands[2]))
3725 operands[2] = force_const_mem (DImode, operands[2]);
3727 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 0), const0_rtx);
3728 emit_move_insn (gen_rtx_SUBREG (DImode, op3, 8), operands[1]);
3729 emit_insn (gen_udivmodtidi3 (op3, op3, operands[2]));
3730 emit_move_insn (operands[0], gen_rtx_SUBREG (DImode, op3, 0));
3734 (define_insn "udivmodtidi3"
3735 [(set (subreg:DI (match_operand:TI 0 "register_operand" "=d,d") 0)
3737 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
3739 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
3740 (set (subreg:DI (match_dup 0) 8)
3741 (truncate:DI (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))
3742 (clobber (reg:CC 33))]
3747 [(set_attr "op_type" "RRE,RXE")
3748 (set_attr "cycle" "n")
3749 (set_attr "atype" "reg,mem")])
3752 ; divsi3 and modsi3 instruction pattern(s).
3755 (define_expand "divsi3"
3756 [(set (match_operand:SI 0 "register_operand" "=d")
3757 (div:SI (match_operand:SI 1 "register_operand" "d")
3758 (match_operand:SI 2 "nonimmediate_operand" "")))]
3762 rtx tmp = gen_reg_rtx (DImode);
3764 if (CONSTANT_P (operands[2]))
3765 operands[2] = force_const_mem (SImode, operands[2]);
3767 operands[2] = force_reg (SImode, operands[2]);
3769 emit_insn (gen_rtx_CLOBBER (SImode, gen_rtx_SUBREG (SImode, tmp, 4)));
3770 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), operands[1]);
3771 emit_insn (gen_ashrdi3 (tmp, tmp, GEN_INT (32)));
3772 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3773 emit_move_insn (operands[0], gen_rtx_SUBREG (SImode, tmp, 4));
3777 (define_expand "modsi3"
3778 [(set (match_operand:SI 0 "register_operand" "=d")
3779 (mod:SI (match_operand:SI 1 "register_operand" "d")
3780 (match_operand:SI 2 "nonimmediate_operand" "")))]
3784 rtx tmp = gen_reg_rtx (DImode);
3786 if (CONSTANT_P (operands[2]))
3787 operands[2] = force_const_mem (SImode, operands[2]);
3789 operands[2] = force_reg (SImode, operands[2]);
3791 emit_insn (gen_rtx_CLOBBER (SImode, gen_rtx_SUBREG (SImode, tmp, 4)));
3792 emit_insn (gen_movsi (gen_rtx_SUBREG (SImode, tmp, 0), operands[1]));
3793 emit_insn (gen_ashrdi3 (tmp, tmp, GEN_INT (32)));
3794 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3795 emit_move_insn (operands[0], gen_rtx_SUBREG (SImode, tmp, 0));
3799 (define_insn "divmoddisi3"
3800 [(set (subreg:SI (match_operand:DI 0 "register_operand" "=d,d") 0)
3802 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
3804 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
3805 (set (subreg:SI (match_dup 0) 4)
3806 (truncate:SI (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))
3807 (clobber (reg:CC 33))]
3812 [(set_attr "op_type" "RR,RX")
3813 (set_attr "cycle" "n")
3814 (set_attr "atype" "reg,mem")])
3817 ; udivsi3 and umodsi3 instruction pattern(s).
3820 (define_expand "udivsi3"
3821 [(set (match_operand:SI 0 "register_operand" "=d")
3822 (udiv:SI (match_operand:SI 1 "general_operand" "")
3823 (match_operand:SI 2 "general_operand" "")))]
3827 rtx dr_0, dr_1, tmp;
3829 tmp = gen_reg_rtx (DImode);
3830 dr_0 = gen_rtx_SUBREG (SImode, tmp, 0);
3831 dr_1 = gen_rtx_SUBREG (SImode, tmp, 4);
3833 if (CONSTANT_P (operands[2]))
3835 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
3837 rtx label1 = gen_label_rtx ();
3839 emit_move_insn (dr_0, operands[1]);
3840 emit_move_insn (dr_1, const0_rtx);
3841 emit_insn (gen_cmpsi (dr_0, operands[2]));
3842 emit_jump_insn (gen_bltu (label1));
3843 emit_move_insn (dr_1, const1_rtx);
3844 emit_label (label1);
3848 operands[2] = force_const_mem (SImode, operands[2]);
3849 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), const0_rtx);
3850 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 4), operands[1]);
3851 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3856 rtx label1 = gen_label_rtx ();
3857 rtx label2 = gen_label_rtx ();
3858 rtx label3 = gen_label_rtx ();
3860 operands[1] = force_reg (SImode, operands[1]);
3861 operands[2] = force_reg (SImode, operands[2]);
3863 emit_move_insn (dr_1, const0_rtx);
3864 emit_insn (gen_cmpsi (operands[2], operands[1]));
3865 emit_jump_insn (gen_bgtu (label3));
3866 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3867 emit_jump_insn (gen_blt (label2));
3868 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3869 emit_jump_insn (gen_beq (label1));
3870 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), const0_rtx);
3871 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 4), operands[1]);
3872 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3874 emit_label (label1);
3875 emit_move_insn (dr_1, operands[1]);
3877 emit_label (label2);
3878 emit_move_insn (dr_1, const1_rtx);
3879 emit_label (label3);
3882 emit_move_insn (operands[0], dr_1);
3886 (define_expand "umodsi3"
3887 [(set (match_operand:SI 0 "register_operand" "=d")
3888 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
3889 (match_operand:SI 2 "nonimmediate_operand" "")))]
3893 rtx dr_0, dr_1, tmp;
3895 tmp = gen_reg_rtx (DImode);
3896 dr_0 = gen_rtx_SUBREG (SImode, tmp, 0);
3897 dr_1 = gen_rtx_SUBREG (SImode, tmp, 4);
3899 if (CONSTANT_P (operands[2]))
3901 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
3903 rtx label1 = gen_label_rtx ();
3905 emit_move_insn (dr_0, operands[1]);
3906 emit_insn (gen_cmpsi (dr_0, operands[2]));
3907 emit_jump_insn (gen_bltu (label1));
3908 emit_insn (gen_abssi2 (dr_0, operands[2]));
3909 emit_insn (gen_addsi3 (dr_0,dr_0, operands[1]));
3910 emit_label (label1);
3914 operands[2] = force_const_mem (SImode, operands[2]);
3915 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), const0_rtx);
3916 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 4), operands[1]);
3917 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3922 rtx label1 = gen_label_rtx ();
3923 rtx label2 = gen_label_rtx ();
3924 rtx label3 = gen_label_rtx ();
3926 operands[1] = force_reg (SImode, operands[1]);
3927 operands[2] = force_reg (SImode, operands[2]);
3929 emit_move_insn(dr_0, operands[1]);
3930 emit_insn (gen_cmpsi (operands[2], dr_0));
3931 emit_jump_insn (gen_bgtu (label3));
3932 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3933 emit_jump_insn (gen_blt (label2));
3934 emit_insn (gen_cmpsi (operands[2], const1_rtx));
3935 emit_jump_insn (gen_beq (label1));
3936 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 0), const0_rtx);
3937 emit_move_insn (gen_rtx_SUBREG (SImode, tmp, 4), operands[1]);
3938 emit_insn (gen_divmoddisi3 (tmp, tmp, operands[2]));
3940 emit_label (label1);
3941 emit_move_insn (dr_0, const0_rtx);
3943 emit_label (label2);
3944 emit_insn (gen_subsi3 (dr_0, dr_0, operands[2]));
3945 emit_label (label3);
3948 emit_move_insn (operands[0], dr_0);
3953 ; divdf3 instruction pattern(s).
3956 (define_expand "divdf3"
3958 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
3959 (div:DF (match_operand:DF 1 "general_operand" "0,0")
3960 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3961 (clobber (reg:CC 33))])]
3965 (define_insn "*divdf3"
3966 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
3967 (div:DF (match_operand:DF 1 "general_operand" "0,0")
3968 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3969 (clobber (reg:CC 33))]
3970 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3974 [(set_attr "op_type" "RR,RX")
3975 (set_attr "cycle" "n")
3976 (set_attr "atype" "reg,mem")])
3978 (define_insn "*divdf3_ibm"
3979 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
3980 (div:DF (match_operand:DF 1 "general_operand" "0,0")
3981 (match_operand:DF 2 "nonimmediate_operand" "f,m")))
3982 (clobber (reg:CC 33))]
3983 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3987 [(set_attr "op_type" "RR,RX")
3988 (set_attr "cycle" "n")
3989 (set_attr "atype" "reg,mem")])
3992 ; divsf3 instruction pattern(s).
3995 (define_expand "divsf3"
3997 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f")
3998 (div:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
3999 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
4000 (clobber (reg:CC 33))])]
4004 (define_insn "*divsf3"
4005 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f")
4006 (div:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4007 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
4008 (clobber (reg:CC 33))]
4009 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4013 [(set_attr "op_type" "RR,RX")
4014 (set_attr "cycle" "n")
4015 (set_attr "atype" "reg,mem")])
4017 (define_insn "*divsf3"
4018 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f")
4019 (div:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4020 (match_operand:SF 2 "nonimmediate_operand" "f,m")))
4021 (clobber (reg:CC 33))]
4022 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4026 [(set_attr "op_type" "RR,RX")
4027 (set_attr "cycle" "n")
4028 (set_attr "atype" "reg,mem")])
4032 ;;- And instructions.
4036 ; anddi3 instruction pattern(s).
4039 (define_insn "*anddi3_cc"
4041 (compare (and:DI (match_operand:DI 1 "r_or_s_operand" "%0,0,0")
4042 (match_operand:DI 2 "r_or_s_operand" "d,m,Q"))
4044 (set (match_operand:DI 0 "r_or_s_operand" "=d,d,Q")
4045 (and:DI (match_dup 1) (match_dup 2)))]
4046 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4051 [(set_attr "op_type" "RR,RX,SS")
4052 (set_attr "atype" "reg,mem,mem")
4053 (set_attr "type" "set")])
4055 (define_insn "*anddi3_cconly"
4057 (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
4058 (match_operand:DI 2 "r_or_s_operand" "d,m"))
4060 (clobber (match_scratch:DI 0 "=d,d"))]
4061 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
4065 [(set_attr "op_type" "RR,RX")
4066 (set_attr "atype" "reg,mem")
4067 (set_attr "type" "set")])
4069 (define_insn "anddi3"
4070 [(set (match_operand:DI 0 "r_or_s_operand" "=d,d,Q")
4071 (and:DI (match_operand:DI 1 "r_or_s_operand" "%0,0,0")
4072 (match_operand:DI 2 "r_or_s_operand" "d,m,Q")))
4073 (clobber (reg:CC 33))]
4079 [(set_attr "op_type" "RR,RX,SS")
4080 (set_attr "atype" "reg,mem,mem")
4081 (set_attr "type" "set")])
4084 ; andsi3 instruction pattern(s).
4087 (define_insn "*andsi3_cc"
4089 (compare (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0,0")
4090 (match_operand:SI 2 "r_or_s_operand" "d,m,Q"))
4092 (set (match_operand:SI 0 "r_or_s_operand" "=d,d,Q")
4093 (and:SI (match_dup 1) (match_dup 2)))]
4094 "s390_match_ccmode(insn, CCTmode)"
4099 [(set_attr "op_type" "RR,RX,SS")
4100 (set_attr "atype" "reg,mem,mem")
4101 (set_attr "type" "set")])
4103 (define_insn "*andsi3_cconly"
4105 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
4106 (match_operand:SI 2 "r_or_s_operand" "d,m"))
4108 (clobber (match_scratch:SI 0 "=d,d"))]
4109 "s390_match_ccmode(insn, CCTmode)"
4113 [(set_attr "op_type" "RR,RX")
4114 (set_attr "atype" "reg,mem")
4115 (set_attr "type" "set")])
4117 (define_insn "andsi3"
4118 [(set (match_operand:SI 0 "r_or_s_operand" "=d,d,Q")
4119 (and:SI (match_operand:SI 1 "r_or_s_operand" "%0,0,0")
4120 (match_operand:SI 2 "r_or_s_operand" "d,m,Q")))
4121 (clobber (reg:CC 33))]
4127 [(set_attr "op_type" "RR,RX,SS")
4128 (set_attr "atype" "reg,mem,mem")
4129 (set_attr "type" "set")])
4132 ; andhi3 instruction pattern(s).
4135 (define_expand "andhi3"
4137 [(set (match_operand:HI 0 "r_or_s_operand" "")
4138 (and:HI (match_operand:HI 1 "r_or_s_operand" "")
4139 (match_operand:HI 2 "r_or_s_operand" "")))
4140 (clobber (reg:CC 33))])]
4144 if (CONSTANT_P (operands[2]))
4145 operands[2] = force_const_mem (HImode, operands[2]);
4148 (define_insn "*andhi3"
4149 [(set (match_operand:HI 0 "r_or_s_operand" "=d,Q")
4150 (and:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
4151 (match_operand:HI 2 "r_or_s_operand" "d,Q")))
4152 (clobber (reg:CC 33))]
4157 [(set_attr "op_type" "RR,SS")
4158 (set_attr "atype" "reg,mem")])
4161 ; andqi3 instruction pattern(s).
4164 (define_insn "andqi3"
4165 [(set (match_operand:QI 0 "r_or_s_operand" "=d,Q,Q")
4166 (and:QI (match_operand:QI 1 "r_or_s_operand" "%0,0,0")
4167 (match_operand:QI 2 "r_or_s_or_im8_operand" "d,n,Q")))
4168 (clobber (reg:CC 33))]
4174 [(set_attr "op_type" "RR,SI,SS")
4175 (set_attr "atype" "reg,mem,mem")])
4179 ;;- Bit set (inclusive or) instructions.
4183 ; iordi3 instruction pattern(s).
4186 (define_insn "iordi3"
4187 [(set (match_operand:DI 0 "r_or_s_operand" "=d,d,Q,d")
4188 (ior:DI (match_operand:DI 1 "r_or_s_operand" "%0,0,0,0")
4189 (match_operand:DI 2 "r_or_s_operand" "d,m,Q,L")))
4190 (clobber (reg:CC 33))]
4197 [(set_attr "op_type" "RRE,RXE,SS,RI")
4198 (set_attr "atype" "reg,mem,mem,reg")
4199 (set_attr "type" "set")])
4202 ; iorsi3 instruction pattern(s).
4205 (define_expand "iorsi3"
4207 [(set (match_operand:SI 0 "r_or_s_operand" "")
4208 (ior:SI (match_operand:SI 1 "r_or_s_operand" "")
4209 (match_operand:SI 2 "r_or_s_operand" "")))
4210 (clobber (reg:CC 33))])]
4214 if (CONSTANT_P (operands[2]))
4215 operands[2] = force_const_mem (SImode, operands[2]);
4218 (define_insn "*iorsi3"
4219 [(set (match_operand:SI 0 "r_or_s_operand" "=d,d,Q")
4220 (ior:SI (match_operand:SI 1 "r_or_s_operand" "%0,0,0")
4221 (match_operand:SI 2 "r_or_s_operand" "d,m,Q")))
4222 (clobber (reg:CC 33))]
4228 [(set_attr "op_type" "RR,RX,SS")
4229 (set_attr "atype" "reg,mem,mem")
4230 (set_attr "type" "set")])
4233 ; iorhi3 instruction pattern(s).
4236 (define_expand "iorhi3"
4238 [(set (match_operand:HI 0 "r_or_s_operand" "")
4239 (ior:HI (match_operand:HI 1 "r_or_s_operand" "")
4240 (match_operand:HI 2 "r_or_s_operand" "")))
4241 (clobber (reg:CC 33))])]
4245 if (CONSTANT_P (operands[2]))
4246 operands[2] = force_const_mem (HImode, operands[2]);
4249 (define_insn "*iorhi3"
4250 [(set (match_operand:HI 0 "r_or_s_operand" "=d,Q")
4251 (ior:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
4252 (match_operand:HI 2 "r_or_s_operand" "d,Q")))
4253 (clobber (reg:CC 33))]
4258 [(set_attr "op_type" "RR,SS")
4259 (set_attr "atype" "reg,mem")])
4262 ; iorqi3 instruction pattern(s).
4265 (define_insn "iorqi3"
4266 [(set (match_operand:QI 0 "r_or_s_operand" "=d,Q,Q")
4267 (ior:QI (match_operand:QI 1 "r_or_s_operand" "%0,0,0")
4268 (match_operand:QI 2 "r_or_s_or_im8_operand" "d,n,Q")))
4269 (clobber (reg:CC 33))]
4275 [(set_attr "op_type" "RR,SI,SS")
4276 (set_attr "atype" "reg,mem,mem")])
4280 ;;- Xor instructions.
4284 ; xordi3 instruction pattern(s).
4287 (define_insn "xordi3"
4288 [(set (match_operand:DI 0 "r_or_s_operand" "=d,d,Q")
4289 (xor:DI (match_operand:DI 1 "r_or_s_operand" "%0,0,0")
4290 (match_operand:DI 2 "r_or_s_operand" "d,m,Q")))
4291 (clobber (reg:CC 33))]
4297 [(set_attr "op_type" "RRE,RXE,SS")
4298 (set_attr "atype" "reg,mem,mem")
4299 (set_attr "type" "set")])
4302 ; xorsi3 instruction pattern(s).
4305 (define_expand "xorsi3"
4307 [(set (match_operand:SI 0 "r_or_s_operand" "")
4308 (xor:SI (match_operand:SI 1 "r_or_s_operand" "")
4309 (match_operand:SI 2 "r_or_s_operand" "")))
4310 (clobber (reg:CC 33))])]
4314 if (CONSTANT_P (operands[2]))
4315 operands[2] = force_const_mem (SImode, operands[2]);
4318 (define_insn "*xorsi3"
4319 [(set (match_operand:SI 0 "r_or_s_operand" "=d,d,Q")
4320 (xor:SI (match_operand:SI 1 "r_or_s_operand" "%0,0,0")
4321 (match_operand:SI 2 "r_or_s_operand" "d,m,Q")))
4322 (clobber (reg:CC 33))]
4328 [(set_attr "op_type" "RR,RX,SS")
4329 (set_attr "atype" "reg,mem,mem")
4330 (set_attr "type" "set")])
4333 ; xorhi3 instruction pattern(s).
4336 (define_expand "xorhi3"
4338 [(set (match_operand:HI 0 "r_or_s_operand" "")
4339 (xor:HI (match_operand:HI 1 "r_or_s_operand" "")
4340 (match_operand:HI 2 "r_or_s_operand" "")))
4341 (clobber (reg:CC 33))])]
4345 if (CONSTANT_P (operands[2]))
4346 operands[2] = force_const_mem (HImode, operands[2]);
4349 (define_insn "*xorhi3"
4350 [(set (match_operand:HI 0 "r_or_s_operand" "=d,Q")
4351 (xor:HI (match_operand:HI 1 "r_or_s_operand" "%0,0")
4352 (match_operand:HI 2 "r_or_s_operand" "d,Q")))
4353 (clobber (reg:CC 33))]
4358 [(set_attr "op_type" "RR,SS")
4359 (set_attr "atype" "reg,mem")])
4362 ; xorqi3 instruction pattern(s).
4365 (define_insn "xorqi3"
4366 [(set (match_operand:QI 0 "r_or_s_operand" "=d,Q,Q")
4367 (xor:QI (match_operand:QI 1 "r_or_s_operand" "0,0,0")
4368 (match_operand:QI 2 "r_or_s_or_im8_operand" "d,n,Q")))
4369 (clobber (reg:CC 33))]
4375 [(set_attr "op_type" "RR,SI,SS")
4376 (set_attr "atype" "reg,mem,mem")])
4380 ;;- Negate instructions.
4384 ; negdi2 instruction pattern(s).
4387 (define_expand "negdi2"
4389 [(set (match_operand:DI 0 "register_operand" "=d")
4390 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4391 (clobber (reg:CC 33))])]
4395 (define_insn "*negdi2_64"
4396 [(set (match_operand:DI 0 "register_operand" "=d")
4397 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4398 (clobber (reg:CC 33))]
4401 [(set_attr "op_type" "RR")
4402 (set_attr "type" "set")])
4404 (define_insn "*negdi2_31"
4405 [(set (match_operand:DI 0 "register_operand" "=d")
4406 (neg:DI (match_operand:DI 1 "register_operand" "d")))
4407 (clobber (reg:CC 33))]
4412 xop[0] = gen_label_rtx ();
4413 output_asm_insn (\"lcr\\t%0,%1\", operands);
4414 output_asm_insn (\"lcr\\t%N0,%N1\", operands);
4415 output_asm_insn (\"je\\t%l0\", xop);
4416 output_asm_insn (\"bctr\\t%0,0\", operands);
4417 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
4418 CODE_LABEL_NUMBER (xop[0]));
4421 [(set_attr "op_type" "NN")
4422 (set_attr "length" "10")])
4425 ; negsi2 instruction pattern(s).
4428 (define_insn "negsi2"
4429 [(set (match_operand:SI 0 "register_operand" "=d")
4430 (neg:SI (match_operand:SI 1 "register_operand" "d")))
4431 (clobber (reg:CC 33))]
4434 [(set_attr "op_type" "RR")
4435 (set_attr "type" "set")])
4438 ; negdf2 instruction pattern(s).
4441 (define_expand "negdf2"
4443 [(set (match_operand:DF 0 "register_operand" "=f")
4444 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4445 (clobber (reg:CC 33))])]
4449 (define_insn "*negdf2"
4450 [(set (match_operand:DF 0 "register_operand" "=f")
4451 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4452 (clobber (reg:CC 33))]
4453 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4455 [(set_attr "op_type" "RR")])
4457 (define_insn "*negdf2_ibm"
4458 [(set (match_operand:DF 0 "register_operand" "=f")
4459 (neg:DF (match_operand:DF 1 "register_operand" "f")))
4460 (clobber (reg:CC 33))]
4461 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4463 [(set_attr "op_type" "RR")])
4466 ; negsf2 instruction pattern(s).
4469 (define_expand "negsf2"
4471 [(set (match_operand:SF 0 "register_operand" "=f")
4472 (neg:SF (match_operand:SF 1 "register_operand" "f")))
4473 (clobber (reg:CC 33))])]
4477 (define_insn "*negsf2"
4478 [(set (match_operand:SF 0 "register_operand" "=f")
4479 (neg:SF (match_operand:SF 1 "register_operand" "f")))
4480 (clobber (reg:CC 33))]
4481 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4483 [(set_attr "op_type" "RR")])
4485 (define_insn "*negsf2"
4486 [(set (match_operand:SF 0 "register_operand" "=f")
4487 (neg:SF (match_operand:SF 1 "register_operand" "f")))
4488 (clobber (reg:CC 33))]
4489 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4491 [(set_attr "op_type" "RR")])
4495 ;;- Absolute value instructions.
4499 ; absdi2 instruction pattern(s).
4502 (define_insn "absdi2"
4503 [(set (match_operand:DI 0 "register_operand" "=d")
4504 (abs:DI (match_operand:DI 1 "register_operand" "d")))
4505 (clobber (reg:CC 33))]
4508 [(set_attr "op_type" "RRE")
4509 (set_attr "type" "set")])
4512 ; abssi2 instruction pattern(s).
4515 (define_insn "abssi2"
4516 [(set (match_operand:SI 0 "register_operand" "=d")
4517 (abs:SI (match_operand:SI 1 "register_operand" "d")))
4518 (clobber (reg:CC 33))]
4521 [(set_attr "op_type" "RR")
4522 (set_attr "type" "set")])
4525 ; abshi2 instruction pattern(s).
4528 (define_insn "abshi2"
4529 [(set (match_operand:HI 0 "register_operand" "=d")
4530 (abs:HI (match_operand:HI 1 "register_operand" "d")))
4531 (clobber (reg:CC 33))]
4533 "sll\\t%1,16\;sra\\t%1,16\;lpr\\t%0,%1"
4534 [(set_attr "op_type" "NN")
4535 (set_attr "cycle" "3")
4536 (set_attr "length" "10")])
4539 ; absdf2 instruction pattern(s).
4542 (define_expand "absdf2"
4544 [(set (match_operand:DF 0 "register_operand" "=f")
4545 (abs:DF (match_operand:DF 1 "register_operand" "f")))
4546 (clobber (reg:CC 33))])]
4550 (define_insn "*absdf2"
4551 [(set (match_operand:DF 0 "register_operand" "=f")
4552 (abs:DF (match_operand:DF 1 "register_operand" "f")))
4553 (clobber (reg:CC 33))]
4554 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4556 [(set_attr "op_type" "RR")])
4558 (define_insn "*absdf2_ibm"
4559 [(set (match_operand:DF 0 "register_operand" "=f")
4560 (abs:DF (match_operand:DF 1 "register_operand" "f")))
4561 (clobber (reg:CC 33))]
4562 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4564 [(set_attr "op_type" "RR")])
4567 ; abssf2 instruction pattern(s).
4570 (define_expand "abssf2"
4572 [(set (match_operand:SF 0 "register_operand" "=f")
4573 (abs:SF (match_operand:SF 1 "register_operand" "f")))
4574 (clobber (reg:CC 33))])]
4578 (define_insn "*abssf2"
4579 [(set (match_operand:SF 0 "register_operand" "=f")
4580 (abs:SF (match_operand:SF 1 "register_operand" "f")))
4581 (clobber (reg:CC 33))]
4582 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4584 [(set_attr "op_type" "RR")])
4586 (define_insn "*abssf2_ibm"
4587 [(set (match_operand:SF 0 "register_operand" "=f")
4588 (abs:SF (match_operand:SF 1 "register_operand" "f")))
4589 (clobber (reg:CC 33))]
4590 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4592 [(set_attr "op_type" "RR")])
4596 ;;- One complement instructions.
4600 ; one_cmpldi2 instruction pattern(s).
4603 (define_expand "one_cmpldi2"
4605 [(set (match_operand:DI 0 "r_or_s_operand" "=d")
4606 (not:DI (match_operand:DI 1 "r_or_s_operand" "0")))
4608 (clobber (reg:CC 33))])]
4610 "{ operands[2] = force_const_mem (DImode, constm1_rtx); }")
4612 (define_insn "*one_cmpldi2"
4613 [(set (match_operand:DI 0 "r_or_s_operand" "=d,Q")
4614 (not:DI (match_operand:DI 1 "r_or_s_operand" "0,0")))
4615 (use (match_operand:DI 2 "memory_operand" "m,m"))
4616 (clobber (reg:CC 33))]
4621 [(set_attr "op_type" "RR,SS")
4622 (set_attr "atype" "mem")])
4625 ; one_cmplsi2 instruction pattern(s).
4628 (define_expand "one_cmplsi2"
4630 [(set (match_operand:SI 0 "r_or_s_operand" "=d")
4631 (not:SI (match_operand:SI 1 "r_or_s_operand" "0")))
4633 (clobber (reg:CC 33))])]
4635 "{ operands[2] = force_const_mem (SImode, constm1_rtx); }")
4637 (define_insn "*one_cmplsi2"
4638 [(set (match_operand:SI 0 "r_or_s_operand" "=d,Q")
4639 (not:SI (match_operand:SI 1 "r_or_s_operand" "0,0")))
4640 (use (match_operand:SI 2 "memory_operand" "m,m"))
4641 (clobber (reg:CC 33))]
4646 [(set_attr "op_type" "RR,SS")
4647 (set_attr "atype" "mem")])
4650 ; one_cmplhi2 instruction pattern(s).
4653 (define_expand "one_cmplhi2"
4655 [(set (match_operand:HI 0 "r_or_s_operand" "=d")
4656 (not:HI (match_operand:HI 1 "r_or_s_operand" "0")))
4658 (clobber (reg:CC 33))])]
4660 "{ operands[2] = force_const_mem (SImode, constm1_rtx); }")
4662 (define_insn "*one_cmplhi2"
4663 [(set (match_operand:HI 0 "r_or_s_operand" "=d,Q")
4664 (not:HI (match_operand:HI 1 "r_or_s_operand" "0,0")))
4665 (use (match_operand:SI 2 "memory_operand" "m,m"))
4666 (clobber (reg:CC 33))]
4671 [(set_attr "op_type" "RX,SS")
4672 (set_attr "atype" "mem")])
4675 ; one_cmplqi2 instruction pattern(s).
4678 (define_insn "one_cmpqi2"
4679 [(set (match_operand:QI 0 "memory_operand" "=Q")
4680 (not:QI (match_operand:QI 1 "memory_operand" "0")))
4681 (clobber (reg:CC 33))]
4684 [(set_attr "op_type" "SI")])
4688 ;;- Rotate instructions.
4692 ; rotldi3 instruction pattern(s).
4695 (define_insn "rotldi3"
4696 [(set (match_operand:DI 0 "register_operand" "=d,d")
4697 (rotate:DI (match_operand:DI 1 "register_operand" "d,d")
4698 (match_operand:DI 2 "nonmemory_operand" "J,a")))
4699 (clobber (reg:CC 33))]
4704 [(set_attr "op_type" "RSE")
4705 (set_attr "type" "set")])
4708 ; rotlsi3 instruction pattern(s).
4711 (define_insn "rotlsi3"
4712 [(set (match_operand:SI 0 "register_operand" "=d,d")
4713 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
4714 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4715 (clobber (reg:CC 33))]
4720 [(set_attr "op_type" "RSE")
4721 (set_attr "type" "set")])
4725 ;;- Arithmetic shift instructions.
4727 ;; for left shifts always setal shifts are used (ANSI-C)
4730 ; ashldi3 instruction pattern(s).
4733 (define_expand "ashldi3"
4735 [(set (match_operand:DI 0 "register_operand" "")
4736 (ashift:DI (match_operand:DI 1 "register_operand" "")
4737 (match_operand:SI 2 "nonmemory_operand" "")))
4738 (clobber (reg:CC 33))])]
4742 (define_insn "*ashldi3_31"
4743 [(set (match_operand:DI 0 "register_operand" "=d,d")
4744 (ashift:DI (match_operand:DI 1 "register_operand" "0,0")
4745 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4746 (clobber (reg:CC 33))]
4751 [(set_attr "op_type" "RS")
4752 (set_attr "type" "set")])
4754 (define_insn "*ashldi3_64"
4755 [(set (match_operand:DI 0 "register_operand" "=d,d")
4756 (ashift:DI (match_operand:DI 1 "register_operand" "d,d")
4757 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4758 (clobber (reg:CC 33))]
4763 [(set_attr "op_type" "RSE")
4764 (set_attr "type" "set")])
4767 ; ashrdi3 instruction pattern(s).
4770 (define_expand "ashrdi3"
4772 [(set (match_operand:DI 0 "register_operand" "")
4773 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4774 (match_operand:SI 2 "nonmemory_operand" "")))
4775 (clobber (reg:CC 33))])]
4779 (define_insn "*ashrdi3_31"
4780 [(set (match_operand:DI 0 "register_operand" "=d,d")
4781 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4782 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4783 (clobber (reg:CC 33))]
4788 [(set_attr "op_type" "RS")])
4790 (define_insn "*ashrdi3_64"
4791 [(set (match_operand:DI 0 "register_operand" "=d,d")
4792 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
4793 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4794 (clobber (reg:CC 33))]
4799 [(set_attr "op_type" "RSE")
4800 (set_attr "type" "set")])
4803 ; ashlsi3 instruction pattern(s).
4805 ; all 32 bits has to be shifted (testcase co750c)
4807 (define_insn "ashlsi3"
4808 [(set (match_operand:SI 0 "register_operand" "=d,d")
4809 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
4810 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4811 (clobber (reg:CC 33))]
4816 [(set_attr "op_type" "RS")
4817 (set_attr "type" "set")])
4820 ; ashrsi3 instruction pattern(s).
4823 (define_insn "ashrsi3"
4824 [(set (match_operand:SI 0 "register_operand" "=d,d")
4825 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
4826 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4827 (clobber (reg:CC 33))]
4832 [(set_attr "op_type" "RS")
4833 (set_attr "type" "set")])
4836 ; ashlhi3 instruction pattern(s).
4839 (define_insn "ashlhi3"
4840 [(set (match_operand:HI 0 "register_operand" "=d,d")
4841 (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
4842 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4843 (clobber (reg:CC 33))]
4848 [(set_attr "op_type" "RS,RS")])
4851 ; ashrhi3 instruction pattern(s).
4854 (define_insn "ashrhi3"
4855 [(set (match_operand:HI 0 "register_operand" "=d,d")
4856 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
4857 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4858 (clobber (reg:CC 33))]
4861 sll\\t%0,16\;sra\\t%0,16+%c2
4862 sll\\t%0,16\;sra\\t%0,16(%2)"
4863 [(set_attr "op_type" "NN,NN")
4864 (set_attr "length" "8,8")])
4868 ;;- logical shift instructions.
4872 ; lshrdi3 instruction pattern(s).
4875 (define_expand "lshrdi3"
4877 [(set (match_operand:DI 0 "register_operand" "")
4878 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4879 (match_operand:SI 2 "nonmemory_operand" "")))
4880 (clobber (reg:CC 33))])]
4884 (define_insn "*lshrdi3_31"
4885 [(set (match_operand:DI 0 "register_operand" "=d,d")
4886 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4887 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4888 (clobber (reg:CC 33))]
4893 [(set_attr "op_type" "RS,RS")])
4895 (define_insn "*lshrdi3_64"
4896 [(set (match_operand:DI 0 "register_operand" "=d,d")
4897 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
4898 (match_operand:SI 2 "nonmemory_operand" "J,a")))
4899 (clobber (reg:CC 33))]
4904 [(set_attr "op_type" "RS,RS")
4905 (set_attr "type" "set")])
4908 ; lshrsi3 instruction pattern(s).
4911 (define_insn "lshrsi3"
4912 [(set (match_operand:SI 0 "register_operand" "=d,d")
4913 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0")
4914 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4915 (clobber (reg:CC 33))]
4920 [(set_attr "op_type" "RS")
4921 (set_attr "type" "set")])
4924 ; lshrhi3 instruction pattern(s).
4927 (define_insn "lshrhi3"
4928 [(set (match_operand:HI 0 "register_operand" "=d,d")
4929 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
4930 (match_operand:SI 2 "r_or_im8_operand" "J,a")))
4931 (clobber (reg:CC 33))]
4934 sll\\t%0,16\;srl\\t%0,16+%c2
4935 sll\\t%0,16\;srl\\t%0,16(%2)"
4936 [(set_attr "op_type" "NN,NN")
4937 (set_attr "length" "8,8")])
4941 ;; Branch instruction patterns.
4944 (define_expand "beq"
4945 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
4947 (if_then_else (eq (reg:CCZ 33) (const_int 0))
4948 (label_ref (match_operand 0 "" ""))
4951 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4953 (define_expand "bne"
4954 [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2)))
4956 (if_then_else (ne (reg:CCZ 33) (const_int 0))
4957 (label_ref (match_operand 0 "" ""))
4960 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4962 (define_expand "bgt"
4963 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4965 (if_then_else (gt (reg:CCS 33) (const_int 0))
4966 (label_ref (match_operand 0 "" ""))
4969 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4971 (define_expand "bgtu"
4972 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
4974 (if_then_else (gtu (reg:CCU 33) (const_int 0))
4975 (label_ref (match_operand 0 "" ""))
4978 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4980 (define_expand "blt"
4981 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
4983 (if_then_else (lt (reg:CCS 33) (const_int 0))
4984 (label_ref (match_operand 0 "" ""))
4987 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4989 (define_expand "bltu"
4990 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
4992 (if_then_else (ltu (reg:CCU 33) (const_int 0))
4993 (label_ref (match_operand 0 "" ""))
4996 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
4998 (define_expand "bge"
4999 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5001 (if_then_else (ge (reg:CCS 33) (const_int 0))
5002 (label_ref (match_operand 0 "" ""))
5005 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5007 (define_expand "bgeu"
5008 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5010 (if_then_else (geu (reg:CCU 33) (const_int 0))
5011 (label_ref (match_operand 0 "" ""))
5014 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5016 (define_expand "ble"
5017 [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2)))
5019 (if_then_else (le (reg:CCS 33) (const_int 0))
5020 (label_ref (match_operand 0 "" ""))
5023 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5025 (define_expand "bleu"
5026 [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2)))
5028 (if_then_else (leu (reg:CCU 33) (const_int 0))
5029 (label_ref (match_operand 0 "" ""))
5032 "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }")
5036 ;;- Conditional jump instructions.
5039 (define_insn "cjump"
5042 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5043 (label_ref (match_operand 0 "" ""))
5048 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5049 return \"j%C1\\t%l0\";
5051 return \"jg%C1\\t%l0\";
5053 [(set_attr "op_type" "RI")
5054 (set (attr "length") (if_then_else
5055 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5056 (const_int 4) (const_int 6)))])
5058 (define_insn "*cjump_long"
5061 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5062 (match_operand 0 "address_operand" "p")
5067 if (get_attr_op_type (insn) == OP_TYPE_RR)
5068 return \"b%C1r\\t%0\";
5070 return \"b%C1\\t%a0\";
5072 [(set (attr "op_type")
5073 (if_then_else (match_operand 0 "register_operand" "")
5074 (const_string "RR") (const_string "RX")))
5075 (set_attr "atype" "mem")])
5079 ;;- Negated conditional jump instructions.
5082 (define_insn "icjump"
5085 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5087 (label_ref (match_operand 0 "" ""))))]
5091 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5092 return \"j%D1\\t%l0\";
5094 return \"jg%D1\\t%l0\";
5096 [(set_attr "op_type" "RI")
5097 (set (attr "length") (if_then_else
5098 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5099 (const_int 4) (const_int 6)))])
5101 (define_insn "*icjump_long"
5104 (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)])
5106 (match_operand 0 "address_operand" "p")))]
5110 if (get_attr_op_type (insn) == OP_TYPE_RR)
5111 return \"b%D1r\\t%0\";
5113 return \"b%D1\\t%a0\";
5115 [(set (attr "op_type")
5116 (if_then_else (match_operand 0 "register_operand" "")
5117 (const_string "RR") (const_string "RX")))
5118 (set_attr "atype" "mem")])
5122 ;;- Subtract one and jump if not zero.
5125 ;(define_expand "decrement_and_branch_on_count"
5126 ; [(use (match_operand 0 "register_operand" ""))
5127 ; (use (label_ref (match_operand 1 "" "")))]
5131 ;/* if (TARGET_64BIT)
5132 ; emit_jump_insn (gen_brctdi (operands[0], operands[1]));
5134 ; emit_jump_insn (gen_brctsi (operands[0], operands[1]));
5138 ;(define_insn "brctsi"
5141 ; (ne (match_operand:SI 0 "register_operand" "+a")
5143 ; (label_ref (match_operand 1 "" ""))
5145 ; (set (match_dup 0)
5146 ; (plus:SI (match_dup 0) (const_int -1)))]
5149 ; [(set_attr "op_type" "RI")
5150 ; (set_attr "type" "branch")]
5153 ;(define_insn "ibrctsi"
5156 ; (eq (match_operand:SI 0 "register_operand" "+a")
5159 ; (label_ref (match_operand 1 "" ""))))
5160 ; (set (match_dup 0)
5161 ; (plus:SI (match_dup 0) (const_int -1)))]
5164 ; [(set_attr "op_type" "RI")
5165 ; (set_attr "type" "branch")]
5170 ;;- Unconditional jump instructions.
5174 ; jump instruction pattern(s).
5178 [(set (pc) (label_ref (match_operand 0 "" "")))]
5182 if (get_attr_length (insn) == 4 || !TARGET_64BIT)
5185 return \"jg\\t%l0\";
5187 [(set_attr "op_type" "RI")
5188 (set (attr "length") (if_then_else
5189 (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
5190 (const_int 4) (const_int 6)))])
5193 ; indirect-jump instruction pattern(s).
5196 (define_insn "indirect_jump"
5197 [(set (pc) (match_operand 0 "address_operand" "p"))]
5201 if (get_attr_op_type (insn) == OP_TYPE_RR)
5206 [(set (attr "op_type")
5207 (if_then_else (match_operand 0 "register_operand" "")
5208 (const_string "RR") (const_string "RX")))
5209 (set_attr "atype" "mem")])
5212 ; casesi instruction pattern(s).
5215 (define_insn "casesi_jump"
5216 [(set (pc) (match_operand 0 "address_operand" "p"))
5217 (use (label_ref (match_operand 1 "" "")))]
5221 if (get_attr_op_type (insn) == OP_TYPE_RR)
5226 [(set (attr "op_type")
5227 (if_then_else (match_operand 0 "register_operand" "")
5228 (const_string "RR") (const_string "RX")))
5229 (set_attr "atype" "mem")])
5231 (define_expand "casesi"
5232 [(match_operand:SI 0 "general_operand" "")
5233 (match_operand:SI 1 "general_operand" "")
5234 (match_operand:SI 2 "general_operand" "")
5235 (label_ref (match_operand 3 "" ""))
5236 (label_ref (match_operand 4 "" ""))]
5240 rtx index = gen_reg_rtx (SImode);
5241 rtx base = gen_reg_rtx (Pmode);
5242 rtx target = gen_reg_rtx (Pmode);
5244 emit_move_insn (index, operands[0]);
5245 emit_insn (gen_subsi3 (index, index, operands[1]));
5246 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
5249 if (Pmode != SImode)
5250 index = convert_to_mode (Pmode, index, 1);
5251 if (GET_CODE (index) != REG)
5252 index = copy_to_mode_reg (Pmode, index);
5255 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
5257 emit_insn (gen_ashlsi3 (index, index, GEN_INT (2)));
5259 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
5261 index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index));
5262 emit_move_insn (target, index);
5265 target = gen_rtx_PLUS (Pmode, base, target);
5266 emit_jump_insn (gen_casesi_jump (target, operands[3]));
5273 ;;- Jump to subroutine.
5278 ; untyped call instruction pattern(s).
5281 ;; Call subroutine returning any type.
5282 (define_expand "untyped_call"
5283 [(parallel [(call (match_operand 0 "" "")
5285 (match_operand 1 "" "")
5286 (match_operand 2 "" "")])]
5292 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
5294 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5296 rtx set = XVECEXP (operands[2], 0, i);
5297 emit_move_insn (SET_DEST (set), SET_SRC (set));
5300 /* The optimizer does not know that the call sets the function value
5301 registers we stored in the result block. We avoid problems by
5302 claiming that all hard registers are used and clobbered at this
5304 emit_insn (gen_blockage ());
5309 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5310 ;; all of memory. This blocks insns from being moved across this point.
5312 (define_insn "blockage"
5313 [(unspec_volatile [(const_int 0)] 0)]
5319 ; call instruction pattern(s).
5322 (define_expand "call"
5323 [(parallel [(call (match_operand 0 "" "")
5324 (match_operand 1 "" ""))
5325 (clobber (match_operand 2 "" ""))])]
5329 /* Abuse operand 2 to hold the return register. */
5330 operands[2] = gen_rtx_REG (Pmode, RETURN_REGNUM);
5332 /* In 31-bit, we must load the GOT register even if the
5333 compiler doesn't know about it, because the PLT glue
5334 code uses it. In 64-bit, this is not necessary. */
5335 if (flag_pic && !TARGET_64BIT)
5336 current_function_uses_pic_offset_table = 1;
5338 /* Direct function calls need special treatment. */
5339 if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
5341 rtx sym = XEXP (operands[0], 0);
5343 /* When calling a global routine in PIC mode, we must
5344 replace the symbol itself with the PLT stub. */
5345 if (flag_pic && !SYMBOL_REF_FLAG(sym))
5347 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
5348 sym = gen_rtx_CONST (Pmode, sym);
5351 /* Unless we can use the bras(l) insn, force the
5352 routine address into a register. */
5353 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
5355 rtx target = gen_reg_rtx (Pmode);
5356 emit_move_insn (target, sym);
5360 operands[0] = gen_rtx_MEM (QImode, sym);
5364 (define_insn "brasl"
5365 [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X"))
5366 (match_operand:SI 1 "const_int_operand" "n"))
5367 (clobber (match_operand:DI 2 "register_operand" "=r"))]
5370 [(set_attr "op_type" "RIL")
5371 (set_attr "cycle" "n")])
5374 [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X"))
5375 (match_operand:SI 1 "const_int_operand" "n"))
5376 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5379 [(set_attr "op_type" "RI")
5380 (set_attr "cycle" "n")])
5382 (define_insn "basr_64"
5383 [(call (mem:QI (match_operand:DI 0 "register_operand" "a"))
5384 (match_operand:SI 1 "const_int_operand" "n"))
5385 (clobber (match_operand:DI 2 "register_operand" "=r"))]
5388 [(set_attr "op_type" "RR")
5389 (set_attr "cycle" "n")
5390 (set_attr "atype" "mem")])
5392 (define_insn "basr_31"
5393 [(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
5394 (match_operand:SI 1 "const_int_operand" "n"))
5395 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5398 [(set_attr "op_type" "RR")
5399 (set_attr "cycle" "n")
5400 (set_attr "atype" "mem")])
5402 (define_insn "bas_64"
5403 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
5404 (match_operand:SI 1 "const_int_operand" "n"))
5405 (clobber (match_operand:DI 2 "register_operand" "=r"))]
5408 [(set_attr "op_type" "RX")
5409 (set_attr "cycle" "n")
5410 (set_attr "atype" "mem")])
5412 (define_insn "bas_31"
5413 [(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
5414 (match_operand:SI 1 "const_int_operand" "n"))
5415 (clobber (match_operand:SI 2 "register_operand" "=r"))]
5418 [(set_attr "op_type" "RX")
5419 (set_attr "cycle" "n")
5420 (set_attr "atype" "mem")])
5424 ; call_value instruction pattern(s).
5427 (define_expand "call_value"
5428 [(parallel [(set (match_operand 0 "" "")
5429 (call (match_operand 1 "" "")
5430 (match_operand 2 "" "")))
5431 (clobber (match_operand 3 "" ""))])]
5435 /* Abuse operand 3 to hold the return register. */
5436 operands[3] = gen_rtx_REG (Pmode, RETURN_REGNUM);
5438 /* In 31-bit, we must load the GOT register even if the
5439 compiler doesn't know about it, because the PLT glue
5440 code uses it. In 64-bit, this is not necessary. */
5441 if (flag_pic && !TARGET_64BIT)
5442 current_function_uses_pic_offset_table = 1;
5444 /* Direct function calls need special treatment. */
5445 if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
5447 rtx sym = XEXP (operands[1], 0);
5449 /* When calling a global routine in PIC mode, we must
5450 replace the symbol itself with the PLT stub. */
5451 if (flag_pic && !SYMBOL_REF_FLAG(sym))
5453 sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113);
5454 sym = gen_rtx_CONST (Pmode, sym);
5457 /* Unless we can use the bras(l) insn, force the
5458 routine address into a register. */
5459 if (!TARGET_SMALL_EXEC && !TARGET_64BIT)
5461 rtx target = gen_reg_rtx (Pmode);
5462 emit_move_insn (target, sym);
5466 operands[1] = gen_rtx_MEM (QImode, sym);
5470 (define_insn "brasl_r"
5471 [(set (match_operand 0 "register_operand" "=df")
5472 (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X"))
5473 (match_operand:SI 2 "const_int_operand" "n")))
5474 (clobber (match_operand:DI 3 "register_operand" "=r"))]
5477 [(set_attr "op_type" "RIL")
5478 (set_attr "cycle" "n")])
5480 (define_insn "bras_r"
5481 [(set (match_operand 0 "register_operand" "=df")
5482 (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X"))
5483 (match_operand:SI 2 "const_int_operand" "n")))
5484 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5487 [(set_attr "op_type" "RI")
5488 (set_attr "cycle" "n")])
5490 (define_insn "basr_r_64"
5491 [(set (match_operand 0 "register_operand" "=df")
5492 (call (mem:QI (match_operand:DI 1 "register_operand" "a"))
5493 (match_operand:SI 2 "const_int_operand" "n")))
5494 (clobber (match_operand:DI 3 "register_operand" "=r"))]
5497 [(set_attr "op_type" "RR")
5498 (set_attr "cycle" "n")])
5500 (define_insn "basr_r_31"
5501 [(set (match_operand 0 "register_operand" "=df")
5502 (call (mem:QI (match_operand:SI 1 "register_operand" "a"))
5503 (match_operand:SI 2 "const_int_operand" "n")))
5504 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5507 [(set_attr "op_type" "RR")
5508 (set_attr "cycle" "n")
5509 (set_attr "atype" "mem")])
5511 (define_insn "bas_r_64"
5512 [(set (match_operand 0 "register_operand" "=df")
5513 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
5514 (match_operand:SI 2 "const_int_operand" "n")))
5515 (clobber (match_operand:DI 3 "register_operand" "=r"))]
5518 [(set_attr "op_type" "RX")
5519 (set_attr "cycle" "n")
5520 (set_attr "atype" "mem")])
5522 (define_insn "bas_r_31"
5523 [(set (match_operand 0 "register_operand" "=df")
5524 (call (mem:QI (match_operand:QI 1 "address_operand" "p"))
5525 (match_operand:SI 2 "const_int_operand" "n")))
5526 (clobber (match_operand:SI 3 "register_operand" "=r"))]
5529 [(set_attr "op_type" "RX")
5530 (set_attr "cycle" "n")
5531 (set_attr "atype" "mem")])
5535 ;;- Miscellaneous instructions.
5539 ; allocate stack instruction pattern(s).
5542 (define_expand "allocate_stack"
5544 (plus (reg 15) (match_operand 1 "general_operand" "")))
5545 (set (match_operand 0 "general_operand" "")
5550 rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM);
5551 rtx chain = gen_rtx (MEM, Pmode, stack);
5552 rtx temp = gen_reg_rtx (Pmode);
5554 emit_move_insn (temp, chain);
5557 emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1])));
5559 emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1])));
5561 emit_move_insn (chain, temp);
5563 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
5569 ; setjmp/longjmp instruction pattern(s).
5572 (define_expand "builtin_setjmp_setup"
5573 [(unspec [(match_operand 0 "register_operand" "a")] 1)]
5577 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
5578 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
5580 emit_move_insn (base, basereg);
5584 (define_expand "builtin_setjmp_receiver"
5585 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)]
5589 rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM);
5590 rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\");
5591 SYMBOL_REF_FLAG (got) = 1;
5593 emit_move_insn (gotreg, got);
5594 emit_insn (gen_rtx_USE (VOIDmode, gotreg));
5598 (define_expand "builtin_longjmp"
5599 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
5603 /* The elements of the buffer are, in order: */
5604 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
5605 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode)));
5606 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode)));
5607 rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode)));
5608 rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER);
5609 rtx jmp = gen_rtx_REG (Pmode, 14);
5611 emit_move_insn (jmp, lab);
5612 emit_move_insn (basereg, base);
5613 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
5614 emit_move_insn (hard_frame_pointer_rtx, fp);
5616 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
5617 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
5618 emit_insn (gen_rtx_USE (VOIDmode, basereg));
5619 emit_indirect_jump (jmp);
5624 ;; These patterns say how to save and restore the stack pointer. We need not
5625 ;; save the stack pointer at function level since we are careful to
5626 ;; preserve the backchain. At block level, we have to restore the backchain
5627 ;; when we restore the stack pointer.
5629 ;; For nonlocal gotos, we must save both the stack pointer and its
5630 ;; backchain and restore both. Note that in the nonlocal case, the
5631 ;; save area is a memory location.
5633 (define_expand "save_stack_function"
5634 [(match_operand 0 "general_operand" "")
5635 (match_operand 1 "general_operand" "")]
5639 (define_expand "restore_stack_function"
5640 [(match_operand 0 "general_operand" "")
5641 (match_operand 1 "general_operand" "")]
5645 (define_expand "restore_stack_block"
5646 [(use (match_operand 0 "register_operand" ""))
5647 (set (match_dup 2) (match_dup 3))
5648 (set (match_dup 0) (match_operand 1 "register_operand" ""))
5649 (set (match_dup 3) (match_dup 2))]
5653 operands[2] = gen_reg_rtx (Pmode);
5654 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
5657 (define_expand "save_stack_nonlocal"
5658 [(match_operand 0 "memory_operand" "")
5659 (match_operand 1 "register_operand" "")]
5663 rtx temp = gen_reg_rtx (Pmode);
5665 /* Copy the backchain to the first word, sp to the second. */
5666 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
5667 emit_move_insn (operand_subword (operands[0], 0, 0,
5668 TARGET_64BIT ? TImode : DImode),
5670 emit_move_insn (operand_subword (operands[0], 1, 0,
5671 TARGET_64BIT ? TImode : DImode),
5676 (define_expand "restore_stack_nonlocal"
5677 [(match_operand 0 "register_operand" "")
5678 (match_operand 1 "memory_operand" "")]
5682 rtx temp = gen_reg_rtx (Pmode);
5684 /* Restore the backchain from the first word, sp from the second. */
5685 emit_move_insn (temp,
5686 operand_subword (operands[1], 0, 0,
5687 TARGET_64BIT ? TImode : DImode));
5688 emit_move_insn (operands[0],
5689 operand_subword (operands[1], 1, 0,
5690 TARGET_64BIT ? TImode : DImode));
5691 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
5697 ; nop instruction pattern(s).
5704 [(set_attr "op_type" "RR")])
5708 ; Special literal pool access instruction pattern(s).
5711 (define_insn "reload_base"
5712 [(parallel [(set (reg 13) (pc))
5713 (use (label_ref (match_operand 0 "" "")))])]
5718 return \"larl\\t13,%y0\";
5720 return \"basr\\t13,0\;ahi\\t13,%Y0\";
5722 [(set_attr "op_type" "NN")
5723 (set_attr "cycle" "2")
5724 (set_attr "length" "8")])
5726 (define_insn "ltorg"
5727 [(parallel [(set (reg 13) (pc))
5728 (use (match_operand:SI 0 "const_int_operand" ""))])]
5732 s390_dump_literal_pool (insn, operands[0]);
5735 [(set_attr "op_type" "NN")
5736 (set_attr "cycle" "n")
5737 (set_attr "length" "4096")])
5741 ;; Peephole optimization patterns.
5745 [(set (match_operand:SI 0 "memory_operand" "m")
5746 (match_operand:SI 1 "register_operand" "d"))
5753 [(set (match_operand:SI 0 "memory_operand" "m")
5754 (match_operand:SI 1 "register_operand" "d"))
5761 [(set (match_operand:SI 0 "register_operand" "")
5762 (match_operand:SI 1 "register_operand" ""))
5765 (plus:SI (match_dup 0)
5766 (match_operand:SI 2 "immediate_operand" "")))
5767 (clobber (reg:CC 33))])]
5768 "(REGNO (operands[0]) == STACK_POINTER_REGNUM ||
5769 REGNO (operands[1]) == STACK_POINTER_REGNUM ||
5770 REGNO (operands[0]) == BASE_REGISTER ||
5771 REGNO (operands[1]) == BASE_REGISTER) &&
5772 INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096"
5776 ; peepholes for fast char instructions
5780 ; [(set (match_operand:QI 0 "register_operand" "d")
5781 ; (match_operand:QI 1 "s_operand" "Q"))
5782 ; (set (match_operand:SI 2 "register_operand" "0")
5783 ; (zero_extend:SI (match_dup 0)))]
5784 ; "REGNO(operands[0]) == REGNO(operands[2])"
5785 ; "icm\\t%0,8,%1\;srl\\t%0,24")
5788 ; [(set (match_operand:QI 0 "register_operand" "d")
5789 ; (match_operand:QI 1 "s_operand" "Q"))
5790 ; (set (match_operand:SI 2 "register_operand" "0")
5791 ; (sign_extend:SI (match_dup 0)))]
5792 ; "REGNO(operands[0]) == REGNO(operands[2])"
5793 ; "icm\\t%0,8,%1\;sra\\t%0,24")
5796 [(set (match_operand:QI 0 "register_operand" "d")
5797 (match_operand:QI 1 "immediate_operand" "J"))
5798 (set (match_operand:SI 2 "register_operand" "0" )
5799 (sign_extend:SI (match_dup 0) ) )]
5800 "REGNO(operands[0]) == REGNO(operands[2])"
5804 ; peepholes for fast short instructions
5808 ; [(set (match_operand:HI 0 "register_operand" "d")
5809 ; (match_operand:HI 1 "s_operand" "Q"))
5810 ; (set (match_operand:SI 2 "register_operand" "0" )
5811 ; (zero_extend:SI (match_dup 0)))]
5812 ; "REGNO(operands[0]) == REGNO(operands[2])"
5813 ; "icm\\t%0,12,%1\;srl\\t%0,16")
5816 [(set (match_operand:HI 0 "register_operand" "d")
5817 (match_operand:HI 1 "memory_operand" "m"))
5818 (set (match_operand:SI 2 "register_operand" "0" )
5819 (sign_extend:SI (match_dup 0)))]
5820 "REGNO(operands[0]) == REGNO(operands[2])"
5824 [(set (match_operand:HI 0 "register_operand" "d")
5825 (match_operand:HI 1 "immediate_operand" "K"))
5826 (set (match_operand:SI 2 "register_operand" "0" )
5827 (sign_extend:SI (match_dup 0) ) )]
5828 "REGNO(operands[0]) == REGNO(operands[2])"
5832 ; peepholes for divide instructions
5836 [(set (match_operand:DI 0 "register_operand" "d")
5837 (match_operand:DI 1 "memory_operand" "m"))
5839 (lshiftrt:DI (match_dup 0)
5840 (match_operand:SI 2 "immediate_operand" "J")))
5842 (div:SI (match_dup 0)
5843 (match_operand:SI 3 "nonimmediate_operand" "g")))
5849 output_asm_insn (\"l\\t%0,%1\", operands);
5850 output_asm_insn (\"srdl\\t%0,%b2\", operands);
5852 if (REG_P (operands[3]))
5853 output_asm_insn (\"dr\\t%0,%3\", operands);
5855 output_asm_insn (\"d\\t%0,%3\", operands);
5857 return \"st\\t%N0,%N1\";
5861 [(set (match_operand:DI 0 "register_operand" "d")
5862 (match_operand:DI 1 "memory_operand" "m"))
5864 (lshiftrt:DI (match_dup 0)
5865 (match_operand:SI 2 "immediate_operand" "J")))
5867 (mod:SI (match_dup 0)
5868 (match_operand:SI 3 "nonimmediate_operand" "g")))
5874 output_asm_insn (\"l\\t%0,%1\", operands);
5875 output_asm_insn (\"srdl\\t%0,%b2\", operands);
5877 if (REG_P (operands[3]))
5878 output_asm_insn (\"dr\\t%0,%3\", operands);
5880 output_asm_insn (\"d\\t%0,%3\", operands);
5882 return \"st\\t%0,%1\";