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rtlanal.c (refers_to_regno_p): Change return value from int to bool.
[gcc.git] / gcc / config / s390 / s390.c
1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
6
7 This file is part of GCC.
8
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
12 version.
13
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
22
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27 #include "rtl.h"
28 #include "tree.h"
29 #include "print-tree.h"
30 #include "stringpool.h"
31 #include "stor-layout.h"
32 #include "varasm.h"
33 #include "calls.h"
34 #include "tm_p.h"
35 #include "regs.h"
36 #include "hard-reg-set.h"
37 #include "insn-config.h"
38 #include "conditions.h"
39 #include "output.h"
40 #include "insn-attr.h"
41 #include "flags.h"
42 #include "except.h"
43 #include "hashtab.h"
44 #include "hash-set.h"
45 #include "vec.h"
46 #include "machmode.h"
47 #include "input.h"
48 #include "function.h"
49 #include "recog.h"
50 #include "expr.h"
51 #include "reload.h"
52 #include "diagnostic-core.h"
53 #include "predict.h"
54 #include "dominance.h"
55 #include "cfg.h"
56 #include "cfgrtl.h"
57 #include "cfganal.h"
58 #include "lcm.h"
59 #include "cfgbuild.h"
60 #include "cfgcleanup.h"
61 #include "basic-block.h"
62 #include "ggc.h"
63 #include "target.h"
64 #include "target-def.h"
65 #include "debug.h"
66 #include "langhooks.h"
67 #include "insn-codes.h"
68 #include "optabs.h"
69 #include "hash-table.h"
70 #include "tree-ssa-alias.h"
71 #include "internal-fn.h"
72 #include "gimple-fold.h"
73 #include "tree-eh.h"
74 #include "gimple-expr.h"
75 #include "is-a.h"
76 #include "gimple.h"
77 #include "gimplify.h"
78 #include "df.h"
79 #include "params.h"
80 #include "cfgloop.h"
81 #include "opts.h"
82 #include "tree-pass.h"
83 #include "context.h"
84 #include "builtins.h"
85 #include "rtl-iter.h"
86
87 /* Define the specific costs for a given cpu. */
88
89 struct processor_costs
90 {
91 /* multiplication */
92 const int m; /* cost of an M instruction. */
93 const int mghi; /* cost of an MGHI instruction. */
94 const int mh; /* cost of an MH instruction. */
95 const int mhi; /* cost of an MHI instruction. */
96 const int ml; /* cost of an ML instruction. */
97 const int mr; /* cost of an MR instruction. */
98 const int ms; /* cost of an MS instruction. */
99 const int msg; /* cost of an MSG instruction. */
100 const int msgf; /* cost of an MSGF instruction. */
101 const int msgfr; /* cost of an MSGFR instruction. */
102 const int msgr; /* cost of an MSGR instruction. */
103 const int msr; /* cost of an MSR instruction. */
104 const int mult_df; /* cost of multiplication in DFmode. */
105 const int mxbr;
106 /* square root */
107 const int sqxbr; /* cost of square root in TFmode. */
108 const int sqdbr; /* cost of square root in DFmode. */
109 const int sqebr; /* cost of square root in SFmode. */
110 /* multiply and add */
111 const int madbr; /* cost of multiply and add in DFmode. */
112 const int maebr; /* cost of multiply and add in SFmode. */
113 /* division */
114 const int dxbr;
115 const int ddbr;
116 const int debr;
117 const int dlgr;
118 const int dlr;
119 const int dr;
120 const int dsgfr;
121 const int dsgr;
122 };
123
124 const struct processor_costs *s390_cost;
125
126 static const
127 struct processor_costs z900_cost =
128 {
129 COSTS_N_INSNS (5), /* M */
130 COSTS_N_INSNS (10), /* MGHI */
131 COSTS_N_INSNS (5), /* MH */
132 COSTS_N_INSNS (4), /* MHI */
133 COSTS_N_INSNS (5), /* ML */
134 COSTS_N_INSNS (5), /* MR */
135 COSTS_N_INSNS (4), /* MS */
136 COSTS_N_INSNS (15), /* MSG */
137 COSTS_N_INSNS (7), /* MSGF */
138 COSTS_N_INSNS (7), /* MSGFR */
139 COSTS_N_INSNS (10), /* MSGR */
140 COSTS_N_INSNS (4), /* MSR */
141 COSTS_N_INSNS (7), /* multiplication in DFmode */
142 COSTS_N_INSNS (13), /* MXBR */
143 COSTS_N_INSNS (136), /* SQXBR */
144 COSTS_N_INSNS (44), /* SQDBR */
145 COSTS_N_INSNS (35), /* SQEBR */
146 COSTS_N_INSNS (18), /* MADBR */
147 COSTS_N_INSNS (13), /* MAEBR */
148 COSTS_N_INSNS (134), /* DXBR */
149 COSTS_N_INSNS (30), /* DDBR */
150 COSTS_N_INSNS (27), /* DEBR */
151 COSTS_N_INSNS (220), /* DLGR */
152 COSTS_N_INSNS (34), /* DLR */
153 COSTS_N_INSNS (34), /* DR */
154 COSTS_N_INSNS (32), /* DSGFR */
155 COSTS_N_INSNS (32), /* DSGR */
156 };
157
158 static const
159 struct processor_costs z990_cost =
160 {
161 COSTS_N_INSNS (4), /* M */
162 COSTS_N_INSNS (2), /* MGHI */
163 COSTS_N_INSNS (2), /* MH */
164 COSTS_N_INSNS (2), /* MHI */
165 COSTS_N_INSNS (4), /* ML */
166 COSTS_N_INSNS (4), /* MR */
167 COSTS_N_INSNS (5), /* MS */
168 COSTS_N_INSNS (6), /* MSG */
169 COSTS_N_INSNS (4), /* MSGF */
170 COSTS_N_INSNS (4), /* MSGFR */
171 COSTS_N_INSNS (4), /* MSGR */
172 COSTS_N_INSNS (4), /* MSR */
173 COSTS_N_INSNS (1), /* multiplication in DFmode */
174 COSTS_N_INSNS (28), /* MXBR */
175 COSTS_N_INSNS (130), /* SQXBR */
176 COSTS_N_INSNS (66), /* SQDBR */
177 COSTS_N_INSNS (38), /* SQEBR */
178 COSTS_N_INSNS (1), /* MADBR */
179 COSTS_N_INSNS (1), /* MAEBR */
180 COSTS_N_INSNS (60), /* DXBR */
181 COSTS_N_INSNS (40), /* DDBR */
182 COSTS_N_INSNS (26), /* DEBR */
183 COSTS_N_INSNS (176), /* DLGR */
184 COSTS_N_INSNS (31), /* DLR */
185 COSTS_N_INSNS (31), /* DR */
186 COSTS_N_INSNS (31), /* DSGFR */
187 COSTS_N_INSNS (31), /* DSGR */
188 };
189
190 static const
191 struct processor_costs z9_109_cost =
192 {
193 COSTS_N_INSNS (4), /* M */
194 COSTS_N_INSNS (2), /* MGHI */
195 COSTS_N_INSNS (2), /* MH */
196 COSTS_N_INSNS (2), /* MHI */
197 COSTS_N_INSNS (4), /* ML */
198 COSTS_N_INSNS (4), /* MR */
199 COSTS_N_INSNS (5), /* MS */
200 COSTS_N_INSNS (6), /* MSG */
201 COSTS_N_INSNS (4), /* MSGF */
202 COSTS_N_INSNS (4), /* MSGFR */
203 COSTS_N_INSNS (4), /* MSGR */
204 COSTS_N_INSNS (4), /* MSR */
205 COSTS_N_INSNS (1), /* multiplication in DFmode */
206 COSTS_N_INSNS (28), /* MXBR */
207 COSTS_N_INSNS (130), /* SQXBR */
208 COSTS_N_INSNS (66), /* SQDBR */
209 COSTS_N_INSNS (38), /* SQEBR */
210 COSTS_N_INSNS (1), /* MADBR */
211 COSTS_N_INSNS (1), /* MAEBR */
212 COSTS_N_INSNS (60), /* DXBR */
213 COSTS_N_INSNS (40), /* DDBR */
214 COSTS_N_INSNS (26), /* DEBR */
215 COSTS_N_INSNS (30), /* DLGR */
216 COSTS_N_INSNS (23), /* DLR */
217 COSTS_N_INSNS (23), /* DR */
218 COSTS_N_INSNS (24), /* DSGFR */
219 COSTS_N_INSNS (24), /* DSGR */
220 };
221
222 static const
223 struct processor_costs z10_cost =
224 {
225 COSTS_N_INSNS (10), /* M */
226 COSTS_N_INSNS (10), /* MGHI */
227 COSTS_N_INSNS (10), /* MH */
228 COSTS_N_INSNS (10), /* MHI */
229 COSTS_N_INSNS (10), /* ML */
230 COSTS_N_INSNS (10), /* MR */
231 COSTS_N_INSNS (10), /* MS */
232 COSTS_N_INSNS (10), /* MSG */
233 COSTS_N_INSNS (10), /* MSGF */
234 COSTS_N_INSNS (10), /* MSGFR */
235 COSTS_N_INSNS (10), /* MSGR */
236 COSTS_N_INSNS (10), /* MSR */
237 COSTS_N_INSNS (1) , /* multiplication in DFmode */
238 COSTS_N_INSNS (50), /* MXBR */
239 COSTS_N_INSNS (120), /* SQXBR */
240 COSTS_N_INSNS (52), /* SQDBR */
241 COSTS_N_INSNS (38), /* SQEBR */
242 COSTS_N_INSNS (1), /* MADBR */
243 COSTS_N_INSNS (1), /* MAEBR */
244 COSTS_N_INSNS (111), /* DXBR */
245 COSTS_N_INSNS (39), /* DDBR */
246 COSTS_N_INSNS (32), /* DEBR */
247 COSTS_N_INSNS (160), /* DLGR */
248 COSTS_N_INSNS (71), /* DLR */
249 COSTS_N_INSNS (71), /* DR */
250 COSTS_N_INSNS (71), /* DSGFR */
251 COSTS_N_INSNS (71), /* DSGR */
252 };
253
254 static const
255 struct processor_costs z196_cost =
256 {
257 COSTS_N_INSNS (7), /* M */
258 COSTS_N_INSNS (5), /* MGHI */
259 COSTS_N_INSNS (5), /* MH */
260 COSTS_N_INSNS (5), /* MHI */
261 COSTS_N_INSNS (7), /* ML */
262 COSTS_N_INSNS (7), /* MR */
263 COSTS_N_INSNS (6), /* MS */
264 COSTS_N_INSNS (8), /* MSG */
265 COSTS_N_INSNS (6), /* MSGF */
266 COSTS_N_INSNS (6), /* MSGFR */
267 COSTS_N_INSNS (8), /* MSGR */
268 COSTS_N_INSNS (6), /* MSR */
269 COSTS_N_INSNS (1) , /* multiplication in DFmode */
270 COSTS_N_INSNS (40), /* MXBR B+40 */
271 COSTS_N_INSNS (100), /* SQXBR B+100 */
272 COSTS_N_INSNS (42), /* SQDBR B+42 */
273 COSTS_N_INSNS (28), /* SQEBR B+28 */
274 COSTS_N_INSNS (1), /* MADBR B */
275 COSTS_N_INSNS (1), /* MAEBR B */
276 COSTS_N_INSNS (101), /* DXBR B+101 */
277 COSTS_N_INSNS (29), /* DDBR */
278 COSTS_N_INSNS (22), /* DEBR */
279 COSTS_N_INSNS (160), /* DLGR cracked */
280 COSTS_N_INSNS (160), /* DLR cracked */
281 COSTS_N_INSNS (160), /* DR expanded */
282 COSTS_N_INSNS (160), /* DSGFR cracked */
283 COSTS_N_INSNS (160), /* DSGR cracked */
284 };
285
286 static const
287 struct processor_costs zEC12_cost =
288 {
289 COSTS_N_INSNS (7), /* M */
290 COSTS_N_INSNS (5), /* MGHI */
291 COSTS_N_INSNS (5), /* MH */
292 COSTS_N_INSNS (5), /* MHI */
293 COSTS_N_INSNS (7), /* ML */
294 COSTS_N_INSNS (7), /* MR */
295 COSTS_N_INSNS (6), /* MS */
296 COSTS_N_INSNS (8), /* MSG */
297 COSTS_N_INSNS (6), /* MSGF */
298 COSTS_N_INSNS (6), /* MSGFR */
299 COSTS_N_INSNS (8), /* MSGR */
300 COSTS_N_INSNS (6), /* MSR */
301 COSTS_N_INSNS (1) , /* multiplication in DFmode */
302 COSTS_N_INSNS (40), /* MXBR B+40 */
303 COSTS_N_INSNS (100), /* SQXBR B+100 */
304 COSTS_N_INSNS (42), /* SQDBR B+42 */
305 COSTS_N_INSNS (28), /* SQEBR B+28 */
306 COSTS_N_INSNS (1), /* MADBR B */
307 COSTS_N_INSNS (1), /* MAEBR B */
308 COSTS_N_INSNS (131), /* DXBR B+131 */
309 COSTS_N_INSNS (29), /* DDBR */
310 COSTS_N_INSNS (22), /* DEBR */
311 COSTS_N_INSNS (160), /* DLGR cracked */
312 COSTS_N_INSNS (160), /* DLR cracked */
313 COSTS_N_INSNS (160), /* DR expanded */
314 COSTS_N_INSNS (160), /* DSGFR cracked */
315 COSTS_N_INSNS (160), /* DSGR cracked */
316 };
317
318 extern int reload_completed;
319
320 /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
321 static rtx_insn *last_scheduled_insn;
322
323 /* Structure used to hold the components of a S/390 memory
324 address. A legitimate address on S/390 is of the general
325 form
326 base + index + displacement
327 where any of the components is optional.
328
329 base and index are registers of the class ADDR_REGS,
330 displacement is an unsigned 12-bit immediate constant. */
331
332 struct s390_address
333 {
334 rtx base;
335 rtx indx;
336 rtx disp;
337 bool pointer;
338 bool literal_pool;
339 };
340
341 /* The following structure is embedded in the machine
342 specific part of struct function. */
343
344 struct GTY (()) s390_frame_layout
345 {
346 /* Offset within stack frame. */
347 HOST_WIDE_INT gprs_offset;
348 HOST_WIDE_INT f0_offset;
349 HOST_WIDE_INT f4_offset;
350 HOST_WIDE_INT f8_offset;
351 HOST_WIDE_INT backchain_offset;
352
353 /* Number of first and last gpr where slots in the register
354 save area are reserved for. */
355 int first_save_gpr_slot;
356 int last_save_gpr_slot;
357
358 /* Location (FP register number) where GPRs (r0-r15) should
359 be saved to.
360 0 - does not need to be saved at all
361 -1 - stack slot */
362 signed char gpr_save_slots[16];
363
364 /* Number of first and last gpr to be saved, restored. */
365 int first_save_gpr;
366 int first_restore_gpr;
367 int last_save_gpr;
368 int last_restore_gpr;
369
370 /* Bits standing for floating point registers. Set, if the
371 respective register has to be saved. Starting with reg 16 (f0)
372 at the rightmost bit.
373 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
374 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
375 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
376 unsigned int fpr_bitmap;
377
378 /* Number of floating point registers f8-f15 which must be saved. */
379 int high_fprs;
380
381 /* Set if return address needs to be saved.
382 This flag is set by s390_return_addr_rtx if it could not use
383 the initial value of r14 and therefore depends on r14 saved
384 to the stack. */
385 bool save_return_addr_p;
386
387 /* Size of stack frame. */
388 HOST_WIDE_INT frame_size;
389 };
390
391 /* Define the structure for the machine field in struct function. */
392
393 struct GTY(()) machine_function
394 {
395 struct s390_frame_layout frame_layout;
396
397 /* Literal pool base register. */
398 rtx base_reg;
399
400 /* True if we may need to perform branch splitting. */
401 bool split_branches_pending_p;
402
403 bool has_landing_pad_p;
404
405 /* True if the current function may contain a tbegin clobbering
406 FPRs. */
407 bool tbegin_p;
408 };
409
410 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
411
412 #define cfun_frame_layout (cfun->machine->frame_layout)
413 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
414 #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
415 ? cfun_frame_layout.fpr_bitmap & 0x0f \
416 : cfun_frame_layout.fpr_bitmap & 0x03))
417 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
418 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
419 #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
420 (1 << (REGNO - FPR0_REGNUM)))
421 #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
422 (1 << (REGNO - FPR0_REGNUM))))
423 #define cfun_gpr_save_slot(REGNO) \
424 cfun->machine->frame_layout.gpr_save_slots[REGNO]
425
426 /* Number of GPRs and FPRs used for argument passing. */
427 #define GP_ARG_NUM_REG 5
428 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
429
430 /* A couple of shortcuts. */
431 #define CONST_OK_FOR_J(x) \
432 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
433 #define CONST_OK_FOR_K(x) \
434 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
435 #define CONST_OK_FOR_Os(x) \
436 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
437 #define CONST_OK_FOR_Op(x) \
438 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
439 #define CONST_OK_FOR_On(x) \
440 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
441
442 #define REGNO_PAIR_OK(REGNO, MODE) \
443 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
444
445 /* That's the read ahead of the dynamic branch prediction unit in
446 bytes on a z10 (or higher) CPU. */
447 #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
448
449 static const int s390_hotpatch_trampoline_halfwords_default = 12;
450 static const int s390_hotpatch_trampoline_halfwords_max = 1000000;
451 static int s390_hotpatch_trampoline_halfwords = -1;
452
453 /* Return the argument of the given hotpatch attribute or the default value if
454 no argument is present. */
455
456 static inline int
457 get_hotpatch_attribute (tree hotpatch_attr)
458 {
459 const_tree args;
460
461 args = TREE_VALUE (hotpatch_attr);
462
463 return (args) ?
464 TREE_INT_CST_LOW (TREE_VALUE (args)):
465 s390_hotpatch_trampoline_halfwords_default;
466 }
467
468 /* Check whether the hotpatch attribute is applied to a function and, if it has
469 an argument, the argument is valid. */
470
471 static tree
472 s390_handle_hotpatch_attribute (tree *node, tree name, tree args,
473 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
474 {
475 if (TREE_CODE (*node) != FUNCTION_DECL)
476 {
477 warning (OPT_Wattributes, "%qE attribute only applies to functions",
478 name);
479 *no_add_attrs = true;
480 }
481 else if (args)
482 {
483 tree expr = TREE_VALUE (args);
484
485 if (TREE_CODE (expr) != INTEGER_CST
486 || !INTEGRAL_TYPE_P (TREE_TYPE (expr))
487 || wi::gtu_p (expr, s390_hotpatch_trampoline_halfwords_max))
488 {
489 error ("requested %qE attribute is not a non-negative integer"
490 " constant or too large (max. %d)", name,
491 s390_hotpatch_trampoline_halfwords_max);
492 *no_add_attrs = true;
493 }
494 }
495
496 return NULL_TREE;
497 }
498
499 static const struct attribute_spec s390_attribute_table[] = {
500 { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute, false
501 },
502 /* End element. */
503 { NULL, 0, 0, false, false, false, NULL, false }
504 };
505
506 /* Return the alignment for LABEL. We default to the -falign-labels
507 value except for the literal pool base label. */
508 int
509 s390_label_align (rtx label)
510 {
511 rtx_insn *prev_insn = prev_active_insn (label);
512 rtx set, src;
513
514 if (prev_insn == NULL_RTX)
515 goto old;
516
517 set = single_set (prev_insn);
518
519 if (set == NULL_RTX)
520 goto old;
521
522 src = SET_SRC (set);
523
524 /* Don't align literal pool base labels. */
525 if (GET_CODE (src) == UNSPEC
526 && XINT (src, 1) == UNSPEC_MAIN_BASE)
527 return 0;
528
529 old:
530 return align_labels_log;
531 }
532
533 static machine_mode
534 s390_libgcc_cmp_return_mode (void)
535 {
536 return TARGET_64BIT ? DImode : SImode;
537 }
538
539 static machine_mode
540 s390_libgcc_shift_count_mode (void)
541 {
542 return TARGET_64BIT ? DImode : SImode;
543 }
544
545 static machine_mode
546 s390_unwind_word_mode (void)
547 {
548 return TARGET_64BIT ? DImode : SImode;
549 }
550
551 /* Return true if the back end supports mode MODE. */
552 static bool
553 s390_scalar_mode_supported_p (machine_mode mode)
554 {
555 /* In contrast to the default implementation reject TImode constants on 31bit
556 TARGET_ZARCH for ABI compliance. */
557 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
558 return false;
559
560 if (DECIMAL_FLOAT_MODE_P (mode))
561 return default_decimal_float_supported_p ();
562
563 return default_scalar_mode_supported_p (mode);
564 }
565
566 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
567
568 void
569 s390_set_has_landing_pad_p (bool value)
570 {
571 cfun->machine->has_landing_pad_p = value;
572 }
573
574 /* If two condition code modes are compatible, return a condition code
575 mode which is compatible with both. Otherwise, return
576 VOIDmode. */
577
578 static machine_mode
579 s390_cc_modes_compatible (machine_mode m1, machine_mode m2)
580 {
581 if (m1 == m2)
582 return m1;
583
584 switch (m1)
585 {
586 case CCZmode:
587 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
588 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
589 return m2;
590 return VOIDmode;
591
592 case CCSmode:
593 case CCUmode:
594 case CCTmode:
595 case CCSRmode:
596 case CCURmode:
597 case CCZ1mode:
598 if (m2 == CCZmode)
599 return m1;
600
601 return VOIDmode;
602
603 default:
604 return VOIDmode;
605 }
606 return VOIDmode;
607 }
608
609 /* Return true if SET either doesn't set the CC register, or else
610 the source and destination have matching CC modes and that
611 CC mode is at least as constrained as REQ_MODE. */
612
613 static bool
614 s390_match_ccmode_set (rtx set, machine_mode req_mode)
615 {
616 machine_mode set_mode;
617
618 gcc_assert (GET_CODE (set) == SET);
619
620 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
621 return 1;
622
623 set_mode = GET_MODE (SET_DEST (set));
624 switch (set_mode)
625 {
626 case CCSmode:
627 case CCSRmode:
628 case CCUmode:
629 case CCURmode:
630 case CCLmode:
631 case CCL1mode:
632 case CCL2mode:
633 case CCL3mode:
634 case CCT1mode:
635 case CCT2mode:
636 case CCT3mode:
637 if (req_mode != set_mode)
638 return 0;
639 break;
640
641 case CCZmode:
642 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
643 && req_mode != CCSRmode && req_mode != CCURmode)
644 return 0;
645 break;
646
647 case CCAPmode:
648 case CCANmode:
649 if (req_mode != CCAmode)
650 return 0;
651 break;
652
653 default:
654 gcc_unreachable ();
655 }
656
657 return (GET_MODE (SET_SRC (set)) == set_mode);
658 }
659
660 /* Return true if every SET in INSN that sets the CC register
661 has source and destination with matching CC modes and that
662 CC mode is at least as constrained as REQ_MODE.
663 If REQ_MODE is VOIDmode, always return false. */
664
665 bool
666 s390_match_ccmode (rtx_insn *insn, machine_mode req_mode)
667 {
668 int i;
669
670 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
671 if (req_mode == VOIDmode)
672 return false;
673
674 if (GET_CODE (PATTERN (insn)) == SET)
675 return s390_match_ccmode_set (PATTERN (insn), req_mode);
676
677 if (GET_CODE (PATTERN (insn)) == PARALLEL)
678 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
679 {
680 rtx set = XVECEXP (PATTERN (insn), 0, i);
681 if (GET_CODE (set) == SET)
682 if (!s390_match_ccmode_set (set, req_mode))
683 return false;
684 }
685
686 return true;
687 }
688
689 /* If a test-under-mask instruction can be used to implement
690 (compare (and ... OP1) OP2), return the CC mode required
691 to do that. Otherwise, return VOIDmode.
692 MIXED is true if the instruction can distinguish between
693 CC1 and CC2 for mixed selected bits (TMxx), it is false
694 if the instruction cannot (TM). */
695
696 machine_mode
697 s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
698 {
699 int bit0, bit1;
700
701 /* ??? Fixme: should work on CONST_DOUBLE as well. */
702 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
703 return VOIDmode;
704
705 /* Selected bits all zero: CC0.
706 e.g.: int a; if ((a & (16 + 128)) == 0) */
707 if (INTVAL (op2) == 0)
708 return CCTmode;
709
710 /* Selected bits all one: CC3.
711 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
712 if (INTVAL (op2) == INTVAL (op1))
713 return CCT3mode;
714
715 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
716 int a;
717 if ((a & (16 + 128)) == 16) -> CCT1
718 if ((a & (16 + 128)) == 128) -> CCT2 */
719 if (mixed)
720 {
721 bit1 = exact_log2 (INTVAL (op2));
722 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
723 if (bit0 != -1 && bit1 != -1)
724 return bit0 > bit1 ? CCT1mode : CCT2mode;
725 }
726
727 return VOIDmode;
728 }
729
730 /* Given a comparison code OP (EQ, NE, etc.) and the operands
731 OP0 and OP1 of a COMPARE, return the mode to be used for the
732 comparison. */
733
734 machine_mode
735 s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
736 {
737 switch (code)
738 {
739 case EQ:
740 case NE:
741 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
742 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
743 return CCAPmode;
744 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
745 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
746 return CCAPmode;
747 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
748 || GET_CODE (op1) == NEG)
749 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
750 return CCLmode;
751
752 if (GET_CODE (op0) == AND)
753 {
754 /* Check whether we can potentially do it via TM. */
755 machine_mode ccmode;
756 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
757 if (ccmode != VOIDmode)
758 {
759 /* Relax CCTmode to CCZmode to allow fall-back to AND
760 if that turns out to be beneficial. */
761 return ccmode == CCTmode ? CCZmode : ccmode;
762 }
763 }
764
765 if (register_operand (op0, HImode)
766 && GET_CODE (op1) == CONST_INT
767 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
768 return CCT3mode;
769 if (register_operand (op0, QImode)
770 && GET_CODE (op1) == CONST_INT
771 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
772 return CCT3mode;
773
774 return CCZmode;
775
776 case LE:
777 case LT:
778 case GE:
779 case GT:
780 /* The only overflow condition of NEG and ABS happens when
781 -INT_MAX is used as parameter, which stays negative. So
782 we have an overflow from a positive value to a negative.
783 Using CCAP mode the resulting cc can be used for comparisons. */
784 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
785 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
786 return CCAPmode;
787
788 /* If constants are involved in an add instruction it is possible to use
789 the resulting cc for comparisons with zero. Knowing the sign of the
790 constant the overflow behavior gets predictable. e.g.:
791 int a, b; if ((b = a + c) > 0)
792 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
793 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
794 && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
795 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
796 /* Avoid INT32_MIN on 32 bit. */
797 && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1))))
798 {
799 if (INTVAL (XEXP((op0), 1)) < 0)
800 return CCANmode;
801 else
802 return CCAPmode;
803 }
804 /* Fall through. */
805 case UNORDERED:
806 case ORDERED:
807 case UNEQ:
808 case UNLE:
809 case UNLT:
810 case UNGE:
811 case UNGT:
812 case LTGT:
813 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
814 && GET_CODE (op1) != CONST_INT)
815 return CCSRmode;
816 return CCSmode;
817
818 case LTU:
819 case GEU:
820 if (GET_CODE (op0) == PLUS
821 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
822 return CCL1mode;
823
824 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
825 && GET_CODE (op1) != CONST_INT)
826 return CCURmode;
827 return CCUmode;
828
829 case LEU:
830 case GTU:
831 if (GET_CODE (op0) == MINUS
832 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
833 return CCL2mode;
834
835 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
836 && GET_CODE (op1) != CONST_INT)
837 return CCURmode;
838 return CCUmode;
839
840 default:
841 gcc_unreachable ();
842 }
843 }
844
845 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
846 that we can implement more efficiently. */
847
848 static void
849 s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
850 bool op0_preserve_value)
851 {
852 if (op0_preserve_value)
853 return;
854
855 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
856 if ((*code == EQ || *code == NE)
857 && *op1 == const0_rtx
858 && GET_CODE (*op0) == ZERO_EXTRACT
859 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
860 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
861 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
862 {
863 rtx inner = XEXP (*op0, 0);
864 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
865 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
866 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
867
868 if (len > 0 && len < modesize
869 && pos >= 0 && pos + len <= modesize
870 && modesize <= HOST_BITS_PER_WIDE_INT)
871 {
872 unsigned HOST_WIDE_INT block;
873 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
874 block <<= modesize - pos - len;
875
876 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
877 gen_int_mode (block, GET_MODE (inner)));
878 }
879 }
880
881 /* Narrow AND of memory against immediate to enable TM. */
882 if ((*code == EQ || *code == NE)
883 && *op1 == const0_rtx
884 && GET_CODE (*op0) == AND
885 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
886 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
887 {
888 rtx inner = XEXP (*op0, 0);
889 rtx mask = XEXP (*op0, 1);
890
891 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
892 if (GET_CODE (inner) == SUBREG
893 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
894 && (GET_MODE_SIZE (GET_MODE (inner))
895 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
896 && ((INTVAL (mask)
897 & GET_MODE_MASK (GET_MODE (inner))
898 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
899 == 0))
900 inner = SUBREG_REG (inner);
901
902 /* Do not change volatile MEMs. */
903 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
904 {
905 int part = s390_single_part (XEXP (*op0, 1),
906 GET_MODE (inner), QImode, 0);
907 if (part >= 0)
908 {
909 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
910 inner = adjust_address_nv (inner, QImode, part);
911 *op0 = gen_rtx_AND (QImode, inner, mask);
912 }
913 }
914 }
915
916 /* Narrow comparisons against 0xffff to HImode if possible. */
917 if ((*code == EQ || *code == NE)
918 && GET_CODE (*op1) == CONST_INT
919 && INTVAL (*op1) == 0xffff
920 && SCALAR_INT_MODE_P (GET_MODE (*op0))
921 && (nonzero_bits (*op0, GET_MODE (*op0))
922 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
923 {
924 *op0 = gen_lowpart (HImode, *op0);
925 *op1 = constm1_rtx;
926 }
927
928 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
929 if (GET_CODE (*op0) == UNSPEC
930 && XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT
931 && XVECLEN (*op0, 0) == 1
932 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
933 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
934 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
935 && *op1 == const0_rtx)
936 {
937 enum rtx_code new_code = UNKNOWN;
938 switch (*code)
939 {
940 case EQ: new_code = EQ; break;
941 case NE: new_code = NE; break;
942 case LT: new_code = GTU; break;
943 case GT: new_code = LTU; break;
944 case LE: new_code = GEU; break;
945 case GE: new_code = LEU; break;
946 default: break;
947 }
948
949 if (new_code != UNKNOWN)
950 {
951 *op0 = XVECEXP (*op0, 0, 0);
952 *code = new_code;
953 }
954 }
955
956 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
957 if (GET_CODE (*op0) == UNSPEC
958 && XINT (*op0, 1) == UNSPEC_CC_TO_INT
959 && XVECLEN (*op0, 0) == 1
960 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
961 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
962 && CONST_INT_P (*op1))
963 {
964 enum rtx_code new_code = UNKNOWN;
965 switch (GET_MODE (XVECEXP (*op0, 0, 0)))
966 {
967 case CCZmode:
968 case CCRAWmode:
969 switch (*code)
970 {
971 case EQ: new_code = EQ; break;
972 case NE: new_code = NE; break;
973 default: break;
974 }
975 break;
976 default: break;
977 }
978
979 if (new_code != UNKNOWN)
980 {
981 /* For CCRAWmode put the required cc mask into the second
982 operand. */
983 if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode
984 && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3)
985 *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));
986 *op0 = XVECEXP (*op0, 0, 0);
987 *code = new_code;
988 }
989 }
990
991 /* Simplify cascaded EQ, NE with const0_rtx. */
992 if ((*code == NE || *code == EQ)
993 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
994 && GET_MODE (*op0) == SImode
995 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
996 && REG_P (XEXP (*op0, 0))
997 && XEXP (*op0, 1) == const0_rtx
998 && *op1 == const0_rtx)
999 {
1000 if ((*code == EQ && GET_CODE (*op0) == NE)
1001 || (*code == NE && GET_CODE (*op0) == EQ))
1002 *code = EQ;
1003 else
1004 *code = NE;
1005 *op0 = XEXP (*op0, 0);
1006 }
1007
1008 /* Prefer register over memory as first operand. */
1009 if (MEM_P (*op0) && REG_P (*op1))
1010 {
1011 rtx tem = *op0; *op0 = *op1; *op1 = tem;
1012 *code = (int)swap_condition ((enum rtx_code)*code);
1013 }
1014 }
1015
1016 /* Emit a compare instruction suitable to implement the comparison
1017 OP0 CODE OP1. Return the correct condition RTL to be placed in
1018 the IF_THEN_ELSE of the conditional branch testing the result. */
1019
1020 rtx
1021 s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
1022 {
1023 machine_mode mode = s390_select_ccmode (code, op0, op1);
1024 rtx cc;
1025
1026 /* Do not output a redundant compare instruction if a compare_and_swap
1027 pattern already computed the result and the machine modes are compatible. */
1028 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
1029 {
1030 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
1031 == GET_MODE (op0));
1032 cc = op0;
1033 }
1034 else
1035 {
1036 cc = gen_rtx_REG (mode, CC_REGNUM);
1037 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
1038 }
1039
1040 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
1041 }
1042
1043 /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
1044 matches CMP.
1045 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1046 conditional branch testing the result. */
1047
1048 static rtx
1049 s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
1050 rtx cmp, rtx new_rtx)
1051 {
1052 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
1053 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
1054 const0_rtx);
1055 }
1056
1057 /* Emit a jump instruction to TARGET and return it. If COND is
1058 NULL_RTX, emit an unconditional jump, else a conditional jump under
1059 condition COND. */
1060
1061 rtx_insn *
1062 s390_emit_jump (rtx target, rtx cond)
1063 {
1064 rtx insn;
1065
1066 target = gen_rtx_LABEL_REF (VOIDmode, target);
1067 if (cond)
1068 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
1069
1070 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
1071 return emit_jump_insn (insn);
1072 }
1073
1074 /* Return branch condition mask to implement a branch
1075 specified by CODE. Return -1 for invalid comparisons. */
1076
1077 int
1078 s390_branch_condition_mask (rtx code)
1079 {
1080 const int CC0 = 1 << 3;
1081 const int CC1 = 1 << 2;
1082 const int CC2 = 1 << 1;
1083 const int CC3 = 1 << 0;
1084
1085 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
1086 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
1087 gcc_assert (XEXP (code, 1) == const0_rtx
1088 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1089 && CONST_INT_P (XEXP (code, 1))));
1090
1091
1092 switch (GET_MODE (XEXP (code, 0)))
1093 {
1094 case CCZmode:
1095 case CCZ1mode:
1096 switch (GET_CODE (code))
1097 {
1098 case EQ: return CC0;
1099 case NE: return CC1 | CC2 | CC3;
1100 default: return -1;
1101 }
1102 break;
1103
1104 case CCT1mode:
1105 switch (GET_CODE (code))
1106 {
1107 case EQ: return CC1;
1108 case NE: return CC0 | CC2 | CC3;
1109 default: return -1;
1110 }
1111 break;
1112
1113 case CCT2mode:
1114 switch (GET_CODE (code))
1115 {
1116 case EQ: return CC2;
1117 case NE: return CC0 | CC1 | CC3;
1118 default: return -1;
1119 }
1120 break;
1121
1122 case CCT3mode:
1123 switch (GET_CODE (code))
1124 {
1125 case EQ: return CC3;
1126 case NE: return CC0 | CC1 | CC2;
1127 default: return -1;
1128 }
1129 break;
1130
1131 case CCLmode:
1132 switch (GET_CODE (code))
1133 {
1134 case EQ: return CC0 | CC2;
1135 case NE: return CC1 | CC3;
1136 default: return -1;
1137 }
1138 break;
1139
1140 case CCL1mode:
1141 switch (GET_CODE (code))
1142 {
1143 case LTU: return CC2 | CC3; /* carry */
1144 case GEU: return CC0 | CC1; /* no carry */
1145 default: return -1;
1146 }
1147 break;
1148
1149 case CCL2mode:
1150 switch (GET_CODE (code))
1151 {
1152 case GTU: return CC0 | CC1; /* borrow */
1153 case LEU: return CC2 | CC3; /* no borrow */
1154 default: return -1;
1155 }
1156 break;
1157
1158 case CCL3mode:
1159 switch (GET_CODE (code))
1160 {
1161 case EQ: return CC0 | CC2;
1162 case NE: return CC1 | CC3;
1163 case LTU: return CC1;
1164 case GTU: return CC3;
1165 case LEU: return CC1 | CC2;
1166 case GEU: return CC2 | CC3;
1167 default: return -1;
1168 }
1169
1170 case CCUmode:
1171 switch (GET_CODE (code))
1172 {
1173 case EQ: return CC0;
1174 case NE: return CC1 | CC2 | CC3;
1175 case LTU: return CC1;
1176 case GTU: return CC2;
1177 case LEU: return CC0 | CC1;
1178 case GEU: return CC0 | CC2;
1179 default: return -1;
1180 }
1181 break;
1182
1183 case CCURmode:
1184 switch (GET_CODE (code))
1185 {
1186 case EQ: return CC0;
1187 case NE: return CC2 | CC1 | CC3;
1188 case LTU: return CC2;
1189 case GTU: return CC1;
1190 case LEU: return CC0 | CC2;
1191 case GEU: return CC0 | CC1;
1192 default: return -1;
1193 }
1194 break;
1195
1196 case CCAPmode:
1197 switch (GET_CODE (code))
1198 {
1199 case EQ: return CC0;
1200 case NE: return CC1 | CC2 | CC3;
1201 case LT: return CC1 | CC3;
1202 case GT: return CC2;
1203 case LE: return CC0 | CC1 | CC3;
1204 case GE: return CC0 | CC2;
1205 default: return -1;
1206 }
1207 break;
1208
1209 case CCANmode:
1210 switch (GET_CODE (code))
1211 {
1212 case EQ: return CC0;
1213 case NE: return CC1 | CC2 | CC3;
1214 case LT: return CC1;
1215 case GT: return CC2 | CC3;
1216 case LE: return CC0 | CC1;
1217 case GE: return CC0 | CC2 | CC3;
1218 default: return -1;
1219 }
1220 break;
1221
1222 case CCSmode:
1223 switch (GET_CODE (code))
1224 {
1225 case EQ: return CC0;
1226 case NE: return CC1 | CC2 | CC3;
1227 case LT: return CC1;
1228 case GT: return CC2;
1229 case LE: return CC0 | CC1;
1230 case GE: return CC0 | CC2;
1231 case UNORDERED: return CC3;
1232 case ORDERED: return CC0 | CC1 | CC2;
1233 case UNEQ: return CC0 | CC3;
1234 case UNLT: return CC1 | CC3;
1235 case UNGT: return CC2 | CC3;
1236 case UNLE: return CC0 | CC1 | CC3;
1237 case UNGE: return CC0 | CC2 | CC3;
1238 case LTGT: return CC1 | CC2;
1239 default: return -1;
1240 }
1241 break;
1242
1243 case CCSRmode:
1244 switch (GET_CODE (code))
1245 {
1246 case EQ: return CC0;
1247 case NE: return CC2 | CC1 | CC3;
1248 case LT: return CC2;
1249 case GT: return CC1;
1250 case LE: return CC0 | CC2;
1251 case GE: return CC0 | CC1;
1252 case UNORDERED: return CC3;
1253 case ORDERED: return CC0 | CC2 | CC1;
1254 case UNEQ: return CC0 | CC3;
1255 case UNLT: return CC2 | CC3;
1256 case UNGT: return CC1 | CC3;
1257 case UNLE: return CC0 | CC2 | CC3;
1258 case UNGE: return CC0 | CC1 | CC3;
1259 case LTGT: return CC2 | CC1;
1260 default: return -1;
1261 }
1262 break;
1263
1264 case CCRAWmode:
1265 switch (GET_CODE (code))
1266 {
1267 case EQ:
1268 return INTVAL (XEXP (code, 1));
1269 case NE:
1270 return (INTVAL (XEXP (code, 1))) ^ 0xf;
1271 default:
1272 gcc_unreachable ();
1273 }
1274
1275 default:
1276 return -1;
1277 }
1278 }
1279
1280
1281 /* Return branch condition mask to implement a compare and branch
1282 specified by CODE. Return -1 for invalid comparisons. */
1283
1284 int
1285 s390_compare_and_branch_condition_mask (rtx code)
1286 {
1287 const int CC0 = 1 << 3;
1288 const int CC1 = 1 << 2;
1289 const int CC2 = 1 << 1;
1290
1291 switch (GET_CODE (code))
1292 {
1293 case EQ:
1294 return CC0;
1295 case NE:
1296 return CC1 | CC2;
1297 case LT:
1298 case LTU:
1299 return CC1;
1300 case GT:
1301 case GTU:
1302 return CC2;
1303 case LE:
1304 case LEU:
1305 return CC0 | CC1;
1306 case GE:
1307 case GEU:
1308 return CC0 | CC2;
1309 default:
1310 gcc_unreachable ();
1311 }
1312 return -1;
1313 }
1314
1315 /* If INV is false, return assembler mnemonic string to implement
1316 a branch specified by CODE. If INV is true, return mnemonic
1317 for the corresponding inverted branch. */
1318
1319 static const char *
1320 s390_branch_condition_mnemonic (rtx code, int inv)
1321 {
1322 int mask;
1323
1324 static const char *const mnemonic[16] =
1325 {
1326 NULL, "o", "h", "nle",
1327 "l", "nhe", "lh", "ne",
1328 "e", "nlh", "he", "nl",
1329 "le", "nh", "no", NULL
1330 };
1331
1332 if (GET_CODE (XEXP (code, 0)) == REG
1333 && REGNO (XEXP (code, 0)) == CC_REGNUM
1334 && (XEXP (code, 1) == const0_rtx
1335 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1336 && CONST_INT_P (XEXP (code, 1)))))
1337 mask = s390_branch_condition_mask (code);
1338 else
1339 mask = s390_compare_and_branch_condition_mask (code);
1340
1341 gcc_assert (mask >= 0);
1342
1343 if (inv)
1344 mask ^= 15;
1345
1346 gcc_assert (mask >= 1 && mask <= 14);
1347
1348 return mnemonic[mask];
1349 }
1350
1351 /* Return the part of op which has a value different from def.
1352 The size of the part is determined by mode.
1353 Use this function only if you already know that op really
1354 contains such a part. */
1355
1356 unsigned HOST_WIDE_INT
1357 s390_extract_part (rtx op, machine_mode mode, int def)
1358 {
1359 unsigned HOST_WIDE_INT value = 0;
1360 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1361 int part_bits = GET_MODE_BITSIZE (mode);
1362 unsigned HOST_WIDE_INT part_mask
1363 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
1364 int i;
1365
1366 for (i = 0; i < max_parts; i++)
1367 {
1368 if (i == 0)
1369 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1370 else
1371 value >>= part_bits;
1372
1373 if ((value & part_mask) != (def & part_mask))
1374 return value & part_mask;
1375 }
1376
1377 gcc_unreachable ();
1378 }
1379
1380 /* If OP is an integer constant of mode MODE with exactly one
1381 part of mode PART_MODE unequal to DEF, return the number of that
1382 part. Otherwise, return -1. */
1383
1384 int
1385 s390_single_part (rtx op,
1386 machine_mode mode,
1387 machine_mode part_mode,
1388 int def)
1389 {
1390 unsigned HOST_WIDE_INT value = 0;
1391 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
1392 unsigned HOST_WIDE_INT part_mask
1393 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
1394 int i, part = -1;
1395
1396 if (GET_CODE (op) != CONST_INT)
1397 return -1;
1398
1399 for (i = 0; i < n_parts; i++)
1400 {
1401 if (i == 0)
1402 value = (unsigned HOST_WIDE_INT) INTVAL (op);
1403 else
1404 value >>= GET_MODE_BITSIZE (part_mode);
1405
1406 if ((value & part_mask) != (def & part_mask))
1407 {
1408 if (part != -1)
1409 return -1;
1410 else
1411 part = i;
1412 }
1413 }
1414 return part == -1 ? -1 : n_parts - 1 - part;
1415 }
1416
1417 /* Return true if IN contains a contiguous bitfield in the lower SIZE
1418 bits and no other bits are set in IN. POS and LENGTH can be used
1419 to obtain the start position and the length of the bitfield.
1420
1421 POS gives the position of the first bit of the bitfield counting
1422 from the lowest order bit starting with zero. In order to use this
1423 value for S/390 instructions this has to be converted to "bits big
1424 endian" style. */
1425
1426 bool
1427 s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1428 int *pos, int *length)
1429 {
1430 int tmp_pos = 0;
1431 int tmp_length = 0;
1432 int i;
1433 unsigned HOST_WIDE_INT mask = 1ULL;
1434 bool contiguous = false;
1435
1436 for (i = 0; i < size; mask <<= 1, i++)
1437 {
1438 if (contiguous)
1439 {
1440 if (mask & in)
1441 tmp_length++;
1442 else
1443 break;
1444 }
1445 else
1446 {
1447 if (mask & in)
1448 {
1449 contiguous = true;
1450 tmp_length++;
1451 }
1452 else
1453 tmp_pos++;
1454 }
1455 }
1456
1457 if (!tmp_length)
1458 return false;
1459
1460 /* Calculate a mask for all bits beyond the contiguous bits. */
1461 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1462
1463 if (mask & in)
1464 return false;
1465
1466 if (tmp_length + tmp_pos - 1 > size)
1467 return false;
1468
1469 if (length)
1470 *length = tmp_length;
1471
1472 if (pos)
1473 *pos = tmp_pos;
1474
1475 return true;
1476 }
1477
1478 /* Check whether a rotate of ROTL followed by an AND of CONTIG is
1479 equivalent to a shift followed by the AND. In particular, CONTIG
1480 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
1481 for ROTL indicate a rotate to the right. */
1482
1483 bool
1484 s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
1485 {
1486 int pos, len;
1487 bool ok;
1488
1489 ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
1490 gcc_assert (ok);
1491
1492 return ((rotl >= 0 && rotl <= pos)
1493 || (rotl < 0 && -rotl <= bitsize - len - pos));
1494 }
1495
1496 /* Check whether we can (and want to) split a double-word
1497 move in mode MODE from SRC to DST into two single-word
1498 moves, moving the subword FIRST_SUBWORD first. */
1499
1500 bool
1501 s390_split_ok_p (rtx dst, rtx src, machine_mode mode, int first_subword)
1502 {
1503 /* Floating point registers cannot be split. */
1504 if (FP_REG_P (src) || FP_REG_P (dst))
1505 return false;
1506
1507 /* We don't need to split if operands are directly accessible. */
1508 if (s_operand (src, mode) || s_operand (dst, mode))
1509 return false;
1510
1511 /* Non-offsettable memory references cannot be split. */
1512 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1513 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1514 return false;
1515
1516 /* Moving the first subword must not clobber a register
1517 needed to move the second subword. */
1518 if (register_operand (dst, mode))
1519 {
1520 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1521 if (reg_overlap_mentioned_p (subreg, src))
1522 return false;
1523 }
1524
1525 return true;
1526 }
1527
1528 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1529 and [MEM2, MEM2 + SIZE] do overlap and false
1530 otherwise. */
1531
1532 bool
1533 s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1534 {
1535 rtx addr1, addr2, addr_delta;
1536 HOST_WIDE_INT delta;
1537
1538 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1539 return true;
1540
1541 if (size == 0)
1542 return false;
1543
1544 addr1 = XEXP (mem1, 0);
1545 addr2 = XEXP (mem2, 0);
1546
1547 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1548
1549 /* This overlapping check is used by peepholes merging memory block operations.
1550 Overlapping operations would otherwise be recognized by the S/390 hardware
1551 and would fall back to a slower implementation. Allowing overlapping
1552 operations would lead to slow code but not to wrong code. Therefore we are
1553 somewhat optimistic if we cannot prove that the memory blocks are
1554 overlapping.
1555 That's why we return false here although this may accept operations on
1556 overlapping memory areas. */
1557 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1558 return false;
1559
1560 delta = INTVAL (addr_delta);
1561
1562 if (delta == 0
1563 || (delta > 0 && delta < size)
1564 || (delta < 0 && -delta < size))
1565 return true;
1566
1567 return false;
1568 }
1569
1570 /* Check whether the address of memory reference MEM2 equals exactly
1571 the address of memory reference MEM1 plus DELTA. Return true if
1572 we can prove this to be the case, false otherwise. */
1573
1574 bool
1575 s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1576 {
1577 rtx addr1, addr2, addr_delta;
1578
1579 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1580 return false;
1581
1582 addr1 = XEXP (mem1, 0);
1583 addr2 = XEXP (mem2, 0);
1584
1585 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1586 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1587 return false;
1588
1589 return true;
1590 }
1591
1592 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1593
1594 void
1595 s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
1596 rtx *operands)
1597 {
1598 machine_mode wmode = mode;
1599 rtx dst = operands[0];
1600 rtx src1 = operands[1];
1601 rtx src2 = operands[2];
1602 rtx op, clob, tem;
1603
1604 /* If we cannot handle the operation directly, use a temp register. */
1605 if (!s390_logical_operator_ok_p (operands))
1606 dst = gen_reg_rtx (mode);
1607
1608 /* QImode and HImode patterns make sense only if we have a destination
1609 in memory. Otherwise perform the operation in SImode. */
1610 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1611 wmode = SImode;
1612
1613 /* Widen operands if required. */
1614 if (mode != wmode)
1615 {
1616 if (GET_CODE (dst) == SUBREG
1617 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1618 dst = tem;
1619 else if (REG_P (dst))
1620 dst = gen_rtx_SUBREG (wmode, dst, 0);
1621 else
1622 dst = gen_reg_rtx (wmode);
1623
1624 if (GET_CODE (src1) == SUBREG
1625 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1626 src1 = tem;
1627 else if (GET_MODE (src1) != VOIDmode)
1628 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1629
1630 if (GET_CODE (src2) == SUBREG
1631 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1632 src2 = tem;
1633 else if (GET_MODE (src2) != VOIDmode)
1634 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1635 }
1636
1637 /* Emit the instruction. */
1638 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1639 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1640 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1641
1642 /* Fix up the destination if needed. */
1643 if (dst != operands[0])
1644 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1645 }
1646
1647 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1648
1649 bool
1650 s390_logical_operator_ok_p (rtx *operands)
1651 {
1652 /* If the destination operand is in memory, it needs to coincide
1653 with one of the source operands. After reload, it has to be
1654 the first source operand. */
1655 if (GET_CODE (operands[0]) == MEM)
1656 return rtx_equal_p (operands[0], operands[1])
1657 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1658
1659 return true;
1660 }
1661
1662 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1663 operand IMMOP to switch from SS to SI type instructions. */
1664
1665 void
1666 s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1667 {
1668 int def = code == AND ? -1 : 0;
1669 HOST_WIDE_INT mask;
1670 int part;
1671
1672 gcc_assert (GET_CODE (*memop) == MEM);
1673 gcc_assert (!MEM_VOLATILE_P (*memop));
1674
1675 mask = s390_extract_part (*immop, QImode, def);
1676 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1677 gcc_assert (part >= 0);
1678
1679 *memop = adjust_address (*memop, QImode, part);
1680 *immop = gen_int_mode (mask, QImode);
1681 }
1682
1683
1684 /* How to allocate a 'struct machine_function'. */
1685
1686 static struct machine_function *
1687 s390_init_machine_status (void)
1688 {
1689 return ggc_cleared_alloc<machine_function> ();
1690 }
1691
1692 /* Map for smallest class containing reg regno. */
1693
1694 const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
1695 { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1696 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1697 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1698 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1699 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1700 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1701 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1702 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1703 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1704 ACCESS_REGS, ACCESS_REGS
1705 };
1706
1707 /* Return attribute type of insn. */
1708
1709 static enum attr_type
1710 s390_safe_attr_type (rtx_insn *insn)
1711 {
1712 if (recog_memoized (insn) >= 0)
1713 return get_attr_type (insn);
1714 else
1715 return TYPE_NONE;
1716 }
1717
1718 /* Return true if DISP is a valid short displacement. */
1719
1720 static bool
1721 s390_short_displacement (rtx disp)
1722 {
1723 /* No displacement is OK. */
1724 if (!disp)
1725 return true;
1726
1727 /* Without the long displacement facility we don't need to
1728 distingiush between long and short displacement. */
1729 if (!TARGET_LONG_DISPLACEMENT)
1730 return true;
1731
1732 /* Integer displacement in range. */
1733 if (GET_CODE (disp) == CONST_INT)
1734 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1735
1736 /* GOT offset is not OK, the GOT can be large. */
1737 if (GET_CODE (disp) == CONST
1738 && GET_CODE (XEXP (disp, 0)) == UNSPEC
1739 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1740 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
1741 return false;
1742
1743 /* All other symbolic constants are literal pool references,
1744 which are OK as the literal pool must be small. */
1745 if (GET_CODE (disp) == CONST)
1746 return true;
1747
1748 return false;
1749 }
1750
1751 /* Decompose a RTL expression ADDR for a memory address into
1752 its components, returned in OUT.
1753
1754 Returns false if ADDR is not a valid memory address, true
1755 otherwise. If OUT is NULL, don't return the components,
1756 but check for validity only.
1757
1758 Note: Only addresses in canonical form are recognized.
1759 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1760 canonical form so that they will be recognized. */
1761
1762 static int
1763 s390_decompose_address (rtx addr, struct s390_address *out)
1764 {
1765 HOST_WIDE_INT offset = 0;
1766 rtx base = NULL_RTX;
1767 rtx indx = NULL_RTX;
1768 rtx disp = NULL_RTX;
1769 rtx orig_disp;
1770 bool pointer = false;
1771 bool base_ptr = false;
1772 bool indx_ptr = false;
1773 bool literal_pool = false;
1774
1775 /* We may need to substitute the literal pool base register into the address
1776 below. However, at this point we do not know which register is going to
1777 be used as base, so we substitute the arg pointer register. This is going
1778 to be treated as holding a pointer below -- it shouldn't be used for any
1779 other purpose. */
1780 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
1781
1782 /* Decompose address into base + index + displacement. */
1783
1784 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1785 base = addr;
1786
1787 else if (GET_CODE (addr) == PLUS)
1788 {
1789 rtx op0 = XEXP (addr, 0);
1790 rtx op1 = XEXP (addr, 1);
1791 enum rtx_code code0 = GET_CODE (op0);
1792 enum rtx_code code1 = GET_CODE (op1);
1793
1794 if (code0 == REG || code0 == UNSPEC)
1795 {
1796 if (code1 == REG || code1 == UNSPEC)
1797 {
1798 indx = op0; /* index + base */
1799 base = op1;
1800 }
1801
1802 else
1803 {
1804 base = op0; /* base + displacement */
1805 disp = op1;
1806 }
1807 }
1808
1809 else if (code0 == PLUS)
1810 {
1811 indx = XEXP (op0, 0); /* index + base + disp */
1812 base = XEXP (op0, 1);
1813 disp = op1;
1814 }
1815
1816 else
1817 {
1818 return false;
1819 }
1820 }
1821
1822 else
1823 disp = addr; /* displacement */
1824
1825 /* Extract integer part of displacement. */
1826 orig_disp = disp;
1827 if (disp)
1828 {
1829 if (GET_CODE (disp) == CONST_INT)
1830 {
1831 offset = INTVAL (disp);
1832 disp = NULL_RTX;
1833 }
1834 else if (GET_CODE (disp) == CONST
1835 && GET_CODE (XEXP (disp, 0)) == PLUS
1836 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1837 {
1838 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1839 disp = XEXP (XEXP (disp, 0), 0);
1840 }
1841 }
1842
1843 /* Strip off CONST here to avoid special case tests later. */
1844 if (disp && GET_CODE (disp) == CONST)
1845 disp = XEXP (disp, 0);
1846
1847 /* We can convert literal pool addresses to
1848 displacements by basing them off the base register. */
1849 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1850 {
1851 /* Either base or index must be free to hold the base register. */
1852 if (!base)
1853 base = fake_pool_base, literal_pool = true;
1854 else if (!indx)
1855 indx = fake_pool_base, literal_pool = true;
1856 else
1857 return false;
1858
1859 /* Mark up the displacement. */
1860 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1861 UNSPEC_LTREL_OFFSET);
1862 }
1863
1864 /* Validate base register. */
1865 if (base)
1866 {
1867 if (GET_CODE (base) == UNSPEC)
1868 switch (XINT (base, 1))
1869 {
1870 case UNSPEC_LTREF:
1871 if (!disp)
1872 disp = gen_rtx_UNSPEC (Pmode,
1873 gen_rtvec (1, XVECEXP (base, 0, 0)),
1874 UNSPEC_LTREL_OFFSET);
1875 else
1876 return false;
1877
1878 base = XVECEXP (base, 0, 1);
1879 break;
1880
1881 case UNSPEC_LTREL_BASE:
1882 if (XVECLEN (base, 0) == 1)
1883 base = fake_pool_base, literal_pool = true;
1884 else
1885 base = XVECEXP (base, 0, 1);
1886 break;
1887
1888 default:
1889 return false;
1890 }
1891
1892 if (!REG_P (base)
1893 || (GET_MODE (base) != SImode
1894 && GET_MODE (base) != Pmode))
1895 return false;
1896
1897 if (REGNO (base) == STACK_POINTER_REGNUM
1898 || REGNO (base) == FRAME_POINTER_REGNUM
1899 || ((reload_completed || reload_in_progress)
1900 && frame_pointer_needed
1901 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1902 || REGNO (base) == ARG_POINTER_REGNUM
1903 || (flag_pic
1904 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
1905 pointer = base_ptr = true;
1906
1907 if ((reload_completed || reload_in_progress)
1908 && base == cfun->machine->base_reg)
1909 pointer = base_ptr = literal_pool = true;
1910 }
1911
1912 /* Validate index register. */
1913 if (indx)
1914 {
1915 if (GET_CODE (indx) == UNSPEC)
1916 switch (XINT (indx, 1))
1917 {
1918 case UNSPEC_LTREF:
1919 if (!disp)
1920 disp = gen_rtx_UNSPEC (Pmode,
1921 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1922 UNSPEC_LTREL_OFFSET);
1923 else
1924 return false;
1925
1926 indx = XVECEXP (indx, 0, 1);
1927 break;
1928
1929 case UNSPEC_LTREL_BASE:
1930 if (XVECLEN (indx, 0) == 1)
1931 indx = fake_pool_base, literal_pool = true;
1932 else
1933 indx = XVECEXP (indx, 0, 1);
1934 break;
1935
1936 default:
1937 return false;
1938 }
1939
1940 if (!REG_P (indx)
1941 || (GET_MODE (indx) != SImode
1942 && GET_MODE (indx) != Pmode))
1943 return false;
1944
1945 if (REGNO (indx) == STACK_POINTER_REGNUM
1946 || REGNO (indx) == FRAME_POINTER_REGNUM
1947 || ((reload_completed || reload_in_progress)
1948 && frame_pointer_needed
1949 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1950 || REGNO (indx) == ARG_POINTER_REGNUM
1951 || (flag_pic
1952 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
1953 pointer = indx_ptr = true;
1954
1955 if ((reload_completed || reload_in_progress)
1956 && indx == cfun->machine->base_reg)
1957 pointer = indx_ptr = literal_pool = true;
1958 }
1959
1960 /* Prefer to use pointer as base, not index. */
1961 if (base && indx && !base_ptr
1962 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1963 {
1964 rtx tmp = base;
1965 base = indx;
1966 indx = tmp;
1967 }
1968
1969 /* Validate displacement. */
1970 if (!disp)
1971 {
1972 /* If virtual registers are involved, the displacement will change later
1973 anyway as the virtual registers get eliminated. This could make a
1974 valid displacement invalid, but it is more likely to make an invalid
1975 displacement valid, because we sometimes access the register save area
1976 via negative offsets to one of those registers.
1977 Thus we don't check the displacement for validity here. If after
1978 elimination the displacement turns out to be invalid after all,
1979 this is fixed up by reload in any case. */
1980 /* LRA maintains always displacements up to date and we need to
1981 know the displacement is right during all LRA not only at the
1982 final elimination. */
1983 if (lra_in_progress
1984 || (base != arg_pointer_rtx
1985 && indx != arg_pointer_rtx
1986 && base != return_address_pointer_rtx
1987 && indx != return_address_pointer_rtx
1988 && base != frame_pointer_rtx
1989 && indx != frame_pointer_rtx
1990 && base != virtual_stack_vars_rtx
1991 && indx != virtual_stack_vars_rtx))
1992 if (!DISP_IN_RANGE (offset))
1993 return false;
1994 }
1995 else
1996 {
1997 /* All the special cases are pointers. */
1998 pointer = true;
1999
2000 /* In the small-PIC case, the linker converts @GOT
2001 and @GOTNTPOFF offsets to possible displacements. */
2002 if (GET_CODE (disp) == UNSPEC
2003 && (XINT (disp, 1) == UNSPEC_GOT
2004 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
2005 && flag_pic == 1)
2006 {
2007 ;
2008 }
2009
2010 /* Accept pool label offsets. */
2011 else if (GET_CODE (disp) == UNSPEC
2012 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2013 ;
2014
2015 /* Accept literal pool references. */
2016 else if (GET_CODE (disp) == UNSPEC
2017 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2018 {
2019 /* In case CSE pulled a non literal pool reference out of
2020 the pool we have to reject the address. This is
2021 especially important when loading the GOT pointer on non
2022 zarch CPUs. In this case the literal pool contains an lt
2023 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2024 will most likely exceed the displacement. */
2025 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2026 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2027 return false;
2028
2029 orig_disp = gen_rtx_CONST (Pmode, disp);
2030 if (offset)
2031 {
2032 /* If we have an offset, make sure it does not
2033 exceed the size of the constant pool entry. */
2034 rtx sym = XVECEXP (disp, 0, 0);
2035 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
2036 return false;
2037
2038 orig_disp = plus_constant (Pmode, orig_disp, offset);
2039 }
2040 }
2041
2042 else
2043 return false;
2044 }
2045
2046 if (!base && !indx)
2047 pointer = true;
2048
2049 if (out)
2050 {
2051 out->base = base;
2052 out->indx = indx;
2053 out->disp = orig_disp;
2054 out->pointer = pointer;
2055 out->literal_pool = literal_pool;
2056 }
2057
2058 return true;
2059 }
2060
2061 /* Decompose a RTL expression OP for a shift count into its components,
2062 and return the base register in BASE and the offset in OFFSET.
2063
2064 Return true if OP is a valid shift count, false if not. */
2065
2066 bool
2067 s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
2068 {
2069 HOST_WIDE_INT off = 0;
2070
2071 /* We can have an integer constant, an address register,
2072 or a sum of the two. */
2073 if (GET_CODE (op) == CONST_INT)
2074 {
2075 off = INTVAL (op);
2076 op = NULL_RTX;
2077 }
2078 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2079 {
2080 off = INTVAL (XEXP (op, 1));
2081 op = XEXP (op, 0);
2082 }
2083 while (op && GET_CODE (op) == SUBREG)
2084 op = SUBREG_REG (op);
2085
2086 if (op && GET_CODE (op) != REG)
2087 return false;
2088
2089 if (offset)
2090 *offset = off;
2091 if (base)
2092 *base = op;
2093
2094 return true;
2095 }
2096
2097
2098 /* Return true if CODE is a valid address without index. */
2099
2100 bool
2101 s390_legitimate_address_without_index_p (rtx op)
2102 {
2103 struct s390_address addr;
2104
2105 if (!s390_decompose_address (XEXP (op, 0), &addr))
2106 return false;
2107 if (addr.indx)
2108 return false;
2109
2110 return true;
2111 }
2112
2113
2114 /* Return TRUE if ADDR is an operand valid for a load/store relative
2115 instruction. Be aware that the alignment of the operand needs to
2116 be checked separately.
2117 Valid addresses are single references or a sum of a reference and a
2118 constant integer. Return these parts in SYMREF and ADDEND. You can
2119 pass NULL in REF and/or ADDEND if you are not interested in these
2120 values. Literal pool references are *not* considered symbol
2121 references. */
2122
2123 static bool
2124 s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
2125 {
2126 HOST_WIDE_INT tmpaddend = 0;
2127
2128 if (GET_CODE (addr) == CONST)
2129 addr = XEXP (addr, 0);
2130
2131 if (GET_CODE (addr) == PLUS)
2132 {
2133 if (!CONST_INT_P (XEXP (addr, 1)))
2134 return false;
2135
2136 tmpaddend = INTVAL (XEXP (addr, 1));
2137 addr = XEXP (addr, 0);
2138 }
2139
2140 if ((GET_CODE (addr) == SYMBOL_REF && !CONSTANT_POOL_ADDRESS_P (addr))
2141 || (GET_CODE (addr) == UNSPEC
2142 && (XINT (addr, 1) == UNSPEC_GOTENT
2143 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
2144 {
2145 if (symref)
2146 *symref = addr;
2147 if (addend)
2148 *addend = tmpaddend;
2149
2150 return true;
2151 }
2152 return false;
2153 }
2154
2155 /* Return true if the address in OP is valid for constraint letter C
2156 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2157 pool MEMs should be accepted. Only the Q, R, S, T constraint
2158 letters are allowed for C. */
2159
2160 static int
2161 s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2162 {
2163 struct s390_address addr;
2164 bool decomposed = false;
2165
2166 /* This check makes sure that no symbolic address (except literal
2167 pool references) are accepted by the R or T constraints. */
2168 if (s390_loadrelative_operand_p (op, NULL, NULL))
2169 return 0;
2170
2171 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2172 if (!lit_pool_ok)
2173 {
2174 if (!s390_decompose_address (op, &addr))
2175 return 0;
2176 if (addr.literal_pool)
2177 return 0;
2178 decomposed = true;
2179 }
2180
2181 switch (c)
2182 {
2183 case 'Q': /* no index short displacement */
2184 if (!decomposed && !s390_decompose_address (op, &addr))
2185 return 0;
2186 if (addr.indx)
2187 return 0;
2188 if (!s390_short_displacement (addr.disp))
2189 return 0;
2190 break;
2191
2192 case 'R': /* with index short displacement */
2193 if (TARGET_LONG_DISPLACEMENT)
2194 {
2195 if (!decomposed && !s390_decompose_address (op, &addr))
2196 return 0;
2197 if (!s390_short_displacement (addr.disp))
2198 return 0;
2199 }
2200 /* Any invalid address here will be fixed up by reload,
2201 so accept it for the most generic constraint. */
2202 break;
2203
2204 case 'S': /* no index long displacement */
2205 if (!TARGET_LONG_DISPLACEMENT)
2206 return 0;
2207 if (!decomposed && !s390_decompose_address (op, &addr))
2208 return 0;
2209 if (addr.indx)
2210 return 0;
2211 if (s390_short_displacement (addr.disp))
2212 return 0;
2213 break;
2214
2215 case 'T': /* with index long displacement */
2216 if (!TARGET_LONG_DISPLACEMENT)
2217 return 0;
2218 /* Any invalid address here will be fixed up by reload,
2219 so accept it for the most generic constraint. */
2220 if ((decomposed || s390_decompose_address (op, &addr))
2221 && s390_short_displacement (addr.disp))
2222 return 0;
2223 break;
2224 default:
2225 return 0;
2226 }
2227 return 1;
2228 }
2229
2230
2231 /* Evaluates constraint strings described by the regular expression
2232 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2233 the constraint given in STR, or 0 else. */
2234
2235 int
2236 s390_mem_constraint (const char *str, rtx op)
2237 {
2238 char c = str[0];
2239
2240 switch (c)
2241 {
2242 case 'A':
2243 /* Check for offsettable variants of memory constraints. */
2244 if (!MEM_P (op) || MEM_VOLATILE_P (op))
2245 return 0;
2246 if ((reload_completed || reload_in_progress)
2247 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
2248 return 0;
2249 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2250 case 'B':
2251 /* Check for non-literal-pool variants of memory constraints. */
2252 if (!MEM_P (op))
2253 return 0;
2254 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2255 case 'Q':
2256 case 'R':
2257 case 'S':
2258 case 'T':
2259 if (GET_CODE (op) != MEM)
2260 return 0;
2261 return s390_check_qrst_address (c, XEXP (op, 0), true);
2262 case 'U':
2263 return (s390_check_qrst_address ('Q', op, true)
2264 || s390_check_qrst_address ('R', op, true));
2265 case 'W':
2266 return (s390_check_qrst_address ('S', op, true)
2267 || s390_check_qrst_address ('T', op, true));
2268 case 'Y':
2269 /* Simply check for the basic form of a shift count. Reload will
2270 take care of making sure we have a proper base register. */
2271 if (!s390_decompose_shift_count (op, NULL, NULL))
2272 return 0;
2273 break;
2274 case 'Z':
2275 return s390_check_qrst_address (str[1], op, true);
2276 default:
2277 return 0;
2278 }
2279 return 1;
2280 }
2281
2282
2283 /* Evaluates constraint strings starting with letter O. Input
2284 parameter C is the second letter following the "O" in the constraint
2285 string. Returns 1 if VALUE meets the respective constraint and 0
2286 otherwise. */
2287
2288 int
2289 s390_O_constraint_str (const char c, HOST_WIDE_INT value)
2290 {
2291 if (!TARGET_EXTIMM)
2292 return 0;
2293
2294 switch (c)
2295 {
2296 case 's':
2297 return trunc_int_for_mode (value, SImode) == value;
2298
2299 case 'p':
2300 return value == 0
2301 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2302
2303 case 'n':
2304 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
2305
2306 default:
2307 gcc_unreachable ();
2308 }
2309 }
2310
2311
2312 /* Evaluates constraint strings starting with letter N. Parameter STR
2313 contains the letters following letter "N" in the constraint string.
2314 Returns true if VALUE matches the constraint. */
2315
2316 int
2317 s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
2318 {
2319 machine_mode mode, part_mode;
2320 int def;
2321 int part, part_goal;
2322
2323
2324 if (str[0] == 'x')
2325 part_goal = -1;
2326 else
2327 part_goal = str[0] - '0';
2328
2329 switch (str[1])
2330 {
2331 case 'Q':
2332 part_mode = QImode;
2333 break;
2334 case 'H':
2335 part_mode = HImode;
2336 break;
2337 case 'S':
2338 part_mode = SImode;
2339 break;
2340 default:
2341 return 0;
2342 }
2343
2344 switch (str[2])
2345 {
2346 case 'H':
2347 mode = HImode;
2348 break;
2349 case 'S':
2350 mode = SImode;
2351 break;
2352 case 'D':
2353 mode = DImode;
2354 break;
2355 default:
2356 return 0;
2357 }
2358
2359 switch (str[3])
2360 {
2361 case '0':
2362 def = 0;
2363 break;
2364 case 'F':
2365 def = -1;
2366 break;
2367 default:
2368 return 0;
2369 }
2370
2371 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2372 return 0;
2373
2374 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2375 if (part < 0)
2376 return 0;
2377 if (part_goal != -1 && part_goal != part)
2378 return 0;
2379
2380 return 1;
2381 }
2382
2383
2384 /* Returns true if the input parameter VALUE is a float zero. */
2385
2386 int
2387 s390_float_const_zero_p (rtx value)
2388 {
2389 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2390 && value == CONST0_RTX (GET_MODE (value)));
2391 }
2392
2393 /* Implement TARGET_REGISTER_MOVE_COST. */
2394
2395 static int
2396 s390_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
2397 reg_class_t from, reg_class_t to)
2398 {
2399 /* On s390, copy between fprs and gprs is expensive as long as no
2400 ldgr/lgdr can be used. */
2401 if ((!TARGET_Z10 || GET_MODE_SIZE (mode) != 8)
2402 && ((reg_classes_intersect_p (from, GENERAL_REGS)
2403 && reg_classes_intersect_p (to, FP_REGS))
2404 || (reg_classes_intersect_p (from, FP_REGS)
2405 && reg_classes_intersect_p (to, GENERAL_REGS))))
2406 return 10;
2407
2408 return 1;
2409 }
2410
2411 /* Implement TARGET_MEMORY_MOVE_COST. */
2412
2413 static int
2414 s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
2415 reg_class_t rclass ATTRIBUTE_UNUSED,
2416 bool in ATTRIBUTE_UNUSED)
2417 {
2418 return 1;
2419 }
2420
2421 /* Compute a (partial) cost for rtx X. Return true if the complete
2422 cost has been computed, and false if subexpressions should be
2423 scanned. In either case, *TOTAL contains the cost result.
2424 CODE contains GET_CODE (x), OUTER_CODE contains the code
2425 of the superexpression of x. */
2426
2427 static bool
2428 s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2429 int *total, bool speed ATTRIBUTE_UNUSED)
2430 {
2431 switch (code)
2432 {
2433 case CONST:
2434 case CONST_INT:
2435 case LABEL_REF:
2436 case SYMBOL_REF:
2437 case CONST_DOUBLE:
2438 case MEM:
2439 *total = 0;
2440 return true;
2441
2442 case ASHIFT:
2443 case ASHIFTRT:
2444 case LSHIFTRT:
2445 case ROTATE:
2446 case ROTATERT:
2447 case AND:
2448 case IOR:
2449 case XOR:
2450 case NEG:
2451 case NOT:
2452 *total = COSTS_N_INSNS (1);
2453 return false;
2454
2455 case PLUS:
2456 case MINUS:
2457 *total = COSTS_N_INSNS (1);
2458 return false;
2459
2460 case MULT:
2461 switch (GET_MODE (x))
2462 {
2463 case SImode:
2464 {
2465 rtx left = XEXP (x, 0);
2466 rtx right = XEXP (x, 1);
2467 if (GET_CODE (right) == CONST_INT
2468 && CONST_OK_FOR_K (INTVAL (right)))
2469 *total = s390_cost->mhi;
2470 else if (GET_CODE (left) == SIGN_EXTEND)
2471 *total = s390_cost->mh;
2472 else
2473 *total = s390_cost->ms; /* msr, ms, msy */
2474 break;
2475 }
2476 case DImode:
2477 {
2478 rtx left = XEXP (x, 0);
2479 rtx right = XEXP (x, 1);
2480 if (TARGET_ZARCH)
2481 {
2482 if (GET_CODE (right) == CONST_INT
2483 && CONST_OK_FOR_K (INTVAL (right)))
2484 *total = s390_cost->mghi;
2485 else if (GET_CODE (left) == SIGN_EXTEND)
2486 *total = s390_cost->msgf;
2487 else
2488 *total = s390_cost->msg; /* msgr, msg */
2489 }
2490 else /* TARGET_31BIT */
2491 {
2492 if (GET_CODE (left) == SIGN_EXTEND
2493 && GET_CODE (right) == SIGN_EXTEND)
2494 /* mulsidi case: mr, m */
2495 *total = s390_cost->m;
2496 else if (GET_CODE (left) == ZERO_EXTEND
2497 && GET_CODE (right) == ZERO_EXTEND
2498 && TARGET_CPU_ZARCH)
2499 /* umulsidi case: ml, mlr */
2500 *total = s390_cost->ml;
2501 else
2502 /* Complex calculation is required. */
2503 *total = COSTS_N_INSNS (40);
2504 }
2505 break;
2506 }
2507 case SFmode:
2508 case DFmode:
2509 *total = s390_cost->mult_df;
2510 break;
2511 case TFmode:
2512 *total = s390_cost->mxbr;
2513 break;
2514 default:
2515 return false;
2516 }
2517 return false;
2518
2519 case FMA:
2520 switch (GET_MODE (x))
2521 {
2522 case DFmode:
2523 *total = s390_cost->madbr;
2524 break;
2525 case SFmode:
2526 *total = s390_cost->maebr;
2527 break;
2528 default:
2529 return false;
2530 }
2531 /* Negate in the third argument is free: FMSUB. */
2532 if (GET_CODE (XEXP (x, 2)) == NEG)
2533 {
2534 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2535 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2536 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
2537 return true;
2538 }
2539 return false;
2540
2541 case UDIV:
2542 case UMOD:
2543 if (GET_MODE (x) == TImode) /* 128 bit division */
2544 *total = s390_cost->dlgr;
2545 else if (GET_MODE (x) == DImode)
2546 {
2547 rtx right = XEXP (x, 1);
2548 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2549 *total = s390_cost->dlr;
2550 else /* 64 by 64 bit division */
2551 *total = s390_cost->dlgr;
2552 }
2553 else if (GET_MODE (x) == SImode) /* 32 bit division */
2554 *total = s390_cost->dlr;
2555 return false;
2556
2557 case DIV:
2558 case MOD:
2559 if (GET_MODE (x) == DImode)
2560 {
2561 rtx right = XEXP (x, 1);
2562 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2563 if (TARGET_ZARCH)
2564 *total = s390_cost->dsgfr;
2565 else
2566 *total = s390_cost->dr;
2567 else /* 64 by 64 bit division */
2568 *total = s390_cost->dsgr;
2569 }
2570 else if (GET_MODE (x) == SImode) /* 32 bit division */
2571 *total = s390_cost->dlr;
2572 else if (GET_MODE (x) == SFmode)
2573 {
2574 *total = s390_cost->debr;
2575 }
2576 else if (GET_MODE (x) == DFmode)
2577 {
2578 *total = s390_cost->ddbr;
2579 }
2580 else if (GET_MODE (x) == TFmode)
2581 {
2582 *total = s390_cost->dxbr;
2583 }
2584 return false;
2585
2586 case SQRT:
2587 if (GET_MODE (x) == SFmode)
2588 *total = s390_cost->sqebr;
2589 else if (GET_MODE (x) == DFmode)
2590 *total = s390_cost->sqdbr;
2591 else /* TFmode */
2592 *total = s390_cost->sqxbr;
2593 return false;
2594
2595 case SIGN_EXTEND:
2596 case ZERO_EXTEND:
2597 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2598 || outer_code == PLUS || outer_code == MINUS
2599 || outer_code == COMPARE)
2600 *total = 0;
2601 return false;
2602
2603 case COMPARE:
2604 *total = COSTS_N_INSNS (1);
2605 if (GET_CODE (XEXP (x, 0)) == AND
2606 && GET_CODE (XEXP (x, 1)) == CONST_INT
2607 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2608 {
2609 rtx op0 = XEXP (XEXP (x, 0), 0);
2610 rtx op1 = XEXP (XEXP (x, 0), 1);
2611 rtx op2 = XEXP (x, 1);
2612
2613 if (memory_operand (op0, GET_MODE (op0))
2614 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2615 return true;
2616 if (register_operand (op0, GET_MODE (op0))
2617 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2618 return true;
2619 }
2620 return false;
2621
2622 default:
2623 return false;
2624 }
2625 }
2626
2627 /* Return the cost of an address rtx ADDR. */
2628
2629 static int
2630 s390_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED,
2631 addr_space_t as ATTRIBUTE_UNUSED,
2632 bool speed ATTRIBUTE_UNUSED)
2633 {
2634 struct s390_address ad;
2635 if (!s390_decompose_address (addr, &ad))
2636 return 1000;
2637
2638 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2639 }
2640
2641 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2642 otherwise return 0. */
2643
2644 int
2645 tls_symbolic_operand (rtx op)
2646 {
2647 if (GET_CODE (op) != SYMBOL_REF)
2648 return 0;
2649 return SYMBOL_REF_TLS_MODEL (op);
2650 }
2651 \f
2652 /* Split DImode access register reference REG (on 64-bit) into its constituent
2653 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2654 gen_highpart cannot be used as they assume all registers are word-sized,
2655 while our access registers have only half that size. */
2656
2657 void
2658 s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2659 {
2660 gcc_assert (TARGET_64BIT);
2661 gcc_assert (ACCESS_REG_P (reg));
2662 gcc_assert (GET_MODE (reg) == DImode);
2663 gcc_assert (!(REGNO (reg) & 1));
2664
2665 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2666 *hi = gen_rtx_REG (SImode, REGNO (reg));
2667 }
2668
2669 /* Return true if OP contains a symbol reference */
2670
2671 bool
2672 symbolic_reference_mentioned_p (rtx op)
2673 {
2674 const char *fmt;
2675 int i;
2676
2677 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2678 return 1;
2679
2680 fmt = GET_RTX_FORMAT (GET_CODE (op));
2681 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2682 {
2683 if (fmt[i] == 'E')
2684 {
2685 int j;
2686
2687 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2688 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2689 return 1;
2690 }
2691
2692 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2693 return 1;
2694 }
2695
2696 return 0;
2697 }
2698
2699 /* Return true if OP contains a reference to a thread-local symbol. */
2700
2701 bool
2702 tls_symbolic_reference_mentioned_p (rtx op)
2703 {
2704 const char *fmt;
2705 int i;
2706
2707 if (GET_CODE (op) == SYMBOL_REF)
2708 return tls_symbolic_operand (op);
2709
2710 fmt = GET_RTX_FORMAT (GET_CODE (op));
2711 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2712 {
2713 if (fmt[i] == 'E')
2714 {
2715 int j;
2716
2717 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2718 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2719 return true;
2720 }
2721
2722 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
2723 return true;
2724 }
2725
2726 return false;
2727 }
2728
2729
2730 /* Return true if OP is a legitimate general operand when
2731 generating PIC code. It is given that flag_pic is on
2732 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2733
2734 int
2735 legitimate_pic_operand_p (rtx op)
2736 {
2737 /* Accept all non-symbolic constants. */
2738 if (!SYMBOLIC_CONST (op))
2739 return 1;
2740
2741 /* Reject everything else; must be handled
2742 via emit_symbolic_move. */
2743 return 0;
2744 }
2745
2746 /* Returns true if the constant value OP is a legitimate general operand.
2747 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2748
2749 static bool
2750 s390_legitimate_constant_p (machine_mode mode, rtx op)
2751 {
2752 /* Accept all non-symbolic constants. */
2753 if (!SYMBOLIC_CONST (op))
2754 return 1;
2755
2756 /* Accept immediate LARL operands. */
2757 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
2758 return 1;
2759
2760 /* Thread-local symbols are never legal constants. This is
2761 so that emit_call knows that computing such addresses
2762 might require a function call. */
2763 if (TLS_SYMBOLIC_CONST (op))
2764 return 0;
2765
2766 /* In the PIC case, symbolic constants must *not* be
2767 forced into the literal pool. We accept them here,
2768 so that they will be handled by emit_symbolic_move. */
2769 if (flag_pic)
2770 return 1;
2771
2772 /* All remaining non-PIC symbolic constants are
2773 forced into the literal pool. */
2774 return 0;
2775 }
2776
2777 /* Determine if it's legal to put X into the constant pool. This
2778 is not possible if X contains the address of a symbol that is
2779 not constant (TLS) or not known at final link time (PIC). */
2780
2781 static bool
2782 s390_cannot_force_const_mem (machine_mode mode, rtx x)
2783 {
2784 switch (GET_CODE (x))
2785 {
2786 case CONST_INT:
2787 case CONST_DOUBLE:
2788 /* Accept all non-symbolic constants. */
2789 return false;
2790
2791 case LABEL_REF:
2792 /* Labels are OK iff we are non-PIC. */
2793 return flag_pic != 0;
2794
2795 case SYMBOL_REF:
2796 /* 'Naked' TLS symbol references are never OK,
2797 non-TLS symbols are OK iff we are non-PIC. */
2798 if (tls_symbolic_operand (x))
2799 return true;
2800 else
2801 return flag_pic != 0;
2802
2803 case CONST:
2804 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
2805 case PLUS:
2806 case MINUS:
2807 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2808 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
2809
2810 case UNSPEC:
2811 switch (XINT (x, 1))
2812 {
2813 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2814 case UNSPEC_LTREL_OFFSET:
2815 case UNSPEC_GOT:
2816 case UNSPEC_GOTOFF:
2817 case UNSPEC_PLTOFF:
2818 case UNSPEC_TLSGD:
2819 case UNSPEC_TLSLDM:
2820 case UNSPEC_NTPOFF:
2821 case UNSPEC_DTPOFF:
2822 case UNSPEC_GOTNTPOFF:
2823 case UNSPEC_INDNTPOFF:
2824 return false;
2825
2826 /* If the literal pool shares the code section, be put
2827 execute template placeholders into the pool as well. */
2828 case UNSPEC_INSN:
2829 return TARGET_CPU_ZARCH;
2830
2831 default:
2832 return true;
2833 }
2834 break;
2835
2836 default:
2837 gcc_unreachable ();
2838 }
2839 }
2840
2841 /* Returns true if the constant value OP is a legitimate general
2842 operand during and after reload. The difference to
2843 legitimate_constant_p is that this function will not accept
2844 a constant that would need to be forced to the literal pool
2845 before it can be used as operand.
2846 This function accepts all constants which can be loaded directly
2847 into a GPR. */
2848
2849 bool
2850 legitimate_reload_constant_p (rtx op)
2851 {
2852 /* Accept la(y) operands. */
2853 if (GET_CODE (op) == CONST_INT
2854 && DISP_IN_RANGE (INTVAL (op)))
2855 return true;
2856
2857 /* Accept l(g)hi/l(g)fi operands. */
2858 if (GET_CODE (op) == CONST_INT
2859 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
2860 return true;
2861
2862 /* Accept lliXX operands. */
2863 if (TARGET_ZARCH
2864 && GET_CODE (op) == CONST_INT
2865 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2866 && s390_single_part (op, word_mode, HImode, 0) >= 0)
2867 return true;
2868
2869 if (TARGET_EXTIMM
2870 && GET_CODE (op) == CONST_INT
2871 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2872 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2873 return true;
2874
2875 /* Accept larl operands. */
2876 if (TARGET_CPU_ZARCH
2877 && larl_operand (op, VOIDmode))
2878 return true;
2879
2880 /* Accept floating-point zero operands that fit into a single GPR. */
2881 if (GET_CODE (op) == CONST_DOUBLE
2882 && s390_float_const_zero_p (op)
2883 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2884 return true;
2885
2886 /* Accept double-word operands that can be split. */
2887 if (GET_CODE (op) == CONST_INT
2888 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2889 {
2890 machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2891 rtx hi = operand_subword (op, 0, 0, dword_mode);
2892 rtx lo = operand_subword (op, 1, 0, dword_mode);
2893 return legitimate_reload_constant_p (hi)
2894 && legitimate_reload_constant_p (lo);
2895 }
2896
2897 /* Everything else cannot be handled without reload. */
2898 return false;
2899 }
2900
2901 /* Returns true if the constant value OP is a legitimate fp operand
2902 during and after reload.
2903 This function accepts all constants which can be loaded directly
2904 into an FPR. */
2905
2906 static bool
2907 legitimate_reload_fp_constant_p (rtx op)
2908 {
2909 /* Accept floating-point zero operands if the load zero instruction
2910 can be used. Prior to z196 the load fp zero instruction caused a
2911 performance penalty if the result is used as BFP number. */
2912 if (TARGET_Z196
2913 && GET_CODE (op) == CONST_DOUBLE
2914 && s390_float_const_zero_p (op))
2915 return true;
2916
2917 return false;
2918 }
2919
2920 /* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
2921 return the class of reg to actually use. */
2922
2923 static reg_class_t
2924 s390_preferred_reload_class (rtx op, reg_class_t rclass)
2925 {
2926 switch (GET_CODE (op))
2927 {
2928 /* Constants we cannot reload into general registers
2929 must be forced into the literal pool. */
2930 case CONST_DOUBLE:
2931 case CONST_INT:
2932 if (reg_class_subset_p (GENERAL_REGS, rclass)
2933 && legitimate_reload_constant_p (op))
2934 return GENERAL_REGS;
2935 else if (reg_class_subset_p (ADDR_REGS, rclass)
2936 && legitimate_reload_constant_p (op))
2937 return ADDR_REGS;
2938 else if (reg_class_subset_p (FP_REGS, rclass)
2939 && legitimate_reload_fp_constant_p (op))
2940 return FP_REGS;
2941 return NO_REGS;
2942
2943 /* If a symbolic constant or a PLUS is reloaded,
2944 it is most likely being used as an address, so
2945 prefer ADDR_REGS. If 'class' is not a superset
2946 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2947 case CONST:
2948 /* Symrefs cannot be pushed into the literal pool with -fPIC
2949 so we *MUST NOT* return NO_REGS for these cases
2950 (s390_cannot_force_const_mem will return true).
2951
2952 On the other hand we MUST return NO_REGS for symrefs with
2953 invalid addend which might have been pushed to the literal
2954 pool (no -fPIC). Usually we would expect them to be
2955 handled via secondary reload but this does not happen if
2956 they are used as literal pool slot replacement in reload
2957 inheritance (see emit_input_reload_insns). */
2958 if (TARGET_CPU_ZARCH
2959 && GET_CODE (XEXP (op, 0)) == PLUS
2960 && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
2961 && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
2962 {
2963 if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))
2964 return ADDR_REGS;
2965 else
2966 return NO_REGS;
2967 }
2968 /* fallthrough */
2969 case LABEL_REF:
2970 case SYMBOL_REF:
2971 if (!legitimate_reload_constant_p (op))
2972 return NO_REGS;
2973 /* fallthrough */
2974 case PLUS:
2975 /* load address will be used. */
2976 if (reg_class_subset_p (ADDR_REGS, rclass))
2977 return ADDR_REGS;
2978 else
2979 return NO_REGS;
2980
2981 default:
2982 break;
2983 }
2984
2985 return rclass;
2986 }
2987
2988 /* Return true if ADDR is SYMBOL_REF + addend with addend being a
2989 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2990 aligned. */
2991
2992 bool
2993 s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2994 {
2995 HOST_WIDE_INT addend;
2996 rtx symref;
2997
2998 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
2999 return false;
3000
3001 if (addend & (alignment - 1))
3002 return false;
3003
3004 if (GET_CODE (symref) == SYMBOL_REF
3005 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref))
3006 return true;
3007
3008 if (GET_CODE (symref) == UNSPEC
3009 && alignment <= UNITS_PER_LONG)
3010 return true;
3011
3012 return false;
3013 }
3014
3015 /* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3016 operand SCRATCH is used to reload the even part of the address and
3017 adding one. */
3018
3019 void
3020 s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3021 {
3022 HOST_WIDE_INT addend;
3023 rtx symref;
3024
3025 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
3026 gcc_unreachable ();
3027
3028 if (!(addend & 1))
3029 /* Easy case. The addend is even so larl will do fine. */
3030 emit_move_insn (reg, addr);
3031 else
3032 {
3033 /* We can leave the scratch register untouched if the target
3034 register is a valid base register. */
3035 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3036 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3037 scratch = reg;
3038
3039 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3040 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3041
3042 if (addend != 1)
3043 emit_move_insn (scratch,
3044 gen_rtx_CONST (Pmode,
3045 gen_rtx_PLUS (Pmode, symref,
3046 GEN_INT (addend - 1))));
3047 else
3048 emit_move_insn (scratch, symref);
3049
3050 /* Increment the address using la in order to avoid clobbering cc. */
3051 s390_load_address (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
3052 }
3053 }
3054
3055 /* Generate what is necessary to move between REG and MEM using
3056 SCRATCH. The direction is given by TOMEM. */
3057
3058 void
3059 s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3060 {
3061 /* Reload might have pulled a constant out of the literal pool.
3062 Force it back in. */
3063 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3064 || GET_CODE (mem) == CONST)
3065 mem = force_const_mem (GET_MODE (reg), mem);
3066
3067 gcc_assert (MEM_P (mem));
3068
3069 /* For a load from memory we can leave the scratch register
3070 untouched if the target register is a valid base register. */
3071 if (!tomem
3072 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3073 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3074 && GET_MODE (reg) == GET_MODE (scratch))
3075 scratch = reg;
3076
3077 /* Load address into scratch register. Since we can't have a
3078 secondary reload for a secondary reload we have to cover the case
3079 where larl would need a secondary reload here as well. */
3080 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3081
3082 /* Now we can use a standard load/store to do the move. */
3083 if (tomem)
3084 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3085 else
3086 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3087 }
3088
3089 /* Inform reload about cases where moving X with a mode MODE to a register in
3090 RCLASS requires an extra scratch or immediate register. Return the class
3091 needed for the immediate register. */
3092
3093 static reg_class_t
3094 s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
3095 machine_mode mode, secondary_reload_info *sri)
3096 {
3097 enum reg_class rclass = (enum reg_class) rclass_i;
3098
3099 /* Intermediate register needed. */
3100 if (reg_classes_intersect_p (CC_REGS, rclass))
3101 return GENERAL_REGS;
3102
3103 if (TARGET_Z10)
3104 {
3105 HOST_WIDE_INT offset;
3106 rtx symref;
3107
3108 /* On z10 several optimizer steps may generate larl operands with
3109 an odd addend. */
3110 if (in_p
3111 && s390_loadrelative_operand_p (x, &symref, &offset)
3112 && mode == Pmode
3113 && !SYMBOL_REF_ALIGN1_P (symref)
3114 && (offset & 1) == 1)
3115 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3116 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3117
3118 /* On z10 we need a scratch register when moving QI, TI or floating
3119 point mode values from or to a memory location with a SYMBOL_REF
3120 or if the symref addend of a SI or DI move is not aligned to the
3121 width of the access. */
3122 if (MEM_P (x)
3123 && s390_loadrelative_operand_p (XEXP (x, 0), NULL, NULL)
3124 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
3125 || (!TARGET_ZARCH && mode == DImode)
3126 || ((mode == HImode || mode == SImode || mode == DImode)
3127 && (!s390_check_symref_alignment (XEXP (x, 0),
3128 GET_MODE_SIZE (mode))))))
3129 {
3130 #define __SECONDARY_RELOAD_CASE(M,m) \
3131 case M##mode: \
3132 if (TARGET_64BIT) \
3133 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3134 CODE_FOR_reload##m##di_tomem_z10; \
3135 else \
3136 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3137 CODE_FOR_reload##m##si_tomem_z10; \
3138 break;
3139
3140 switch (GET_MODE (x))
3141 {
3142 __SECONDARY_RELOAD_CASE (QI, qi);
3143 __SECONDARY_RELOAD_CASE (HI, hi);
3144 __SECONDARY_RELOAD_CASE (SI, si);
3145 __SECONDARY_RELOAD_CASE (DI, di);
3146 __SECONDARY_RELOAD_CASE (TI, ti);
3147 __SECONDARY_RELOAD_CASE (SF, sf);
3148 __SECONDARY_RELOAD_CASE (DF, df);
3149 __SECONDARY_RELOAD_CASE (TF, tf);
3150 __SECONDARY_RELOAD_CASE (SD, sd);
3151 __SECONDARY_RELOAD_CASE (DD, dd);
3152 __SECONDARY_RELOAD_CASE (TD, td);
3153
3154 default:
3155 gcc_unreachable ();
3156 }
3157 #undef __SECONDARY_RELOAD_CASE
3158 }
3159 }
3160
3161 /* We need a scratch register when loading a PLUS expression which
3162 is not a legitimate operand of the LOAD ADDRESS instruction. */
3163 /* LRA can deal with transformation of plus op very well -- so we
3164 don't need to prompt LRA in this case. */
3165 if (! lra_in_progress && in_p && s390_plus_operand (x, mode))
3166 sri->icode = (TARGET_64BIT ?
3167 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3168
3169 /* Performing a multiword move from or to memory we have to make sure the
3170 second chunk in memory is addressable without causing a displacement
3171 overflow. If that would be the case we calculate the address in
3172 a scratch register. */
3173 if (MEM_P (x)
3174 && GET_CODE (XEXP (x, 0)) == PLUS
3175 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3176 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
3177 + GET_MODE_SIZE (mode) - 1))
3178 {
3179 /* For GENERAL_REGS a displacement overflow is no problem if occurring
3180 in a s_operand address since we may fallback to lm/stm. So we only
3181 have to care about overflows in the b+i+d case. */
3182 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
3183 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3184 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3185 /* For FP_REGS no lm/stm is available so this check is triggered
3186 for displacement overflows in b+i+d and b+d like addresses. */
3187 || (reg_classes_intersect_p (FP_REGS, rclass)
3188 && s390_class_max_nregs (FP_REGS, mode) > 1))
3189 {
3190 if (in_p)
3191 sri->icode = (TARGET_64BIT ?
3192 CODE_FOR_reloaddi_nonoffmem_in :
3193 CODE_FOR_reloadsi_nonoffmem_in);
3194 else
3195 sri->icode = (TARGET_64BIT ?
3196 CODE_FOR_reloaddi_nonoffmem_out :
3197 CODE_FOR_reloadsi_nonoffmem_out);
3198 }
3199 }
3200
3201 /* A scratch address register is needed when a symbolic constant is
3202 copied to r0 compiling with -fPIC. In other cases the target
3203 register might be used as temporary (see legitimize_pic_address). */
3204 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
3205 sri->icode = (TARGET_64BIT ?
3206 CODE_FOR_reloaddi_PIC_addr :
3207 CODE_FOR_reloadsi_PIC_addr);
3208
3209 /* Either scratch or no register needed. */
3210 return NO_REGS;
3211 }
3212
3213 /* Generate code to load SRC, which is PLUS that is not a
3214 legitimate operand for the LA instruction, into TARGET.
3215 SCRATCH may be used as scratch register. */
3216
3217 void
3218 s390_expand_plus_operand (rtx target, rtx src,
3219 rtx scratch)
3220 {
3221 rtx sum1, sum2;
3222 struct s390_address ad;
3223
3224 /* src must be a PLUS; get its two operands. */
3225 gcc_assert (GET_CODE (src) == PLUS);
3226 gcc_assert (GET_MODE (src) == Pmode);
3227
3228 /* Check if any of the two operands is already scheduled
3229 for replacement by reload. This can happen e.g. when
3230 float registers occur in an address. */
3231 sum1 = find_replacement (&XEXP (src, 0));
3232 sum2 = find_replacement (&XEXP (src, 1));
3233 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3234
3235 /* If the address is already strictly valid, there's nothing to do. */
3236 if (!s390_decompose_address (src, &ad)
3237 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3238 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3239 {
3240 /* Otherwise, one of the operands cannot be an address register;
3241 we reload its value into the scratch register. */
3242 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3243 {
3244 emit_move_insn (scratch, sum1);
3245 sum1 = scratch;
3246 }
3247 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3248 {
3249 emit_move_insn (scratch, sum2);
3250 sum2 = scratch;
3251 }
3252
3253 /* According to the way these invalid addresses are generated
3254 in reload.c, it should never happen (at least on s390) that
3255 *neither* of the PLUS components, after find_replacements
3256 was applied, is an address register. */
3257 if (sum1 == scratch && sum2 == scratch)
3258 {
3259 debug_rtx (src);
3260 gcc_unreachable ();
3261 }
3262
3263 src = gen_rtx_PLUS (Pmode, sum1, sum2);
3264 }
3265
3266 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3267 is only ever performed on addresses, so we can mark the
3268 sum as legitimate for LA in any case. */
3269 s390_load_address (target, src);
3270 }
3271
3272
3273 /* Return true if ADDR is a valid memory address.
3274 STRICT specifies whether strict register checking applies. */
3275
3276 static bool
3277 s390_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
3278 {
3279 struct s390_address ad;
3280
3281 if (TARGET_Z10
3282 && larl_operand (addr, VOIDmode)
3283 && (mode == VOIDmode
3284 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3285 return true;
3286
3287 if (!s390_decompose_address (addr, &ad))
3288 return false;
3289
3290 if (strict)
3291 {
3292 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3293 return false;
3294
3295 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3296 return false;
3297 }
3298 else
3299 {
3300 if (ad.base
3301 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3302 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3303 return false;
3304
3305 if (ad.indx
3306 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3307 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3308 return false;
3309 }
3310 return true;
3311 }
3312
3313 /* Return true if OP is a valid operand for the LA instruction.
3314 In 31-bit, we need to prove that the result is used as an
3315 address, as LA performs only a 31-bit addition. */
3316
3317 bool
3318 legitimate_la_operand_p (rtx op)
3319 {
3320 struct s390_address addr;
3321 if (!s390_decompose_address (op, &addr))
3322 return false;
3323
3324 return (TARGET_64BIT || addr.pointer);
3325 }
3326
3327 /* Return true if it is valid *and* preferable to use LA to
3328 compute the sum of OP1 and OP2. */
3329
3330 bool
3331 preferred_la_operand_p (rtx op1, rtx op2)
3332 {
3333 struct s390_address addr;
3334
3335 if (op2 != const0_rtx)
3336 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3337
3338 if (!s390_decompose_address (op1, &addr))
3339 return false;
3340 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3341 return false;
3342 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3343 return false;
3344
3345 /* Avoid LA instructions with index register on z196; it is
3346 preferable to use regular add instructions when possible.
3347 Starting with zEC12 the la with index register is "uncracked"
3348 again. */
3349 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3350 return false;
3351
3352 if (!TARGET_64BIT && !addr.pointer)
3353 return false;
3354
3355 if (addr.pointer)
3356 return true;
3357
3358 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3359 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3360 return true;
3361
3362 return false;
3363 }
3364
3365 /* Emit a forced load-address operation to load SRC into DST.
3366 This will use the LOAD ADDRESS instruction even in situations
3367 where legitimate_la_operand_p (SRC) returns false. */
3368
3369 void
3370 s390_load_address (rtx dst, rtx src)
3371 {
3372 if (TARGET_64BIT)
3373 emit_move_insn (dst, src);
3374 else
3375 emit_insn (gen_force_la_31 (dst, src));
3376 }
3377
3378 /* Return a legitimate reference for ORIG (an address) using the
3379 register REG. If REG is 0, a new pseudo is generated.
3380
3381 There are two types of references that must be handled:
3382
3383 1. Global data references must load the address from the GOT, via
3384 the PIC reg. An insn is emitted to do this load, and the reg is
3385 returned.
3386
3387 2. Static data references, constant pool addresses, and code labels
3388 compute the address as an offset from the GOT, whose base is in
3389 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
3390 differentiate them from global data objects. The returned
3391 address is the PIC reg + an unspec constant.
3392
3393 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
3394 reg also appears in the address. */
3395
3396 rtx
3397 legitimize_pic_address (rtx orig, rtx reg)
3398 {
3399 rtx addr = orig;
3400 rtx addend = const0_rtx;
3401 rtx new_rtx = orig;
3402
3403 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3404
3405 if (GET_CODE (addr) == CONST)
3406 addr = XEXP (addr, 0);
3407
3408 if (GET_CODE (addr) == PLUS)
3409 {
3410 addend = XEXP (addr, 1);
3411 addr = XEXP (addr, 0);
3412 }
3413
3414 if ((GET_CODE (addr) == LABEL_REF
3415 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr))
3416 || (GET_CODE (addr) == UNSPEC &&
3417 (XINT (addr, 1) == UNSPEC_GOTENT
3418 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
3419 && GET_CODE (addend) == CONST_INT)
3420 {
3421 /* This can be locally addressed. */
3422
3423 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
3424 rtx const_addr = (GET_CODE (addr) == UNSPEC ?
3425 gen_rtx_CONST (Pmode, addr) : addr);
3426
3427 if (TARGET_CPU_ZARCH
3428 && larl_operand (const_addr, VOIDmode)
3429 && INTVAL (addend) < (HOST_WIDE_INT)1 << 31
3430 && INTVAL (addend) >= -((HOST_WIDE_INT)1 << 31))
3431 {
3432 if (INTVAL (addend) & 1)
3433 {
3434 /* LARL can't handle odd offsets, so emit a pair of LARL
3435 and LA. */
3436 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3437
3438 if (!DISP_IN_RANGE (INTVAL (addend)))
3439 {
3440 HOST_WIDE_INT even = INTVAL (addend) - 1;
3441 addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (even));
3442 addr = gen_rtx_CONST (Pmode, addr);
3443 addend = const1_rtx;
3444 }
3445
3446 emit_move_insn (temp, addr);
3447 new_rtx = gen_rtx_PLUS (Pmode, temp, addend);
3448
3449 if (reg != 0)
3450 {
3451 s390_load_address (reg, new_rtx);
3452 new_rtx = reg;
3453 }
3454 }
3455 else
3456 {
3457 /* If the offset is even, we can just use LARL. This
3458 will happen automatically. */
3459 }
3460 }
3461 else
3462 {
3463 /* No larl - Access local symbols relative to the GOT. */
3464
3465 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3466
3467 if (reload_in_progress || reload_completed)
3468 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3469
3470 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3471 if (addend != const0_rtx)
3472 addr = gen_rtx_PLUS (Pmode, addr, addend);
3473 addr = gen_rtx_CONST (Pmode, addr);
3474 addr = force_const_mem (Pmode, addr);
3475 emit_move_insn (temp, addr);
3476
3477 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3478 if (reg != 0)
3479 {
3480 s390_load_address (reg, new_rtx);
3481 new_rtx = reg;
3482 }
3483 }
3484 }
3485 else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx)
3486 {
3487 /* A non-local symbol reference without addend.
3488
3489 The symbol ref is wrapped into an UNSPEC to make sure the
3490 proper operand modifier (@GOT or @GOTENT) will be emitted.
3491 This will tell the linker to put the symbol into the GOT.
3492
3493 Additionally the code dereferencing the GOT slot is emitted here.
3494
3495 An addend to the symref needs to be added afterwards.
3496 legitimize_pic_address calls itself recursively to handle
3497 that case. So no need to do it here. */
3498
3499 if (reg == 0)
3500 reg = gen_reg_rtx (Pmode);
3501
3502 if (TARGET_Z10)
3503 {
3504 /* Use load relative if possible.
3505 lgrl <target>, sym@GOTENT */
3506 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3507 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3508 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3509
3510 emit_move_insn (reg, new_rtx);
3511 new_rtx = reg;
3512 }
3513 else if (flag_pic == 1)
3514 {
3515 /* Assume GOT offset is a valid displacement operand (< 4k
3516 or < 512k with z990). This is handled the same way in
3517 both 31- and 64-bit code (@GOT).
3518 lg <target>, sym@GOT(r12) */
3519
3520 if (reload_in_progress || reload_completed)
3521 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3522
3523 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3524 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3525 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3526 new_rtx = gen_const_mem (Pmode, new_rtx);
3527 emit_move_insn (reg, new_rtx);
3528 new_rtx = reg;
3529 }
3530 else if (TARGET_CPU_ZARCH)
3531 {
3532 /* If the GOT offset might be >= 4k, we determine the position
3533 of the GOT entry via a PC-relative LARL (@GOTENT).
3534 larl temp, sym@GOTENT
3535 lg <target>, 0(temp) */
3536
3537 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3538
3539 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3540 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3541
3542 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3543 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3544 emit_move_insn (temp, new_rtx);
3545
3546 new_rtx = gen_const_mem (Pmode, temp);
3547 emit_move_insn (reg, new_rtx);
3548
3549 new_rtx = reg;
3550 }
3551 else
3552 {
3553 /* If the GOT offset might be >= 4k, we have to load it
3554 from the literal pool (@GOT).
3555
3556 lg temp, lit-litbase(r13)
3557 lg <target>, 0(temp)
3558 lit: .long sym@GOT */
3559
3560 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3561
3562 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3563 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
3564
3565 if (reload_in_progress || reload_completed)
3566 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3567
3568 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3569 addr = gen_rtx_CONST (Pmode, addr);
3570 addr = force_const_mem (Pmode, addr);
3571 emit_move_insn (temp, addr);
3572
3573 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3574 new_rtx = gen_const_mem (Pmode, new_rtx);
3575 emit_move_insn (reg, new_rtx);
3576 new_rtx = reg;
3577 }
3578 }
3579 else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT)
3580 {
3581 gcc_assert (XVECLEN (addr, 0) == 1);
3582 switch (XINT (addr, 1))
3583 {
3584 /* These address symbols (or PLT slots) relative to the GOT
3585 (not GOT slots!). In general this will exceed the
3586 displacement range so these value belong into the literal
3587 pool. */
3588 case UNSPEC_GOTOFF:
3589 case UNSPEC_PLTOFF:
3590 new_rtx = force_const_mem (Pmode, orig);
3591 break;
3592
3593 /* For -fPIC the GOT size might exceed the displacement
3594 range so make sure the value is in the literal pool. */
3595 case UNSPEC_GOT:
3596 if (flag_pic == 2)
3597 new_rtx = force_const_mem (Pmode, orig);
3598 break;
3599
3600 /* For @GOTENT larl is used. This is handled like local
3601 symbol refs. */
3602 case UNSPEC_GOTENT:
3603 gcc_unreachable ();
3604 break;
3605
3606 /* @PLT is OK as is on 64-bit, must be converted to
3607 GOT-relative @PLTOFF on 31-bit. */
3608 case UNSPEC_PLT:
3609 if (!TARGET_CPU_ZARCH)
3610 {
3611 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3612
3613 if (reload_in_progress || reload_completed)
3614 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3615
3616 addr = XVECEXP (addr, 0, 0);
3617 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3618 UNSPEC_PLTOFF);
3619 if (addend != const0_rtx)
3620 addr = gen_rtx_PLUS (Pmode, addr, addend);
3621 addr = gen_rtx_CONST (Pmode, addr);
3622 addr = force_const_mem (Pmode, addr);
3623 emit_move_insn (temp, addr);
3624
3625 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3626 if (reg != 0)
3627 {
3628 s390_load_address (reg, new_rtx);
3629 new_rtx = reg;
3630 }
3631 }
3632 else
3633 /* On 64 bit larl can be used. This case is handled like
3634 local symbol refs. */
3635 gcc_unreachable ();
3636 break;
3637
3638 /* Everything else cannot happen. */
3639 default:
3640 gcc_unreachable ();
3641 }
3642 }
3643 else if (addend != const0_rtx)
3644 {
3645 /* Otherwise, compute the sum. */
3646
3647 rtx base = legitimize_pic_address (addr, reg);
3648 new_rtx = legitimize_pic_address (addend,
3649 base == reg ? NULL_RTX : reg);
3650 if (GET_CODE (new_rtx) == CONST_INT)
3651 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3652 else
3653 {
3654 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3655 {
3656 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3657 new_rtx = XEXP (new_rtx, 1);
3658 }
3659 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
3660 }
3661
3662 if (GET_CODE (new_rtx) == CONST)
3663 new_rtx = XEXP (new_rtx, 0);
3664 new_rtx = force_operand (new_rtx, 0);
3665 }
3666
3667 return new_rtx;
3668 }
3669
3670 /* Load the thread pointer into a register. */
3671
3672 rtx
3673 s390_get_thread_pointer (void)
3674 {
3675 rtx tp = gen_reg_rtx (Pmode);
3676
3677 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
3678 mark_reg_pointer (tp, BITS_PER_WORD);
3679
3680 return tp;
3681 }
3682
3683 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3684 in s390_tls_symbol which always refers to __tls_get_offset.
3685 The returned offset is written to RESULT_REG and an USE rtx is
3686 generated for TLS_CALL. */
3687
3688 static GTY(()) rtx s390_tls_symbol;
3689
3690 static void
3691 s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
3692 {
3693 rtx insn;
3694
3695 if (!flag_pic)
3696 emit_insn (s390_load_got ());
3697
3698 if (!s390_tls_symbol)
3699 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3700
3701 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3702 gen_rtx_REG (Pmode, RETURN_REGNUM));
3703
3704 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
3705 RTL_CONST_CALL_P (insn) = 1;
3706 }
3707
3708 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3709 this (thread-local) address. REG may be used as temporary. */
3710
3711 static rtx
3712 legitimize_tls_address (rtx addr, rtx reg)
3713 {
3714 rtx new_rtx, tls_call, temp, base, r2, insn;
3715
3716 if (GET_CODE (addr) == SYMBOL_REF)
3717 switch (tls_symbolic_operand (addr))
3718 {
3719 case TLS_MODEL_GLOBAL_DYNAMIC:
3720 start_sequence ();
3721 r2 = gen_rtx_REG (Pmode, 2);
3722 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
3723 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3724 new_rtx = force_const_mem (Pmode, new_rtx);
3725 emit_move_insn (r2, new_rtx);
3726 s390_emit_tls_call_insn (r2, tls_call);
3727 insn = get_insns ();
3728 end_sequence ();
3729
3730 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3731 temp = gen_reg_rtx (Pmode);
3732 emit_libcall_block (insn, temp, r2, new_rtx);
3733
3734 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3735 if (reg != 0)
3736 {
3737 s390_load_address (reg, new_rtx);
3738 new_rtx = reg;
3739 }
3740 break;
3741
3742 case TLS_MODEL_LOCAL_DYNAMIC:
3743 start_sequence ();
3744 r2 = gen_rtx_REG (Pmode, 2);
3745 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
3746 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3747 new_rtx = force_const_mem (Pmode, new_rtx);
3748 emit_move_insn (r2, new_rtx);
3749 s390_emit_tls_call_insn (r2, tls_call);
3750 insn = get_insns ();
3751 end_sequence ();
3752
3753 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
3754 temp = gen_reg_rtx (Pmode);
3755 emit_libcall_block (insn, temp, r2, new_rtx);
3756
3757 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3758 base = gen_reg_rtx (Pmode);
3759 s390_load_address (base, new_rtx);
3760
3761 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3762 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3763 new_rtx = force_const_mem (Pmode, new_rtx);
3764 temp = gen_reg_rtx (Pmode);
3765 emit_move_insn (temp, new_rtx);
3766
3767 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
3768 if (reg != 0)
3769 {
3770 s390_load_address (reg, new_rtx);
3771 new_rtx = reg;
3772 }
3773 break;
3774
3775 case TLS_MODEL_INITIAL_EXEC:
3776 if (flag_pic == 1)
3777 {
3778 /* Assume GOT offset < 4k. This is handled the same way
3779 in both 31- and 64-bit code. */
3780
3781 if (reload_in_progress || reload_completed)
3782 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3783
3784 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3785 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3786 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3787 new_rtx = gen_const_mem (Pmode, new_rtx);
3788 temp = gen_reg_rtx (Pmode);
3789 emit_move_insn (temp, new_rtx);
3790 }
3791 else if (TARGET_CPU_ZARCH)
3792 {
3793 /* If the GOT offset might be >= 4k, we determine the position
3794 of the GOT entry via a PC-relative LARL. */
3795
3796 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3797 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3798 temp = gen_reg_rtx (Pmode);
3799 emit_move_insn (temp, new_rtx);
3800
3801 new_rtx = gen_const_mem (Pmode, temp);
3802 temp = gen_reg_rtx (Pmode);
3803 emit_move_insn (temp, new_rtx);
3804 }
3805 else if (flag_pic)
3806 {
3807 /* If the GOT offset might be >= 4k, we have to load it
3808 from the literal pool. */
3809
3810 if (reload_in_progress || reload_completed)
3811 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3812
3813 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3814 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3815 new_rtx = force_const_mem (Pmode, new_rtx);
3816 temp = gen_reg_rtx (Pmode);
3817 emit_move_insn (temp, new_rtx);
3818
3819 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3820 new_rtx = gen_const_mem (Pmode, new_rtx);
3821
3822 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3823 temp = gen_reg_rtx (Pmode);
3824 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3825 }
3826 else
3827 {
3828 /* In position-dependent code, load the absolute address of
3829 the GOT entry from the literal pool. */
3830
3831 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3832 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3833 new_rtx = force_const_mem (Pmode, new_rtx);
3834 temp = gen_reg_rtx (Pmode);
3835 emit_move_insn (temp, new_rtx);
3836
3837 new_rtx = temp;
3838 new_rtx = gen_const_mem (Pmode, new_rtx);
3839 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
3840 temp = gen_reg_rtx (Pmode);
3841 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
3842 }
3843
3844 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3845 if (reg != 0)
3846 {
3847 s390_load_address (reg, new_rtx);
3848 new_rtx = reg;
3849 }
3850 break;
3851
3852 case TLS_MODEL_LOCAL_EXEC:
3853 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3854 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3855 new_rtx = force_const_mem (Pmode, new_rtx);
3856 temp = gen_reg_rtx (Pmode);
3857 emit_move_insn (temp, new_rtx);
3858
3859 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
3860 if (reg != 0)
3861 {
3862 s390_load_address (reg, new_rtx);
3863 new_rtx = reg;
3864 }
3865 break;
3866
3867 default:
3868 gcc_unreachable ();
3869 }
3870
3871 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3872 {
3873 switch (XINT (XEXP (addr, 0), 1))
3874 {
3875 case UNSPEC_INDNTPOFF:
3876 gcc_assert (TARGET_CPU_ZARCH);
3877 new_rtx = addr;
3878 break;
3879
3880 default:
3881 gcc_unreachable ();
3882 }
3883 }
3884
3885 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3886 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3887 {
3888 new_rtx = XEXP (XEXP (addr, 0), 0);
3889 if (GET_CODE (new_rtx) != SYMBOL_REF)
3890 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3891
3892 new_rtx = legitimize_tls_address (new_rtx, reg);
3893 new_rtx = plus_constant (Pmode, new_rtx,
3894 INTVAL (XEXP (XEXP (addr, 0), 1)));
3895 new_rtx = force_operand (new_rtx, 0);
3896 }
3897
3898 else
3899 gcc_unreachable (); /* for now ... */
3900
3901 return new_rtx;
3902 }
3903
3904 /* Emit insns making the address in operands[1] valid for a standard
3905 move to operands[0]. operands[1] is replaced by an address which
3906 should be used instead of the former RTX to emit the move
3907 pattern. */
3908
3909 void
3910 emit_symbolic_move (rtx *operands)
3911 {
3912 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
3913
3914 if (GET_CODE (operands[0]) == MEM)
3915 operands[1] = force_reg (Pmode, operands[1]);
3916 else if (TLS_SYMBOLIC_CONST (operands[1]))
3917 operands[1] = legitimize_tls_address (operands[1], temp);
3918 else if (flag_pic)
3919 operands[1] = legitimize_pic_address (operands[1], temp);
3920 }
3921
3922 /* Try machine-dependent ways of modifying an illegitimate address X
3923 to be legitimate. If we find one, return the new, valid address.
3924
3925 OLDX is the address as it was before break_out_memory_refs was called.
3926 In some cases it is useful to look at this to decide what needs to be done.
3927
3928 MODE is the mode of the operand pointed to by X.
3929
3930 When -fpic is used, special handling is needed for symbolic references.
3931 See comments by legitimize_pic_address for details. */
3932
3933 static rtx
3934 s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3935 machine_mode mode ATTRIBUTE_UNUSED)
3936 {
3937 rtx constant_term = const0_rtx;
3938
3939 if (TLS_SYMBOLIC_CONST (x))
3940 {
3941 x = legitimize_tls_address (x, 0);
3942
3943 if (s390_legitimate_address_p (mode, x, FALSE))
3944 return x;
3945 }
3946 else if (GET_CODE (x) == PLUS
3947 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
3948 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3949 {
3950 return x;
3951 }
3952 else if (flag_pic)
3953 {
3954 if (SYMBOLIC_CONST (x)
3955 || (GET_CODE (x) == PLUS
3956 && (SYMBOLIC_CONST (XEXP (x, 0))
3957 || SYMBOLIC_CONST (XEXP (x, 1)))))
3958 x = legitimize_pic_address (x, 0);
3959
3960 if (s390_legitimate_address_p (mode, x, FALSE))
3961 return x;
3962 }
3963
3964 x = eliminate_constant_term (x, &constant_term);
3965
3966 /* Optimize loading of large displacements by splitting them
3967 into the multiple of 4K and the rest; this allows the
3968 former to be CSE'd if possible.
3969
3970 Don't do this if the displacement is added to a register
3971 pointing into the stack frame, as the offsets will
3972 change later anyway. */
3973
3974 if (GET_CODE (constant_term) == CONST_INT
3975 && !TARGET_LONG_DISPLACEMENT
3976 && !DISP_IN_RANGE (INTVAL (constant_term))
3977 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3978 {
3979 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3980 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3981
3982 rtx temp = gen_reg_rtx (Pmode);
3983 rtx val = force_operand (GEN_INT (upper), temp);
3984 if (val != temp)
3985 emit_move_insn (temp, val);
3986
3987 x = gen_rtx_PLUS (Pmode, x, temp);
3988 constant_term = GEN_INT (lower);
3989 }
3990
3991 if (GET_CODE (x) == PLUS)
3992 {
3993 if (GET_CODE (XEXP (x, 0)) == REG)
3994 {
3995 rtx temp = gen_reg_rtx (Pmode);
3996 rtx val = force_operand (XEXP (x, 1), temp);
3997 if (val != temp)
3998 emit_move_insn (temp, val);
3999
4000 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
4001 }
4002
4003 else if (GET_CODE (XEXP (x, 1)) == REG)
4004 {
4005 rtx temp = gen_reg_rtx (Pmode);
4006 rtx val = force_operand (XEXP (x, 0), temp);
4007 if (val != temp)
4008 emit_move_insn (temp, val);
4009
4010 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4011 }
4012 }
4013
4014 if (constant_term != const0_rtx)
4015 x = gen_rtx_PLUS (Pmode, x, constant_term);
4016
4017 return x;
4018 }
4019
4020 /* Try a machine-dependent way of reloading an illegitimate address AD
4021 operand. If we find one, push the reload and return the new address.
4022
4023 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4024 and TYPE is the reload type of the current reload. */
4025
4026 rtx
4027 legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED,
4028 int opnum, int type)
4029 {
4030 if (!optimize || TARGET_LONG_DISPLACEMENT)
4031 return NULL_RTX;
4032
4033 if (GET_CODE (ad) == PLUS)
4034 {
4035 rtx tem = simplify_binary_operation (PLUS, Pmode,
4036 XEXP (ad, 0), XEXP (ad, 1));
4037 if (tem)
4038 ad = tem;
4039 }
4040
4041 if (GET_CODE (ad) == PLUS
4042 && GET_CODE (XEXP (ad, 0)) == REG
4043 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4044 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4045 {
4046 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4047 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
4048 rtx cst, tem, new_rtx;
4049
4050 cst = GEN_INT (upper);
4051 if (!legitimate_reload_constant_p (cst))
4052 cst = force_const_mem (Pmode, cst);
4053
4054 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
4055 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
4056
4057 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
4058 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
4059 opnum, (enum reload_type) type);
4060 return new_rtx;
4061 }
4062
4063 return NULL_RTX;
4064 }
4065
4066 /* Emit code to move LEN bytes from DST to SRC. */
4067
4068 bool
4069 s390_expand_movmem (rtx dst, rtx src, rtx len)
4070 {
4071 /* When tuning for z10 or higher we rely on the Glibc functions to
4072 do the right thing. Only for constant lengths below 64k we will
4073 generate inline code. */
4074 if (s390_tune >= PROCESSOR_2097_Z10
4075 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4076 return false;
4077
4078 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4079 {
4080 if (INTVAL (len) > 0)
4081 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4082 }
4083
4084 else if (TARGET_MVCLE)
4085 {
4086 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4087 }
4088
4089 else
4090 {
4091 rtx dst_addr, src_addr, count, blocks, temp;
4092 rtx_code_label *loop_start_label = gen_label_rtx ();
4093 rtx_code_label *loop_end_label = gen_label_rtx ();
4094 rtx_code_label *end_label = gen_label_rtx ();
4095 machine_mode mode;
4096
4097 mode = GET_MODE (len);
4098 if (mode == VOIDmode)
4099 mode = Pmode;
4100
4101 dst_addr = gen_reg_rtx (Pmode);
4102 src_addr = gen_reg_rtx (Pmode);
4103 count = gen_reg_rtx (mode);
4104 blocks = gen_reg_rtx (mode);
4105
4106 convert_move (count, len, 1);
4107 emit_cmp_and_jump_insns (count, const0_rtx,
4108 EQ, NULL_RTX, mode, 1, end_label);
4109
4110 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4111 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4112 dst = change_address (dst, VOIDmode, dst_addr);
4113 src = change_address (src, VOIDmode, src_addr);
4114
4115 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4116 OPTAB_DIRECT);
4117 if (temp != count)
4118 emit_move_insn (count, temp);
4119
4120 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4121 OPTAB_DIRECT);
4122 if (temp != blocks)
4123 emit_move_insn (blocks, temp);
4124
4125 emit_cmp_and_jump_insns (blocks, const0_rtx,
4126 EQ, NULL_RTX, mode, 1, loop_end_label);
4127
4128 emit_label (loop_start_label);
4129
4130 if (TARGET_Z10
4131 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4132 {
4133 rtx prefetch;
4134
4135 /* Issue a read prefetch for the +3 cache line. */
4136 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4137 const0_rtx, const0_rtx);
4138 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4139 emit_insn (prefetch);
4140
4141 /* Issue a write prefetch for the +3 cache line. */
4142 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4143 const1_rtx, const0_rtx);
4144 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4145 emit_insn (prefetch);
4146 }
4147
4148 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
4149 s390_load_address (dst_addr,
4150 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4151 s390_load_address (src_addr,
4152 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
4153
4154 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4155 OPTAB_DIRECT);
4156 if (temp != blocks)
4157 emit_move_insn (blocks, temp);
4158
4159 emit_cmp_and_jump_insns (blocks, const0_rtx,
4160 EQ, NULL_RTX, mode, 1, loop_end_label);
4161
4162 emit_jump (loop_start_label);
4163 emit_label (loop_end_label);
4164
4165 emit_insn (gen_movmem_short (dst, src,
4166 convert_to_mode (Pmode, count, 1)));
4167 emit_label (end_label);
4168 }
4169 return true;
4170 }
4171
4172 /* Emit code to set LEN bytes at DST to VAL.
4173 Make use of clrmem if VAL is zero. */
4174
4175 void
4176 s390_expand_setmem (rtx dst, rtx len, rtx val)
4177 {
4178 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4179 return;
4180
4181 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
4182
4183 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4184 {
4185 if (val == const0_rtx && INTVAL (len) <= 256)
4186 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
4187 else
4188 {
4189 /* Initialize memory by storing the first byte. */
4190 emit_move_insn (adjust_address (dst, QImode, 0), val);
4191
4192 if (INTVAL (len) > 1)
4193 {
4194 /* Initiate 1 byte overlap move.
4195 The first byte of DST is propagated through DSTP1.
4196 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4197 DST is set to size 1 so the rest of the memory location
4198 does not count as source operand. */
4199 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
4200 set_mem_size (dst, 1);
4201
4202 emit_insn (gen_movmem_short (dstp1, dst,
4203 GEN_INT (INTVAL (len) - 2)));
4204 }
4205 }
4206 }
4207
4208 else if (TARGET_MVCLE)
4209 {
4210 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4211 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4212 }
4213
4214 else
4215 {
4216 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
4217 rtx_code_label *loop_start_label = gen_label_rtx ();
4218 rtx_code_label *loop_end_label = gen_label_rtx ();
4219 rtx_code_label *end_label = gen_label_rtx ();
4220 machine_mode mode;
4221
4222 mode = GET_MODE (len);
4223 if (mode == VOIDmode)
4224 mode = Pmode;
4225
4226 dst_addr = gen_reg_rtx (Pmode);
4227 count = gen_reg_rtx (mode);
4228 blocks = gen_reg_rtx (mode);
4229
4230 convert_move (count, len, 1);
4231 emit_cmp_and_jump_insns (count, const0_rtx,
4232 EQ, NULL_RTX, mode, 1, end_label);
4233
4234 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4235 dst = change_address (dst, VOIDmode, dst_addr);
4236
4237 if (val == const0_rtx)
4238 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4239 OPTAB_DIRECT);
4240 else
4241 {
4242 dstp1 = adjust_address (dst, VOIDmode, 1);
4243 set_mem_size (dst, 1);
4244
4245 /* Initialize memory by storing the first byte. */
4246 emit_move_insn (adjust_address (dst, QImode, 0), val);
4247
4248 /* If count is 1 we are done. */
4249 emit_cmp_and_jump_insns (count, const1_rtx,
4250 EQ, NULL_RTX, mode, 1, end_label);
4251
4252 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4253 OPTAB_DIRECT);
4254 }
4255 if (temp != count)
4256 emit_move_insn (count, temp);
4257
4258 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4259 OPTAB_DIRECT);
4260 if (temp != blocks)
4261 emit_move_insn (blocks, temp);
4262
4263 emit_cmp_and_jump_insns (blocks, const0_rtx,
4264 EQ, NULL_RTX, mode, 1, loop_end_label);
4265
4266 emit_label (loop_start_label);
4267
4268 if (TARGET_Z10
4269 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4270 {
4271 /* Issue a write prefetch for the +4 cache line. */
4272 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4273 GEN_INT (1024)),
4274 const1_rtx, const0_rtx);
4275 emit_insn (prefetch);
4276 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4277 }
4278
4279 if (val == const0_rtx)
4280 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4281 else
4282 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
4283 s390_load_address (dst_addr,
4284 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
4285
4286 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4287 OPTAB_DIRECT);
4288 if (temp != blocks)
4289 emit_move_insn (blocks, temp);
4290
4291 emit_cmp_and_jump_insns (blocks, const0_rtx,
4292 EQ, NULL_RTX, mode, 1, loop_end_label);
4293
4294 emit_jump (loop_start_label);
4295 emit_label (loop_end_label);
4296
4297 if (val == const0_rtx)
4298 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4299 else
4300 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4301 emit_label (end_label);
4302 }
4303 }
4304
4305 /* Emit code to compare LEN bytes at OP0 with those at OP1,
4306 and return the result in TARGET. */
4307
4308 bool
4309 s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4310 {
4311 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
4312 rtx tmp;
4313
4314 /* When tuning for z10 or higher we rely on the Glibc functions to
4315 do the right thing. Only for constant lengths below 64k we will
4316 generate inline code. */
4317 if (s390_tune >= PROCESSOR_2097_Z10
4318 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4319 return false;
4320
4321 /* As the result of CMPINT is inverted compared to what we need,
4322 we have to swap the operands. */
4323 tmp = op0; op0 = op1; op1 = tmp;
4324
4325 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4326 {
4327 if (INTVAL (len) > 0)
4328 {
4329 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
4330 emit_insn (gen_cmpint (target, ccreg));
4331 }
4332 else
4333 emit_move_insn (target, const0_rtx);
4334 }
4335 else if (TARGET_MVCLE)
4336 {
4337 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
4338 emit_insn (gen_cmpint (target, ccreg));
4339 }
4340 else
4341 {
4342 rtx addr0, addr1, count, blocks, temp;
4343 rtx_code_label *loop_start_label = gen_label_rtx ();
4344 rtx_code_label *loop_end_label = gen_label_rtx ();
4345 rtx_code_label *end_label = gen_label_rtx ();
4346 machine_mode mode;
4347
4348 mode = GET_MODE (len);
4349 if (mode == VOIDmode)
4350 mode = Pmode;
4351
4352 addr0 = gen_reg_rtx (Pmode);
4353 addr1 = gen_reg_rtx (Pmode);
4354 count = gen_reg_rtx (mode);
4355 blocks = gen_reg_rtx (mode);
4356
4357 convert_move (count, len, 1);
4358 emit_cmp_and_jump_insns (count, const0_rtx,
4359 EQ, NULL_RTX, mode, 1, end_label);
4360
4361 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4362 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4363 op0 = change_address (op0, VOIDmode, addr0);
4364 op1 = change_address (op1, VOIDmode, addr1);
4365
4366 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4367 OPTAB_DIRECT);
4368 if (temp != count)
4369 emit_move_insn (count, temp);
4370
4371 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4372 OPTAB_DIRECT);
4373 if (temp != blocks)
4374 emit_move_insn (blocks, temp);
4375
4376 emit_cmp_and_jump_insns (blocks, const0_rtx,
4377 EQ, NULL_RTX, mode, 1, loop_end_label);
4378
4379 emit_label (loop_start_label);
4380
4381 if (TARGET_Z10
4382 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4383 {
4384 rtx prefetch;
4385
4386 /* Issue a read prefetch for the +2 cache line of operand 1. */
4387 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4388 const0_rtx, const0_rtx);
4389 emit_insn (prefetch);
4390 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4391
4392 /* Issue a read prefetch for the +2 cache line of operand 2. */
4393 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4394 const0_rtx, const0_rtx);
4395 emit_insn (prefetch);
4396 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4397 }
4398
4399 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
4400 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
4401 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4402 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4403 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4404 emit_jump_insn (temp);
4405
4406 s390_load_address (addr0,
4407 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
4408 s390_load_address (addr1,
4409 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
4410
4411 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4412 OPTAB_DIRECT);
4413 if (temp != blocks)
4414 emit_move_insn (blocks, temp);
4415
4416 emit_cmp_and_jump_insns (blocks, const0_rtx,
4417 EQ, NULL_RTX, mode, 1, loop_end_label);
4418
4419 emit_jump (loop_start_label);
4420 emit_label (loop_end_label);
4421
4422 emit_insn (gen_cmpmem_short (op0, op1,
4423 convert_to_mode (Pmode, count, 1)));
4424 emit_label (end_label);
4425
4426 emit_insn (gen_cmpint (target, ccreg));
4427 }
4428 return true;
4429 }
4430
4431
4432 /* Expand conditional increment or decrement using alc/slb instructions.
4433 Should generate code setting DST to either SRC or SRC + INCREMENT,
4434 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
4435 Returns true if successful, false otherwise.
4436
4437 That makes it possible to implement some if-constructs without jumps e.g.:
4438 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4439 unsigned int a, b, c;
4440 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4441 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4442 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4443 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4444
4445 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4446 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4447 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4448 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4449 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
4450
4451 bool
4452 s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4453 rtx dst, rtx src, rtx increment)
4454 {
4455 machine_mode cmp_mode;
4456 machine_mode cc_mode;
4457 rtx op_res;
4458 rtx insn;
4459 rtvec p;
4460 int ret;
4461
4462 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4463 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4464 cmp_mode = SImode;
4465 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4466 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4467 cmp_mode = DImode;
4468 else
4469 return false;
4470
4471 /* Try ADD LOGICAL WITH CARRY. */
4472 if (increment == const1_rtx)
4473 {
4474 /* Determine CC mode to use. */
4475 if (cmp_code == EQ || cmp_code == NE)
4476 {
4477 if (cmp_op1 != const0_rtx)
4478 {
4479 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4480 NULL_RTX, 0, OPTAB_WIDEN);
4481 cmp_op1 = const0_rtx;
4482 }
4483
4484 cmp_code = cmp_code == EQ ? LEU : GTU;
4485 }
4486
4487 if (cmp_code == LTU || cmp_code == LEU)
4488 {
4489 rtx tem = cmp_op0;
4490 cmp_op0 = cmp_op1;
4491 cmp_op1 = tem;
4492 cmp_code = swap_condition (cmp_code);
4493 }
4494
4495 switch (cmp_code)
4496 {
4497 case GTU:
4498 cc_mode = CCUmode;
4499 break;
4500
4501 case GEU:
4502 cc_mode = CCL3mode;
4503 break;
4504
4505 default:
4506 return false;
4507 }
4508
4509 /* Emit comparison instruction pattern. */
4510 if (!register_operand (cmp_op0, cmp_mode))
4511 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4512
4513 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4514 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4515 /* We use insn_invalid_p here to add clobbers if required. */
4516 ret = insn_invalid_p (emit_insn (insn), false);
4517 gcc_assert (!ret);
4518
4519 /* Emit ALC instruction pattern. */
4520 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4521 gen_rtx_REG (cc_mode, CC_REGNUM),
4522 const0_rtx);
4523
4524 if (src != const0_rtx)
4525 {
4526 if (!register_operand (src, GET_MODE (dst)))
4527 src = force_reg (GET_MODE (dst), src);
4528
4529 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4530 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
4531 }
4532
4533 p = rtvec_alloc (2);
4534 RTVEC_ELT (p, 0) =
4535 gen_rtx_SET (VOIDmode, dst, op_res);
4536 RTVEC_ELT (p, 1) =
4537 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4538 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4539
4540 return true;
4541 }
4542
4543 /* Try SUBTRACT LOGICAL WITH BORROW. */
4544 if (increment == constm1_rtx)
4545 {
4546 /* Determine CC mode to use. */
4547 if (cmp_code == EQ || cmp_code == NE)
4548 {
4549 if (cmp_op1 != const0_rtx)
4550 {
4551 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4552 NULL_RTX, 0, OPTAB_WIDEN);
4553 cmp_op1 = const0_rtx;
4554 }
4555
4556 cmp_code = cmp_code == EQ ? LEU : GTU;
4557 }
4558
4559 if (cmp_code == GTU || cmp_code == GEU)
4560 {
4561 rtx tem = cmp_op0;
4562 cmp_op0 = cmp_op1;
4563 cmp_op1 = tem;
4564 cmp_code = swap_condition (cmp_code);
4565 }
4566
4567 switch (cmp_code)
4568 {
4569 case LEU:
4570 cc_mode = CCUmode;
4571 break;
4572
4573 case LTU:
4574 cc_mode = CCL3mode;
4575 break;
4576
4577 default:
4578 return false;
4579 }
4580
4581 /* Emit comparison instruction pattern. */
4582 if (!register_operand (cmp_op0, cmp_mode))
4583 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4584
4585 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4586 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4587 /* We use insn_invalid_p here to add clobbers if required. */
4588 ret = insn_invalid_p (emit_insn (insn), false);
4589 gcc_assert (!ret);
4590
4591 /* Emit SLB instruction pattern. */
4592 if (!register_operand (src, GET_MODE (dst)))
4593 src = force_reg (GET_MODE (dst), src);
4594
4595 op_res = gen_rtx_MINUS (GET_MODE (dst),
4596 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4597 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4598 gen_rtx_REG (cc_mode, CC_REGNUM),
4599 const0_rtx));
4600 p = rtvec_alloc (2);
4601 RTVEC_ELT (p, 0) =
4602 gen_rtx_SET (VOIDmode, dst, op_res);
4603 RTVEC_ELT (p, 1) =
4604 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4605 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4606
4607 return true;
4608 }
4609
4610 return false;
4611 }
4612
4613 /* Expand code for the insv template. Return true if successful. */
4614
4615 bool
4616 s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4617 {
4618 int bitsize = INTVAL (op1);
4619 int bitpos = INTVAL (op2);
4620 machine_mode mode = GET_MODE (dest);
4621 machine_mode smode;
4622 int smode_bsize, mode_bsize;
4623 rtx op, clobber;
4624
4625 if (bitsize + bitpos > GET_MODE_BITSIZE (mode))
4626 return false;
4627
4628 /* Generate INSERT IMMEDIATE (IILL et al). */
4629 /* (set (ze (reg)) (const_int)). */
4630 if (TARGET_ZARCH
4631 && register_operand (dest, word_mode)
4632 && (bitpos % 16) == 0
4633 && (bitsize % 16) == 0
4634 && const_int_operand (src, VOIDmode))
4635 {
4636 HOST_WIDE_INT val = INTVAL (src);
4637 int regpos = bitpos + bitsize;
4638
4639 while (regpos > bitpos)
4640 {
4641 machine_mode putmode;
4642 int putsize;
4643
4644 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4645 putmode = SImode;
4646 else
4647 putmode = HImode;
4648
4649 putsize = GET_MODE_BITSIZE (putmode);
4650 regpos -= putsize;
4651 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4652 GEN_INT (putsize),
4653 GEN_INT (regpos)),
4654 gen_int_mode (val, putmode));
4655 val >>= putsize;
4656 }
4657 gcc_assert (regpos == bitpos);
4658 return true;
4659 }
4660
4661 smode = smallest_mode_for_size (bitsize, MODE_INT);
4662 smode_bsize = GET_MODE_BITSIZE (smode);
4663 mode_bsize = GET_MODE_BITSIZE (mode);
4664
4665 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
4666 if (bitpos == 0
4667 && (bitsize % BITS_PER_UNIT) == 0
4668 && MEM_P (dest)
4669 && (register_operand (src, word_mode)
4670 || const_int_operand (src, VOIDmode)))
4671 {
4672 /* Emit standard pattern if possible. */
4673 if (smode_bsize == bitsize)
4674 {
4675 emit_move_insn (adjust_address (dest, smode, 0),
4676 gen_lowpart (smode, src));
4677 return true;
4678 }
4679
4680 /* (set (ze (mem)) (const_int)). */
4681 else if (const_int_operand (src, VOIDmode))
4682 {
4683 int size = bitsize / BITS_PER_UNIT;
4684 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4685 BLKmode,
4686 UNITS_PER_WORD - size);
4687
4688 dest = adjust_address (dest, BLKmode, 0);
4689 set_mem_size (dest, size);
4690 s390_expand_movmem (dest, src_mem, GEN_INT (size));
4691 return true;
4692 }
4693
4694 /* (set (ze (mem)) (reg)). */
4695 else if (register_operand (src, word_mode))
4696 {
4697 if (bitsize <= 32)
4698 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4699 const0_rtx), src);
4700 else
4701 {
4702 /* Emit st,stcmh sequence. */
4703 int stcmh_width = bitsize - 32;
4704 int size = stcmh_width / BITS_PER_UNIT;
4705
4706 emit_move_insn (adjust_address (dest, SImode, size),
4707 gen_lowpart (SImode, src));
4708 set_mem_size (dest, size);
4709 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4710 GEN_INT (stcmh_width),
4711 const0_rtx),
4712 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
4713 }
4714 return true;
4715 }
4716 }
4717
4718 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4719 if ((bitpos % BITS_PER_UNIT) == 0
4720 && (bitsize % BITS_PER_UNIT) == 0
4721 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4722 && MEM_P (src)
4723 && (mode == DImode || mode == SImode)
4724 && register_operand (dest, mode))
4725 {
4726 /* Emit a strict_low_part pattern if possible. */
4727 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4728 {
4729 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4730 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4731 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4732 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4733 return true;
4734 }
4735
4736 /* ??? There are more powerful versions of ICM that are not
4737 completely represented in the md file. */
4738 }
4739
4740 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4741 if (TARGET_Z10 && (mode == DImode || mode == SImode))
4742 {
4743 machine_mode mode_s = GET_MODE (src);
4744
4745 if (mode_s == VOIDmode)
4746 {
4747 /* Assume const_int etc already in the proper mode. */
4748 src = force_reg (mode, src);
4749 }
4750 else if (mode_s != mode)
4751 {
4752 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4753 src = force_reg (mode_s, src);
4754 src = gen_lowpart (mode, src);
4755 }
4756
4757 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4758 op = gen_rtx_SET (VOIDmode, op, src);
4759
4760 if (!TARGET_ZEC12)
4761 {
4762 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4763 op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber));
4764 }
4765 emit_insn (op);
4766
4767 return true;
4768 }
4769
4770 return false;
4771 }
4772
4773 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4774 register that holds VAL of mode MODE shifted by COUNT bits. */
4775
4776 static inline rtx
4777 s390_expand_mask_and_shift (rtx val, machine_mode mode, rtx count)
4778 {
4779 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4780 NULL_RTX, 1, OPTAB_DIRECT);
4781 return expand_simple_binop (SImode, ASHIFT, val, count,
4782 NULL_RTX, 1, OPTAB_DIRECT);
4783 }
4784
4785 /* Structure to hold the initial parameters for a compare_and_swap operation
4786 in HImode and QImode. */
4787
4788 struct alignment_context
4789 {
4790 rtx memsi; /* SI aligned memory location. */
4791 rtx shift; /* Bit offset with regard to lsb. */
4792 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4793 rtx modemaski; /* ~modemask */
4794 bool aligned; /* True if memory is aligned, false else. */
4795 };
4796
4797 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4798 structure AC for transparent simplifying, if the memory alignment is known
4799 to be at least 32bit. MEM is the memory location for the actual operation
4800 and MODE its mode. */
4801
4802 static void
4803 init_alignment_context (struct alignment_context *ac, rtx mem,
4804 machine_mode mode)
4805 {
4806 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4807 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4808
4809 if (ac->aligned)
4810 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4811 else
4812 {
4813 /* Alignment is unknown. */
4814 rtx byteoffset, addr, align;
4815
4816 /* Force the address into a register. */
4817 addr = force_reg (Pmode, XEXP (mem, 0));
4818
4819 /* Align it to SImode. */
4820 align = expand_simple_binop (Pmode, AND, addr,
4821 GEN_INT (-GET_MODE_SIZE (SImode)),
4822 NULL_RTX, 1, OPTAB_DIRECT);
4823 /* Generate MEM. */
4824 ac->memsi = gen_rtx_MEM (SImode, align);
4825 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
4826 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
4827 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4828
4829 /* Calculate shiftcount. */
4830 byteoffset = expand_simple_binop (Pmode, AND, addr,
4831 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4832 NULL_RTX, 1, OPTAB_DIRECT);
4833 /* As we already have some offset, evaluate the remaining distance. */
4834 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4835 NULL_RTX, 1, OPTAB_DIRECT);
4836 }
4837
4838 /* Shift is the byte count, but we need the bitcount. */
4839 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4840 NULL_RTX, 1, OPTAB_DIRECT);
4841
4842 /* Calculate masks. */
4843 ac->modemask = expand_simple_binop (SImode, ASHIFT,
4844 GEN_INT (GET_MODE_MASK (mode)),
4845 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4846 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4847 NULL_RTX, 1);
4848 }
4849
4850 /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4851 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4852 perform the merge in SEQ2. */
4853
4854 static rtx
4855 s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
4856 machine_mode mode, rtx val, rtx ins)
4857 {
4858 rtx tmp;
4859
4860 if (ac->aligned)
4861 {
4862 start_sequence ();
4863 tmp = copy_to_mode_reg (SImode, val);
4864 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4865 const0_rtx, ins))
4866 {
4867 *seq1 = NULL;
4868 *seq2 = get_insns ();
4869 end_sequence ();
4870 return tmp;
4871 }
4872 end_sequence ();
4873 }
4874
4875 /* Failed to use insv. Generate a two part shift and mask. */
4876 start_sequence ();
4877 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4878 *seq1 = get_insns ();
4879 end_sequence ();
4880
4881 start_sequence ();
4882 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4883 *seq2 = get_insns ();
4884 end_sequence ();
4885
4886 return tmp;
4887 }
4888
4889 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4890 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4891 value to set if CMP == MEM. */
4892
4893 void
4894 s390_expand_cs_hqi (machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
4895 rtx cmp, rtx new_rtx, bool is_weak)
4896 {
4897 struct alignment_context ac;
4898 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
4899 rtx res = gen_reg_rtx (SImode);
4900 rtx_code_label *csloop = NULL, *csend = NULL;
4901
4902 gcc_assert (MEM_P (mem));
4903
4904 init_alignment_context (&ac, mem, mode);
4905
4906 /* Load full word. Subsequent loads are performed by CS. */
4907 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4908 NULL_RTX, 1, OPTAB_DIRECT);
4909
4910 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4911 possible, we try to use insv to make this happen efficiently. If
4912 that fails we'll generate code both inside and outside the loop. */
4913 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
4914 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
4915
4916 if (seq0)
4917 emit_insn (seq0);
4918 if (seq1)
4919 emit_insn (seq1);
4920
4921 /* Start CS loop. */
4922 if (!is_weak)
4923 {
4924 /* Begin assuming success. */
4925 emit_move_insn (btarget, const1_rtx);
4926
4927 csloop = gen_label_rtx ();
4928 csend = gen_label_rtx ();
4929 emit_label (csloop);
4930 }
4931
4932 /* val = "<mem>00..0<mem>"
4933 * cmp = "00..0<cmp>00..0"
4934 * new = "00..0<new>00..0"
4935 */
4936
4937 emit_insn (seq2);
4938 emit_insn (seq3);
4939
4940 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
4941 if (is_weak)
4942 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
4943 else
4944 {
4945 rtx tmp;
4946
4947 /* Jump to end if we're done (likely?). */
4948 s390_emit_jump (csend, cc);
4949
4950 /* Check for changes outside mode, and loop internal if so.
4951 Arrange the moves so that the compare is adjacent to the
4952 branch so that we can generate CRJ. */
4953 tmp = copy_to_reg (val);
4954 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
4955 1, OPTAB_DIRECT);
4956 cc = s390_emit_compare (NE, val, tmp);
4957 s390_emit_jump (csloop, cc);
4958
4959 /* Failed. */
4960 emit_move_insn (btarget, const0_rtx);
4961 emit_label (csend);
4962 }
4963
4964 /* Return the correct part of the bitfield. */
4965 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4966 NULL_RTX, 1, OPTAB_DIRECT), 1);
4967 }
4968
4969 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4970 and VAL the value to play with. If AFTER is true then store the value
4971 MEM holds after the operation, if AFTER is false then store the value MEM
4972 holds before the operation. If TARGET is zero then discard that value, else
4973 store it to TARGET. */
4974
4975 void
4976 s390_expand_atomic (machine_mode mode, enum rtx_code code,
4977 rtx target, rtx mem, rtx val, bool after)
4978 {
4979 struct alignment_context ac;
4980 rtx cmp;
4981 rtx new_rtx = gen_reg_rtx (SImode);
4982 rtx orig = gen_reg_rtx (SImode);
4983 rtx_code_label *csloop = gen_label_rtx ();
4984
4985 gcc_assert (!target || register_operand (target, VOIDmode));
4986 gcc_assert (MEM_P (mem));
4987
4988 init_alignment_context (&ac, mem, mode);
4989
4990 /* Shift val to the correct bit positions.
4991 Preserve "icm", but prevent "ex icm". */
4992 if (!(ac.aligned && code == SET && MEM_P (val)))
4993 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4994
4995 /* Further preparation insns. */
4996 if (code == PLUS || code == MINUS)
4997 emit_move_insn (orig, val);
4998 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4999 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
5000 NULL_RTX, 1, OPTAB_DIRECT);
5001
5002 /* Load full word. Subsequent loads are performed by CS. */
5003 cmp = force_reg (SImode, ac.memsi);
5004
5005 /* Start CS loop. */
5006 emit_label (csloop);
5007 emit_move_insn (new_rtx, cmp);
5008
5009 /* Patch new with val at correct position. */
5010 switch (code)
5011 {
5012 case PLUS:
5013 case MINUS:
5014 val = expand_simple_binop (SImode, code, new_rtx, orig,
5015 NULL_RTX, 1, OPTAB_DIRECT);
5016 val = expand_simple_binop (SImode, AND, val, ac.modemask,
5017 NULL_RTX, 1, OPTAB_DIRECT);
5018 /* FALLTHRU */
5019 case SET:
5020 if (ac.aligned && MEM_P (val))
5021 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
5022 0, 0, SImode, val);
5023 else
5024 {
5025 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
5026 NULL_RTX, 1, OPTAB_DIRECT);
5027 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
5028 NULL_RTX, 1, OPTAB_DIRECT);
5029 }
5030 break;
5031 case AND:
5032 case IOR:
5033 case XOR:
5034 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
5035 NULL_RTX, 1, OPTAB_DIRECT);
5036 break;
5037 case MULT: /* NAND */
5038 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
5039 NULL_RTX, 1, OPTAB_DIRECT);
5040 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
5041 NULL_RTX, 1, OPTAB_DIRECT);
5042 break;
5043 default:
5044 gcc_unreachable ();
5045 }
5046
5047 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
5048 ac.memsi, cmp, new_rtx));
5049
5050 /* Return the correct part of the bitfield. */
5051 if (target)
5052 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
5053 after ? new_rtx : cmp, ac.shift,
5054 NULL_RTX, 1, OPTAB_DIRECT), 1);
5055 }
5056
5057 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
5058 We need to emit DTP-relative relocations. */
5059
5060 static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5061
5062 static void
5063 s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
5064 {
5065 switch (size)
5066 {
5067 case 4:
5068 fputs ("\t.long\t", file);
5069 break;
5070 case 8:
5071 fputs ("\t.quad\t", file);
5072 break;
5073 default:
5074 gcc_unreachable ();
5075 }
5076 output_addr_const (file, x);
5077 fputs ("@DTPOFF", file);
5078 }
5079
5080 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
5081 /* Implement TARGET_MANGLE_TYPE. */
5082
5083 static const char *
5084 s390_mangle_type (const_tree type)
5085 {
5086 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5087 && TARGET_LONG_DOUBLE_128)
5088 return "g";
5089
5090 /* For all other types, use normal C++ mangling. */
5091 return NULL;
5092 }
5093 #endif
5094
5095 /* In the name of slightly smaller debug output, and to cater to
5096 general assembler lossage, recognize various UNSPEC sequences
5097 and turn them back into a direct symbol reference. */
5098
5099 static rtx
5100 s390_delegitimize_address (rtx orig_x)
5101 {
5102 rtx x, y;
5103
5104 orig_x = delegitimize_mem_from_attrs (orig_x);
5105 x = orig_x;
5106
5107 /* Extract the symbol ref from:
5108 (plus:SI (reg:SI 12 %r12)
5109 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
5110 UNSPEC_GOTOFF/PLTOFF)))
5111 and
5112 (plus:SI (reg:SI 12 %r12)
5113 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5114 UNSPEC_GOTOFF/PLTOFF)
5115 (const_int 4 [0x4])))) */
5116 if (GET_CODE (x) == PLUS
5117 && REG_P (XEXP (x, 0))
5118 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5119 && GET_CODE (XEXP (x, 1)) == CONST)
5120 {
5121 HOST_WIDE_INT offset = 0;
5122
5123 /* The const operand. */
5124 y = XEXP (XEXP (x, 1), 0);
5125
5126 if (GET_CODE (y) == PLUS
5127 && GET_CODE (XEXP (y, 1)) == CONST_INT)
5128 {
5129 offset = INTVAL (XEXP (y, 1));
5130 y = XEXP (y, 0);
5131 }
5132
5133 if (GET_CODE (y) == UNSPEC
5134 && (XINT (y, 1) == UNSPEC_GOTOFF
5135 || XINT (y, 1) == UNSPEC_PLTOFF))
5136 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
5137 }
5138
5139 if (GET_CODE (x) != MEM)
5140 return orig_x;
5141
5142 x = XEXP (x, 0);
5143 if (GET_CODE (x) == PLUS
5144 && GET_CODE (XEXP (x, 1)) == CONST
5145 && GET_CODE (XEXP (x, 0)) == REG
5146 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5147 {
5148 y = XEXP (XEXP (x, 1), 0);
5149 if (GET_CODE (y) == UNSPEC
5150 && XINT (y, 1) == UNSPEC_GOT)
5151 y = XVECEXP (y, 0, 0);
5152 else
5153 return orig_x;
5154 }
5155 else if (GET_CODE (x) == CONST)
5156 {
5157 /* Extract the symbol ref from:
5158 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5159 UNSPEC_PLT/GOTENT))) */
5160
5161 y = XEXP (x, 0);
5162 if (GET_CODE (y) == UNSPEC
5163 && (XINT (y, 1) == UNSPEC_GOTENT
5164 || XINT (y, 1) == UNSPEC_PLT))
5165 y = XVECEXP (y, 0, 0);
5166 else
5167 return orig_x;
5168 }
5169 else
5170 return orig_x;
5171
5172 if (GET_MODE (orig_x) != Pmode)
5173 {
5174 if (GET_MODE (orig_x) == BLKmode)
5175 return orig_x;
5176 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5177 if (y == NULL_RTX)
5178 return orig_x;
5179 }
5180 return y;
5181 }
5182
5183 /* Output operand OP to stdio stream FILE.
5184 OP is an address (register + offset) which is not used to address data;
5185 instead the rightmost bits are interpreted as the value. */
5186
5187 static void
5188 print_shift_count_operand (FILE *file, rtx op)
5189 {
5190 HOST_WIDE_INT offset;
5191 rtx base;
5192
5193 /* Extract base register and offset. */
5194 if (!s390_decompose_shift_count (op, &base, &offset))
5195 gcc_unreachable ();
5196
5197 /* Sanity check. */
5198 if (base)
5199 {
5200 gcc_assert (GET_CODE (base) == REG);
5201 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5202 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
5203 }
5204
5205 /* Offsets are constricted to twelve bits. */
5206 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
5207 if (base)
5208 fprintf (file, "(%s)", reg_names[REGNO (base)]);
5209 }
5210
5211 /* Returns -1 if the function should not be made hotpatchable. Otherwise it
5212 returns a number >= 0 that is the desired size of the hotpatch trampoline
5213 in halfwords. */
5214
5215 static int s390_function_num_hotpatch_trampoline_halfwords (tree decl,
5216 bool do_warn)
5217 {
5218 tree attr;
5219
5220 if (DECL_DECLARED_INLINE_P (decl)
5221 || DECL_ARTIFICIAL (decl)
5222 || MAIN_NAME_P (DECL_NAME (decl)))
5223 {
5224 /* - Explicitly inlined functions cannot be hotpatched.
5225 - Artificial functions need not be hotpatched.
5226 - Making the main function hotpatchable is useless. */
5227 return -1;
5228 }
5229 attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl));
5230 if (attr || s390_hotpatch_trampoline_halfwords >= 0)
5231 {
5232 if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl)))
5233 {
5234 if (do_warn)
5235 warning (OPT_Wattributes, "function %qE with the %qs attribute"
5236 " is not hotpatchable", DECL_NAME (decl), "always_inline");
5237 return -1;
5238 }
5239 else
5240 {
5241 return (attr) ?
5242 get_hotpatch_attribute (attr) : s390_hotpatch_trampoline_halfwords;
5243 }
5244 }
5245
5246 return -1;
5247 }
5248
5249 /* Hook to determine if one function can safely inline another. */
5250
5251 static bool
5252 s390_can_inline_p (tree caller, tree callee)
5253 {
5254 if (s390_function_num_hotpatch_trampoline_halfwords (callee, false) >= 0)
5255 return false;
5256
5257 return default_target_can_inline_p (caller, callee);
5258 }
5259
5260 /* Write the extra assembler code needed to declare a function properly. */
5261
5262 void
5263 s390_asm_output_function_label (FILE *asm_out_file, const char *fname,
5264 tree decl)
5265 {
5266 int hotpatch_trampoline_halfwords = -1;
5267
5268 if (decl)
5269 {
5270 hotpatch_trampoline_halfwords =
5271 s390_function_num_hotpatch_trampoline_halfwords (decl, true);
5272 if (hotpatch_trampoline_halfwords >= 0
5273 && decl_function_context (decl) != NULL_TREE)
5274 {
5275 warning_at (DECL_SOURCE_LOCATION (decl), OPT_mhotpatch,
5276 "hotpatching is not compatible with nested functions");
5277 hotpatch_trampoline_halfwords = -1;
5278 }
5279 }
5280
5281 if (hotpatch_trampoline_halfwords > 0)
5282 {
5283 int i;
5284
5285 /* Add a trampoline code area before the function label and initialize it
5286 with two-byte nop instructions. This area can be overwritten with code
5287 that jumps to a patched version of the function. */
5288 for (i = 0; i < hotpatch_trampoline_halfwords; i++)
5289 asm_fprintf (asm_out_file, "\tnopr\t%%r7\n");
5290 /* Note: The function label must be aligned so that (a) the bytes of the
5291 following nop do not cross a cacheline boundary, and (b) a jump address
5292 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
5293 stored directly before the label without crossing a cacheline
5294 boundary. All this is necessary to make sure the trampoline code can
5295 be changed atomically. */
5296 }
5297
5298 ASM_OUTPUT_LABEL (asm_out_file, fname);
5299
5300 /* Output a four-byte nop if hotpatching is enabled. This can be overwritten
5301 atomically with a relative backwards jump to the trampoline area. */
5302 if (hotpatch_trampoline_halfwords >= 0)
5303 asm_fprintf (asm_out_file, "\tnop\t0\n");
5304 }
5305
5306 /* Output machine-dependent UNSPECs occurring in address constant X
5307 in assembler syntax to stdio stream FILE. Returns true if the
5308 constant X could be recognized, false otherwise. */
5309
5310 static bool
5311 s390_output_addr_const_extra (FILE *file, rtx x)
5312 {
5313 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5314 switch (XINT (x, 1))
5315 {
5316 case UNSPEC_GOTENT:
5317 output_addr_const (file, XVECEXP (x, 0, 0));
5318 fprintf (file, "@GOTENT");
5319 return true;
5320 case UNSPEC_GOT:
5321 output_addr_const (file, XVECEXP (x, 0, 0));
5322 fprintf (file, "@GOT");
5323 return true;
5324 case UNSPEC_GOTOFF:
5325 output_addr_const (file, XVECEXP (x, 0, 0));
5326 fprintf (file, "@GOTOFF");
5327 return true;
5328 case UNSPEC_PLT:
5329 output_addr_const (file, XVECEXP (x, 0, 0));
5330 fprintf (file, "@PLT");
5331 return true;
5332 case UNSPEC_PLTOFF:
5333 output_addr_const (file, XVECEXP (x, 0, 0));
5334 fprintf (file, "@PLTOFF");
5335 return true;
5336 case UNSPEC_TLSGD:
5337 output_addr_const (file, XVECEXP (x, 0, 0));
5338 fprintf (file, "@TLSGD");
5339 return true;
5340 case UNSPEC_TLSLDM:
5341 assemble_name (file, get_some_local_dynamic_name ());
5342 fprintf (file, "@TLSLDM");
5343 return true;
5344 case UNSPEC_DTPOFF:
5345 output_addr_const (file, XVECEXP (x, 0, 0));
5346 fprintf (file, "@DTPOFF");
5347 return true;
5348 case UNSPEC_NTPOFF:
5349 output_addr_const (file, XVECEXP (x, 0, 0));
5350 fprintf (file, "@NTPOFF");
5351 return true;
5352 case UNSPEC_GOTNTPOFF:
5353 output_addr_const (file, XVECEXP (x, 0, 0));
5354 fprintf (file, "@GOTNTPOFF");
5355 return true;
5356 case UNSPEC_INDNTPOFF:
5357 output_addr_const (file, XVECEXP (x, 0, 0));
5358 fprintf (file, "@INDNTPOFF");
5359 return true;
5360 }
5361
5362 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5363 switch (XINT (x, 1))
5364 {
5365 case UNSPEC_POOL_OFFSET:
5366 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5367 output_addr_const (file, x);
5368 return true;
5369 }
5370 return false;
5371 }
5372
5373 /* Output address operand ADDR in assembler syntax to
5374 stdio stream FILE. */
5375
5376 void
5377 print_operand_address (FILE *file, rtx addr)
5378 {
5379 struct s390_address ad;
5380
5381 if (s390_loadrelative_operand_p (addr, NULL, NULL))
5382 {
5383 if (!TARGET_Z10)
5384 {
5385 output_operand_lossage ("symbolic memory references are "
5386 "only supported on z10 or later");
5387 return;
5388 }
5389 output_addr_const (file, addr);
5390 return;
5391 }
5392
5393 if (!s390_decompose_address (addr, &ad)
5394 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5395 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
5396 output_operand_lossage ("cannot decompose address");
5397
5398 if (ad.disp)
5399 output_addr_const (file, ad.disp);
5400 else
5401 fprintf (file, "0");
5402
5403 if (ad.base && ad.indx)
5404 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5405 reg_names[REGNO (ad.base)]);
5406 else if (ad.base)
5407 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5408 }
5409
5410 /* Output operand X in assembler syntax to stdio stream FILE.
5411 CODE specified the format flag. The following format flags
5412 are recognized:
5413
5414 'C': print opcode suffix for branch condition.
5415 'D': print opcode suffix for inverse branch condition.
5416 'E': print opcode suffix for branch on index instruction.
5417 'G': print the size of the operand in bytes.
5418 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5419 'M': print the second word of a TImode operand.
5420 'N': print the second word of a DImode operand.
5421 'O': print only the displacement of a memory reference.
5422 'R': print only the base register of a memory reference.
5423 'S': print S-type memory reference (base+displacement).
5424 'Y': print shift count operand.
5425
5426 'b': print integer X as if it's an unsigned byte.
5427 'c': print integer X as if it's an signed byte.
5428 'e': "end" of DImode contiguous bitmask X.
5429 'f': "end" of SImode contiguous bitmask X.
5430 'h': print integer X as if it's a signed halfword.
5431 'i': print the first nonzero HImode part of X.
5432 'j': print the first HImode part unequal to -1 of X.
5433 'k': print the first nonzero SImode part of X.
5434 'm': print the first SImode part unequal to -1 of X.
5435 'o': print integer X as if it's an unsigned 32bit word.
5436 's': "start" of DImode contiguous bitmask X.
5437 't': "start" of SImode contiguous bitmask X.
5438 'x': print integer X as if it's an unsigned halfword.
5439 */
5440
5441 void
5442 print_operand (FILE *file, rtx x, int code)
5443 {
5444 HOST_WIDE_INT ival;
5445
5446 switch (code)
5447 {
5448 case 'C':
5449 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
5450 return;
5451
5452 case 'D':
5453 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
5454 return;
5455
5456 case 'E':
5457 if (GET_CODE (x) == LE)
5458 fprintf (file, "l");
5459 else if (GET_CODE (x) == GT)
5460 fprintf (file, "h");
5461 else
5462 output_operand_lossage ("invalid comparison operator "
5463 "for 'E' output modifier");
5464 return;
5465
5466 case 'J':
5467 if (GET_CODE (x) == SYMBOL_REF)
5468 {
5469 fprintf (file, "%s", ":tls_load:");
5470 output_addr_const (file, x);
5471 }
5472 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5473 {
5474 fprintf (file, "%s", ":tls_gdcall:");
5475 output_addr_const (file, XVECEXP (x, 0, 0));
5476 }
5477 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5478 {
5479 fprintf (file, "%s", ":tls_ldcall:");
5480 const char *name = get_some_local_dynamic_name ();
5481 gcc_assert (name);
5482 assemble_name (file, name);
5483 }
5484 else
5485 output_operand_lossage ("invalid reference for 'J' output modifier");
5486 return;
5487
5488 case 'G':
5489 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5490 return;
5491
5492 case 'O':
5493 {
5494 struct s390_address ad;
5495 int ret;
5496
5497 if (!MEM_P (x))
5498 {
5499 output_operand_lossage ("memory reference expected for "
5500 "'O' output modifier");
5501 return;
5502 }
5503
5504 ret = s390_decompose_address (XEXP (x, 0), &ad);
5505
5506 if (!ret
5507 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5508 || ad.indx)
5509 {
5510 output_operand_lossage ("invalid address for 'O' output modifier");
5511 return;
5512 }
5513
5514 if (ad.disp)
5515 output_addr_const (file, ad.disp);
5516 else
5517 fprintf (file, "0");
5518 }
5519 return;
5520
5521 case 'R':
5522 {
5523 struct s390_address ad;
5524 int ret;
5525
5526 if (!MEM_P (x))
5527 {
5528 output_operand_lossage ("memory reference expected for "
5529 "'R' output modifier");
5530 return;
5531 }
5532
5533 ret = s390_decompose_address (XEXP (x, 0), &ad);
5534
5535 if (!ret
5536 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5537 || ad.indx)
5538 {
5539 output_operand_lossage ("invalid address for 'R' output modifier");
5540 return;
5541 }
5542
5543 if (ad.base)
5544 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5545 else
5546 fprintf (file, "0");
5547 }
5548 return;
5549
5550 case 'S':
5551 {
5552 struct s390_address ad;
5553 int ret;
5554
5555 if (!MEM_P (x))
5556 {
5557 output_operand_lossage ("memory reference expected for "
5558 "'S' output modifier");
5559 return;
5560 }
5561 ret = s390_decompose_address (XEXP (x, 0), &ad);
5562
5563 if (!ret
5564 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5565 || ad.indx)
5566 {
5567 output_operand_lossage ("invalid address for 'S' output modifier");
5568 return;
5569 }
5570
5571 if (ad.disp)
5572 output_addr_const (file, ad.disp);
5573 else
5574 fprintf (file, "0");
5575
5576 if (ad.base)
5577 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5578 }
5579 return;
5580
5581 case 'N':
5582 if (GET_CODE (x) == REG)
5583 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5584 else if (GET_CODE (x) == MEM)
5585 x = change_address (x, VOIDmode,
5586 plus_constant (Pmode, XEXP (x, 0), 4));
5587 else
5588 output_operand_lossage ("register or memory expression expected "
5589 "for 'N' output modifier");
5590 break;
5591
5592 case 'M':
5593 if (GET_CODE (x) == REG)
5594 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5595 else if (GET_CODE (x) == MEM)
5596 x = change_address (x, VOIDmode,
5597 plus_constant (Pmode, XEXP (x, 0), 8));
5598 else
5599 output_operand_lossage ("register or memory expression expected "
5600 "for 'M' output modifier");
5601 break;
5602
5603 case 'Y':
5604 print_shift_count_operand (file, x);
5605 return;
5606 }
5607
5608 switch (GET_CODE (x))
5609 {
5610 case REG:
5611 fprintf (file, "%s", reg_names[REGNO (x)]);
5612 break;
5613
5614 case MEM:
5615 output_address (XEXP (x, 0));
5616 break;
5617
5618 case CONST:
5619 case CODE_LABEL:
5620 case LABEL_REF:
5621 case SYMBOL_REF:
5622 output_addr_const (file, x);
5623 break;
5624
5625 case CONST_INT:
5626 ival = INTVAL (x);
5627 switch (code)
5628 {
5629 case 0:
5630 break;
5631 case 'b':
5632 ival &= 0xff;
5633 break;
5634 case 'c':
5635 ival = ((ival & 0xff) ^ 0x80) - 0x80;
5636 break;
5637 case 'x':
5638 ival &= 0xffff;
5639 break;
5640 case 'h':
5641 ival = ((ival & 0xffff) ^ 0x8000) - 0x8000;
5642 break;
5643 case 'i':
5644 ival = s390_extract_part (x, HImode, 0);
5645 break;
5646 case 'j':
5647 ival = s390_extract_part (x, HImode, -1);
5648 break;
5649 case 'k':
5650 ival = s390_extract_part (x, SImode, 0);
5651 break;
5652 case 'm':
5653 ival = s390_extract_part (x, SImode, -1);
5654 break;
5655 case 'o':
5656 ival &= 0xffffffff;
5657 break;
5658 case 'e': case 'f':
5659 case 's': case 't':
5660 {
5661 int pos, len;
5662 bool ok;
5663
5664 len = (code == 's' || code == 'e' ? 64 : 32);
5665 ok = s390_contiguous_bitmask_p (ival, len, &pos, &len);
5666 gcc_assert (ok);
5667 if (code == 's' || code == 't')
5668 ival = 64 - pos - len;
5669 else
5670 ival = 64 - 1 - pos;
5671 }
5672 break;
5673 default:
5674 output_operand_lossage ("invalid constant for output modifier '%c'", code);
5675 }
5676 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
5677 break;
5678
5679 case CONST_DOUBLE:
5680 gcc_assert (GET_MODE (x) == VOIDmode);
5681 if (code == 'b')
5682 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
5683 else if (code == 'x')
5684 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
5685 else if (code == 'h')
5686 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5687 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
5688 else
5689 {
5690 if (code == 0)
5691 output_operand_lossage ("invalid constant - try using "
5692 "an output modifier");
5693 else
5694 output_operand_lossage ("invalid constant for output modifier '%c'",
5695 code);
5696 }
5697 break;
5698
5699 default:
5700 if (code == 0)
5701 output_operand_lossage ("invalid expression - try using "
5702 "an output modifier");
5703 else
5704 output_operand_lossage ("invalid expression for output "
5705 "modifier '%c'", code);
5706 break;
5707 }
5708 }
5709
5710 /* Target hook for assembling integer objects. We need to define it
5711 here to work a round a bug in some versions of GAS, which couldn't
5712 handle values smaller than INT_MIN when printed in decimal. */
5713
5714 static bool
5715 s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
5716 {
5717 if (size == 8 && aligned_p
5718 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5719 {
5720 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5721 INTVAL (x));
5722 return true;
5723 }
5724 return default_assemble_integer (x, size, aligned_p);
5725 }
5726
5727 /* Returns true if register REGNO is used for forming
5728 a memory address in expression X. */
5729
5730 static bool
5731 reg_used_in_mem_p (int regno, rtx x)
5732 {
5733 enum rtx_code code = GET_CODE (x);
5734 int i, j;
5735 const char *fmt;
5736
5737 if (code == MEM)
5738 {
5739 if (refers_to_regno_p (regno, XEXP (x, 0)))
5740 return true;
5741 }
5742 else if (code == SET
5743 && GET_CODE (SET_DEST (x)) == PC)
5744 {
5745 if (refers_to_regno_p (regno, SET_SRC (x)))
5746 return true;
5747 }
5748
5749 fmt = GET_RTX_FORMAT (code);
5750 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5751 {
5752 if (fmt[i] == 'e'
5753 && reg_used_in_mem_p (regno, XEXP (x, i)))
5754 return true;
5755
5756 else if (fmt[i] == 'E')
5757 for (j = 0; j < XVECLEN (x, i); j++)
5758 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
5759 return true;
5760 }
5761 return false;
5762 }
5763
5764 /* Returns true if expression DEP_RTX sets an address register
5765 used by instruction INSN to address memory. */
5766
5767 static bool
5768 addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn)
5769 {
5770 rtx target, pat;
5771
5772 if (NONJUMP_INSN_P (dep_rtx))
5773 dep_rtx = PATTERN (dep_rtx);
5774
5775 if (GET_CODE (dep_rtx) == SET)
5776 {
5777 target = SET_DEST (dep_rtx);
5778 if (GET_CODE (target) == STRICT_LOW_PART)
5779 target = XEXP (target, 0);
5780 while (GET_CODE (target) == SUBREG)
5781 target = SUBREG_REG (target);
5782
5783 if (GET_CODE (target) == REG)
5784 {
5785 int regno = REGNO (target);
5786
5787 if (s390_safe_attr_type (insn) == TYPE_LA)
5788 {
5789 pat = PATTERN (insn);
5790 if (GET_CODE (pat) == PARALLEL)
5791 {
5792 gcc_assert (XVECLEN (pat, 0) == 2);
5793 pat = XVECEXP (pat, 0, 0);
5794 }
5795 gcc_assert (GET_CODE (pat) == SET);
5796 return refers_to_regno_p (regno, SET_SRC (pat));
5797 }
5798 else if (get_attr_atype (insn) == ATYPE_AGEN)
5799 return reg_used_in_mem_p (regno, PATTERN (insn));
5800 }
5801 }
5802 return false;
5803 }
5804
5805 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
5806
5807 int
5808 s390_agen_dep_p (rtx_insn *dep_insn, rtx_insn *insn)
5809 {
5810 rtx dep_rtx = PATTERN (dep_insn);
5811 int i;
5812
5813 if (GET_CODE (dep_rtx) == SET
5814 && addr_generation_dependency_p (dep_rtx, insn))
5815 return 1;
5816 else if (GET_CODE (dep_rtx) == PARALLEL)
5817 {
5818 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5819 {
5820 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5821 return 1;
5822 }
5823 }
5824 return 0;
5825 }
5826
5827
5828 /* A C statement (sans semicolon) to update the integer scheduling priority
5829 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5830 reduce the priority to execute INSN later. Do not define this macro if
5831 you do not need to adjust the scheduling priorities of insns.
5832
5833 A STD instruction should be scheduled earlier,
5834 in order to use the bypass. */
5835 static int
5836 s390_adjust_priority (rtx_insn *insn, int priority)
5837 {
5838 if (! INSN_P (insn))
5839 return priority;
5840
5841 if (s390_tune != PROCESSOR_2084_Z990
5842 && s390_tune != PROCESSOR_2094_Z9_109
5843 && s390_tune != PROCESSOR_2097_Z10
5844 && s390_tune != PROCESSOR_2817_Z196
5845 && s390_tune != PROCESSOR_2827_ZEC12)
5846 return priority;
5847
5848 switch (s390_safe_attr_type (insn))
5849 {
5850 case TYPE_FSTOREDF:
5851 case TYPE_FSTORESF:
5852 priority = priority << 3;
5853 break;
5854 case TYPE_STORE:
5855 case TYPE_STM:
5856 priority = priority << 1;
5857 break;
5858 default:
5859 break;
5860 }
5861 return priority;
5862 }
5863
5864
5865 /* The number of instructions that can be issued per cycle. */
5866
5867 static int
5868 s390_issue_rate (void)
5869 {
5870 switch (s390_tune)
5871 {
5872 case PROCESSOR_2084_Z990:
5873 case PROCESSOR_2094_Z9_109:
5874 case PROCESSOR_2817_Z196:
5875 return 3;
5876 case PROCESSOR_2097_Z10:
5877 case PROCESSOR_2827_ZEC12:
5878 return 2;
5879 default:
5880 return 1;
5881 }
5882 }
5883
5884 static int
5885 s390_first_cycle_multipass_dfa_lookahead (void)
5886 {
5887 return 4;
5888 }
5889
5890 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5891 Fix up MEMs as required. */
5892
5893 static void
5894 annotate_constant_pool_refs (rtx *x)
5895 {
5896 int i, j;
5897 const char *fmt;
5898
5899 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5900 || !CONSTANT_POOL_ADDRESS_P (*x));
5901
5902 /* Literal pool references can only occur inside a MEM ... */
5903 if (GET_CODE (*x) == MEM)
5904 {
5905 rtx memref = XEXP (*x, 0);
5906
5907 if (GET_CODE (memref) == SYMBOL_REF
5908 && CONSTANT_POOL_ADDRESS_P (memref))
5909 {
5910 rtx base = cfun->machine->base_reg;
5911 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5912 UNSPEC_LTREF);
5913
5914 *x = replace_equiv_address (*x, addr);
5915 return;
5916 }
5917
5918 if (GET_CODE (memref) == CONST
5919 && GET_CODE (XEXP (memref, 0)) == PLUS
5920 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5921 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5922 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5923 {
5924 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5925 rtx sym = XEXP (XEXP (memref, 0), 0);
5926 rtx base = cfun->machine->base_reg;
5927 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5928 UNSPEC_LTREF);
5929
5930 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
5931 return;
5932 }
5933 }
5934
5935 /* ... or a load-address type pattern. */
5936 if (GET_CODE (*x) == SET)
5937 {
5938 rtx addrref = SET_SRC (*x);
5939
5940 if (GET_CODE (addrref) == SYMBOL_REF
5941 && CONSTANT_POOL_ADDRESS_P (addrref))
5942 {
5943 rtx base = cfun->machine->base_reg;
5944 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5945 UNSPEC_LTREF);
5946
5947 SET_SRC (*x) = addr;
5948 return;
5949 }
5950
5951 if (GET_CODE (addrref) == CONST
5952 && GET_CODE (XEXP (addrref, 0)) == PLUS
5953 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5954 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5955 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5956 {
5957 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5958 rtx sym = XEXP (XEXP (addrref, 0), 0);
5959 rtx base = cfun->machine->base_reg;
5960 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5961 UNSPEC_LTREF);
5962
5963 SET_SRC (*x) = plus_constant (Pmode, addr, off);
5964 return;
5965 }
5966 }
5967
5968 /* Annotate LTREL_BASE as well. */
5969 if (GET_CODE (*x) == UNSPEC
5970 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5971 {
5972 rtx base = cfun->machine->base_reg;
5973 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5974 UNSPEC_LTREL_BASE);
5975 return;
5976 }
5977
5978 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5979 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5980 {
5981 if (fmt[i] == 'e')
5982 {
5983 annotate_constant_pool_refs (&XEXP (*x, i));
5984 }
5985 else if (fmt[i] == 'E')
5986 {
5987 for (j = 0; j < XVECLEN (*x, i); j++)
5988 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5989 }
5990 }
5991 }
5992
5993 /* Split all branches that exceed the maximum distance.
5994 Returns true if this created a new literal pool entry. */
5995
5996 static int
5997 s390_split_branches (void)
5998 {
5999 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
6000 int new_literal = 0, ret;
6001 rtx_insn *insn;
6002 rtx pat, target;
6003 rtx *label;
6004
6005 /* We need correct insn addresses. */
6006
6007 shorten_branches (get_insns ());
6008
6009 /* Find all branches that exceed 64KB, and split them. */
6010
6011 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6012 {
6013 if (! JUMP_P (insn) || tablejump_p (insn, NULL, NULL))
6014 continue;
6015
6016 pat = PATTERN (insn);
6017 if (GET_CODE (pat) == PARALLEL)
6018 pat = XVECEXP (pat, 0, 0);
6019 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
6020 continue;
6021
6022 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
6023 {
6024 label = &SET_SRC (pat);
6025 }
6026 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
6027 {
6028 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
6029 label = &XEXP (SET_SRC (pat), 1);
6030 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
6031 label = &XEXP (SET_SRC (pat), 2);
6032 else
6033 continue;
6034 }
6035 else
6036 continue;
6037
6038 if (get_attr_length (insn) <= 4)
6039 continue;
6040
6041 /* We are going to use the return register as scratch register,
6042 make sure it will be saved/restored by the prologue/epilogue. */
6043 cfun_frame_layout.save_return_addr_p = 1;
6044
6045 if (!flag_pic)
6046 {
6047 new_literal = 1;
6048 rtx mem = force_const_mem (Pmode, *label);
6049 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, mem), insn);
6050 INSN_ADDRESSES_NEW (set_insn, -1);
6051 annotate_constant_pool_refs (&PATTERN (set_insn));
6052
6053 target = temp_reg;
6054 }
6055 else
6056 {
6057 new_literal = 1;
6058 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
6059 UNSPEC_LTREL_OFFSET);
6060 target = gen_rtx_CONST (Pmode, target);
6061 target = force_const_mem (Pmode, target);
6062 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
6063 INSN_ADDRESSES_NEW (set_insn, -1);
6064 annotate_constant_pool_refs (&PATTERN (set_insn));
6065
6066 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
6067 cfun->machine->base_reg),
6068 UNSPEC_LTREL_BASE);
6069 target = gen_rtx_PLUS (Pmode, temp_reg, target);
6070 }
6071
6072 ret = validate_change (insn, label, target, 0);
6073 gcc_assert (ret);
6074 }
6075
6076 return new_literal;
6077 }
6078
6079
6080 /* Find an annotated literal pool symbol referenced in RTX X,
6081 and store it at REF. Will abort if X contains references to
6082 more than one such pool symbol; multiple references to the same
6083 symbol are allowed, however.
6084
6085 The rtx pointed to by REF must be initialized to NULL_RTX
6086 by the caller before calling this routine. */
6087
6088 static void
6089 find_constant_pool_ref (rtx x, rtx *ref)
6090 {
6091 int i, j;
6092 const char *fmt;
6093
6094 /* Ignore LTREL_BASE references. */
6095 if (GET_CODE (x) == UNSPEC
6096 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6097 return;
6098 /* Likewise POOL_ENTRY insns. */
6099 if (GET_CODE (x) == UNSPEC_VOLATILE
6100 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
6101 return;
6102
6103 gcc_assert (GET_CODE (x) != SYMBOL_REF
6104 || !CONSTANT_POOL_ADDRESS_P (x));
6105
6106 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
6107 {
6108 rtx sym = XVECEXP (x, 0, 0);
6109 gcc_assert (GET_CODE (sym) == SYMBOL_REF
6110 && CONSTANT_POOL_ADDRESS_P (sym));
6111
6112 if (*ref == NULL_RTX)
6113 *ref = sym;
6114 else
6115 gcc_assert (*ref == sym);
6116
6117 return;
6118 }
6119
6120 fmt = GET_RTX_FORMAT (GET_CODE (x));
6121 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6122 {
6123 if (fmt[i] == 'e')
6124 {
6125 find_constant_pool_ref (XEXP (x, i), ref);
6126 }
6127 else if (fmt[i] == 'E')
6128 {
6129 for (j = 0; j < XVECLEN (x, i); j++)
6130 find_constant_pool_ref (XVECEXP (x, i, j), ref);
6131 }
6132 }
6133 }
6134
6135 /* Replace every reference to the annotated literal pool
6136 symbol REF in X by its base plus OFFSET. */
6137
6138 static void
6139 replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
6140 {
6141 int i, j;
6142 const char *fmt;
6143
6144 gcc_assert (*x != ref);
6145
6146 if (GET_CODE (*x) == UNSPEC
6147 && XINT (*x, 1) == UNSPEC_LTREF
6148 && XVECEXP (*x, 0, 0) == ref)
6149 {
6150 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6151 return;
6152 }
6153
6154 if (GET_CODE (*x) == PLUS
6155 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6156 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6157 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6158 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
6159 {
6160 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
6161 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
6162 return;
6163 }
6164
6165 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6166 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6167 {
6168 if (fmt[i] == 'e')
6169 {
6170 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
6171 }
6172 else if (fmt[i] == 'E')
6173 {
6174 for (j = 0; j < XVECLEN (*x, i); j++)
6175 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
6176 }
6177 }
6178 }
6179
6180 /* Check whether X contains an UNSPEC_LTREL_BASE.
6181 Return its constant pool symbol if found, NULL_RTX otherwise. */
6182
6183 static rtx
6184 find_ltrel_base (rtx x)
6185 {
6186 int i, j;
6187 const char *fmt;
6188
6189 if (GET_CODE (x) == UNSPEC
6190 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6191 return XVECEXP (x, 0, 0);
6192
6193 fmt = GET_RTX_FORMAT (GET_CODE (x));
6194 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6195 {
6196 if (fmt[i] == 'e')
6197 {
6198 rtx fnd = find_ltrel_base (XEXP (x, i));
6199 if (fnd)
6200 return fnd;
6201 }
6202 else if (fmt[i] == 'E')
6203 {
6204 for (j = 0; j < XVECLEN (x, i); j++)
6205 {
6206 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6207 if (fnd)
6208 return fnd;
6209 }
6210 }
6211 }
6212
6213 return NULL_RTX;
6214 }
6215
6216 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
6217
6218 static void
6219 replace_ltrel_base (rtx *x)
6220 {
6221 int i, j;
6222 const char *fmt;
6223
6224 if (GET_CODE (*x) == UNSPEC
6225 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
6226 {
6227 *x = XVECEXP (*x, 0, 1);
6228 return;
6229 }
6230
6231 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6232 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6233 {
6234 if (fmt[i] == 'e')
6235 {
6236 replace_ltrel_base (&XEXP (*x, i));
6237 }
6238 else if (fmt[i] == 'E')
6239 {
6240 for (j = 0; j < XVECLEN (*x, i); j++)
6241 replace_ltrel_base (&XVECEXP (*x, i, j));
6242 }
6243 }
6244 }
6245
6246
6247 /* We keep a list of constants which we have to add to internal
6248 constant tables in the middle of large functions. */
6249
6250 #define NR_C_MODES 11
6251 machine_mode constant_modes[NR_C_MODES] =
6252 {
6253 TFmode, TImode, TDmode,
6254 DFmode, DImode, DDmode,
6255 SFmode, SImode, SDmode,
6256 HImode,
6257 QImode
6258 };
6259
6260 struct constant
6261 {
6262 struct constant *next;
6263 rtx value;
6264 rtx_code_label *label;
6265 };
6266
6267 struct constant_pool
6268 {
6269 struct constant_pool *next;
6270 rtx_insn *first_insn;
6271 rtx_insn *pool_insn;
6272 bitmap insns;
6273 rtx_insn *emit_pool_after;
6274
6275 struct constant *constants[NR_C_MODES];
6276 struct constant *execute;
6277 rtx_code_label *label;
6278 int size;
6279 };
6280
6281 /* Allocate new constant_pool structure. */
6282
6283 static struct constant_pool *
6284 s390_alloc_pool (void)
6285 {
6286 struct constant_pool *pool;
6287 int i;
6288
6289 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6290 pool->next = NULL;
6291 for (i = 0; i < NR_C_MODES; i++)
6292 pool->constants[i] = NULL;
6293
6294 pool->execute = NULL;
6295 pool->label = gen_label_rtx ();
6296 pool->first_insn = NULL;
6297 pool->pool_insn = NULL;
6298 pool->insns = BITMAP_ALLOC (NULL);
6299 pool->size = 0;
6300 pool->emit_pool_after = NULL;
6301
6302 return pool;
6303 }
6304
6305 /* Create new constant pool covering instructions starting at INSN
6306 and chain it to the end of POOL_LIST. */
6307
6308 static struct constant_pool *
6309 s390_start_pool (struct constant_pool **pool_list, rtx_insn *insn)
6310 {
6311 struct constant_pool *pool, **prev;
6312
6313 pool = s390_alloc_pool ();
6314 pool->first_insn = insn;
6315
6316 for (prev = pool_list; *prev; prev = &(*prev)->next)
6317 ;
6318 *prev = pool;
6319
6320 return pool;
6321 }
6322
6323 /* End range of instructions covered by POOL at INSN and emit
6324 placeholder insn representing the pool. */
6325
6326 static void
6327 s390_end_pool (struct constant_pool *pool, rtx_insn *insn)
6328 {
6329 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6330
6331 if (!insn)
6332 insn = get_last_insn ();
6333
6334 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6335 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6336 }
6337
6338 /* Add INSN to the list of insns covered by POOL. */
6339
6340 static void
6341 s390_add_pool_insn (struct constant_pool *pool, rtx insn)
6342 {
6343 bitmap_set_bit (pool->insns, INSN_UID (insn));
6344 }
6345
6346 /* Return pool out of POOL_LIST that covers INSN. */
6347
6348 static struct constant_pool *
6349 s390_find_pool (struct constant_pool *pool_list, rtx insn)
6350 {
6351 struct constant_pool *pool;
6352
6353 for (pool = pool_list; pool; pool = pool->next)
6354 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
6355 break;
6356
6357 return pool;
6358 }
6359
6360 /* Add constant VAL of mode MODE to the constant pool POOL. */
6361
6362 static void
6363 s390_add_constant (struct constant_pool *pool, rtx val, machine_mode mode)
6364 {
6365 struct constant *c;
6366 int i;
6367
6368 for (i = 0; i < NR_C_MODES; i++)
6369 if (constant_modes[i] == mode)
6370 break;
6371 gcc_assert (i != NR_C_MODES);
6372
6373 for (c = pool->constants[i]; c != NULL; c = c->next)
6374 if (rtx_equal_p (val, c->value))
6375 break;
6376
6377 if (c == NULL)
6378 {
6379 c = (struct constant *) xmalloc (sizeof *c);
6380 c->value = val;
6381 c->label = gen_label_rtx ();
6382 c->next = pool->constants[i];
6383 pool->constants[i] = c;
6384 pool->size += GET_MODE_SIZE (mode);
6385 }
6386 }
6387
6388 /* Return an rtx that represents the offset of X from the start of
6389 pool POOL. */
6390
6391 static rtx
6392 s390_pool_offset (struct constant_pool *pool, rtx x)
6393 {
6394 rtx label;
6395
6396 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6397 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6398 UNSPEC_POOL_OFFSET);
6399 return gen_rtx_CONST (GET_MODE (x), x);
6400 }
6401
6402 /* Find constant VAL of mode MODE in the constant pool POOL.
6403 Return an RTX describing the distance from the start of
6404 the pool to the location of the new constant. */
6405
6406 static rtx
6407 s390_find_constant (struct constant_pool *pool, rtx val,
6408 machine_mode mode)
6409 {
6410 struct constant *c;
6411 int i;
6412
6413 for (i = 0; i < NR_C_MODES; i++)
6414 if (constant_modes[i] == mode)
6415 break;
6416 gcc_assert (i != NR_C_MODES);
6417
6418 for (c = pool->constants[i]; c != NULL; c = c->next)
6419 if (rtx_equal_p (val, c->value))
6420 break;
6421
6422 gcc_assert (c);
6423
6424 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6425 }
6426
6427 /* Check whether INSN is an execute. Return the label_ref to its
6428 execute target template if so, NULL_RTX otherwise. */
6429
6430 static rtx
6431 s390_execute_label (rtx insn)
6432 {
6433 if (NONJUMP_INSN_P (insn)
6434 && GET_CODE (PATTERN (insn)) == PARALLEL
6435 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6436 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6437 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6438
6439 return NULL_RTX;
6440 }
6441
6442 /* Add execute target for INSN to the constant pool POOL. */
6443
6444 static void
6445 s390_add_execute (struct constant_pool *pool, rtx insn)
6446 {
6447 struct constant *c;
6448
6449 for (c = pool->execute; c != NULL; c = c->next)
6450 if (INSN_UID (insn) == INSN_UID (c->value))
6451 break;
6452
6453 if (c == NULL)
6454 {
6455 c = (struct constant *) xmalloc (sizeof *c);
6456 c->value = insn;
6457 c->label = gen_label_rtx ();
6458 c->next = pool->execute;
6459 pool->execute = c;
6460 pool->size += 6;
6461 }
6462 }
6463
6464 /* Find execute target for INSN in the constant pool POOL.
6465 Return an RTX describing the distance from the start of
6466 the pool to the location of the execute target. */
6467
6468 static rtx
6469 s390_find_execute (struct constant_pool *pool, rtx insn)
6470 {
6471 struct constant *c;
6472
6473 for (c = pool->execute; c != NULL; c = c->next)
6474 if (INSN_UID (insn) == INSN_UID (c->value))
6475 break;
6476
6477 gcc_assert (c);
6478
6479 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
6480 }
6481
6482 /* For an execute INSN, extract the execute target template. */
6483
6484 static rtx
6485 s390_execute_target (rtx insn)
6486 {
6487 rtx pattern = PATTERN (insn);
6488 gcc_assert (s390_execute_label (insn));
6489
6490 if (XVECLEN (pattern, 0) == 2)
6491 {
6492 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6493 }
6494 else
6495 {
6496 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6497 int i;
6498
6499 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6500 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6501
6502 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6503 }
6504
6505 return pattern;
6506 }
6507
6508 /* Indicate that INSN cannot be duplicated. This is the case for
6509 execute insns that carry a unique label. */
6510
6511 static bool
6512 s390_cannot_copy_insn_p (rtx_insn *insn)
6513 {
6514 rtx label = s390_execute_label (insn);
6515 return label && label != const0_rtx;
6516 }
6517
6518 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
6519 do not emit the pool base label. */
6520
6521 static void
6522 s390_dump_pool (struct constant_pool *pool, bool remote_label)
6523 {
6524 struct constant *c;
6525 rtx_insn *insn = pool->pool_insn;
6526 int i;
6527
6528 /* Switch to rodata section. */
6529 if (TARGET_CPU_ZARCH)
6530 {
6531 insn = emit_insn_after (gen_pool_section_start (), insn);
6532 INSN_ADDRESSES_NEW (insn, -1);
6533 }
6534
6535 /* Ensure minimum pool alignment. */
6536 if (TARGET_CPU_ZARCH)
6537 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
6538 else
6539 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
6540 INSN_ADDRESSES_NEW (insn, -1);
6541
6542 /* Emit pool base label. */
6543 if (!remote_label)
6544 {
6545 insn = emit_label_after (pool->label, insn);
6546 INSN_ADDRESSES_NEW (insn, -1);
6547 }
6548
6549 /* Dump constants in descending alignment requirement order,
6550 ensuring proper alignment for every constant. */
6551 for (i = 0; i < NR_C_MODES; i++)
6552 for (c = pool->constants[i]; c; c = c->next)
6553 {
6554 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
6555 rtx value = copy_rtx (c->value);
6556 if (GET_CODE (value) == CONST
6557 && GET_CODE (XEXP (value, 0)) == UNSPEC
6558 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
6559 && XVECLEN (XEXP (value, 0), 0) == 1)
6560 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
6561
6562 insn = emit_label_after (c->label, insn);
6563 INSN_ADDRESSES_NEW (insn, -1);
6564
6565 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
6566 gen_rtvec (1, value),
6567 UNSPECV_POOL_ENTRY);
6568 insn = emit_insn_after (value, insn);
6569 INSN_ADDRESSES_NEW (insn, -1);
6570 }
6571
6572 /* Ensure minimum alignment for instructions. */
6573 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
6574 INSN_ADDRESSES_NEW (insn, -1);
6575
6576 /* Output in-pool execute template insns. */
6577 for (c = pool->execute; c; c = c->next)
6578 {
6579 insn = emit_label_after (c->label, insn);
6580 INSN_ADDRESSES_NEW (insn, -1);
6581
6582 insn = emit_insn_after (s390_execute_target (c->value), insn);
6583 INSN_ADDRESSES_NEW (insn, -1);
6584 }
6585
6586 /* Switch back to previous section. */
6587 if (TARGET_CPU_ZARCH)
6588 {
6589 insn = emit_insn_after (gen_pool_section_end (), insn);
6590 INSN_ADDRESSES_NEW (insn, -1);
6591 }
6592
6593 insn = emit_barrier_after (insn);
6594 INSN_ADDRESSES_NEW (insn, -1);
6595
6596 /* Remove placeholder insn. */
6597 remove_insn (pool->pool_insn);
6598 }
6599
6600 /* Free all memory used by POOL. */
6601
6602 static void
6603 s390_free_pool (struct constant_pool *pool)
6604 {
6605 struct constant *c, *next;
6606 int i;
6607
6608 for (i = 0; i < NR_C_MODES; i++)
6609 for (c = pool->constants[i]; c; c = next)
6610 {
6611 next = c->next;
6612 free (c);
6613 }
6614
6615 for (c = pool->execute; c; c = next)
6616 {
6617 next = c->next;
6618 free (c);
6619 }
6620
6621 BITMAP_FREE (pool->insns);
6622 free (pool);
6623 }
6624
6625
6626 /* Collect main literal pool. Return NULL on overflow. */
6627
6628 static struct constant_pool *
6629 s390_mainpool_start (void)
6630 {
6631 struct constant_pool *pool;
6632 rtx_insn *insn;
6633
6634 pool = s390_alloc_pool ();
6635
6636 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6637 {
6638 if (NONJUMP_INSN_P (insn)
6639 && GET_CODE (PATTERN (insn)) == SET
6640 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6641 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
6642 {
6643 /* There might be two main_pool instructions if base_reg
6644 is call-clobbered; one for shrink-wrapped code and one
6645 for the rest. We want to keep the first. */
6646 if (pool->pool_insn)
6647 {
6648 insn = PREV_INSN (insn);
6649 delete_insn (NEXT_INSN (insn));
6650 continue;
6651 }
6652 pool->pool_insn = insn;
6653 }
6654
6655 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6656 {
6657 s390_add_execute (pool, insn);
6658 }
6659 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6660 {
6661 rtx pool_ref = NULL_RTX;
6662 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6663 if (pool_ref)
6664 {
6665 rtx constant = get_pool_constant (pool_ref);
6666 machine_mode mode = get_pool_mode (pool_ref);
6667 s390_add_constant (pool, constant, mode);
6668 }
6669 }
6670
6671 /* If hot/cold partitioning is enabled we have to make sure that
6672 the literal pool is emitted in the same section where the
6673 initialization of the literal pool base pointer takes place.
6674 emit_pool_after is only used in the non-overflow case on non
6675 Z cpus where we can emit the literal pool at the end of the
6676 function body within the text section. */
6677 if (NOTE_P (insn)
6678 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6679 && !pool->emit_pool_after)
6680 pool->emit_pool_after = PREV_INSN (insn);
6681 }
6682
6683 gcc_assert (pool->pool_insn || pool->size == 0);
6684
6685 if (pool->size >= 4096)
6686 {
6687 /* We're going to chunkify the pool, so remove the main
6688 pool placeholder insn. */
6689 remove_insn (pool->pool_insn);
6690
6691 s390_free_pool (pool);
6692 pool = NULL;
6693 }
6694
6695 /* If the functions ends with the section where the literal pool
6696 should be emitted set the marker to its end. */
6697 if (pool && !pool->emit_pool_after)
6698 pool->emit_pool_after = get_last_insn ();
6699
6700 return pool;
6701 }
6702
6703 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6704 Modify the current function to output the pool constants as well as
6705 the pool register setup instruction. */
6706
6707 static void
6708 s390_mainpool_finish (struct constant_pool *pool)
6709 {
6710 rtx base_reg = cfun->machine->base_reg;
6711
6712 /* If the pool is empty, we're done. */
6713 if (pool->size == 0)
6714 {
6715 /* We don't actually need a base register after all. */
6716 cfun->machine->base_reg = NULL_RTX;
6717
6718 if (pool->pool_insn)
6719 remove_insn (pool->pool_insn);
6720 s390_free_pool (pool);
6721 return;
6722 }
6723
6724 /* We need correct insn addresses. */
6725 shorten_branches (get_insns ());
6726
6727 /* On zSeries, we use a LARL to load the pool register. The pool is
6728 located in the .rodata section, so we emit it after the function. */
6729 if (TARGET_CPU_ZARCH)
6730 {
6731 rtx set = gen_main_base_64 (base_reg, pool->label);
6732 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
6733 INSN_ADDRESSES_NEW (insn, -1);
6734 remove_insn (pool->pool_insn);
6735
6736 insn = get_last_insn ();
6737 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6738 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6739
6740 s390_dump_pool (pool, 0);
6741 }
6742
6743 /* On S/390, if the total size of the function's code plus literal pool
6744 does not exceed 4096 bytes, we use BASR to set up a function base
6745 pointer, and emit the literal pool at the end of the function. */
6746 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
6747 + pool->size + 8 /* alignment slop */ < 4096)
6748 {
6749 rtx set = gen_main_base_31_small (base_reg, pool->label);
6750 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
6751 INSN_ADDRESSES_NEW (insn, -1);
6752 remove_insn (pool->pool_insn);
6753
6754 insn = emit_label_after (pool->label, insn);
6755 INSN_ADDRESSES_NEW (insn, -1);
6756
6757 /* emit_pool_after will be set by s390_mainpool_start to the
6758 last insn of the section where the literal pool should be
6759 emitted. */
6760 insn = pool->emit_pool_after;
6761
6762 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6763 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6764
6765 s390_dump_pool (pool, 1);
6766 }
6767
6768 /* Otherwise, we emit an inline literal pool and use BASR to branch
6769 over it, setting up the pool register at the same time. */
6770 else
6771 {
6772 rtx_code_label *pool_end = gen_label_rtx ();
6773
6774 rtx pat = gen_main_base_31_large (base_reg, pool->label, pool_end);
6775 rtx_insn *insn = emit_jump_insn_after (pat, pool->pool_insn);
6776 JUMP_LABEL (insn) = pool_end;
6777 INSN_ADDRESSES_NEW (insn, -1);
6778 remove_insn (pool->pool_insn);
6779
6780 insn = emit_label_after (pool->label, insn);
6781 INSN_ADDRESSES_NEW (insn, -1);
6782
6783 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6784 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6785
6786 insn = emit_label_after (pool_end, pool->pool_insn);
6787 INSN_ADDRESSES_NEW (insn, -1);
6788
6789 s390_dump_pool (pool, 1);
6790 }
6791
6792
6793 /* Replace all literal pool references. */
6794
6795 for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn))
6796 {
6797 if (INSN_P (insn))
6798 replace_ltrel_base (&PATTERN (insn));
6799
6800 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6801 {
6802 rtx addr, pool_ref = NULL_RTX;
6803 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6804 if (pool_ref)
6805 {
6806 if (s390_execute_label (insn))
6807 addr = s390_find_execute (pool, insn);
6808 else
6809 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6810 get_pool_mode (pool_ref));
6811
6812 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6813 INSN_CODE (insn) = -1;
6814 }
6815 }
6816 }
6817
6818
6819 /* Free the pool. */
6820 s390_free_pool (pool);
6821 }
6822
6823 /* POOL holds the main literal pool as collected by s390_mainpool_start.
6824 We have decided we cannot use this pool, so revert all changes
6825 to the current function that were done by s390_mainpool_start. */
6826 static void
6827 s390_mainpool_cancel (struct constant_pool *pool)
6828 {
6829 /* We didn't actually change the instruction stream, so simply
6830 free the pool memory. */
6831 s390_free_pool (pool);
6832 }
6833
6834
6835 /* Chunkify the literal pool. */
6836
6837 #define S390_POOL_CHUNK_MIN 0xc00
6838 #define S390_POOL_CHUNK_MAX 0xe00
6839
6840 static struct constant_pool *
6841 s390_chunkify_start (void)
6842 {
6843 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6844 int extra_size = 0;
6845 bitmap far_labels;
6846 rtx pending_ltrel = NULL_RTX;
6847 rtx_insn *insn;
6848
6849 rtx (*gen_reload_base) (rtx, rtx) =
6850 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
6851
6852
6853 /* We need correct insn addresses. */
6854
6855 shorten_branches (get_insns ());
6856
6857 /* Scan all insns and move literals to pool chunks. */
6858
6859 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6860 {
6861 bool section_switch_p = false;
6862
6863 /* Check for pending LTREL_BASE. */
6864 if (INSN_P (insn))
6865 {
6866 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6867 if (ltrel_base)
6868 {
6869 gcc_assert (ltrel_base == pending_ltrel);
6870 pending_ltrel = NULL_RTX;
6871 }
6872 }
6873
6874 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
6875 {
6876 if (!curr_pool)
6877 curr_pool = s390_start_pool (&pool_list, insn);
6878
6879 s390_add_execute (curr_pool, insn);
6880 s390_add_pool_insn (curr_pool, insn);
6881 }
6882 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
6883 {
6884 rtx pool_ref = NULL_RTX;
6885 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6886 if (pool_ref)
6887 {
6888 rtx constant = get_pool_constant (pool_ref);
6889 machine_mode mode = get_pool_mode (pool_ref);
6890
6891 if (!curr_pool)
6892 curr_pool = s390_start_pool (&pool_list, insn);
6893
6894 s390_add_constant (curr_pool, constant, mode);
6895 s390_add_pool_insn (curr_pool, insn);
6896
6897 /* Don't split the pool chunk between a LTREL_OFFSET load
6898 and the corresponding LTREL_BASE. */
6899 if (GET_CODE (constant) == CONST
6900 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6901 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6902 {
6903 gcc_assert (!pending_ltrel);
6904 pending_ltrel = pool_ref;
6905 }
6906 }
6907 }
6908
6909 if (JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) || LABEL_P (insn))
6910 {
6911 if (curr_pool)
6912 s390_add_pool_insn (curr_pool, insn);
6913 /* An LTREL_BASE must follow within the same basic block. */
6914 gcc_assert (!pending_ltrel);
6915 }
6916
6917 if (NOTE_P (insn))
6918 switch (NOTE_KIND (insn))
6919 {
6920 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6921 section_switch_p = true;
6922 break;
6923 case NOTE_INSN_VAR_LOCATION:
6924 case NOTE_INSN_CALL_ARG_LOCATION:
6925 continue;
6926 default:
6927 break;
6928 }
6929
6930 if (!curr_pool
6931 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6932 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
6933 continue;
6934
6935 if (TARGET_CPU_ZARCH)
6936 {
6937 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6938 continue;
6939
6940 s390_end_pool (curr_pool, NULL);
6941 curr_pool = NULL;
6942 }
6943 else
6944 {
6945 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
6946 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
6947 + extra_size;
6948
6949 /* We will later have to insert base register reload insns.
6950 Those will have an effect on code size, which we need to
6951 consider here. This calculation makes rather pessimistic
6952 worst-case assumptions. */
6953 if (LABEL_P (insn))
6954 extra_size += 6;
6955
6956 if (chunk_size < S390_POOL_CHUNK_MIN
6957 && curr_pool->size < S390_POOL_CHUNK_MIN
6958 && !section_switch_p)
6959 continue;
6960
6961 /* Pool chunks can only be inserted after BARRIERs ... */
6962 if (BARRIER_P (insn))
6963 {
6964 s390_end_pool (curr_pool, insn);
6965 curr_pool = NULL;
6966 extra_size = 0;
6967 }
6968
6969 /* ... so if we don't find one in time, create one. */
6970 else if (chunk_size > S390_POOL_CHUNK_MAX
6971 || curr_pool->size > S390_POOL_CHUNK_MAX
6972 || section_switch_p)
6973 {
6974 rtx_insn *label, *jump, *barrier, *next, *prev;
6975
6976 if (!section_switch_p)
6977 {
6978 /* We can insert the barrier only after a 'real' insn. */
6979 if (! NONJUMP_INSN_P (insn) && ! CALL_P (insn))
6980 continue;
6981 if (get_attr_length (insn) == 0)
6982 continue;
6983 /* Don't separate LTREL_BASE from the corresponding
6984 LTREL_OFFSET load. */
6985 if (pending_ltrel)
6986 continue;
6987 next = insn;
6988 do
6989 {
6990 insn = next;
6991 next = NEXT_INSN (insn);
6992 }
6993 while (next
6994 && NOTE_P (next)
6995 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6996 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
6997 }
6998 else
6999 {
7000 gcc_assert (!pending_ltrel);
7001
7002 /* The old pool has to end before the section switch
7003 note in order to make it part of the current
7004 section. */
7005 insn = PREV_INSN (insn);
7006 }
7007
7008 label = gen_label_rtx ();
7009 prev = insn;
7010 if (prev && NOTE_P (prev))
7011 prev = prev_nonnote_insn (prev);
7012 if (prev)
7013 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
7014 INSN_LOCATION (prev));
7015 else
7016 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
7017 barrier = emit_barrier_after (jump);
7018 insn = emit_label_after (label, barrier);
7019 JUMP_LABEL (jump) = label;
7020 LABEL_NUSES (label) = 1;
7021
7022 INSN_ADDRESSES_NEW (jump, -1);
7023 INSN_ADDRESSES_NEW (barrier, -1);
7024 INSN_ADDRESSES_NEW (insn, -1);
7025
7026 s390_end_pool (curr_pool, barrier);
7027 curr_pool = NULL;
7028 extra_size = 0;
7029 }
7030 }
7031 }
7032
7033 if (curr_pool)
7034 s390_end_pool (curr_pool, NULL);
7035 gcc_assert (!pending_ltrel);
7036
7037 /* Find all labels that are branched into
7038 from an insn belonging to a different chunk. */
7039
7040 far_labels = BITMAP_ALLOC (NULL);
7041
7042 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7043 {
7044 rtx_jump_table_data *table;
7045
7046 /* Labels marked with LABEL_PRESERVE_P can be target
7047 of non-local jumps, so we have to mark them.
7048 The same holds for named labels.
7049
7050 Don't do that, however, if it is the label before
7051 a jump table. */
7052
7053 if (LABEL_P (insn)
7054 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
7055 {
7056 rtx_insn *vec_insn = NEXT_INSN (insn);
7057 if (! vec_insn || ! JUMP_TABLE_DATA_P (vec_insn))
7058 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
7059 }
7060 /* Check potential targets in a table jump (casesi_jump). */
7061 else if (tablejump_p (insn, NULL, &table))
7062 {
7063 rtx vec_pat = PATTERN (table);
7064 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
7065
7066 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
7067 {
7068 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
7069
7070 if (s390_find_pool (pool_list, label)
7071 != s390_find_pool (pool_list, insn))
7072 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7073 }
7074 }
7075 /* If we have a direct jump (conditional or unconditional),
7076 check all potential targets. */
7077 else if (JUMP_P (insn))
7078 {
7079 rtx pat = PATTERN (insn);
7080
7081 if (GET_CODE (pat) == PARALLEL)
7082 pat = XVECEXP (pat, 0, 0);
7083
7084 if (GET_CODE (pat) == SET)
7085 {
7086 rtx label = JUMP_LABEL (insn);
7087 if (label && !ANY_RETURN_P (label))
7088 {
7089 if (s390_find_pool (pool_list, label)
7090 != s390_find_pool (pool_list, insn))
7091 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7092 }
7093 }
7094 }
7095 }
7096
7097 /* Insert base register reload insns before every pool. */
7098
7099 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7100 {
7101 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7102 curr_pool->label);
7103 rtx_insn *insn = curr_pool->first_insn;
7104 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
7105 }
7106
7107 /* Insert base register reload insns at every far label. */
7108
7109 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7110 if (LABEL_P (insn)
7111 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
7112 {
7113 struct constant_pool *pool = s390_find_pool (pool_list, insn);
7114 if (pool)
7115 {
7116 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
7117 pool->label);
7118 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
7119 }
7120 }
7121
7122
7123 BITMAP_FREE (far_labels);
7124
7125
7126 /* Recompute insn addresses. */
7127
7128 init_insn_lengths ();
7129 shorten_branches (get_insns ());
7130
7131 return pool_list;
7132 }
7133
7134 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7135 After we have decided to use this list, finish implementing
7136 all changes to the current function as required. */
7137
7138 static void
7139 s390_chunkify_finish (struct constant_pool *pool_list)
7140 {
7141 struct constant_pool *curr_pool = NULL;
7142 rtx_insn *insn;
7143
7144
7145 /* Replace all literal pool references. */
7146
7147 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7148 {
7149 if (INSN_P (insn))
7150 replace_ltrel_base (&PATTERN (insn));
7151
7152 curr_pool = s390_find_pool (pool_list, insn);
7153 if (!curr_pool)
7154 continue;
7155
7156 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
7157 {
7158 rtx addr, pool_ref = NULL_RTX;
7159 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7160 if (pool_ref)
7161 {
7162 if (s390_execute_label (insn))
7163 addr = s390_find_execute (curr_pool, insn);
7164 else
7165 addr = s390_find_constant (curr_pool,
7166 get_pool_constant (pool_ref),
7167 get_pool_mode (pool_ref));
7168
7169 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7170 INSN_CODE (insn) = -1;
7171 }
7172 }
7173 }
7174
7175 /* Dump out all literal pools. */
7176
7177 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7178 s390_dump_pool (curr_pool, 0);
7179
7180 /* Free pool list. */
7181
7182 while (pool_list)
7183 {
7184 struct constant_pool *next = pool_list->next;
7185 s390_free_pool (pool_list);
7186 pool_list = next;
7187 }
7188 }
7189
7190 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7191 We have decided we cannot use this list, so revert all changes
7192 to the current function that were done by s390_chunkify_start. */
7193
7194 static void
7195 s390_chunkify_cancel (struct constant_pool *pool_list)
7196 {
7197 struct constant_pool *curr_pool = NULL;
7198 rtx_insn *insn;
7199
7200 /* Remove all pool placeholder insns. */
7201
7202 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7203 {
7204 /* Did we insert an extra barrier? Remove it. */
7205 rtx_insn *barrier = PREV_INSN (curr_pool->pool_insn);
7206 rtx_insn *jump = barrier? PREV_INSN (barrier) : NULL;
7207 rtx_insn *label = NEXT_INSN (curr_pool->pool_insn);
7208
7209 if (jump && JUMP_P (jump)
7210 && barrier && BARRIER_P (barrier)
7211 && label && LABEL_P (label)
7212 && GET_CODE (PATTERN (jump)) == SET
7213 && SET_DEST (PATTERN (jump)) == pc_rtx
7214 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7215 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7216 {
7217 remove_insn (jump);
7218 remove_insn (barrier);
7219 remove_insn (label);
7220 }
7221
7222 remove_insn (curr_pool->pool_insn);
7223 }
7224
7225 /* Remove all base register reload insns. */
7226
7227 for (insn = get_insns (); insn; )
7228 {
7229 rtx_insn *next_insn = NEXT_INSN (insn);
7230
7231 if (NONJUMP_INSN_P (insn)
7232 && GET_CODE (PATTERN (insn)) == SET
7233 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
7234 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
7235 remove_insn (insn);
7236
7237 insn = next_insn;
7238 }
7239
7240 /* Free pool list. */
7241
7242 while (pool_list)
7243 {
7244 struct constant_pool *next = pool_list->next;
7245 s390_free_pool (pool_list);
7246 pool_list = next;
7247 }
7248 }
7249
7250 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
7251
7252 void
7253 s390_output_pool_entry (rtx exp, machine_mode mode, unsigned int align)
7254 {
7255 REAL_VALUE_TYPE r;
7256
7257 switch (GET_MODE_CLASS (mode))
7258 {
7259 case MODE_FLOAT:
7260 case MODE_DECIMAL_FLOAT:
7261 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
7262
7263 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7264 assemble_real (r, mode, align);
7265 break;
7266
7267 case MODE_INT:
7268 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
7269 mark_symbol_refs_as_used (exp);
7270 break;
7271
7272 default:
7273 gcc_unreachable ();
7274 }
7275 }
7276
7277
7278 /* Return an RTL expression representing the value of the return address
7279 for the frame COUNT steps up from the current frame. FRAME is the
7280 frame pointer of that frame. */
7281
7282 rtx
7283 s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
7284 {
7285 int offset;
7286 rtx addr;
7287
7288 /* Without backchain, we fail for all but the current frame. */
7289
7290 if (!TARGET_BACKCHAIN && count > 0)
7291 return NULL_RTX;
7292
7293 /* For the current frame, we need to make sure the initial
7294 value of RETURN_REGNUM is actually saved. */
7295
7296 if (count == 0)
7297 {
7298 /* On non-z architectures branch splitting could overwrite r14. */
7299 if (TARGET_CPU_ZARCH)
7300 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7301 else
7302 {
7303 cfun_frame_layout.save_return_addr_p = true;
7304 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7305 }
7306 }
7307
7308 if (TARGET_PACKED_STACK)
7309 offset = -2 * UNITS_PER_LONG;
7310 else
7311 offset = RETURN_REGNUM * UNITS_PER_LONG;
7312
7313 addr = plus_constant (Pmode, frame, offset);
7314 addr = memory_address (Pmode, addr);
7315 return gen_rtx_MEM (Pmode, addr);
7316 }
7317
7318 /* Return an RTL expression representing the back chain stored in
7319 the current stack frame. */
7320
7321 rtx
7322 s390_back_chain_rtx (void)
7323 {
7324 rtx chain;
7325
7326 gcc_assert (TARGET_BACKCHAIN);
7327
7328 if (TARGET_PACKED_STACK)
7329 chain = plus_constant (Pmode, stack_pointer_rtx,
7330 STACK_POINTER_OFFSET - UNITS_PER_LONG);
7331 else
7332 chain = stack_pointer_rtx;
7333
7334 chain = gen_rtx_MEM (Pmode, chain);
7335 return chain;
7336 }
7337
7338 /* Find first call clobbered register unused in a function.
7339 This could be used as base register in a leaf function
7340 or for holding the return address before epilogue. */
7341
7342 static int
7343 find_unused_clobbered_reg (void)
7344 {
7345 int i;
7346 for (i = 0; i < 6; i++)
7347 if (!df_regs_ever_live_p (i))
7348 return i;
7349 return 0;
7350 }
7351
7352
7353 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7354 clobbered hard regs in SETREG. */
7355
7356 static void
7357 s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7358 {
7359 char *regs_ever_clobbered = (char *)data;
7360 unsigned int i, regno;
7361 machine_mode mode = GET_MODE (setreg);
7362
7363 if (GET_CODE (setreg) == SUBREG)
7364 {
7365 rtx inner = SUBREG_REG (setreg);
7366 if (!GENERAL_REG_P (inner) && !FP_REG_P (inner))
7367 return;
7368 regno = subreg_regno (setreg);
7369 }
7370 else if (GENERAL_REG_P (setreg) || FP_REG_P (setreg))
7371 regno = REGNO (setreg);
7372 else
7373 return;
7374
7375 for (i = regno;
7376 i < regno + HARD_REGNO_NREGS (regno, mode);
7377 i++)
7378 regs_ever_clobbered[i] = 1;
7379 }
7380
7381 /* Walks through all basic blocks of the current function looking
7382 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7383 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7384 each of those regs. */
7385
7386 static void
7387 s390_regs_ever_clobbered (char regs_ever_clobbered[])
7388 {
7389 basic_block cur_bb;
7390 rtx_insn *cur_insn;
7391 unsigned int i;
7392
7393 memset (regs_ever_clobbered, 0, 32);
7394
7395 /* For non-leaf functions we have to consider all call clobbered regs to be
7396 clobbered. */
7397 if (!crtl->is_leaf)
7398 {
7399 for (i = 0; i < 32; i++)
7400 regs_ever_clobbered[i] = call_really_used_regs[i];
7401 }
7402
7403 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7404 this work is done by liveness analysis (mark_regs_live_at_end).
7405 Special care is needed for functions containing landing pads. Landing pads
7406 may use the eh registers, but the code which sets these registers is not
7407 contained in that function. Hence s390_regs_ever_clobbered is not able to
7408 deal with this automatically. */
7409 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7410 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
7411 if (crtl->calls_eh_return
7412 || (cfun->machine->has_landing_pad_p
7413 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
7414 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7415
7416 /* For nonlocal gotos all call-saved registers have to be saved.
7417 This flag is also set for the unwinding code in libgcc.
7418 See expand_builtin_unwind_init. For regs_ever_live this is done by
7419 reload. */
7420 if (crtl->saves_all_registers)
7421 for (i = 0; i < 32; i++)
7422 if (!call_really_used_regs[i])
7423 regs_ever_clobbered[i] = 1;
7424
7425 FOR_EACH_BB_FN (cur_bb, cfun)
7426 {
7427 FOR_BB_INSNS (cur_bb, cur_insn)
7428 {
7429 rtx pat;
7430
7431 if (!INSN_P (cur_insn))
7432 continue;
7433
7434 pat = PATTERN (cur_insn);
7435
7436 /* Ignore GPR restore insns. */
7437 if (epilogue_completed && RTX_FRAME_RELATED_P (cur_insn))
7438 {
7439 if (GET_CODE (pat) == SET
7440 && GENERAL_REG_P (SET_DEST (pat)))
7441 {
7442 /* lgdr */
7443 if (GET_MODE (SET_SRC (pat)) == DImode
7444 && FP_REG_P (SET_SRC (pat)))
7445 continue;
7446
7447 /* l / lg */
7448 if (GET_CODE (SET_SRC (pat)) == MEM)
7449 continue;
7450 }
7451
7452 /* lm / lmg */
7453 if (GET_CODE (pat) == PARALLEL
7454 && load_multiple_operation (pat, VOIDmode))
7455 continue;
7456 }
7457
7458 note_stores (pat,
7459 s390_reg_clobbered_rtx,
7460 regs_ever_clobbered);
7461 }
7462 }
7463 }
7464
7465 /* Determine the frame area which actually has to be accessed
7466 in the function epilogue. The values are stored at the
7467 given pointers AREA_BOTTOM (address of the lowest used stack
7468 address) and AREA_TOP (address of the first item which does
7469 not belong to the stack frame). */
7470
7471 static void
7472 s390_frame_area (int *area_bottom, int *area_top)
7473 {
7474 int b, t;
7475
7476 b = INT_MAX;
7477 t = INT_MIN;
7478
7479 if (cfun_frame_layout.first_restore_gpr != -1)
7480 {
7481 b = (cfun_frame_layout.gprs_offset
7482 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
7483 t = b + (cfun_frame_layout.last_restore_gpr
7484 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
7485 }
7486
7487 if (TARGET_64BIT && cfun_save_high_fprs_p)
7488 {
7489 b = MIN (b, cfun_frame_layout.f8_offset);
7490 t = MAX (t, (cfun_frame_layout.f8_offset
7491 + cfun_frame_layout.high_fprs * 8));
7492 }
7493
7494 if (!TARGET_64BIT)
7495 {
7496 if (cfun_fpr_save_p (FPR4_REGNUM))
7497 {
7498 b = MIN (b, cfun_frame_layout.f4_offset);
7499 t = MAX (t, cfun_frame_layout.f4_offset + 8);
7500 }
7501 if (cfun_fpr_save_p (FPR6_REGNUM))
7502 {
7503 b = MIN (b, cfun_frame_layout.f4_offset + 8);
7504 t = MAX (t, cfun_frame_layout.f4_offset + 16);
7505 }
7506 }
7507 *area_bottom = b;
7508 *area_top = t;
7509 }
7510 /* Update gpr_save_slots in the frame layout trying to make use of
7511 FPRs as GPR save slots.
7512 This is a helper routine of s390_register_info. */
7513
7514 static void
7515 s390_register_info_gprtofpr ()
7516 {
7517 int save_reg_slot = FPR0_REGNUM;
7518 int i, j;
7519
7520 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
7521 return;
7522
7523 for (i = 15; i >= 6; i--)
7524 {
7525 if (cfun_gpr_save_slot (i) == 0)
7526 continue;
7527
7528 /* Advance to the next FP register which can be used as a
7529 GPR save slot. */
7530 while ((!call_really_used_regs[save_reg_slot]
7531 || df_regs_ever_live_p (save_reg_slot)
7532 || cfun_fpr_save_p (save_reg_slot))
7533 && FP_REGNO_P (save_reg_slot))
7534 save_reg_slot++;
7535 if (!FP_REGNO_P (save_reg_slot))
7536 {
7537 /* We only want to use ldgr/lgdr if we can get rid of
7538 stm/lm entirely. So undo the gpr slot allocation in
7539 case we ran out of FPR save slots. */
7540 for (j = 6; j <= 15; j++)
7541 if (FP_REGNO_P (cfun_gpr_save_slot (j)))
7542 cfun_gpr_save_slot (j) = -1;
7543 break;
7544 }
7545 cfun_gpr_save_slot (i) = save_reg_slot++;
7546 }
7547 }
7548
7549 /* Set the bits in fpr_bitmap for FPRs which need to be saved due to
7550 stdarg.
7551 This is a helper routine for s390_register_info. */
7552
7553 static void
7554 s390_register_info_stdarg_fpr ()
7555 {
7556 int i;
7557 int min_fpr;
7558 int max_fpr;
7559
7560 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
7561 f0-f4 for 64 bit. */
7562 if (!cfun->stdarg
7563 || !TARGET_HARD_FLOAT
7564 || !cfun->va_list_fpr_size
7565 || crtl->args.info.fprs >= FP_ARG_NUM_REG)
7566 return;
7567
7568 min_fpr = crtl->args.info.fprs;
7569 max_fpr = min_fpr + cfun->va_list_fpr_size;
7570 if (max_fpr > FP_ARG_NUM_REG)
7571 max_fpr = FP_ARG_NUM_REG;
7572
7573 for (i = min_fpr; i < max_fpr; i++)
7574 cfun_set_fpr_save (i + FPR0_REGNUM);
7575 }
7576
7577 /* Reserve the GPR save slots for GPRs which need to be saved due to
7578 stdarg.
7579 This is a helper routine for s390_register_info. */
7580
7581 static void
7582 s390_register_info_stdarg_gpr ()
7583 {
7584 int i;
7585 int min_gpr;
7586 int max_gpr;
7587
7588 if (!cfun->stdarg
7589 || !cfun->va_list_gpr_size
7590 || crtl->args.info.gprs >= GP_ARG_NUM_REG)
7591 return;
7592
7593 min_gpr = crtl->args.info.gprs;
7594 max_gpr = min_gpr + cfun->va_list_gpr_size;
7595 if (max_gpr > GP_ARG_NUM_REG)
7596 max_gpr = GP_ARG_NUM_REG;
7597
7598 for (i = min_gpr; i < max_gpr; i++)
7599 cfun_gpr_save_slot (2 + i) = -1;
7600 }
7601
7602 /* The GPR and FPR save slots in cfun->machine->frame_layout are set
7603 for registers which need to be saved in function prologue.
7604 This function can be used until the insns emitted for save/restore
7605 of the regs are visible in the RTL stream. */
7606
7607 static void
7608 s390_register_info ()
7609 {
7610 int i, j;
7611 char clobbered_regs[32];
7612
7613 gcc_assert (!epilogue_completed);
7614
7615 if (reload_completed)
7616 /* After reload we rely on our own routine to determine which
7617 registers need saving. */
7618 s390_regs_ever_clobbered (clobbered_regs);
7619 else
7620 /* During reload we use regs_ever_live as a base since reload
7621 does changes in there which we otherwise would not be aware
7622 of. */
7623 for (i = 0; i < 32; i++)
7624 clobbered_regs[i] = df_regs_ever_live_p (i);
7625
7626 for (i = 0; i < 32; i++)
7627 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
7628
7629 /* Mark the call-saved FPRs which need to be saved.
7630 This needs to be done before checking the special GPRs since the
7631 stack pointer usage depends on whether high FPRs have to be saved
7632 or not. */
7633 cfun_frame_layout.fpr_bitmap = 0;
7634 cfun_frame_layout.high_fprs = 0;
7635 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
7636 if (clobbered_regs[i] && !call_really_used_regs[i])
7637 {
7638 cfun_set_fpr_save (i);
7639 if (i >= FPR8_REGNUM)
7640 cfun_frame_layout.high_fprs++;
7641 }
7642
7643 if (flag_pic)
7644 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
7645 |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
7646
7647 clobbered_regs[BASE_REGNUM]
7648 |= (cfun->machine->base_reg
7649 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
7650
7651 clobbered_regs[HARD_FRAME_POINTER_REGNUM]
7652 |= !!frame_pointer_needed;
7653
7654 /* On pre z900 machines this might take until machine dependent
7655 reorg to decide.
7656 save_return_addr_p will only be set on non-zarch machines so
7657 there is no risk that r14 goes into an FPR instead of a stack
7658 slot. */
7659 clobbered_regs[RETURN_REGNUM]
7660 |= (!crtl->is_leaf
7661 || TARGET_TPF_PROFILING
7662 || cfun->machine->split_branches_pending_p
7663 || cfun_frame_layout.save_return_addr_p
7664 || crtl->calls_eh_return);
7665
7666 clobbered_regs[STACK_POINTER_REGNUM]
7667 |= (!crtl->is_leaf
7668 || TARGET_TPF_PROFILING
7669 || cfun_save_high_fprs_p
7670 || get_frame_size () > 0
7671 || (reload_completed && cfun_frame_layout.frame_size > 0)
7672 || cfun->calls_alloca);
7673
7674 memset (cfun_frame_layout.gpr_save_slots, 0, 16);
7675
7676 for (i = 6; i < 16; i++)
7677 if (clobbered_regs[i])
7678 cfun_gpr_save_slot (i) = -1;
7679
7680 s390_register_info_stdarg_fpr ();
7681 s390_register_info_gprtofpr ();
7682
7683 /* First find the range of GPRs to be restored. Vararg regs don't
7684 need to be restored so we do it before assigning slots to the
7685 vararg GPRs. */
7686 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7687 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7688 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7689 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
7690
7691 /* stdarg functions might need to save GPRs 2 to 6. This might
7692 override the GPR->FPR save decision made above for r6 since
7693 vararg regs must go to the stack. */
7694 s390_register_info_stdarg_gpr ();
7695
7696 /* Now the range of GPRs which need saving. */
7697 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7698 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7699 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7700 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
7701 }
7702
7703 /* This function is called by s390_optimize_prologue in order to get
7704 rid of unnecessary GPR save/restore instructions. The register info
7705 for the GPRs is re-computed and the ranges are re-calculated. */
7706
7707 static void
7708 s390_optimize_register_info ()
7709 {
7710 char clobbered_regs[32];
7711 int i, j;
7712
7713 gcc_assert (epilogue_completed);
7714 gcc_assert (!cfun->machine->split_branches_pending_p);
7715
7716 s390_regs_ever_clobbered (clobbered_regs);
7717
7718 for (i = 0; i < 32; i++)
7719 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
7720
7721 /* There is still special treatment needed for cases invisible to
7722 s390_regs_ever_clobbered. */
7723 clobbered_regs[RETURN_REGNUM]
7724 |= (TARGET_TPF_PROFILING
7725 /* When expanding builtin_return_addr in ESA mode we do not
7726 know whether r14 will later be needed as scratch reg when
7727 doing branch splitting. So the builtin always accesses the
7728 r14 save slot and we need to stick to the save/restore
7729 decision for r14 even if it turns out that it didn't get
7730 clobbered. */
7731 || cfun_frame_layout.save_return_addr_p
7732 || crtl->calls_eh_return);
7733
7734 memset (cfun_frame_layout.gpr_save_slots, 0, 6);
7735
7736 for (i = 6; i < 16; i++)
7737 if (!clobbered_regs[i])
7738 cfun_gpr_save_slot (i) = 0;
7739
7740 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7741 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7742 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7743 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
7744
7745 s390_register_info_stdarg_gpr ();
7746
7747 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7748 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7749 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7750 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
7751 }
7752
7753 /* Fill cfun->machine with info about frame of current function. */
7754
7755 static void
7756 s390_frame_info (void)
7757 {
7758 HOST_WIDE_INT lowest_offset;
7759
7760 cfun_frame_layout.first_save_gpr_slot = cfun_frame_layout.first_save_gpr;
7761 cfun_frame_layout.last_save_gpr_slot = cfun_frame_layout.last_save_gpr;
7762
7763 /* The va_arg builtin uses a constant distance of 16 *
7764 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
7765 pointer. So even if we are going to save the stack pointer in an
7766 FPR we need the stack space in order to keep the offsets
7767 correct. */
7768 if (cfun->stdarg && cfun_save_arg_fprs_p)
7769 {
7770 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7771
7772 if (cfun_frame_layout.first_save_gpr_slot == -1)
7773 cfun_frame_layout.first_save_gpr_slot = STACK_POINTER_REGNUM;
7774 }
7775
7776 cfun_frame_layout.frame_size = get_frame_size ();
7777 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
7778 fatal_error ("total size of local variables exceeds architecture limit");
7779
7780 if (!TARGET_PACKED_STACK)
7781 {
7782 /* Fixed stack layout. */
7783 cfun_frame_layout.backchain_offset = 0;
7784 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
7785 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7786 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
7787 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
7788 * UNITS_PER_LONG);
7789 }
7790 else if (TARGET_BACKCHAIN)
7791 {
7792 /* Kernel stack layout - packed stack, backchain, no float */
7793 gcc_assert (TARGET_SOFT_FLOAT);
7794 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
7795 - UNITS_PER_LONG);
7796
7797 /* The distance between the backchain and the return address
7798 save slot must not change. So we always need a slot for the
7799 stack pointer which resides in between. */
7800 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7801
7802 cfun_frame_layout.gprs_offset
7803 = cfun_frame_layout.backchain_offset - cfun_gprs_save_area_size;
7804
7805 /* FPRs will not be saved. Nevertheless pick sane values to
7806 keep area calculations valid. */
7807 cfun_frame_layout.f0_offset =
7808 cfun_frame_layout.f4_offset =
7809 cfun_frame_layout.f8_offset = cfun_frame_layout.gprs_offset;
7810 }
7811 else
7812 {
7813 int num_fprs;
7814
7815 /* Packed stack layout without backchain. */
7816
7817 /* With stdarg FPRs need their dedicated slots. */
7818 num_fprs = (TARGET_64BIT && cfun->stdarg ? 2
7819 : (cfun_fpr_save_p (FPR4_REGNUM) +
7820 cfun_fpr_save_p (FPR6_REGNUM)));
7821 cfun_frame_layout.f4_offset = STACK_POINTER_OFFSET - 8 * num_fprs;
7822
7823 num_fprs = (cfun->stdarg ? 2
7824 : (cfun_fpr_save_p (FPR0_REGNUM)
7825 + cfun_fpr_save_p (FPR2_REGNUM)));
7826 cfun_frame_layout.f0_offset = cfun_frame_layout.f4_offset - 8 * num_fprs;
7827
7828 cfun_frame_layout.gprs_offset
7829 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
7830
7831 cfun_frame_layout.f8_offset = (cfun_frame_layout.gprs_offset
7832 - cfun_frame_layout.high_fprs * 8);
7833 }
7834
7835 if (cfun_save_high_fprs_p)
7836 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7837
7838 if (!crtl->is_leaf)
7839 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7840
7841 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
7842 sized area at the bottom of the stack. This is required also for
7843 leaf functions. When GCC generates a local stack reference it
7844 will always add STACK_POINTER_OFFSET to all these references. */
7845 if (crtl->is_leaf
7846 && !TARGET_TPF_PROFILING
7847 && cfun_frame_layout.frame_size == 0
7848 && !cfun->calls_alloca)
7849 return;
7850
7851 /* Calculate the number of bytes we have used in our own register
7852 save area. With the packed stack layout we can re-use the
7853 remaining bytes for normal stack elements. */
7854
7855 if (TARGET_PACKED_STACK)
7856 lowest_offset = MIN (MIN (cfun_frame_layout.f0_offset,
7857 cfun_frame_layout.f4_offset),
7858 cfun_frame_layout.gprs_offset);
7859 else
7860 lowest_offset = 0;
7861
7862 if (TARGET_BACKCHAIN)
7863 lowest_offset = MIN (lowest_offset, cfun_frame_layout.backchain_offset);
7864
7865 cfun_frame_layout.frame_size += STACK_POINTER_OFFSET - lowest_offset;
7866
7867 /* If under 31 bit an odd number of gprs has to be saved we have to
7868 adjust the frame size to sustain 8 byte alignment of stack
7869 frames. */
7870 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7871 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7872 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
7873 }
7874
7875 /* Generate frame layout. Fills in register and frame data for the current
7876 function in cfun->machine. This routine can be called multiple times;
7877 it will re-do the complete frame layout every time. */
7878
7879 static void
7880 s390_init_frame_layout (void)
7881 {
7882 HOST_WIDE_INT frame_size;
7883 int base_used;
7884
7885 gcc_assert (!reload_completed);
7886
7887 /* On S/390 machines, we may need to perform branch splitting, which
7888 will require both base and return address register. We have no
7889 choice but to assume we're going to need them until right at the
7890 end of the machine dependent reorg phase. */
7891 if (!TARGET_CPU_ZARCH)
7892 cfun->machine->split_branches_pending_p = true;
7893
7894 do
7895 {
7896 frame_size = cfun_frame_layout.frame_size;
7897
7898 /* Try to predict whether we'll need the base register. */
7899 base_used = cfun->machine->split_branches_pending_p
7900 || crtl->uses_const_pool
7901 || (!DISP_IN_RANGE (frame_size)
7902 && !CONST_OK_FOR_K (frame_size));
7903
7904 /* Decide which register to use as literal pool base. In small
7905 leaf functions, try to use an unused call-clobbered register
7906 as base register to avoid save/restore overhead. */
7907 if (!base_used)
7908 cfun->machine->base_reg = NULL_RTX;
7909 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
7910 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7911 else
7912 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
7913
7914 s390_register_info ();
7915 s390_frame_info ();
7916 }
7917 while (frame_size != cfun_frame_layout.frame_size);
7918 }
7919
7920 /* Remove the FPR clobbers from a tbegin insn if it can be proven that
7921 the TX is nonescaping. A transaction is considered escaping if
7922 there is at least one path from tbegin returning CC0 to the
7923 function exit block without an tend.
7924
7925 The check so far has some limitations:
7926 - only single tbegin/tend BBs are supported
7927 - the first cond jump after tbegin must separate the CC0 path from ~CC0
7928 - when CC is copied to a GPR and the CC0 check is done with the GPR
7929 this is not supported
7930 */
7931
7932 static void
7933 s390_optimize_nonescaping_tx (void)
7934 {
7935 const unsigned int CC0 = 1 << 3;
7936 basic_block tbegin_bb = NULL;
7937 basic_block tend_bb = NULL;
7938 basic_block bb;
7939 rtx_insn *insn;
7940 bool result = true;
7941 int bb_index;
7942 rtx_insn *tbegin_insn = NULL;
7943
7944 if (!cfun->machine->tbegin_p)
7945 return;
7946
7947 for (bb_index = 0; bb_index < n_basic_blocks_for_fn (cfun); bb_index++)
7948 {
7949 bb = BASIC_BLOCK_FOR_FN (cfun, bb_index);
7950
7951 if (!bb)
7952 continue;
7953
7954 FOR_BB_INSNS (bb, insn)
7955 {
7956 rtx ite, cc, pat, target;
7957 unsigned HOST_WIDE_INT mask;
7958
7959 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
7960 continue;
7961
7962 pat = PATTERN (insn);
7963
7964 if (GET_CODE (pat) == PARALLEL)
7965 pat = XVECEXP (pat, 0, 0);
7966
7967 if (GET_CODE (pat) != SET
7968 || GET_CODE (SET_SRC (pat)) != UNSPEC_VOLATILE)
7969 continue;
7970
7971 if (XINT (SET_SRC (pat), 1) == UNSPECV_TBEGIN)
7972 {
7973 rtx_insn *tmp;
7974
7975 tbegin_insn = insn;
7976
7977 /* Just return if the tbegin doesn't have clobbers. */
7978 if (GET_CODE (PATTERN (insn)) != PARALLEL)
7979 return;
7980
7981 if (tbegin_bb != NULL)
7982 return;
7983
7984 /* Find the next conditional jump. */
7985 for (tmp = NEXT_INSN (insn);
7986 tmp != NULL_RTX;
7987 tmp = NEXT_INSN (tmp))
7988 {
7989 if (reg_set_p (gen_rtx_REG (CCmode, CC_REGNUM), tmp))
7990 return;
7991 if (!JUMP_P (tmp))
7992 continue;
7993
7994 ite = SET_SRC (PATTERN (tmp));
7995 if (GET_CODE (ite) != IF_THEN_ELSE)
7996 continue;
7997
7998 cc = XEXP (XEXP (ite, 0), 0);
7999 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))
8000 || GET_MODE (cc) != CCRAWmode
8001 || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT)
8002 return;
8003
8004 if (bb->succs->length () != 2)
8005 return;
8006
8007 mask = INTVAL (XEXP (XEXP (ite, 0), 1));
8008 if (GET_CODE (XEXP (ite, 0)) == NE)
8009 mask ^= 0xf;
8010
8011 if (mask == CC0)
8012 target = XEXP (ite, 1);
8013 else if (mask == (CC0 ^ 0xf))
8014 target = XEXP (ite, 2);
8015 else
8016 return;
8017
8018 {
8019 edge_iterator ei;
8020 edge e1, e2;
8021
8022 ei = ei_start (bb->succs);
8023 e1 = ei_safe_edge (ei);
8024 ei_next (&ei);
8025 e2 = ei_safe_edge (ei);
8026
8027 if (e2->flags & EDGE_FALLTHRU)
8028 {
8029 e2 = e1;
8030 e1 = ei_safe_edge (ei);
8031 }
8032
8033 if (!(e1->flags & EDGE_FALLTHRU))
8034 return;
8035
8036 tbegin_bb = (target == pc_rtx) ? e1->dest : e2->dest;
8037 }
8038 if (tmp == BB_END (bb))
8039 break;
8040 }
8041 }
8042
8043 if (XINT (SET_SRC (pat), 1) == UNSPECV_TEND)
8044 {
8045 if (tend_bb != NULL)
8046 return;
8047 tend_bb = bb;
8048 }
8049 }
8050 }
8051
8052 /* Either we successfully remove the FPR clobbers here or we are not
8053 able to do anything for this TX. Both cases don't qualify for
8054 another look. */
8055 cfun->machine->tbegin_p = false;
8056
8057 if (tbegin_bb == NULL || tend_bb == NULL)
8058 return;
8059
8060 calculate_dominance_info (CDI_POST_DOMINATORS);
8061 result = dominated_by_p (CDI_POST_DOMINATORS, tbegin_bb, tend_bb);
8062 free_dominance_info (CDI_POST_DOMINATORS);
8063
8064 if (!result)
8065 return;
8066
8067 PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode,
8068 gen_rtvec (2,
8069 XVECEXP (PATTERN (tbegin_insn), 0, 0),
8070 XVECEXP (PATTERN (tbegin_insn), 0, 1)));
8071 INSN_CODE (tbegin_insn) = -1;
8072 df_insn_rescan (tbegin_insn);
8073
8074 return;
8075 }
8076
8077 /* Return true if it is legal to put a value with MODE into REGNO. */
8078
8079 bool
8080 s390_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
8081 {
8082 switch (REGNO_REG_CLASS (regno))
8083 {
8084 case FP_REGS:
8085 if (REGNO_PAIR_OK (regno, mode))
8086 {
8087 if (mode == SImode || mode == DImode)
8088 return true;
8089
8090 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
8091 return true;
8092 }
8093 break;
8094 case ADDR_REGS:
8095 if (FRAME_REGNO_P (regno) && mode == Pmode)
8096 return true;
8097
8098 /* fallthrough */
8099 case GENERAL_REGS:
8100 if (REGNO_PAIR_OK (regno, mode))
8101 {
8102 if (TARGET_ZARCH
8103 || (mode != TFmode && mode != TCmode && mode != TDmode))
8104 return true;
8105 }
8106 break;
8107 case CC_REGS:
8108 if (GET_MODE_CLASS (mode) == MODE_CC)
8109 return true;
8110 break;
8111 case ACCESS_REGS:
8112 if (REGNO_PAIR_OK (regno, mode))
8113 {
8114 if (mode == SImode || mode == Pmode)
8115 return true;
8116 }
8117 break;
8118 default:
8119 return false;
8120 }
8121
8122 return false;
8123 }
8124
8125 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
8126
8127 bool
8128 s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
8129 {
8130 /* Once we've decided upon a register to use as base register, it must
8131 no longer be used for any other purpose. */
8132 if (cfun->machine->base_reg)
8133 if (REGNO (cfun->machine->base_reg) == old_reg
8134 || REGNO (cfun->machine->base_reg) == new_reg)
8135 return false;
8136
8137 /* Prevent regrename from using call-saved regs which haven't
8138 actually been saved. This is necessary since regrename assumes
8139 the backend save/restore decisions are based on
8140 df_regs_ever_live. Since we have our own routine we have to tell
8141 regrename manually about it. */
8142 if (GENERAL_REGNO_P (new_reg)
8143 && !call_really_used_regs[new_reg]
8144 && cfun_gpr_save_slot (new_reg) == 0)
8145 return false;
8146
8147 return true;
8148 }
8149
8150 /* Return nonzero if register REGNO can be used as a scratch register
8151 in peephole2. */
8152
8153 static bool
8154 s390_hard_regno_scratch_ok (unsigned int regno)
8155 {
8156 /* See s390_hard_regno_rename_ok. */
8157 if (GENERAL_REGNO_P (regno)
8158 && !call_really_used_regs[regno]
8159 && cfun_gpr_save_slot (regno) == 0)
8160 return false;
8161
8162 return true;
8163 }
8164
8165 /* Maximum number of registers to represent a value of mode MODE
8166 in a register of class RCLASS. */
8167
8168 int
8169 s390_class_max_nregs (enum reg_class rclass, machine_mode mode)
8170 {
8171 switch (rclass)
8172 {
8173 case FP_REGS:
8174 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8175 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
8176 else
8177 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
8178 case ACCESS_REGS:
8179 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
8180 default:
8181 break;
8182 }
8183 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8184 }
8185
8186 /* Return true if we use LRA instead of reload pass. */
8187 static bool
8188 s390_lra_p (void)
8189 {
8190 return s390_lra_flag;
8191 }
8192
8193 /* Return true if register FROM can be eliminated via register TO. */
8194
8195 static bool
8196 s390_can_eliminate (const int from, const int to)
8197 {
8198 /* On zSeries machines, we have not marked the base register as fixed.
8199 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
8200 If a function requires the base register, we say here that this
8201 elimination cannot be performed. This will cause reload to free
8202 up the base register (as if it were fixed). On the other hand,
8203 if the current function does *not* require the base register, we
8204 say here the elimination succeeds, which in turn allows reload
8205 to allocate the base register for any other purpose. */
8206 if (from == BASE_REGNUM && to == BASE_REGNUM)
8207 {
8208 if (TARGET_CPU_ZARCH)
8209 {
8210 s390_init_frame_layout ();
8211 return cfun->machine->base_reg == NULL_RTX;
8212 }
8213
8214 return false;
8215 }
8216
8217 /* Everything else must point into the stack frame. */
8218 gcc_assert (to == STACK_POINTER_REGNUM
8219 || to == HARD_FRAME_POINTER_REGNUM);
8220
8221 gcc_assert (from == FRAME_POINTER_REGNUM
8222 || from == ARG_POINTER_REGNUM
8223 || from == RETURN_ADDRESS_POINTER_REGNUM);
8224
8225 /* Make sure we actually saved the return address. */
8226 if (from == RETURN_ADDRESS_POINTER_REGNUM)
8227 if (!crtl->calls_eh_return
8228 && !cfun->stdarg
8229 && !cfun_frame_layout.save_return_addr_p)
8230 return false;
8231
8232 return true;
8233 }
8234
8235 /* Return offset between register FROM and TO initially after prolog. */
8236
8237 HOST_WIDE_INT
8238 s390_initial_elimination_offset (int from, int to)
8239 {
8240 HOST_WIDE_INT offset;
8241
8242 /* ??? Why are we called for non-eliminable pairs? */
8243 if (!s390_can_eliminate (from, to))
8244 return 0;
8245
8246 switch (from)
8247 {
8248 case FRAME_POINTER_REGNUM:
8249 offset = (get_frame_size()
8250 + STACK_POINTER_OFFSET
8251 + crtl->outgoing_args_size);
8252 break;
8253
8254 case ARG_POINTER_REGNUM:
8255 s390_init_frame_layout ();
8256 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
8257 break;
8258
8259 case RETURN_ADDRESS_POINTER_REGNUM:
8260 s390_init_frame_layout ();
8261
8262 if (cfun_frame_layout.first_save_gpr_slot == -1)
8263 {
8264 /* If it turns out that for stdarg nothing went into the reg
8265 save area we also do not need the return address
8266 pointer. */
8267 if (cfun->stdarg && !cfun_save_arg_fprs_p)
8268 return 0;
8269
8270 gcc_unreachable ();
8271 }
8272
8273 /* In order to make the following work it is not necessary for
8274 r14 to have a save slot. It is sufficient if one other GPR
8275 got one. Since the GPRs are always stored without gaps we
8276 are able to calculate where the r14 save slot would
8277 reside. */
8278 offset = (cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset +
8279 (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) *
8280 UNITS_PER_LONG);
8281 break;
8282
8283 case BASE_REGNUM:
8284 offset = 0;
8285 break;
8286
8287 default:
8288 gcc_unreachable ();
8289 }
8290
8291 return offset;
8292 }
8293
8294 /* Emit insn to save fpr REGNUM at offset OFFSET relative
8295 to register BASE. Return generated insn. */
8296
8297 static rtx
8298 save_fpr (rtx base, int offset, int regnum)
8299 {
8300 rtx addr;
8301 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
8302
8303 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
8304 set_mem_alias_set (addr, get_varargs_alias_set ());
8305 else
8306 set_mem_alias_set (addr, get_frame_alias_set ());
8307
8308 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
8309 }
8310
8311 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
8312 to register BASE. Return generated insn. */
8313
8314 static rtx
8315 restore_fpr (rtx base, int offset, int regnum)
8316 {
8317 rtx addr;
8318 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
8319 set_mem_alias_set (addr, get_frame_alias_set ());
8320
8321 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
8322 }
8323
8324 /* Return true if REGNO is a global register, but not one
8325 of the special ones that need to be saved/restored in anyway. */
8326
8327 static inline bool
8328 global_not_special_regno_p (int regno)
8329 {
8330 return (global_regs[regno]
8331 /* These registers are special and need to be
8332 restored in any case. */
8333 && !(regno == STACK_POINTER_REGNUM
8334 || regno == RETURN_REGNUM
8335 || regno == BASE_REGNUM
8336 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
8337 }
8338
8339 /* Generate insn to save registers FIRST to LAST into
8340 the register save area located at offset OFFSET
8341 relative to register BASE. */
8342
8343 static rtx
8344 save_gprs (rtx base, int offset, int first, int last)
8345 {
8346 rtx addr, insn, note;
8347 int i;
8348
8349 addr = plus_constant (Pmode, base, offset);
8350 addr = gen_rtx_MEM (Pmode, addr);
8351
8352 set_mem_alias_set (addr, get_frame_alias_set ());
8353
8354 /* Special-case single register. */
8355 if (first == last)
8356 {
8357 if (TARGET_64BIT)
8358 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
8359 else
8360 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
8361
8362 if (!global_not_special_regno_p (first))
8363 RTX_FRAME_RELATED_P (insn) = 1;
8364 return insn;
8365 }
8366
8367
8368 insn = gen_store_multiple (addr,
8369 gen_rtx_REG (Pmode, first),
8370 GEN_INT (last - first + 1));
8371
8372 if (first <= 6 && cfun->stdarg)
8373 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8374 {
8375 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
8376
8377 if (first + i <= 6)
8378 set_mem_alias_set (mem, get_varargs_alias_set ());
8379 }
8380
8381 /* We need to set the FRAME_RELATED flag on all SETs
8382 inside the store-multiple pattern.
8383
8384 However, we must not emit DWARF records for registers 2..5
8385 if they are stored for use by variable arguments ...
8386
8387 ??? Unfortunately, it is not enough to simply not the
8388 FRAME_RELATED flags for those SETs, because the first SET
8389 of the PARALLEL is always treated as if it had the flag
8390 set, even if it does not. Therefore we emit a new pattern
8391 without those registers as REG_FRAME_RELATED_EXPR note. */
8392
8393 if (first >= 6 && !global_not_special_regno_p (first))
8394 {
8395 rtx pat = PATTERN (insn);
8396
8397 for (i = 0; i < XVECLEN (pat, 0); i++)
8398 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8399 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
8400 0, i)))))
8401 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
8402
8403 RTX_FRAME_RELATED_P (insn) = 1;
8404 }
8405 else if (last >= 6)
8406 {
8407 int start;
8408
8409 for (start = first >= 6 ? first : 6; start <= last; start++)
8410 if (!global_not_special_regno_p (start))
8411 break;
8412
8413 if (start > last)
8414 return insn;
8415
8416 addr = plus_constant (Pmode, base,
8417 offset + (start - first) * UNITS_PER_LONG);
8418
8419 if (start == last)
8420 {
8421 if (TARGET_64BIT)
8422 note = gen_movdi (gen_rtx_MEM (Pmode, addr),
8423 gen_rtx_REG (Pmode, start));
8424 else
8425 note = gen_movsi (gen_rtx_MEM (Pmode, addr),
8426 gen_rtx_REG (Pmode, start));
8427 note = PATTERN (note);
8428
8429 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8430 RTX_FRAME_RELATED_P (insn) = 1;
8431
8432 return insn;
8433 }
8434
8435 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
8436 gen_rtx_REG (Pmode, start),
8437 GEN_INT (last - start + 1));
8438 note = PATTERN (note);
8439
8440 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8441
8442 for (i = 0; i < XVECLEN (note, 0); i++)
8443 if (GET_CODE (XVECEXP (note, 0, i)) == SET
8444 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
8445 0, i)))))
8446 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
8447
8448 RTX_FRAME_RELATED_P (insn) = 1;
8449 }
8450
8451 return insn;
8452 }
8453
8454 /* Generate insn to restore registers FIRST to LAST from
8455 the register save area located at offset OFFSET
8456 relative to register BASE. */
8457
8458 static rtx
8459 restore_gprs (rtx base, int offset, int first, int last)
8460 {
8461 rtx addr, insn;
8462
8463 addr = plus_constant (Pmode, base, offset);
8464 addr = gen_rtx_MEM (Pmode, addr);
8465 set_mem_alias_set (addr, get_frame_alias_set ());
8466
8467 /* Special-case single register. */
8468 if (first == last)
8469 {
8470 if (TARGET_64BIT)
8471 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8472 else
8473 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8474
8475 RTX_FRAME_RELATED_P (insn) = 1;
8476 return insn;
8477 }
8478
8479 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8480 addr,
8481 GEN_INT (last - first + 1));
8482 RTX_FRAME_RELATED_P (insn) = 1;
8483 return insn;
8484 }
8485
8486 /* Return insn sequence to load the GOT register. */
8487
8488 static GTY(()) rtx got_symbol;
8489 rtx_insn *
8490 s390_load_got (void)
8491 {
8492 rtx_insn *insns;
8493
8494 /* We cannot use pic_offset_table_rtx here since we use this
8495 function also for non-pic if __tls_get_offset is called and in
8496 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8497 aren't usable. */
8498 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8499
8500 if (!got_symbol)
8501 {
8502 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8503 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8504 }
8505
8506 start_sequence ();
8507
8508 if (TARGET_CPU_ZARCH)
8509 {
8510 emit_move_insn (got_rtx, got_symbol);
8511 }
8512 else
8513 {
8514 rtx offset;
8515
8516 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
8517 UNSPEC_LTREL_OFFSET);
8518 offset = gen_rtx_CONST (Pmode, offset);
8519 offset = force_const_mem (Pmode, offset);
8520
8521 emit_move_insn (got_rtx, offset);
8522
8523 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
8524 UNSPEC_LTREL_BASE);
8525 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
8526
8527 emit_move_insn (got_rtx, offset);
8528 }
8529
8530 insns = get_insns ();
8531 end_sequence ();
8532 return insns;
8533 }
8534
8535 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
8536 and the change to the stack pointer. */
8537
8538 static void
8539 s390_emit_stack_tie (void)
8540 {
8541 rtx mem = gen_frame_mem (BLKmode,
8542 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8543
8544 emit_insn (gen_stack_tie (mem));
8545 }
8546
8547 /* Copy GPRS into FPR save slots. */
8548
8549 static void
8550 s390_save_gprs_to_fprs (void)
8551 {
8552 int i;
8553
8554 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8555 return;
8556
8557 for (i = 6; i < 16; i++)
8558 {
8559 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8560 {
8561 rtx_insn *insn =
8562 emit_move_insn (gen_rtx_REG (DImode, cfun_gpr_save_slot (i)),
8563 gen_rtx_REG (DImode, i));
8564 RTX_FRAME_RELATED_P (insn) = 1;
8565 }
8566 }
8567 }
8568
8569 /* Restore GPRs from FPR save slots. */
8570
8571 static void
8572 s390_restore_gprs_from_fprs (void)
8573 {
8574 int i;
8575
8576 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8577 return;
8578
8579 for (i = 6; i < 16; i++)
8580 {
8581 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8582 {
8583 rtx_insn *insn =
8584 emit_move_insn (gen_rtx_REG (DImode, i),
8585 gen_rtx_REG (DImode, cfun_gpr_save_slot (i)));
8586 df_set_regs_ever_live (i, true);
8587 add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, i));
8588 if (i == STACK_POINTER_REGNUM)
8589 add_reg_note (insn, REG_CFA_DEF_CFA,
8590 plus_constant (Pmode, stack_pointer_rtx,
8591 STACK_POINTER_OFFSET));
8592 RTX_FRAME_RELATED_P (insn) = 1;
8593 }
8594 }
8595 }
8596
8597
8598 /* A pass run immediately before shrink-wrapping and prologue and epilogue
8599 generation. */
8600
8601 namespace {
8602
8603 const pass_data pass_data_s390_early_mach =
8604 {
8605 RTL_PASS, /* type */
8606 "early_mach", /* name */
8607 OPTGROUP_NONE, /* optinfo_flags */
8608 TV_MACH_DEP, /* tv_id */
8609 0, /* properties_required */
8610 0, /* properties_provided */
8611 0, /* properties_destroyed */
8612 0, /* todo_flags_start */
8613 ( TODO_df_verify | TODO_df_finish ), /* todo_flags_finish */
8614 };
8615
8616 class pass_s390_early_mach : public rtl_opt_pass
8617 {
8618 public:
8619 pass_s390_early_mach (gcc::context *ctxt)
8620 : rtl_opt_pass (pass_data_s390_early_mach, ctxt)
8621 {}
8622
8623 /* opt_pass methods: */
8624 virtual unsigned int execute (function *);
8625
8626 }; // class pass_s390_early_mach
8627
8628 unsigned int
8629 pass_s390_early_mach::execute (function *fun)
8630 {
8631 rtx_insn *insn;
8632
8633 /* Try to get rid of the FPR clobbers. */
8634 s390_optimize_nonescaping_tx ();
8635
8636 /* Re-compute register info. */
8637 s390_register_info ();
8638
8639 /* If we're using a base register, ensure that it is always valid for
8640 the first non-prologue instruction. */
8641 if (fun->machine->base_reg)
8642 emit_insn_at_entry (gen_main_pool (fun->machine->base_reg));
8643
8644 /* Annotate all constant pool references to let the scheduler know
8645 they implicitly use the base register. */
8646 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8647 if (INSN_P (insn))
8648 {
8649 annotate_constant_pool_refs (&PATTERN (insn));
8650 df_insn_rescan (insn);
8651 }
8652 return 0;
8653 }
8654
8655 } // anon namespace
8656
8657 /* Expand the prologue into a bunch of separate insns. */
8658
8659 void
8660 s390_emit_prologue (void)
8661 {
8662 rtx insn, addr;
8663 rtx temp_reg;
8664 int i;
8665 int offset;
8666 int next_fpr = 0;
8667
8668 /* Choose best register to use for temp use within prologue.
8669 See below for why TPF must use the register 1. */
8670
8671 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
8672 && !crtl->is_leaf
8673 && !TARGET_TPF_PROFILING)
8674 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8675 else
8676 temp_reg = gen_rtx_REG (Pmode, 1);
8677
8678 s390_save_gprs_to_fprs ();
8679
8680 /* Save call saved gprs. */
8681 if (cfun_frame_layout.first_save_gpr != -1)
8682 {
8683 insn = save_gprs (stack_pointer_rtx,
8684 cfun_frame_layout.gprs_offset +
8685 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
8686 - cfun_frame_layout.first_save_gpr_slot),
8687 cfun_frame_layout.first_save_gpr,
8688 cfun_frame_layout.last_save_gpr);
8689 emit_insn (insn);
8690 }
8691
8692 /* Dummy insn to mark literal pool slot. */
8693
8694 if (cfun->machine->base_reg)
8695 emit_insn (gen_main_pool (cfun->machine->base_reg));
8696
8697 offset = cfun_frame_layout.f0_offset;
8698
8699 /* Save f0 and f2. */
8700 for (i = FPR0_REGNUM; i <= FPR0_REGNUM + 1; i++)
8701 {
8702 if (cfun_fpr_save_p (i))
8703 {
8704 save_fpr (stack_pointer_rtx, offset, i);
8705 offset += 8;
8706 }
8707 else if (!TARGET_PACKED_STACK || cfun->stdarg)
8708 offset += 8;
8709 }
8710
8711 /* Save f4 and f6. */
8712 offset = cfun_frame_layout.f4_offset;
8713 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
8714 {
8715 if (cfun_fpr_save_p (i))
8716 {
8717 insn = save_fpr (stack_pointer_rtx, offset, i);
8718 offset += 8;
8719
8720 /* If f4 and f6 are call clobbered they are saved due to
8721 stdargs and therefore are not frame related. */
8722 if (!call_really_used_regs[i])
8723 RTX_FRAME_RELATED_P (insn) = 1;
8724 }
8725 else if (!TARGET_PACKED_STACK || call_really_used_regs[i])
8726 offset += 8;
8727 }
8728
8729 if (TARGET_PACKED_STACK
8730 && cfun_save_high_fprs_p
8731 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8732 {
8733 offset = (cfun_frame_layout.f8_offset
8734 + (cfun_frame_layout.high_fprs - 1) * 8);
8735
8736 for (i = FPR15_REGNUM; i >= FPR8_REGNUM && offset >= 0; i--)
8737 if (cfun_fpr_save_p (i))
8738 {
8739 insn = save_fpr (stack_pointer_rtx, offset, i);
8740
8741 RTX_FRAME_RELATED_P (insn) = 1;
8742 offset -= 8;
8743 }
8744 if (offset >= cfun_frame_layout.f8_offset)
8745 next_fpr = i;
8746 }
8747
8748 if (!TARGET_PACKED_STACK)
8749 next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : 0;
8750
8751 if (flag_stack_usage_info)
8752 current_function_static_stack_size = cfun_frame_layout.frame_size;
8753
8754 /* Decrement stack pointer. */
8755
8756 if (cfun_frame_layout.frame_size > 0)
8757 {
8758 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8759 rtx real_frame_off;
8760
8761 if (s390_stack_size)
8762 {
8763 HOST_WIDE_INT stack_guard;
8764
8765 if (s390_stack_guard)
8766 stack_guard = s390_stack_guard;
8767 else
8768 {
8769 /* If no value for stack guard is provided the smallest power of 2
8770 larger than the current frame size is chosen. */
8771 stack_guard = 1;
8772 while (stack_guard < cfun_frame_layout.frame_size)
8773 stack_guard <<= 1;
8774 }
8775
8776 if (cfun_frame_layout.frame_size >= s390_stack_size)
8777 {
8778 warning (0, "frame size of function %qs is %wd"
8779 " bytes exceeding user provided stack limit of "
8780 "%d bytes. "
8781 "An unconditional trap is added.",
8782 current_function_name(), cfun_frame_layout.frame_size,
8783 s390_stack_size);
8784 emit_insn (gen_trap ());
8785 }
8786 else
8787 {
8788 /* stack_guard has to be smaller than s390_stack_size.
8789 Otherwise we would emit an AND with zero which would
8790 not match the test under mask pattern. */
8791 if (stack_guard >= s390_stack_size)
8792 {
8793 warning (0, "frame size of function %qs is %wd"
8794 " bytes which is more than half the stack size. "
8795 "The dynamic check would not be reliable. "
8796 "No check emitted for this function.",
8797 current_function_name(),
8798 cfun_frame_layout.frame_size);
8799 }
8800 else
8801 {
8802 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8803 & ~(stack_guard - 1));
8804
8805 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8806 GEN_INT (stack_check_mask));
8807 if (TARGET_64BIT)
8808 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8809 t, const0_rtx),
8810 t, const0_rtx, const0_rtx));
8811 else
8812 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8813 t, const0_rtx),
8814 t, const0_rtx, const0_rtx));
8815 }
8816 }
8817 }
8818
8819 if (s390_warn_framesize > 0
8820 && cfun_frame_layout.frame_size >= s390_warn_framesize)
8821 warning (0, "frame size of %qs is %wd bytes",
8822 current_function_name (), cfun_frame_layout.frame_size);
8823
8824 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
8825 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
8826
8827 /* Save incoming stack pointer into temp reg. */
8828 if (TARGET_BACKCHAIN || next_fpr)
8829 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
8830
8831 /* Subtract frame size from stack pointer. */
8832
8833 if (DISP_IN_RANGE (INTVAL (frame_off)))
8834 {
8835 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8836 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8837 frame_off));
8838 insn = emit_insn (insn);
8839 }
8840 else
8841 {
8842 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
8843 frame_off = force_const_mem (Pmode, frame_off);
8844
8845 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
8846 annotate_constant_pool_refs (&PATTERN (insn));
8847 }
8848
8849 RTX_FRAME_RELATED_P (insn) = 1;
8850 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8851 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8852 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8853 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8854 real_frame_off)));
8855
8856 /* Set backchain. */
8857
8858 if (TARGET_BACKCHAIN)
8859 {
8860 if (cfun_frame_layout.backchain_offset)
8861 addr = gen_rtx_MEM (Pmode,
8862 plus_constant (Pmode, stack_pointer_rtx,
8863 cfun_frame_layout.backchain_offset));
8864 else
8865 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8866 set_mem_alias_set (addr, get_frame_alias_set ());
8867 insn = emit_insn (gen_move_insn (addr, temp_reg));
8868 }
8869
8870 /* If we support non-call exceptions (e.g. for Java),
8871 we need to make sure the backchain pointer is set up
8872 before any possibly trapping memory access. */
8873 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
8874 {
8875 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
8876 emit_clobber (addr);
8877 }
8878 }
8879
8880 /* Save fprs 8 - 15 (64 bit ABI). */
8881
8882 if (cfun_save_high_fprs_p && next_fpr)
8883 {
8884 /* If the stack might be accessed through a different register
8885 we have to make sure that the stack pointer decrement is not
8886 moved below the use of the stack slots. */
8887 s390_emit_stack_tie ();
8888
8889 insn = emit_insn (gen_add2_insn (temp_reg,
8890 GEN_INT (cfun_frame_layout.f8_offset)));
8891
8892 offset = 0;
8893
8894 for (i = FPR8_REGNUM; i <= next_fpr; i++)
8895 if (cfun_fpr_save_p (i))
8896 {
8897 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
8898 cfun_frame_layout.frame_size
8899 + cfun_frame_layout.f8_offset
8900 + offset);
8901
8902 insn = save_fpr (temp_reg, offset, i);
8903 offset += 8;
8904 RTX_FRAME_RELATED_P (insn) = 1;
8905 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8906 gen_rtx_SET (VOIDmode,
8907 gen_rtx_MEM (DFmode, addr),
8908 gen_rtx_REG (DFmode, i)));
8909 }
8910 }
8911
8912 /* Set frame pointer, if needed. */
8913
8914 if (frame_pointer_needed)
8915 {
8916 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8917 RTX_FRAME_RELATED_P (insn) = 1;
8918 }
8919
8920 /* Set up got pointer, if needed. */
8921
8922 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
8923 {
8924 rtx_insn *insns = s390_load_got ();
8925
8926 for (rtx_insn *insn = insns; insn; insn = NEXT_INSN (insn))
8927 annotate_constant_pool_refs (&PATTERN (insn));
8928
8929 emit_insn (insns);
8930 }
8931
8932 if (TARGET_TPF_PROFILING)
8933 {
8934 /* Generate a BAS instruction to serve as a function
8935 entry intercept to facilitate the use of tracing
8936 algorithms located at the branch target. */
8937 emit_insn (gen_prologue_tpf ());
8938
8939 /* Emit a blockage here so that all code
8940 lies between the profiling mechanisms. */
8941 emit_insn (gen_blockage ());
8942 }
8943 }
8944
8945 /* Expand the epilogue into a bunch of separate insns. */
8946
8947 void
8948 s390_emit_epilogue (bool sibcall)
8949 {
8950 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
8951 int area_bottom, area_top, offset = 0;
8952 int next_offset;
8953 rtvec p;
8954 int i;
8955
8956 if (TARGET_TPF_PROFILING)
8957 {
8958
8959 /* Generate a BAS instruction to serve as a function
8960 entry intercept to facilitate the use of tracing
8961 algorithms located at the branch target. */
8962
8963 /* Emit a blockage here so that all code
8964 lies between the profiling mechanisms. */
8965 emit_insn (gen_blockage ());
8966
8967 emit_insn (gen_epilogue_tpf ());
8968 }
8969
8970 /* Check whether to use frame or stack pointer for restore. */
8971
8972 frame_pointer = (frame_pointer_needed
8973 ? hard_frame_pointer_rtx : stack_pointer_rtx);
8974
8975 s390_frame_area (&area_bottom, &area_top);
8976
8977 /* Check whether we can access the register save area.
8978 If not, increment the frame pointer as required. */
8979
8980 if (area_top <= area_bottom)
8981 {
8982 /* Nothing to restore. */
8983 }
8984 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8985 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8986 {
8987 /* Area is in range. */
8988 offset = cfun_frame_layout.frame_size;
8989 }
8990 else
8991 {
8992 rtx insn, frame_off, cfa;
8993
8994 offset = area_bottom < 0 ? -area_bottom : 0;
8995 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
8996
8997 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8998 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8999 if (DISP_IN_RANGE (INTVAL (frame_off)))
9000 {
9001 insn = gen_rtx_SET (VOIDmode, frame_pointer,
9002 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
9003 insn = emit_insn (insn);
9004 }
9005 else
9006 {
9007 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
9008 frame_off = force_const_mem (Pmode, frame_off);
9009
9010 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
9011 annotate_constant_pool_refs (&PATTERN (insn));
9012 }
9013 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
9014 RTX_FRAME_RELATED_P (insn) = 1;
9015 }
9016
9017 /* Restore call saved fprs. */
9018
9019 if (TARGET_64BIT)
9020 {
9021 if (cfun_save_high_fprs_p)
9022 {
9023 next_offset = cfun_frame_layout.f8_offset;
9024 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
9025 {
9026 if (cfun_fpr_save_p (i))
9027 {
9028 restore_fpr (frame_pointer,
9029 offset + next_offset, i);
9030 cfa_restores
9031 = alloc_reg_note (REG_CFA_RESTORE,
9032 gen_rtx_REG (DFmode, i), cfa_restores);
9033 next_offset += 8;
9034 }
9035 }
9036 }
9037
9038 }
9039 else
9040 {
9041 next_offset = cfun_frame_layout.f4_offset;
9042 /* f4, f6 */
9043 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
9044 {
9045 if (cfun_fpr_save_p (i))
9046 {
9047 restore_fpr (frame_pointer,
9048 offset + next_offset, i);
9049 cfa_restores
9050 = alloc_reg_note (REG_CFA_RESTORE,
9051 gen_rtx_REG (DFmode, i), cfa_restores);
9052 next_offset += 8;
9053 }
9054 else if (!TARGET_PACKED_STACK)
9055 next_offset += 8;
9056 }
9057
9058 }
9059
9060 /* Return register. */
9061
9062 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
9063
9064 /* Restore call saved gprs. */
9065
9066 if (cfun_frame_layout.first_restore_gpr != -1)
9067 {
9068 rtx insn, addr;
9069 int i;
9070
9071 /* Check for global register and save them
9072 to stack location from where they get restored. */
9073
9074 for (i = cfun_frame_layout.first_restore_gpr;
9075 i <= cfun_frame_layout.last_restore_gpr;
9076 i++)
9077 {
9078 if (global_not_special_regno_p (i))
9079 {
9080 addr = plus_constant (Pmode, frame_pointer,
9081 offset + cfun_frame_layout.gprs_offset
9082 + (i - cfun_frame_layout.first_save_gpr_slot)
9083 * UNITS_PER_LONG);
9084 addr = gen_rtx_MEM (Pmode, addr);
9085 set_mem_alias_set (addr, get_frame_alias_set ());
9086 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
9087 }
9088 else
9089 cfa_restores
9090 = alloc_reg_note (REG_CFA_RESTORE,
9091 gen_rtx_REG (Pmode, i), cfa_restores);
9092 }
9093
9094 if (! sibcall)
9095 {
9096 /* Fetch return address from stack before load multiple,
9097 this will do good for scheduling.
9098
9099 Only do this if we already decided that r14 needs to be
9100 saved to a stack slot. (And not just because r14 happens to
9101 be in between two GPRs which need saving.) Otherwise it
9102 would be difficult to take that decision back in
9103 s390_optimize_prologue. */
9104 if (cfun_gpr_save_slot (RETURN_REGNUM) == -1)
9105 {
9106 int return_regnum = find_unused_clobbered_reg();
9107 if (!return_regnum)
9108 return_regnum = 4;
9109 return_reg = gen_rtx_REG (Pmode, return_regnum);
9110
9111 addr = plus_constant (Pmode, frame_pointer,
9112 offset + cfun_frame_layout.gprs_offset
9113 + (RETURN_REGNUM
9114 - cfun_frame_layout.first_save_gpr_slot)
9115 * UNITS_PER_LONG);
9116 addr = gen_rtx_MEM (Pmode, addr);
9117 set_mem_alias_set (addr, get_frame_alias_set ());
9118 emit_move_insn (return_reg, addr);
9119
9120 /* Once we did that optimization we have to make sure
9121 s390_optimize_prologue does not try to remove the
9122 store of r14 since we will not be able to find the
9123 load issued here. */
9124 cfun_frame_layout.save_return_addr_p = true;
9125 }
9126 }
9127
9128 insn = restore_gprs (frame_pointer,
9129 offset + cfun_frame_layout.gprs_offset
9130 + (cfun_frame_layout.first_restore_gpr
9131 - cfun_frame_layout.first_save_gpr_slot)
9132 * UNITS_PER_LONG,
9133 cfun_frame_layout.first_restore_gpr,
9134 cfun_frame_layout.last_restore_gpr);
9135 insn = emit_insn (insn);
9136 REG_NOTES (insn) = cfa_restores;
9137 add_reg_note (insn, REG_CFA_DEF_CFA,
9138 plus_constant (Pmode, stack_pointer_rtx,
9139 STACK_POINTER_OFFSET));
9140 RTX_FRAME_RELATED_P (insn) = 1;
9141 }
9142
9143 s390_restore_gprs_from_fprs ();
9144
9145 if (! sibcall)
9146 {
9147
9148 /* Return to caller. */
9149
9150 p = rtvec_alloc (2);
9151
9152 RTVEC_ELT (p, 0) = ret_rtx;
9153 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
9154 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
9155 }
9156 }
9157
9158 /* Implement TARGET_SET_UP_BY_PROLOGUE. */
9159
9160 static void
9161 s300_set_up_by_prologue (hard_reg_set_container *regs)
9162 {
9163 if (cfun->machine->base_reg
9164 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9165 SET_HARD_REG_BIT (regs->set, REGNO (cfun->machine->base_reg));
9166 }
9167
9168 /* Return true if the function can use simple_return to return outside
9169 of a shrink-wrapped region. At present shrink-wrapping is supported
9170 in all cases. */
9171
9172 bool
9173 s390_can_use_simple_return_insn (void)
9174 {
9175 return true;
9176 }
9177
9178 /* Return true if the epilogue is guaranteed to contain only a return
9179 instruction and if a direct return can therefore be used instead.
9180 One of the main advantages of using direct return instructions
9181 is that we can then use conditional returns. */
9182
9183 bool
9184 s390_can_use_return_insn (void)
9185 {
9186 int i;
9187
9188 if (!reload_completed)
9189 return false;
9190
9191 if (crtl->profile)
9192 return false;
9193
9194 if (TARGET_TPF_PROFILING)
9195 return false;
9196
9197 for (i = 0; i < 16; i++)
9198 if (cfun_gpr_save_slot (i))
9199 return false;
9200
9201 /* For 31 bit this is not covered by the frame_size check below
9202 since f4, f6 are saved in the register save area without needing
9203 additional stack space. */
9204 if (!TARGET_64BIT
9205 && (cfun_fpr_save_p (FPR4_REGNUM) || cfun_fpr_save_p (FPR6_REGNUM)))
9206 return false;
9207
9208 if (cfun->machine->base_reg
9209 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9210 return false;
9211
9212 return cfun_frame_layout.frame_size == 0;
9213 }
9214
9215 /* Return the size in bytes of a function argument of
9216 type TYPE and/or mode MODE. At least one of TYPE or
9217 MODE must be specified. */
9218
9219 static int
9220 s390_function_arg_size (machine_mode mode, const_tree type)
9221 {
9222 if (type)
9223 return int_size_in_bytes (type);
9224
9225 /* No type info available for some library calls ... */
9226 if (mode != BLKmode)
9227 return GET_MODE_SIZE (mode);
9228
9229 /* If we have neither type nor mode, abort */
9230 gcc_unreachable ();
9231 }
9232
9233 /* Return true if a function argument of type TYPE and mode MODE
9234 is to be passed in a floating-point register, if available. */
9235
9236 static bool
9237 s390_function_arg_float (machine_mode mode, const_tree type)
9238 {
9239 int size = s390_function_arg_size (mode, type);
9240 if (size > 8)
9241 return false;
9242
9243 /* Soft-float changes the ABI: no floating-point registers are used. */
9244 if (TARGET_SOFT_FLOAT)
9245 return false;
9246
9247 /* No type info available for some library calls ... */
9248 if (!type)
9249 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
9250
9251 /* The ABI says that record types with a single member are treated
9252 just like that member would be. */
9253 while (TREE_CODE (type) == RECORD_TYPE)
9254 {
9255 tree field, single = NULL_TREE;
9256
9257 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
9258 {
9259 if (TREE_CODE (field) != FIELD_DECL)
9260 continue;
9261
9262 if (single == NULL_TREE)
9263 single = TREE_TYPE (field);
9264 else
9265 return false;
9266 }
9267
9268 if (single == NULL_TREE)
9269 return false;
9270 else
9271 type = single;
9272 }
9273
9274 return TREE_CODE (type) == REAL_TYPE;
9275 }
9276
9277 /* Return true if a function argument of type TYPE and mode MODE
9278 is to be passed in an integer register, or a pair of integer
9279 registers, if available. */
9280
9281 static bool
9282 s390_function_arg_integer (machine_mode mode, const_tree type)
9283 {
9284 int size = s390_function_arg_size (mode, type);
9285 if (size > 8)
9286 return false;
9287
9288 /* No type info available for some library calls ... */
9289 if (!type)
9290 return GET_MODE_CLASS (mode) == MODE_INT
9291 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
9292
9293 /* We accept small integral (and similar) types. */
9294 if (INTEGRAL_TYPE_P (type)
9295 || POINTER_TYPE_P (type)
9296 || TREE_CODE (type) == NULLPTR_TYPE
9297 || TREE_CODE (type) == OFFSET_TYPE
9298 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
9299 return true;
9300
9301 /* We also accept structs of size 1, 2, 4, 8 that are not
9302 passed in floating-point registers. */
9303 if (AGGREGATE_TYPE_P (type)
9304 && exact_log2 (size) >= 0
9305 && !s390_function_arg_float (mode, type))
9306 return true;
9307
9308 return false;
9309 }
9310
9311 /* Return 1 if a function argument of type TYPE and mode MODE
9312 is to be passed by reference. The ABI specifies that only
9313 structures of size 1, 2, 4, or 8 bytes are passed by value,
9314 all other structures (and complex numbers) are passed by
9315 reference. */
9316
9317 static bool
9318 s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
9319 machine_mode mode, const_tree type,
9320 bool named ATTRIBUTE_UNUSED)
9321 {
9322 int size = s390_function_arg_size (mode, type);
9323 if (size > 8)
9324 return true;
9325
9326 if (type)
9327 {
9328 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
9329 return 1;
9330
9331 if (TREE_CODE (type) == COMPLEX_TYPE
9332 || TREE_CODE (type) == VECTOR_TYPE)
9333 return 1;
9334 }
9335
9336 return 0;
9337 }
9338
9339 /* Update the data in CUM to advance over an argument of mode MODE and
9340 data type TYPE. (TYPE is null for libcalls where that information
9341 may not be available.). The boolean NAMED specifies whether the
9342 argument is a named argument (as opposed to an unnamed argument
9343 matching an ellipsis). */
9344
9345 static void
9346 s390_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
9347 const_tree type, bool named ATTRIBUTE_UNUSED)
9348 {
9349 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9350
9351 if (s390_function_arg_float (mode, type))
9352 {
9353 cum->fprs += 1;
9354 }
9355 else if (s390_function_arg_integer (mode, type))
9356 {
9357 int size = s390_function_arg_size (mode, type);
9358 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
9359 }
9360 else
9361 gcc_unreachable ();
9362 }
9363
9364 /* Define where to put the arguments to a function.
9365 Value is zero to push the argument on the stack,
9366 or a hard register in which to store the argument.
9367
9368 MODE is the argument's machine mode.
9369 TYPE is the data type of the argument (as a tree).
9370 This is null for libcalls where that information may
9371 not be available.
9372 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9373 the preceding args and about the function being called.
9374 NAMED is nonzero if this argument is a named parameter
9375 (otherwise it is an extra parameter matching an ellipsis).
9376
9377 On S/390, we use general purpose registers 2 through 6 to
9378 pass integer, pointer, and certain structure arguments, and
9379 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
9380 to pass floating point arguments. All remaining arguments
9381 are pushed to the stack. */
9382
9383 static rtx
9384 s390_function_arg (cumulative_args_t cum_v, machine_mode mode,
9385 const_tree type, bool named ATTRIBUTE_UNUSED)
9386 {
9387 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9388
9389 if (s390_function_arg_float (mode, type))
9390 {
9391 if (cum->fprs + 1 > FP_ARG_NUM_REG)
9392 return 0;
9393 else
9394 return gen_rtx_REG (mode, cum->fprs + 16);
9395 }
9396 else if (s390_function_arg_integer (mode, type))
9397 {
9398 int size = s390_function_arg_size (mode, type);
9399 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9400
9401 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
9402 return 0;
9403 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
9404 return gen_rtx_REG (mode, cum->gprs + 2);
9405 else if (n_gprs == 2)
9406 {
9407 rtvec p = rtvec_alloc (2);
9408
9409 RTVEC_ELT (p, 0)
9410 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
9411 const0_rtx);
9412 RTVEC_ELT (p, 1)
9413 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
9414 GEN_INT (4));
9415
9416 return gen_rtx_PARALLEL (mode, p);
9417 }
9418 }
9419
9420 /* After the real arguments, expand_call calls us once again
9421 with a void_type_node type. Whatever we return here is
9422 passed as operand 2 to the call expanders.
9423
9424 We don't need this feature ... */
9425 else if (type == void_type_node)
9426 return const0_rtx;
9427
9428 gcc_unreachable ();
9429 }
9430
9431 /* Return true if return values of type TYPE should be returned
9432 in a memory buffer whose address is passed by the caller as
9433 hidden first argument. */
9434
9435 static bool
9436 s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
9437 {
9438 /* We accept small integral (and similar) types. */
9439 if (INTEGRAL_TYPE_P (type)
9440 || POINTER_TYPE_P (type)
9441 || TREE_CODE (type) == OFFSET_TYPE
9442 || TREE_CODE (type) == REAL_TYPE)
9443 return int_size_in_bytes (type) > 8;
9444
9445 /* Aggregates and similar constructs are always returned
9446 in memory. */
9447 if (AGGREGATE_TYPE_P (type)
9448 || TREE_CODE (type) == COMPLEX_TYPE
9449 || TREE_CODE (type) == VECTOR_TYPE)
9450 return true;
9451
9452 /* ??? We get called on all sorts of random stuff from
9453 aggregate_value_p. We can't abort, but it's not clear
9454 what's safe to return. Pretend it's a struct I guess. */
9455 return true;
9456 }
9457
9458 /* Function arguments and return values are promoted to word size. */
9459
9460 static machine_mode
9461 s390_promote_function_mode (const_tree type, machine_mode mode,
9462 int *punsignedp,
9463 const_tree fntype ATTRIBUTE_UNUSED,
9464 int for_return ATTRIBUTE_UNUSED)
9465 {
9466 if (INTEGRAL_MODE_P (mode)
9467 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
9468 {
9469 if (type != NULL_TREE && POINTER_TYPE_P (type))
9470 *punsignedp = POINTERS_EXTEND_UNSIGNED;
9471 return Pmode;
9472 }
9473
9474 return mode;
9475 }
9476
9477 /* Define where to return a (scalar) value of type RET_TYPE.
9478 If RET_TYPE is null, define where to return a (scalar)
9479 value of mode MODE from a libcall. */
9480
9481 static rtx
9482 s390_function_and_libcall_value (machine_mode mode,
9483 const_tree ret_type,
9484 const_tree fntype_or_decl,
9485 bool outgoing ATTRIBUTE_UNUSED)
9486 {
9487 /* For normal functions perform the promotion as
9488 promote_function_mode would do. */
9489 if (ret_type)
9490 {
9491 int unsignedp = TYPE_UNSIGNED (ret_type);
9492 mode = promote_function_mode (ret_type, mode, &unsignedp,
9493 fntype_or_decl, 1);
9494 }
9495
9496 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
9497 gcc_assert (GET_MODE_SIZE (mode) <= 8);
9498
9499 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
9500 return gen_rtx_REG (mode, 16);
9501 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
9502 || UNITS_PER_LONG == UNITS_PER_WORD)
9503 return gen_rtx_REG (mode, 2);
9504 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
9505 {
9506 /* This case is triggered when returning a 64 bit value with
9507 -m31 -mzarch. Although the value would fit into a single
9508 register it has to be forced into a 32 bit register pair in
9509 order to match the ABI. */
9510 rtvec p = rtvec_alloc (2);
9511
9512 RTVEC_ELT (p, 0)
9513 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
9514 RTVEC_ELT (p, 1)
9515 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
9516
9517 return gen_rtx_PARALLEL (mode, p);
9518 }
9519
9520 gcc_unreachable ();
9521 }
9522
9523 /* Define where to return a scalar return value of type RET_TYPE. */
9524
9525 static rtx
9526 s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
9527 bool outgoing)
9528 {
9529 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
9530 fn_decl_or_type, outgoing);
9531 }
9532
9533 /* Define where to return a scalar libcall return value of mode
9534 MODE. */
9535
9536 static rtx
9537 s390_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
9538 {
9539 return s390_function_and_libcall_value (mode, NULL_TREE,
9540 NULL_TREE, true);
9541 }
9542
9543
9544 /* Create and return the va_list datatype.
9545
9546 On S/390, va_list is an array type equivalent to
9547
9548 typedef struct __va_list_tag
9549 {
9550 long __gpr;
9551 long __fpr;
9552 void *__overflow_arg_area;
9553 void *__reg_save_area;
9554 } va_list[1];
9555
9556 where __gpr and __fpr hold the number of general purpose
9557 or floating point arguments used up to now, respectively,
9558 __overflow_arg_area points to the stack location of the
9559 next argument passed on the stack, and __reg_save_area
9560 always points to the start of the register area in the
9561 call frame of the current function. The function prologue
9562 saves all registers used for argument passing into this
9563 area if the function uses variable arguments. */
9564
9565 static tree
9566 s390_build_builtin_va_list (void)
9567 {
9568 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
9569
9570 record = lang_hooks.types.make_type (RECORD_TYPE);
9571
9572 type_decl =
9573 build_decl (BUILTINS_LOCATION,
9574 TYPE_DECL, get_identifier ("__va_list_tag"), record);
9575
9576 f_gpr = build_decl (BUILTINS_LOCATION,
9577 FIELD_DECL, get_identifier ("__gpr"),
9578 long_integer_type_node);
9579 f_fpr = build_decl (BUILTINS_LOCATION,
9580 FIELD_DECL, get_identifier ("__fpr"),
9581 long_integer_type_node);
9582 f_ovf = build_decl (BUILTINS_LOCATION,
9583 FIELD_DECL, get_identifier ("__overflow_arg_area"),
9584 ptr_type_node);
9585 f_sav = build_decl (BUILTINS_LOCATION,
9586 FIELD_DECL, get_identifier ("__reg_save_area"),
9587 ptr_type_node);
9588
9589 va_list_gpr_counter_field = f_gpr;
9590 va_list_fpr_counter_field = f_fpr;
9591
9592 DECL_FIELD_CONTEXT (f_gpr) = record;
9593 DECL_FIELD_CONTEXT (f_fpr) = record;
9594 DECL_FIELD_CONTEXT (f_ovf) = record;
9595 DECL_FIELD_CONTEXT (f_sav) = record;
9596
9597 TYPE_STUB_DECL (record) = type_decl;
9598 TYPE_NAME (record) = type_decl;
9599 TYPE_FIELDS (record) = f_gpr;
9600 DECL_CHAIN (f_gpr) = f_fpr;
9601 DECL_CHAIN (f_fpr) = f_ovf;
9602 DECL_CHAIN (f_ovf) = f_sav;
9603
9604 layout_type (record);
9605
9606 /* The correct type is an array type of one element. */
9607 return build_array_type (record, build_index_type (size_zero_node));
9608 }
9609
9610 /* Implement va_start by filling the va_list structure VALIST.
9611 STDARG_P is always true, and ignored.
9612 NEXTARG points to the first anonymous stack argument.
9613
9614 The following global variables are used to initialize
9615 the va_list structure:
9616
9617 crtl->args.info:
9618 holds number of gprs and fprs used for named arguments.
9619 crtl->args.arg_offset_rtx:
9620 holds the offset of the first anonymous stack argument
9621 (relative to the virtual arg pointer). */
9622
9623 static void
9624 s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
9625 {
9626 HOST_WIDE_INT n_gpr, n_fpr;
9627 int off;
9628 tree f_gpr, f_fpr, f_ovf, f_sav;
9629 tree gpr, fpr, ovf, sav, t;
9630
9631 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9632 f_fpr = DECL_CHAIN (f_gpr);
9633 f_ovf = DECL_CHAIN (f_fpr);
9634 f_sav = DECL_CHAIN (f_ovf);
9635
9636 valist = build_simple_mem_ref (valist);
9637 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9638 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9639 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9640 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9641
9642 /* Count number of gp and fp argument registers used. */
9643
9644 n_gpr = crtl->args.info.gprs;
9645 n_fpr = crtl->args.info.fprs;
9646
9647 if (cfun->va_list_gpr_size)
9648 {
9649 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9650 build_int_cst (NULL_TREE, n_gpr));
9651 TREE_SIDE_EFFECTS (t) = 1;
9652 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9653 }
9654
9655 if (cfun->va_list_fpr_size)
9656 {
9657 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
9658 build_int_cst (NULL_TREE, n_fpr));
9659 TREE_SIDE_EFFECTS (t) = 1;
9660 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9661 }
9662
9663 /* Find the overflow area. */
9664 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9665 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9666 {
9667 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9668
9669 off = INTVAL (crtl->args.arg_offset_rtx);
9670 off = off < 0 ? 0 : off;
9671 if (TARGET_DEBUG_ARG)
9672 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9673 (int)n_gpr, (int)n_fpr, off);
9674
9675 t = fold_build_pointer_plus_hwi (t, off);
9676
9677 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
9678 TREE_SIDE_EFFECTS (t) = 1;
9679 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9680 }
9681
9682 /* Find the register save area. */
9683 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9684 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9685 {
9686 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
9687 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
9688
9689 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
9690 TREE_SIDE_EFFECTS (t) = 1;
9691 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9692 }
9693 }
9694
9695 /* Implement va_arg by updating the va_list structure
9696 VALIST as required to retrieve an argument of type
9697 TYPE, and returning that argument.
9698
9699 Generates code equivalent to:
9700
9701 if (integral value) {
9702 if (size <= 4 && args.gpr < 5 ||
9703 size > 4 && args.gpr < 4 )
9704 ret = args.reg_save_area[args.gpr+8]
9705 else
9706 ret = *args.overflow_arg_area++;
9707 } else if (float value) {
9708 if (args.fgpr < 2)
9709 ret = args.reg_save_area[args.fpr+64]
9710 else
9711 ret = *args.overflow_arg_area++;
9712 } else if (aggregate value) {
9713 if (args.gpr < 5)
9714 ret = *args.reg_save_area[args.gpr]
9715 else
9716 ret = **args.overflow_arg_area++;
9717 } */
9718
9719 static tree
9720 s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
9721 gimple_seq *post_p ATTRIBUTE_UNUSED)
9722 {
9723 tree f_gpr, f_fpr, f_ovf, f_sav;
9724 tree gpr, fpr, ovf, sav, reg, t, u;
9725 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
9726 tree lab_false, lab_over, addr;
9727
9728 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
9729 f_fpr = DECL_CHAIN (f_gpr);
9730 f_ovf = DECL_CHAIN (f_fpr);
9731 f_sav = DECL_CHAIN (f_ovf);
9732
9733 valist = build_va_arg_indirect_ref (valist);
9734 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9735 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9736 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9737
9738 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9739 both appear on a lhs. */
9740 valist = unshare_expr (valist);
9741 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9742
9743 size = int_size_in_bytes (type);
9744
9745 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9746 {
9747 if (TARGET_DEBUG_ARG)
9748 {
9749 fprintf (stderr, "va_arg: aggregate type");
9750 debug_tree (type);
9751 }
9752
9753 /* Aggregates are passed by reference. */
9754 indirect_p = 1;
9755 reg = gpr;
9756 n_reg = 1;
9757
9758 /* kernel stack layout on 31 bit: It is assumed here that no padding
9759 will be added by s390_frame_info because for va_args always an even
9760 number of gprs has to be saved r15-r2 = 14 regs. */
9761 sav_ofs = 2 * UNITS_PER_LONG;
9762 sav_scale = UNITS_PER_LONG;
9763 size = UNITS_PER_LONG;
9764 max_reg = GP_ARG_NUM_REG - n_reg;
9765 }
9766 else if (s390_function_arg_float (TYPE_MODE (type), type))
9767 {
9768 if (TARGET_DEBUG_ARG)
9769 {
9770 fprintf (stderr, "va_arg: float type");
9771 debug_tree (type);
9772 }
9773
9774 /* FP args go in FP registers, if present. */
9775 indirect_p = 0;
9776 reg = fpr;
9777 n_reg = 1;
9778 sav_ofs = 16 * UNITS_PER_LONG;
9779 sav_scale = 8;
9780 max_reg = FP_ARG_NUM_REG - n_reg;
9781 }
9782 else
9783 {
9784 if (TARGET_DEBUG_ARG)
9785 {
9786 fprintf (stderr, "va_arg: other type");
9787 debug_tree (type);
9788 }
9789
9790 /* Otherwise into GP registers. */
9791 indirect_p = 0;
9792 reg = gpr;
9793 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9794
9795 /* kernel stack layout on 31 bit: It is assumed here that no padding
9796 will be added by s390_frame_info because for va_args always an even
9797 number of gprs has to be saved r15-r2 = 14 regs. */
9798 sav_ofs = 2 * UNITS_PER_LONG;
9799
9800 if (size < UNITS_PER_LONG)
9801 sav_ofs += UNITS_PER_LONG - size;
9802
9803 sav_scale = UNITS_PER_LONG;
9804 max_reg = GP_ARG_NUM_REG - n_reg;
9805 }
9806
9807 /* Pull the value out of the saved registers ... */
9808
9809 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9810 lab_over = create_artificial_label (UNKNOWN_LOCATION);
9811 addr = create_tmp_var (ptr_type_node, "addr");
9812
9813 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
9814 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9815 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9816 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9817 gimplify_and_add (t, pre_p);
9818
9819 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
9820 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
9821 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
9822 t = fold_build_pointer_plus (t, u);
9823
9824 gimplify_assign (addr, t, pre_p);
9825
9826 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9827
9828 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9829
9830
9831 /* ... Otherwise out of the overflow area. */
9832
9833 t = ovf;
9834 if (size < UNITS_PER_LONG)
9835 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
9836
9837 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9838
9839 gimplify_assign (addr, t, pre_p);
9840
9841 t = fold_build_pointer_plus_hwi (t, size);
9842 gimplify_assign (ovf, t, pre_p);
9843
9844 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
9845
9846
9847 /* Increment register save count. */
9848
9849 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9850 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9851 gimplify_and_add (u, pre_p);
9852
9853 if (indirect_p)
9854 {
9855 t = build_pointer_type_for_mode (build_pointer_type (type),
9856 ptr_mode, true);
9857 addr = fold_convert (t, addr);
9858 addr = build_va_arg_indirect_ref (addr);
9859 }
9860 else
9861 {
9862 t = build_pointer_type_for_mode (type, ptr_mode, true);
9863 addr = fold_convert (t, addr);
9864 }
9865
9866 return build_va_arg_indirect_ref (addr);
9867 }
9868
9869 /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
9870 expanders.
9871 DEST - Register location where CC will be stored.
9872 TDB - Pointer to a 256 byte area where to store the transaction.
9873 diagnostic block. NULL if TDB is not needed.
9874 RETRY - Retry count value. If non-NULL a retry loop for CC2
9875 is emitted
9876 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
9877 of the tbegin instruction pattern. */
9878
9879 void
9880 s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)
9881 {
9882 rtx retry_plus_two = gen_reg_rtx (SImode);
9883 rtx retry_reg = gen_reg_rtx (SImode);
9884 rtx_code_label *retry_label = NULL;
9885
9886 if (retry != NULL_RTX)
9887 {
9888 emit_move_insn (retry_reg, retry);
9889 emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx));
9890 emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx));
9891 retry_label = gen_label_rtx ();
9892 emit_label (retry_label);
9893 }
9894
9895 if (clobber_fprs_p)
9896 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));
9897 else
9898 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
9899 tdb));
9900
9901 emit_move_insn (dest, gen_rtx_UNSPEC (SImode,
9902 gen_rtvec (1, gen_rtx_REG (CCRAWmode,
9903 CC_REGNUM)),
9904 UNSPEC_CC_TO_INT));
9905 if (retry != NULL_RTX)
9906 {
9907 const int CC0 = 1 << 3;
9908 const int CC1 = 1 << 2;
9909 const int CC3 = 1 << 0;
9910 rtx jump;
9911 rtx count = gen_reg_rtx (SImode);
9912 rtx_code_label *leave_label = gen_label_rtx ();
9913
9914 /* Exit for success and permanent failures. */
9915 jump = s390_emit_jump (leave_label,
9916 gen_rtx_EQ (VOIDmode,
9917 gen_rtx_REG (CCRAWmode, CC_REGNUM),
9918 gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3)));
9919 LABEL_NUSES (leave_label) = 1;
9920
9921 /* CC2 - transient failure. Perform retry with ppa. */
9922 emit_move_insn (count, retry_plus_two);
9923 emit_insn (gen_subsi3 (count, count, retry_reg));
9924 emit_insn (gen_tx_assist (count));
9925 jump = emit_jump_insn (gen_doloop_si64 (retry_label,
9926 retry_reg,
9927 retry_reg));
9928 JUMP_LABEL (jump) = retry_label;
9929 LABEL_NUSES (retry_label) = 1;
9930 emit_label (leave_label);
9931 }
9932 }
9933
9934 /* Builtins. */
9935
9936 enum s390_builtin
9937 {
9938 S390_BUILTIN_TBEGIN,
9939 S390_BUILTIN_TBEGIN_NOFLOAT,
9940 S390_BUILTIN_TBEGIN_RETRY,
9941 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9942 S390_BUILTIN_TBEGINC,
9943 S390_BUILTIN_TEND,
9944 S390_BUILTIN_TABORT,
9945 S390_BUILTIN_NON_TX_STORE,
9946 S390_BUILTIN_TX_NESTING_DEPTH,
9947 S390_BUILTIN_TX_ASSIST,
9948
9949 S390_BUILTIN_max
9950 };
9951
9952 static enum insn_code const code_for_builtin[S390_BUILTIN_max] = {
9953 CODE_FOR_tbegin,
9954 CODE_FOR_tbegin_nofloat,
9955 CODE_FOR_tbegin_retry,
9956 CODE_FOR_tbegin_retry_nofloat,
9957 CODE_FOR_tbeginc,
9958 CODE_FOR_tend,
9959 CODE_FOR_tabort,
9960 CODE_FOR_ntstg,
9961 CODE_FOR_etnd,
9962 CODE_FOR_tx_assist
9963 };
9964
9965 static void
9966 s390_init_builtins (void)
9967 {
9968 tree ftype, uint64_type;
9969 tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"),
9970 NULL, NULL);
9971 tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL);
9972
9973 /* void foo (void) */
9974 ftype = build_function_type_list (void_type_node, NULL_TREE);
9975 add_builtin_function ("__builtin_tbeginc", ftype, S390_BUILTIN_TBEGINC,
9976 BUILT_IN_MD, NULL, NULL_TREE);
9977
9978 /* void foo (int) */
9979 ftype = build_function_type_list (void_type_node, integer_type_node,
9980 NULL_TREE);
9981 add_builtin_function ("__builtin_tabort", ftype,
9982 S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr);
9983 add_builtin_function ("__builtin_tx_assist", ftype,
9984 S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);
9985
9986 /* int foo (void *) */
9987 ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);
9988 add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,
9989 BUILT_IN_MD, NULL, returns_twice_attr);
9990 add_builtin_function ("__builtin_tbegin_nofloat", ftype,
9991 S390_BUILTIN_TBEGIN_NOFLOAT,
9992 BUILT_IN_MD, NULL, returns_twice_attr);
9993
9994 /* int foo (void *, int) */
9995 ftype = build_function_type_list (integer_type_node, ptr_type_node,
9996 integer_type_node, NULL_TREE);
9997 add_builtin_function ("__builtin_tbegin_retry", ftype,
9998 S390_BUILTIN_TBEGIN_RETRY,
9999 BUILT_IN_MD,
10000 NULL, returns_twice_attr);
10001 add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,
10002 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
10003 BUILT_IN_MD,
10004 NULL, returns_twice_attr);
10005
10006 /* int foo (void) */
10007 ftype = build_function_type_list (integer_type_node, NULL_TREE);
10008 add_builtin_function ("__builtin_tx_nesting_depth", ftype,
10009 S390_BUILTIN_TX_NESTING_DEPTH,
10010 BUILT_IN_MD, NULL, NULL_TREE);
10011 add_builtin_function ("__builtin_tend", ftype,
10012 S390_BUILTIN_TEND, BUILT_IN_MD, NULL, NULL_TREE);
10013
10014 /* void foo (uint64_t *, uint64_t) */
10015 if (TARGET_64BIT)
10016 uint64_type = long_unsigned_type_node;
10017 else
10018 uint64_type = long_long_unsigned_type_node;
10019
10020 ftype = build_function_type_list (void_type_node,
10021 build_pointer_type (uint64_type),
10022 uint64_type, NULL_TREE);
10023 add_builtin_function ("__builtin_non_tx_store", ftype,
10024 S390_BUILTIN_NON_TX_STORE,
10025 BUILT_IN_MD, NULL, NULL_TREE);
10026 }
10027
10028 /* Expand an expression EXP that calls a built-in function,
10029 with result going to TARGET if that's convenient
10030 (and in mode MODE if that's convenient).
10031 SUBTARGET may be used as the target for computing one of EXP's operands.
10032 IGNORE is nonzero if the value is to be ignored. */
10033
10034 static rtx
10035 s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10036 machine_mode mode ATTRIBUTE_UNUSED,
10037 int ignore ATTRIBUTE_UNUSED)
10038 {
10039 #define MAX_ARGS 2
10040
10041 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10042 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10043 enum insn_code icode;
10044 rtx op[MAX_ARGS], pat;
10045 int arity;
10046 bool nonvoid;
10047 tree arg;
10048 call_expr_arg_iterator iter;
10049
10050 if (fcode >= S390_BUILTIN_max)
10051 internal_error ("bad builtin fcode");
10052 icode = code_for_builtin[fcode];
10053 if (icode == 0)
10054 internal_error ("bad builtin fcode");
10055
10056 if (!TARGET_HTM)
10057 error ("Transactional execution builtins not enabled (-mhtm)\n");
10058
10059 /* Set a flag in the machine specific cfun part in order to support
10060 saving/restoring of FPRs. */
10061 if (fcode == S390_BUILTIN_TBEGIN || fcode == S390_BUILTIN_TBEGIN_RETRY)
10062 cfun->machine->tbegin_p = true;
10063
10064 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
10065
10066 arity = 0;
10067 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10068 {
10069 const struct insn_operand_data *insn_op;
10070
10071 if (arg == error_mark_node)
10072 return NULL_RTX;
10073 if (arity >= MAX_ARGS)
10074 return NULL_RTX;
10075
10076 insn_op = &insn_data[icode].operand[arity + nonvoid];
10077
10078 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
10079
10080 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
10081 {
10082 if (insn_op->predicate == memory_operand)
10083 {
10084 /* Don't move a NULL pointer into a register. Otherwise
10085 we have to rely on combine being able to move it back
10086 in order to get an immediate 0 in the instruction. */
10087 if (op[arity] != const0_rtx)
10088 op[arity] = copy_to_mode_reg (Pmode, op[arity]);
10089 op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]);
10090 }
10091 else
10092 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
10093 }
10094
10095 arity++;
10096 }
10097
10098 if (nonvoid)
10099 {
10100 machine_mode tmode = insn_data[icode].operand[0].mode;
10101 if (!target
10102 || GET_MODE (target) != tmode
10103 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
10104 target = gen_reg_rtx (tmode);
10105 }
10106
10107 switch (arity)
10108 {
10109 case 0:
10110 pat = GEN_FCN (icode) (target);
10111 break;
10112 case 1:
10113 if (nonvoid)
10114 pat = GEN_FCN (icode) (target, op[0]);
10115 else
10116 pat = GEN_FCN (icode) (op[0]);
10117 break;
10118 case 2:
10119 if (nonvoid)
10120 pat = GEN_FCN (icode) (target, op[0], op[1]);
10121 else
10122 pat = GEN_FCN (icode) (op[0], op[1]);
10123 break;
10124 default:
10125 gcc_unreachable ();
10126 }
10127 if (!pat)
10128 return NULL_RTX;
10129 emit_insn (pat);
10130
10131 if (nonvoid)
10132 return target;
10133 else
10134 return const0_rtx;
10135 }
10136
10137 /* We call mcount before the function prologue. So a profiled leaf
10138 function should stay a leaf function. */
10139
10140 static bool
10141 s390_keep_leaf_when_profiled ()
10142 {
10143 return true;
10144 }
10145
10146 /* Output assembly code for the trampoline template to
10147 stdio stream FILE.
10148
10149 On S/390, we use gpr 1 internally in the trampoline code;
10150 gpr 0 is used to hold the static chain. */
10151
10152 static void
10153 s390_asm_trampoline_template (FILE *file)
10154 {
10155 rtx op[2];
10156 op[0] = gen_rtx_REG (Pmode, 0);
10157 op[1] = gen_rtx_REG (Pmode, 1);
10158
10159 if (TARGET_64BIT)
10160 {
10161 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10162 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
10163 output_asm_insn ("br\t%1", op); /* 2 byte */
10164 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
10165 }
10166 else
10167 {
10168 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10169 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
10170 output_asm_insn ("br\t%1", op); /* 2 byte */
10171 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
10172 }
10173 }
10174
10175 /* Emit RTL insns to initialize the variable parts of a trampoline.
10176 FNADDR is an RTX for the address of the function's pure code.
10177 CXT is an RTX for the static chain value for the function. */
10178
10179 static void
10180 s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
10181 {
10182 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10183 rtx mem;
10184
10185 emit_block_move (m_tramp, assemble_trampoline_template (),
10186 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
10187
10188 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
10189 emit_move_insn (mem, cxt);
10190 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
10191 emit_move_insn (mem, fnaddr);
10192 }
10193
10194 /* Output assembler code to FILE to increment profiler label # LABELNO
10195 for profiling a function entry. */
10196
10197 void
10198 s390_function_profiler (FILE *file, int labelno)
10199 {
10200 rtx op[7];
10201
10202 char label[128];
10203 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
10204
10205 fprintf (file, "# function profiler \n");
10206
10207 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
10208 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
10209 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
10210
10211 op[2] = gen_rtx_REG (Pmode, 1);
10212 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
10213 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
10214
10215 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
10216 if (flag_pic)
10217 {
10218 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
10219 op[4] = gen_rtx_CONST (Pmode, op[4]);
10220 }
10221
10222 if (TARGET_64BIT)
10223 {
10224 output_asm_insn ("stg\t%0,%1", op);
10225 output_asm_insn ("larl\t%2,%3", op);
10226 output_asm_insn ("brasl\t%0,%4", op);
10227 output_asm_insn ("lg\t%0,%1", op);
10228 }
10229 else if (!flag_pic)
10230 {
10231 op[6] = gen_label_rtx ();
10232
10233 output_asm_insn ("st\t%0,%1", op);
10234 output_asm_insn ("bras\t%2,%l6", op);
10235 output_asm_insn (".long\t%4", op);
10236 output_asm_insn (".long\t%3", op);
10237 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10238 output_asm_insn ("l\t%0,0(%2)", op);
10239 output_asm_insn ("l\t%2,4(%2)", op);
10240 output_asm_insn ("basr\t%0,%0", op);
10241 output_asm_insn ("l\t%0,%1", op);
10242 }
10243 else
10244 {
10245 op[5] = gen_label_rtx ();
10246 op[6] = gen_label_rtx ();
10247
10248 output_asm_insn ("st\t%0,%1", op);
10249 output_asm_insn ("bras\t%2,%l6", op);
10250 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
10251 output_asm_insn (".long\t%4-%l5", op);
10252 output_asm_insn (".long\t%3-%l5", op);
10253 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10254 output_asm_insn ("lr\t%0,%2", op);
10255 output_asm_insn ("a\t%0,0(%2)", op);
10256 output_asm_insn ("a\t%2,4(%2)", op);
10257 output_asm_insn ("basr\t%0,%0", op);
10258 output_asm_insn ("l\t%0,%1", op);
10259 }
10260 }
10261
10262 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
10263 into its SYMBOL_REF_FLAGS. */
10264
10265 static void
10266 s390_encode_section_info (tree decl, rtx rtl, int first)
10267 {
10268 default_encode_section_info (decl, rtl, first);
10269
10270 if (TREE_CODE (decl) == VAR_DECL)
10271 {
10272 /* If a variable has a forced alignment to < 2 bytes, mark it
10273 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
10274 operand. */
10275 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
10276 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
10277 if (!DECL_SIZE (decl)
10278 || !DECL_ALIGN (decl)
10279 || !tree_fits_shwi_p (DECL_SIZE (decl))
10280 || (DECL_ALIGN (decl) <= 64
10281 && DECL_ALIGN (decl) != tree_to_shwi (DECL_SIZE (decl))))
10282 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
10283 }
10284
10285 /* Literal pool references don't have a decl so they are handled
10286 differently here. We rely on the information in the MEM_ALIGN
10287 entry to decide upon natural alignment. */
10288 if (MEM_P (rtl)
10289 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
10290 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
10291 && (MEM_ALIGN (rtl) == 0
10292 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
10293 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
10294 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
10295 }
10296
10297 /* Output thunk to FILE that implements a C++ virtual function call (with
10298 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
10299 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
10300 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
10301 relative to the resulting this pointer. */
10302
10303 static void
10304 s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10305 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10306 tree function)
10307 {
10308 rtx op[10];
10309 int nonlocal = 0;
10310
10311 /* Make sure unwind info is emitted for the thunk if needed. */
10312 final_start_function (emit_barrier (), file, 1);
10313
10314 /* Operand 0 is the target function. */
10315 op[0] = XEXP (DECL_RTL (function), 0);
10316 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
10317 {
10318 nonlocal = 1;
10319 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
10320 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
10321 op[0] = gen_rtx_CONST (Pmode, op[0]);
10322 }
10323
10324 /* Operand 1 is the 'this' pointer. */
10325 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10326 op[1] = gen_rtx_REG (Pmode, 3);
10327 else
10328 op[1] = gen_rtx_REG (Pmode, 2);
10329
10330 /* Operand 2 is the delta. */
10331 op[2] = GEN_INT (delta);
10332
10333 /* Operand 3 is the vcall_offset. */
10334 op[3] = GEN_INT (vcall_offset);
10335
10336 /* Operand 4 is the temporary register. */
10337 op[4] = gen_rtx_REG (Pmode, 1);
10338
10339 /* Operands 5 to 8 can be used as labels. */
10340 op[5] = NULL_RTX;
10341 op[6] = NULL_RTX;
10342 op[7] = NULL_RTX;
10343 op[8] = NULL_RTX;
10344
10345 /* Operand 9 can be used for temporary register. */
10346 op[9] = NULL_RTX;
10347
10348 /* Generate code. */
10349 if (TARGET_64BIT)
10350 {
10351 /* Setup literal pool pointer if required. */
10352 if ((!DISP_IN_RANGE (delta)
10353 && !CONST_OK_FOR_K (delta)
10354 && !CONST_OK_FOR_Os (delta))
10355 || (!DISP_IN_RANGE (vcall_offset)
10356 && !CONST_OK_FOR_K (vcall_offset)
10357 && !CONST_OK_FOR_Os (vcall_offset)))
10358 {
10359 op[5] = gen_label_rtx ();
10360 output_asm_insn ("larl\t%4,%5", op);
10361 }
10362
10363 /* Add DELTA to this pointer. */
10364 if (delta)
10365 {
10366 if (CONST_OK_FOR_J (delta))
10367 output_asm_insn ("la\t%1,%2(%1)", op);
10368 else if (DISP_IN_RANGE (delta))
10369 output_asm_insn ("lay\t%1,%2(%1)", op);
10370 else if (CONST_OK_FOR_K (delta))
10371 output_asm_insn ("aghi\t%1,%2", op);
10372 else if (CONST_OK_FOR_Os (delta))
10373 output_asm_insn ("agfi\t%1,%2", op);
10374 else
10375 {
10376 op[6] = gen_label_rtx ();
10377 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
10378 }
10379 }
10380
10381 /* Perform vcall adjustment. */
10382 if (vcall_offset)
10383 {
10384 if (DISP_IN_RANGE (vcall_offset))
10385 {
10386 output_asm_insn ("lg\t%4,0(%1)", op);
10387 output_asm_insn ("ag\t%1,%3(%4)", op);
10388 }
10389 else if (CONST_OK_FOR_K (vcall_offset))
10390 {
10391 output_asm_insn ("lghi\t%4,%3", op);
10392 output_asm_insn ("ag\t%4,0(%1)", op);
10393 output_asm_insn ("ag\t%1,0(%4)", op);
10394 }
10395 else if (CONST_OK_FOR_Os (vcall_offset))
10396 {
10397 output_asm_insn ("lgfi\t%4,%3", op);
10398 output_asm_insn ("ag\t%4,0(%1)", op);
10399 output_asm_insn ("ag\t%1,0(%4)", op);
10400 }
10401 else
10402 {
10403 op[7] = gen_label_rtx ();
10404 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
10405 output_asm_insn ("ag\t%4,0(%1)", op);
10406 output_asm_insn ("ag\t%1,0(%4)", op);
10407 }
10408 }
10409
10410 /* Jump to target. */
10411 output_asm_insn ("jg\t%0", op);
10412
10413 /* Output literal pool if required. */
10414 if (op[5])
10415 {
10416 output_asm_insn (".align\t4", op);
10417 targetm.asm_out.internal_label (file, "L",
10418 CODE_LABEL_NUMBER (op[5]));
10419 }
10420 if (op[6])
10421 {
10422 targetm.asm_out.internal_label (file, "L",
10423 CODE_LABEL_NUMBER (op[6]));
10424 output_asm_insn (".long\t%2", op);
10425 }
10426 if (op[7])
10427 {
10428 targetm.asm_out.internal_label (file, "L",
10429 CODE_LABEL_NUMBER (op[7]));
10430 output_asm_insn (".long\t%3", op);
10431 }
10432 }
10433 else
10434 {
10435 /* Setup base pointer if required. */
10436 if (!vcall_offset
10437 || (!DISP_IN_RANGE (delta)
10438 && !CONST_OK_FOR_K (delta)
10439 && !CONST_OK_FOR_Os (delta))
10440 || (!DISP_IN_RANGE (delta)
10441 && !CONST_OK_FOR_K (vcall_offset)
10442 && !CONST_OK_FOR_Os (vcall_offset)))
10443 {
10444 op[5] = gen_label_rtx ();
10445 output_asm_insn ("basr\t%4,0", op);
10446 targetm.asm_out.internal_label (file, "L",
10447 CODE_LABEL_NUMBER (op[5]));
10448 }
10449
10450 /* Add DELTA to this pointer. */
10451 if (delta)
10452 {
10453 if (CONST_OK_FOR_J (delta))
10454 output_asm_insn ("la\t%1,%2(%1)", op);
10455 else if (DISP_IN_RANGE (delta))
10456 output_asm_insn ("lay\t%1,%2(%1)", op);
10457 else if (CONST_OK_FOR_K (delta))
10458 output_asm_insn ("ahi\t%1,%2", op);
10459 else if (CONST_OK_FOR_Os (delta))
10460 output_asm_insn ("afi\t%1,%2", op);
10461 else
10462 {
10463 op[6] = gen_label_rtx ();
10464 output_asm_insn ("a\t%1,%6-%5(%4)", op);
10465 }
10466 }
10467
10468 /* Perform vcall adjustment. */
10469 if (vcall_offset)
10470 {
10471 if (CONST_OK_FOR_J (vcall_offset))
10472 {
10473 output_asm_insn ("l\t%4,0(%1)", op);
10474 output_asm_insn ("a\t%1,%3(%4)", op);
10475 }
10476 else if (DISP_IN_RANGE (vcall_offset))
10477 {
10478 output_asm_insn ("l\t%4,0(%1)", op);
10479 output_asm_insn ("ay\t%1,%3(%4)", op);
10480 }
10481 else if (CONST_OK_FOR_K (vcall_offset))
10482 {
10483 output_asm_insn ("lhi\t%4,%3", op);
10484 output_asm_insn ("a\t%4,0(%1)", op);
10485 output_asm_insn ("a\t%1,0(%4)", op);
10486 }
10487 else if (CONST_OK_FOR_Os (vcall_offset))
10488 {
10489 output_asm_insn ("iilf\t%4,%3", op);
10490 output_asm_insn ("a\t%4,0(%1)", op);
10491 output_asm_insn ("a\t%1,0(%4)", op);
10492 }
10493 else
10494 {
10495 op[7] = gen_label_rtx ();
10496 output_asm_insn ("l\t%4,%7-%5(%4)", op);
10497 output_asm_insn ("a\t%4,0(%1)", op);
10498 output_asm_insn ("a\t%1,0(%4)", op);
10499 }
10500
10501 /* We had to clobber the base pointer register.
10502 Re-setup the base pointer (with a different base). */
10503 op[5] = gen_label_rtx ();
10504 output_asm_insn ("basr\t%4,0", op);
10505 targetm.asm_out.internal_label (file, "L",
10506 CODE_LABEL_NUMBER (op[5]));
10507 }
10508
10509 /* Jump to target. */
10510 op[8] = gen_label_rtx ();
10511
10512 if (!flag_pic)
10513 output_asm_insn ("l\t%4,%8-%5(%4)", op);
10514 else if (!nonlocal)
10515 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10516 /* We cannot call through .plt, since .plt requires %r12 loaded. */
10517 else if (flag_pic == 1)
10518 {
10519 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10520 output_asm_insn ("l\t%4,%0(%4)", op);
10521 }
10522 else if (flag_pic == 2)
10523 {
10524 op[9] = gen_rtx_REG (Pmode, 0);
10525 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
10526 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10527 output_asm_insn ("ar\t%4,%9", op);
10528 output_asm_insn ("l\t%4,0(%4)", op);
10529 }
10530
10531 output_asm_insn ("br\t%4", op);
10532
10533 /* Output literal pool. */
10534 output_asm_insn (".align\t4", op);
10535
10536 if (nonlocal && flag_pic == 2)
10537 output_asm_insn (".long\t%0", op);
10538 if (nonlocal)
10539 {
10540 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
10541 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
10542 }
10543
10544 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
10545 if (!flag_pic)
10546 output_asm_insn (".long\t%0", op);
10547 else
10548 output_asm_insn (".long\t%0-%5", op);
10549
10550 if (op[6])
10551 {
10552 targetm.asm_out.internal_label (file, "L",
10553 CODE_LABEL_NUMBER (op[6]));
10554 output_asm_insn (".long\t%2", op);
10555 }
10556 if (op[7])
10557 {
10558 targetm.asm_out.internal_label (file, "L",
10559 CODE_LABEL_NUMBER (op[7]));
10560 output_asm_insn (".long\t%3", op);
10561 }
10562 }
10563 final_end_function ();
10564 }
10565
10566 static bool
10567 s390_valid_pointer_mode (machine_mode mode)
10568 {
10569 return (mode == SImode || (TARGET_64BIT && mode == DImode));
10570 }
10571
10572 /* Checks whether the given CALL_EXPR would use a caller
10573 saved register. This is used to decide whether sibling call
10574 optimization could be performed on the respective function
10575 call. */
10576
10577 static bool
10578 s390_call_saved_register_used (tree call_expr)
10579 {
10580 CUMULATIVE_ARGS cum_v;
10581 cumulative_args_t cum;
10582 tree parameter;
10583 machine_mode mode;
10584 tree type;
10585 rtx parm_rtx;
10586 int reg, i;
10587
10588 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
10589 cum = pack_cumulative_args (&cum_v);
10590
10591 for (i = 0; i < call_expr_nargs (call_expr); i++)
10592 {
10593 parameter = CALL_EXPR_ARG (call_expr, i);
10594 gcc_assert (parameter);
10595
10596 /* For an undeclared variable passed as parameter we will get
10597 an ERROR_MARK node here. */
10598 if (TREE_CODE (parameter) == ERROR_MARK)
10599 return true;
10600
10601 type = TREE_TYPE (parameter);
10602 gcc_assert (type);
10603
10604 mode = TYPE_MODE (type);
10605 gcc_assert (mode);
10606
10607 if (pass_by_reference (&cum_v, mode, type, true))
10608 {
10609 mode = Pmode;
10610 type = build_pointer_type (type);
10611 }
10612
10613 parm_rtx = s390_function_arg (cum, mode, type, 0);
10614
10615 s390_function_arg_advance (cum, mode, type, 0);
10616
10617 if (!parm_rtx)
10618 continue;
10619
10620 if (REG_P (parm_rtx))
10621 {
10622 for (reg = 0;
10623 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
10624 reg++)
10625 if (!call_used_regs[reg + REGNO (parm_rtx)])
10626 return true;
10627 }
10628
10629 if (GET_CODE (parm_rtx) == PARALLEL)
10630 {
10631 int i;
10632
10633 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
10634 {
10635 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
10636
10637 gcc_assert (REG_P (r));
10638
10639 for (reg = 0;
10640 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
10641 reg++)
10642 if (!call_used_regs[reg + REGNO (r)])
10643 return true;
10644 }
10645 }
10646
10647 }
10648 return false;
10649 }
10650
10651 /* Return true if the given call expression can be
10652 turned into a sibling call.
10653 DECL holds the declaration of the function to be called whereas
10654 EXP is the call expression itself. */
10655
10656 static bool
10657 s390_function_ok_for_sibcall (tree decl, tree exp)
10658 {
10659 /* The TPF epilogue uses register 1. */
10660 if (TARGET_TPF_PROFILING)
10661 return false;
10662
10663 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
10664 which would have to be restored before the sibcall. */
10665 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
10666 return false;
10667
10668 /* Register 6 on s390 is available as an argument register but unfortunately
10669 "caller saved". This makes functions needing this register for arguments
10670 not suitable for sibcalls. */
10671 return !s390_call_saved_register_used (exp);
10672 }
10673
10674 /* Return the fixed registers used for condition codes. */
10675
10676 static bool
10677 s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
10678 {
10679 *p1 = CC_REGNUM;
10680 *p2 = INVALID_REGNUM;
10681
10682 return true;
10683 }
10684
10685 /* This function is used by the call expanders of the machine description.
10686 It emits the call insn itself together with the necessary operations
10687 to adjust the target address and returns the emitted insn.
10688 ADDR_LOCATION is the target address rtx
10689 TLS_CALL the location of the thread-local symbol
10690 RESULT_REG the register where the result of the call should be stored
10691 RETADDR_REG the register where the return address should be stored
10692 If this parameter is NULL_RTX the call is considered
10693 to be a sibling call. */
10694
10695 rtx_insn *
10696 s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
10697 rtx retaddr_reg)
10698 {
10699 bool plt_call = false;
10700 rtx_insn *insn;
10701 rtx call;
10702 rtx clobber;
10703 rtvec vec;
10704
10705 /* Direct function calls need special treatment. */
10706 if (GET_CODE (addr_location) == SYMBOL_REF)
10707 {
10708 /* When calling a global routine in PIC mode, we must
10709 replace the symbol itself with the PLT stub. */
10710 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
10711 {
10712 if (retaddr_reg != NULL_RTX)
10713 {
10714 addr_location = gen_rtx_UNSPEC (Pmode,
10715 gen_rtvec (1, addr_location),
10716 UNSPEC_PLT);
10717 addr_location = gen_rtx_CONST (Pmode, addr_location);
10718 plt_call = true;
10719 }
10720 else
10721 /* For -fpic code the PLT entries might use r12 which is
10722 call-saved. Therefore we cannot do a sibcall when
10723 calling directly using a symbol ref. When reaching
10724 this point we decided (in s390_function_ok_for_sibcall)
10725 to do a sibcall for a function pointer but one of the
10726 optimizers was able to get rid of the function pointer
10727 by propagating the symbol ref into the call. This
10728 optimization is illegal for S/390 so we turn the direct
10729 call into a indirect call again. */
10730 addr_location = force_reg (Pmode, addr_location);
10731 }
10732
10733 /* Unless we can use the bras(l) insn, force the
10734 routine address into a register. */
10735 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
10736 {
10737 if (flag_pic)
10738 addr_location = legitimize_pic_address (addr_location, 0);
10739 else
10740 addr_location = force_reg (Pmode, addr_location);
10741 }
10742 }
10743
10744 /* If it is already an indirect call or the code above moved the
10745 SYMBOL_REF to somewhere else make sure the address can be found in
10746 register 1. */
10747 if (retaddr_reg == NULL_RTX
10748 && GET_CODE (addr_location) != SYMBOL_REF
10749 && !plt_call)
10750 {
10751 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
10752 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
10753 }
10754
10755 addr_location = gen_rtx_MEM (QImode, addr_location);
10756 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
10757
10758 if (result_reg != NULL_RTX)
10759 call = gen_rtx_SET (VOIDmode, result_reg, call);
10760
10761 if (retaddr_reg != NULL_RTX)
10762 {
10763 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
10764
10765 if (tls_call != NULL_RTX)
10766 vec = gen_rtvec (3, call, clobber,
10767 gen_rtx_USE (VOIDmode, tls_call));
10768 else
10769 vec = gen_rtvec (2, call, clobber);
10770
10771 call = gen_rtx_PARALLEL (VOIDmode, vec);
10772 }
10773
10774 insn = emit_call_insn (call);
10775
10776 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10777 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
10778 {
10779 /* s390_function_ok_for_sibcall should
10780 have denied sibcalls in this case. */
10781 gcc_assert (retaddr_reg != NULL_RTX);
10782 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
10783 }
10784 return insn;
10785 }
10786
10787 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
10788
10789 static void
10790 s390_conditional_register_usage (void)
10791 {
10792 int i;
10793
10794 if (flag_pic)
10795 {
10796 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10797 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10798 }
10799 if (TARGET_CPU_ZARCH)
10800 {
10801 fixed_regs[BASE_REGNUM] = 0;
10802 call_used_regs[BASE_REGNUM] = 0;
10803 fixed_regs[RETURN_REGNUM] = 0;
10804 call_used_regs[RETURN_REGNUM] = 0;
10805 }
10806 if (TARGET_64BIT)
10807 {
10808 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
10809 call_used_regs[i] = call_really_used_regs[i] = 0;
10810 }
10811 else
10812 {
10813 call_used_regs[FPR4_REGNUM] = call_really_used_regs[FPR4_REGNUM] = 0;
10814 call_used_regs[FPR6_REGNUM] = call_really_used_regs[FPR6_REGNUM] = 0;
10815 }
10816
10817 if (TARGET_SOFT_FLOAT)
10818 {
10819 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
10820 call_used_regs[i] = fixed_regs[i] = 1;
10821 }
10822 }
10823
10824 /* Corresponding function to eh_return expander. */
10825
10826 static GTY(()) rtx s390_tpf_eh_return_symbol;
10827 void
10828 s390_emit_tpf_eh_return (rtx target)
10829 {
10830 rtx_insn *insn;
10831 rtx reg, orig_ra;
10832
10833 if (!s390_tpf_eh_return_symbol)
10834 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
10835
10836 reg = gen_rtx_REG (Pmode, 2);
10837 orig_ra = gen_rtx_REG (Pmode, 3);
10838
10839 emit_move_insn (reg, target);
10840 emit_move_insn (orig_ra, get_hard_reg_initial_val (Pmode, RETURN_REGNUM));
10841 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
10842 gen_rtx_REG (Pmode, RETURN_REGNUM));
10843 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
10844 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), orig_ra);
10845
10846 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
10847 }
10848
10849 /* Rework the prologue/epilogue to avoid saving/restoring
10850 registers unnecessarily. */
10851
10852 static void
10853 s390_optimize_prologue (void)
10854 {
10855 rtx_insn *insn, *new_insn, *next_insn;
10856
10857 /* Do a final recompute of the frame-related data. */
10858 s390_optimize_register_info ();
10859
10860 /* If all special registers are in fact used, there's nothing we
10861 can do, so no point in walking the insn list. */
10862
10863 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
10864 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
10865 && (TARGET_CPU_ZARCH
10866 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
10867 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10868 return;
10869
10870 /* Search for prologue/epilogue insns and replace them. */
10871
10872 for (insn = get_insns (); insn; insn = next_insn)
10873 {
10874 int first, last, off;
10875 rtx set, base, offset;
10876 rtx pat;
10877
10878 next_insn = NEXT_INSN (insn);
10879
10880 if (! NONJUMP_INSN_P (insn) || ! RTX_FRAME_RELATED_P (insn))
10881 continue;
10882
10883 pat = PATTERN (insn);
10884
10885 /* Remove ldgr/lgdr instructions used for saving and restore
10886 GPRs if possible. */
10887 if (TARGET_Z10
10888 && GET_CODE (pat) == SET
10889 && GET_MODE (SET_SRC (pat)) == DImode
10890 && REG_P (SET_SRC (pat))
10891 && REG_P (SET_DEST (pat)))
10892 {
10893 int src_regno = REGNO (SET_SRC (pat));
10894 int dest_regno = REGNO (SET_DEST (pat));
10895 int gpr_regno;
10896 int fpr_regno;
10897
10898 if (!((GENERAL_REGNO_P (src_regno) && FP_REGNO_P (dest_regno))
10899 || (FP_REGNO_P (src_regno) && GENERAL_REGNO_P (dest_regno))))
10900 continue;
10901
10902 gpr_regno = GENERAL_REGNO_P (src_regno) ? src_regno : dest_regno;
10903 fpr_regno = FP_REGNO_P (src_regno) ? src_regno : dest_regno;
10904
10905 /* GPR must be call-saved, FPR must be call-clobbered. */
10906 if (!call_really_used_regs[fpr_regno]
10907 || call_really_used_regs[gpr_regno])
10908 continue;
10909
10910 /* It must not happen that what we once saved in an FPR now
10911 needs a stack slot. */
10912 gcc_assert (cfun_gpr_save_slot (gpr_regno) != -1);
10913
10914 if (cfun_gpr_save_slot (gpr_regno) == 0)
10915 {
10916 remove_insn (insn);
10917 continue;
10918 }
10919 }
10920
10921 if (GET_CODE (pat) == PARALLEL
10922 && store_multiple_operation (pat, VOIDmode))
10923 {
10924 set = XVECEXP (pat, 0, 0);
10925 first = REGNO (SET_SRC (set));
10926 last = first + XVECLEN (pat, 0) - 1;
10927 offset = const0_rtx;
10928 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10929 off = INTVAL (offset);
10930
10931 if (GET_CODE (base) != REG || off < 0)
10932 continue;
10933 if (cfun_frame_layout.first_save_gpr != -1
10934 && (cfun_frame_layout.first_save_gpr < first
10935 || cfun_frame_layout.last_save_gpr > last))
10936 continue;
10937 if (REGNO (base) != STACK_POINTER_REGNUM
10938 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10939 continue;
10940 if (first > BASE_REGNUM || last < BASE_REGNUM)
10941 continue;
10942
10943 if (cfun_frame_layout.first_save_gpr != -1)
10944 {
10945 rtx s_pat = save_gprs (base,
10946 off + (cfun_frame_layout.first_save_gpr
10947 - first) * UNITS_PER_LONG,
10948 cfun_frame_layout.first_save_gpr,
10949 cfun_frame_layout.last_save_gpr);
10950 new_insn = emit_insn_before (s_pat, insn);
10951 INSN_ADDRESSES_NEW (new_insn, -1);
10952 }
10953
10954 remove_insn (insn);
10955 continue;
10956 }
10957
10958 if (cfun_frame_layout.first_save_gpr == -1
10959 && GET_CODE (pat) == SET
10960 && GENERAL_REG_P (SET_SRC (pat))
10961 && GET_CODE (SET_DEST (pat)) == MEM)
10962 {
10963 set = pat;
10964 first = REGNO (SET_SRC (set));
10965 offset = const0_rtx;
10966 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10967 off = INTVAL (offset);
10968
10969 if (GET_CODE (base) != REG || off < 0)
10970 continue;
10971 if (REGNO (base) != STACK_POINTER_REGNUM
10972 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10973 continue;
10974
10975 remove_insn (insn);
10976 continue;
10977 }
10978
10979 if (GET_CODE (pat) == PARALLEL
10980 && load_multiple_operation (pat, VOIDmode))
10981 {
10982 set = XVECEXP (pat, 0, 0);
10983 first = REGNO (SET_DEST (set));
10984 last = first + XVECLEN (pat, 0) - 1;
10985 offset = const0_rtx;
10986 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10987 off = INTVAL (offset);
10988
10989 if (GET_CODE (base) != REG || off < 0)
10990 continue;
10991
10992 if (cfun_frame_layout.first_restore_gpr != -1
10993 && (cfun_frame_layout.first_restore_gpr < first
10994 || cfun_frame_layout.last_restore_gpr > last))
10995 continue;
10996 if (REGNO (base) != STACK_POINTER_REGNUM
10997 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10998 continue;
10999 if (first > BASE_REGNUM || last < BASE_REGNUM)
11000 continue;
11001
11002 if (cfun_frame_layout.first_restore_gpr != -1)
11003 {
11004 rtx rpat = restore_gprs (base,
11005 off + (cfun_frame_layout.first_restore_gpr
11006 - first) * UNITS_PER_LONG,
11007 cfun_frame_layout.first_restore_gpr,
11008 cfun_frame_layout.last_restore_gpr);
11009
11010 /* Remove REG_CFA_RESTOREs for registers that we no
11011 longer need to save. */
11012 REG_NOTES (rpat) = REG_NOTES (insn);
11013 for (rtx *ptr = &REG_NOTES (rpat); *ptr; )
11014 if (REG_NOTE_KIND (*ptr) == REG_CFA_RESTORE
11015 && ((int) REGNO (XEXP (*ptr, 0))
11016 < cfun_frame_layout.first_restore_gpr))
11017 *ptr = XEXP (*ptr, 1);
11018 else
11019 ptr = &XEXP (*ptr, 1);
11020 new_insn = emit_insn_before (rpat, insn);
11021 RTX_FRAME_RELATED_P (new_insn) = 1;
11022 INSN_ADDRESSES_NEW (new_insn, -1);
11023 }
11024
11025 remove_insn (insn);
11026 continue;
11027 }
11028
11029 if (cfun_frame_layout.first_restore_gpr == -1
11030 && GET_CODE (pat) == SET
11031 && GENERAL_REG_P (SET_DEST (pat))
11032 && GET_CODE (SET_SRC (pat)) == MEM)
11033 {
11034 set = pat;
11035 first = REGNO (SET_DEST (set));
11036 offset = const0_rtx;
11037 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
11038 off = INTVAL (offset);
11039
11040 if (GET_CODE (base) != REG || off < 0)
11041 continue;
11042
11043 if (REGNO (base) != STACK_POINTER_REGNUM
11044 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
11045 continue;
11046
11047 remove_insn (insn);
11048 continue;
11049 }
11050 }
11051 }
11052
11053 /* On z10 and later the dynamic branch prediction must see the
11054 backward jump within a certain windows. If not it falls back to
11055 the static prediction. This function rearranges the loop backward
11056 branch in a way which makes the static prediction always correct.
11057 The function returns true if it added an instruction. */
11058 static bool
11059 s390_fix_long_loop_prediction (rtx_insn *insn)
11060 {
11061 rtx set = single_set (insn);
11062 rtx code_label, label_ref, new_label;
11063 rtx_insn *uncond_jump;
11064 rtx_insn *cur_insn;
11065 rtx tmp;
11066 int distance;
11067
11068 /* This will exclude branch on count and branch on index patterns
11069 since these are correctly statically predicted. */
11070 if (!set
11071 || SET_DEST (set) != pc_rtx
11072 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
11073 return false;
11074
11075 /* Skip conditional returns. */
11076 if (ANY_RETURN_P (XEXP (SET_SRC (set), 1))
11077 && XEXP (SET_SRC (set), 2) == pc_rtx)
11078 return false;
11079
11080 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
11081 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
11082
11083 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
11084
11085 code_label = XEXP (label_ref, 0);
11086
11087 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
11088 || INSN_ADDRESSES (INSN_UID (insn)) == -1
11089 || (INSN_ADDRESSES (INSN_UID (insn))
11090 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
11091 return false;
11092
11093 for (distance = 0, cur_insn = PREV_INSN (insn);
11094 distance < PREDICT_DISTANCE - 6;
11095 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
11096 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
11097 return false;
11098
11099 new_label = gen_label_rtx ();
11100 uncond_jump = emit_jump_insn_after (
11101 gen_rtx_SET (VOIDmode, pc_rtx,
11102 gen_rtx_LABEL_REF (VOIDmode, code_label)),
11103 insn);
11104 emit_label_after (new_label, uncond_jump);
11105
11106 tmp = XEXP (SET_SRC (set), 1);
11107 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
11108 XEXP (SET_SRC (set), 2) = tmp;
11109 INSN_CODE (insn) = -1;
11110
11111 XEXP (label_ref, 0) = new_label;
11112 JUMP_LABEL (insn) = new_label;
11113 JUMP_LABEL (uncond_jump) = code_label;
11114
11115 return true;
11116 }
11117
11118 /* Returns 1 if INSN reads the value of REG for purposes not related
11119 to addressing of memory, and 0 otherwise. */
11120 static int
11121 s390_non_addr_reg_read_p (rtx reg, rtx_insn *insn)
11122 {
11123 return reg_referenced_p (reg, PATTERN (insn))
11124 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
11125 }
11126
11127 /* Starting from INSN find_cond_jump looks downwards in the insn
11128 stream for a single jump insn which is the last user of the
11129 condition code set in INSN. */
11130 static rtx_insn *
11131 find_cond_jump (rtx_insn *insn)
11132 {
11133 for (; insn; insn = NEXT_INSN (insn))
11134 {
11135 rtx ite, cc;
11136
11137 if (LABEL_P (insn))
11138 break;
11139
11140 if (!JUMP_P (insn))
11141 {
11142 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
11143 break;
11144 continue;
11145 }
11146
11147 /* This will be triggered by a return. */
11148 if (GET_CODE (PATTERN (insn)) != SET)
11149 break;
11150
11151 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
11152 ite = SET_SRC (PATTERN (insn));
11153
11154 if (GET_CODE (ite) != IF_THEN_ELSE)
11155 break;
11156
11157 cc = XEXP (XEXP (ite, 0), 0);
11158 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
11159 break;
11160
11161 if (find_reg_note (insn, REG_DEAD, cc))
11162 return insn;
11163 break;
11164 }
11165
11166 return NULL;
11167 }
11168
11169 /* Swap the condition in COND and the operands in OP0 and OP1 so that
11170 the semantics does not change. If NULL_RTX is passed as COND the
11171 function tries to find the conditional jump starting with INSN. */
11172 static void
11173 s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx_insn *insn)
11174 {
11175 rtx tmp = *op0;
11176
11177 if (cond == NULL_RTX)
11178 {
11179 rtx_insn *jump = find_cond_jump (NEXT_INSN (insn));
11180 rtx set = jump ? single_set (jump) : NULL_RTX;
11181
11182 if (set == NULL_RTX)
11183 return;
11184
11185 cond = XEXP (SET_SRC (set), 0);
11186 }
11187
11188 *op0 = *op1;
11189 *op1 = tmp;
11190 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
11191 }
11192
11193 /* On z10, instructions of the compare-and-branch family have the
11194 property to access the register occurring as second operand with
11195 its bits complemented. If such a compare is grouped with a second
11196 instruction that accesses the same register non-complemented, and
11197 if that register's value is delivered via a bypass, then the
11198 pipeline recycles, thereby causing significant performance decline.
11199 This function locates such situations and exchanges the two
11200 operands of the compare. The function return true whenever it
11201 added an insn. */
11202 static bool
11203 s390_z10_optimize_cmp (rtx_insn *insn)
11204 {
11205 rtx_insn *prev_insn, *next_insn;
11206 bool insn_added_p = false;
11207 rtx cond, *op0, *op1;
11208
11209 if (GET_CODE (PATTERN (insn)) == PARALLEL)
11210 {
11211 /* Handle compare and branch and branch on count
11212 instructions. */
11213 rtx pattern = single_set (insn);
11214
11215 if (!pattern
11216 || SET_DEST (pattern) != pc_rtx
11217 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
11218 return false;
11219
11220 cond = XEXP (SET_SRC (pattern), 0);
11221 op0 = &XEXP (cond, 0);
11222 op1 = &XEXP (cond, 1);
11223 }
11224 else if (GET_CODE (PATTERN (insn)) == SET)
11225 {
11226 rtx src, dest;
11227
11228 /* Handle normal compare instructions. */
11229 src = SET_SRC (PATTERN (insn));
11230 dest = SET_DEST (PATTERN (insn));
11231
11232 if (!REG_P (dest)
11233 || !CC_REGNO_P (REGNO (dest))
11234 || GET_CODE (src) != COMPARE)
11235 return false;
11236
11237 /* s390_swap_cmp will try to find the conditional
11238 jump when passing NULL_RTX as condition. */
11239 cond = NULL_RTX;
11240 op0 = &XEXP (src, 0);
11241 op1 = &XEXP (src, 1);
11242 }
11243 else
11244 return false;
11245
11246 if (!REG_P (*op0) || !REG_P (*op1))
11247 return false;
11248
11249 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
11250 return false;
11251
11252 /* Swap the COMPARE arguments and its mask if there is a
11253 conflicting access in the previous insn. */
11254 prev_insn = prev_active_insn (insn);
11255 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
11256 && reg_referenced_p (*op1, PATTERN (prev_insn)))
11257 s390_swap_cmp (cond, op0, op1, insn);
11258
11259 /* Check if there is a conflict with the next insn. If there
11260 was no conflict with the previous insn, then swap the
11261 COMPARE arguments and its mask. If we already swapped
11262 the operands, or if swapping them would cause a conflict
11263 with the previous insn, issue a NOP after the COMPARE in
11264 order to separate the two instuctions. */
11265 next_insn = next_active_insn (insn);
11266 if (next_insn != NULL_RTX && INSN_P (next_insn)
11267 && s390_non_addr_reg_read_p (*op1, next_insn))
11268 {
11269 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
11270 && s390_non_addr_reg_read_p (*op0, prev_insn))
11271 {
11272 if (REGNO (*op1) == 0)
11273 emit_insn_after (gen_nop1 (), insn);
11274 else
11275 emit_insn_after (gen_nop (), insn);
11276 insn_added_p = true;
11277 }
11278 else
11279 s390_swap_cmp (cond, op0, op1, insn);
11280 }
11281 return insn_added_p;
11282 }
11283
11284 /* Perform machine-dependent processing. */
11285
11286 static void
11287 s390_reorg (void)
11288 {
11289 bool pool_overflow = false;
11290
11291 /* Make sure all splits have been performed; splits after
11292 machine_dependent_reorg might confuse insn length counts. */
11293 split_all_insns_noflow ();
11294
11295 /* Install the main literal pool and the associated base
11296 register load insns.
11297
11298 In addition, there are two problematic situations we need
11299 to correct:
11300
11301 - the literal pool might be > 4096 bytes in size, so that
11302 some of its elements cannot be directly accessed
11303
11304 - a branch target might be > 64K away from the branch, so that
11305 it is not possible to use a PC-relative instruction.
11306
11307 To fix those, we split the single literal pool into multiple
11308 pool chunks, reloading the pool base register at various
11309 points throughout the function to ensure it always points to
11310 the pool chunk the following code expects, and / or replace
11311 PC-relative branches by absolute branches.
11312
11313 However, the two problems are interdependent: splitting the
11314 literal pool can move a branch further away from its target,
11315 causing the 64K limit to overflow, and on the other hand,
11316 replacing a PC-relative branch by an absolute branch means
11317 we need to put the branch target address into the literal
11318 pool, possibly causing it to overflow.
11319
11320 So, we loop trying to fix up both problems until we manage
11321 to satisfy both conditions at the same time. Note that the
11322 loop is guaranteed to terminate as every pass of the loop
11323 strictly decreases the total number of PC-relative branches
11324 in the function. (This is not completely true as there
11325 might be branch-over-pool insns introduced by chunkify_start.
11326 Those never need to be split however.) */
11327
11328 for (;;)
11329 {
11330 struct constant_pool *pool = NULL;
11331
11332 /* Collect the literal pool. */
11333 if (!pool_overflow)
11334 {
11335 pool = s390_mainpool_start ();
11336 if (!pool)
11337 pool_overflow = true;
11338 }
11339
11340 /* If literal pool overflowed, start to chunkify it. */
11341 if (pool_overflow)
11342 pool = s390_chunkify_start ();
11343
11344 /* Split out-of-range branches. If this has created new
11345 literal pool entries, cancel current chunk list and
11346 recompute it. zSeries machines have large branch
11347 instructions, so we never need to split a branch. */
11348 if (!TARGET_CPU_ZARCH && s390_split_branches ())
11349 {
11350 if (pool_overflow)
11351 s390_chunkify_cancel (pool);
11352 else
11353 s390_mainpool_cancel (pool);
11354
11355 continue;
11356 }
11357
11358 /* If we made it up to here, both conditions are satisfied.
11359 Finish up literal pool related changes. */
11360 if (pool_overflow)
11361 s390_chunkify_finish (pool);
11362 else
11363 s390_mainpool_finish (pool);
11364
11365 /* We're done splitting branches. */
11366 cfun->machine->split_branches_pending_p = false;
11367 break;
11368 }
11369
11370 /* Generate out-of-pool execute target insns. */
11371 if (TARGET_CPU_ZARCH)
11372 {
11373 rtx_insn *insn, *target;
11374 rtx label;
11375
11376 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11377 {
11378 label = s390_execute_label (insn);
11379 if (!label)
11380 continue;
11381
11382 gcc_assert (label != const0_rtx);
11383
11384 target = emit_label (XEXP (label, 0));
11385 INSN_ADDRESSES_NEW (target, -1);
11386
11387 target = emit_insn (s390_execute_target (insn));
11388 INSN_ADDRESSES_NEW (target, -1);
11389 }
11390 }
11391
11392 /* Try to optimize prologue and epilogue further. */
11393 s390_optimize_prologue ();
11394
11395 /* Walk over the insns and do some >=z10 specific changes. */
11396 if (s390_tune == PROCESSOR_2097_Z10
11397 || s390_tune == PROCESSOR_2817_Z196
11398 || s390_tune == PROCESSOR_2827_ZEC12)
11399 {
11400 rtx_insn *insn;
11401 bool insn_added_p = false;
11402
11403 /* The insn lengths and addresses have to be up to date for the
11404 following manipulations. */
11405 shorten_branches (get_insns ());
11406
11407 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11408 {
11409 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
11410 continue;
11411
11412 if (JUMP_P (insn))
11413 insn_added_p |= s390_fix_long_loop_prediction (insn);
11414
11415 if ((GET_CODE (PATTERN (insn)) == PARALLEL
11416 || GET_CODE (PATTERN (insn)) == SET)
11417 && s390_tune == PROCESSOR_2097_Z10)
11418 insn_added_p |= s390_z10_optimize_cmp (insn);
11419 }
11420
11421 /* Adjust branches if we added new instructions. */
11422 if (insn_added_p)
11423 shorten_branches (get_insns ());
11424 }
11425 }
11426
11427 /* Return true if INSN is a fp load insn writing register REGNO. */
11428 static inline bool
11429 s390_fpload_toreg (rtx_insn *insn, unsigned int regno)
11430 {
11431 rtx set;
11432 enum attr_type flag = s390_safe_attr_type (insn);
11433
11434 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
11435 return false;
11436
11437 set = single_set (insn);
11438
11439 if (set == NULL_RTX)
11440 return false;
11441
11442 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
11443 return false;
11444
11445 if (REGNO (SET_DEST (set)) != regno)
11446 return false;
11447
11448 return true;
11449 }
11450
11451 /* This value describes the distance to be avoided between an
11452 aritmetic fp instruction and an fp load writing the same register.
11453 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
11454 fine but the exact value has to be avoided. Otherwise the FP
11455 pipeline will throw an exception causing a major penalty. */
11456 #define Z10_EARLYLOAD_DISTANCE 7
11457
11458 /* Rearrange the ready list in order to avoid the situation described
11459 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
11460 moved to the very end of the ready list. */
11461 static void
11462 s390_z10_prevent_earlyload_conflicts (rtx_insn **ready, int *nready_p)
11463 {
11464 unsigned int regno;
11465 int nready = *nready_p;
11466 rtx_insn *tmp;
11467 int i;
11468 rtx_insn *insn;
11469 rtx set;
11470 enum attr_type flag;
11471 int distance;
11472
11473 /* Skip DISTANCE - 1 active insns. */
11474 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
11475 distance > 0 && insn != NULL_RTX;
11476 distance--, insn = prev_active_insn (insn))
11477 if (CALL_P (insn) || JUMP_P (insn))
11478 return;
11479
11480 if (insn == NULL_RTX)
11481 return;
11482
11483 set = single_set (insn);
11484
11485 if (set == NULL_RTX || !REG_P (SET_DEST (set))
11486 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
11487 return;
11488
11489 flag = s390_safe_attr_type (insn);
11490
11491 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
11492 return;
11493
11494 regno = REGNO (SET_DEST (set));
11495 i = nready - 1;
11496
11497 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
11498 i--;
11499
11500 if (!i)
11501 return;
11502
11503 tmp = ready[i];
11504 memmove (&ready[1], &ready[0], sizeof (rtx_insn *) * i);
11505 ready[0] = tmp;
11506 }
11507
11508
11509 /* The s390_sched_state variable tracks the state of the current or
11510 the last instruction group.
11511
11512 0,1,2 number of instructions scheduled in the current group
11513 3 the last group is complete - normal insns
11514 4 the last group was a cracked/expanded insn */
11515
11516 static int s390_sched_state;
11517
11518 #define S390_OOO_SCHED_STATE_NORMAL 3
11519 #define S390_OOO_SCHED_STATE_CRACKED 4
11520
11521 #define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
11522 #define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
11523 #define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
11524 #define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
11525
11526 static unsigned int
11527 s390_get_sched_attrmask (rtx_insn *insn)
11528 {
11529 unsigned int mask = 0;
11530
11531 if (get_attr_ooo_cracked (insn))
11532 mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED;
11533 if (get_attr_ooo_expanded (insn))
11534 mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED;
11535 if (get_attr_ooo_endgroup (insn))
11536 mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP;
11537 if (get_attr_ooo_groupalone (insn))
11538 mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE;
11539 return mask;
11540 }
11541
11542 /* Return the scheduling score for INSN. The higher the score the
11543 better. The score is calculated from the OOO scheduling attributes
11544 of INSN and the scheduling state s390_sched_state. */
11545 static int
11546 s390_sched_score (rtx_insn *insn)
11547 {
11548 unsigned int mask = s390_get_sched_attrmask (insn);
11549 int score = 0;
11550
11551 switch (s390_sched_state)
11552 {
11553 case 0:
11554 /* Try to put insns into the first slot which would otherwise
11555 break a group. */
11556 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11557 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11558 score += 5;
11559 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11560 score += 10;
11561 case 1:
11562 /* Prefer not cracked insns while trying to put together a
11563 group. */
11564 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11565 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11566 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11567 score += 10;
11568 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0)
11569 score += 5;
11570 break;
11571 case 2:
11572 /* Prefer not cracked insns while trying to put together a
11573 group. */
11574 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11575 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11576 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11577 score += 10;
11578 /* Prefer endgroup insns in the last slot. */
11579 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0)
11580 score += 10;
11581 break;
11582 case S390_OOO_SCHED_STATE_NORMAL:
11583 /* Prefer not cracked insns if the last was not cracked. */
11584 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11585 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0)
11586 score += 5;
11587 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11588 score += 10;
11589 break;
11590 case S390_OOO_SCHED_STATE_CRACKED:
11591 /* Try to keep cracked insns together to prevent them from
11592 interrupting groups. */
11593 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11594 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11595 score += 5;
11596 break;
11597 }
11598 return score;
11599 }
11600
11601 /* This function is called via hook TARGET_SCHED_REORDER before
11602 issuing one insn from list READY which contains *NREADYP entries.
11603 For target z10 it reorders load instructions to avoid early load
11604 conflicts in the floating point pipeline */
11605 static int
11606 s390_sched_reorder (FILE *file, int verbose,
11607 rtx_insn **ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
11608 {
11609 if (s390_tune == PROCESSOR_2097_Z10)
11610 if (reload_completed && *nreadyp > 1)
11611 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
11612
11613 if (s390_tune == PROCESSOR_2827_ZEC12
11614 && reload_completed
11615 && *nreadyp > 1)
11616 {
11617 int i;
11618 int last_index = *nreadyp - 1;
11619 int max_index = -1;
11620 int max_score = -1;
11621 rtx_insn *tmp;
11622
11623 /* Just move the insn with the highest score to the top (the
11624 end) of the list. A full sort is not needed since a conflict
11625 in the hazard recognition cannot happen. So the top insn in
11626 the ready list will always be taken. */
11627 for (i = last_index; i >= 0; i--)
11628 {
11629 int score;
11630
11631 if (recog_memoized (ready[i]) < 0)
11632 continue;
11633
11634 score = s390_sched_score (ready[i]);
11635 if (score > max_score)
11636 {
11637 max_score = score;
11638 max_index = i;
11639 }
11640 }
11641
11642 if (max_index != -1)
11643 {
11644 if (max_index != last_index)
11645 {
11646 tmp = ready[max_index];
11647 ready[max_index] = ready[last_index];
11648 ready[last_index] = tmp;
11649
11650 if (verbose > 5)
11651 fprintf (file,
11652 "move insn %d to the top of list\n",
11653 INSN_UID (ready[last_index]));
11654 }
11655 else if (verbose > 5)
11656 fprintf (file,
11657 "best insn %d already on top\n",
11658 INSN_UID (ready[last_index]));
11659 }
11660
11661 if (verbose > 5)
11662 {
11663 fprintf (file, "ready list ooo attributes - sched state: %d\n",
11664 s390_sched_state);
11665
11666 for (i = last_index; i >= 0; i--)
11667 {
11668 if (recog_memoized (ready[i]) < 0)
11669 continue;
11670 fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]),
11671 s390_sched_score (ready[i]));
11672 #define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
11673 PRINT_OOO_ATTR (ooo_cracked);
11674 PRINT_OOO_ATTR (ooo_expanded);
11675 PRINT_OOO_ATTR (ooo_endgroup);
11676 PRINT_OOO_ATTR (ooo_groupalone);
11677 #undef PRINT_OOO_ATTR
11678 fprintf (file, "\n");
11679 }
11680 }
11681 }
11682
11683 return s390_issue_rate ();
11684 }
11685
11686
11687 /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
11688 the scheduler has issued INSN. It stores the last issued insn into
11689 last_scheduled_insn in order to make it available for
11690 s390_sched_reorder. */
11691 static int
11692 s390_sched_variable_issue (FILE *file, int verbose, rtx_insn *insn, int more)
11693 {
11694 last_scheduled_insn = insn;
11695
11696 if (s390_tune == PROCESSOR_2827_ZEC12
11697 && reload_completed
11698 && recog_memoized (insn) >= 0)
11699 {
11700 unsigned int mask = s390_get_sched_attrmask (insn);
11701
11702 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11703 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11704 s390_sched_state = S390_OOO_SCHED_STATE_CRACKED;
11705 else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0
11706 || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11707 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11708 else
11709 {
11710 /* Only normal insns are left (mask == 0). */
11711 switch (s390_sched_state)
11712 {
11713 case 0:
11714 case 1:
11715 case 2:
11716 case S390_OOO_SCHED_STATE_NORMAL:
11717 if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL)
11718 s390_sched_state = 1;
11719 else
11720 s390_sched_state++;
11721
11722 break;
11723 case S390_OOO_SCHED_STATE_CRACKED:
11724 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11725 break;
11726 }
11727 }
11728 if (verbose > 5)
11729 {
11730 fprintf (file, "insn %d: ", INSN_UID (insn));
11731 #define PRINT_OOO_ATTR(ATTR) \
11732 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
11733 PRINT_OOO_ATTR (ooo_cracked);
11734 PRINT_OOO_ATTR (ooo_expanded);
11735 PRINT_OOO_ATTR (ooo_endgroup);
11736 PRINT_OOO_ATTR (ooo_groupalone);
11737 #undef PRINT_OOO_ATTR
11738 fprintf (file, "\n");
11739 fprintf (file, "sched state: %d\n", s390_sched_state);
11740 }
11741 }
11742
11743 if (GET_CODE (PATTERN (insn)) != USE
11744 && GET_CODE (PATTERN (insn)) != CLOBBER)
11745 return more - 1;
11746 else
11747 return more;
11748 }
11749
11750 static void
11751 s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
11752 int verbose ATTRIBUTE_UNUSED,
11753 int max_ready ATTRIBUTE_UNUSED)
11754 {
11755 last_scheduled_insn = NULL;
11756 s390_sched_state = 0;
11757 }
11758
11759 /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
11760 a new number struct loop *loop should be unrolled if tuned for cpus with
11761 a built-in stride prefetcher.
11762 The loop is analyzed for memory accesses by calling check_dpu for
11763 each rtx of the loop. Depending on the loop_depth and the amount of
11764 memory accesses a new number <=nunroll is returned to improve the
11765 behaviour of the hardware prefetch unit. */
11766 static unsigned
11767 s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
11768 {
11769 basic_block *bbs;
11770 rtx_insn *insn;
11771 unsigned i;
11772 unsigned mem_count = 0;
11773
11774 if (s390_tune != PROCESSOR_2097_Z10
11775 && s390_tune != PROCESSOR_2817_Z196
11776 && s390_tune != PROCESSOR_2827_ZEC12)
11777 return nunroll;
11778
11779 /* Count the number of memory references within the loop body. */
11780 bbs = get_loop_body (loop);
11781 subrtx_iterator::array_type array;
11782 for (i = 0; i < loop->num_nodes; i++)
11783 FOR_BB_INSNS (bbs[i], insn)
11784 if (INSN_P (insn) && INSN_CODE (insn) != -1)
11785 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
11786 if (MEM_P (*iter))
11787 mem_count += 1;
11788 free (bbs);
11789
11790 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11791 if (mem_count == 0)
11792 return nunroll;
11793
11794 switch (loop_depth(loop))
11795 {
11796 case 1:
11797 return MIN (nunroll, 28 / mem_count);
11798 case 2:
11799 return MIN (nunroll, 22 / mem_count);
11800 default:
11801 return MIN (nunroll, 16 / mem_count);
11802 }
11803 }
11804
11805 static void
11806 s390_option_override (void)
11807 {
11808 unsigned int i;
11809 cl_deferred_option *opt;
11810 vec<cl_deferred_option> *v =
11811 (vec<cl_deferred_option> *) s390_deferred_options;
11812
11813 if (v)
11814 FOR_EACH_VEC_ELT (*v, i, opt)
11815 {
11816 switch (opt->opt_index)
11817 {
11818 case OPT_mhotpatch:
11819 s390_hotpatch_trampoline_halfwords = (opt->value) ?
11820 s390_hotpatch_trampoline_halfwords_default : -1;
11821 break;
11822 case OPT_mhotpatch_:
11823 {
11824 int val;
11825
11826 val = integral_argument (opt->arg);
11827 if (val == -1)
11828 {
11829 /* argument is not a plain number */
11830 error ("argument to %qs should be a non-negative integer",
11831 "-mhotpatch=");
11832 break;
11833 }
11834 else if (val > s390_hotpatch_trampoline_halfwords_max)
11835 {
11836 error ("argument to %qs is too large (max. %d)",
11837 "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max);
11838 break;
11839 }
11840 s390_hotpatch_trampoline_halfwords = val;
11841 break;
11842 }
11843 default:
11844 gcc_unreachable ();
11845 }
11846 }
11847
11848 /* Set up function hooks. */
11849 init_machine_status = s390_init_machine_status;
11850
11851 /* Architecture mode defaults according to ABI. */
11852 if (!(target_flags_explicit & MASK_ZARCH))
11853 {
11854 if (TARGET_64BIT)
11855 target_flags |= MASK_ZARCH;
11856 else
11857 target_flags &= ~MASK_ZARCH;
11858 }
11859
11860 /* Set the march default in case it hasn't been specified on
11861 cmdline. */
11862 if (s390_arch == PROCESSOR_max)
11863 {
11864 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
11865 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
11866 s390_arch_flags = processor_flags_table[(int)s390_arch];
11867 }
11868
11869 /* Determine processor to tune for. */
11870 if (s390_tune == PROCESSOR_max)
11871 {
11872 s390_tune = s390_arch;
11873 s390_tune_flags = s390_arch_flags;
11874 }
11875
11876 /* Sanity checks. */
11877 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
11878 error ("z/Architecture mode not supported on %s", s390_arch_string);
11879 if (TARGET_64BIT && !TARGET_ZARCH)
11880 error ("64-bit ABI not supported in ESA/390 mode");
11881
11882 /* Use hardware DFP if available and not explicitly disabled by
11883 user. E.g. with -m31 -march=z10 -mzarch */
11884 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
11885 target_flags |= MASK_HARD_DFP;
11886
11887 /* Enable hardware transactions if available and not explicitly
11888 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
11889 if (!(target_flags_explicit & MASK_OPT_HTM) && TARGET_CPU_HTM && TARGET_ZARCH)
11890 target_flags |= MASK_OPT_HTM;
11891
11892 if (TARGET_HARD_DFP && !TARGET_DFP)
11893 {
11894 if (target_flags_explicit & MASK_HARD_DFP)
11895 {
11896 if (!TARGET_CPU_DFP)
11897 error ("hardware decimal floating point instructions"
11898 " not available on %s", s390_arch_string);
11899 if (!TARGET_ZARCH)
11900 error ("hardware decimal floating point instructions"
11901 " not available in ESA/390 mode");
11902 }
11903 else
11904 target_flags &= ~MASK_HARD_DFP;
11905 }
11906
11907 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
11908 {
11909 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
11910 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
11911
11912 target_flags &= ~MASK_HARD_DFP;
11913 }
11914
11915 /* Set processor cost function. */
11916 switch (s390_tune)
11917 {
11918 case PROCESSOR_2084_Z990:
11919 s390_cost = &z990_cost;
11920 break;
11921 case PROCESSOR_2094_Z9_109:
11922 s390_cost = &z9_109_cost;
11923 break;
11924 case PROCESSOR_2097_Z10:
11925 s390_cost = &z10_cost;
11926 break;
11927 case PROCESSOR_2817_Z196:
11928 s390_cost = &z196_cost;
11929 break;
11930 case PROCESSOR_2827_ZEC12:
11931 s390_cost = &zEC12_cost;
11932 break;
11933 default:
11934 s390_cost = &z900_cost;
11935 }
11936
11937 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
11938 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
11939 "in combination");
11940
11941 if (s390_stack_size)
11942 {
11943 if (s390_stack_guard >= s390_stack_size)
11944 error ("stack size must be greater than the stack guard value");
11945 else if (s390_stack_size > 1 << 16)
11946 error ("stack size must not be greater than 64k");
11947 }
11948 else if (s390_stack_guard)
11949 error ("-mstack-guard implies use of -mstack-size");
11950
11951 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
11952 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
11953 target_flags |= MASK_LONG_DOUBLE_128;
11954 #endif
11955
11956 if (s390_tune == PROCESSOR_2097_Z10
11957 || s390_tune == PROCESSOR_2817_Z196
11958 || s390_tune == PROCESSOR_2827_ZEC12)
11959 {
11960 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
11961 global_options.x_param_values,
11962 global_options_set.x_param_values);
11963 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
11964 global_options.x_param_values,
11965 global_options_set.x_param_values);
11966 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
11967 global_options.x_param_values,
11968 global_options_set.x_param_values);
11969 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
11970 global_options.x_param_values,
11971 global_options_set.x_param_values);
11972 }
11973
11974 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
11975 global_options.x_param_values,
11976 global_options_set.x_param_values);
11977 /* values for loop prefetching */
11978 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
11979 global_options.x_param_values,
11980 global_options_set.x_param_values);
11981 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
11982 global_options.x_param_values,
11983 global_options_set.x_param_values);
11984 /* s390 has more than 2 levels and the size is much larger. Since
11985 we are always running virtualized assume that we only get a small
11986 part of the caches above l1. */
11987 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
11988 global_options.x_param_values,
11989 global_options_set.x_param_values);
11990 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
11991 global_options.x_param_values,
11992 global_options_set.x_param_values);
11993 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
11994 global_options.x_param_values,
11995 global_options_set.x_param_values);
11996
11997 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
11998 requires the arch flags to be evaluated already. Since prefetching
11999 is beneficial on s390, we enable it if available. */
12000 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
12001 flag_prefetch_loop_arrays = 1;
12002
12003 /* Use the alternative scheduling-pressure algorithm by default. */
12004 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
12005 global_options.x_param_values,
12006 global_options_set.x_param_values);
12007
12008 if (TARGET_TPF)
12009 {
12010 /* Don't emit DWARF3/4 unless specifically selected. The TPF
12011 debuggers do not yet support DWARF 3/4. */
12012 if (!global_options_set.x_dwarf_strict)
12013 dwarf_strict = 1;
12014 if (!global_options_set.x_dwarf_version)
12015 dwarf_version = 2;
12016 }
12017
12018 /* Register a target-specific optimization-and-lowering pass
12019 to run immediately before prologue and epilogue generation.
12020
12021 Registering the pass must be done at start up. It's
12022 convenient to do it here. */
12023 opt_pass *new_pass = new pass_s390_early_mach (g);
12024 struct register_pass_info insert_pass_s390_early_mach =
12025 {
12026 new_pass, /* pass */
12027 "pro_and_epilogue", /* reference_pass_name */
12028 1, /* ref_pass_instance_number */
12029 PASS_POS_INSERT_BEFORE /* po_op */
12030 };
12031 register_pass (&insert_pass_s390_early_mach);
12032 }
12033
12034 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
12035
12036 static bool
12037 s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
12038 unsigned int align ATTRIBUTE_UNUSED,
12039 enum by_pieces_operation op ATTRIBUTE_UNUSED,
12040 bool speed_p ATTRIBUTE_UNUSED)
12041 {
12042 return (size == 1 || size == 2
12043 || size == 4 || (TARGET_ZARCH && size == 8));
12044 }
12045
12046 /* Initialize GCC target structure. */
12047
12048 #undef TARGET_ASM_ALIGNED_HI_OP
12049 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
12050 #undef TARGET_ASM_ALIGNED_DI_OP
12051 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
12052 #undef TARGET_ASM_INTEGER
12053 #define TARGET_ASM_INTEGER s390_assemble_integer
12054
12055 #undef TARGET_ASM_OPEN_PAREN
12056 #define TARGET_ASM_OPEN_PAREN ""
12057
12058 #undef TARGET_ASM_CLOSE_PAREN
12059 #define TARGET_ASM_CLOSE_PAREN ""
12060
12061 #undef TARGET_OPTION_OVERRIDE
12062 #define TARGET_OPTION_OVERRIDE s390_option_override
12063
12064 #undef TARGET_ENCODE_SECTION_INFO
12065 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
12066
12067 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12068 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12069
12070 #ifdef HAVE_AS_TLS
12071 #undef TARGET_HAVE_TLS
12072 #define TARGET_HAVE_TLS true
12073 #endif
12074 #undef TARGET_CANNOT_FORCE_CONST_MEM
12075 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
12076
12077 #undef TARGET_DELEGITIMIZE_ADDRESS
12078 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
12079
12080 #undef TARGET_LEGITIMIZE_ADDRESS
12081 #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
12082
12083 #undef TARGET_RETURN_IN_MEMORY
12084 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
12085
12086 #undef TARGET_INIT_BUILTINS
12087 #define TARGET_INIT_BUILTINS s390_init_builtins
12088 #undef TARGET_EXPAND_BUILTIN
12089 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
12090
12091 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
12092 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
12093
12094 #undef TARGET_ASM_OUTPUT_MI_THUNK
12095 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
12096 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
12097 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
12098
12099 #undef TARGET_SCHED_ADJUST_PRIORITY
12100 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
12101 #undef TARGET_SCHED_ISSUE_RATE
12102 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
12103 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12104 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
12105
12106 #undef TARGET_SCHED_VARIABLE_ISSUE
12107 #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
12108 #undef TARGET_SCHED_REORDER
12109 #define TARGET_SCHED_REORDER s390_sched_reorder
12110 #undef TARGET_SCHED_INIT
12111 #define TARGET_SCHED_INIT s390_sched_init
12112
12113 #undef TARGET_CANNOT_COPY_INSN_P
12114 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
12115 #undef TARGET_RTX_COSTS
12116 #define TARGET_RTX_COSTS s390_rtx_costs
12117 #undef TARGET_ADDRESS_COST
12118 #define TARGET_ADDRESS_COST s390_address_cost
12119 #undef TARGET_REGISTER_MOVE_COST
12120 #define TARGET_REGISTER_MOVE_COST s390_register_move_cost
12121 #undef TARGET_MEMORY_MOVE_COST
12122 #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
12123
12124 #undef TARGET_MACHINE_DEPENDENT_REORG
12125 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
12126
12127 #undef TARGET_VALID_POINTER_MODE
12128 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
12129
12130 #undef TARGET_BUILD_BUILTIN_VA_LIST
12131 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
12132 #undef TARGET_EXPAND_BUILTIN_VA_START
12133 #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
12134 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
12135 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
12136
12137 #undef TARGET_PROMOTE_FUNCTION_MODE
12138 #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
12139 #undef TARGET_PASS_BY_REFERENCE
12140 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
12141
12142 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
12143 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
12144 #undef TARGET_FUNCTION_ARG
12145 #define TARGET_FUNCTION_ARG s390_function_arg
12146 #undef TARGET_FUNCTION_ARG_ADVANCE
12147 #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
12148 #undef TARGET_FUNCTION_VALUE
12149 #define TARGET_FUNCTION_VALUE s390_function_value
12150 #undef TARGET_LIBCALL_VALUE
12151 #define TARGET_LIBCALL_VALUE s390_libcall_value
12152
12153 #undef TARGET_KEEP_LEAF_WHEN_PROFILED
12154 #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
12155
12156 #undef TARGET_FIXED_CONDITION_CODE_REGS
12157 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
12158
12159 #undef TARGET_CC_MODES_COMPATIBLE
12160 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
12161
12162 #undef TARGET_INVALID_WITHIN_DOLOOP
12163 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
12164
12165 #ifdef HAVE_AS_TLS
12166 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12167 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
12168 #endif
12169
12170 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
12171 #undef TARGET_MANGLE_TYPE
12172 #define TARGET_MANGLE_TYPE s390_mangle_type
12173 #endif
12174
12175 #undef TARGET_SCALAR_MODE_SUPPORTED_P
12176 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12177
12178 #undef TARGET_PREFERRED_RELOAD_CLASS
12179 #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
12180
12181 #undef TARGET_SECONDARY_RELOAD
12182 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
12183
12184 #undef TARGET_LIBGCC_CMP_RETURN_MODE
12185 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
12186
12187 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
12188 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
12189
12190 #undef TARGET_LEGITIMATE_ADDRESS_P
12191 #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
12192
12193 #undef TARGET_LEGITIMATE_CONSTANT_P
12194 #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
12195
12196 #undef TARGET_LRA_P
12197 #define TARGET_LRA_P s390_lra_p
12198
12199 #undef TARGET_CAN_ELIMINATE
12200 #define TARGET_CAN_ELIMINATE s390_can_eliminate
12201
12202 #undef TARGET_CONDITIONAL_REGISTER_USAGE
12203 #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
12204
12205 #undef TARGET_LOOP_UNROLL_ADJUST
12206 #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
12207
12208 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
12209 #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
12210 #undef TARGET_TRAMPOLINE_INIT
12211 #define TARGET_TRAMPOLINE_INIT s390_trampoline_init
12212
12213 #undef TARGET_UNWIND_WORD_MODE
12214 #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
12215
12216 #undef TARGET_CANONICALIZE_COMPARISON
12217 #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
12218
12219 #undef TARGET_HARD_REGNO_SCRATCH_OK
12220 #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
12221
12222 #undef TARGET_ATTRIBUTE_TABLE
12223 #define TARGET_ATTRIBUTE_TABLE s390_attribute_table
12224
12225 #undef TARGET_CAN_INLINE_P
12226 #define TARGET_CAN_INLINE_P s390_can_inline_p
12227
12228 #undef TARGET_SET_UP_BY_PROLOGUE
12229 #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
12230
12231 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
12232 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
12233 s390_use_by_pieces_infrastructure_p
12234
12235 struct gcc_target targetm = TARGET_INITIALIZER;
12236
12237 #include "gt-s390.h"
GNU Compiler Collection
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