gcc/config/rs6000/rs6000.opt

   1 ; Options for the rs6000 port of the compiler
   2 ;
   3 ; Copyright (C) 2005-2024 Free Software Foundation, Inc.
   4 ; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
   5 ;
   6 ; This file is part of GCC.
   7 ;
   8 ; GCC is free software; you can redistribute it and/or modify it under
   9 ; the terms of the GNU General Public License as published by the Free
  10 ; Software Foundation; either version 3, or (at your option) any later
  11 ; version.
  12 ;
  13 ; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ; License for more details.
  17 ;
  18 ; You should have received a copy of the GNU General Public License
  19 ; along with GCC; see the file COPYING3.  If not see
  20 ; <http://www.gnu.org/licenses/>.
  21
  22 HeaderInclude
  23 config/rs6000/rs6000-opts.h
  24
  25 ;; ISA flag bits (on/off)
  26 Variable
  27 HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
  28
  29 TargetSave
  30 HOST_WIDE_INT x_rs6000_isa_flags
  31
  32 ;; Miscellaneous flag bits that were set explicitly by the user
  33 Variable
  34 HOST_WIDE_INT rs6000_isa_flags_explicit
  35
  36 TargetSave
  37 HOST_WIDE_INT x_rs6000_isa_flags_explicit
  38
  39 ;; Current processor
  40 TargetVariable
  41 enum processor_type rs6000_cpu = PROCESSOR_PPC603
  42
  43 ;; Current tuning
  44 TargetVariable
  45 enum processor_type rs6000_tune = PROCESSOR_PPC603
  46
  47 ;; Always emit branch hint bits.
  48 TargetVariable
  49 unsigned char rs6000_always_hint
  50
  51 ;; Schedule instructions for group formation.
  52 TargetVariable
  53 unsigned char rs6000_sched_groups
  54
  55 ;; Align branch targets.
  56 TargetVariable
  57 unsigned char rs6000_align_branch_targets
  58
  59 ;; Support for -msched-costly-dep option.
  60 TargetVariable
  61 enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
  62
  63 ;; Support for -minsert-sched-nops option.
  64 TargetVariable
  65 enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
  66
  67 ;; Non-zero to allow overriding loop alignment.
  68 TargetVariable
  69 unsigned char can_override_loop_align
  70
  71 ;; Which small data model to use (for System V targets only)
  72 TargetVariable
  73 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
  74
  75 ;; Bit size of immediate TLS offsets and string from which it is decoded.
  76 TargetVariable
  77 int rs6000_tls_size = 32
  78
  79 ;; ABI enumeration available for subtarget to use.
  80 TargetVariable
  81 enum rs6000_abi rs6000_current_abi = ABI_NONE
  82
  83 ;; Type of traceback to use.
  84 TargetVariable
  85 enum rs6000_traceback_type rs6000_traceback = traceback_default
  86
  87 ;; Control alignment for fields within structures.
  88 TargetVariable
  89 unsigned char rs6000_alignment_flags
  90
  91 ;; Code model for 64-bit linux.
  92 TargetVariable
  93 enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
  94
  95 ;; What type of reciprocal estimation instructions to generate
  96 TargetVariable
  97 unsigned int rs6000_recip_control
  98
  99 ;; Debug flags
 100 TargetVariable
 101 unsigned int rs6000_debug
 102
 103 ;; Whether to enable the -mfloat128 stuff without necessarily enabling the
 104 ;; __float128 keyword.
 105 TargetSave
 106 unsigned char x_TARGET_FLOAT128_TYPE
 107
 108 Variable
 109 unsigned char TARGET_FLOAT128_TYPE
 110
 111 ;; This option existed in the past, but now is always on.
 112 mpowerpc
 113 Target RejectNegative Undocumented Ignore
 114
 115 mpowerpc64
 116 Target Mask(POWERPC64) Var(rs6000_isa_flags)
 117 Use PowerPC-64 instruction set.
 118
 119 mpowerpc-gpopt
 120 Target Mask(PPC_GPOPT) Var(rs6000_isa_flags)
 121 Use PowerPC General Purpose group optional instructions.
 122
 123 mpowerpc-gfxopt
 124 Target Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
 125 Use PowerPC Graphics group optional instructions.
 126
 127 mmfcrf
 128 Target Mask(MFCRF) Var(rs6000_isa_flags)
 129 Use PowerPC V2.01 single field mfcr instruction.
 130
 131 mpopcntb
 132 Target Mask(POPCNTB) Var(rs6000_isa_flags)
 133 Use PowerPC V2.02 popcntb instruction.
 134
 135 mfprnd
 136 Target Mask(FPRND) Var(rs6000_isa_flags)
 137 Use PowerPC V2.02 floating point rounding instructions.
 138
 139 mcmpb
 140 Target Mask(CMPB) Var(rs6000_isa_flags)
 141 Use PowerPC V2.05 compare bytes instruction.
 142
 143 ;; This option existed in the past, but now is always off.
 144 mno-mfpgpr
 145 Target RejectNegative Undocumented Ignore
 146
 147 mmfpgpr
 148 Target RejectNegative Undocumented WarnRemoved
 149
 150 maltivec
 151 Target Mask(ALTIVEC) Var(rs6000_isa_flags)
 152 Use AltiVec instructions.
 153
 154 mhard-dfp
 155 Target Mask(DFP) Var(rs6000_isa_flags)
 156 Use decimal floating point instructions.
 157
 158 mmulhw
 159 Target Mask(MULHW) Var(rs6000_isa_flags)
 160 Use 4xx half-word multiply instructions.
 161
 162 mdlmzb
 163 Target Mask(DLMZB) Var(rs6000_isa_flags)
 164 Use 4xx string-search dlmzb instruction.
 165
 166 mmultiple
 167 Target Mask(MULTIPLE) Var(rs6000_isa_flags)
 168 Generate load/store multiple instructions.
 169
 170 ;; This option existed in the past, but now is always off.
 171 mno-string
 172 Target RejectNegative Undocumented Ignore
 173
 174 mstring
 175 Target RejectNegative Undocumented WarnRemoved
 176
 177 msoft-float
 178 Target RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
 179 Do not use hardware floating point.
 180
 181 mhard-float
 182 Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
 183 Use hardware floating point.
 184
 185 mpopcntd
 186 Target Mask(POPCNTD) Var(rs6000_isa_flags)
 187 Use PowerPC V2.06 popcntd instruction.
 188
 189 mfriz
 190 Target Var(TARGET_FRIZ) Init(-1) Save
 191 Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
 192
 193 mveclibabi=
 194 Target RejectNegative Joined Var(rs6000_veclibabi_name)
 195 Vector library ABI to use.
 196
 197 mvsx
 198 Target Mask(VSX) Var(rs6000_isa_flags)
 199 Use vector/scalar (VSX) instructions.
 200
 201 mvsx-align-128
 202 Target Undocumented Var(TARGET_VSX_ALIGN_128) Save
 203 ; If -mvsx, set alignment to 128 bits instead of 32/64
 204
 205 mallow-movmisalign
 206 Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
 207 ; Allow the movmisalign in DF/DI vectors
 208
 209 mefficient-unaligned-vsx
 210 Target Undocumented Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
 211 ; Consider unaligned VSX vector and fp accesses to be efficient
 212
 213 msched-groups
 214 Target Undocumented Var(TARGET_SCHED_GROUPS) Init(-1) Save
 215 ; Explicitly set rs6000_sched_groups
 216
 217 malways-hint
 218 Target Undocumented Var(TARGET_ALWAYS_HINT) Init(-1) Save
 219 ; Explicitly set rs6000_always_hint
 220
 221 malign-branch-targets
 222 Target Undocumented Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
 223 ; Explicitly set rs6000_align_branch_targets
 224
 225 mno-update
 226 Target RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
 227 Do not generate load/store with update instructions.
 228
 229 mupdate
 230 Target RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
 231 Generate load/store with update instructions.
 232
 233 msingle-pic-base
 234 Target Var(TARGET_SINGLE_PIC_BASE) Init(0)
 235 Do not load the PIC register in function prologues.
 236
 237 mavoid-indexed-addresses
 238 Target Var(TARGET_AVOID_XFORM) Init(-1) Save
 239 Avoid generation of indexed load/store instructions when possible.
 240
 241 msched-epilog
 242 Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
 243
 244 msched-prolog
 245 Target Var(TARGET_SCHED_PROLOG) Save
 246 Schedule the start and end of the procedure.
 247
 248 maix-struct-return
 249 Target RejectNegative Var(aix_struct_return) Save
 250 Return all structures in memory (AIX default).
 251
 252 msvr4-struct-return
 253 Target RejectNegative Var(aix_struct_return,0) Save
 254 Return small structures in registers (SVR4 default).
 255
 256 mxl-compat
 257 Target Var(TARGET_XL_COMPAT) Save
 258 Conform more closely to IBM XLC semantics.
 259
 260 mrecip
 261 Target
 262 Generate software reciprocal divide and square root for better throughput.
 263
 264 mrecip=
 265 Target RejectNegative Joined Var(rs6000_recip_name)
 266 Generate software reciprocal divide and square root for better throughput.
 267
 268 mrecip-precision
 269 Target Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
 270 Assume that the reciprocal estimate instructions provide more accuracy.
 271
 272 mno-fp-in-toc
 273 Target RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
 274 Do not place floating point constants in TOC.
 275
 276 mfp-in-toc
 277 Target RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
 278 Place floating point constants in TOC.
 279
 280 mno-sum-in-toc
 281 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
 282 Do not place symbol+offset constants in TOC.
 283
 284 msum-in-toc
 285 Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
 286 Place symbol+offset constants in TOC.
 287
 288 ;  Output only one TOC entry per module.  Normally linking fails if
 289 ;   there are more than 16K unique variables/constants in an executable.  With
 290 ;   this option, linking fails only if there are more than 16K modules, or
 291 ;   if there are more than 16K unique variables/constant in a single module.
 292 ;
 293 ;   This is at the cost of having 2 extra loads and one extra store per
 294 ;   function, and one less allocable register.
 295 mminimal-toc
 296 Target Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
 297 Use only one TOC entry per procedure.
 298
 299 mfull-toc
 300 Target
 301 Put everything in the regular TOC.
 302
 303 mvrsave
 304 Target Var(TARGET_ALTIVEC_VRSAVE) Save
 305 Generate VRSAVE instructions when generating AltiVec code.
 306
 307 mvrsave=no
 308 Target RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead)
 309 Deprecated option.  Use -mno-vrsave instead.
 310
 311 mvrsave=yes
 312 Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead)
 313 Deprecated option.  Use -mvrsave instead.
 314
 315 mblock-move-inline-limit=
 316 Target Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
 317 Max number of bytes to move inline.
 318
 319 mblock-ops-unaligned-vsx
 320 Target Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags)
 321 Generate unaligned VSX load/store for inline expansion of memcpy/memmove.
 322
 323 mblock-ops-vector-pair
 324 Target Undocumented Mask(BLOCK_OPS_VECTOR_PAIR) Var(rs6000_isa_flags)
 325 Generate unaligned VSX vector pair load/store for inline expansion of memcpy/memmove.
 326
 327 mblock-compare-inline-limit=
 328 Target Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save
 329 Max number of bytes to compare without loops.
 330
 331 mblock-compare-inline-loop-limit=
 332 Target Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save
 333 Max number of bytes to compare with loops.
 334
 335 mstring-compare-inline-limit=
 336 Target Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save
 337 Max number of bytes to compare.
 338
 339 misel
 340 Target Mask(ISEL) Var(rs6000_isa_flags)
 341 Generate isel instructions.
 342
 343 mdebug=
 344 Target RejectNegative Joined
 345 -mdebug=        Enable debug output.
 346
 347 ; Altivec ABI
 348 mabi=altivec
 349 Target RejectNegative Var(rs6000_altivec_abi) Save
 350 Use the AltiVec ABI extensions.
 351
 352 mabi=no-altivec
 353 Target RejectNegative Var(rs6000_altivec_abi, 0)
 354 Do not use the AltiVec ABI extensions.
 355
 356 ; AIX Extended vector ABI
 357 mabi=vec-extabi
 358 Target RejectNegative Var(rs6000_aix_extabi, 1) Save
 359 Use the AIX Vector Extended ABI.
 360
 361 mabi=vec-default
 362 Target RejectNegative Var(rs6000_aix_extabi, 0)
 363 Do not use the AIX Vector Extended ABI.
 364
 365 ; PPC64 Linux ELF ABI
 366 mabi=elfv1
 367 Target RejectNegative Var(rs6000_elf_abi, 1) Save
 368 Use the ELFv1 ABI.
 369
 370 mabi=elfv2
 371 Target RejectNegative Var(rs6000_elf_abi, 2)
 372 Use the ELFv2 ABI.
 373
 374 ; These are here for testing during development only, do not document
 375 ; in the manual please.
 376
 377 ; If we want Darwin's struct-by-value-in-regs ABI.
 378 mabi=d64
 379 Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
 380
 381 mabi=d32
 382 Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
 383
 384 mabi=ieeelongdouble
 385 Target RejectNegative Var(rs6000_ieeequad) Save
 386
 387 mabi=ibmlongdouble
 388 Target RejectNegative Var(rs6000_ieeequad, 0)
 389
 390 mcpu=
 391 Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
 392 -mcpu=  Use features of and schedule code for given CPU.
 393
 394 mtune=
 395 Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
 396 -mtune= Schedule code for given CPU.
 397
 398 mtraceback=
 399 Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
 400 -mtraceback=[full,part,no]      Select type of traceback table.
 401
 402 Enum
 403 Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
 404
 405 EnumValue
 406 Enum(rs6000_traceback_type) String(full) Value(traceback_full)
 407
 408 EnumValue
 409 Enum(rs6000_traceback_type) String(part) Value(traceback_part)
 410
 411 EnumValue
 412 Enum(rs6000_traceback_type) String(no) Value(traceback_none)
 413
 414 mlongcall
 415 Target Var(rs6000_default_long_calls) Save
 416 Avoid all range limits on call instructions.
 417
 418 ; This option existed in the past, but now is always on.
 419 mgen-cell-microcode
 420 Target RejectNegative Undocumented Ignore
 421
 422 mwarn-altivec-long
 423 Target Var(rs6000_warn_altivec_long) Init(1) Save
 424 Warn about deprecated 'vector long ...' AltiVec type usage.
 425
 426 mlong-double-
 427 Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
 428 Use -mlong-double-64 for 64-bit IEEE floating point format.  Use
 429 -mlong-double-128 for 128-bit floating point format (either IEEE or IBM).
 430
 431 ; This option existed in the past, but now is always on.
 432 mlra
 433 Target RejectNegative Undocumented Ignore
 434
 435 msched-costly-dep=
 436 Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
 437 Determine which dependences between insns are considered costly.
 438
 439 minsert-sched-nops=
 440 Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
 441 Specify which post scheduling nop insertion scheme to apply.
 442
 443 malign-
 444 Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
 445 Specify alignment of structure fields default/natural.
 446
 447 Enum
 448 Name(rs6000_alignment_flags) Type(unsigned char)
 449 Valid arguments to -malign-:
 450
 451 EnumValue
 452 Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
 453
 454 EnumValue
 455 Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
 456
 457 mprioritize-restricted-insns=
 458 Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
 459 Specify scheduling priority for dispatch slot restricted insns.
 460
 461 mpointers-to-nested-functions
 462 Target Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
 463 Use r11 to hold the static link in calls to functions via pointers.
 464
 465 msave-toc-indirect
 466 Target Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
 467 Save the TOC in the prologue for indirect calls rather than inline.
 468
 469 ; This option existed in the past, but now is always the same as -mvsx.
 470 mvsx-timode
 471 Target RejectNegative Undocumented Ignore
 472
 473 mpower8-fusion
 474 Target Mask(P8_FUSION) Var(rs6000_isa_flags)
 475 Fuse certain integer operations together for better performance on power8.
 476
 477 mpower8-fusion-sign
 478 Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
 479 Allow sign extension in fusion operations.
 480
 481 mpower8-vector
 482 Target Undocumented Mask(P8_VECTOR) Var(rs6000_isa_flags) WarnRemoved
 483 Use vector and scalar instructions added in ISA 2.07.
 484
 485 mpower10-fusion
 486 Target Undocumented Mask(P10_FUSION) Var(rs6000_isa_flags)
 487 Fuse certain integer operations together for better performance on power10.
 488
 489 mcrypto
 490 Target Mask(CRYPTO) Var(rs6000_isa_flags)
 491 Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
 492
 493 mdirect-move
 494 Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) WarnRemoved
 495
 496 mhtm
 497 Target Mask(HTM) Var(rs6000_isa_flags)
 498 Use ISA 2.07 transactional memory (HTM) instructions.
 499
 500 mquad-memory
 501 Target Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
 502 Generate the quad word memory instructions (lq/stq).
 503
 504 mquad-memory-atomic
 505 Target Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
 506 Generate the quad word memory atomic instructions (lqarx/stqcx).
 507
 508 mcompat-align-parm
 509 Target Var(rs6000_compat_align_parm) Init(0) Save
 510 Generate aggregate parameter passing code with at most 64-bit alignment.
 511
 512 moptimize-swaps
 513 Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
 514 Analyze and remove doubleword swaps from VSX computations.
 515
 516 munroll-only-small-loops
 517 Target Undocumented Var(unroll_only_small_loops) Init(0) Save
 518 ; Use conservative small loop unrolling.
 519
 520 mpower9-misc
 521 Target Undocumented Mask(P9_MISC) Var(rs6000_isa_flags)
 522 Use certain scalar instructions added in ISA 3.0.
 523
 524 mpower9-vector
 525 Target Undocumented Mask(P9_VECTOR) Var(rs6000_isa_flags) WarnRemoved
 526 Use vector instructions added in ISA 3.0.
 527
 528 mpower9-minmax
 529 Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
 530 Use the new min/max instructions defined in ISA 3.0.
 531
 532 mmodulo
 533 Target Undocumented Mask(MODULO) Var(rs6000_isa_flags)
 534 Generate the integer modulo instructions.
 535
 536 mfloat128
 537 Target Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
 538 Enable IEEE 128-bit floating point via the __float128 keyword.
 539
 540 mfloat128-hardware
 541 Target Mask(FLOAT128_HW) Var(rs6000_isa_flags)
 542 Enable using IEEE 128-bit floating point instructions.
 543
 544 mfloat128-convert
 545 Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
 546 Enable default conversions between __float128 & long double.
 547
 548 mstack-protector-guard=
 549 Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
 550 Use given stack-protector guard.
 551
 552 Enum
 553 Name(stack_protector_guard) Type(enum stack_protector_guard)
 554 Valid arguments to -mstack-protector-guard=:
 555
 556 EnumValue
 557 Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
 558
 559 EnumValue
 560 Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
 561
 562 mstack-protector-guard-reg=
 563 Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str)
 564 Use the given base register for addressing the stack-protector guard.
 565
 566 TargetVariable
 567 int rs6000_stack_protector_guard_reg = 0
 568
 569 mstack-protector-guard-offset=
 570 Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str)
 571 Use the given offset for addressing the stack-protector guard.
 572
 573 TargetVariable
 574 long rs6000_stack_protector_guard_offset = 0
 575
 576 ;; -mno-speculate-indirect-jumps adds deliberate misprediction to indirect
 577 ;; branches via the CTR.
 578 mspeculate-indirect-jumps
 579 Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
 580
 581 mpower10
 582 Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved
 583
 584 mpower11
 585 Target Undocumented Mask(POWER11) Var(rs6000_isa_flags) Warn(Do not use %<-mpower11>)
 586
 587 mprefixed
 588 Target Mask(PREFIXED) Var(rs6000_isa_flags)
 589 Generate (do not generate) prefixed memory instructions.
 590
 591 mpcrel
 592 Target Mask(PCREL) Var(rs6000_isa_flags)
 593 Generate (do not generate) pc-relative memory addressing.
 594
 595 mpcrel-opt
 596 Target Undocumented Mask(PCREL_OPT) Var(rs6000_isa_flags)
 597 Generate (do not generate) pc-relative memory optimizations for externals.
 598
 599 mmma
 600 Target Mask(MMA) Var(rs6000_isa_flags)
 601 Generate (do not generate) MMA instructions.
 602
 603 mrelative-jumptables
 604 Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
 605
 606 mrop-protect
 607 Target Var(rs6000_rop_protect) Init(0)
 608 Enable instructions that guard against return-oriented programming attacks.
 609
 610 mprivileged
 611 Target Var(rs6000_privileged) Init(0)
 612 Generate code that will run in privileged state.
 613
 614 msplat-word-constant
 615 Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save
 616 Generate (do not generate) code that uses the XXSPLTIW instruction.
 617
 618 msplat-float-constant
 619 Target Var(TARGET_SPLAT_FLOAT_CONSTANT) Init(1) Save
 620 Generate (do not generate) code that uses the XXSPLTIDP instruction.
 621
 622 mieee128-constant
 623 Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
 624 Generate (do not generate) code that uses the LXVKQ instruction.
 625
 626 ; Documented parameters
 627
 628 -param=rs6000-vect-unroll-limit=
 629 Target Joined UInteger Var(rs6000_vect_unroll_limit) Init(4) IntegerRange(1, 64) Param
 630 Used to limit unroll factor which indicates how much the autovectorizer may
 631 unroll a loop.  The default value is 4.
 632
 633 ; Undocumented parameters
 634 -param=rs6000-density-pct-threshold=
 635 Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
 636 When costing for loop vectorization, we probably need to penalize the loop body
 637 cost if the existing cost model may not adequately reflect delays from
 638 unavailable vector resources.  We collect the cost for vectorized statements
 639 and non-vectorized statements separately, check the proportion of vec_cost to
 640 total cost of vec_cost and non vec_cost, and penalize only if the proportion
 641 exceeds the threshold specified by this parameter.  The default value is 85.
 642
 643 -param=rs6000-density-size-threshold=
 644 Target Undocumented Joined UInteger Var(rs6000_density_size_threshold) Init(70) IntegerRange(0, 1000) Param
 645 Like parameter rs6000-density-pct-threshold, we also check the total sum of
 646 vec_cost and non vec_cost, and penalize only if the sum exceeds the threshold
 647 specified by this parameter.  The default value is 70.
 648
 649 -param=rs6000-density-penalty=
 650 Target Undocumented Joined UInteger Var(rs6000_density_penalty) Init(10) IntegerRange(0, 1000) Param
 651 When both heuristics with rs6000-density-pct-threshold and
 652 rs6000-density-size-threshold are satisfied, we decide to penalize the loop
 653 body cost by the value which is specified by this parameter.  The default
 654 value is 10.
 655
 656 -param=rs6000-density-load-pct-threshold=
 657 Target Undocumented Joined UInteger Var(rs6000_density_load_pct_threshold) Init(45) IntegerRange(0, 100) Param
 658 When costing for loop vectorization, we probably need to penalize the loop body
 659 cost by accounting for excess strided or elementwise loads.  We collect the
 660 numbers for general statements and load statements according to the information
 661 for statements to be vectorized, check the proportion of load statements, and
 662 penalize only if the proportion exceeds the threshold specified by this
 663 parameter.  The default value is 45.
 664
 665 -param=rs6000-density-load-num-threshold=
 666 Target Undocumented Joined UInteger Var(rs6000_density_load_num_threshold) Init(20) IntegerRange(0, 1000) Param
 667 Like parameter rs6000-density-load-pct-threshold, we also check if the total
 668 number of load statements exceeds the threshold specified by this parameter,
 669 and penalize only if it's satisfied.  The default value is 20.
 670
 671 -param=rs6000-vect-unroll-issue=
 672 Target Undocumented Joined UInteger Var(rs6000_vect_unroll_issue) Init(4) IntegerRange(1, 128) Param
 673 Indicate how many non memory access vector instructions can be issued per
 674 cycle, it's used in unroll factor determination for autovectorizer.  The
 675 default value is 4.
 676
 677 -param=rs6000-vect-unroll-reduc-threshold=
 678 Target Undocumented Joined UInteger Var(rs6000_vect_unroll_reduc_threshold) Init(1) Param
 679 When reduction factor computed for a loop exceeds the threshold specified by
 680 this parameter, prefer to unroll this loop.  The default value is 1.