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1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
21
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 \f
24 ;; Define an insn type attribute. This is used in function unit delay
25 ;; computations.
26 (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
27 (const_string "integer"))
28
29 ;; Length (in bytes).
30 (define_attr "length" ""
31 (if_then_else (eq_attr "type" "branch")
32 (if_then_else (and (ge (minus (pc) (match_dup 0))
33 (const_int -32768))
34 (lt (minus (pc) (match_dup 0))
35 (const_int 32767)))
36 (const_int 8)
37 (const_int 12))
38 (const_int 4)))
39
40 ;; Processor type -- this attribute must exactly match the processor_type
41 ;; enumeration in rs6000.h.
42
43 (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc602,ppc603,ppc604,ppc620"
44 (const (symbol_ref "rs6000_cpu_attr")))
45
46 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
47 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
48
49 ; Load/Store Unit -- POWER/2 and pure PowerPC only
50 ; (POWER and 601 use Integer Unit)
51 (define_function_unit "lsu" 1 0
52 (and (eq_attr "type" "load")
53 (eq_attr "cpu" "mpccore,ppc602,ppc603,ppc604,ppc620"))
54 2 1)
55
56 (define_function_unit "lsu" 1 0
57 (and (eq_attr "type" "fpload")
58 (eq_attr "cpu" "ppc604,ppc620"))
59 3 1)
60
61 (define_function_unit "lsu" 1 0
62 (and (eq_attr "type" "fpload")
63 (eq_attr "cpu" "mpccore,ppc602,ppc603"))
64 2 1)
65
66 (define_function_unit "iu" 1 0
67 (and (eq_attr "type" "load")
68 (eq_attr "cpu" "rios1,ppc601,ppc403"))
69 2 1)
70
71 (define_function_unit "iu" 1 0
72 (and (eq_attr "type" "fpload")
73 (eq_attr "cpu" "rios1,ppc601"))
74 2 0)
75
76 ; Integer Unit (RIOS1, PPC601, PPC603)
77 ; Trivial operations take one cycle which need not be listed here.
78 (define_function_unit "iu" 1 0
79 (and (eq_attr "type" "imul")
80 (eq_attr "cpu" "rios1"))
81 3 3)
82
83 (define_function_unit "iu" 1 0
84 (and (eq_attr "type" "imul")
85 (eq_attr "cpu" "ppc403"))
86 4 4)
87
88 (define_function_unit "iu" 1 0
89 (and (eq_attr "type" "imul")
90 (eq_attr "cpu" "ppc601,ppc602,ppc603"))
91 5 5)
92
93 (define_function_unit "iu" 1 0
94 (and (eq_attr "type" "idiv")
95 (eq_attr "cpu" "rios1"))
96 19 19)
97
98 (define_function_unit "iu" 1 0
99 (and (eq_attr "type" "idiv")
100 (eq_attr "cpu" "ppc601"))
101 36 36)
102
103 (define_function_unit "iu" 1 0
104 (and (eq_attr "type" "idiv")
105 (eq_attr "cpu" "ppc403"))
106 33 33)
107
108 (define_function_unit "iu" 1 0
109 (and (eq_attr "type" "idiv")
110 (eq_attr "cpu" "ppc602,ppc603"))
111 37 36)
112
113 ; RIOS2 has two integer units: a primary one which can perform all
114 ; operations and a secondary one which is fed in lock step with the first
115 ; and can perform "simple" integer operations.
116 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
117 ; for the complex insns.
118 (define_function_unit "iu2" 2 0
119 (and (eq_attr "type" "integer")
120 (eq_attr "cpu" "rios2"))
121 1 0)
122
123 (define_function_unit "iu2" 2 0
124 (and (eq_attr "type" "imul")
125 (eq_attr "cpu" "rios2"))
126 2 2)
127
128 (define_function_unit "iu2" 2 0
129 (and (eq_attr "type" "idiv")
130 (eq_attr "cpu" "rios2"))
131 13 13)
132
133 (define_function_unit "imuldiv" 1 0
134 (and (eq_attr "type" "imul")
135 (eq_attr "cpu" "rios2"))
136 2 2)
137
138
139 (define_function_unit "imuldiv" 1 0
140 (and (eq_attr "type" "idiv")
141 (eq_attr "cpu" "rios2"))
142 13 13)
143
144 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
145 ; Divide latency varies greatly from 2-11, use 6 as average
146 (define_function_unit "imuldiv" 1 0
147 (and (eq_attr "type" "imul")
148 (eq_attr "cpu" "mpccore"))
149 2 1)
150
151 (define_function_unit "imuldiv" 1 0
152 (and (eq_attr "type" "idiv")
153 (eq_attr "cpu" "mpccore"))
154 6 6)
155
156 ; PPC604 has two units that perform integer operations
157 ; and one unit for divide/multiply operations (and move
158 ; from/to spr).
159 (define_function_unit "iu2" 2 0
160 (and (eq_attr "type" "integer")
161 (eq_attr "cpu" "ppc604,ppc620"))
162 1 1
163 [(eq_attr "type" "imul,idiv")])
164
165 (define_function_unit "imuldiv" 1 0
166 (and (eq_attr "type" "imul")
167 (eq_attr "cpu" "ppc604,ppc620"))
168 4 2
169 [(eq_attr "type" "integer")])
170
171 (define_function_unit "imuldiv" 1 0
172 (and (eq_attr "type" "idiv")
173 (eq_attr "cpu" "ppc604,ppc620"))
174 20 19
175 [(eq_attr "type" "integer")])
176
177 ; compare is done on integer unit, but feeds insns which
178 ; execute on the branch unit. Ready-delay of the compare
179 ; on the branch unit is large (3-5 cycles). On the iu/fpu
180 ; it is 1. One drawback is that the compare will also be
181 ; assigned to the bpu, but this inaccuracy is worth for being
182 ; able to fill the compare-branch delay, with insns on iu/fpu.
183 (define_function_unit "iu" 1 0
184 (and (eq_attr "type" "compare")
185 (eq_attr "cpu" "rios1,mpccore,ppc601"))
186 1 1)
187
188 (define_function_unit "iu2" 2 0
189 (and (eq_attr "type" "compare")
190 (eq_attr "cpu" "rios2"))
191 1 1)
192
193 (define_function_unit "bpu" 1 0
194 (and (eq_attr "type" "compare")
195 (eq_attr "cpu" "rios1,rios2,ppc403,mpccore,ppc601,ppc603,ppc604,ppc620"))
196 4 1)
197
198 ; different machines have different compare timings
199 ; in ppc604, compare is done on the one of the two
200 ; main integer units.
201 (define_function_unit "iu2" 2 0
202 (and (eq_attr "type" "compare")
203 (eq_attr "cpu" "ppc604,ppc620"))
204 1 1)
205
206 (define_function_unit "bpu" 1 0
207 (eq_attr "type" "delayed_compare")
208 5 0)
209
210 ; fp compare uses fp unit
211 (define_function_unit "fpu" 1 0
212 (and (eq_attr "type" "fpcompare")
213 (eq_attr "cpu" "rios1"))
214 8 1)
215
216 ; rios1 and rios2 have different fpcompare delays
217 (define_function_unit "fpu2" 2 0
218 (and (eq_attr "type" "fpcompare")
219 (eq_attr "cpu" "rios2"))
220 5 1)
221
222 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
223 ; the integer unit
224 ; here we do not define delays, just occupy the unit. The dependencies
225 ; will be signed by the fpcompare definition in the fpu.
226 (define_function_unit "iu" 1 0
227 (and (eq_attr "type" "fpcompare")
228 (eq_attr "cpu" "ppc601,ppc602,ppc603"))
229 0 2)
230
231 ; fp compare uses fp unit
232 (define_function_unit "fpu" 1 0
233 (and (eq_attr "type" "fpcompare")
234 (eq_attr "cpu" "ppc601,ppc602,ppc603,ppc604,ppc620"))
235 5 1)
236
237 (define_function_unit "fpu" 1 0
238 (and (eq_attr "type" "fpcompare")
239 (eq_attr "cpu" "mpccore"))
240 1 1)
241
242 (define_function_unit "bpu" 1 0
243 (and (eq_attr "type" "mtjmpr")
244 (eq_attr "cpu" "rios1,rios2"))
245 5 0)
246
247 (define_function_unit "bpu" 1 0
248 (and (eq_attr "type" "mtjmpr")
249 (eq_attr "cpu" "ppc403,mpccore,ppc601,ppc602,ppc603,ppc604,ppc620"))
250 4 0)
251
252 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
253 (define_function_unit "bpu" 1 0
254 (eq_attr "type" "jmpreg")
255 1 0)
256
257 (define_function_unit "bpu" 1 0
258 (eq_attr "type" "branch")
259 1 0)
260
261 ; Floating Point Unit
262 (define_function_unit "fpu" 1 0
263 (and (eq_attr "type" "fp,dmul")
264 (eq_attr "cpu" "rios1"))
265 2 0)
266
267 (define_function_unit "fpu" 1 0
268 (and (eq_attr "type" "fp")
269 (eq_attr "cpu" "mpccore"))
270 4 4)
271
272 (define_function_unit "fpu" 1 0
273 (and (eq_attr "type" "fp")
274 (eq_attr "cpu" "ppc601"))
275 4 0)
276
277 (define_function_unit "fpu" 1 0
278 (and (eq_attr "type" "fp")
279 (eq_attr "cpu" "ppc602,ppc603,ppc604,ppc620"))
280 3 1)
281
282 (define_function_unit "fpu" 1 0
283 (and (eq_attr "type" "dmul")
284 (eq_attr "cpu" "mpccore"))
285 5 5)
286
287 (define_function_unit "fpu" 1 0
288 (and (eq_attr "type" "dmul")
289 (eq_attr "cpu" "ppc601"))
290 5 2)
291
292 ; is this true?
293 (define_function_unit "fpu" 1 0
294 (and (eq_attr "type" "dmul")
295 (eq_attr "cpu" "ppc602,ppc603"))
296 4 2)
297
298 (define_function_unit "fpu" 1 0
299 (and (eq_attr "type" "dmul")
300 (eq_attr "cpu" "ppc604,ppc620"))
301 3 1)
302
303 (define_function_unit "fpu" 1 0
304 (and (eq_attr "type" "sdiv,ddiv")
305 (eq_attr "cpu" "rios1"))
306 19 19)
307
308 (define_function_unit "fpu" 1 0
309 (and (eq_attr "type" "sdiv")
310 (eq_attr "cpu" "ppc601"))
311 17 17)
312
313 (define_function_unit "fpu" 1 0
314 (and (eq_attr "type" "sdiv")
315 (eq_attr "cpu" "mpccore"))
316 10 10)
317
318 (define_function_unit "fpu" 1 0
319 (and (eq_attr "type" "sdiv")
320 (eq_attr "cpu" "ppc602,ppc603,ppc604,ppc620"))
321 18 18)
322
323 (define_function_unit "fpu" 1 0
324 (and (eq_attr "type" "ddiv")
325 (eq_attr "cpu" "mpccore"))
326 17 17)
327
328 (define_function_unit "fpu" 1 0
329 (and (eq_attr "type" "ddiv")
330 (eq_attr "cpu" "ppc601,ppc604,ppc620"))
331 31 31)
332
333 (define_function_unit "fpu" 1 0
334 (and (eq_attr "type" "ddiv")
335 (eq_attr "cpu" "ppc602,ppc603"))
336 33 33)
337
338 (define_function_unit "fpu" 1 0
339 (and (eq_attr "type" "ssqrt")
340 (eq_attr "cpu" "ppc620"))
341 31 31)
342
343 (define_function_unit "fpu" 1 0
344 (and (eq_attr "type" "dsqrt")
345 (eq_attr "cpu" "ppc620"))
346 31 31)
347
348 ; RIOS2 has two symmetric FPUs.
349 (define_function_unit "fpu2" 2 0
350 (and (eq_attr "type" "fp")
351 (eq_attr "cpu" "rios2"))
352 2 0)
353
354 (define_function_unit "fpu2" 2 0
355 (and (eq_attr "type" "dmul")
356 (eq_attr "cpu" "rios2"))
357 2 0)
358
359 (define_function_unit "fpu2" 2 0
360 (and (eq_attr "type" "sdiv,ddiv")
361 (eq_attr "cpu" "rios2"))
362 17 17)
363
364 (define_function_unit "fpu2" 2 0
365 (and (eq_attr "type" "ssqrt,dsqrt")
366 (eq_attr "cpu" "rios2"))
367 26 26)
368
369 \f
370 ;; Start with fixed-point load and store insns. Here we put only the more
371 ;; complex forms. Basic data transfer is done later.
372
373 (define_expand "zero_extendqidi2"
374 [(set (match_operand:DI 0 "gpc_reg_operand" "")
375 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
376 "TARGET_POWERPC64"
377 "")
378
379 (define_insn ""
380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
381 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
382 "TARGET_POWERPC64"
383 "@
384 lbz%U1%X1 %0,%1
385 rldicl %0,%1,0,56"
386 [(set_attr "type" "load,*")])
387
388 (define_insn ""
389 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
390 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
391 (const_int 0)))
392 (clobber (match_scratch:DI 2 "=r"))]
393 "TARGET_POWERPC64"
394 "rldicl. %2,%1,0,56"
395 [(set_attr "type" "compare")])
396
397 (define_insn ""
398 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
399 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
400 (const_int 0)))
401 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
402 (zero_extend:DI (match_dup 1)))]
403 "TARGET_POWERPC64"
404 "rldicl. %0,%1,0,56"
405 [(set_attr "type" "compare")])
406
407 (define_insn "extendqidi2"
408 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
409 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
410 "TARGET_POWERPC64"
411 "extsb %0,%1")
412
413 (define_insn ""
414 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
415 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
416 (const_int 0)))
417 (clobber (match_scratch:DI 2 "=r"))]
418 "TARGET_POWERPC64"
419 "extsb. %2,%1"
420 [(set_attr "type" "compare")])
421
422 (define_insn ""
423 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
424 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
425 (const_int 0)))
426 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
427 (sign_extend:DI (match_dup 1)))]
428 "TARGET_POWERPC64"
429 "extsb. %0,%1"
430 [(set_attr "type" "compare")])
431
432 (define_expand "zero_extendhidi2"
433 [(set (match_operand:DI 0 "gpc_reg_operand" "")
434 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
435 "TARGET_POWERPC64"
436 "")
437
438 (define_insn ""
439 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
440 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
441 "TARGET_POWERPC64"
442 "@
443 lhz%U1%X1 %0,%1
444 rldicl %0,%1,0,48"
445 [(set_attr "type" "load,*")])
446
447 (define_insn ""
448 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
449 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
450 (const_int 0)))
451 (clobber (match_scratch:DI 2 "=r"))]
452 "TARGET_POWERPC64"
453 "rldicl. %2,%1,0,48"
454 [(set_attr "type" "compare")])
455
456 (define_insn ""
457 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
458 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
459 (const_int 0)))
460 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
461 (zero_extend:DI (match_dup 1)))]
462 "TARGET_POWERPC64"
463 "rldicl. %0,%1,0,48"
464 [(set_attr "type" "compare")])
465
466 (define_expand "extendhidi2"
467 [(set (match_operand:DI 0 "gpc_reg_operand" "")
468 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
469 "TARGET_POWERPC64"
470 "")
471
472 (define_insn ""
473 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
474 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
475 "TARGET_POWERPC64"
476 "@
477 lha%U1%X1 %0,%1
478 extsh %0,%1"
479 [(set_attr "type" "load,*")])
480
481 (define_insn ""
482 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
483 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
484 (const_int 0)))
485 (clobber (match_scratch:DI 2 "=r"))]
486 "TARGET_POWERPC64"
487 "extsh. %2,%1"
488 [(set_attr "type" "compare")])
489
490 (define_insn ""
491 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
492 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
493 (const_int 0)))
494 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
495 (sign_extend:DI (match_dup 1)))]
496 "TARGET_POWERPC64"
497 "extsh. %0,%1"
498 [(set_attr "type" "compare")])
499
500 (define_expand "zero_extendsidi2"
501 [(set (match_operand:DI 0 "gpc_reg_operand" "")
502 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
503 "TARGET_POWERPC64"
504 "")
505
506 (define_insn ""
507 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
508 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
509 "TARGET_POWERPC64"
510 "@
511 lwz%U1%X1 %0,%1
512 rldicl %0,%1,0,32"
513 [(set_attr "type" "load,*")])
514
515 (define_insn ""
516 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
517 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
518 (const_int 0)))
519 (clobber (match_scratch:DI 2 "=r"))]
520 "TARGET_POWERPC64"
521 "rldicl. %2,%1,0,32"
522 [(set_attr "type" "compare")])
523
524 (define_insn ""
525 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
526 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
527 (const_int 0)))
528 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
529 (zero_extend:DI (match_dup 1)))]
530 "TARGET_POWERPC64"
531 "rldicl. %0,%1,0,32"
532 [(set_attr "type" "compare")])
533
534 (define_expand "extendsidi2"
535 [(set (match_operand:DI 0 "gpc_reg_operand" "")
536 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
537 "TARGET_POWERPC64"
538 "")
539
540 (define_insn ""
541 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
542 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
543 "TARGET_POWERPC64"
544 "@
545 lwa%U1%X1 %0,%1
546 extsw %0,%1"
547 [(set_attr "type" "load,*")])
548
549 (define_insn ""
550 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
551 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
552 (const_int 0)))
553 (clobber (match_scratch:DI 2 "=r"))]
554 "TARGET_POWERPC64"
555 "extsw. %2,%1"
556 [(set_attr "type" "compare")])
557
558 (define_insn ""
559 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
560 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
561 (const_int 0)))
562 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
563 (sign_extend:DI (match_dup 1)))]
564 "TARGET_POWERPC64"
565 "extsw. %0,%1"
566 [(set_attr "type" "compare")])
567
568 (define_expand "zero_extendqisi2"
569 [(set (match_operand:SI 0 "gpc_reg_operand" "")
570 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
571 ""
572 "")
573
574 (define_insn ""
575 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
576 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
577 ""
578 "@
579 lbz%U1%X1 %0,%1
580 {rlinm|rlwinm} %0,%1,0,0xff"
581 [(set_attr "type" "load,*")])
582
583 (define_insn ""
584 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
585 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
586 (const_int 0)))
587 (clobber (match_scratch:SI 2 "=r"))]
588 ""
589 "{andil.|andi.} %2,%1,0xff"
590 [(set_attr "type" "compare")])
591
592 (define_insn ""
593 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
594 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
595 (const_int 0)))
596 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
597 (zero_extend:SI (match_dup 1)))]
598 ""
599 "{andil.|andi.} %0,%1,0xff"
600 [(set_attr "type" "compare")])
601
602 (define_expand "extendqisi2"
603 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
604 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
605 ""
606 "
607 {
608 if (TARGET_POWERPC)
609 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
610 else if (TARGET_POWER)
611 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
612 else
613 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
614 DONE;
615 }")
616
617 (define_insn "extendqisi2_ppc"
618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
619 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
620 "TARGET_POWERPC"
621 "extsb %0,%1")
622
623 (define_insn ""
624 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
625 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
626 (const_int 0)))
627 (clobber (match_scratch:SI 2 "=r"))]
628 "TARGET_POWERPC"
629 "extsb. %2,%1"
630 [(set_attr "type" "compare")])
631
632 (define_insn ""
633 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
634 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
635 (const_int 0)))
636 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
637 (sign_extend:SI (match_dup 1)))]
638 "TARGET_POWERPC"
639 "extsb. %0,%1"
640 [(set_attr "type" "compare")])
641
642 (define_expand "extendqisi2_power"
643 [(parallel [(set (match_dup 2)
644 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
645 (const_int 24)))
646 (clobber (scratch:SI))])
647 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
648 (ashiftrt:SI (match_dup 2)
649 (const_int 24)))
650 (clobber (scratch:SI))])]
651 "TARGET_POWER"
652 "
653 { operands[1] = gen_lowpart (SImode, operands[1]);
654 operands[2] = gen_reg_rtx (SImode); }")
655
656 (define_expand "extendqisi2_no_power"
657 [(set (match_dup 2)
658 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
659 (const_int 24)))
660 (set (match_operand:SI 0 "gpc_reg_operand" "")
661 (ashiftrt:SI (match_dup 2)
662 (const_int 24)))]
663 "! TARGET_POWER && ! TARGET_POWERPC"
664 "
665 { operands[1] = gen_lowpart (SImode, operands[1]);
666 operands[2] = gen_reg_rtx (SImode); }")
667
668 (define_expand "zero_extendqihi2"
669 [(set (match_operand:HI 0 "gpc_reg_operand" "")
670 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
671 ""
672 "")
673
674 (define_insn ""
675 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
676 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
677 ""
678 "@
679 lbz%U1%X1 %0,%1
680 {rlinm|rlwinm} %0,%1,0,0xff"
681 [(set_attr "type" "load,*")])
682
683 (define_insn ""
684 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
685 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
686 (const_int 0)))
687 (clobber (match_scratch:HI 2 "=r"))]
688 ""
689 "{andil.|andi.} %2,%1,0xff"
690 [(set_attr "type" "compare")])
691
692 (define_insn ""
693 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
694 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
695 (const_int 0)))
696 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
697 (zero_extend:HI (match_dup 1)))]
698 ""
699 "{andil.|andi.} %0,%1,0xff"
700 [(set_attr "type" "compare")])
701
702 (define_expand "extendqihi2"
703 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
704 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
705 ""
706 "
707 {
708 if (TARGET_POWERPC)
709 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
710 else if (TARGET_POWER)
711 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
712 else
713 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
714 DONE;
715 }")
716
717 (define_insn "extendqihi2_ppc"
718 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
719 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
720 "TARGET_POWERPC"
721 "extsb %0,%1")
722
723 (define_insn ""
724 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
725 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
726 (const_int 0)))
727 (clobber (match_scratch:HI 2 "=r"))]
728 "TARGET_POWERPC"
729 "extsb. %2,%1"
730 [(set_attr "type" "compare")])
731
732 (define_insn ""
733 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
734 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
735 (const_int 0)))
736 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
737 (sign_extend:HI (match_dup 1)))]
738 "TARGET_POWERPC"
739 "extsb. %0,%1"
740 [(set_attr "type" "compare")])
741
742 (define_expand "extendqihi2_power"
743 [(parallel [(set (match_dup 2)
744 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
745 (const_int 24)))
746 (clobber (scratch:SI))])
747 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
748 (ashiftrt:SI (match_dup 2)
749 (const_int 24)))
750 (clobber (scratch:SI))])]
751 "TARGET_POWER"
752 "
753 { operands[0] = gen_lowpart (SImode, operands[0]);
754 operands[1] = gen_lowpart (SImode, operands[1]);
755 operands[2] = gen_reg_rtx (SImode); }")
756
757 (define_expand "extendqihi2_no_power"
758 [(set (match_dup 2)
759 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
760 (const_int 24)))
761 (set (match_operand:HI 0 "gpc_reg_operand" "")
762 (ashiftrt:SI (match_dup 2)
763 (const_int 24)))]
764 "! TARGET_POWER && ! TARGET_POWERPC"
765 "
766 { operands[0] = gen_lowpart (SImode, operands[0]);
767 operands[1] = gen_lowpart (SImode, operands[1]);
768 operands[2] = gen_reg_rtx (SImode); }")
769
770 (define_expand "zero_extendhisi2"
771 [(set (match_operand:SI 0 "gpc_reg_operand" "")
772 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
773 ""
774 "")
775
776 (define_insn ""
777 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
778 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
779 ""
780 "@
781 lhz%U1%X1 %0,%1
782 {rlinm|rlwinm} %0,%1,0,0xffff"
783 [(set_attr "type" "load,*")])
784
785 (define_insn ""
786 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
787 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
788 (const_int 0)))
789 (clobber (match_scratch:SI 2 "=r"))]
790 ""
791 "{andil.|andi.} %2,%1,0xffff"
792 [(set_attr "type" "compare")])
793
794 (define_insn ""
795 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
796 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
797 (const_int 0)))
798 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
799 (zero_extend:SI (match_dup 1)))]
800 ""
801 "{andil.|andi.} %0,%1,0xffff"
802 [(set_attr "type" "compare")])
803
804 (define_expand "extendhisi2"
805 [(set (match_operand:SI 0 "gpc_reg_operand" "")
806 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
807 ""
808 "")
809
810 (define_insn ""
811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
812 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
813 ""
814 "@
815 lha%U1%X1 %0,%1
816 {exts|extsh} %0,%1"
817 [(set_attr "type" "load,*")])
818
819 (define_insn ""
820 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
821 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
822 (const_int 0)))
823 (clobber (match_scratch:SI 2 "=r"))]
824 ""
825 "{exts.|extsh.} %2,%1"
826 [(set_attr "type" "compare")])
827
828 (define_insn ""
829 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
830 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
831 (const_int 0)))
832 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
833 (sign_extend:SI (match_dup 1)))]
834 ""
835 "{exts.|extsh.} %0,%1"
836 [(set_attr "type" "compare")])
837 \f
838 ;; Fixed-point arithmetic insns.
839
840 ;; Discourage ai/addic because of carry but provide it in an alternative
841 ;; allowing register zero as source.
842 (define_insn "addsi3"
843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
844 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
845 (match_operand:SI 2 "add_operand" "r,I,I,J")))]
846 ""
847 "@
848 {cax|add} %0,%1,%2
849 {cal %0,%2(%1)|addi %0,%1,%2}
850 {ai|addic} %0,%1,%2
851 {cau|addis} %0,%1,%u2")
852
853 (define_insn ""
854 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
855 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
856 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
857 (const_int 0)))
858 (clobber (match_scratch:SI 3 "=r,r"))]
859 ""
860 "@
861 {cax.|add.} %3,%1,%2
862 {ai.|addic.} %3,%1,%2"
863 [(set_attr "type" "compare")])
864
865 (define_insn ""
866 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
867 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
868 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
869 (const_int 0)))
870 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
871 (plus:SI (match_dup 1) (match_dup 2)))]
872 ""
873 "@
874 {cax.|add.} %0,%1,%2
875 {ai.|addic.} %0,%1,%2"
876 [(set_attr "type" "compare")])
877
878 ;; Split an add that we can't do in one insn into two insns, each of which
879 ;; does one 16-bit part. This is used by combine. Note that the low-order
880 ;; add should be last in case the result gets used in an address.
881
882 (define_split
883 [(set (match_operand:SI 0 "gpc_reg_operand" "")
884 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
885 (match_operand:SI 2 "non_add_cint_operand" "")))]
886 ""
887 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
888 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
889 "
890 {
891 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
892 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
893
894 if (low & 0x8000)
895 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
896
897 operands[3] = GEN_INT (high);
898 operands[4] = GEN_INT (low);
899 }")
900
901 (define_insn "one_cmplsi2"
902 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
903 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
904 ""
905 "nor %0,%1,%1")
906
907 (define_insn ""
908 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
909 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
910 (const_int 0)))
911 (clobber (match_scratch:SI 2 "=r"))]
912 ""
913 "nor. %2,%1,%1"
914 [(set_attr "type" "compare")])
915
916 (define_insn ""
917 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
918 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
919 (const_int 0)))
920 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
921 (not:SI (match_dup 1)))]
922 ""
923 "nor. %0,%2,%1"
924 [(set_attr "type" "compare")])
925
926 (define_insn ""
927 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
928 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
929 (match_operand:SI 2 "gpc_reg_operand" "r")))]
930 "! TARGET_POWERPC"
931 "{sf%I1|subf%I1c} %0,%2,%1")
932
933 (define_insn ""
934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
935 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
936 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
937 "TARGET_POWERPC"
938 "@
939 subf %0,%2,%1
940 subfic %0,%2,%1")
941
942 (define_insn ""
943 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
944 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
945 (match_operand:SI 2 "gpc_reg_operand" "r"))
946 (const_int 0)))
947 (clobber (match_scratch:SI 3 "=r"))]
948 "! TARGET_POWERPC"
949 "{sf.|subfc.} %3,%2,%1"
950 [(set_attr "type" "compare")])
951
952 (define_insn ""
953 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
954 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
955 (match_operand:SI 2 "gpc_reg_operand" "r"))
956 (const_int 0)))
957 (clobber (match_scratch:SI 3 "=r"))]
958 "TARGET_POWERPC"
959 "subf. %3,%2,%1"
960 [(set_attr "type" "compare")])
961
962 (define_insn ""
963 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
964 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
965 (match_operand:SI 2 "gpc_reg_operand" "r"))
966 (const_int 0)))
967 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
968 (minus:SI (match_dup 1) (match_dup 2)))]
969 "! TARGET_POWERPC"
970 "{sf.|subfc.} %0,%2,%1"
971 [(set_attr "type" "compare")])
972
973 (define_insn ""
974 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
975 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
976 (match_operand:SI 2 "gpc_reg_operand" "r"))
977 (const_int 0)))
978 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
979 (minus:SI (match_dup 1) (match_dup 2)))]
980 "TARGET_POWERPC"
981 "subf. %0,%2,%1"
982 [(set_attr "type" "compare")])
983
984 (define_expand "subsi3"
985 [(set (match_operand:SI 0 "gpc_reg_operand" "")
986 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
987 (match_operand:SI 2 "reg_or_cint_operand" "")))]
988 ""
989 "
990 {
991 if (GET_CODE (operands[2]) == CONST_INT)
992 {
993 emit_insn (gen_addsi3 (operands[0], operands[1],
994 negate_rtx (SImode, operands[2])));
995 DONE;
996 }
997 }")
998
999 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1000 ;; instruction and some auxiliary computations. Then we just have a single
1001 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1002 ;; combine.
1003
1004 (define_expand "sminsi3"
1005 [(set (match_dup 3)
1006 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1007 (match_operand:SI 2 "reg_or_short_operand" ""))
1008 (const_int 0)
1009 (minus:SI (match_dup 2) (match_dup 1))))
1010 (set (match_operand:SI 0 "gpc_reg_operand" "")
1011 (minus:SI (match_dup 2) (match_dup 3)))]
1012 "TARGET_POWER"
1013 "
1014 { operands[3] = gen_reg_rtx (SImode); }")
1015
1016 (define_split
1017 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1018 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1019 (match_operand:SI 2 "reg_or_short_operand" "")))
1020 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1021 "TARGET_POWER"
1022 [(set (match_dup 3)
1023 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1024 (const_int 0)
1025 (minus:SI (match_dup 2) (match_dup 1))))
1026 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1027 "")
1028
1029 (define_expand "smaxsi3"
1030 [(set (match_dup 3)
1031 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1032 (match_operand:SI 2 "reg_or_short_operand" ""))
1033 (const_int 0)
1034 (minus:SI (match_dup 2) (match_dup 1))))
1035 (set (match_operand:SI 0 "gpc_reg_operand" "")
1036 (plus:SI (match_dup 3) (match_dup 1)))]
1037 "TARGET_POWER"
1038 "
1039 { operands[3] = gen_reg_rtx (SImode); }")
1040
1041 (define_split
1042 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1043 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1044 (match_operand:SI 2 "reg_or_short_operand" "")))
1045 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1046 "TARGET_POWER"
1047 [(set (match_dup 3)
1048 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1049 (const_int 0)
1050 (minus:SI (match_dup 2) (match_dup 1))))
1051 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1052 "")
1053
1054 (define_expand "uminsi3"
1055 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1056 (match_dup 5)))
1057 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1058 (match_dup 5)))
1059 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1060 (const_int 0)
1061 (minus:SI (match_dup 4) (match_dup 3))))
1062 (set (match_operand:SI 0 "gpc_reg_operand" "")
1063 (minus:SI (match_dup 2) (match_dup 3)))]
1064 "TARGET_POWER"
1065 "
1066 {
1067 operands[3] = gen_reg_rtx (SImode);
1068 operands[4] = gen_reg_rtx (SImode);
1069 operands[5] = GEN_INT (-2147483647 - 1);
1070 }")
1071
1072 (define_expand "umaxsi3"
1073 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1074 (match_dup 5)))
1075 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1076 (match_dup 5)))
1077 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1078 (const_int 0)
1079 (minus:SI (match_dup 4) (match_dup 3))))
1080 (set (match_operand:SI 0 "gpc_reg_operand" "")
1081 (plus:SI (match_dup 3) (match_dup 1)))]
1082 "TARGET_POWER"
1083 "
1084 {
1085 operands[3] = gen_reg_rtx (SImode);
1086 operands[4] = gen_reg_rtx (SImode);
1087 operands[5] = GEN_INT (-2147483647 - 1);
1088 }")
1089
1090 (define_insn ""
1091 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1092 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1093 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1094 (const_int 0)
1095 (minus:SI (match_dup 2) (match_dup 1))))]
1096 "TARGET_POWER"
1097 "doz%I2 %0,%1,%2")
1098
1099 (define_insn ""
1100 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1101 (compare:CC
1102 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1103 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1104 (const_int 0)
1105 (minus:SI (match_dup 2) (match_dup 1)))
1106 (const_int 0)))
1107 (clobber (match_scratch:SI 3 "=r"))]
1108 "TARGET_POWER"
1109 "doz%I2. %3,%1,%2"
1110 [(set_attr "type" "delayed_compare")])
1111
1112 (define_insn ""
1113 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1114 (compare:CC
1115 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1116 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1117 (const_int 0)
1118 (minus:SI (match_dup 2) (match_dup 1)))
1119 (const_int 0)))
1120 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1121 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1122 (const_int 0)
1123 (minus:SI (match_dup 2) (match_dup 1))))]
1124 "TARGET_POWER"
1125 "doz%I2. %0,%1,%2"
1126 [(set_attr "type" "delayed_compare")])
1127
1128 ;; We don't need abs with condition code because such comparisons should
1129 ;; never be done.
1130 (define_expand "abssi2"
1131 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1132 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1133 ""
1134 "
1135 {
1136 if (!TARGET_POWER)
1137 {
1138 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1139 DONE;
1140 }
1141 }")
1142
1143 (define_insn "abssi2_power"
1144 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1145 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1146 "TARGET_POWER"
1147 "abs %0,%1")
1148
1149 (define_insn "abssi2_nopower"
1150 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1151 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1152 (clobber (match_scratch:SI 2 "=&r,&r"))]
1153 "!TARGET_POWER"
1154 "*
1155 {
1156 return (TARGET_POWERPC)
1157 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
1158 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
1159 }"
1160 [(set_attr "length" "12")])
1161
1162 (define_split
1163 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1164 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1165 (clobber (match_scratch:SI 2 "=&r,&r"))]
1166 "!TARGET_POWER && reload_completed"
1167 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1168 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1169 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1170 "")
1171
1172 (define_insn ""
1173 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1174 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1175 "TARGET_POWER"
1176 "nabs %0,%1")
1177
1178 (define_insn ""
1179 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1180 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1181 (clobber (match_scratch:SI 2 "=&r,&r"))]
1182 "!TARGET_POWER"
1183 "*
1184 {
1185 return (TARGET_POWERPC)
1186 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
1187 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
1188 }"
1189 [(set_attr "length" "12")])
1190
1191 (define_split
1192 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1193 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1194 (clobber (match_scratch:SI 2 "=&r,&r"))]
1195 "!TARGET_POWER && reload_completed"
1196 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1197 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1198 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1199 "")
1200
1201 (define_insn "negsi2"
1202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1203 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1204 ""
1205 "neg %0,%1")
1206
1207 (define_insn ""
1208 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1209 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1210 (const_int 0)))
1211 (clobber (match_scratch:SI 2 "=r"))]
1212 ""
1213 "neg. %2,%1"
1214 [(set_attr "type" "compare")])
1215
1216 (define_insn ""
1217 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1218 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1219 (const_int 0)))
1220 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1221 (neg:SI (match_dup 1)))]
1222 ""
1223 "neg. %0,%1"
1224 [(set_attr "type" "compare")])
1225
1226 (define_insn "ffssi2"
1227 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1228 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1229 ""
1230 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
1231 [(set_attr "length" "16")])
1232
1233 (define_expand "mulsi3"
1234 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1235 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1236 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1237 ""
1238 "
1239 {
1240 if (TARGET_POWER)
1241 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1242 else
1243 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1244 DONE;
1245 }")
1246
1247 (define_insn "mulsi3_mq"
1248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1249 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1250 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1251 (clobber (match_scratch:SI 3 "=q,q"))]
1252 "TARGET_POWER"
1253 "@
1254 {muls|mullw} %0,%1,%2
1255 {muli|mulli} %0,%1,%2"
1256 [(set_attr "type" "imul")])
1257
1258 (define_insn "mulsi3_no_mq"
1259 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1260 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1261 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1262 "! TARGET_POWER"
1263 "@
1264 {muls|mullw} %0,%1,%2
1265 {muli|mulli} %0,%1,%2"
1266 [(set_attr "type" "imul")])
1267
1268 (define_insn ""
1269 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1270 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1271 (match_operand:SI 2 "gpc_reg_operand" "r"))
1272 (const_int 0)))
1273 (clobber (match_scratch:SI 3 "=r"))
1274 (clobber (match_scratch:SI 4 "=q"))]
1275 "TARGET_POWER"
1276 "{muls.|mullw.} %3,%1,%2"
1277 [(set_attr "type" "delayed_compare")])
1278
1279 (define_insn ""
1280 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1281 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1282 (match_operand:SI 2 "gpc_reg_operand" "r"))
1283 (const_int 0)))
1284 (clobber (match_scratch:SI 3 "=r"))]
1285 "! TARGET_POWER"
1286 "{muls.|mullw.} %3,%1,%2"
1287 [(set_attr "type" "delayed_compare")])
1288
1289 (define_insn ""
1290 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1291 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1292 (match_operand:SI 2 "gpc_reg_operand" "r"))
1293 (const_int 0)))
1294 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1295 (mult:SI (match_dup 1) (match_dup 2)))
1296 (clobber (match_scratch:SI 4 "=q"))]
1297 "TARGET_POWER"
1298 "{muls.|mullw.} %0,%1,%2"
1299 [(set_attr "type" "delayed_compare")])
1300
1301 (define_insn ""
1302 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1303 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1304 (match_operand:SI 2 "gpc_reg_operand" "r"))
1305 (const_int 0)))
1306 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1307 (mult:SI (match_dup 1) (match_dup 2)))]
1308 "! TARGET_POWER"
1309 "{muls.|mullw.} %0,%1,%2"
1310 [(set_attr "type" "delayed_compare")])
1311
1312 ;; Operand 1 is divided by operand 2; quotient goes to operand
1313 ;; 0 and remainder to operand 3.
1314 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1315
1316 (define_expand "divmodsi4"
1317 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1318 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1319 (match_operand:SI 2 "gpc_reg_operand" "")))
1320 (set (match_operand:SI 3 "gpc_reg_operand" "")
1321 (mod:SI (match_dup 1) (match_dup 2)))])]
1322 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1323 "
1324 {
1325 if (! TARGET_POWER && ! TARGET_POWERPC)
1326 {
1327 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1328 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1329 emit_insn (gen_divss_call ());
1330 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1331 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1332 DONE;
1333 }
1334 }")
1335
1336 (define_insn ""
1337 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1338 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1339 (match_operand:SI 2 "gpc_reg_operand" "r")))
1340 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1341 (mod:SI (match_dup 1) (match_dup 2)))]
1342 "TARGET_POWER"
1343 "divs %0,%1,%2"
1344 [(set_attr "type" "idiv")])
1345
1346 (define_insn ""
1347 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1348 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1349 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1350 "TARGET_POWERPC"
1351 "divw %0,%1,%2"
1352 [(set_attr "type" "idiv")])
1353
1354 (define_expand "udivsi3"
1355 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1356 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1357 (match_operand:SI 2 "gpc_reg_operand" "")))]
1358 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1359 "
1360 {
1361 if (! TARGET_POWER && ! TARGET_POWERPC)
1362 {
1363 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1364 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1365 emit_insn (gen_quous_call ());
1366 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1367 DONE;
1368 }
1369 }")
1370
1371 (define_insn ""
1372 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1373 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1374 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1375 "TARGET_POWERPC"
1376 "divwu %0,%1,%2"
1377 [(set_attr "type" "idiv")])
1378
1379 ;; For powers of two we can do srai/aze for divide and then adjust for
1380 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1381 ;; used; for PowerPC, force operands into register and do a normal divide;
1382 ;; for AIX common-mode, use quoss call on register operands.
1383 (define_expand "divsi3"
1384 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1385 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1386 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1387 ""
1388 "
1389 {
1390 if (GET_CODE (operands[2]) == CONST_INT
1391 && exact_log2 (INTVAL (operands[2])) >= 0)
1392 ;
1393 else if (TARGET_POWERPC)
1394 operands[2] = force_reg (SImode, operands[2]);
1395 else if (TARGET_POWER)
1396 FAIL;
1397 else
1398 {
1399 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1400 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1401 emit_insn (gen_quoss_call ());
1402 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1403 DONE;
1404 }
1405 }")
1406
1407 (define_expand "modsi3"
1408 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1409 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1410 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1411 ""
1412 "
1413 {
1414 int i = exact_log2 (INTVAL (operands[2]));
1415 rtx temp1;
1416 rtx temp2;
1417
1418 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
1419 FAIL;
1420
1421 temp1 = gen_reg_rtx (SImode);
1422 temp2 = gen_reg_rtx (SImode);
1423
1424 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1425 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1426 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1427 DONE;
1428 }")
1429
1430 (define_insn ""
1431 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1432 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1433 (match_operand:SI 2 "const_int_operand" "N")))]
1434 "exact_log2 (INTVAL (operands[2])) >= 0"
1435 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1436 [(set_attr "length" "8")])
1437
1438 (define_insn ""
1439 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1440 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1441 (match_operand:SI 2 "const_int_operand" "N"))
1442 (const_int 0)))
1443 (clobber (match_scratch:SI 3 "=r"))]
1444 "exact_log2 (INTVAL (operands[2])) >= 0"
1445 "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
1446 [(set_attr "type" "compare")
1447 (set_attr "length" "8")])
1448
1449 (define_insn ""
1450 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1451 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1452 (match_operand:SI 2 "const_int_operand" "N"))
1453 (const_int 0)))
1454 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1455 (div:SI (match_dup 1) (match_dup 2)))]
1456 "exact_log2 (INTVAL (operands[2])) >= 0"
1457 "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0"
1458 [(set_attr "type" "compare")
1459 (set_attr "length" "8")])
1460
1461 (define_insn ""
1462 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1463 (udiv:SI
1464 (plus:DI (ashift:DI
1465 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1466 (const_int 32))
1467 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
1468 (match_operand:SI 3 "gpc_reg_operand" "r")))
1469 (set (match_operand:SI 2 "register_operand" "=*q")
1470 (umod:SI
1471 (plus:DI (ashift:DI
1472 (zero_extend:DI (match_dup 1)) (const_int 32))
1473 (zero_extend:DI (match_dup 4)))
1474 (match_dup 3)))]
1475 "TARGET_POWER"
1476 "div %0,%1,%3"
1477 [(set_attr "type" "idiv")])
1478
1479 ;; To do unsigned divide we handle the cases of the divisor looking like a
1480 ;; negative number. If it is a constant that is less than 2**31, we don't
1481 ;; have to worry about the branches. So make a few subroutines here.
1482 ;;
1483 ;; First comes the normal case.
1484 (define_expand "udivmodsi4_normal"
1485 [(set (match_dup 4) (const_int 0))
1486 (parallel [(set (match_operand:SI 0 "" "")
1487 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1488 (const_int 32))
1489 (zero_extend:DI (match_operand:SI 1 "" "")))
1490 (match_operand:SI 2 "" "")))
1491 (set (match_operand:SI 3 "" "")
1492 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1493 (const_int 32))
1494 (zero_extend:DI (match_dup 1)))
1495 (match_dup 2)))])]
1496 "TARGET_POWER"
1497 "
1498 { operands[4] = gen_reg_rtx (SImode); }")
1499
1500 ;; This handles the branches.
1501 (define_expand "udivmodsi4_tests"
1502 [(set (match_operand:SI 0 "" "") (const_int 0))
1503 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
1504 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
1505 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
1506 (label_ref (match_operand:SI 4 "" "")) (pc)))
1507 (set (match_dup 0) (const_int 1))
1508 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
1509 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
1510 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
1511 (label_ref (match_dup 4)) (pc)))]
1512 "TARGET_POWER"
1513 "
1514 { operands[5] = gen_reg_rtx (CCUNSmode);
1515 operands[6] = gen_reg_rtx (CCmode);
1516 }")
1517
1518 (define_expand "udivmodsi4"
1519 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1520 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1521 (match_operand:SI 2 "reg_or_cint_operand" "")))
1522 (set (match_operand:SI 3 "gpc_reg_operand" "")
1523 (umod:SI (match_dup 1) (match_dup 2)))])]
1524 ""
1525 "
1526 {
1527 rtx label = 0;
1528
1529 if (! TARGET_POWER)
1530 if (! TARGET_POWERPC)
1531 {
1532 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1533 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1534 emit_insn (gen_divus_call ());
1535 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1536 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1537 DONE;
1538 }
1539 else
1540 FAIL;
1541
1542 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
1543 {
1544 operands[2] = force_reg (SImode, operands[2]);
1545 label = gen_label_rtx ();
1546 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
1547 operands[3], label));
1548 }
1549 else
1550 operands[2] = force_reg (SImode, operands[2]);
1551
1552 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
1553 operands[3]));
1554 if (label)
1555 emit_label (label);
1556
1557 DONE;
1558 }")
1559
1560 ;; AIX architecture-independent common-mode multiply (DImode),
1561 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1562 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
1563 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1564 ;; assumed unused if generating common-mode, so ignore.
1565 (define_insn "mulh_call"
1566 [(set (reg:SI 3)
1567 (truncate:SI
1568 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
1569 (sign_extend:DI (reg:SI 4)))
1570 (const_int 32))))
1571 (clobber (match_scratch:SI 0 "=l"))]
1572 "! TARGET_POWER && ! TARGET_POWERPC"
1573 "bla __mulh")
1574
1575 (define_insn "mull_call"
1576 [(set (reg:DI 3)
1577 (mult:DI (sign_extend:DI (reg:SI 3))
1578 (sign_extend:DI (reg:SI 4))))
1579 (clobber (match_scratch:SI 0 "=l"))
1580 (clobber (reg:SI 0))]
1581 "! TARGET_POWER && ! TARGET_POWERPC"
1582 "bla __mull")
1583
1584 (define_insn "divss_call"
1585 [(set (reg:SI 3)
1586 (div:SI (reg:SI 3) (reg:SI 4)))
1587 (set (reg:SI 4)
1588 (mod:SI (reg:SI 3) (reg:SI 4)))
1589 (clobber (match_scratch:SI 0 "=l"))
1590 (clobber (reg:SI 0))]
1591 "! TARGET_POWER && ! TARGET_POWERPC"
1592 "bla __divss")
1593
1594 (define_insn "divus_call"
1595 [(set (reg:SI 3)
1596 (udiv:SI (reg:SI 3) (reg:SI 4)))
1597 (set (reg:SI 4)
1598 (umod:SI (reg:SI 3) (reg:SI 4)))
1599 (clobber (match_scratch:SI 0 "=l"))
1600 (clobber (reg:SI 0))
1601 (clobber (match_scratch:CC 1 "=x"))
1602 (clobber (reg:CC 69))]
1603 "! TARGET_POWER && ! TARGET_POWERPC"
1604 "bla __divus")
1605
1606 (define_insn "quoss_call"
1607 [(set (reg:SI 3)
1608 (div:SI (reg:SI 3) (reg:SI 4)))
1609 (clobber (match_scratch:SI 0 "=l"))]
1610 "! TARGET_POWER && ! TARGET_POWERPC"
1611 "bla __quoss")
1612
1613 (define_insn "quous_call"
1614 [(set (reg:SI 3)
1615 (udiv:SI (reg:SI 3) (reg:SI 4)))
1616 (clobber (match_scratch:SI 0 "=l"))
1617 (clobber (reg:SI 0))
1618 (clobber (match_scratch:CC 1 "=x"))
1619 (clobber (reg:CC 69))]
1620 "! TARGET_POWER && ! TARGET_POWERPC"
1621 "bla __quous")
1622 \f
1623 (define_insn "andsi3"
1624 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1625 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1626 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
1627 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1628 ""
1629 "@
1630 and %0,%1,%2
1631 {rlinm|rlwinm} %0,%1,0,%m2,%M2
1632 {andil.|andi.} %0,%1,%b2
1633 {andiu.|andis.} %0,%1,%u2")
1634
1635 (define_insn ""
1636 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
1637 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1638 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1639 (const_int 0)))
1640 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1641 ""
1642 "@
1643 and. %3,%1,%2
1644 {andil.|andi.} %3,%1,%b2
1645 {andiu.|andis.} %3,%1,%u2
1646 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2"
1647 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1648
1649 (define_insn ""
1650 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
1651 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1652 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1653 (const_int 0)))
1654 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1655 (and:SI (match_dup 1) (match_dup 2)))]
1656 ""
1657 "@
1658 and. %0,%1,%2
1659 {andil.|andi.} %0,%1,%b2
1660 {andiu.|andis.} %0,%1,%u2
1661 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2"
1662 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1663
1664 ;; Take a AND with a constant that cannot be done in a single insn and try to
1665 ;; split it into two insns. This does not verify that the insns are valid
1666 ;; since this need not be done as combine will do it.
1667
1668 (define_split
1669 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1670 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
1671 (match_operand:SI 2 "non_and_cint_operand" "")))]
1672 ""
1673 [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
1674 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
1675 "
1676 {
1677 int maskval = INTVAL (operands[2]);
1678 int i, transitions, last_bit_value;
1679 int orig = maskval, first_c = maskval, second_c;
1680
1681 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
1682 the low-order bit and count for the third transition. When we get there,
1683 make a first mask that has everything to the left of that position
1684 a one. Then make the second mask to turn off whatever else is needed. */
1685
1686 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
1687 {
1688 if (((maskval >>= 1) & 1) != last_bit_value)
1689 last_bit_value ^= 1, transitions++;
1690
1691 if (transitions > 2)
1692 {
1693 first_c |= (~0) << i;
1694 break;
1695 }
1696 }
1697
1698 second_c = orig | ~ first_c;
1699
1700 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
1701 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
1702 }")
1703
1704 (define_insn "iorsi3"
1705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1706 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1707 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1708 ""
1709 "@
1710 or %0,%1,%2
1711 {oril|ori} %0,%1,%b2
1712 {oriu|oris} %0,%1,%u2")
1713
1714 (define_insn ""
1715 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1716 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1717 (match_operand:SI 2 "gpc_reg_operand" "r"))
1718 (const_int 0)))
1719 (clobber (match_scratch:SI 3 "=r"))]
1720 ""
1721 "or. %3,%1,%2"
1722 [(set_attr "type" "compare")])
1723
1724 (define_insn ""
1725 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1726 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1727 (match_operand:SI 2 "gpc_reg_operand" "r"))
1728 (const_int 0)))
1729 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1730 (ior:SI (match_dup 1) (match_dup 2)))]
1731 ""
1732 "or. %0,%1,%2"
1733 [(set_attr "type" "compare")])
1734
1735 ;; Split an IOR that we can't do in one insn into two insns, each of which
1736 ;; does one 16-bit part. This is used by combine.
1737
1738 (define_split
1739 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1740 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1741 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1742 ""
1743 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
1744 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
1745 "
1746 {
1747 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1748 INTVAL (operands[2]) & 0xffff0000);
1749 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1750 }")
1751
1752 (define_insn "xorsi3"
1753 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1754 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1755 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1756 ""
1757 "@
1758 xor %0,%1,%2
1759 {xoril|xori} %0,%1,%b2
1760 {xoriu|xoris} %0,%1,%u2")
1761
1762 (define_insn ""
1763 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1764 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1765 (match_operand:SI 2 "gpc_reg_operand" "r"))
1766 (const_int 0)))
1767 (clobber (match_scratch:SI 3 "=r"))]
1768 ""
1769 "xor. %3,%1,%2"
1770 [(set_attr "type" "compare")])
1771
1772 (define_insn ""
1773 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1774 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1775 (match_operand:SI 2 "gpc_reg_operand" "r"))
1776 (const_int 0)))
1777 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1778 (xor:SI (match_dup 1) (match_dup 2)))]
1779 ""
1780 "xor. %0,%1,%2"
1781 [(set_attr "type" "compare")])
1782
1783 ;; Split an XOR that we can't do in one insn into two insns, each of which
1784 ;; does one 16-bit part. This is used by combine.
1785
1786 (define_split
1787 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1788 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1789 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1790 ""
1791 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
1792 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
1793 "
1794 {
1795 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1796 INTVAL (operands[2]) & 0xffff0000);
1797 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1798 }")
1799
1800 (define_insn ""
1801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1802 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1803 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1804 ""
1805 "eqv %0,%1,%2")
1806
1807 (define_insn ""
1808 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1809 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1810 (match_operand:SI 2 "gpc_reg_operand" "r")))
1811 (const_int 0)))
1812 (clobber (match_scratch:SI 3 "=r"))]
1813 ""
1814 "eqv. %3,%1,%2"
1815 [(set_attr "type" "compare")])
1816
1817 (define_insn ""
1818 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1819 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1820 (match_operand:SI 2 "gpc_reg_operand" "r")))
1821 (const_int 0)))
1822 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1823 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
1824 ""
1825 "eqv. %0,%1,%2"
1826 [(set_attr "type" "compare")])
1827
1828 (define_insn ""
1829 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1830 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1831 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1832 ""
1833 "andc %0,%2,%1")
1834
1835 (define_insn ""
1836 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1837 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1838 (match_operand:SI 2 "gpc_reg_operand" "r"))
1839 (const_int 0)))
1840 (clobber (match_scratch:SI 3 "=r"))]
1841 ""
1842 "andc. %3,%2,%1"
1843 [(set_attr "type" "compare")])
1844
1845 (define_insn ""
1846 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1847 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1848 (match_operand:SI 2 "gpc_reg_operand" "r"))
1849 (const_int 0)))
1850 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1851 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
1852 ""
1853 "andc. %0,%2,%1"
1854 [(set_attr "type" "compare")])
1855
1856 (define_insn ""
1857 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1858 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1859 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1860 ""
1861 "orc %0,%2,%1")
1862
1863 (define_insn ""
1864 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1865 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1866 (match_operand:SI 2 "gpc_reg_operand" "r"))
1867 (const_int 0)))
1868 (clobber (match_scratch:SI 3 "=r"))]
1869 ""
1870 "orc. %3,%2,%1"
1871 [(set_attr "type" "compare")])
1872
1873 (define_insn ""
1874 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1875 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1876 (match_operand:SI 2 "gpc_reg_operand" "r"))
1877 (const_int 0)))
1878 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1879 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
1880 ""
1881 "orc. %0,%2,%1"
1882 [(set_attr "type" "compare")])
1883
1884 (define_insn ""
1885 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1886 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1887 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1888 ""
1889 "nand %0,%1,%2")
1890
1891 (define_insn ""
1892 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1893 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1894 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1895 (const_int 0)))
1896 (clobber (match_scratch:SI 3 "=r"))]
1897 ""
1898 "nand. %3,%1,%2"
1899 [(set_attr "type" "compare")])
1900
1901 (define_insn ""
1902 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1903 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1904 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1905 (const_int 0)))
1906 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1907 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1908 ""
1909 "nand. %0,%1,%2"
1910 [(set_attr "type" "compare")])
1911
1912 (define_insn ""
1913 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1914 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1915 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1916 ""
1917 "nor %0,%1,%2")
1918
1919 (define_insn ""
1920 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1921 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1922 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1923 (const_int 0)))
1924 (clobber (match_scratch:SI 3 "=r"))]
1925 ""
1926 "nor. %3,%1,%2"
1927 [(set_attr "type" "compare")])
1928
1929 (define_insn ""
1930 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1931 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1932 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1933 (const_int 0)))
1934 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1935 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1936 ""
1937 "nor. %0,%1,%2"
1938 [(set_attr "type" "compare")])
1939
1940 ;; maskir insn. We need four forms because things might be in arbitrary
1941 ;; orders. Don't define forms that only set CR fields because these
1942 ;; would modify an input register.
1943
1944 (define_insn ""
1945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1946 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1947 (match_operand:SI 1 "gpc_reg_operand" "0"))
1948 (and:SI (match_dup 2)
1949 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
1950 "TARGET_POWER"
1951 "maskir %0,%3,%2")
1952
1953 (define_insn ""
1954 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1955 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1956 (match_operand:SI 1 "gpc_reg_operand" "0"))
1957 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1958 (match_dup 2))))]
1959 "TARGET_POWER"
1960 "maskir %0,%3,%2")
1961
1962 (define_insn ""
1963 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1964 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1965 (match_operand:SI 3 "gpc_reg_operand" "r"))
1966 (and:SI (not:SI (match_dup 2))
1967 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1968 "TARGET_POWER"
1969 "maskir %0,%3,%2")
1970
1971 (define_insn ""
1972 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1973 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1974 (match_operand:SI 2 "gpc_reg_operand" "r"))
1975 (and:SI (not:SI (match_dup 2))
1976 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1977 "TARGET_POWER"
1978 "maskir %0,%3,%2")
1979
1980 (define_insn ""
1981 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1982 (compare:CC
1983 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1984 (match_operand:SI 1 "gpc_reg_operand" "0"))
1985 (and:SI (match_dup 2)
1986 (match_operand:SI 3 "gpc_reg_operand" "r")))
1987 (const_int 0)))
1988 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1989 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
1990 (and:SI (match_dup 2) (match_dup 3))))]
1991 "TARGET_POWER"
1992 "maskir. %0,%3,%2"
1993 [(set_attr "type" "compare")])
1994
1995 (define_insn ""
1996 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1997 (compare:CC
1998 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1999 (match_operand:SI 1 "gpc_reg_operand" "0"))
2000 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2001 (match_dup 2)))
2002 (const_int 0)))
2003 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2004 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
2005 (and:SI (match_dup 3) (match_dup 2))))]
2006 "TARGET_POWER"
2007 "maskir. %0,%3,%2"
2008 [(set_attr "type" "compare")])
2009
2010 (define_insn ""
2011 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2012 (compare:CC
2013 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2014 (match_operand:SI 3 "gpc_reg_operand" "r"))
2015 (and:SI (not:SI (match_dup 2))
2016 (match_operand:SI 1 "gpc_reg_operand" "0")))
2017 (const_int 0)))
2018 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2019 (ior:SI (and:SI (match_dup 2) (match_dup 3))
2020 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2021 "TARGET_POWER"
2022 "maskir. %0,%3,%2"
2023 [(set_attr "type" "compare")])
2024
2025 (define_insn ""
2026 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2027 (compare:CC
2028 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2029 (match_operand:SI 2 "gpc_reg_operand" "r"))
2030 (and:SI (not:SI (match_dup 2))
2031 (match_operand:SI 1 "gpc_reg_operand" "0")))
2032 (const_int 0)))
2033 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2034 (ior:SI (and:SI (match_dup 3) (match_dup 2))
2035 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
2036 "TARGET_POWER"
2037 "maskir. %0,%3,%2"
2038 [(set_attr "type" "compare")])
2039 \f
2040 ;; Rotate and shift insns, in all their variants. These support shifts,
2041 ;; field inserts and extracts, and various combinations thereof.
2042 (define_expand "insv"
2043 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2044 (match_operand:SI 1 "const_int_operand" "i")
2045 (match_operand:SI 2 "const_int_operand" "i"))
2046 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2047 ""
2048 "
2049 {
2050 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2051 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2052 compiler if the address of the structure is taken later. */
2053 if (GET_CODE (operands[0]) == SUBREG
2054 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2055 FAIL;
2056 }")
2057
2058 (define_insn ""
2059 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2060 (match_operand:SI 1 "const_int_operand" "i")
2061 (match_operand:SI 2 "const_int_operand" "i"))
2062 (match_operand:SI 3 "gpc_reg_operand" "r"))]
2063 ""
2064 "*
2065 {
2066 int start = INTVAL (operands[2]) & 31;
2067 int size = INTVAL (operands[1]) & 31;
2068
2069 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
2070 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2071 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
2072 }")
2073
2074 (define_insn ""
2075 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2076 (match_operand:SI 1 "const_int_operand" "i")
2077 (match_operand:SI 2 "const_int_operand" "i"))
2078 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2079 (match_operand:SI 4 "const_int_operand" "i")))]
2080 ""
2081 "*
2082 {
2083 int shift = INTVAL (operands[4]) & 31;
2084 int start = INTVAL (operands[2]) & 31;
2085 int size = INTVAL (operands[1]) & 31;
2086
2087 operands[4] = gen_rtx (CONST_INT, VOIDmode, (shift - start - size) & 31);
2088 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2089 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
2090 }")
2091
2092 (define_insn ""
2093 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2094 (match_operand:SI 1 "const_int_operand" "i")
2095 (match_operand:SI 2 "const_int_operand" "i"))
2096 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2097 (match_operand:SI 4 "const_int_operand" "i")))]
2098 ""
2099 "*
2100 {
2101 int shift = INTVAL (operands[4]) & 31;
2102 int start = INTVAL (operands[2]) & 31;
2103 int size = INTVAL (operands[1]) & 31;
2104
2105 operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
2106 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2107 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
2108 }")
2109
2110 (define_insn ""
2111 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2112 (match_operand:SI 1 "const_int_operand" "i")
2113 (match_operand:SI 2 "const_int_operand" "i"))
2114 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2115 (match_operand:SI 4 "const_int_operand" "i")))]
2116 ""
2117 "*
2118 {
2119 int shift = INTVAL (operands[4]) & 31;
2120 int start = INTVAL (operands[2]) & 31;
2121 int size = INTVAL (operands[1]) & 31;
2122
2123 operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
2124 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
2125 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
2126 }")
2127
2128 (define_insn ""
2129 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2130 (match_operand:SI 1 "const_int_operand" "i")
2131 (match_operand:SI 2 "const_int_operand" "i"))
2132 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2133 (match_operand:SI 4 "const_int_operand" "i")
2134 (match_operand:SI 5 "const_int_operand" "i")))]
2135 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2136 "*
2137 {
2138 int extract_start = INTVAL (operands[5]) & 31;
2139 int extract_size = INTVAL (operands[4]) & 31;
2140 int insert_start = INTVAL (operands[2]) & 31;
2141 int insert_size = INTVAL (operands[1]) & 31;
2142
2143 /* Align extract field with insert field */
2144 operands[5] = gen_rtx (CONST_INT, VOIDmode,
2145 (extract_start + extract_size - insert_start - insert_size) & 31);
2146 operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1);
2147 return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\";
2148 }")
2149
2150 (define_expand "extzv"
2151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2152 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2153 (match_operand:SI 2 "const_int_operand" "i")
2154 (match_operand:SI 3 "const_int_operand" "i")))]
2155 ""
2156 "
2157 {
2158 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
2159 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2160 compiler if the address of the structure is taken later. */
2161 if (GET_CODE (operands[0]) == SUBREG
2162 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
2163 FAIL;
2164 }")
2165
2166 (define_insn ""
2167 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2168 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2169 (match_operand:SI 2 "const_int_operand" "i")
2170 (match_operand:SI 3 "const_int_operand" "i")))]
2171 ""
2172 "*
2173 {
2174 int start = INTVAL (operands[3]) & 31;
2175 int size = INTVAL (operands[2]) & 31;
2176
2177 if (start + size >= 32)
2178 operands[3] = const0_rtx;
2179 else
2180 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2181 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
2182 }")
2183
2184 (define_insn ""
2185 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2186 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2187 (match_operand:SI 2 "const_int_operand" "i")
2188 (match_operand:SI 3 "const_int_operand" "i"))
2189 (const_int 0)))
2190 (clobber (match_scratch:SI 4 "=r"))]
2191 ""
2192 "*
2193 {
2194 int start = INTVAL (operands[3]) & 31;
2195 int size = INTVAL (operands[2]) & 31;
2196
2197 /* If the bitfield being tested fits in the upper or lower half of a
2198 word, it is possible to use andiu. or andil. to test it. This is
2199 useful because the condition register set-use delay is smaller for
2200 andi[ul]. than for rlinm. This doesn't work when the starting bit
2201 position is 0 because the LT and GT bits may be set wrong. */
2202
2203 if ((start > 0 && start + size <= 16) || start >= 16)
2204 {
2205 operands[3] = gen_rtx (CONST_INT, VOIDmode,
2206 ((1 << (16 - (start & 15)))
2207 - (1 << (16 - (start & 15) - size))));
2208 if (start < 16)
2209 return \"{andiu.|andis.} %4,%1,%3\";
2210 else
2211 return \"{andil.|andi.} %4,%1,%3\";
2212 }
2213
2214 if (start + size >= 32)
2215 operands[3] = const0_rtx;
2216 else
2217 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2218 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
2219 }"
2220 [(set_attr "type" "compare")])
2221
2222 (define_insn ""
2223 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2224 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2225 (match_operand:SI 2 "const_int_operand" "i")
2226 (match_operand:SI 3 "const_int_operand" "i"))
2227 (const_int 0)))
2228 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2229 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
2230 ""
2231 "*
2232 {
2233 int start = INTVAL (operands[3]) & 31;
2234 int size = INTVAL (operands[2]) & 31;
2235
2236 if (start >= 16 && start + size == 32)
2237 {
2238 operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
2239 return \"{andil.|andi.} %0,%1,%3\";
2240 }
2241
2242 if (start + size >= 32)
2243 operands[3] = const0_rtx;
2244 else
2245 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2246 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
2247 }"
2248 [(set_attr "type" "delayed_compare")])
2249
2250 (define_insn "rotlsi3"
2251 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2252 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2253 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2254 ""
2255 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
2256
2257 (define_insn ""
2258 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2259 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2260 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2261 (const_int 0)))
2262 (clobber (match_scratch:SI 3 "=r"))]
2263 ""
2264 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
2265 [(set_attr "type" "delayed_compare")])
2266
2267 (define_insn ""
2268 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2269 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2270 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2271 (const_int 0)))
2272 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2273 (rotate:SI (match_dup 1) (match_dup 2)))]
2274 ""
2275 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff"
2276 [(set_attr "type" "delayed_compare")])
2277
2278 (define_insn ""
2279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2280 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2281 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2282 (match_operand:SI 3 "mask_operand" "L")))]
2283 ""
2284 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
2285
2286 (define_insn ""
2287 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2288 (compare:CC (and:SI
2289 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2290 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2291 (match_operand:SI 3 "mask_operand" "L"))
2292 (const_int 0)))
2293 (clobber (match_scratch:SI 4 "=r"))]
2294 ""
2295 "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3"
2296 [(set_attr "type" "delayed_compare")])
2297
2298 (define_insn ""
2299 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2300 (compare:CC (and:SI
2301 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2302 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2303 (match_operand:SI 3 "mask_operand" "L"))
2304 (const_int 0)))
2305 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2306 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2307 ""
2308 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3"
2309 [(set_attr "type" "delayed_compare")])
2310
2311 (define_insn ""
2312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2313 (zero_extend:SI
2314 (subreg:QI
2315 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2316 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2317 ""
2318 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
2319
2320 (define_insn ""
2321 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2322 (compare:CC (zero_extend:SI
2323 (subreg:QI
2324 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2325 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2326 (const_int 0)))
2327 (clobber (match_scratch:SI 3 "=r"))]
2328 ""
2329 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff"
2330 [(set_attr "type" "delayed_compare")])
2331
2332 (define_insn ""
2333 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2334 (compare:CC (zero_extend:SI
2335 (subreg:QI
2336 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2337 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2338 (const_int 0)))
2339 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2340 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2341 ""
2342 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff"
2343 [(set_attr "type" "delayed_compare")])
2344
2345 (define_insn ""
2346 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2347 (zero_extend:SI
2348 (subreg:HI
2349 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2350 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2351 ""
2352 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
2353
2354 (define_insn ""
2355 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2356 (compare:CC (zero_extend:SI
2357 (subreg:HI
2358 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2359 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2360 (const_int 0)))
2361 (clobber (match_scratch:SI 3 "=r"))]
2362 ""
2363 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff"
2364 [(set_attr "type" "delayed_compare")])
2365
2366 (define_insn ""
2367 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2368 (compare:CC (zero_extend:SI
2369 (subreg:HI
2370 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2371 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2372 (const_int 0)))
2373 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2374 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2375 ""
2376 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff"
2377 [(set_attr "type" "delayed_compare")])
2378
2379 ;; Note that we use "sle." instead of "sl." so that we can set
2380 ;; SHIFT_COUNT_TRUNCATED.
2381
2382 (define_expand "ashlsi3"
2383 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2384 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2385 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2386 ""
2387 "
2388 {
2389 if (TARGET_POWER)
2390 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
2391 else
2392 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
2393 DONE;
2394 }")
2395
2396 (define_insn "ashlsi3_power"
2397 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2398 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2399 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2400 (clobber (match_scratch:SI 3 "=q,X"))]
2401 "TARGET_POWER"
2402 "@
2403 sle %0,%1,%2
2404 {sli|slwi} %0,%1,%h2"
2405 [(set_attr "length" "8")])
2406
2407 (define_insn "ashlsi3_no_power"
2408 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2409 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2410 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2411 "! TARGET_POWER"
2412 "{sl|slw}%I2 %0,%1,%h2"
2413 [(set_attr "length" "8")])
2414
2415 (define_insn ""
2416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2417 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2418 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2419 (const_int 0)))
2420 (clobber (match_scratch:SI 3 "=r,r"))
2421 (clobber (match_scratch:SI 4 "=q,X"))]
2422 "TARGET_POWER"
2423 "@
2424 sle. %3,%1,%2
2425 {sli.|slwi.} %3,%1,%h2"
2426 [(set_attr "type" "delayed_compare")])
2427
2428 (define_insn ""
2429 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2430 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2431 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2432 (const_int 0)))
2433 (clobber (match_scratch:SI 3 "=r"))]
2434 "! TARGET_POWER"
2435 "{sl|slw}%I2. %3,%1,%h2"
2436 [(set_attr "type" "delayed_compare")])
2437
2438 (define_insn ""
2439 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2440 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2441 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2442 (const_int 0)))
2443 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2444 (ashift:SI (match_dup 1) (match_dup 2)))
2445 (clobber (match_scratch:SI 4 "=q,X"))]
2446 "TARGET_POWER"
2447 "@
2448 sle. %0,%1,%2
2449 {sli.|slwi.} %0,%1,%h2"
2450 [(set_attr "type" "delayed_compare")])
2451
2452 (define_insn ""
2453 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2454 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2455 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2456 (const_int 0)))
2457 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2458 (ashift:SI (match_dup 1) (match_dup 2)))]
2459 "! TARGET_POWER"
2460 "{sl|slw}%I2. %0,%1,%h2"
2461 [(set_attr "type" "delayed_compare")])
2462
2463 (define_insn ""
2464 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2465 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2466 (match_operand:SI 2 "const_int_operand" "i"))
2467 (match_operand:SI 3 "mask_operand" "L")))]
2468 "includes_lshift_p (operands[2], operands[3])"
2469 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
2470
2471 (define_insn ""
2472 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2473 (compare:CC
2474 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2475 (match_operand:SI 2 "const_int_operand" "i"))
2476 (match_operand:SI 3 "mask_operand" "L"))
2477 (const_int 0)))
2478 (clobber (match_scratch:SI 4 "=r"))]
2479 "includes_lshift_p (operands[2], operands[3])"
2480 "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
2481 [(set_attr "type" "delayed_compare")])
2482
2483 (define_insn ""
2484 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2485 (compare:CC
2486 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2487 (match_operand:SI 2 "const_int_operand" "i"))
2488 (match_operand:SI 3 "mask_operand" "L"))
2489 (const_int 0)))
2490 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2491 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2492 "includes_lshift_p (operands[2], operands[3])"
2493 "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
2494 [(set_attr "type" "delayed_compare")])
2495
2496 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
2497 ;; "sli x,x,0".
2498 (define_expand "lshrsi3"
2499 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2500 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2501 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2502 ""
2503 "
2504 {
2505 if (TARGET_POWER)
2506 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
2507 else
2508 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
2509 DONE;
2510 }")
2511
2512 (define_insn "lshrsi3_power"
2513 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2514 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2515 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2516 (clobber (match_scratch:SI 3 "=q,X"))]
2517 "TARGET_POWER"
2518 "@
2519 sre %0,%1,%2
2520 {s%A2i|s%A2wi} %0,%1,%h2")
2521
2522 (define_insn "lshrsi3_no_power"
2523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2524 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2525 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2526 "! TARGET_POWER"
2527 "{sr|srw}%I2 %0,%1,%h2")
2528
2529 (define_insn ""
2530 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2531 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2532 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2533 (const_int 0)))
2534 (clobber (match_scratch:SI 3 "=r,r"))
2535 (clobber (match_scratch:SI 4 "=q,X"))]
2536 "TARGET_POWER"
2537 "@
2538 sre. %3,%1,%2
2539 {s%A2i.|s%A2wi.} %3,%1,%h2"
2540 [(set_attr "type" "delayed_compare")])
2541
2542 (define_insn ""
2543 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2544 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2545 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2546 (const_int 0)))
2547 (clobber (match_scratch:SI 3 "=r"))]
2548 "! TARGET_POWER"
2549 "{sr|srw}%I2. %3,%1,%h2"
2550 [(set_attr "type" "delayed_compare")])
2551
2552 (define_insn ""
2553 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2554 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2555 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2556 (const_int 0)))
2557 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2558 (lshiftrt:SI (match_dup 1) (match_dup 2)))
2559 (clobber (match_scratch:SI 4 "=q,X"))]
2560 "TARGET_POWER"
2561 "@
2562 sre. %0,%1,%2
2563 {s%A2i.|s%A2wi.} %0,%1,%h2"
2564 [(set_attr "type" "delayed_compare")])
2565
2566 (define_insn ""
2567 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2568 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2569 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2570 (const_int 0)))
2571 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2572 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
2573 "! TARGET_POWER"
2574 "{sr|srw}%I2. %0,%1,%h2"
2575 [(set_attr "type" "delayed_compare")])
2576
2577 (define_insn ""
2578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2579 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2580 (match_operand:SI 2 "const_int_operand" "i"))
2581 (match_operand:SI 3 "mask_operand" "L")))]
2582 "includes_rshift_p (operands[2], operands[3])"
2583 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
2584
2585 (define_insn ""
2586 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2587 (compare:CC
2588 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2589 (match_operand:SI 2 "const_int_operand" "i"))
2590 (match_operand:SI 3 "mask_operand" "L"))
2591 (const_int 0)))
2592 (clobber (match_scratch:SI 4 "=r"))]
2593 "includes_rshift_p (operands[2], operands[3])"
2594 "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3"
2595 [(set_attr "type" "delayed_compare")])
2596
2597 (define_insn ""
2598 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2599 (compare:CC
2600 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2601 (match_operand:SI 2 "const_int_operand" "i"))
2602 (match_operand:SI 3 "mask_operand" "L"))
2603 (const_int 0)))
2604 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2605 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2606 "includes_rshift_p (operands[2], operands[3])"
2607 "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3"
2608 [(set_attr "type" "delayed_compare")])
2609
2610 (define_insn ""
2611 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2612 (zero_extend:SI
2613 (subreg:QI
2614 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2615 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2616 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2617 "{rlinm|rlwinm} %0,%1,%s2,0xff")
2618
2619 (define_insn ""
2620 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2621 (compare:CC
2622 (zero_extend:SI
2623 (subreg:QI
2624 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2625 (match_operand:SI 2 "const_int_operand" "i")) 0))
2626 (const_int 0)))
2627 (clobber (match_scratch:SI 3 "=r"))]
2628 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2629 "{rlinm.|rlwinm.} %3,%1,%s2,0xff"
2630 [(set_attr "type" "delayed_compare")])
2631
2632 (define_insn ""
2633 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2634 (compare:CC
2635 (zero_extend:SI
2636 (subreg:QI
2637 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2638 (match_operand:SI 2 "const_int_operand" "i")) 0))
2639 (const_int 0)))
2640 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2641 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2642 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2643 "{rlinm.|rlwinm.} %0,%1,%s2,0xff"
2644 [(set_attr "type" "delayed_compare")])
2645
2646 (define_insn ""
2647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2648 (zero_extend:SI
2649 (subreg:HI
2650 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2651 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2652 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2653 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
2654
2655 (define_insn ""
2656 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2657 (compare:CC
2658 (zero_extend:SI
2659 (subreg:HI
2660 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2661 (match_operand:SI 2 "const_int_operand" "i")) 0))
2662 (const_int 0)))
2663 (clobber (match_scratch:SI 3 "=r"))]
2664 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2665 "{rlinm.|rlwinm.} %3,%1,%s2,0xffff"
2666 [(set_attr "type" "delayed_compare")])
2667
2668 (define_insn ""
2669 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2670 (compare:CC
2671 (zero_extend:SI
2672 (subreg:HI
2673 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2674 (match_operand:SI 2 "const_int_operand" "i")) 0))
2675 (const_int 0)))
2676 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2677 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2678 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2679 "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
2680 [(set_attr "type" "delayed_compare")])
2681
2682 (define_insn ""
2683 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2684 (const_int 1)
2685 (match_operand:SI 1 "gpc_reg_operand" "r"))
2686 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2687 (const_int 31)))]
2688 "TARGET_POWER"
2689 "rrib %0,%1,%2")
2690
2691 (define_insn ""
2692 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2693 (const_int 1)
2694 (match_operand:SI 1 "gpc_reg_operand" "r"))
2695 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2696 (const_int 31)))]
2697 "TARGET_POWER"
2698 "rrib %0,%1,%2")
2699
2700 (define_insn ""
2701 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2702 (const_int 1)
2703 (match_operand:SI 1 "gpc_reg_operand" "r"))
2704 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2705 (const_int 1)
2706 (const_int 0)))]
2707 "TARGET_POWER"
2708 "rrib %0,%1,%2")
2709
2710 (define_expand "ashrsi3"
2711 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2712 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
2713 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2714 ""
2715 "
2716 {
2717 if (TARGET_POWER)
2718 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
2719 else
2720 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
2721 DONE;
2722 }")
2723
2724 (define_insn "ashrsi3_power"
2725 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2726 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2727 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2728 (clobber (match_scratch:SI 3 "=q,X"))]
2729 "TARGET_POWER"
2730 "@
2731 srea %0,%1,%2
2732 {srai|srawi} %0,%1,%h2")
2733
2734 (define_insn "ashrsi3_no_power"
2735 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2736 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2737 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2738 "! TARGET_POWER"
2739 "{sra|sraw}%I2 %0,%1,%h2")
2740
2741 (define_insn ""
2742 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2743 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2744 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2745 (const_int 0)))
2746 (clobber (match_scratch:SI 3 "=r,r"))
2747 (clobber (match_scratch:SI 4 "=q,X"))]
2748 "TARGET_POWER"
2749 "@
2750 srea. %3,%1,%2
2751 {srai.|srawi.} %3,%1,%h2"
2752 [(set_attr "type" "delayed_compare")])
2753
2754 (define_insn ""
2755 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2756 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2757 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2758 (const_int 0)))
2759 (clobber (match_scratch:SI 3 "=r"))]
2760 "! TARGET_POWER"
2761 "{sra|sraw}%I2. %3,%1,%h2"
2762 [(set_attr "type" "delayed_compare")])
2763
2764 (define_insn ""
2765 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2766 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2767 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2768 (const_int 0)))
2769 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2770 (ashiftrt:SI (match_dup 1) (match_dup 2)))
2771 (clobber (match_scratch:SI 4 "=q,X"))]
2772 "TARGET_POWER"
2773 "@
2774 srea. %0,%1,%2
2775 {srai.|srawi.} %0,%1,%h2"
2776 [(set_attr "type" "delayed_compare")])
2777
2778 (define_insn ""
2779 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2780 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2781 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2782 (const_int 0)))
2783 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2784 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
2785 "! TARGET_POWER"
2786 "{sra|sraw}%I2. %0,%1,%h2"
2787 [(set_attr "type" "delayed_compare")])
2788 \f
2789 ;; Floating-point insns, excluding normal data motion.
2790 ;;
2791 ;; PowerPC has a full set of single-precision floating point instructions.
2792 ;;
2793 ;; For the POWER architecture, we pretend that we have both SFmode and
2794 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2795 ;; The only conversions we will do will be when storing to memory. In that
2796 ;; case, we will use the "frsp" instruction before storing.
2797 ;;
2798 ;; Note that when we store into a single-precision memory location, we need to
2799 ;; use the frsp insn first. If the register being stored isn't dead, we
2800 ;; need a scratch register for the frsp. But this is difficult when the store
2801 ;; is done by reload. It is not incorrect to do the frsp on the register in
2802 ;; this case, we just lose precision that we would have otherwise gotten but
2803 ;; is not guaranteed. Perhaps this should be tightened up at some point.
2804
2805 (define_insn "extendsfdf2"
2806 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2807 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2808 "TARGET_HARD_FLOAT"
2809 "*
2810 {
2811 if (REGNO (operands[0]) == REGNO (operands[1]))
2812 return \"\";
2813 else
2814 return \"fmr %0,%1\";
2815 }"
2816 [(set_attr "type" "fp")])
2817
2818 (define_insn "truncdfsf2"
2819 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2820 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
2821 "TARGET_HARD_FLOAT"
2822 "frsp %0,%1"
2823 [(set_attr "type" "fp")])
2824
2825 (define_insn "aux_truncdfsf2"
2826 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2827 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
2828 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2829 "frsp %0,%1"
2830 [(set_attr "type" "fp")])
2831
2832 (define_insn "negsf2"
2833 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2834 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2835 "TARGET_HARD_FLOAT"
2836 "fneg %0,%1"
2837 [(set_attr "type" "fp")])
2838
2839 (define_insn "abssf2"
2840 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2841 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2842 "TARGET_HARD_FLOAT"
2843 "fabs %0,%1"
2844 [(set_attr "type" "fp")])
2845
2846 (define_insn ""
2847 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2848 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
2849 "TARGET_HARD_FLOAT"
2850 "fnabs %0,%1"
2851 [(set_attr "type" "fp")])
2852
2853 (define_expand "addsf3"
2854 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2855 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2856 (match_operand:SF 2 "gpc_reg_operand" "")))]
2857 "TARGET_HARD_FLOAT"
2858 "")
2859
2860 (define_insn ""
2861 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2862 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2863 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2864 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2865 "fadds %0,%1,%2"
2866 [(set_attr "type" "fp")])
2867
2868 (define_insn ""
2869 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2870 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2871 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2872 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2873 "{fa|fadd} %0,%1,%2"
2874 [(set_attr "type" "fp")])
2875
2876 (define_expand "subsf3"
2877 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2878 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2879 (match_operand:SF 2 "gpc_reg_operand" "")))]
2880 "TARGET_HARD_FLOAT"
2881 "")
2882
2883 (define_insn ""
2884 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2885 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2886 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2887 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2888 "fsubs %0,%1,%2"
2889 [(set_attr "type" "fp")])
2890
2891 (define_insn ""
2892 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2893 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2894 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2895 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2896 "{fs|fsub} %0,%1,%2"
2897 [(set_attr "type" "fp")])
2898
2899 (define_expand "mulsf3"
2900 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2901 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
2902 (match_operand:SF 2 "gpc_reg_operand" "")))]
2903 "TARGET_HARD_FLOAT"
2904 "")
2905
2906 (define_insn ""
2907 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2908 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2909 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2910 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2911 "fmuls %0,%1,%2"
2912 [(set_attr "type" "fp")])
2913
2914 (define_insn ""
2915 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2916 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2917 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2918 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2919 "{fm|fmul} %0,%1,%2"
2920 [(set_attr "type" "dmul")])
2921
2922 (define_expand "divsf3"
2923 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2924 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
2925 (match_operand:SF 2 "gpc_reg_operand" "")))]
2926 "TARGET_HARD_FLOAT"
2927 "")
2928
2929 (define_insn ""
2930 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2931 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2932 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2933 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2934 "fdivs %0,%1,%2"
2935 [(set_attr "type" "sdiv")])
2936
2937 (define_insn ""
2938 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2939 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2940 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2941 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2942 "{fd|fdiv} %0,%1,%2"
2943 [(set_attr "type" "ddiv")])
2944
2945 (define_insn ""
2946 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2947 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2948 (match_operand:SF 2 "gpc_reg_operand" "f"))
2949 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2950 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2951 "fmadds %0,%1,%2,%3"
2952 [(set_attr "type" "fp")])
2953
2954 (define_insn ""
2955 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2956 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2957 (match_operand:SF 2 "gpc_reg_operand" "f"))
2958 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2959 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2960 "{fma|fmadd} %0,%1,%2,%3"
2961 [(set_attr "type" "dmul")])
2962
2963 (define_insn ""
2964 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2965 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2966 (match_operand:SF 2 "gpc_reg_operand" "f"))
2967 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2968 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2969 "fmsubs %0,%1,%2,%3"
2970 [(set_attr "type" "fp")])
2971
2972 (define_insn ""
2973 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2974 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2975 (match_operand:SF 2 "gpc_reg_operand" "f"))
2976 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2977 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2978 "{fms|fmsub} %0,%1,%2,%3"
2979 [(set_attr "type" "dmul")])
2980
2981 (define_insn ""
2982 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2983 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2984 (match_operand:SF 2 "gpc_reg_operand" "f"))
2985 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2986 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2987 "fnmadds %0,%1,%2,%3"
2988 [(set_attr "type" "fp")])
2989
2990 (define_insn ""
2991 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2992 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2993 (match_operand:SF 2 "gpc_reg_operand" "f"))
2994 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2995 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2996 "{fnma|fnmadd} %0,%1,%2,%3"
2997 [(set_attr "type" "dmul")])
2998
2999 (define_insn ""
3000 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3001 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3002 (match_operand:SF 2 "gpc_reg_operand" "f"))
3003 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3004 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3005 "fnmsubs %0,%1,%2,%3"
3006 [(set_attr "type" "fp")])
3007
3008 (define_insn ""
3009 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3010 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
3011 (match_operand:SF 2 "gpc_reg_operand" "f"))
3012 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
3013 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3014 "{fnms|fnmsub} %0,%1,%2,%3"
3015 [(set_attr "type" "dmul")])
3016
3017 (define_expand "sqrtsf2"
3018 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3019 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
3020 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3021 "")
3022
3023 (define_insn ""
3024 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3025 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3026 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
3027 "fsqrts %0,%1"
3028 [(set_attr "type" "ssqrt")])
3029
3030 (define_insn ""
3031 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3032 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
3033 "TARGET_POWER2 && TARGET_HARD_FLOAT"
3034 "fsqrt %0,%1"
3035 [(set_attr "type" "dsqrt")])
3036
3037 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3038 ;; fsel instruction and some auxiliary computations. Then we just have a
3039 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3040 ;; combine.
3041 (define_expand "maxsf3"
3042 [(set (match_dup 3)
3043 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
3044 (match_operand:SF 2 "gpc_reg_operand" "")))
3045 (set (match_operand:SF 0 "gpc_reg_operand" "")
3046 (if_then_else:SF (ge (match_dup 3)
3047 (const_int 0))
3048 (match_dup 1)
3049 (match_dup 2)))]
3050 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3051 "
3052 { operands[3] = gen_reg_rtx (SFmode); }")
3053
3054 (define_split
3055 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3056 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
3057 (match_operand:SF 2 "gpc_reg_operand" "")))
3058 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3059 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3060 [(set (match_dup 3)
3061 (minus:SF (match_dup 1) (match_dup 2)))
3062 (set (match_dup 0)
3063 (if_then_else:SF (ge (match_dup 3)
3064 (const_int 0))
3065 (match_dup 1)
3066 (match_dup 2)))]
3067 "")
3068
3069 (define_expand "minsf3"
3070 [(set (match_dup 3)
3071 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
3072 (match_operand:SF 1 "gpc_reg_operand" "")))
3073 (set (match_operand:SF 0 "gpc_reg_operand" "")
3074 (if_then_else:SF (ge (match_dup 3)
3075 (const_int 0))
3076 (match_dup 1)
3077 (match_dup 2)))]
3078 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3079 "
3080 { operands[3] = gen_reg_rtx (SFmode); }")
3081
3082 (define_split
3083 [(set (match_operand:SF 0 "gpc_reg_operand" "")
3084 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
3085 (match_operand:SF 2 "gpc_reg_operand" "")))
3086 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
3087 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3088 [(set (match_dup 3)
3089 (minus:SF (match_dup 2) (match_dup 1)))
3090 (set (match_dup 0)
3091 (if_then_else:SF (ge (match_dup 3)
3092 (const_int 0))
3093 (match_dup 1)
3094 (match_dup 2)))]
3095 "")
3096
3097 (define_expand "movsfcc"
3098 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3099 (if_then_else:SF (match_operand 1 "comparison_operator" "")
3100 (match_operand:SF 2 "gpc_reg_operand" "f")
3101 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3102 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3103 "
3104 {
3105 rtx temp, op0, op1;
3106 enum rtx_code code = GET_CODE (operands[1]);
3107 if (! rs6000_compare_fp_p)
3108 FAIL;
3109 switch (code)
3110 {
3111 case GE: case EQ: case NE:
3112 op0 = rs6000_compare_op0;
3113 op1 = rs6000_compare_op1;
3114 break;
3115 case GT:
3116 op0 = rs6000_compare_op1;
3117 op1 = rs6000_compare_op0;
3118 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3119 break;
3120 case LE:
3121 op0 = rs6000_compare_op1;
3122 op1 = rs6000_compare_op0;
3123 break;
3124 case LT:
3125 op0 = rs6000_compare_op0;
3126 op1 = rs6000_compare_op1;
3127 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3128 break;
3129 default:
3130 FAIL;
3131 }
3132 if (GET_MODE (rs6000_compare_op0) == DFmode)
3133 {
3134 temp = gen_reg_rtx (DFmode);
3135 emit_insn (gen_subdf3 (temp, op0, op1));
3136 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
3137 if (code == EQ)
3138 {
3139 emit_insn (gen_negdf2 (temp, temp));
3140 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
3141 }
3142 if (code == NE)
3143 {
3144 emit_insn (gen_negdf2 (temp, temp));
3145 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0]));
3146 }
3147 }
3148 else
3149 {
3150 temp = gen_reg_rtx (SFmode);
3151 emit_insn (gen_subsf3 (temp, op0, op1));
3152 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
3153 if (code == EQ)
3154 {
3155 emit_insn (gen_negsf2 (temp, temp));
3156 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
3157 }
3158 if (code == NE)
3159 {
3160 emit_insn (gen_negsf2 (temp, temp));
3161 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0]));
3162 }
3163 }
3164 DONE;
3165 }")
3166
3167 (define_insn "fselsfsf4"
3168 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3169 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3170 (const_int 0))
3171 (match_operand:SF 2 "gpc_reg_operand" "f")
3172 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3173 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3174 "fsel %0,%1,%2,%3"
3175 [(set_attr "type" "fp")])
3176
3177 (define_insn "fseldfsf4"
3178 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3179 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3180 (const_int 0))
3181 (match_operand:SF 2 "gpc_reg_operand" "f")
3182 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3183 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3184 "fsel %0,%1,%2,%3"
3185 [(set_attr "type" "fp")])
3186
3187 (define_insn "negdf2"
3188 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3189 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3190 "TARGET_HARD_FLOAT"
3191 "fneg %0,%1"
3192 [(set_attr "type" "fp")])
3193
3194 (define_insn "absdf2"
3195 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3196 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3197 "TARGET_HARD_FLOAT"
3198 "fabs %0,%1"
3199 [(set_attr "type" "fp")])
3200
3201 (define_insn ""
3202 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3203 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3204 "TARGET_HARD_FLOAT"
3205 "fnabs %0,%1"
3206 [(set_attr "type" "fp")])
3207
3208 (define_insn "adddf3"
3209 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3210 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3211 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3212 "TARGET_HARD_FLOAT"
3213 "{fa|fadd} %0,%1,%2"
3214 [(set_attr "type" "fp")])
3215
3216 (define_insn "subdf3"
3217 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3218 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3219 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3220 "TARGET_HARD_FLOAT"
3221 "{fs|fsub} %0,%1,%2"
3222 [(set_attr "type" "fp")])
3223
3224 (define_insn "muldf3"
3225 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3226 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3227 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3228 "TARGET_HARD_FLOAT"
3229 "{fm|fmul} %0,%1,%2"
3230 [(set_attr "type" "dmul")])
3231
3232 (define_insn "divdf3"
3233 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3234 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3235 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3236 "TARGET_HARD_FLOAT"
3237 "{fd|fdiv} %0,%1,%2"
3238 [(set_attr "type" "ddiv")])
3239
3240 (define_insn ""
3241 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3242 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3243 (match_operand:DF 2 "gpc_reg_operand" "f"))
3244 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3245 "TARGET_HARD_FLOAT"
3246 "{fma|fmadd} %0,%1,%2,%3"
3247 [(set_attr "type" "dmul")])
3248
3249 (define_insn ""
3250 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3251 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3252 (match_operand:DF 2 "gpc_reg_operand" "f"))
3253 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3254 "TARGET_HARD_FLOAT"
3255 "{fms|fmsub} %0,%1,%2,%3"
3256 [(set_attr "type" "dmul")])
3257
3258 (define_insn ""
3259 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3260 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3261 (match_operand:DF 2 "gpc_reg_operand" "f"))
3262 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3263 "TARGET_HARD_FLOAT"
3264 "{fnma|fnmadd} %0,%1,%2,%3"
3265 [(set_attr "type" "dmul")])
3266
3267 (define_insn ""
3268 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3269 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3270 (match_operand:DF 2 "gpc_reg_operand" "f"))
3271 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3272 "TARGET_HARD_FLOAT"
3273 "{fnms|fnmsub} %0,%1,%2,%3"
3274 [(set_attr "type" "dmul")])
3275
3276 (define_insn "sqrtdf2"
3277 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3278 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3279 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3280 "fsqrt %0,%1"
3281 [(set_attr "type" "dsqrt")])
3282
3283 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3284 ;; fsel instruction and some auxiliary computations. Then we just have a
3285 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3286 ;; combine.
3287
3288 (define_expand "maxdf3"
3289 [(set (match_dup 3)
3290 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
3291 (match_operand:DF 2 "gpc_reg_operand" "")))
3292 (set (match_operand:DF 0 "gpc_reg_operand" "")
3293 (if_then_else:DF (ge (match_dup 3)
3294 (const_int 0))
3295 (match_dup 1)
3296 (match_dup 2)))]
3297 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3298 "
3299 { operands[3] = gen_reg_rtx (DFmode); }")
3300
3301 (define_split
3302 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3303 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
3304 (match_operand:DF 2 "gpc_reg_operand" "")))
3305 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3306 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3307 [(set (match_dup 3)
3308 (minus:DF (match_dup 1) (match_dup 2)))
3309 (set (match_dup 0)
3310 (if_then_else:DF (ge (match_dup 3)
3311 (const_int 0))
3312 (match_dup 1)
3313 (match_dup 2)))]
3314 "")
3315
3316 (define_expand "mindf3"
3317 [(set (match_dup 3)
3318 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
3319 (match_operand:DF 1 "gpc_reg_operand" "")))
3320 (set (match_operand:DF 0 "gpc_reg_operand" "")
3321 (if_then_else:DF (ge (match_dup 3)
3322 (const_int 0))
3323 (match_dup 1)
3324 (match_dup 2)))]
3325 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3326 "
3327 { operands[3] = gen_reg_rtx (DFmode); }")
3328
3329 (define_split
3330 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3331 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
3332 (match_operand:DF 2 "gpc_reg_operand" "")))
3333 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3334 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3335 [(set (match_dup 3)
3336 (minus:DF (match_dup 2) (match_dup 1)))
3337 (set (match_dup 0)
3338 (if_then_else:DF (ge (match_dup 3)
3339 (const_int 0))
3340 (match_dup 1)
3341 (match_dup 2)))]
3342 "")
3343
3344 (define_expand "movdfcc"
3345 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3346 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3347 (match_operand:DF 2 "gpc_reg_operand" "f")
3348 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3349 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3350 "
3351 {
3352 rtx temp, op0, op1;
3353 enum rtx_code code = GET_CODE (operands[1]);
3354 if (! rs6000_compare_fp_p)
3355 FAIL;
3356 switch (code)
3357 {
3358 case GE: case EQ: case NE:
3359 op0 = rs6000_compare_op0;
3360 op1 = rs6000_compare_op1;
3361 break;
3362 case GT:
3363 op0 = rs6000_compare_op1;
3364 op1 = rs6000_compare_op0;
3365 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3366 break;
3367 case LE:
3368 op0 = rs6000_compare_op1;
3369 op1 = rs6000_compare_op0;
3370 break;
3371 case LT:
3372 op0 = rs6000_compare_op0;
3373 op1 = rs6000_compare_op1;
3374 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3375 break;
3376 default:
3377 FAIL;
3378 }
3379 if (GET_MODE (rs6000_compare_op0) == DFmode)
3380 {
3381 temp = gen_reg_rtx (DFmode);
3382 emit_insn (gen_subdf3 (temp, op0, op1));
3383 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
3384 if (code == EQ)
3385 {
3386 emit_insn (gen_negdf2 (temp, temp));
3387 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
3388 }
3389 if (code == NE)
3390 {
3391 emit_insn (gen_negdf2 (temp, temp));
3392 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0]));
3393 }
3394 }
3395 else
3396 {
3397 temp = gen_reg_rtx (SFmode);
3398 emit_insn (gen_subsf3 (temp, op0, op1));
3399 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
3400 if (code == EQ)
3401 {
3402 emit_insn (gen_negsf2 (temp, temp));
3403 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
3404 }
3405 if (code == NE)
3406 {
3407 emit_insn (gen_negsf2 (temp, temp));
3408 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0]));
3409 }
3410 }
3411 DONE;
3412 }")
3413
3414 (define_insn "fseldfdf4"
3415 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3416 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3417 (const_int 0))
3418 (match_operand:DF 2 "gpc_reg_operand" "f")
3419 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3420 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3421 "fsel %0,%1,%2,%3"
3422 [(set_attr "type" "fp")])
3423
3424 (define_insn "fselsfdf4"
3425 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3426 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3427 (const_int 0))
3428 (match_operand:DF 2 "gpc_reg_operand" "f")
3429 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3430 "TARGET_PPC_GFXOPT"
3431 "fsel %0,%1,%2,%3"
3432 [(set_attr "type" "fp")])
3433 \f
3434 ;; Conversions to and from floating-point.
3435 (define_expand "floatsidf2"
3436 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3437 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))]
3438 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3439 "
3440 {
3441 if (operands[0])
3442 { /* prevent unused warning messages */
3443 rtx high = force_reg (SImode, GEN_INT (0x43300000));
3444 rtx low = gen_reg_rtx (SImode);
3445 rtx df = gen_reg_rtx (DFmode);
3446 rtx adjust = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
3447
3448 emit_insn (gen_xorsi3 (low, operands[1], GEN_INT (0x80000000)));
3449 emit_insn (gen_move_to_float (df, low, high));
3450 emit_insn (gen_subdf3 (operands[0], df, adjust));
3451 DONE;
3452 }
3453 }")
3454
3455 (define_expand "floatunssidf2"
3456 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3457 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))]
3458 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3459 "
3460 {
3461 if (operands[0])
3462 { /* prevent unused warning messages */
3463 rtx high = force_reg (SImode, GEN_INT (0x43300000));
3464 rtx df = gen_reg_rtx (DFmode);
3465 rtx adjust = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
3466
3467 emit_insn (gen_move_to_float (df, operands[1], high));
3468 emit_insn (gen_subdf3 (operands[0], df, adjust));
3469 DONE;
3470 }
3471 }")
3472
3473 (define_expand "move_to_float"
3474 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3475 (unspec [(match_operand:SI 1 "gpc_reg_operand" "")
3476 (match_operand:SI 2 "gpc_reg_operand" "")
3477 (match_dup 3)] 2))]
3478 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3479 "
3480 {
3481 operands[3] = XEXP (rs6000_stack_temp (DFmode, 8, 1), 0);
3482 }")
3483
3484 (define_split
3485 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3486 (unspec [(match_operand:SI 1 "gpc_reg_operand" "")
3487 (match_operand:SI 2 "gpc_reg_operand" "")
3488 (match_operand:SI 3 "offsettable_addr_operand" "")] 2))]
3489 "reload_completed"
3490 [(set (match_dup 4) (match_dup 1))
3491 (set (match_dup 5) (match_dup 2))
3492 (set (match_dup 0) (mem:DF (match_dup 3)))]
3493 "
3494 {
3495 rtx word1 = gen_rtx (MEM, SImode, operands[3]);
3496 rtx word2 = gen_rtx (MEM, SImode, plus_constant (operands[3], 4));
3497
3498 MEM_IN_STRUCT_P (word1) = 1;
3499 MEM_IN_STRUCT_P (word2) = 1;
3500
3501 if (WORDS_BIG_ENDIAN)
3502 {
3503 operands[4] = word2;
3504 operands[5] = word1;
3505 }
3506 else
3507 {
3508 operands[4] = word1;
3509 operands[5] = word2;
3510 }
3511 }")
3512
3513 (define_insn ""
3514 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3515 (unspec [(match_operand:SI 1 "gpc_reg_operand" "r")
3516 (match_operand:SI 2 "gpc_reg_operand" "r")
3517 (match_operand:SI 3 "offsettable_addr_operand" "p")] 2))]
3518 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3519 "#"
3520 [(set_attr "length" "12")])
3521
3522 (define_expand "fix_truncdfsi2"
3523 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3524 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
3525 "TARGET_HARD_FLOAT"
3526 "
3527 {
3528 if (TARGET_POWER2 || TARGET_POWERPC)
3529 {
3530 int endian = (WORDS_BIG_ENDIAN == 0);
3531 rtx stack_slot = rs6000_stack_temp (DImode, 8, 1);
3532 rtx temp = gen_reg_rtx (DImode);
3533
3534 emit_insn (gen_fpcvtsi (temp, operands[1]));
3535 emit_move_insn (stack_slot, temp);
3536 emit_move_insn (operands[0],
3537 operand_subword (stack_slot, 1 - endian, 0, DImode));
3538 DONE;
3539 }
3540 else
3541 {
3542 emit_insn (gen_trunc_call (operands[0], operands[1],
3543 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
3544 DONE;
3545 }
3546 }")
3547
3548 (define_insn "fpcvtsi"
3549 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3550 (sign_extend:DI
3551 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3552 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3553 "{fcirz|fctiwz} %0,%1"
3554 [(set_attr "type" "fp")])
3555
3556 (define_expand "fixuns_truncdfsi2"
3557 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3558 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
3559 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
3560 "
3561 {
3562 emit_insn (gen_trunc_call (operands[0], operands[1],
3563 gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
3564 DONE;
3565 }")
3566
3567 (define_expand "trunc_call"
3568 [(parallel [(set (match_operand:SI 0 "" "")
3569 (fix:SI (match_operand:DF 1 "" "")))
3570 (use (match_operand:SI 2 "" ""))])]
3571 "TARGET_HARD_FLOAT"
3572 "
3573 {
3574 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
3575 rtx first = XVECEXP (insns, 0, 0);
3576 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
3577
3578 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
3579 REG_NOTES (first));
3580 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
3581
3582 emit_insn (insns);
3583 DONE;
3584 }")
3585
3586 (define_expand "trunc_call_rtl"
3587 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
3588 (use (reg:DF 33))
3589 (parallel [(set (reg:SI 3)
3590 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
3591 (use (const_int 0))
3592 (clobber (scratch:SI))])
3593 (set (match_operand:SI 0 "gpc_reg_operand" "")
3594 (reg:SI 3))]
3595 "TARGET_HARD_FLOAT"
3596 "
3597 {
3598 rs6000_trunc_used = 1;
3599 }")
3600
3601 (define_insn "floatdidf2"
3602 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3603 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
3604 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3605 "fcfid %0,%1"
3606 [(set_attr "type" "fp")])
3607
3608 (define_insn "fix_truncdfdi2"
3609 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3610 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
3611 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3612 "fctidz %0,%1"
3613 [(set_attr "type" "fp")])
3614 \f
3615 ;; Define the DImode operations that can be done in a small number
3616 ;; of instructions. The & constraints are to prevent the register
3617 ;; allocator from allocating registers that overlap with the inputs
3618 ;; (for example, having an input in 7,8 and an output in 6,7). We
3619 ;; also allow for the the output being the same as one of the inputs.
3620
3621 (define_insn "*adddi3_noppc64"
3622 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
3623 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
3624 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
3625 "! TARGET_POWERPC64"
3626 "*
3627 {
3628 if (WORDS_BIG_ENDIAN)
3629 return (GET_CODE (operands[2])) != CONST_INT
3630 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
3631 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
3632 else
3633 return (GET_CODE (operands[2])) != CONST_INT
3634 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
3635 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
3636 }"
3637 [(set_attr "length" "8")])
3638
3639 (define_insn "*subdi3_noppc64"
3640 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
3641 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
3642 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
3643 "! TARGET_POWERPC64"
3644 "*
3645 {
3646 if (WORDS_BIG_ENDIAN)
3647 return (GET_CODE (operands[1]) != CONST_INT)
3648 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
3649 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
3650 else
3651 return (GET_CODE (operands[1]) != CONST_INT)
3652 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
3653 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
3654 }"
3655 [(set_attr "length" "8")])
3656
3657 (define_insn "*negdi2_noppc64"
3658 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
3659 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
3660 "! TARGET_POWERPC64"
3661 "*
3662 {
3663 return (WORDS_BIG_ENDIAN)
3664 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
3665 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
3666 }"
3667 [(set_attr "length" "8")])
3668
3669 (define_expand "mulsidi3"
3670 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3671 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3672 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
3673 ""
3674 "
3675 {
3676 if (! TARGET_POWER && ! TARGET_POWERPC)
3677 {
3678 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
3679 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
3680 emit_insn (gen_mull_call ());
3681 if (WORDS_BIG_ENDIAN)
3682 emit_move_insn (operands[0], gen_rtx (REG, DImode, 3));
3683 else
3684 {
3685 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
3686 gen_rtx (REG, SImode, 3));
3687 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
3688 gen_rtx (REG, SImode, 4));
3689 }
3690 DONE;
3691 }
3692 else if (TARGET_POWER)
3693 {
3694 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
3695 DONE;
3696 }
3697 }")
3698
3699 (define_insn "mulsidi3_mq"
3700 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3701 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
3702 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
3703 (clobber (match_scratch:SI 3 "=q"))]
3704 "TARGET_POWER"
3705 "mul %0,%1,%2\;mfmq %L0"
3706 [(set_attr "type" "imul")
3707 (set_attr "length" "8")])
3708
3709 (define_insn "*mulsidi3_powerpc"
3710 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
3711 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
3712 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
3713 "TARGET_POWERPC && ! TARGET_POWERPC64"
3714 "*
3715 {
3716 return (WORDS_BIG_ENDIAN)
3717 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
3718 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
3719 }"
3720 [(set_attr "type" "imul")
3721 (set_attr "length" "8")])
3722
3723 (define_split
3724 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3725 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3726 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
3727 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
3728 [(set (match_dup 3)
3729 (truncate:SI
3730 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3731 (sign_extend:DI (match_dup 2)))
3732 (const_int 32))))
3733 (set (match_dup 4)
3734 (mult:SI (match_dup 1)
3735 (match_dup 2)))]
3736 "
3737 {
3738 int endian = (WORDS_BIG_ENDIAN == 0);
3739 operands[3] = operand_subword (operands[0], endian, 0, DImode);
3740 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
3741 }")
3742
3743 (define_insn "umulsidi3"
3744 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
3745 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
3746 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
3747 "TARGET_POWERPC && ! TARGET_POWERPC64"
3748 "*
3749 {
3750 return (WORDS_BIG_ENDIAN)
3751 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
3752 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
3753 }"
3754 [(set_attr "type" "imul")
3755 (set_attr "length" "8")])
3756
3757 (define_split
3758 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3759 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3760 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
3761 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
3762 [(set (match_dup 3)
3763 (truncate:SI
3764 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3765 (zero_extend:DI (match_dup 2)))
3766 (const_int 32))))
3767 (set (match_dup 4)
3768 (mult:SI (match_dup 1)
3769 (match_dup 2)))]
3770 "
3771 {
3772 int endian = (WORDS_BIG_ENDIAN == 0);
3773 operands[3] = operand_subword (operands[0], endian, 0, DImode);
3774 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
3775 }")
3776
3777 (define_expand "smulsi3_highpart"
3778 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3779 (truncate:SI
3780 (lshiftrt:DI (mult:DI (sign_extend:DI
3781 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3782 (sign_extend:DI
3783 (match_operand:SI 2 "gpc_reg_operand" "r")))
3784 (const_int 32))))]
3785 ""
3786 "
3787 {
3788 if (! TARGET_POWER && ! TARGET_POWERPC)
3789 {
3790 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
3791 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
3792 emit_insn (gen_mulh_call ());
3793 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
3794 DONE;
3795 }
3796 else if (TARGET_POWER)
3797 {
3798 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
3799 DONE;
3800 }
3801 }")
3802
3803 (define_insn "smulsi3_highpart_mq"
3804 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3805 (truncate:SI
3806 (lshiftrt:DI (mult:DI (sign_extend:DI
3807 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3808 (sign_extend:DI
3809 (match_operand:SI 2 "gpc_reg_operand" "r")))
3810 (const_int 32))))
3811 (clobber (match_scratch:SI 3 "=q"))]
3812 "TARGET_POWER"
3813 "mul %0,%1,%2"
3814 [(set_attr "type" "imul")])
3815
3816 (define_insn ""
3817 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3818 (truncate:SI
3819 (lshiftrt:DI (mult:DI (sign_extend:DI
3820 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3821 (sign_extend:DI
3822 (match_operand:SI 2 "gpc_reg_operand" "r")))
3823 (const_int 32))))]
3824 "TARGET_POWERPC"
3825 "mulhw %0,%1,%2"
3826 [(set_attr "type" "imul")])
3827
3828 (define_insn "umulsi3_highpart"
3829 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3830 (truncate:SI
3831 (lshiftrt:DI (mult:DI (zero_extend:DI
3832 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3833 (zero_extend:DI
3834 (match_operand:SI 2 "gpc_reg_operand" "r")))
3835 (const_int 32))))]
3836 "TARGET_POWERPC"
3837 "mulhwu %0,%1,%2"
3838 [(set_attr "type" "imul")])
3839
3840 ;; If operands 0 and 2 are in the same register, we have a problem. But
3841 ;; operands 0 and 1 (the usual case) can be in the same register. That's
3842 ;; why we have the strange constraints below.
3843 (define_insn "ashldi3_power"
3844 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
3845 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
3846 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
3847 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
3848 "TARGET_POWER"
3849 "@
3850 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
3851 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
3852 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
3853 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
3854 [(set_attr "length" "8")])
3855
3856 (define_insn "lshrdi3_power"
3857 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
3858 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
3859 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
3860 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
3861 "TARGET_POWER"
3862 "@
3863 {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2
3864 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
3865 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
3866 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
3867 [(set_attr "length" "8")])
3868
3869 ;; Shift by a variable amount is too complex to be worth open-coding. We
3870 ;; just handle shifts by constants.
3871 (define_insn "ashrdi3_power"
3872 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3873 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
3874 (match_operand:SI 2 "const_int_operand" "M,i")))
3875 (clobber (match_scratch:SI 3 "=X,q"))]
3876 "TARGET_POWER"
3877 "@
3878 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
3879 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
3880 [(set_attr "length" "8")])
3881 \f
3882 ;; PowerPC64 DImode operations.
3883
3884 (define_expand "adddi3"
3885 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3886 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
3887 (match_operand:DI 2 "add_operand" "")))]
3888 ""
3889 "
3890 {
3891 if (! TARGET_POWERPC64 && non_add_cint_operand (operands[2], DImode))
3892 FAIL;
3893 }")
3894
3895 ;; Discourage ai/addic because of carry but provide it in an alternative
3896 ;; allowing register zero as source.
3897
3898 (define_insn ""
3899 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
3900 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
3901 (match_operand:DI 2 "add_operand" "r,I,I,J")))]
3902 "TARGET_POWERPC64"
3903 "@
3904 add %0,%1,%2
3905 addi %0,%1,%2
3906 addic %0,%1,%2
3907 addis %0,%1,%u2")
3908
3909 (define_insn ""
3910 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3911 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
3912 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
3913 (const_int 0)))
3914 (clobber (match_scratch:DI 3 "=r,r"))]
3915 "TARGET_POWERPC64"
3916 "@
3917 add. %3,%1,%2
3918 addic. %3,%1,%2"
3919 [(set_attr "type" "compare")])
3920
3921 (define_insn ""
3922 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3923 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
3924 (match_operand:DI 2 "reg_or_short_operand" "r,I"))
3925 (const_int 0)))
3926 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3927 (plus:DI (match_dup 1) (match_dup 2)))]
3928 "TARGET_POWERPC64"
3929 "@
3930 add. %0,%1,%2
3931 addic. %0,%1,%2"
3932 [(set_attr "type" "compare")])
3933
3934 ;; Split an add that we can't do in one insn into two insns, each of which
3935 ;; does one 16-bit part. This is used by combine. Note that the low-order
3936 ;; add should be last in case the result gets used in an address.
3937
3938 (define_split
3939 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3940 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
3941 (match_operand:DI 2 "non_add_cint_operand" "")))]
3942 "TARGET_POWERPC64"
3943 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
3944 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
3945 "
3946 {
3947 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
3948 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
3949
3950 if (low & 0x8000)
3951 high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
3952
3953 operands[3] = GEN_INT (high);
3954 operands[4] = GEN_INT (low);
3955 }")
3956
3957 (define_insn "one_cmpldi2"
3958 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3959 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
3960 "TARGET_POWERPC64"
3961 "nor %0,%1,%1")
3962
3963 (define_insn ""
3964 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3965 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
3966 (const_int 0)))
3967 (clobber (match_scratch:DI 2 "=r"))]
3968 "TARGET_POWERPC64"
3969 "nor. %2,%1,%1"
3970 [(set_attr "type" "compare")])
3971
3972 (define_insn ""
3973 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
3974 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
3975 (const_int 0)))
3976 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3977 (not:DI (match_dup 1)))]
3978 "TARGET_POWERPC64"
3979 "nor. %0,%2,%1"
3980 [(set_attr "type" "compare")])
3981
3982 (define_insn ""
3983 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3984 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
3985 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
3986 "TARGET_POWERPC64"
3987 "@
3988 subf %0,%2,%1
3989 subfic %0,%2,%1")
3990
3991 (define_insn ""
3992 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3993 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3994 (match_operand:DI 2 "gpc_reg_operand" "r"))
3995 (const_int 0)))
3996 (clobber (match_scratch:DI 3 "=r"))]
3997 "TARGET_POWERPC64"
3998 "subf. %3,%2,%1"
3999 [(set_attr "type" "compare")])
4000
4001 (define_insn ""
4002 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4003 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4004 (match_operand:DI 2 "gpc_reg_operand" "r"))
4005 (const_int 0)))
4006 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4007 (minus:DI (match_dup 1) (match_dup 2)))]
4008 "TARGET_POWERPC64"
4009 "subf. %0,%2,%1"
4010 [(set_attr "type" "compare")])
4011
4012 (define_expand "subdi3"
4013 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4014 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
4015 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4016 ""
4017 "
4018 {
4019 if (GET_CODE (operands[2]) == CONST_INT)
4020 {
4021 emit_insn (gen_adddi3 (operands[0], operands[1],
4022 negate_rtx (DImode, operands[2])));
4023 DONE;
4024 }
4025 }")
4026
4027 (define_insn "absdi2"
4028 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4029 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
4030 (clobber (match_scratch:DI 2 "=&r,&r"))]
4031 "TARGET_POWERPC64"
4032 "sradi %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0"
4033 [(set_attr "length" "12")])
4034
4035 (define_split
4036 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4037 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
4038 (clobber (match_scratch:DI 2 "=&r,&r"))]
4039 "TARGET_POWERPC64 && reload_completed"
4040 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 31)))
4041 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
4042 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
4043 "")
4044
4045 (define_insn ""
4046 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4047 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
4048 (clobber (match_scratch:DI 2 "=&r,&r"))]
4049 "TARGET_POWERPC64"
4050 "sradi %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2"
4051 [(set_attr "length" "12")])
4052
4053 (define_split
4054 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
4055 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
4056 (clobber (match_scratch:DI 2 "=&r,&r"))]
4057 "TARGET_POWERPC64 && reload_completed"
4058 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 31)))
4059 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
4060 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
4061 "")
4062
4063 (define_expand "negdi2"
4064 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4065 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
4066 ""
4067 "")
4068
4069 (define_insn ""
4070 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4071 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4072 "TARGET_POWERPC64"
4073 "neg %0,%1")
4074
4075 (define_insn ""
4076 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4077 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4078 (const_int 0)))
4079 (clobber (match_scratch:DI 2 "=r"))]
4080 "TARGET_POWERPC64"
4081 "neg. %2,%1"
4082 [(set_attr "type" "compare")])
4083
4084 (define_insn ""
4085 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4086 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4087 (const_int 0)))
4088 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4089 (neg:DI (match_dup 1)))]
4090 "TARGET_POWERPC64"
4091 "neg. %0,%1"
4092 [(set_attr "type" "compare")])
4093
4094 (define_insn "ffsdi2"
4095 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
4096 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
4097 "TARGET_POWERPC64"
4098 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
4099 [(set_attr "length" "16")])
4100
4101 (define_insn "muldi3"
4102 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4103 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4104 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4105 "TARGET_POWERPC64"
4106 "mulld %0,%1,%2"
4107 [(set_attr "type" "imul")])
4108
4109 (define_insn "smuldi3_highpart"
4110 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4111 (truncate:DI
4112 (lshiftrt:TI (mult:TI (sign_extend:TI
4113 (match_operand:DI 1 "gpc_reg_operand" "%r"))
4114 (sign_extend:TI
4115 (match_operand:DI 2 "gpc_reg_operand" "r")))
4116 (const_int 64))))]
4117 "TARGET_POWERPC64"
4118 "mulhd %0,%1,%2"
4119 [(set_attr "type" "imul")])
4120
4121 (define_insn "umuldi3_highpart"
4122 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4123 (truncate:DI
4124 (lshiftrt:TI (mult:TI (zero_extend:TI
4125 (match_operand:DI 1 "gpc_reg_operand" "%r"))
4126 (zero_extend:TI
4127 (match_operand:DI 2 "gpc_reg_operand" "r")))
4128 (const_int 64))))]
4129 "TARGET_POWERPC64"
4130 "mulhdu %0,%1,%2"
4131 [(set_attr "type" "imul")])
4132
4133 (define_expand "divdi3"
4134 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4135 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
4136 (match_operand:DI 2 "reg_or_cint_operand" "")))]
4137 "TARGET_POWERPC64"
4138 "
4139 {
4140 if (GET_CODE (operands[2]) == CONST_INT
4141 && exact_log2 (INTVAL (operands[2])) >= 0)
4142 ;
4143 else
4144 operands[2] = force_reg (DImode, operands[2]);
4145 }")
4146
4147 (define_expand "moddi3"
4148 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
4149 (use (match_operand:DI 1 "gpc_reg_operand" ""))
4150 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
4151 "TARGET_POWERPC64"
4152 "
4153 {
4154 int i = exact_log2 (INTVAL (operands[2]));
4155 rtx temp1;
4156 rtx temp2;
4157
4158 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
4159 FAIL;
4160
4161 temp1 = gen_reg_rtx (DImode);
4162 temp2 = gen_reg_rtx (DImode);
4163
4164 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
4165 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
4166 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
4167 DONE;
4168 }")
4169
4170 (define_insn ""
4171 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4172 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4173 (match_operand:DI 2 "const_int_operand" "N")))]
4174 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4175 "sradi %0,%1,%p2\;addze %0,%0"
4176 [(set_attr "length" "8")])
4177
4178 (define_insn ""
4179 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4180 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4181 (match_operand:DI 2 "const_int_operand" "N"))
4182 (const_int 0)))
4183 (clobber (match_scratch:DI 3 "=r"))]
4184 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4185 "sradi %3,%1,%p2\;addze. %3,%3"
4186 [(set_attr "type" "compare")
4187 (set_attr "length" "8")])
4188
4189 (define_insn ""
4190 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4191 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4192 (match_operand:DI 2 "const_int_operand" "N"))
4193 (const_int 0)))
4194 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4195 (div:DI (match_dup 1) (match_dup 2)))]
4196 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
4197 "sradi %0,%1,%p2\;addze. %0,%0"
4198 [(set_attr "type" "compare")
4199 (set_attr "length" "8")])
4200
4201 (define_insn ""
4202 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4203 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4204 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4205 "TARGET_POWERPC64"
4206 "divd %0,%1,%2"
4207 [(set_attr "type" "idiv")])
4208
4209 (define_insn "udivdi3"
4210 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4211 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4212 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4213 "TARGET_POWERPC64"
4214 "divdu %0,%1,%2"
4215 [(set_attr "type" "idiv")])
4216
4217 (define_insn "rotldi3"
4218 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4219 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4220 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
4221 "TARGET_POWERPC64"
4222 "rld%I2cl %0,%1,%h2,0")
4223
4224 (define_insn ""
4225 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4226 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4227 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4228 (const_int 0)))
4229 (clobber (match_scratch:DI 3 "=r"))]
4230 "TARGET_POWERPC64"
4231 "rld%I2cl. %3,%1,%h2,0"
4232 [(set_attr "type" "delayed_compare")])
4233
4234 (define_insn ""
4235 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4236 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4237 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
4238 (const_int 0)))
4239 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4240 (rotate:DI (match_dup 1) (match_dup 2)))]
4241 "TARGET_POWERPC64"
4242 "rld%I2cl. %0,%1,%h2,0"
4243 [(set_attr "type" "delayed_compare")])
4244
4245 (define_expand "ashldi3"
4246 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4247 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
4248 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4249 "TARGET_POWERPC64 || TARGET_POWER"
4250 "
4251 {
4252 if (TARGET_POWERPC64)
4253 ;
4254 else if (TARGET_POWER)
4255 {
4256 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
4257 DONE;
4258 }
4259 else
4260 FAIL;
4261 }")
4262
4263 (define_insn ""
4264 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4265 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4266 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4267 "TARGET_POWERPC64"
4268 "sld%I2 %0,%1,%2"
4269 [(set_attr "length" "8")])
4270
4271 (define_insn ""
4272 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4273 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4274 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4275 (const_int 0)))
4276 (clobber (match_scratch:DI 3 "=r"))]
4277 "TARGET_POWERPC64"
4278 "sld%I2. %3,%1,%2"
4279 [(set_attr "type" "delayed_compare")])
4280
4281 (define_insn ""
4282 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4283 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4284 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4285 (const_int 0)))
4286 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4287 (ashift:DI (match_dup 1) (match_dup 2)))]
4288 "TARGET_POWERPC64"
4289 "sld%I2. %0,%1,%2"
4290 [(set_attr "type" "delayed_compare")])
4291
4292 (define_expand "lshrdi3"
4293 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4294 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
4295 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4296 "TARGET_POWERPC64 || TARGET_POWER"
4297 "
4298 {
4299 if (TARGET_POWERPC64)
4300 ;
4301 else if (TARGET_POWER)
4302 {
4303 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
4304 DONE;
4305 }
4306 else
4307 FAIL;
4308 }")
4309
4310 (define_insn ""
4311 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4312 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4313 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4314 "TARGET_POWERPC64"
4315 "srd%I2 %0,%1,%2")
4316
4317 (define_insn ""
4318 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4319 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4320 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4321 (const_int 0)))
4322 (clobber (match_scratch:DI 3 "=r"))]
4323 "TARGET_POWERPC64"
4324 "srd%I2. %3,%1,%2"
4325 [(set_attr "type" "delayed_compare")])
4326
4327 (define_insn ""
4328 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4329 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4330 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4331 (const_int 0)))
4332 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4333 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
4334 "TARGET_POWERPC64"
4335 "srd%I2. %0,%1,%2"
4336 [(set_attr "type" "delayed_compare")])
4337
4338 (define_expand "ashrdi3"
4339 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4340 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
4341 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4342 "TARGET_POWERPC64 || TARGET_POWER"
4343 "
4344 {
4345 if (TARGET_POWERPC64)
4346 ;
4347 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
4348 {
4349 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
4350 DONE;
4351 }
4352 else
4353 FAIL;
4354 }")
4355
4356 (define_insn ""
4357 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4358 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4359 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4360 "TARGET_POWERPC64"
4361 "srad%I2 %0,%1,%2")
4362
4363 (define_insn ""
4364 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4365 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4366 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4367 (const_int 0)))
4368 (clobber (match_scratch:DI 3 "=r"))]
4369 "TARGET_POWERPC64"
4370 "srad%I2. %3,%1,%2"
4371 [(set_attr "type" "delayed_compare")])
4372
4373 (define_insn ""
4374 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4375 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4376 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4377 (const_int 0)))
4378 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4379 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
4380 "TARGET_POWERPC64"
4381 "srad%I2. %0,%1,%2"
4382 [(set_attr "type" "delayed_compare")])
4383
4384 (define_insn "anddi3"
4385 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4386 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4387 (match_operand:DI 2 "and_operand" "?r,K,J")))
4388 (clobber (match_scratch:CC 3 "=X,x,x"))]
4389 "TARGET_POWERPC64"
4390 "@
4391 and %0,%1,%2
4392 andi. %0,%1,%b2
4393 andis. %0,%1,%u2")
4394
4395 (define_insn ""
4396 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x")
4397 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4398 (match_operand:DI 2 "and_operand" "r,K,J"))
4399 (const_int 0)))
4400 (clobber (match_scratch:DI 3 "=r,r,r"))]
4401 "TARGET_POWERPC64"
4402 "@
4403 and. %3,%1,%2
4404 andi. %3,%1,%b2
4405 andis. %3,%1,%u2"
4406 [(set_attr "type" "compare,compare,compare")])
4407
4408 (define_insn ""
4409 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x")
4410 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4411 (match_operand:DI 2 "and_operand" "r,K,J"))
4412 (const_int 0)))
4413 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4414 (and:DI (match_dup 1) (match_dup 2)))]
4415 "TARGET_POWERPC64"
4416 "@
4417 and. %0,%1,%2
4418 andi. %0,%1,%b2
4419 andis. %0,%1,%u2"
4420 [(set_attr "type" "compare,compare,compare")])
4421
4422 ;; Take a AND with a constant that cannot be done in a single insn and try to
4423 ;; split it into two insns. This does not verify that the insns are valid
4424 ;; since this need not be done as combine will do it.
4425
4426 (define_split
4427 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4428 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
4429 (match_operand:DI 2 "non_and_cint_operand" "")))]
4430 "TARGET_POWERPC64"
4431 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
4432 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
4433 "
4434 {
4435 int maskval = INTVAL (operands[2]);
4436 int i, transitions, last_bit_value;
4437 int orig = maskval, first_c = maskval, second_c;
4438
4439 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
4440 the low-order bit and count for the third transition. When we get there,
4441 make a first mask that has everything to the left of that position
4442 a one. Then make the second mask to turn off whatever else is needed. */
4443
4444 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
4445 {
4446 if (((maskval >>= 1) & 1) != last_bit_value)
4447 last_bit_value ^= 1, transitions++;
4448
4449 if (transitions > 2)
4450 {
4451 first_c |= (~0) << i;
4452 break;
4453 }
4454 }
4455
4456 second_c = orig | ~ first_c;
4457
4458 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
4459 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
4460 }")
4461
4462 (define_insn "iordi3"
4463 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4464 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4465 (match_operand:DI 2 "logical_operand" "r,K,J")))]
4466 "TARGET_POWERPC64"
4467 "@
4468 or %0,%1,%2
4469 ori %0,%1,%b2
4470 oris %0,%1,%u2")
4471
4472 (define_insn ""
4473 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4474 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4475 (match_operand:DI 2 "gpc_reg_operand" "r"))
4476 (const_int 0)))
4477 (clobber (match_scratch:DI 3 "=r"))]
4478 "TARGET_POWERPC64"
4479 "or. %3,%1,%2"
4480 [(set_attr "type" "compare")])
4481
4482 (define_insn ""
4483 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4484 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4485 (match_operand:DI 2 "gpc_reg_operand" "r"))
4486 (const_int 0)))
4487 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4488 (ior:DI (match_dup 1) (match_dup 2)))]
4489 "TARGET_POWERPC64"
4490 "or. %0,%1,%2"
4491 [(set_attr "type" "compare")])
4492
4493 ;; Split an IOR that we can't do in one insn into two insns, each of which
4494 ;; does one 16-bit part. This is used by combine.
4495
4496 (define_split
4497 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4498 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
4499 (match_operand:DI 2 "non_logical_cint_operand" "")))]
4500 "TARGET_POWERPC64"
4501 [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3)))
4502 (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))]
4503 "
4504 {
4505 operands[3] = gen_rtx (CONST_INT, VOIDmode,
4506 INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
4507 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
4508 }")
4509
4510 (define_insn "xordi3"
4511 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
4512 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
4513 (match_operand:DI 2 "logical_operand" "r,K,J")))]
4514 "TARGET_POWERPC64"
4515 "@
4516 xor %0,%1,%2
4517 xori %0,%1,%b2
4518 xoris %0,%1,%u2")
4519
4520 (define_insn ""
4521 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4522 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4523 (match_operand:DI 2 "gpc_reg_operand" "r"))
4524 (const_int 0)))
4525 (clobber (match_scratch:DI 3 "=r"))]
4526 "TARGET_POWERPC64"
4527 "xor. %3,%1,%2"
4528 [(set_attr "type" "compare")])
4529
4530 (define_insn ""
4531 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4532 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4533 (match_operand:DI 2 "gpc_reg_operand" "r"))
4534 (const_int 0)))
4535 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4536 (xor:DI (match_dup 1) (match_dup 2)))]
4537 "TARGET_POWERPC64"
4538 "xor. %0,%1,%2"
4539 [(set_attr "type" "compare")])
4540
4541 ;; Split an XOR that we can't do in one insn into two insns, each of which
4542 ;; does one 16-bit part. This is used by combine.
4543
4544 (define_split
4545 [(set (match_operand:DI 0 "gpc_reg_operand" "")
4546 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
4547 (match_operand:DI 2 "non_logical_cint_operand" "")))]
4548 "TARGET_POWERPC64"
4549 [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3)))
4550 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))]
4551 "
4552 {
4553 operands[3] = gen_rtx (CONST_INT, VOIDmode,
4554 INTVAL (operands[2]) & 0xffff0000);
4555 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
4556 }")
4557
4558 (define_insn ""
4559 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4560 (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4561 (match_operand:DI 2 "gpc_reg_operand" "r"))))]
4562 "TARGET_POWERPC64"
4563 "eqv %0,%1,%2")
4564
4565 (define_insn ""
4566 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4567 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4568 (match_operand:DI 2 "gpc_reg_operand" "r")))
4569 (const_int 0)))
4570 (clobber (match_scratch:DI 3 "=r"))]
4571 "TARGET_POWERPC64"
4572 "eqv. %3,%1,%2"
4573 [(set_attr "type" "compare")])
4574
4575 (define_insn ""
4576 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4577 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
4578 (match_operand:DI 2 "gpc_reg_operand" "r")))
4579 (const_int 0)))
4580 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4581 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
4582 "TARGET_POWERPC64"
4583 "eqv. %0,%1,%2"
4584 [(set_attr "type" "compare")])
4585
4586 (define_insn ""
4587 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4588 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4589 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4590 "TARGET_POWERPC64"
4591 "andc %0,%2,%1")
4592
4593 (define_insn ""
4594 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4595 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4596 (match_operand:DI 2 "gpc_reg_operand" "r"))
4597 (const_int 0)))
4598 (clobber (match_scratch:DI 3 "=r"))]
4599 "TARGET_POWERPC64"
4600 "andc. %3,%2,%1"
4601 [(set_attr "type" "compare")])
4602
4603 (define_insn ""
4604 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4605 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4606 (match_operand:DI 2 "gpc_reg_operand" "r"))
4607 (const_int 0)))
4608 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4609 (and:DI (not:DI (match_dup 1)) (match_dup 2)))]
4610 "TARGET_POWERPC64"
4611 "andc. %0,%2,%1"
4612 [(set_attr "type" "compare")])
4613
4614 (define_insn ""
4615 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4616 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4617 (match_operand:DI 2 "gpc_reg_operand" "r")))]
4618 "TARGET_POWERPC64"
4619 "orc %0,%2,%1")
4620
4621 (define_insn ""
4622 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4623 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4624 (match_operand:DI 2 "gpc_reg_operand" "r"))
4625 (const_int 0)))
4626 (clobber (match_scratch:DI 3 "=r"))]
4627 "TARGET_POWERPC64"
4628 "orc. %3,%2,%1"
4629 [(set_attr "type" "compare")])
4630
4631 (define_insn ""
4632 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4633 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
4634 (match_operand:DI 2 "gpc_reg_operand" "r"))
4635 (const_int 0)))
4636 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4637 (ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
4638 "TARGET_POWERPC64"
4639 "orc. %0,%2,%1"
4640 [(set_attr "type" "compare")])
4641
4642 (define_insn ""
4643 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4644 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4645 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
4646 "TARGET_POWERPC64"
4647 "nand %0,%1,%2")
4648
4649 (define_insn ""
4650 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4651 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4652 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
4653 (const_int 0)))
4654 (clobber (match_scratch:DI 3 "=r"))]
4655 "TARGET_POWERPC64"
4656 "nand. %3,%1,%2"
4657 [(set_attr "type" "compare")])
4658
4659 (define_insn ""
4660 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4661 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4662 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
4663 (const_int 0)))
4664 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4665 (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
4666 "TARGET_POWERPC64"
4667 "nand. %0,%1,%2"
4668 [(set_attr "type" "compare")])
4669
4670 (define_insn ""
4671 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4672 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4673 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
4674 "TARGET_POWERPC64"
4675 "nor %0,%1,%2")
4676
4677 (define_insn ""
4678 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4679 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4680 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
4681 (const_int 0)))
4682 (clobber (match_scratch:DI 3 "=r"))]
4683 "TARGET_POWERPC64"
4684 "nor. %3,%1,%2"
4685 [(set_attr "type" "compare")])
4686
4687 (define_insn ""
4688 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4689 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "%r"))
4690 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r")))
4691 (const_int 0)))
4692 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4693 (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
4694 "TARGET_POWERPC64"
4695 "nor. %0,%1,%2"
4696 [(set_attr "type" "compare")])
4697 \f
4698 ;; Now define ways of moving data around.
4699
4700 ;; Elf specific ways of loading addresses for non-PIC code.
4701 ;; The output of this could be r0, but we limit it to base
4702 ;; registers, since almost all uses of this will need it
4703 ;; in a base register shortly.
4704 (define_insn "elf_high"
4705 [(set (match_operand:SI 0 "register_operand" "=b")
4706 (high:SI (match_operand 1 "" "")))]
4707 "TARGET_ELF && !TARGET_64BIT"
4708 "{cau|addis} %0,0,%1@ha")
4709
4710 (define_insn "elf_low"
4711 [(set (match_operand:SI 0 "register_operand" "=r")
4712 (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
4713 (match_operand 2 "" "")))]
4714 "TARGET_ELF && !TARGET_64BIT"
4715 "{cal %0,%a2@l(%1)|addi %0,%1,%2@l}")
4716
4717 ;; For SI, we special-case integers that can't be loaded in one insn. We
4718 ;; do the load 16-bits at a time. We could do this by loading from memory,
4719 ;; and this is even supposed to be faster, but it is simpler not to get
4720 ;; integers in the TOC.
4721 (define_expand "movsi"
4722 [(set (match_operand:SI 0 "general_operand" "")
4723 (match_operand:SI 1 "any_operand" ""))]
4724 ""
4725 "
4726 {
4727 if (GET_CODE (operands[0]) != REG)
4728 operands[1] = force_reg (SImode, operands[1]);
4729
4730 /* Convert a move of a CONST_DOUBLE into a CONST_INT */
4731 if (GET_CODE (operands[1]) == CONST_DOUBLE)
4732 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
4733
4734 /* Use default pattern for address of ELF small data */
4735 if (TARGET_ELF
4736 && DEFAULT_ABI == ABI_V4
4737 && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
4738 && small_data_operand (operands[1], SImode))
4739 {
4740 emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
4741 DONE;
4742 }
4743
4744 if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
4745 && CONSTANT_P (operands[1])
4746 && GET_CODE (operands[1]) != HIGH
4747 && GET_CODE (operands[1]) != CONST_INT)
4748 {
4749 rtx target = (reload_completed || reload_in_progress)
4750 ? operands[0] : gen_reg_rtx (SImode);
4751
4752 /* If this is a function address on -mcall-aixdesc or -mcall-nt,
4753 convert it to the address of the descriptor. */
4754 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
4755 && GET_CODE (operands[1]) == SYMBOL_REF
4756 && XSTR (operands[1], 0)[0] == '.')
4757 {
4758 char *name = XSTR (operands[1], 0);
4759 rtx new_ref;
4760 while (*name == '.')
4761 name++;
4762 new_ref = gen_rtx (SYMBOL_REF, Pmode, name);
4763 CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[1]);
4764 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
4765 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4766 operands[1] = new_ref;
4767 }
4768
4769 emit_insn (gen_elf_high (target, operands[1]));
4770 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4771 DONE;
4772 }
4773
4774 if (GET_CODE (operands[1]) == CONST
4775 && DEFAULT_ABI == ABI_NT
4776 && !side_effects_p (operands[0]))
4777 {
4778 rtx const_term = const0_rtx;
4779 rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term);
4780 if (sym && GET_CODE (const_term) == CONST_INT
4781 && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
4782 {
4783 unsigned HOST_WIDE_INT value = INTVAL (const_term);
4784 int new_reg_p = (flag_expensive_optimizations
4785 && !reload_completed
4786 && !reload_in_progress);
4787 rtx tmp1 = (new_reg_p && value != 0) ? gen_reg_rtx (SImode) : operands[0];
4788
4789 emit_insn (gen_movsi (tmp1, sym));
4790 if (INTVAL (const_term) != 0)
4791 {
4792 if (value + 0x8000 < 0x10000)
4793 emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value)));
4794
4795 else
4796 {
4797 HOST_WIDE_INT high_int = value & (~ (HOST_WIDE_INT) 0xffff);
4798 HOST_WIDE_INT low_int = value & 0xffff;
4799 rtx tmp2 = (!new_reg_p || !low_int) ? operands[0] : gen_reg_rtx (Pmode);
4800
4801 if (low_int & 0x8000)
4802 high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16;
4803
4804 emit_insn (gen_addsi3 (tmp2, tmp1, GEN_INT (high_int)));
4805 if (low_int)
4806 emit_insn (gen_addsi3 (operands[0], tmp2, GEN_INT (low_int)));
4807 }
4808 }
4809 DONE;
4810 }
4811 else
4812 fatal_insn (\"bad address\", operands[1]);
4813 }
4814
4815 if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
4816 && CONSTANT_P (operands[1])
4817 && GET_CODE (operands[1]) != CONST_INT
4818 && GET_CODE (operands[1]) != HIGH
4819 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
4820 {
4821 /* If we are to limit the number of things we put in the TOC and
4822 this is a symbol plus a constant we can add in one insn,
4823 just put the symbol in the TOC and add the constant. Don't do
4824 this if reload is in progress. */
4825 if (GET_CODE (operands[1]) == CONST
4826 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4827 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4828 && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
4829 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4830 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4831 && ! side_effects_p (operands[0]))
4832 {
4833 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
4834 rtx other = XEXP (XEXP (operands[1], 0), 1);
4835
4836 emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
4837 DONE;
4838 }
4839
4840 operands[1] = force_const_mem (SImode, operands[1]);
4841 if (! memory_address_p (SImode, XEXP (operands[1], 0))
4842 && ! reload_in_progress)
4843 operands[1] = change_address (operands[1], SImode,
4844 XEXP (operands[1], 0));
4845 }
4846 }")
4847
4848 (define_insn ""
4849 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
4850 (match_operand:SI 1 "input_operand" "r,S,T,U,m,r,I,J,n,R,*h,r,r,0"))]
4851 "gpc_reg_operand (operands[0], SImode)
4852 || gpc_reg_operand (operands[1], SImode)"
4853 "@
4854 mr %0,%1
4855 {l|lwz} %0,[toc]%1(2)
4856 {l|lwz} %0,[toc]%l1(2)
4857 {cal|la} %0,%a1
4858 {l%U1%X1|lwz%U1%X1} %0,%1
4859 {st%U0%X0|stw%U0%X0} %1,%0
4860 {lil|li} %0,%1
4861 {liu|lis} %0,%u1
4862 #
4863 {cal|la} %0,%1(%*)
4864 mf%1 %0
4865 mt%0 %1
4866 mt%0 %1
4867 cror 0,0,0"
4868 [(set_attr "type" "*,load,load,*,load,*,*,*,*,*,*,*,mtjmpr,*")
4869 (set_attr "length" "4,4,4,4,4,4,4,4,8,4,4,4,4,4")])
4870
4871 ;; Split a load of a large constant into the appropriate two-insn
4872 ;; sequence.
4873
4874 (define_split
4875 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4876 (match_operand:SI 1 "const_int_operand" ""))]
4877 "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
4878 && (INTVAL (operands[1]) & 0xffff) != 0"
4879 [(set (match_dup 0)
4880 (match_dup 2))
4881 (set (match_dup 0)
4882 (ior:SI (match_dup 0)
4883 (match_dup 3)))]
4884 "
4885 {
4886 operands[2] = gen_rtx (CONST_INT, VOIDmode,
4887 INTVAL (operands[1]) & 0xffff0000);
4888 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
4889 }")
4890
4891 (define_insn ""
4892 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4893 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
4894 (const_int 0)))
4895 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
4896 ""
4897 "mr. %0,%1"
4898 [(set_attr "type" "compare")])
4899 \f
4900 (define_expand "movhi"
4901 [(set (match_operand:HI 0 "general_operand" "")
4902 (match_operand:HI 1 "any_operand" ""))]
4903 ""
4904 "
4905 {
4906 if (GET_CODE (operands[0]) != REG)
4907 operands[1] = force_reg (HImode, operands[1]);
4908
4909 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
4910 {
4911 operands[1] = force_const_mem (HImode, operands[1]);
4912 if (! memory_address_p (HImode, XEXP (operands[1], 0))
4913 && ! reload_in_progress)
4914 operands[1] = change_address (operands[1], HImode,
4915 XEXP (operands[1], 0));
4916 }
4917 }")
4918
4919 (define_insn ""
4920 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
4921 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
4922 "gpc_reg_operand (operands[0], HImode)
4923 || gpc_reg_operand (operands[1], HImode)"
4924 "@
4925 mr %0,%1
4926 lhz%U1%X1 %0,%1
4927 sth%U0%X0 %1,%0
4928 {lil|li} %0,%w1
4929 mf%1 %0
4930 mt%0 %1
4931 mt%0 %1
4932 cror 0,0,0"
4933 [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
4934
4935 (define_expand "movqi"
4936 [(set (match_operand:QI 0 "general_operand" "")
4937 (match_operand:QI 1 "any_operand" ""))]
4938 ""
4939 "
4940 {
4941 if (GET_CODE (operands[0]) != REG)
4942 operands[1] = force_reg (QImode, operands[1]);
4943
4944 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
4945 {
4946 operands[1] = force_const_mem (QImode, operands[1]);
4947 if (! memory_address_p (QImode, XEXP (operands[1], 0))
4948 && ! reload_in_progress)
4949 operands[1] = change_address (operands[1], QImode,
4950 XEXP (operands[1], 0));
4951 }
4952 }")
4953
4954 (define_insn ""
4955 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
4956 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
4957 "gpc_reg_operand (operands[0], QImode)
4958 || gpc_reg_operand (operands[1], QImode)"
4959 "@
4960 mr %0,%1
4961 lbz%U1%X1 %0,%1
4962 stb%U0%X0 %1,%0
4963 {lil|li} %0,%1
4964 mf%1 %0
4965 mt%0 %1
4966 mt%0 %1
4967 cror 0,0,0"
4968 [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
4969 \f
4970 ;; Here is how to move condition codes around. When we store CC data in
4971 ;; an integer register or memory, we store just the high-order 4 bits.
4972 ;; This lets us not shift in the most common case of CR0.
4973 (define_expand "movcc"
4974 [(set (match_operand:CC 0 "nonimmediate_operand" "")
4975 (match_operand:CC 1 "nonimmediate_operand" ""))]
4976 ""
4977 "")
4978
4979 (define_insn ""
4980 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
4981 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
4982 "register_operand (operands[0], CCmode)
4983 || register_operand (operands[1], CCmode)"
4984 "@
4985 mcrf %0,%1
4986 mtcrf 128,%1
4987 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
4988 mfcr %0
4989 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
4990 mr %0,%1
4991 {l%U1%X1|lwz%U1%X1} %0,%1
4992 {st%U0%U1|stw%U0%U1} %1,%0"
4993 [(set_attr "type" "*,*,*,compare,*,*,load,*")
4994 (set_attr "length" "*,*,12,*,8,*,*,*")])
4995 \f
4996 ;; For floating-point, we normally deal with the floating-point registers
4997 ;; unless -msoft-float is used. The sole exception is that parameter passing
4998 ;; can produce floating-point values in fixed-point registers. Unless the
4999 ;; value is a simple constant or already in memory, we deal with this by
5000 ;; allocating memory and copying the value explicitly via that memory location.
5001 (define_expand "movsf"
5002 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5003 (match_operand:SF 1 "any_operand" ""))]
5004 ""
5005 "
5006 {
5007 /* If we are called from reload, we might be getting a SUBREG of a hard
5008 reg. So expand it. */
5009 if (GET_CODE (operands[0]) == SUBREG
5010 && GET_CODE (SUBREG_REG (operands[0])) == REG
5011 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
5012 operands[0] = alter_subreg (operands[0]);
5013 if (GET_CODE (operands[1]) == SUBREG
5014 && GET_CODE (SUBREG_REG (operands[1])) == REG
5015 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
5016 operands[1] = alter_subreg (operands[1]);
5017
5018 if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM)
5019 operands[1] = force_reg (SFmode, operands[1]);
5020
5021 else if (TARGET_HARD_FLOAT)
5022 {
5023 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
5024 {
5025 /* If this is a store to memory or another integer register do the
5026 move directly. Otherwise store to a temporary stack slot and
5027 load from there into a floating point register. */
5028
5029 if (GET_CODE (operands[0]) == MEM
5030 || (GET_CODE (operands[0]) == REG
5031 && (REGNO (operands[0]) < 32
5032 || (reload_in_progress
5033 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
5034 {
5035 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
5036 operand_subword (operands[1], 0, 0, SFmode));
5037 DONE;
5038 }
5039 else
5040 {
5041 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
5042
5043 emit_move_insn (stack_slot, operands[1]);
5044 emit_move_insn (operands[0], stack_slot);
5045 DONE;
5046 }
5047 }
5048
5049 if (GET_CODE (operands[0]) == MEM)
5050 {
5051 /* If operands[1] is a register, it may have double-precision data
5052 in it, so truncate it to single precision. We need not do
5053 this for POWERPC. */
5054 if (! TARGET_POWERPC && TARGET_HARD_FLOAT
5055 && GET_CODE (operands[1]) == REG)
5056 {
5057 rtx newreg
5058 = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
5059 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
5060 operands[1] = newreg;
5061 }
5062
5063 operands[1] = force_reg (SFmode, operands[1]);
5064 }
5065
5066 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
5067 {
5068 if (GET_CODE (operands[1]) == MEM
5069 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
5070 || GET_CODE (operands[1]) == CONST_DOUBLE
5071 #endif
5072 || (GET_CODE (operands[1]) == REG
5073 && (REGNO (operands[1]) < 32
5074 || (reload_in_progress
5075 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
5076 {
5077 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
5078 operand_subword (operands[1], 0, 0, SFmode));
5079 DONE;
5080 }
5081 else
5082 {
5083 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
5084
5085 emit_move_insn (stack_slot, operands[1]);
5086 emit_move_insn (operands[0], stack_slot);
5087 DONE;
5088 }
5089 }
5090 }
5091
5092 if (CONSTANT_P (operands[1]))
5093 {
5094 operands[1] = force_const_mem (SFmode, operands[1]);
5095 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
5096 && ! reload_in_progress)
5097 operands[1] = change_address (operands[1], SFmode,
5098 XEXP (operands[1], 0));
5099 }
5100 }")
5101
5102 (define_split
5103 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5104 (match_operand:SF 1 "easy_fp_constant" ""))]
5105 "reload_completed && REGNO (operands[0]) <= 31"
5106 [(set (match_dup 2) (match_dup 3))]
5107 "
5108 { operands[2] = operand_subword (operands[0], 0, 0, SFmode);
5109 operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
5110
5111 (define_insn ""
5112 [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
5113 (match_operand:SF 1 "input_operand" "f,m,f"))]
5114 "(gpc_reg_operand (operands[0], SFmode)
5115 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
5116 "@
5117 fmr %0,%1
5118 lfs%U1%X1 %0,%1
5119 stfs%U0%X0 %1,%0"
5120 [(set_attr "type" "fp,fpload,*")])
5121
5122 (define_insn ""
5123 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
5124 (match_operand:SF 1 "input_operand" "r,m,r,I,J,R"))]
5125 "(gpc_reg_operand (operands[0], SFmode)
5126 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
5127 "@
5128 mr %0,%1
5129 {l%U1%X1|lwz%U1%X1} %0,%1
5130 {st%U0%X0|stw%U0%X0} %1,%0
5131 {lil|li} %0,%1
5132 {liu|lis} %0,%u1
5133 {cal|la} %0,%1(%*)"
5134 [(set_attr "type" "*,load,*,*,*,*")])
5135
5136 \f
5137 (define_expand "movdf"
5138 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5139 (match_operand:DF 1 "any_operand" ""))]
5140 ""
5141 "
5142 {
5143 if (GET_CODE (operands[0]) != REG)
5144 operands[1] = force_reg (DFmode, operands[1]);
5145
5146 /* Stores between FPR and any non-FPR registers must go through a
5147 temporary stack slot. */
5148
5149 if (TARGET_POWERPC64
5150 && GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
5151 && ((FP_REGNO_P (REGNO (operands[0]))
5152 && ! FP_REGNO_P (REGNO (operands[1])))
5153 || (FP_REGNO_P (REGNO (operands[1]))
5154 && ! FP_REGNO_P (REGNO (operands[0])))))
5155 {
5156 rtx stack_slot = assign_stack_temp (DFmode, 8, 0);
5157
5158 emit_move_insn (stack_slot, operands[1]);
5159 emit_move_insn (operands[0], stack_slot);
5160 DONE;
5161 }
5162
5163 if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
5164 {
5165 operands[1] = force_const_mem (DFmode, operands[1]);
5166 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
5167 && ! reload_in_progress)
5168 operands[1] = change_address (operands[1], DFmode,
5169 XEXP (operands[1], 0));
5170 }
5171 }")
5172
5173 (define_split
5174 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5175 (match_operand:DF 1 "easy_fp_constant" ""))]
5176 "reload_completed && REGNO (operands[0]) <= 31"
5177 [(set (match_dup 2) (match_dup 3))
5178 (set (match_dup 4) (match_dup 5))]
5179 "
5180 { operands[2] = operand_subword (operands[0], 0, 0, DFmode);
5181 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
5182 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
5183 operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
5184
5185 ;; Don't have reload use general registers to load a constant. First,
5186 ;; it might not work if the output operand has is the equivalent of
5187 ;; a non-offsettable memref, but also it is less efficient than loading
5188 ;; the constant into an FP register, since it will probably be used there.
5189 ;; The "??" is a kludge until we can figure out a more reasonable way
5190 ;; of handling these non-offsettable values.
5191 (define_insn ""
5192 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
5193 (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
5194 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
5195 && (register_operand (operands[0], DFmode)
5196 || register_operand (operands[1], DFmode))"
5197 "*
5198 {
5199 switch (which_alternative)
5200 {
5201 case 0:
5202 /* We normally copy the low-numbered register first. However, if
5203 the first register operand 0 is the same as the second register of
5204 operand 1, we must copy in the opposite order. */
5205 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
5206 return \"mr %L0,%L1\;mr %0,%1\";
5207 else
5208 return \"mr %0,%1\;mr %L0,%L1\";
5209 case 1:
5210 /* If the low-address word is used in the address, we must load it
5211 last. Otherwise, load it first. Note that we cannot have
5212 auto-increment in that case since the address register is known to be
5213 dead. */
5214 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5215 operands [1], 0))
5216 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
5217 else
5218 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
5219 case 2:
5220 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
5221 case 3:
5222 return \"#\";
5223 case 4:
5224 return \"fmr %0,%1\";
5225 case 5:
5226 return \"lfd%U1%X1 %0,%1\";
5227 case 6:
5228 return \"stfd%U0%X0 %1,%0\";
5229 }
5230 }"
5231 [(set_attr "type" "*,load,*,*,fp,fpload,*")
5232 (set_attr "length" "8,8,8,8,*,*,*")])
5233
5234 (define_insn ""
5235 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
5236 (match_operand:DF 1 "input_operand" "r,o,r,G"))]
5237 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5238 && (register_operand (operands[0], DFmode)
5239 || register_operand (operands[1], DFmode))"
5240 "*
5241 {
5242 switch (which_alternative)
5243 {
5244 case 0:
5245 /* We normally copy the low-numbered register first. However, if
5246 the first register operand 0 is the same as the second register of
5247 operand 1, we must copy in the opposite order. */
5248 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
5249 return \"mr %L0,%L1\;mr %0,%1\";
5250 else
5251 return \"mr %0,%1\;mr %L0,%L1\";
5252 case 1:
5253 /* If the low-address word is used in the address, we must load it
5254 last. Otherwise, load it first. Note that we cannot have
5255 auto-increment in that case since the address register is known to be
5256 dead. */
5257 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5258 operands [1], 0))
5259 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
5260 else
5261 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
5262 case 2:
5263 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
5264 case 3:
5265 return \"#\";
5266 }
5267 }"
5268 [(set_attr "type" "*,load,*,*")
5269 (set_attr "length" "8,8,8,8")])
5270
5271 (define_insn ""
5272 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
5273 (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
5274 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
5275 && (register_operand (operands[0], DFmode)
5276 || register_operand (operands[1], DFmode))"
5277 "@
5278 mr %0,%1
5279 ld%U1%X1 %0,%1
5280 std%U0%X0 %1,%0
5281 #
5282 fmr %0,%1
5283 lfd%U1%X1 %0,%1
5284 stfd%U0%X0 %1,%0"
5285 [(set_attr "type" "*,load,*,*,fp,fpload,*")])
5286
5287 (define_insn ""
5288 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
5289 (match_operand:DF 1 "input_operand" "r,o,r,G"))]
5290 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5291 && (register_operand (operands[0], DFmode)
5292 || register_operand (operands[1], DFmode))"
5293 "@
5294 mr %0,%1
5295 ld%U1%X1 %0,%1
5296 std%U0%X0 %1,%0
5297 #"
5298 [(set_attr "type" "*,load,*,*")])
5299 \f
5300 ;; Next come the multi-word integer load and store and the load and store
5301 ;; multiple insns.
5302 (define_expand "movdi"
5303 [(set (match_operand:DI 0 "general_operand" "")
5304 (match_operand:DI 1 "any_operand" ""))]
5305 ""
5306 "
5307 {
5308 if (! TARGET_64BIT && ! general_operand (operands[1], DImode))
5309 FAIL;
5310
5311 if (GET_CODE (operands[0]) != REG)
5312 operands[1] = force_reg (DImode, operands[1]);
5313
5314 if (GET_CODE (operands[1]) == CONST_DOUBLE
5315 || GET_CODE (operands[1]) == CONST_INT)
5316 {
5317 HOST_WIDE_INT low;
5318 HOST_WIDE_INT high;
5319
5320 if (GET_CODE (operands[1]) == CONST_DOUBLE)
5321 {
5322 low = CONST_DOUBLE_LOW (operands[1]);
5323 high = CONST_DOUBLE_HIGH (operands[1]);
5324 }
5325 else if (HOST_BITS_PER_WIDE_INT <= 32)
5326 {
5327 low = INTVAL (operands[1]);
5328 high = (low < 0) ? ~0 : 0;
5329 }
5330 else
5331 {
5332 low = INTVAL (operands[1]) & 0xffffffff;
5333 high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
5334 }
5335
5336 if (! TARGET_POWERPC64)
5337 {
5338 emit_move_insn (gen_rtx (SUBREG, SImode, operands[0],
5339 WORDS_BIG_ENDIAN), GEN_INT (low));
5340
5341 emit_move_insn (gen_rtx (SUBREG, SImode, operands[0],
5342 ! WORDS_BIG_ENDIAN), GEN_INT (high));
5343 DONE;
5344 }
5345 else
5346 {
5347 if (high + 0x8000 >= 0x10000)
5348 {
5349 emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], 1),
5350 GEN_INT (high));
5351 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT(32)));
5352 if (low)
5353 {
5354 HOST_WIDE_INT low_low = low & 0xffff;
5355 HOST_WIDE_INT low_high = low & (~ (HOST_WIDE_INT) 0xffff);
5356 if (low_high)
5357 emit_insn (gen_iordi3 (operands[0], operands[0],
5358 GEN_INT (low_high)));
5359 if (low_low)
5360 emit_insn (gen_iordi3 (operands[0], operands[0],
5361 GEN_INT (low_low)));
5362 }
5363 }
5364 else if (low)
5365 emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], 1),
5366 GEN_INT (low));
5367 DONE;
5368 }
5369 }
5370
5371 /* Stores between FPR and any non-FPR registers must go through a
5372 temporary stack slot. */
5373
5374 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
5375 && ((FP_REGNO_P (REGNO (operands[0]))
5376 && ! FP_REGNO_P (REGNO (operands[1])))
5377 || (FP_REGNO_P (REGNO (operands[1]))
5378 && ! FP_REGNO_P (REGNO (operands[0])))))
5379 {
5380 rtx stack_slot = assign_stack_temp (DImode, 8, 0);
5381
5382 emit_move_insn (stack_slot, operands[1]);
5383 emit_move_insn (operands[0], stack_slot);
5384 DONE;
5385 }
5386 }")
5387
5388 (define_insn ""
5389 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m")
5390 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f"))]
5391 "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
5392 || gpc_reg_operand (operands[1], DImode))"
5393 "*
5394 {
5395 switch (which_alternative)
5396 {
5397 case 0:
5398 /* We normally copy the low-numbered register first. However, if
5399 the first register operand 0 is the same as the second register of
5400 operand 1, we must copy in the opposite order. */
5401 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
5402 return \"mr %L0,%L1\;mr %0,%1\";
5403 else
5404 return \"mr %0,%1\;mr %L0,%L1\";
5405 case 1:
5406 /* If the low-address word is used in the address, we must load it
5407 last. Otherwise, load it first. Note that we cannot have
5408 auto-increment in that case since the address register is known to be
5409 dead. */
5410 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5411 operands [1], 0))
5412 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
5413 else
5414 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
5415 case 2:
5416 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
5417 case 3:
5418 return \"fmr %0,%1\";
5419 case 4:
5420 return \"lfd%U1%X1 %0,%1\";
5421 case 5:
5422 return \"stfd%U0%X0 %1,%0\";
5423 }
5424 }"
5425 [(set_attr "type" "*,load,*,fp,fpload,*")
5426 (set_attr "length" "8,8,8,*,*,*")])
5427
5428 (define_insn ""
5429 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
5430 (match_operand:DI 1 "input_operand" "r,m,r,I,J,n,R,f,m,f,*h,r,0"))]
5431 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
5432 || gpc_reg_operand (operands[1], DImode))"
5433 "@
5434 mr %0,%1
5435 ld%U1%X1 %0,%1
5436 std%U0%X0 %1,%0
5437 li %0,%1
5438 lis %0,%u1
5439 #
5440 {cal|la} %0,%1(%*)
5441 fmr %0,%1
5442 lfd%U1%X1 %0,%1
5443 stfd%U0%X0 %1,%0
5444 mf%1 %0
5445 mt%0 %1
5446 cror 0,0,0"
5447 [(set_attr "type" "*,load,*,*,*,*,*,fp,fpload,*,*,mtjmpr,*")
5448 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
5449
5450 ;; Split a load of a large constant into the appropriate five-instruction
5451 ;; sequence. The expansion in movdi tries to perform the minimum number of
5452 ;; steps, but here we have to handle anything in a constant number of insns.
5453
5454 (define_split
5455 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5456 (match_operand:DI 1 "const_double_operand" ""))]
5457 "TARGET_POWERPC64"
5458 [(set (match_dup 0)
5459 (match_dup 2))
5460 (set (match_dup 0)
5461 (ior:DI (match_dup 0)
5462 (match_dup 3)))
5463 (set (match_dup 0)
5464 (ashift:DI (match_dup 0)
5465 (const_int 32)))
5466 (set (match_dup 0)
5467 (ior:DI (match_dup 0)
5468 (match_dup 4)))
5469 (set (match_dup 0)
5470 (ior:DI (match_dup 0)
5471 (match_dup 5)))]
5472 "
5473 {
5474 HOST_WIDE_INT low;
5475 HOST_WIDE_INT high;
5476
5477 if (GET_CODE (operands[1]) == CONST_DOUBLE)
5478 {
5479 low = CONST_DOUBLE_LOW (operands[1]);
5480 high = CONST_DOUBLE_HIGH (operands[1]);
5481 }
5482 else if (HOST_BITS_PER_WIDE_INT <= 32)
5483 {
5484 low = INTVAL (operands[1]);
5485 high = (low < 0) ? ~0 : 0;
5486 }
5487 else
5488 {
5489 low = INTVAL (operands[1]) & 0xffffffff;
5490 high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
5491 }
5492
5493 if ((high + 0x8000) < 0x10000
5494 && ((low & 0xffff) == 0 || (low & (~ (HOST_WIDE_INT) 0xffff)) == 0))
5495 FAIL;
5496
5497 operands[2] = GEN_INT (high & (~ (HOST_WIDE_INT) 0xffff));
5498 operands[3] = GEN_INT (high & 0xffff);
5499 operands[4] = GEN_INT (low & (~ (HOST_WIDE_INT) 0xffff));
5500 operands[5] = GEN_INT (low & 0xffff);
5501 }")
5502
5503 (define_insn ""
5504 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
5505 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
5506 (const_int 0)))
5507 (set (match_operand:DI 0 "gpc_reg_operand" "=r") (match_dup 1))]
5508 "TARGET_POWERPC64"
5509 "mr. %0,%1"
5510 [(set_attr "type" "compare")])
5511 \f
5512 ;; TImode is similar, except that we usually want to compute the address into
5513 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
5514 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
5515 (define_expand "movti"
5516 [(parallel [(set (match_operand:TI 0 "general_operand" "")
5517 (match_operand:TI 1 "general_operand" ""))
5518 (clobber (scratch:SI))])]
5519 "TARGET_STRING || TARGET_POWERPC64"
5520 "
5521 {
5522 if (GET_CODE (operands[0]) == MEM)
5523 operands[1] = force_reg (TImode, operands[1]);
5524
5525 if (GET_CODE (operands[0]) == MEM
5526 && GET_CODE (XEXP (operands[0], 0)) != REG
5527 && ! reload_in_progress)
5528 operands[0] = change_address (operands[0], TImode,
5529 copy_addr_to_reg (XEXP (operands[0], 0)));
5530
5531 if (GET_CODE (operands[1]) == MEM
5532 && GET_CODE (XEXP (operands[1], 0)) != REG
5533 && ! reload_in_progress)
5534 operands[1] = change_address (operands[1], TImode,
5535 copy_addr_to_reg (XEXP (operands[1], 0)));
5536 }")
5537
5538 ;; We say that MQ is clobbered in the last alternative because the first
5539 ;; alternative would never get used otherwise since it would need a reload
5540 ;; while the 2nd alternative would not. We put memory cases first so they
5541 ;; are preferred. Otherwise, we'd try to reload the output instead of
5542 ;; giving the SCRATCH mq.
5543 (define_insn ""
5544 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
5545 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
5546 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
5547 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
5548 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
5549 "*
5550 {
5551 switch (which_alternative)
5552 {
5553 default:
5554 abort ();
5555
5556 case 0:
5557 return \"{stsi|stswi} %1,%P0,16\";
5558
5559 case 1:
5560 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
5561
5562 case 2:
5563 /* Normally copy registers with lowest numbered register copied first.
5564 But copy in the other order if the first register of the output
5565 is the second, third, or fourth register in the input. */
5566 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
5567 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
5568 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
5569 else
5570 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
5571 case 3:
5572 /* If the address is not used in the output, we can use lsi. Otherwise,
5573 fall through to generating four loads. */
5574 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
5575 return \"{lsi|lswi} %0,%P1,16\";
5576 /* ... fall through ... */
5577 case 4:
5578 /* If the address register is the same as the register for the lowest-
5579 addressed word, load it last. Similarly for the next two words.
5580 Otherwise load lowest address to highest. */
5581 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5582 operands[1], 0))
5583 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
5584 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
5585 REGNO (operands[0]) + 2, operands[1], 0))
5586 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
5587 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
5588 REGNO (operands[0]) + 3, operands[1], 0))
5589 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
5590 else
5591 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
5592 }
5593 }"
5594 [(set_attr "type" "*,load,load,*,*")
5595 (set_attr "length" "*,16,16,*,16")])
5596
5597 (define_insn ""
5598 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
5599 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
5600 (clobber (match_scratch:SI 2 "=X,X,X"))]
5601 "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
5602 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
5603 "*
5604 {
5605 switch (which_alternative)
5606 {
5607 default:
5608 abort ();
5609
5610 case 0:
5611 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
5612
5613 case 1:
5614 /* Normally copy registers with lowest numbered register copied first.
5615 But copy in the other order if the first register of the output
5616 is the second, third, or fourth register in the input. */
5617 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
5618 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
5619 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
5620 else
5621 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
5622 case 2:
5623 /* If the address register is the same as the register for the lowest-
5624 addressed word, load it last. Similarly for the next two words.
5625 Otherwise load lowest address to highest. */
5626 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5627 operands[1], 0))
5628 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
5629 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
5630 REGNO (operands[0]) + 2, operands[1], 0))
5631 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
5632 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
5633 REGNO (operands[0]) + 3, operands[1], 0))
5634 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
5635 else
5636 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
5637 }
5638 }"
5639 [(set_attr "type" "load,*,*")
5640 (set_attr "length" "16,16,16")])
5641
5642 (define_insn ""
5643 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
5644 (match_operand:TI 1 "input_operand" "r,m,r"))]
5645 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
5646 || gpc_reg_operand (operands[1], TImode))"
5647 "*
5648 {
5649 switch (which_alternative)
5650 {
5651 case 0:
5652 /* We normally copy the low-numbered register first. However, if
5653 the first register operand 0 is the same as the second register of
5654 operand 1, we must copy in the opposite order. */
5655 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
5656 return \"mr %L0,%L1\;mr %0,%1\";
5657 else
5658 return \"mr %0,%1\;mr %L0,%L1\";
5659 case 1:
5660 /* If the low-address word is used in the address, we must load it
5661 last. Otherwise, load it first. Note that we cannot have
5662 auto-increment in that case since the address register is known to be
5663 dead. */
5664 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
5665 operands [1], 0))
5666 return \"ld %L0,%L1\;ld %0,%1\";
5667 else
5668 return \"ld%U1 %0,%1\;ld %L0,%L1\";
5669 case 2:
5670 return \"std%U0 %1,%0\;std %L1,%L0\";
5671 }
5672 }"
5673 [(set_attr "type" "*,load,*")
5674 (set_attr "length" "8,8,8")])
5675 \f
5676 (define_expand "load_multiple"
5677 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
5678 (match_operand:SI 1 "" ""))
5679 (use (match_operand:SI 2 "" ""))])]
5680 "TARGET_STRING"
5681 "
5682 {
5683 int regno;
5684 int count;
5685 rtx from;
5686 int i;
5687
5688 /* Support only loading a constant number of fixed-point registers from
5689 memory and only bother with this if more than two; the machine
5690 doesn't support more than eight. */
5691 if (GET_CODE (operands[2]) != CONST_INT
5692 || INTVAL (operands[2]) <= 2
5693 || INTVAL (operands[2]) > 8
5694 || GET_CODE (operands[1]) != MEM
5695 || GET_CODE (operands[0]) != REG
5696 || REGNO (operands[0]) >= 32)
5697 FAIL;
5698
5699 count = INTVAL (operands[2]);
5700 regno = REGNO (operands[0]);
5701
5702 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
5703 from = force_reg (SImode, XEXP (operands[1], 0));
5704
5705 for (i = 0; i < count; i++)
5706 XVECEXP (operands[3], 0, i)
5707 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
5708 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
5709 }")
5710
5711 (define_insn ""
5712 [(match_parallel 0 "load_multiple_operation"
5713 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
5714 (mem:SI (match_operand:SI 2 "register_operand" "b")))])]
5715 "TARGET_STRING"
5716 "*
5717 {
5718 /* We have to handle the case where the pseudo used to contain the address
5719 is assigned to one of the output registers. */
5720 int i, j;
5721 int words = XVECLEN (operands[0], 0);
5722 rtx xop[10];
5723
5724 if (XVECLEN (operands[0], 0) == 1)
5725 return \"{l|lwz} %1,0(%2)\";
5726
5727 for (i = 0; i < words; i++)
5728 if (refers_to_regno_p (REGNO (operands[1]) + i,
5729 REGNO (operands[1]) + i + 1, operands[2], 0))
5730 {
5731 if (i == words-1)
5732 {
5733 xop[0] = operands[1];
5734 xop[1] = operands[2];
5735 xop[2] = GEN_INT (4 * (words-1));
5736 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
5737 return \"\";
5738 }
5739 else if (i == 0)
5740 {
5741 xop[0] = operands[1];
5742 xop[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
5743 xop[2] = GEN_INT (4 * (words-1));
5744 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
5745 return \"\";
5746 }
5747 else
5748 {
5749 for (j = 0; j < words; j++)
5750 if (j != i)
5751 {
5752 xop[0] = gen_rtx (REG, SImode, REGNO (operands[1]) + j);
5753 xop[1] = operands[2];
5754 xop[2] = GEN_INT (j * 4);
5755 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
5756 }
5757 xop[0] = operands[2];
5758 xop[1] = GEN_INT (i * 4);
5759 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
5760 return \"\";
5761 }
5762 }
5763
5764 return \"{lsi|lswi} %1,%2,%N0\";
5765 }"
5766 [(set_attr "type" "load")
5767 (set_attr "length" "32")])
5768 \f
5769
5770 (define_expand "store_multiple"
5771 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
5772 (match_operand:SI 1 "" ""))
5773 (clobber (scratch:SI))
5774 (use (match_operand:SI 2 "" ""))])]
5775 "TARGET_STRING"
5776 "
5777 {
5778 int regno;
5779 int count;
5780 rtx to;
5781 int i;
5782
5783 /* Support only storing a constant number of fixed-point registers to
5784 memory and only bother with this if more than two; the machine
5785 doesn't support more than eight. */
5786 if (GET_CODE (operands[2]) != CONST_INT
5787 || INTVAL (operands[2]) <= 2
5788 || INTVAL (operands[2]) > 8
5789 || GET_CODE (operands[0]) != MEM
5790 || GET_CODE (operands[1]) != REG
5791 || REGNO (operands[1]) >= 32)
5792 FAIL;
5793
5794 count = INTVAL (operands[2]);
5795 regno = REGNO (operands[1]);
5796
5797 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
5798 to = force_reg (SImode, XEXP (operands[0], 0));
5799
5800 XVECEXP (operands[3], 0, 0)
5801 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
5802 XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
5803 gen_rtx (SCRATCH, SImode));
5804
5805 for (i = 1; i < count; i++)
5806 XVECEXP (operands[3], 0, i + 1)
5807 = gen_rtx (SET, VOIDmode,
5808 gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
5809 gen_rtx (REG, SImode, regno + i));
5810 }")
5811
5812 (define_insn ""
5813 [(match_parallel 0 "store_multiple_operation"
5814 [(set (match_operand:SI 1 "indirect_operand" "=Q")
5815 (match_operand:SI 2 "gpc_reg_operand" "r"))
5816 (clobber (match_scratch:SI 3 "=q"))])]
5817 "TARGET_STRING && TARGET_POWER"
5818 "{stsi|stswi} %2,%P1,%O0")
5819
5820 (define_insn ""
5821 [(match_parallel 0 "store_multiple_operation"
5822 [(set (mem:SI (match_operand:SI 1 "register_operand" "b"))
5823 (match_operand:SI 2 "gpc_reg_operand" "r"))
5824 (clobber (match_scratch:SI 3 "X"))])]
5825 "TARGET_STRING && !TARGET_POWER"
5826 "{stsi|stswi} %2,%1,%O0")
5827
5828 \f
5829 ;; String/block move insn.
5830 ;; Argument 0 is the destination
5831 ;; Argument 1 is the source
5832 ;; Argument 2 is the length
5833 ;; Argument 3 is the alignment
5834
5835 (define_expand "movstrsi"
5836 [(parallel [(set (match_operand:BLK 0 "" "")
5837 (match_operand:BLK 1 "" ""))
5838 (use (match_operand:SI 2 "" ""))
5839 (use (match_operand:SI 3 "" ""))])]
5840 ""
5841 "
5842 {
5843 if (expand_block_move (operands))
5844 DONE;
5845 else
5846 FAIL;
5847 }")
5848
5849 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
5850 ;; register allocator doesn't have a clue about allocating 8 word registers
5851 (define_expand "movstrsi_8reg"
5852 [(parallel [(set (match_operand 0 "" "")
5853 (match_operand 1 "" ""))
5854 (use (match_operand 2 "" ""))
5855 (use (match_operand 3 "" ""))
5856 (clobber (reg:SI 5))
5857 (clobber (reg:SI 6))
5858 (clobber (reg:SI 7))
5859 (clobber (reg:SI 8))
5860 (clobber (reg:SI 9))
5861 (clobber (reg:SI 10))
5862 (clobber (reg:SI 11))
5863 (clobber (reg:SI 12))
5864 (clobber (match_scratch:SI 4 ""))])]
5865 "TARGET_STRING"
5866 "")
5867
5868 (define_insn ""
5869 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
5870 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
5871 (use (match_operand:SI 2 "immediate_operand" "i"))
5872 (use (match_operand:SI 3 "immediate_operand" "i"))
5873 (clobber (match_operand:SI 4 "register_operand" "=r"))
5874 (clobber (reg:SI 6))
5875 (clobber (reg:SI 7))
5876 (clobber (reg:SI 8))
5877 (clobber (reg:SI 9))
5878 (clobber (reg:SI 10))
5879 (clobber (reg:SI 11))
5880 (clobber (reg:SI 12))
5881 (clobber (match_scratch:SI 5 "=q"))]
5882 "TARGET_STRING && TARGET_POWER
5883 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
5884 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
5885 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
5886 && REGNO (operands[4]) == 5"
5887 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
5888 [(set_attr "length" "8")])
5889
5890 (define_insn ""
5891 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
5892 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
5893 (use (match_operand:SI 2 "immediate_operand" "i"))
5894 (use (match_operand:SI 3 "immediate_operand" "i"))
5895 (clobber (match_operand:SI 4 "register_operand" "=r"))
5896 (clobber (reg:SI 6))
5897 (clobber (reg:SI 7))
5898 (clobber (reg:SI 8))
5899 (clobber (reg:SI 9))
5900 (clobber (reg:SI 10))
5901 (clobber (reg:SI 11))
5902 (clobber (reg:SI 12))
5903 (clobber (match_scratch:SI 5 "X"))]
5904 "TARGET_STRING && !TARGET_POWER
5905 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
5906 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
5907 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
5908 && REGNO (operands[4]) == 5"
5909 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
5910 [(set_attr "length" "8")])
5911
5912 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
5913 ;; register allocator doesn't have a clue about allocating 6 word registers
5914 (define_expand "movstrsi_6reg"
5915 [(parallel [(set (match_operand 0 "" "")
5916 (match_operand 1 "" ""))
5917 (use (match_operand 2 "" ""))
5918 (use (match_operand 3 "" ""))
5919 (clobber (reg:SI 7))
5920 (clobber (reg:SI 8))
5921 (clobber (reg:SI 9))
5922 (clobber (reg:SI 10))
5923 (clobber (reg:SI 11))
5924 (clobber (reg:SI 12))
5925 (clobber (match_scratch:SI 4 ""))])]
5926 "TARGET_STRING"
5927 "")
5928
5929 (define_insn ""
5930 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
5931 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
5932 (use (match_operand:SI 2 "immediate_operand" "i"))
5933 (use (match_operand:SI 3 "immediate_operand" "i"))
5934 (clobber (match_operand:SI 4 "register_operand" "=r"))
5935 (clobber (reg:SI 8))
5936 (clobber (reg:SI 9))
5937 (clobber (reg:SI 10))
5938 (clobber (reg:SI 11))
5939 (clobber (reg:SI 12))
5940 (clobber (match_scratch:SI 5 "=q"))]
5941 "TARGET_STRING && TARGET_POWER
5942 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
5943 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
5944 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
5945 && REGNO (operands[4]) == 7"
5946 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
5947 [(set_attr "length" "8")])
5948
5949 (define_insn ""
5950 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
5951 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
5952 (use (match_operand:SI 2 "immediate_operand" "i"))
5953 (use (match_operand:SI 3 "immediate_operand" "i"))
5954 (clobber (match_operand:SI 4 "register_operand" "=r"))
5955 (clobber (reg:SI 8))
5956 (clobber (reg:SI 9))
5957 (clobber (reg:SI 10))
5958 (clobber (reg:SI 11))
5959 (clobber (reg:SI 12))
5960 (clobber (match_scratch:SI 5 "X"))]
5961 "TARGET_STRING && !TARGET_POWER
5962 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
5963 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
5964 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
5965 && REGNO (operands[4]) == 7"
5966 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
5967 [(set_attr "length" "8")])
5968
5969 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
5970 ;; with TImode
5971 (define_expand "movstrsi_4reg"
5972 [(parallel [(set (match_operand 0 "" "")
5973 (match_operand 1 "" ""))
5974 (use (match_operand 2 "" ""))
5975 (use (match_operand 3 "" ""))
5976 (clobber (reg:SI 9))
5977 (clobber (reg:SI 10))
5978 (clobber (reg:SI 11))
5979 (clobber (reg:SI 12))
5980 (clobber (match_scratch:SI 4 ""))])]
5981 "TARGET_STRING"
5982 "")
5983
5984 (define_insn ""
5985 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
5986 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
5987 (use (match_operand:SI 2 "immediate_operand" "i"))
5988 (use (match_operand:SI 3 "immediate_operand" "i"))
5989 (clobber (match_operand:SI 4 "register_operand" "=r"))
5990 (clobber (reg:SI 10))
5991 (clobber (reg:SI 11))
5992 (clobber (reg:SI 12))
5993 (clobber (match_scratch:SI 5 "=q"))]
5994 "TARGET_STRING && TARGET_POWER
5995 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
5996 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
5997 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
5998 && REGNO (operands[4]) == 9"
5999 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6000 [(set_attr "length" "8")])
6001
6002 (define_insn ""
6003 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6004 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6005 (use (match_operand:SI 2 "immediate_operand" "i"))
6006 (use (match_operand:SI 3 "immediate_operand" "i"))
6007 (clobber (match_operand:SI 4 "register_operand" "=r"))
6008 (clobber (reg:SI 10))
6009 (clobber (reg:SI 11))
6010 (clobber (reg:SI 12))
6011 (clobber (match_scratch:SI 5 "X"))]
6012 "TARGET_STRING && !TARGET_POWER
6013 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
6014 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
6015 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
6016 && REGNO (operands[4]) == 9"
6017 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6018 [(set_attr "length" "8")])
6019
6020 ;; Move up to 8 bytes at a time.
6021 (define_expand "movstrsi_2reg"
6022 [(parallel [(set (match_operand 0 "" "")
6023 (match_operand 1 "" ""))
6024 (use (match_operand 2 "" ""))
6025 (use (match_operand 3 "" ""))
6026 (clobber (match_scratch:DI 4 ""))
6027 (clobber (match_scratch:SI 5 ""))])]
6028 "TARGET_STRING && !TARGET_64BIT"
6029 "")
6030
6031 (define_insn ""
6032 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6033 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6034 (use (match_operand:SI 2 "immediate_operand" "i"))
6035 (use (match_operand:SI 3 "immediate_operand" "i"))
6036 (clobber (match_scratch:DI 4 "=&r"))
6037 (clobber (match_scratch:SI 5 "=q"))]
6038 "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
6039 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
6040 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6041 [(set_attr "length" "8")])
6042
6043 (define_insn ""
6044 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6045 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6046 (use (match_operand:SI 2 "immediate_operand" "i"))
6047 (use (match_operand:SI 3 "immediate_operand" "i"))
6048 (clobber (match_scratch:DI 4 "=&r"))
6049 (clobber (match_scratch:SI 5 "X"))]
6050 "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
6051 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
6052 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6053 [(set_attr "length" "8")])
6054
6055 ;; Move up to 4 bytes at a time.
6056 (define_expand "movstrsi_1reg"
6057 [(parallel [(set (match_operand 0 "" "")
6058 (match_operand 1 "" ""))
6059 (use (match_operand 2 "" ""))
6060 (use (match_operand 3 "" ""))
6061 (clobber (match_scratch:SI 4 ""))
6062 (clobber (match_scratch:SI 5 ""))])]
6063 "TARGET_STRING"
6064 "")
6065
6066 (define_insn ""
6067 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6068 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6069 (use (match_operand:SI 2 "immediate_operand" "i"))
6070 (use (match_operand:SI 3 "immediate_operand" "i"))
6071 (clobber (match_scratch:SI 4 "=&r"))
6072 (clobber (match_scratch:SI 5 "=q"))]
6073 "TARGET_STRING && TARGET_POWER
6074 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
6075 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6076 [(set_attr "length" "8")])
6077
6078 (define_insn ""
6079 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
6080 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
6081 (use (match_operand:SI 2 "immediate_operand" "i"))
6082 (use (match_operand:SI 3 "immediate_operand" "i"))
6083 (clobber (match_scratch:SI 4 "=&r"))
6084 (clobber (match_scratch:SI 5 "X"))]
6085 "TARGET_STRING && !TARGET_POWER
6086 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
6087 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
6088 [(set_attr "length" "8")])
6089
6090 \f
6091 ;; Define insns that do load or store with update. Some of these we can
6092 ;; get by using pre-decrement or pre-increment, but the hardware can also
6093 ;; do cases where the increment is not the size of the object.
6094 ;;
6095 ;; In all these cases, we use operands 0 and 1 for the register being
6096 ;; incremented because those are the operands that local-alloc will
6097 ;; tie and these are the pair most likely to be tieable (and the ones
6098 ;; that will benefit the most).
6099
6100 (define_insn ""
6101 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
6102 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
6103 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
6104 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
6105 (plus:DI (match_dup 1) (match_dup 2)))]
6106 "TARGET_POWERPC64"
6107 "@
6108 ldux %3,%0,%2
6109 ldu %3,%2(%0)"
6110 [(set_attr "type" "load")])
6111
6112 (define_insn ""
6113 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
6114 (sign_extend:DI
6115 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
6116 (match_operand:DI 2 "gpc_reg_operand" "r")))))
6117 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
6118 (plus:DI (match_dup 1) (match_dup 2)))]
6119 "TARGET_POWERPC64"
6120 "lwaux %3,%0,%2"
6121 [(set_attr "type" "load")])
6122
6123 (define_insn "movdi_update"
6124 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
6125 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
6126 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
6127 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
6128 (plus:DI (match_dup 1) (match_dup 2)))]
6129 "TARGET_POWERPC64"
6130 "@
6131 stdux %3,%0,%2
6132 stdu %3,%2(%0)")
6133
6134 (define_insn ""
6135 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6136 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6137 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6138 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6139 (plus:SI (match_dup 1) (match_dup 2)))]
6140 ""
6141 "@
6142 {lux|lwzux} %3,%0,%2
6143 {lu|lwzu} %3,%2(%0)"
6144 [(set_attr "type" "load")])
6145
6146 (define_insn "movsi_update"
6147 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6148 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6149 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6150 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6151 (plus:SI (match_dup 1) (match_dup 2)))]
6152 ""
6153 "@
6154 {stux|stwux} %3,%0,%2
6155 {stu|stwu} %3,%2(%0)")
6156
6157 (define_insn ""
6158 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
6159 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6160 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6161 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6162 (plus:SI (match_dup 1) (match_dup 2)))]
6163 ""
6164 "@
6165 lhzux %3,%0,%2
6166 lhzu %3,%2(%0)"
6167 [(set_attr "type" "load")])
6168
6169 (define_insn ""
6170 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6171 (zero_extend:SI
6172 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6173 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
6174 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6175 (plus:SI (match_dup 1) (match_dup 2)))]
6176 ""
6177 "@
6178 lhzux %3,%0,%2
6179 lhzu %3,%2(%0)"
6180 [(set_attr "type" "load")])
6181
6182 (define_insn ""
6183 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6184 (sign_extend:SI
6185 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6186 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
6187 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6188 (plus:SI (match_dup 1) (match_dup 2)))]
6189 ""
6190 "@
6191 lhaux %3,%0,%2
6192 lhau %3,%2(%0)"
6193 [(set_attr "type" "load")])
6194
6195 (define_insn ""
6196 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6197 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6198 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
6199 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6200 (plus:SI (match_dup 1) (match_dup 2)))]
6201 ""
6202 "@
6203 sthux %3,%0,%2
6204 sthu %3,%2(%0)")
6205
6206 (define_insn ""
6207 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
6208 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6209 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6210 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6211 (plus:SI (match_dup 1) (match_dup 2)))]
6212 ""
6213 "@
6214 lbzux %3,%0,%2
6215 lbzu %3,%2(%0)"
6216 [(set_attr "type" "load")])
6217
6218 (define_insn ""
6219 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
6220 (zero_extend:SI
6221 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6222 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
6223 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6224 (plus:SI (match_dup 1) (match_dup 2)))]
6225 ""
6226 "@
6227 lbzux %3,%0,%2
6228 lbzu %3,%2(%0)"
6229 [(set_attr "type" "load")])
6230
6231 (define_insn ""
6232 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6233 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6234 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
6235 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6236 (plus:SI (match_dup 1) (match_dup 2)))]
6237 ""
6238 "@
6239 stbux %3,%0,%2
6240 stbu %3,%2(%0)")
6241
6242 (define_insn ""
6243 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
6244 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6245 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6246 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6247 (plus:SI (match_dup 1) (match_dup 2)))]
6248 "TARGET_HARD_FLOAT"
6249 "@
6250 lfsux %3,%0,%2
6251 lfsu %3,%2(%0)"
6252 [(set_attr "type" "fpload")])
6253
6254 (define_insn ""
6255 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6256 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6257 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
6258 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6259 (plus:SI (match_dup 1) (match_dup 2)))]
6260 "TARGET_HARD_FLOAT"
6261 "@
6262 stfsux %3,%0,%2
6263 stfsu %3,%2(%0)")
6264
6265 (define_insn ""
6266 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
6267 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6268 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
6269 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6270 (plus:SI (match_dup 1) (match_dup 2)))]
6271 "TARGET_HARD_FLOAT"
6272 "@
6273 lfdux %3,%0,%2
6274 lfdu %3,%2(%0)"
6275 [(set_attr "type" "fpload")])
6276
6277 (define_insn ""
6278 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
6279 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
6280 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
6281 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
6282 (plus:SI (match_dup 1) (match_dup 2)))]
6283 "TARGET_HARD_FLOAT"
6284 "@
6285 stfdux %3,%0,%2
6286 stfdu %3,%2(%0)")
6287
6288 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
6289
6290 (define_peephole
6291 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6292 (match_operand:DF 1 "memory_operand" ""))
6293 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
6294 (match_operand:DF 3 "memory_operand" ""))]
6295 "TARGET_POWER2
6296 && TARGET_HARD_FLOAT
6297 && registers_ok_for_quad_peep (operands[0], operands[2])
6298 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
6299 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
6300 "lfq%U1%X1 %0,%1")
6301
6302 (define_peephole
6303 [(set (match_operand:DF 0 "memory_operand" "")
6304 (match_operand:DF 1 "gpc_reg_operand" "f"))
6305 (set (match_operand:DF 2 "memory_operand" "")
6306 (match_operand:DF 3 "gpc_reg_operand" "f"))]
6307 "TARGET_POWER2
6308 && TARGET_HARD_FLOAT
6309 && registers_ok_for_quad_peep (operands[1], operands[3])
6310 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
6311 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
6312 "stfq%U0%X0 %1,%0")
6313 \f
6314 ;; Next come insns related to the calling sequence.
6315 ;;
6316 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
6317 ;; We move the back-chain and decrement the stack pointer.
6318
6319 (define_expand "allocate_stack"
6320 [(set (reg:SI 1)
6321 (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))]
6322 ""
6323 "
6324 { rtx chain = gen_reg_rtx (Pmode);
6325 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
6326 rtx neg_op0;
6327
6328 emit_move_insn (chain, stack_bot);
6329
6330 /* Under Windows NT, we need to add stack probes for large/variable allocations,
6331 so do it via a call to the external function alloca, instead of doing it
6332 inline. */
6333 if (DEFAULT_ABI == ABI_NT
6334 && (GET_CODE (operands[0]) != CONST_INT || INTVAL (operands[0]) > 4096))
6335 {
6336 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, \"__allocate_stack\"), 0,
6337 VOIDmode, 1,
6338 operands[0], Pmode);
6339 DONE;
6340 }
6341
6342 if (GET_CODE (operands[0]) != CONST_INT
6343 || INTVAL (operands[0]) < -32767
6344 || INTVAL (operands[0]) > 32768)
6345 {
6346 neg_op0 = gen_reg_rtx (Pmode);
6347 if (TARGET_32BIT)
6348 emit_insn (gen_negsi2 (neg_op0, operands[0]));
6349 else
6350 emit_insn (gen_negdi2 (neg_op0, operands[0]));
6351 }
6352 else
6353 neg_op0 = GEN_INT (- INTVAL (operands[0]));
6354
6355 if (TARGET_32BIT)
6356 emit_insn (gen_movsi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
6357 else
6358 emit_insn (gen_movdi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
6359
6360 DONE;
6361 }")
6362
6363 ;; These patterns say how to save and restore the stack pointer. We need not
6364 ;; save the stack pointer at function level since we are careful to
6365 ;; preserve the backchain. At block level, we have to restore the backchain
6366 ;; when we restore the stack pointer.
6367 ;;
6368 ;; For nonlocal gotos, we must save both the stack pointer and its
6369 ;; backchain and restore both. Note that in the nonlocal case, the
6370 ;; save area is a memory location.
6371
6372 (define_expand "save_stack_function"
6373 [(use (const_int 0))]
6374 ""
6375 "")
6376
6377 (define_expand "restore_stack_function"
6378 [(use (const_int 0))]
6379 ""
6380 "")
6381
6382 (define_expand "restore_stack_block"
6383 [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
6384 (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
6385 (set (mem:SI (match_dup 0)) (match_dup 2))]
6386 ""
6387 "
6388 { operands[2] = gen_reg_rtx (SImode); }")
6389
6390 (define_expand "save_stack_nonlocal"
6391 [(match_operand:DI 0 "memory_operand" "")
6392 (match_operand:SI 1 "register_operand" "")]
6393 ""
6394 "
6395 {
6396 rtx temp = gen_reg_rtx (SImode);
6397
6398 /* Copy the backchain to the first word, sp to the second. */
6399 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
6400 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
6401 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
6402 DONE;
6403 }")
6404
6405 (define_expand "restore_stack_nonlocal"
6406 [(match_operand:SI 0 "register_operand" "")
6407 (match_operand:DI 1 "memory_operand" "")]
6408 ""
6409 "
6410 {
6411 rtx temp = gen_reg_rtx (SImode);
6412
6413 /* Restore the backchain from the first word, sp from the second. */
6414 emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
6415 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
6416 emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
6417 DONE;
6418 }")
6419 \f
6420
6421 ;; A function pointer under AIX is a pointer to a data area whose first word
6422 ;; contains the actual address of the function, whose second word contains a
6423 ;; pointer to its TOC, and whose third word contains a value to place in the
6424 ;; static chain register (r11). Note that if we load the static chain, our
6425 ;; "trampoline" need not have any executable code.
6426 ;;
6427 ;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address)
6428 ;; operands[1] is the stack size to clean up
6429 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX)
6430 ;; operands[3] is location to store the TOC
6431 ;; operands[4] is the TOC register
6432 ;; operands[5] is the static chain register
6433 ;;
6434 ;; We do not break this into separate insns, so that the scheduler will not try
6435 ;; to move the load of the new TOC before any loads from the TOC.
6436
6437 (define_insn "call_indirect_aix"
6438 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
6439 (match_operand 1 "const_int_operand" "n"))
6440 (use (match_operand 2 "const_int_operand" "O"))
6441 (use (match_operand 3 "offsettable_addr_operand" "p"))
6442 (use (match_operand 4 "register_operand" "r"))
6443 (clobber (match_operand 5 "register_operand" "=r"))
6444 (clobber (match_scratch:SI 6 "=&r"))
6445 (clobber (match_scratch:SI 7 "=l"))]
6446 "DEFAULT_ABI == ABI_AIX"
6447 "{st|stw} %4,%a3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0);\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%a3"
6448 [(set_attr "length" "28")])
6449
6450 (define_insn "call_value_indirect_aix"
6451 [(set (match_operand 0 "register_operand" "fg")
6452 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
6453 (match_operand 2 "const_int_operand" "n")))
6454 (use (match_operand 3 "const_int_operand" "O"))
6455 (use (match_operand 4 "offsettable_addr_operand" "p"))
6456 (use (match_operand 5 "register_operand" "r"))
6457 (clobber (match_operand 6 "register_operand" "=r"))
6458 (clobber (match_scratch:SI 7 "=&r"))
6459 (clobber (match_scratch:SI 8 "=l"))]
6460 "DEFAULT_ABI == ABI_AIX"
6461 "{st|stw} %5,%a4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1);\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%a4"
6462 [(set_attr "length" "28")])
6463
6464 ;; A function pointer undef NT is a pointer to a data area whose first word
6465 ;; contains the actual address of the function, whose second word contains a
6466 ;; pointer to its TOC. The static chain is not stored under NT, which means
6467 ;; that we need a trampoline.
6468 ;;
6469 ;; operands[0] is an SImode pseudo in which we place the address of the function.
6470 ;; operands[1] is the stack size to clean up
6471 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT)
6472 ;; operands[3] is location to store the TOC
6473 ;; operands[4] is the TOC register
6474 ;;
6475 ;; We do not break this into separate insns, so that the scheduler will not try
6476 ;; to move the load of the new TOC before any loads from the TOC.
6477
6478 (define_insn "call_indirect_nt"
6479 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
6480 (match_operand 1 "const_int_operand" "n"))
6481 (use (match_operand 2 "const_int_operand" "O"))
6482 (use (match_operand 3 "offsettable_addr_operand" "p"))
6483 (use (match_operand 4 "register_operand" "r"))
6484 (clobber (match_scratch:SI 5 "=&r"))
6485 (clobber (match_scratch:SI 6 "=l"))]
6486 "DEFAULT_ABI == ABI_NT"
6487 "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3"
6488 [(set_attr "length" "24")])
6489
6490 (define_insn "call_value_indirect_nt"
6491 [(set (match_operand 0 "register_operand" "fg")
6492 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
6493 (match_operand 2 "const_int_operand" "n")))
6494 (use (match_operand 3 "const_int_operand" "O"))
6495 (use (match_operand 4 "offsettable_addr_operand" "p"))
6496 (use (match_operand 5 "register_operand" "r"))
6497 (clobber (match_scratch:SI 6 "=&r"))
6498 (clobber (match_scratch:SI 7 "=l"))]
6499 "DEFAULT_ABI == ABI_NT"
6500 "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4"
6501 [(set_attr "length" "24")])
6502
6503 ;; A function pointer under System V is just a normal pointer
6504 ;; operands[0] is the function pointer
6505 ;; operands[1] is the stack size to clean up
6506 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
6507
6508 (define_insn "call_indirect_sysv"
6509 [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l"))
6510 (match_operand 1 "const_int_operand" "n,n"))
6511 (use (match_operand 2 "const_int_operand" "O,n"))
6512 (clobber (match_scratch:SI 3 "=l,l"))]
6513 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC"
6514 "*
6515 {
6516 if (INTVAL (operands[2]) > 0)
6517 return \"creqv 6,6,6\;{brl|blrl}\";
6518
6519 else if (INTVAL (operands[2]) < 0)
6520 return \"crxor 6,6,6\;{brl|blrl}\";
6521
6522 return \"{brl|blrl}\";
6523 }"
6524 [(set_attr "length" "4,8")])
6525
6526 (define_insn "call_value_indirect_sysv"
6527 [(set (match_operand 0 "register_operand" "=fg,fg")
6528 (call (mem:SI (match_operand:SI 1 "register_operand" "l,l"))
6529 (match_operand 2 "const_int_operand" "n,n")))
6530 (use (match_operand 3 "const_int_operand" "O,n"))
6531 (clobber (match_scratch:SI 4 "=l,l"))]
6532 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC"
6533 "*
6534 {
6535 if (INTVAL (operands[3]) > 0)
6536 return \"creqv 6,6,6\;{brl|blrl}\";
6537
6538 else if (INTVAL (operands[3]) < 0)
6539 return \"crxor 6,6,6\;{brl|blrl}\";
6540
6541 return \"{brl|blrl}\";
6542 }"
6543 [(set_attr "length" "4,8")])
6544
6545 ;; Now the definitions for the call and call_value insns
6546 (define_expand "call"
6547 [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
6548 (match_operand 1 "" ""))
6549 (use (match_operand 2 "" ""))
6550 (clobber (scratch:SI))])]
6551 ""
6552 "
6553 {
6554 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
6555 abort ();
6556
6557 operands[0] = XEXP (operands[0], 0);
6558
6559 /* Convert NT DLL imports into an indirect call. */
6560 if (GET_CODE (operands[0]) == SYMBOL_REF
6561 && INTVAL (operands[2]) == (int)CALL_NT_DLLIMPORT)
6562 {
6563 operands[0] = rs6000_dll_import_ref (operands[0]);
6564 operands[2] = GEN_INT ((int)CALL_NORMAL);
6565 }
6566
6567 if (GET_CODE (operands[0]) != SYMBOL_REF)
6568 {
6569 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC)
6570 emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]),
6571 operands[1], operands[2]));
6572 else
6573 {
6574 rtx toc_reg = gen_rtx (REG, Pmode, 2);
6575 rtx toc_addr = RS6000_SAVE_TOC;
6576
6577 if (DEFAULT_ABI == ABI_AIX)
6578 {
6579 /* AIX function pointers are really pointers to a three word area */
6580 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
6581 emit_call_insn (gen_call_indirect_aix (force_reg (Pmode, operands[0]),
6582 operands[1], operands[2],
6583 toc_addr, toc_reg, static_chain));
6584 }
6585 else if (DEFAULT_ABI == ABI_NT)
6586 {
6587 /* NT function pointers are really pointers to a two word area */
6588 rs6000_save_toc_p = 1;
6589 emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]),
6590 operands[1], operands[2],
6591 toc_addr, toc_reg));
6592 }
6593 else
6594 abort ();
6595 }
6596 DONE;
6597 }
6598 }")
6599
6600 (define_expand "call_value"
6601 [(parallel [(set (match_operand 0 "" "")
6602 (call (mem:SI (match_operand:SI 1 "address_operand" ""))
6603 (match_operand 2 "" "")))
6604 (use (match_operand 3 "" ""))
6605 (clobber (scratch:SI))])]
6606 ""
6607 "
6608 {
6609 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
6610 abort ();
6611
6612 operands[1] = XEXP (operands[1], 0);
6613
6614 /* Convert NT DLL imports into an indirect call. */
6615 if (GET_CODE (operands[1]) == SYMBOL_REF
6616 && INTVAL (operands[3]) == (int)CALL_NT_DLLIMPORT)
6617 {
6618 operands[1] = rs6000_dll_import_ref (operands[1]);
6619 operands[3] = GEN_INT ((int)CALL_NORMAL);
6620 }
6621
6622 if (GET_CODE (operands[1]) != SYMBOL_REF)
6623 {
6624 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC)
6625 emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1],
6626 operands[2], operands[3]));
6627 else
6628 {
6629 rtx toc_reg = gen_rtx (REG, Pmode, 2);
6630 rtx toc_addr = RS6000_SAVE_TOC;
6631
6632 if (DEFAULT_ABI == ABI_AIX)
6633 {
6634 /* AIX function pointers are really pointers to a three word area */
6635 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
6636 emit_call_insn (gen_call_value_indirect_aix (operands[0],
6637 force_reg (Pmode, operands[1]),
6638 operands[2], operands[3],
6639 toc_addr, toc_reg, static_chain));
6640 }
6641 else if (DEFAULT_ABI == ABI_NT)
6642 {
6643 /* NT function pointers are really pointers to a two word area */
6644 rs6000_save_toc_p = 1;
6645 emit_call_insn (gen_call_value_indirect_nt (operands[0],
6646 force_reg (Pmode, operands[1]),
6647 operands[2], operands[3],
6648 toc_addr, toc_reg));
6649 }
6650 else
6651 abort ();
6652 }
6653 DONE;
6654 }
6655 }")
6656
6657 ;; Call to function in current module. No TOC pointer reload needed.
6658 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
6659 ;; either the function was not prototyped, or it was prototyped as a
6660 ;; variable argument function. It is > 0 if FP registers were passed
6661 ;; and < 0 if they were not.
6662
6663 (define_insn ""
6664 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
6665 (match_operand 1 "" "g,g"))
6666 (use (match_operand:SI 2 "immediate_operand" "O,n"))
6667 (clobber (match_scratch:SI 3 "=l,l"))]
6668 ""
6669 "*
6670 {
6671 switch ((enum rs6000_call_cookie)INTVAL (operands[2]))
6672 {
6673 case CALL_V4_SET_FP_ARGS: output_asm_insn (\"crxor 6,6,6\", operands); break;
6674 case CALL_V4_CLEAR_FP_ARGS: output_asm_insn (\"creqv 6,6,6\", operands); break;
6675 }
6676
6677 return \"bl %z0\";
6678 }"
6679 [(set_attr "length" "4,8")])
6680
6681 ;; Call to function which may be in another module. Restore the TOC
6682 ;; pointer (r2) after the call unless this is System V.
6683 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
6684 ;; either the function was not prototyped, or it was prototyped as a
6685 ;; variable argument function. It is > 0 if FP registers were passed
6686 ;; and < 0 if they were not.
6687
6688 (define_insn ""
6689 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
6690 (match_operand 1 "" "fg,fg"))
6691 (use (match_operand:SI 2 "immediate_operand" "O,n"))
6692 (clobber (match_scratch:SI 3 "=l,l"))]
6693 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT"
6694 "*
6695 {
6696 /* Indirect calls should go through call_indirect */
6697 if (GET_CODE (operands[0]) == REG)
6698 abort ();
6699
6700 switch ((enum rs6000_call_cookie)INTVAL (operands[2]))
6701 {
6702 case CALL_V4_SET_FP_ARGS: output_asm_insn (\"crxor 6,6,6\", operands); break;
6703 case CALL_V4_CLEAR_FP_ARGS: output_asm_insn (\"creqv 6,6,6\", operands); break;
6704 }
6705
6706 return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
6707 }"
6708 [(set_attr "length" "8,12")])
6709
6710 (define_insn ""
6711 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
6712 (match_operand 1 "" "fg,fg"))
6713 (use (match_operand:SI 2 "immediate_operand" "O,n"))
6714 (clobber (match_scratch:SI 3 "=l,l"))]
6715 "DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4"
6716 "*
6717 {
6718 /* Indirect calls should go through call_indirect */
6719 if (GET_CODE (operands[0]) == REG)
6720 abort ();
6721
6722 switch ((enum rs6000_call_cookie)INTVAL (operands[2]))
6723 {
6724 case CALL_V4_SET_FP_ARGS: output_asm_insn (\"crxor 6,6,6\", operands); break;
6725 case CALL_V4_CLEAR_FP_ARGS: output_asm_insn (\"creqv 6,6,6\", operands); break;
6726 }
6727
6728 return \"bl %z0\";
6729 }"
6730 [(set_attr "length" "4,8")])
6731
6732 (define_insn ""
6733 [(set (match_operand 0 "" "=fg,fg")
6734 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
6735 (match_operand 2 "" "g,g")))
6736 (use (match_operand:SI 3 "immediate_operand" "O,n"))
6737 (clobber (match_scratch:SI 4 "=l,l"))]
6738 ""
6739 "*
6740 {
6741 switch ((enum rs6000_call_cookie)INTVAL (operands[3]))
6742 {
6743 case CALL_V4_SET_FP_ARGS: output_asm_insn (\"crxor 6,6,6\", operands); break;
6744 case CALL_V4_CLEAR_FP_ARGS: output_asm_insn (\"creqv 6,6,6\", operands); break;
6745 }
6746
6747 return \"bl %z1\";
6748 }"
6749 [(set_attr "length" "4,8")])
6750
6751 (define_insn ""
6752 [(set (match_operand 0 "" "=fg,fg")
6753 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
6754 (match_operand 2 "" "fg,fg")))
6755 (use (match_operand:SI 3 "immediate_operand" "O,n"))
6756 (clobber (match_scratch:SI 4 "=l,l"))]
6757 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT"
6758 "*
6759 {
6760 /* This should be handled by call_value_indirect */
6761 if (GET_CODE (operands[1]) == REG)
6762 abort ();
6763
6764 switch ((enum rs6000_call_cookie)INTVAL (operands[3]))
6765 {
6766 case CALL_V4_SET_FP_ARGS: output_asm_insn (\"crxor 6,6,6\", operands); break;
6767 case CALL_V4_CLEAR_FP_ARGS: output_asm_insn (\"creqv 6,6,6\", operands); break;
6768 }
6769
6770 return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
6771 }"
6772 [(set_attr "length" "8,12")])
6773
6774 (define_insn ""
6775 [(set (match_operand 0 "" "=fg,fg")
6776 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
6777 (match_operand 2 "" "fg,fg")))
6778 (use (match_operand:SI 3 "immediate_operand" "O,n"))
6779 (clobber (match_scratch:SI 4 "=l,l"))]
6780 "DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4"
6781 "*
6782 {
6783 /* This should be handled by call_value_indirect */
6784 if (GET_CODE (operands[1]) == REG)
6785 abort ();
6786
6787 switch ((enum rs6000_call_cookie)INTVAL (operands[3]))
6788 {
6789 case CALL_V4_SET_FP_ARGS: output_asm_insn (\"crxor 6,6,6\", operands); break;
6790 case CALL_V4_CLEAR_FP_ARGS: output_asm_insn (\"creqv 6,6,6\", operands); break;
6791 }
6792
6793 return \"bl %z1\";
6794 }"
6795 [(set_attr "length" "4,8")])
6796
6797
6798 ;; Call subroutine returning any type.
6799
6800 (define_expand "untyped_call"
6801 [(parallel [(call (match_operand 0 "" "")
6802 (const_int 0))
6803 (match_operand 1 "" "")
6804 (match_operand 2 "" "")])]
6805 ""
6806 "
6807 {
6808 int i;
6809
6810 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
6811
6812 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6813 {
6814 rtx set = XVECEXP (operands[2], 0, i);
6815 emit_move_insn (SET_DEST (set), SET_SRC (set));
6816 }
6817
6818 /* The optimizer does not know that the call sets the function value
6819 registers we stored in the result block. We avoid problems by
6820 claiming that all hard registers are used and clobbered at this
6821 point. */
6822 emit_insn (gen_blockage ());
6823
6824 DONE;
6825 }")
6826
6827 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6828 ;; all of memory. This blocks insns from being moved across this point.
6829
6830 (define_insn "blockage"
6831 [(unspec_volatile [(const_int 0)] 0)]
6832 ""
6833 "")
6834
6835 ;; Synchronize instructions/data caches for V.4 trampolines
6836 ;; The extra memory_operand is to prevent the optimizer from
6837 ;; deleting insns with "no" effect.
6838 (define_insn "icbi"
6839 [(unspec [(match_operand 0 "memory_operand" "=m")
6840 (match_operand 1 "register_operand" "b")
6841 (match_operand 2 "register_operand" "r")] 3)]
6842 "TARGET_POWERPC"
6843 "icbi %1,%2")
6844
6845 (define_insn "dcbst"
6846 [(unspec [(match_operand 0 "memory_operand" "=m")
6847 (match_operand 1 "register_operand" "b")
6848 (match_operand 2 "register_operand" "r")] 4)]
6849 "TARGET_POWERPC"
6850 "dcbst %1,%2")
6851
6852 (define_insn "sync"
6853 [(unspec [(match_operand 0 "memory_operand" "=m")] 5)]
6854 ""
6855 "{dcs|sync}")
6856
6857 (define_insn "isync"
6858 [(unspec [(match_operand 0 "memory_operand" "=m")] 6)]
6859 ""
6860 "{ics|isync}")
6861
6862 \f
6863 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
6864 ;; signed & unsigned, and one type of branch.
6865 ;;
6866 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
6867 ;; insns, and branches. We store the operands of compares until we see
6868 ;; how it is used.
6869 (define_expand "cmpsi"
6870 [(set (cc0)
6871 (compare (match_operand:SI 0 "gpc_reg_operand" "")
6872 (match_operand:SI 1 "reg_or_short_operand" "")))]
6873 ""
6874 "
6875 {
6876 /* Take care of the possibility that operands[1] might be negative but
6877 this might be a logical operation. That insn doesn't exist. */
6878 if (GET_CODE (operands[1]) == CONST_INT
6879 && INTVAL (operands[1]) < 0)
6880 operands[1] = force_reg (SImode, operands[1]);
6881
6882 rs6000_compare_op0 = operands[0];
6883 rs6000_compare_op1 = operands[1];
6884 rs6000_compare_fp_p = 0;
6885 DONE;
6886 }")
6887
6888 (define_expand "cmpdi"
6889 [(set (cc0)
6890 (compare (match_operand:DI 0 "gpc_reg_operand" "")
6891 (match_operand:DI 1 "reg_or_short_operand" "")))]
6892 "TARGET_POWERPC64"
6893 "
6894 {
6895 /* Take care of the possibility that operands[1] might be negative but
6896 this might be a logical operation. That insn doesn't exist. */
6897 if (GET_CODE (operands[1]) == CONST_INT
6898 && INTVAL (operands[1]) < 0)
6899 operands[1] = force_reg (DImode, operands[1]);
6900
6901 rs6000_compare_op0 = operands[0];
6902 rs6000_compare_op1 = operands[1];
6903 rs6000_compare_fp_p = 0;
6904 DONE;
6905 }")
6906
6907 (define_expand "cmpsf"
6908 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
6909 (match_operand:SF 1 "gpc_reg_operand" "")))]
6910 "TARGET_HARD_FLOAT"
6911 "
6912 {
6913 rs6000_compare_op0 = operands[0];
6914 rs6000_compare_op1 = operands[1];
6915 rs6000_compare_fp_p = 1;
6916 DONE;
6917 }")
6918
6919 (define_expand "cmpdf"
6920 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
6921 (match_operand:DF 1 "gpc_reg_operand" "")))]
6922 "TARGET_HARD_FLOAT"
6923 "
6924 {
6925 rs6000_compare_op0 = operands[0];
6926 rs6000_compare_op1 = operands[1];
6927 rs6000_compare_fp_p = 1;
6928 DONE;
6929 }")
6930
6931 (define_expand "beq"
6932 [(set (match_dup 2) (match_dup 1))
6933 (set (pc)
6934 (if_then_else (eq (match_dup 2)
6935 (const_int 0))
6936 (label_ref (match_operand 0 "" ""))
6937 (pc)))]
6938 ""
6939 "
6940 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
6941 operands[1] = gen_rtx (COMPARE, mode,
6942 rs6000_compare_op0, rs6000_compare_op1);
6943 operands[2] = gen_reg_rtx (mode);
6944 }")
6945
6946 (define_expand "bne"
6947 [(set (match_dup 2) (match_dup 1))
6948 (set (pc)
6949 (if_then_else (ne (match_dup 2)
6950 (const_int 0))
6951 (label_ref (match_operand 0 "" ""))
6952 (pc)))]
6953 ""
6954 "
6955 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
6956 operands[1] = gen_rtx (COMPARE, mode,
6957 rs6000_compare_op0, rs6000_compare_op1);
6958 operands[2] = gen_reg_rtx (mode);
6959 }")
6960
6961 (define_expand "blt"
6962 [(set (match_dup 2) (match_dup 1))
6963 (set (pc)
6964 (if_then_else (lt (match_dup 2)
6965 (const_int 0))
6966 (label_ref (match_operand 0 "" ""))
6967 (pc)))]
6968 ""
6969 "
6970 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
6971 operands[1] = gen_rtx (COMPARE, mode,
6972 rs6000_compare_op0, rs6000_compare_op1);
6973 operands[2] = gen_reg_rtx (mode);
6974 }")
6975
6976 (define_expand "bgt"
6977 [(set (match_dup 2) (match_dup 1))
6978 (set (pc)
6979 (if_then_else (gt (match_dup 2)
6980 (const_int 0))
6981 (label_ref (match_operand 0 "" ""))
6982 (pc)))]
6983 ""
6984 "
6985 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
6986 operands[1] = gen_rtx (COMPARE, mode,
6987 rs6000_compare_op0, rs6000_compare_op1);
6988 operands[2] = gen_reg_rtx (mode);
6989 }")
6990
6991 (define_expand "ble"
6992 [(set (match_dup 2) (match_dup 1))
6993 (set (pc)
6994 (if_then_else (le (match_dup 2)
6995 (const_int 0))
6996 (label_ref (match_operand 0 "" ""))
6997 (pc)))]
6998 ""
6999 "
7000 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7001 operands[1] = gen_rtx (COMPARE, mode,
7002 rs6000_compare_op0, rs6000_compare_op1);
7003 operands[2] = gen_reg_rtx (mode);
7004 }")
7005
7006 (define_expand "bge"
7007 [(set (match_dup 2) (match_dup 1))
7008 (set (pc)
7009 (if_then_else (ge (match_dup 2)
7010 (const_int 0))
7011 (label_ref (match_operand 0 "" ""))
7012 (pc)))]
7013 ""
7014 "
7015 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7016 operands[1] = gen_rtx (COMPARE, mode,
7017 rs6000_compare_op0, rs6000_compare_op1);
7018 operands[2] = gen_reg_rtx (mode);
7019 }")
7020
7021 (define_expand "bgtu"
7022 [(set (match_dup 2) (match_dup 1))
7023 (set (pc)
7024 (if_then_else (gtu (match_dup 2)
7025 (const_int 0))
7026 (label_ref (match_operand 0 "" ""))
7027 (pc)))]
7028 ""
7029 "
7030 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7031 rs6000_compare_op0, rs6000_compare_op1);
7032 operands[2] = gen_reg_rtx (CCUNSmode);
7033 }")
7034
7035 (define_expand "bltu"
7036 [(set (match_dup 2) (match_dup 1))
7037 (set (pc)
7038 (if_then_else (ltu (match_dup 2)
7039 (const_int 0))
7040 (label_ref (match_operand 0 "" ""))
7041 (pc)))]
7042 ""
7043 "
7044 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7045 rs6000_compare_op0, rs6000_compare_op1);
7046 operands[2] = gen_reg_rtx (CCUNSmode);
7047 }")
7048
7049 (define_expand "bgeu"
7050 [(set (match_dup 2) (match_dup 1))
7051 (set (pc)
7052 (if_then_else (geu (match_dup 2)
7053 (const_int 0))
7054 (label_ref (match_operand 0 "" ""))
7055 (pc)))]
7056 ""
7057 "
7058 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7059 rs6000_compare_op0, rs6000_compare_op1);
7060 operands[2] = gen_reg_rtx (CCUNSmode);
7061 }")
7062
7063 (define_expand "bleu"
7064 [(set (match_dup 2) (match_dup 1))
7065 (set (pc)
7066 (if_then_else (leu (match_dup 2)
7067 (const_int 0))
7068 (label_ref (match_operand 0 "" ""))
7069 (pc)))]
7070 ""
7071 "
7072 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7073 rs6000_compare_op0, rs6000_compare_op1);
7074 operands[2] = gen_reg_rtx (CCUNSmode);
7075 }")
7076
7077 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
7078 ;; For SEQ, likewise, except that comparisons with zero should be done
7079 ;; with an scc insns. However, due to the order that combine see the
7080 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
7081 ;; the cases we don't want to handle.
7082 (define_expand "seq"
7083 [(set (match_dup 2) (match_dup 1))
7084 (set (match_operand:SI 0 "gpc_reg_operand" "")
7085 (eq:SI (match_dup 2) (const_int 0)))]
7086 ""
7087 "
7088 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7089 operands[1] = gen_rtx (COMPARE, mode,
7090 rs6000_compare_op0, rs6000_compare_op1);
7091 operands[2] = gen_reg_rtx (mode);
7092 }")
7093
7094 (define_expand "sne"
7095 [(set (match_dup 2) (match_dup 1))
7096 (set (match_operand:SI 0 "gpc_reg_operand" "")
7097 (ne:SI (match_dup 2) (const_int 0)))]
7098 ""
7099 "
7100 { if (! rs6000_compare_fp_p)
7101 FAIL;
7102
7103 operands[1] = gen_rtx (COMPARE, CCFPmode,
7104 rs6000_compare_op0, rs6000_compare_op1);
7105 operands[2] = gen_reg_rtx (CCFPmode);
7106 }")
7107
7108 ;; A > 0 is best done using the portable sequence, so fail in that case.
7109 (define_expand "sgt"
7110 [(set (match_dup 2) (match_dup 1))
7111 (set (match_operand:SI 0 "gpc_reg_operand" "")
7112 (gt:SI (match_dup 2) (const_int 0)))]
7113 ""
7114 "
7115 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7116
7117 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7118 FAIL;
7119
7120 operands[1] = gen_rtx (COMPARE, mode,
7121 rs6000_compare_op0, rs6000_compare_op1);
7122 operands[2] = gen_reg_rtx (mode);
7123 }")
7124
7125 ;; A < 0 is best done in the portable way for A an integer.
7126 (define_expand "slt"
7127 [(set (match_dup 2) (match_dup 1))
7128 (set (match_operand:SI 0 "gpc_reg_operand" "")
7129 (lt:SI (match_dup 2) (const_int 0)))]
7130 ""
7131 "
7132 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7133
7134 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7135 FAIL;
7136
7137 operands[1] = gen_rtx (COMPARE, mode,
7138 rs6000_compare_op0, rs6000_compare_op1);
7139 operands[2] = gen_reg_rtx (mode);
7140 }")
7141
7142 (define_expand "sge"
7143 [(set (match_dup 2) (match_dup 1))
7144 (set (match_operand:SI 0 "gpc_reg_operand" "")
7145 (ge:SI (match_dup 2) (const_int 0)))]
7146 ""
7147 "
7148 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7149 operands[1] = gen_rtx (COMPARE, mode,
7150 rs6000_compare_op0, rs6000_compare_op1);
7151 operands[2] = gen_reg_rtx (mode);
7152 }")
7153
7154 ;; A <= 0 is best done the portable way for A an integer.
7155 (define_expand "sle"
7156 [(set (match_dup 2) (match_dup 1))
7157 (set (match_operand:SI 0 "gpc_reg_operand" "")
7158 (le:SI (match_dup 2) (const_int 0)))]
7159 ""
7160 "
7161 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7162
7163 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7164 FAIL;
7165
7166 operands[1] = gen_rtx (COMPARE, mode,
7167 rs6000_compare_op0, rs6000_compare_op1);
7168 operands[2] = gen_reg_rtx (mode);
7169 }")
7170
7171 (define_expand "sgtu"
7172 [(set (match_dup 2) (match_dup 1))
7173 (set (match_operand:SI 0 "gpc_reg_operand" "")
7174 (gtu:SI (match_dup 2) (const_int 0)))]
7175 ""
7176 "
7177 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7178 rs6000_compare_op0, rs6000_compare_op1);
7179 operands[2] = gen_reg_rtx (CCUNSmode);
7180 }")
7181
7182 (define_expand "sltu"
7183 [(set (match_dup 2) (match_dup 1))
7184 (set (match_operand:SI 0 "gpc_reg_operand" "")
7185 (ltu:SI (match_dup 2) (const_int 0)))]
7186 ""
7187 "
7188 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7189 rs6000_compare_op0, rs6000_compare_op1);
7190 operands[2] = gen_reg_rtx (CCUNSmode);
7191 }")
7192
7193 (define_expand "sgeu"
7194 [(set (match_dup 2) (match_dup 1))
7195 (set (match_operand:SI 0 "gpc_reg_operand" "")
7196 (geu:SI (match_dup 2) (const_int 0)))]
7197 ""
7198 "
7199 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7200 rs6000_compare_op0, rs6000_compare_op1);
7201 operands[2] = gen_reg_rtx (CCUNSmode);
7202 }")
7203
7204 (define_expand "sleu"
7205 [(set (match_dup 2) (match_dup 1))
7206 (set (match_operand:SI 0 "gpc_reg_operand" "")
7207 (leu:SI (match_dup 2) (const_int 0)))]
7208 ""
7209 "
7210 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
7211 rs6000_compare_op0, rs6000_compare_op1);
7212 operands[2] = gen_reg_rtx (CCUNSmode);
7213 }")
7214 \f
7215 ;; Here are the actual compare insns.
7216 (define_insn ""
7217 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
7218 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
7219 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
7220 ""
7221 "{cmp%I2|cmpw%I2} %0,%1,%2"
7222 [(set_attr "type" "compare")])
7223
7224 (define_insn ""
7225 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
7226 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
7227 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
7228 "TARGET_POWERPC64"
7229 "cmpd%I2 %0,%1,%2"
7230 [(set_attr "type" "compare")])
7231
7232 ;; If we are comparing a register for equality with a large constant,
7233 ;; we can do this with an XOR followed by a compare. But we need a scratch
7234 ;; register for the result of the XOR.
7235
7236 (define_split
7237 [(set (match_operand:CC 0 "cc_reg_operand" "")
7238 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7239 (match_operand:SI 2 "non_short_cint_operand" "")))
7240 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
7241 "find_single_use (operands[0], insn, 0)
7242 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
7243 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
7244 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
7245 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
7246 "
7247 {
7248 /* Get the constant we are comparing against, C, and see what it looks like
7249 sign-extended to 16 bits. Then see what constant could be XOR'ed
7250 with C to get the sign-extended value. */
7251
7252 int c = INTVAL (operands[2]);
7253 int sextc = (c << 16) >> 16;
7254 int xorv = c ^ sextc;
7255
7256 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
7257 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
7258 }")
7259
7260 (define_insn ""
7261 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
7262 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
7263 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
7264 ""
7265 "{cmpl%I2|cmplw%I2} %0,%1,%W2"
7266 [(set_attr "type" "compare")])
7267
7268 (define_insn ""
7269 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
7270 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
7271 (match_operand:DI 2 "reg_or_u_short_operand" "rI")))]
7272 ""
7273 "cmpld%I2 %0,%1,%W2"
7274 [(set_attr "type" "compare")])
7275
7276 ;; The following two insns don't exist as single insns, but if we provide
7277 ;; them, we can swap an add and compare, which will enable us to overlap more
7278 ;; of the required delay between a compare and branch. We generate code for
7279 ;; them by splitting.
7280
7281 (define_insn ""
7282 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
7283 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
7284 (match_operand:SI 2 "short_cint_operand" "i")))
7285 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7286 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
7287 ""
7288 "#"
7289 [(set_attr "length" "8")])
7290
7291 (define_insn ""
7292 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
7293 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
7294 (match_operand:SI 2 "u_short_cint_operand" "i")))
7295 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7296 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
7297 ""
7298 "#"
7299 [(set_attr "length" "8")])
7300
7301 (define_split
7302 [(set (match_operand:CC 3 "cc_reg_operand" "")
7303 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7304 (match_operand:SI 2 "short_cint_operand" "")))
7305 (set (match_operand:SI 0 "gpc_reg_operand" "")
7306 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
7307 ""
7308 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
7309 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
7310
7311 (define_split
7312 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
7313 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
7314 (match_operand:SI 2 "u_short_cint_operand" "")))
7315 (set (match_operand:SI 0 "gpc_reg_operand" "")
7316 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
7317 ""
7318 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
7319 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
7320
7321 (define_insn ""
7322 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
7323 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
7324 (match_operand:SF 2 "gpc_reg_operand" "f")))]
7325 "TARGET_HARD_FLOAT"
7326 "fcmpu %0,%1,%2"
7327 [(set_attr "type" "fpcompare")])
7328
7329 (define_insn ""
7330 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
7331 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
7332 (match_operand:DF 2 "gpc_reg_operand" "f")))]
7333 "TARGET_HARD_FLOAT"
7334 "fcmpu %0,%1,%2"
7335 [(set_attr "type" "fpcompare")])
7336 \f
7337 ;; Now we have the scc insns. We can do some combinations because of the
7338 ;; way the machine works.
7339 ;;
7340 ;; Note that this is probably faster if we can put an insn between the
7341 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
7342 ;; cases the insns below which don't use an intermediate CR field will
7343 ;; be used instead.
7344 (define_insn ""
7345 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7346 (match_operator:SI 1 "scc_comparison_operator"
7347 [(match_operand 2 "cc_reg_operand" "y")
7348 (const_int 0)]))]
7349 ""
7350 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
7351 [(set_attr "length" "12")])
7352
7353 (define_insn ""
7354 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
7355 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
7356 [(match_operand 2 "cc_reg_operand" "y")
7357 (const_int 0)])
7358 (const_int 0)))
7359 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
7360 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
7361 ""
7362 "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
7363 [(set_attr "type" "delayed_compare")
7364 (set_attr "length" "12")])
7365
7366 (define_insn ""
7367 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7368 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
7369 [(match_operand 2 "cc_reg_operand" "y")
7370 (const_int 0)])
7371 (match_operand:SI 3 "const_int_operand" "n")))]
7372 ""
7373 "*
7374 {
7375 int is_bit = ccr_bit (operands[1], 1);
7376 int put_bit = 31 - (INTVAL (operands[3]) & 31);
7377 int count;
7378
7379 if (is_bit >= put_bit)
7380 count = is_bit - put_bit;
7381 else
7382 count = 32 - (put_bit - is_bit);
7383
7384 operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
7385 operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
7386
7387 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
7388 }"
7389 [(set_attr "length" "12")])
7390
7391 (define_insn ""
7392 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
7393 (compare:CC
7394 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
7395 [(match_operand 2 "cc_reg_operand" "y")
7396 (const_int 0)])
7397 (match_operand:SI 3 "const_int_operand" "n"))
7398 (const_int 0)))
7399 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
7400 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
7401 (match_dup 3)))]
7402 ""
7403 "*
7404 {
7405 int is_bit = ccr_bit (operands[1], 1);
7406 int put_bit = 31 - (INTVAL (operands[3]) & 31);
7407 int count;
7408
7409 if (is_bit >= put_bit)
7410 count = is_bit - put_bit;
7411 else
7412 count = 32 - (put_bit - is_bit);
7413
7414 operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
7415 operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
7416
7417 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
7418 }"
7419 [(set_attr "type" "delayed_compare")
7420 (set_attr "length" "12")])
7421
7422 ;; If we are comparing the result of two comparisons, this can be done
7423 ;; using creqv or crxor.
7424
7425 (define_insn ""
7426 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
7427 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
7428 [(match_operand 2 "cc_reg_operand" "y")
7429 (const_int 0)])
7430 (match_operator 3 "scc_comparison_operator"
7431 [(match_operand 4 "cc_reg_operand" "y")
7432 (const_int 0)])))]
7433 "REGNO (operands[2]) != REGNO (operands[4])"
7434 "*
7435 {
7436 enum rtx_code code1, code2;
7437
7438 code1 = GET_CODE (operands[1]);
7439 code2 = GET_CODE (operands[3]);
7440
7441 if ((code1 == EQ || code1 == LT || code1 == GT
7442 || code1 == LTU || code1 == GTU
7443 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
7444 !=
7445 (code2 == EQ || code2 == LT || code2 == GT
7446 || code2 == LTU || code2 == GTU
7447 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
7448 return \"%C1%C3crxor %E0,%j1,%j3\";
7449 else
7450 return \"%C1%C3creqv %E0,%j1,%j3\";
7451 }"
7452 [(set_attr "length" "12")])
7453
7454 ;; There is a 3 cycle delay between consecutive mfcr instructions
7455 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
7456
7457 (define_peephole
7458 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7459 (match_operator:SI 1 "scc_comparison_operator"
7460 [(match_operand 2 "cc_reg_operand" "y")
7461 (const_int 0)]))
7462 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
7463 (match_operator:SI 4 "scc_comparison_operator"
7464 [(match_operand 5 "cc_reg_operand" "y")
7465 (const_int 0)]))]
7466 "REGNO (operands[2]) != REGNO (operands[5])"
7467 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
7468 [(set_attr "length" "20")])
7469
7470 ;; There are some scc insns that can be done directly, without a compare.
7471 ;; These are faster because they don't involve the communications between
7472 ;; the FXU and branch units. In fact, we will be replacing all of the
7473 ;; integer scc insns here or in the portable methods in emit_store_flag.
7474 ;;
7475 ;; Also support (neg (scc ..)) since that construct is used to replace
7476 ;; branches, (plus (scc ..) ..) since that construct is common and
7477 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
7478 ;; cases where it is no more expensive than (neg (scc ..)).
7479
7480 ;; Have reload force a constant into a register for the simple insns that
7481 ;; otherwise won't accept constants. We do this because it is faster than
7482 ;; the cmp/mfcr sequence we would otherwise generate.
7483
7484 (define_insn ""
7485 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
7486 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
7487 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
7488 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
7489 ""
7490 "@
7491 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
7492 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
7493 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
7494 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
7495 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
7496 [(set_attr "length" "12,8,12,12,12")])
7497
7498 (define_insn ""
7499 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
7500 (compare:CC
7501 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
7502 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
7503 (const_int 0)))
7504 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
7505 (eq:SI (match_dup 1) (match_dup 2)))
7506 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
7507 ""
7508 "@
7509 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
7510 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
7511 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
7512 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
7513 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0"
7514 [(set_attr "type" "compare")
7515 (set_attr "length" "12,8,12,12,12")])
7516
7517 ;; We have insns of the form shown by the first define_insn below. If
7518 ;; there is something inside the comparison operation, we must split it.
7519 (define_split
7520 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7521 (plus:SI (match_operator 1 "comparison_operator"
7522 [(match_operand:SI 2 "" "")
7523 (match_operand:SI 3
7524 "reg_or_cint_operand" "")])
7525 (match_operand:SI 4 "gpc_reg_operand" "")))
7526 (clobber (match_operand:SI 5 "register_operand" ""))]
7527 "! gpc_reg_operand (operands[2], SImode)"
7528 [(set (match_dup 5) (match_dup 2))
7529 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
7530 (match_dup 4)))])
7531
7532 (define_insn ""
7533 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
7534 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
7535 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
7536 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
7537 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
7538 ""
7539 "@
7540 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
7541 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
7542 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
7543 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
7544 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
7545 [(set_attr "length" "12,8,12,12,12")])
7546
7547 (define_insn ""
7548 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
7549 (compare:CC
7550 (plus:SI
7551 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
7552 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
7553 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
7554 (const_int 0)))
7555 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
7556 ""
7557 "@
7558 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
7559 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
7560 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
7561 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
7562 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
7563 [(set_attr "type" "compare")
7564 (set_attr "length" "12,8,12,12,12")])
7565
7566 (define_insn ""
7567 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
7568 (compare:CC
7569 (plus:SI
7570 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
7571 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
7572 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
7573 (const_int 0)))
7574 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
7575 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
7576 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
7577 ""
7578 "@
7579 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
7580 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
7581 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
7582 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
7583 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
7584 [(set_attr "type" "compare")
7585 (set_attr "length" "12,8,12,12,12")])
7586
7587 (define_insn ""
7588 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
7589 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
7590 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
7591 ""
7592 "@
7593 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
7594 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
7595 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
7596 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
7597 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
7598 [(set_attr "length" "12,8,12,12,12")])
7599
7600 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
7601 ;; since it nabs/sr is just as fast.
7602 (define_insn ""
7603 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7604 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
7605 (const_int 31)))
7606 (clobber (match_scratch:SI 2 "=&r"))]
7607 "!TARGET_POWER"
7608 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
7609 [(set_attr "length" "8")])
7610
7611 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
7612 (define_insn ""
7613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7614 (plus:SI (lshiftrt:SI
7615 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
7616 (const_int 31))
7617 (match_operand:SI 2 "gpc_reg_operand" "r")))
7618 (clobber (match_scratch:SI 3 "=&r"))]
7619 ""
7620 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
7621 [(set_attr "length" "8")])
7622
7623 (define_insn ""
7624 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
7625 (compare:CC
7626 (plus:SI (lshiftrt:SI
7627 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
7628 (const_int 31))
7629 (match_operand:SI 2 "gpc_reg_operand" "r"))
7630 (const_int 0)))
7631 (clobber (match_scratch:SI 3 "=&r"))]
7632 ""
7633 "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
7634 [(set_attr "type" "compare")
7635 (set_attr "length" "8")])
7636
7637 (define_insn ""
7638 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
7639 (compare:CC
7640 (plus:SI (lshiftrt:SI
7641 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
7642 (const_int 31))
7643 (match_operand:SI 2 "gpc_reg_operand" "r"))
7644 (const_int 0)))
7645 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7646 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
7647 (match_dup 2)))
7648 (clobber (match_scratch:SI 3 "=&r"))]
7649 ""
7650 "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
7651 [(set_attr "type" "compare")
7652 (set_attr "length" "8")])
7653
7654 (define_insn ""
7655 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7656 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7657 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
7658 (clobber (match_scratch:SI 3 "=r,X"))]
7659 "TARGET_POWER"
7660 "@
7661 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
7662 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
7663 [(set_attr "length" "12")])
7664
7665 (define_insn ""
7666 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
7667 (compare:CC
7668 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7669 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
7670 (const_int 0)))
7671 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7672 (le:SI (match_dup 1) (match_dup 2)))
7673 (clobber (match_scratch:SI 3 "=r,X"))]
7674 "TARGET_POWER"
7675 "@
7676 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
7677 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
7678 [(set_attr "type" "compare,delayed_compare")
7679 (set_attr "length" "12")])
7680
7681 (define_insn ""
7682 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7683 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7684 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
7685 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
7686 (clobber (match_scratch:SI 4 "=&r,&r"))]
7687 "TARGET_POWER"
7688 "@
7689 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
7690 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
7691 [(set_attr "length" "12")])
7692
7693 (define_insn ""
7694 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
7695 (compare:CC
7696 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7697 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
7698 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
7699 (const_int 0)))
7700 (clobber (match_scratch:SI 4 "=&r,&r"))]
7701 "TARGET_POWER"
7702 "@
7703 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
7704 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3"
7705 [(set_attr "type" "compare")
7706 (set_attr "length" "12")])
7707
7708 (define_insn ""
7709 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
7710 (compare:CC
7711 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7712 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
7713 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
7714 (const_int 0)))
7715 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7716 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
7717 (clobber (match_scratch:SI 4 "=&r,&r"))]
7718 "TARGET_POWER"
7719 "@
7720 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
7721 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3"
7722 [(set_attr "type" "compare")
7723 (set_attr "length" "12")])
7724
7725 (define_insn ""
7726 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7727 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7728 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
7729 "TARGET_POWER"
7730 "@
7731 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
7732 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
7733 [(set_attr "length" "12")])
7734
7735 (define_insn ""
7736 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7737 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7738 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
7739 ""
7740 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
7741 [(set_attr "length" "12")])
7742
7743 (define_insn ""
7744 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
7745 (compare:CC
7746 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7747 (match_operand:SI 2 "reg_or_short_operand" "rI"))
7748 (const_int 0)))
7749 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7750 (leu:SI (match_dup 1) (match_dup 2)))]
7751 ""
7752 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
7753 [(set_attr "type" "compare")
7754 (set_attr "length" "12")])
7755
7756 (define_insn ""
7757 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7758 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7759 (match_operand:SI 2 "reg_or_short_operand" "rI"))
7760 (match_operand:SI 3 "gpc_reg_operand" "r")))
7761 (clobber (match_scratch:SI 4 "=&r"))]
7762 ""
7763 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
7764 [(set_attr "length" "8")])
7765
7766 (define_insn ""
7767 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
7768 (compare:CC
7769 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7770 (match_operand:SI 2 "reg_or_short_operand" "rI"))
7771 (match_operand:SI 3 "gpc_reg_operand" "r"))
7772 (const_int 0)))
7773 (clobber (match_scratch:SI 4 "=&r"))]
7774 ""
7775 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
7776 [(set_attr "type" "compare")
7777 (set_attr "length" "8")])
7778
7779 (define_insn ""
7780 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
7781 (compare:CC
7782 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7783 (match_operand:SI 2 "reg_or_short_operand" "rI"))
7784 (match_operand:SI 3 "gpc_reg_operand" "r"))
7785 (const_int 0)))
7786 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7787 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
7788 (clobber (match_scratch:SI 4 "=&r"))]
7789 ""
7790 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
7791 [(set_attr "type" "compare")
7792 (set_attr "length" "8")])
7793
7794 (define_insn ""
7795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7796 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7797 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
7798 ""
7799 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
7800 [(set_attr "length" "12")])
7801
7802 (define_insn ""
7803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7804 (and:SI (neg:SI
7805 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7806 (match_operand:SI 2 "reg_or_short_operand" "rI")))
7807 (match_operand:SI 3 "gpc_reg_operand" "r")))
7808 (clobber (match_scratch:SI 4 "=&r"))]
7809 ""
7810 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
7811 [(set_attr "length" "12")])
7812
7813 (define_insn ""
7814 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
7815 (compare:CC
7816 (and:SI (neg:SI
7817 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7818 (match_operand:SI 2 "reg_or_short_operand" "rI")))
7819 (match_operand:SI 3 "gpc_reg_operand" "r"))
7820 (const_int 0)))
7821 (clobber (match_scratch:SI 4 "=&r"))]
7822 ""
7823 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
7824 [(set_attr "type" "compare")
7825 (set_attr "length" "12")])
7826
7827 (define_insn ""
7828 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
7829 (compare:CC
7830 (and:SI (neg:SI
7831 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7832 (match_operand:SI 2 "reg_or_short_operand" "rI")))
7833 (match_operand:SI 3 "gpc_reg_operand" "r"))
7834 (const_int 0)))
7835 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7836 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
7837 (clobber (match_scratch:SI 4 "=&r"))]
7838 ""
7839 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
7840 [(set_attr "type" "compare")
7841 (set_attr "length" "12")])
7842
7843 (define_insn ""
7844 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7845 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7846 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
7847 "TARGET_POWER"
7848 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
7849 [(set_attr "length" "12")])
7850
7851 (define_insn ""
7852 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
7853 (compare:CC
7854 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7855 (match_operand:SI 2 "reg_or_short_operand" "rI"))
7856 (const_int 0)))
7857 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7858 (lt:SI (match_dup 1) (match_dup 2)))]
7859 "TARGET_POWER"
7860 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
7861 [(set_attr "type" "delayed_compare")
7862 (set_attr "length" "12")])
7863
7864 (define_insn ""
7865 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7866 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7867 (match_operand:SI 2 "reg_or_short_operand" "rI"))
7868 (match_operand:SI 3 "gpc_reg_operand" "r")))
7869 (clobber (match_scratch:SI 4 "=&r"))]
7870 "TARGET_POWER"
7871 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
7872 [(set_attr "length" "12")])
7873
7874 (define_insn ""
7875 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
7876 (compare:CC
7877 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7878 (match_operand:SI 2 "reg_or_short_operand" "rI"))
7879 (match_operand:SI 3 "gpc_reg_operand" "r"))
7880 (const_int 0)))
7881 (clobber (match_scratch:SI 4 "=&r"))]
7882 "TARGET_POWER"
7883 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
7884 [(set_attr "type" "compare")
7885 (set_attr "length" "12")])
7886
7887 (define_insn ""
7888 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
7889 (compare:CC
7890 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7891 (match_operand:SI 2 "reg_or_short_operand" "rI"))
7892 (match_operand:SI 3 "gpc_reg_operand" "r"))
7893 (const_int 0)))
7894 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
7895 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
7896 (clobber (match_scratch:SI 4 "=&r"))]
7897 "TARGET_POWER"
7898 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
7899 [(set_attr "type" "compare")
7900 (set_attr "length" "12")])
7901
7902 (define_insn ""
7903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7904 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7905 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
7906 "TARGET_POWER"
7907 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
7908 [(set_attr "length" "12")])
7909
7910 (define_insn ""
7911 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7912 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7913 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
7914 ""
7915 "@
7916 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
7917 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
7918 [(set_attr "length" "12")])
7919
7920 (define_insn ""
7921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
7922 (compare:CC
7923 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7924 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
7925 (const_int 0)))
7926 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7927 (ltu:SI (match_dup 1) (match_dup 2)))]
7928 ""
7929 "@
7930 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
7931 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
7932 [(set_attr "type" "compare")
7933 (set_attr "length" "12")])
7934
7935 (define_insn ""
7936 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
7937 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
7938 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
7939 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
7940 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
7941 ""
7942 "@
7943 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
7944 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
7945 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
7946 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
7947 [(set_attr "length" "12")])
7948
7949 (define_insn ""
7950 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
7951 (compare:CC
7952 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7953 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
7954 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
7955 (const_int 0)))
7956 (clobber (match_scratch:SI 4 "=&r,&r"))]
7957 ""
7958 "@
7959 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
7960 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
7961 [(set_attr "type" "compare")
7962 (set_attr "length" "12")])
7963
7964 (define_insn ""
7965 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
7966 (compare:CC
7967 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7968 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
7969 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
7970 (const_int 0)))
7971 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7972 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
7973 (clobber (match_scratch:SI 4 "=&r,&r"))]
7974 ""
7975 "@
7976 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
7977 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
7978 [(set_attr "type" "compare")
7979 (set_attr "length" "12")])
7980
7981 (define_insn ""
7982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7983 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
7984 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
7985 ""
7986 "@
7987 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
7988 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
7989 [(set_attr "length" "8")])
7990
7991 (define_insn ""
7992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7993 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
7994 (match_operand:SI 2 "reg_or_short_operand" "rI")))
7995 (clobber (match_scratch:SI 3 "=r"))]
7996 "TARGET_POWER"
7997 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
7998 [(set_attr "length" "12")])
7999
8000 (define_insn ""
8001 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8002 (compare:CC
8003 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8004 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8005 (const_int 0)))
8006 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8007 (ge:SI (match_dup 1) (match_dup 2)))
8008 (clobber (match_scratch:SI 3 "=r"))]
8009 "TARGET_POWER"
8010 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3"
8011 [(set_attr "type" "compare")
8012 (set_attr "length" "12")])
8013
8014 (define_insn ""
8015 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8016 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8017 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8018 (match_operand:SI 3 "gpc_reg_operand" "r")))
8019 (clobber (match_scratch:SI 4 "=&r"))]
8020 "TARGET_POWER"
8021 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
8022 [(set_attr "length" "12")])
8023
8024 (define_insn ""
8025 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8026 (compare:CC
8027 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8028 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8029 (match_operand:SI 3 "gpc_reg_operand" "r"))
8030 (const_int 0)))
8031 (clobber (match_scratch:SI 4 "=&r"))]
8032 "TARGET_POWER"
8033 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
8034 [(set_attr "type" "compare")
8035 (set_attr "length" "12")])
8036
8037 (define_insn ""
8038 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8039 (compare:CC
8040 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8041 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8042 (match_operand:SI 3 "gpc_reg_operand" "r"))
8043 (const_int 0)))
8044 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8045 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8046 (clobber (match_scratch:SI 4 "=&r"))]
8047 "TARGET_POWER"
8048 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
8049 [(set_attr "type" "compare")
8050 (set_attr "length" "12")])
8051
8052 (define_insn ""
8053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8054 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8055 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
8056 "TARGET_POWER"
8057 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
8058 [(set_attr "length" "12")])
8059
8060 ;; This is (and (neg (ge X (const_int 0))) Y).
8061 (define_insn ""
8062 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8063 (and:SI (neg:SI
8064 (lshiftrt:SI
8065 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
8066 (const_int 31)))
8067 (match_operand:SI 2 "gpc_reg_operand" "r")))
8068 (clobber (match_scratch:SI 3 "=&r"))]
8069 ""
8070 "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
8071 [(set_attr "length" "8")])
8072
8073 (define_insn ""
8074 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8075 (compare:CC
8076 (and:SI (neg:SI
8077 (lshiftrt:SI
8078 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
8079 (const_int 31)))
8080 (match_operand:SI 2 "gpc_reg_operand" "r"))
8081 (const_int 0)))
8082 (clobber (match_scratch:SI 3 "=&r"))]
8083 ""
8084 "{srai|srawi} %3,%1,31\;andc. %3,%2,%3"
8085 [(set_attr "type" "compare")
8086 (set_attr "length" "8")])
8087
8088 (define_insn ""
8089 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8090 (compare:CC
8091 (and:SI (neg:SI
8092 (lshiftrt:SI
8093 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
8094 (const_int 31)))
8095 (match_operand:SI 2 "gpc_reg_operand" "r"))
8096 (const_int 0)))
8097 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8098 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
8099 (const_int 31)))
8100 (match_dup 2)))
8101 (clobber (match_scratch:SI 3 "=&r"))]
8102 ""
8103 "{srai|srawi} %3,%1,31\;andc. %0,%2,%3"
8104 [(set_attr "type" "compare")
8105 (set_attr "length" "8")])
8106
8107 (define_insn ""
8108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8109 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8110 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
8111 ""
8112 "@
8113 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
8114 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
8115 [(set_attr "length" "12")])
8116
8117 (define_insn ""
8118 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
8119 (compare:CC
8120 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8121 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8122 (const_int 0)))
8123 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8124 (geu:SI (match_dup 1) (match_dup 2)))]
8125 ""
8126 "@
8127 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
8128 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
8129 [(set_attr "type" "compare")
8130 (set_attr "length" "12")])
8131
8132 (define_insn ""
8133 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8134 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8135 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8136 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
8137 (clobber (match_scratch:SI 4 "=&r,&r"))]
8138 ""
8139 "@
8140 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
8141 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
8142 [(set_attr "length" "8")])
8143
8144 (define_insn ""
8145 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8146 (compare:CC
8147 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8148 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8149 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8150 (const_int 0)))
8151 (clobber (match_scratch:SI 4 "=&r,&r"))]
8152 ""
8153 "@
8154 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
8155 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
8156 [(set_attr "type" "compare")
8157 (set_attr "length" "8")])
8158
8159 (define_insn ""
8160 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8161 (compare:CC
8162 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8163 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
8164 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8165 (const_int 0)))
8166 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8167 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8168 (clobber (match_scratch:SI 4 "=&r,&r"))]
8169 ""
8170 "@
8171 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
8172 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
8173 [(set_attr "type" "compare")
8174 (set_attr "length" "8")])
8175
8176 (define_insn ""
8177 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8178 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8179 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
8180 ""
8181 "@
8182 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
8183 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
8184 [(set_attr "length" "12")])
8185
8186 (define_insn ""
8187 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8188 (and:SI (neg:SI
8189 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8190 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
8191 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
8192 (clobber (match_scratch:SI 4 "=&r,&r"))]
8193 ""
8194 "@
8195 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
8196 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
8197 [(set_attr "length" "12")])
8198
8199 (define_insn ""
8200 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8201 (compare:CC
8202 (and:SI (neg:SI
8203 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8204 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
8205 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8206 (const_int 0)))
8207 (clobber (match_scratch:SI 4 "=&r,&r"))]
8208 ""
8209 "@
8210 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
8211 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
8212 [(set_attr "type" "compare")
8213 (set_attr "length" "12")])
8214
8215 (define_insn ""
8216 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8217 (compare:CC
8218 (and:SI (neg:SI
8219 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8220 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
8221 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8222 (const_int 0)))
8223 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8224 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
8225 (clobber (match_scratch:SI 4 "=&r,&r"))]
8226 ""
8227 "@
8228 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
8229 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
8230 [(set_attr "type" "compare")
8231 (set_attr "length" "12")])
8232
8233 (define_insn ""
8234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8235 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8236 (const_int 0)))]
8237 ""
8238 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
8239 [(set_attr "length" "12")])
8240
8241 (define_insn ""
8242 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
8243 (compare:CC
8244 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8245 (const_int 0))
8246 (const_int 0)))
8247 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8248 (gt:SI (match_dup 1) (const_int 0)))]
8249 ""
8250 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
8251 [(set_attr "type" "delayed_compare")
8252 (set_attr "length" "12")])
8253
8254 (define_insn ""
8255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8256 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8257 (match_operand:SI 2 "reg_or_short_operand" "r")))]
8258 "TARGET_POWER"
8259 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
8260 [(set_attr "length" "12")])
8261
8262 (define_insn ""
8263 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
8264 (compare:CC
8265 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8266 (match_operand:SI 2 "reg_or_short_operand" "r"))
8267 (const_int 0)))
8268 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8269 (gt:SI (match_dup 1) (match_dup 2)))]
8270 "TARGET_POWER"
8271 "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
8272 [(set_attr "type" "delayed_compare")
8273 (set_attr "length" "12")])
8274
8275 (define_insn ""
8276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8277 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8278 (const_int 0))
8279 (match_operand:SI 2 "gpc_reg_operand" "r")))
8280 (clobber (match_scratch:SI 3 "=&r"))]
8281 ""
8282 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
8283 [(set_attr "length" "12")])
8284
8285 (define_insn ""
8286 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8287 (compare:CC
8288 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8289 (const_int 0))
8290 (match_operand:SI 2 "gpc_reg_operand" "r"))
8291 (const_int 0)))
8292 (clobber (match_scratch:SI 3 "=&r"))]
8293 ""
8294 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
8295 [(set_attr "type" "compare")
8296 (set_attr "length" "12")])
8297
8298 (define_insn ""
8299 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
8300 (compare:CC
8301 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8302 (const_int 0))
8303 (match_operand:SI 2 "gpc_reg_operand" "r"))
8304 (const_int 0)))
8305 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8306 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
8307 (clobber (match_scratch:SI 3 "=&r"))]
8308 ""
8309 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
8310 [(set_attr "type" "compare")
8311 (set_attr "length" "12")])
8312
8313 (define_insn ""
8314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8315 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8316 (match_operand:SI 2 "reg_or_short_operand" "r"))
8317 (match_operand:SI 3 "gpc_reg_operand" "r")))
8318 (clobber (match_scratch:SI 4 "=&r"))]
8319 "TARGET_POWER"
8320 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
8321 [(set_attr "length" "12")])
8322
8323 (define_insn ""
8324 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
8325 (compare:CC
8326 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8327 (match_operand:SI 2 "reg_or_short_operand" "r"))
8328 (match_operand:SI 3 "gpc_reg_operand" "r"))
8329 (const_int 0)))
8330 (clobber (match_scratch:SI 4 "=&r"))]
8331 "TARGET_POWER"
8332 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
8333 [(set_attr "type" "compare")
8334 (set_attr "length" "12")])
8335
8336 (define_insn ""
8337 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
8338 (compare:CC
8339 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8340 (match_operand:SI 2 "reg_or_short_operand" "r"))
8341 (match_operand:SI 3 "gpc_reg_operand" "r"))
8342 (const_int 0)))
8343 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8344 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8345 (clobber (match_scratch:SI 4 "=&r"))]
8346 "TARGET_POWER"
8347 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
8348 [(set_attr "type" "compare")
8349 (set_attr "length" "12")])
8350
8351 (define_insn ""
8352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8353 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8354 (const_int 0))))]
8355 ""
8356 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
8357 [(set_attr "length" "12")])
8358
8359 (define_insn ""
8360 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8361 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8362 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
8363 "TARGET_POWER"
8364 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
8365 [(set_attr "length" "12")])
8366
8367 (define_insn ""
8368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8369 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8370 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
8371 ""
8372 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
8373 [(set_attr "length" "12")])
8374
8375 (define_insn ""
8376 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
8377 (compare:CC
8378 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8379 (match_operand:SI 2 "reg_or_short_operand" "rI"))
8380 (const_int 0)))
8381 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
8382 (gtu:SI (match_dup 1) (match_dup 2)))]
8383 ""
8384 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
8385 [(set_attr "type" "compare")
8386 (set_attr "length" "12")])
8387
8388 (define_insn ""
8389 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
8390 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
8391 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
8392 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
8393 (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
8394 ""
8395 "@
8396 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
8397 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
8398 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
8399 [(set_attr "length" "8,12,12")])
8400
8401 (define_insn ""
8402 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
8403 (compare:CC
8404 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8405 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
8406 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8407 (const_int 0)))
8408 (clobber (match_scratch:SI 4 "=&r,&r"))]
8409 ""
8410 "@
8411 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
8412 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
8413 [(set_attr "type" "compare")
8414 (set_attr "length" "8,12")])
8415
8416 (define_insn ""
8417 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
8418 (compare:CC
8419 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
8420 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
8421 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8422 (const_int 0)))
8423 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8424 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
8425 (clobber (match_scratch:SI 4 "=&r,&r"))]
8426 ""
8427 "@
8428 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
8429 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
8430 [(set_attr "type" "compare")
8431 (set_attr "length" "8,12")])
8432
8433 (define_insn ""
8434 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8435 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
8436 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
8437 ""
8438 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
8439 [(set_attr "length" "8")])
8440 \f
8441 ;; Define both directions of branch and return. If we need a reload
8442 ;; register, we'd rather use CR0 since it is much easier to copy a
8443 ;; register CC value to there.
8444
8445 (define_insn ""
8446 [(set (pc)
8447 (if_then_else (match_operator 1 "branch_comparison_operator"
8448 [(match_operand 2
8449 "cc_reg_operand" "x,?y")
8450 (const_int 0)])
8451 (label_ref (match_operand 0 "" ""))
8452 (pc)))]
8453 ""
8454 "*
8455 {
8456 if (get_attr_length (insn) == 8)
8457 return \"%C1bc %t1,%j1,%l0\";
8458 else
8459 return \"%C1bc %T1,%j1,$+8\;b %l0\";
8460 }"
8461 [(set_attr "type" "branch")])
8462
8463 (define_insn ""
8464 [(set (pc)
8465 (if_then_else (match_operator 0 "branch_comparison_operator"
8466 [(match_operand 1
8467 "cc_reg_operand" "x,?y")
8468 (const_int 0)])
8469 (return)
8470 (pc)))]
8471 "direct_return ()"
8472 "{%C0bcr|%C0bclr} %t0,%j0"
8473 [(set_attr "length" "8")])
8474
8475 (define_insn ""
8476 [(set (pc)
8477 (if_then_else (match_operator 1 "branch_comparison_operator"
8478 [(match_operand 2
8479 "cc_reg_operand" "x,?y")
8480 (const_int 0)])
8481 (pc)
8482 (label_ref (match_operand 0 "" ""))))]
8483 ""
8484 "*
8485 {
8486 if (get_attr_length (insn) == 8)
8487 return \"%C1bc %T1,%j1,%l0\";
8488 else
8489 return \"%C1bc %t1,%j1,$+8\;b %l0\";
8490 }"
8491 [(set_attr "type" "branch")])
8492
8493 (define_insn ""
8494 [(set (pc)
8495 (if_then_else (match_operator 0 "branch_comparison_operator"
8496 [(match_operand 1
8497 "cc_reg_operand" "x,?y")
8498 (const_int 0)])
8499 (pc)
8500 (return)))]
8501 "direct_return ()"
8502 "{%C0bcr|%C0bclr} %T0,%j0"
8503 [(set_attr "length" "8")])
8504
8505 ;; Unconditional branch and return.
8506
8507 (define_insn "jump"
8508 [(set (pc)
8509 (label_ref (match_operand 0 "" "")))]
8510 ""
8511 "b %l0")
8512
8513 (define_insn "return"
8514 [(return)]
8515 "direct_return ()"
8516 "{br|blr}"
8517 [(set_attr "type" "jmpreg")])
8518
8519 (define_insn "indirect_jump"
8520 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
8521 ""
8522 "@
8523 bctr
8524 {br|blr}"
8525 [(set_attr "type" "jmpreg")])
8526
8527 (define_insn ""
8528 [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))]
8529 "TARGET_POWERPC64"
8530 "@
8531 bctr
8532 {br|blr}"
8533 [(set_attr "type" "jmpreg")])
8534
8535 ;; Table jump for switch statements:
8536 (define_expand "tablejump"
8537 [(use (match_operand 0 "" ""))
8538 (use (label_ref (match_operand 1 "" "")))]
8539 ""
8540 "
8541 {
8542 if (TARGET_32BIT)
8543 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
8544 else
8545 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
8546 DONE;
8547 }")
8548
8549 (define_expand "tablejumpsi"
8550 [(set (match_dup 3)
8551 (plus:SI (match_operand:SI 0 "" "")
8552 (match_dup 2)))
8553 (parallel [(set (pc) (match_dup 3))
8554 (use (label_ref (match_operand 1 "" "")))])]
8555 ""
8556 "
8557 { operands[0] = force_reg (SImode, operands[0]);
8558 operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
8559 operands[3] = gen_reg_rtx (SImode);
8560 }")
8561
8562 (define_expand "tablejumpdi"
8563 [(set (match_dup 3)
8564 (plus:DI (match_operand:DI 0 "" "")
8565 (match_dup 2)))
8566 (parallel [(set (pc) (match_dup 3))
8567 (use (label_ref (match_operand 1 "" "")))])]
8568 ""
8569 "
8570 { operands[0] = force_reg (DImode, operands[0]);
8571 operands[2] = force_reg (DImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
8572 operands[3] = gen_reg_rtx (DImode);
8573 }")
8574
8575 (define_insn ""
8576 [(set (pc)
8577 (match_operand:SI 0 "register_operand" "c,l"))
8578 (use (label_ref (match_operand 1 "" "")))]
8579 ""
8580 "@
8581 bctr
8582 {br|blr}"
8583 [(set_attr "type" "jmpreg")])
8584
8585 (define_insn ""
8586 [(set (pc)
8587 (match_operand:DI 0 "register_operand" "c,l"))
8588 (use (label_ref (match_operand 1 "" "")))]
8589 "TARGET_POWERPC64"
8590 "@
8591 bctr
8592 {br|blr}"
8593 [(set_attr "type" "jmpreg")])
8594
8595 (define_insn "nop"
8596 [(const_int 0)]
8597 ""
8598 "{cror 0,0,0|nop}")
8599 \f
8600 ;; Define the subtract-one-and-jump insns, starting with the template
8601 ;; so loop.c knows what to generate.
8602
8603 (define_expand "decrement_and_branch_on_count"
8604 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "")
8605 (const_int 1))
8606 (label_ref (match_operand 1 "" ""))
8607 (pc)))
8608 (set (match_dup 0)
8609 (plus:SI (match_dup 0)
8610 (const_int -1)))
8611 (clobber (match_scratch:CC 2 ""))
8612 (clobber (match_scratch:SI 3 ""))])]
8613 ""
8614 "")
8615
8616 ;; We need to be able to do this for any operand, including MEM, or we
8617 ;; will cause reload to blow up since we don't allow output reloads on
8618 ;; JUMP_INSNs.
8619 ;; In order that the length attribute is calculated correctly, the
8620 ;; label MUST be operand 0.
8621
8622 (define_insn ""
8623 [(set (pc)
8624 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
8625 (const_int 1))
8626 (label_ref (match_operand 0 "" ""))
8627 (pc)))
8628 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
8629 (plus:SI (match_dup 1)
8630 (const_int -1)))
8631 (clobber (match_scratch:CC 3 "=X,&x,&x"))
8632 (clobber (match_scratch:SI 4 "=X,X,r"))]
8633 ""
8634 "*
8635 {
8636 if (which_alternative != 0)
8637 return \"#\";
8638 else if (get_attr_length (insn) == 8)
8639 return \"{bdn|bdnz} %l0\";
8640 else
8641 return \"bdz $+8\;b %l0\";
8642 }"
8643 [(set_attr "type" "branch")
8644 (set_attr "length" "*,12,16")])
8645
8646 (define_insn ""
8647 [(set (pc)
8648 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
8649 (const_int 1))
8650 (pc)
8651 (label_ref (match_operand 0 "" ""))))
8652 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
8653 (plus:SI (match_dup 1)
8654 (const_int -1)))
8655 (clobber (match_scratch:CC 3 "=X,&x,&x"))
8656 (clobber (match_scratch:SI 4 "=X,X,r"))]
8657 ""
8658 "*
8659 {
8660 if (which_alternative != 0)
8661 return \"#\";
8662 else if (get_attr_length (insn) == 8)
8663 return \"bdz %l0\";
8664 else
8665 return \"{bdn|bdnz} $+8\;b %l0\";
8666 }"
8667 [(set_attr "type" "branch")
8668 (set_attr "length" "*,12,16")])
8669
8670 ;; Similar, but we can use GE since we have a REG_NONNEG.
8671 (define_insn ""
8672 [(set (pc)
8673 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
8674 (const_int 0))
8675 (label_ref (match_operand 0 "" ""))
8676 (pc)))
8677 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
8678 (plus:SI (match_dup 1)
8679 (const_int -1)))
8680 (clobber (match_scratch:CC 3 "=X,&x,&X"))
8681 (clobber (match_scratch:SI 4 "=X,X,r"))]
8682 "find_reg_note (insn, REG_NONNEG, 0)"
8683 "*
8684 {
8685 if (which_alternative != 0)
8686 return \"#\";
8687 else if (get_attr_length (insn) == 8)
8688 return \"{bdn|bdnz} %l0\";
8689 else
8690 return \"bdz $+8\;b %l0\";
8691 }"
8692 [(set_attr "type" "branch")
8693 (set_attr "length" "*,12,16")])
8694
8695 (define_insn ""
8696 [(set (pc)
8697 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
8698 (const_int 0))
8699 (pc)
8700 (label_ref (match_operand 0 "" ""))))
8701 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
8702 (plus:SI (match_dup 1)
8703 (const_int -1)))
8704 (clobber (match_scratch:CC 3 "=X,&x,&X"))
8705 (clobber (match_scratch:SI 4 "=X,X,r"))]
8706 "find_reg_note (insn, REG_NONNEG, 0)"
8707 "*
8708 {
8709 if (which_alternative != 0)
8710 return \"#\";
8711 else if (get_attr_length (insn) == 8)
8712 return \"bdz %l0\";
8713 else
8714 return \"{bdn|bdnz} $+8\;b %l0\";
8715 }"
8716 [(set_attr "type" "branch")
8717 (set_attr "length" "*,12,16")])
8718
8719 (define_insn ""
8720 [(set (pc)
8721 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
8722 (const_int 1))
8723 (label_ref (match_operand 0 "" ""))
8724 (pc)))
8725 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
8726 (plus:SI (match_dup 1)
8727 (const_int -1)))
8728 (clobber (match_scratch:CC 3 "=X,&x,&x"))
8729 (clobber (match_scratch:SI 4 "=X,X,r"))]
8730 ""
8731 "*
8732 {
8733 if (which_alternative != 0)
8734 return \"#\";
8735 else if (get_attr_length (insn) == 8)
8736 return \"bdz %l0\";
8737 else
8738 return \"{bdn|bdnz} $+8\;b %l0\";
8739 }"
8740 [(set_attr "type" "branch")
8741 (set_attr "length" "*,12,16")])
8742
8743 (define_insn ""
8744 [(set (pc)
8745 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
8746 (const_int 1))
8747 (pc)
8748 (label_ref (match_operand 0 "" ""))))
8749 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
8750 (plus:SI (match_dup 1)
8751 (const_int -1)))
8752 (clobber (match_scratch:CC 3 "=X,&x,&x"))
8753 (clobber (match_scratch:SI 4 "=X,X,r"))]
8754 ""
8755 "*
8756 {
8757 if (which_alternative != 0)
8758 return \"#\";
8759 else if (get_attr_length (insn) == 8)
8760 return \"{bdn|bdnz} %l0\";
8761 else
8762 return \"bdz $+8\;b %l0\";
8763 }"
8764 [(set_attr "type" "branch")
8765 (set_attr "length" "*,12,16")])
8766
8767 (define_split
8768 [(set (pc)
8769 (if_then_else (match_operator 2 "comparison_operator"
8770 [(match_operand:SI 1 "gpc_reg_operand" "")
8771 (const_int 1)])
8772 (match_operand 5 "" "")
8773 (match_operand 6 "" "")))
8774 (set (match_operand:SI 0 "gpc_reg_operand" "")
8775 (plus:SI (match_dup 1)
8776 (const_int -1)))
8777 (clobber (match_scratch:CC 3 ""))
8778 (clobber (match_scratch:SI 4 ""))]
8779 "reload_completed"
8780 [(parallel [(set (match_dup 3)
8781 (compare:CC (plus:SI (match_dup 1)
8782 (const_int -1))
8783 (const_int 0)))
8784 (set (match_dup 0)
8785 (plus:SI (match_dup 1)
8786 (const_int -1)))])
8787 (set (pc) (if_then_else (match_dup 7)
8788 (match_dup 5)
8789 (match_dup 6)))]
8790 "
8791 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
8792 const0_rtx); }")
8793
8794 (define_split
8795 [(set (pc)
8796 (if_then_else (match_operator 2 "comparison_operator"
8797 [(match_operand:SI 1 "gpc_reg_operand" "")
8798 (const_int 1)])
8799 (match_operand 5 "" "")
8800 (match_operand 6 "" "")))
8801 (set (match_operand:SI 0 "general_operand" "")
8802 (plus:SI (match_dup 1) (const_int -1)))
8803 (clobber (match_scratch:CC 3 ""))
8804 (clobber (match_scratch:SI 4 ""))]
8805 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
8806 [(parallel [(set (match_dup 3)
8807 (compare:CC (plus:SI (match_dup 1)
8808 (const_int -1))
8809 (const_int 0)))
8810 (set (match_dup 4)
8811 (plus:SI (match_dup 1)
8812 (const_int -1)))])
8813 (set (match_dup 0)
8814 (match_dup 4))
8815 (set (pc) (if_then_else (match_dup 7)
8816 (match_dup 5)
8817 (match_dup 6)))]
8818 "
8819 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
8820 const0_rtx); }")
GNU Compiler Collection
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