1 ;; Machine description for IBM RISC System
6000 (POWER) for GNU C compiler
2 ;; Copyright (C)
1990,
91,
92,
93,
94,
95,
1996 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version
2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
20 ;; Boston, MA
02111-
1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Define an insn type attribute. This is used in function unit delay
26 (define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
27 (const_string "integer"))
30 (define_attr "length" ""
31 (if_then_else (eq_attr "type" "branch")
32 (if_then_else (and (ge (minus (pc) (match_dup
0))
34 (lt (minus (pc) (match_dup
0))
40 ;; Processor type -- this attribute must exactly match the processor_type
41 ;; enumeration in rs6000.h.
43 (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"
44 (const (symbol_ref "rs6000_cpu_attr")))
46 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
47 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
49 ; Load/Store Unit -- pure PowerPC only
50 ; (POWER and
601 use Integer Unit)
51 (define_function_unit "lsu"
1 0
52 (and (eq_attr "type" "load")
53 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
56 (define_function_unit "lsu"
1 0
57 (and (eq_attr "type" "store,fpstore")
58 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc620"))
61 (define_function_unit "lsu"
1 0
62 (and (eq_attr "type" "fpload")
63 (eq_attr "cpu" "mpccore,ppc603"))
66 (define_function_unit "lsu"
1 0
67 (and (eq_attr "type" "fpload")
68 (eq_attr "cpu" "ppc604,ppc620"))
71 (define_function_unit "iu"
1 0
72 (and (eq_attr "type" "load")
73 (eq_attr "cpu" "rios1,ppc403,ppc601"))
76 (define_function_unit "iu"
1 0
77 (and (eq_attr "type" "store,fpstore")
78 (eq_attr "cpu" "rios1,ppc403,ppc601"))
81 (define_function_unit "fpu"
1 0
82 (and (eq_attr "type" "fpstore")
83 (eq_attr "cpu" "rios1,ppc601"))
86 (define_function_unit "iu"
1 0
87 (and (eq_attr "type" "fpload")
88 (eq_attr "cpu" "rios1"))
91 (define_function_unit "iu"
1 0
92 (and (eq_attr "type" "fpload")
93 (eq_attr "cpu" "ppc601"))
96 (define_function_unit "iu2"
2 0
97 (and (eq_attr "type" "load,fpload")
98 (eq_attr "cpu" "rios2"))
101 (define_function_unit "iu2"
2 0
102 (and (eq_attr "type" "store,fpstore")
103 (eq_attr "cpu" "rios2"))
106 ; Integer Unit (RIOS1, PPC601, PPC603)
107 (define_function_unit "iu"
1 0
108 (and (eq_attr "type" "integer")
109 (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
112 (define_function_unit "iu"
1 0
113 (and (eq_attr "type" "imul")
114 (eq_attr "cpu" "ppc403"))
117 (define_function_unit "iu"
1 0
118 (and (eq_attr "type" "imul")
119 (eq_attr "cpu" "rios1,ppc601,ppc603"))
122 (define_function_unit "iu"
1 0
123 (and (eq_attr "type" "idiv")
124 (eq_attr "cpu" "rios1"))
127 (define_function_unit "iu"
1 0
128 (and (eq_attr "type" "idiv")
129 (eq_attr "cpu" "ppc403"))
132 (define_function_unit "iu"
1 0
133 (and (eq_attr "type" "idiv")
134 (eq_attr "cpu" "ppc601"))
137 (define_function_unit "iu"
1 0
138 (and (eq_attr "type" "idiv")
139 (eq_attr "cpu" "ppc603"))
142 ; RIOS2 has two integer units: a primary one which can perform all
143 ; operations and a secondary one which is fed in lock step with the first
144 ; and can perform "simple" integer operations.
145 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
146 ; for the complex insns.
147 (define_function_unit "iu2"
2 0
148 (and (eq_attr "type" "integer")
149 (eq_attr "cpu" "rios2"))
152 (define_function_unit "iu2"
2 0
153 (and (eq_attr "type" "imul")
154 (eq_attr "cpu" "rios2"))
157 (define_function_unit "iu2"
2 0
158 (and (eq_attr "type" "idiv")
159 (eq_attr "cpu" "rios2"))
162 (define_function_unit "imuldiv"
1 0
163 (and (eq_attr "type" "imul")
164 (eq_attr "cpu" "rios2"))
167 (define_function_unit "imuldiv"
1 0
168 (and (eq_attr "type" "idiv")
169 (eq_attr "cpu" "rios2"))
172 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
173 ; Divide latency varies greatly from
2-
11, use
6 as average
174 (define_function_unit "imuldiv"
1 0
175 (and (eq_attr "type" "imul")
176 (eq_attr "cpu" "mpccore"))
179 (define_function_unit "imuldiv"
1 0
180 (and (eq_attr "type" "idiv")
181 (eq_attr "cpu" "mpccore"))
184 ; PPC604 has two units that perform integer operations
185 ; and one unit for divide/multiply operations (and move
187 (define_function_unit "iu2"
2 0
188 (and (eq_attr "type" "integer")
189 (eq_attr "cpu" "ppc604,ppc620"))
192 (define_function_unit "imuldiv"
1 0
193 (and (eq_attr "type" "imul")
194 (eq_attr "cpu" "ppc604,ppc620"))
197 (define_function_unit "imuldiv"
1 0
198 (and (eq_attr "type" "idiv")
199 (eq_attr "cpu" "ppc604,ppc620"))
202 ; compare is done on integer unit, but feeds insns which
203 ; execute on the branch unit.
204 (define_function_unit "iu"
1 0
205 (and (eq_attr "type" "compare")
206 (eq_attr "cpu" "rios1"))
209 (define_function_unit "iu"
1 0
210 (and (eq_attr "type" "delayed_compare")
211 (eq_attr "cpu" "rios1"))
214 (define_function_unit "iu"
1 0
215 (and (eq_attr "type" "compare,delayed_compare")
216 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
219 (define_function_unit "iu2"
2 0
220 (and (eq_attr "type" "compare,delayed_compare")
221 (eq_attr "cpu" "rios2"))
224 (define_function_unit "iu2"
2 0
225 (and (eq_attr "type" "compare,delayed_compare")
226 (eq_attr "cpu" "ppc604,ppc620"))
229 ; fp compare uses fp unit
230 (define_function_unit "fpu"
1 0
231 (and (eq_attr "type" "fpcompare")
232 (eq_attr "cpu" "rios1"))
235 ; rios1 and rios2 have different fpcompare delays
236 (define_function_unit "fpu2"
2 0
237 (and (eq_attr "type" "fpcompare")
238 (eq_attr "cpu" "rios2"))
241 ; on ppc601 and ppc603, fpcompare takes also
2 cycles from
243 ; here we do not define delays, just occupy the unit. The dependencies
244 ; will be assigned by the fpcompare definition in the fpu.
245 (define_function_unit "iu"
1 0
246 (and (eq_attr "type" "fpcompare")
247 (eq_attr "cpu" "ppc601,ppc603"))
250 ; fp compare uses fp unit
251 (define_function_unit "fpu"
1 0
252 (and (eq_attr "type" "fpcompare")
253 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
256 (define_function_unit "fpu"
1 0
257 (and (eq_attr "type" "fpcompare")
258 (eq_attr "cpu" "mpccore"))
261 (define_function_unit "bpu"
1 0
262 (and (eq_attr "type" "mtjmpr")
263 (eq_attr "cpu" "rios1,rios2"))
266 (define_function_unit "bpu"
1 0
267 (and (eq_attr "type" "mtjmpr")
268 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc620"))
271 ; all jumps/branches are executing on the bpu, in
1 cycle, for all machines.
272 (define_function_unit "bpu"
1 0
273 (eq_attr "type" "jmpreg")
276 (define_function_unit "bpu"
1 0
277 (eq_attr "type" "branch")
280 ; Floating Point Unit
281 (define_function_unit "fpu"
1 0
282 (and (eq_attr "type" "fp,dmul")
283 (eq_attr "cpu" "rios1"))
286 (define_function_unit "fpu"
1 0
287 (and (eq_attr "type" "fp")
288 (eq_attr "cpu" "mpccore"))
291 (define_function_unit "fpu"
1 0
292 (and (eq_attr "type" "fp")
293 (eq_attr "cpu" "ppc601"))
296 (define_function_unit "fpu"
1 0
297 (and (eq_attr "type" "fp")
298 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
301 (define_function_unit "fpu"
1 0
302 (and (eq_attr "type" "dmul")
303 (eq_attr "cpu" "mpccore"))
306 (define_function_unit "fpu"
1 0
307 (and (eq_attr "type" "dmul")
308 (eq_attr "cpu" "ppc601"))
312 (define_function_unit "fpu"
1 0
313 (and (eq_attr "type" "dmul")
314 (eq_attr "cpu" "ppc603"))
317 (define_function_unit "fpu"
1 0
318 (and (eq_attr "type" "dmul")
319 (eq_attr "cpu" "ppc604,ppc620"))
322 (define_function_unit "fpu"
1 0
323 (and (eq_attr "type" "sdiv,ddiv")
324 (eq_attr "cpu" "rios1"))
327 (define_function_unit "fpu"
1 0
328 (and (eq_attr "type" "sdiv")
329 (eq_attr "cpu" "ppc601"))
332 (define_function_unit "fpu"
1 0
333 (and (eq_attr "type" "sdiv")
334 (eq_attr "cpu" "mpccore"))
337 (define_function_unit "fpu"
1 0
338 (and (eq_attr "type" "sdiv")
339 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
342 (define_function_unit "fpu"
1 0
343 (and (eq_attr "type" "ddiv")
344 (eq_attr "cpu" "mpccore"))
347 (define_function_unit "fpu"
1 0
348 (and (eq_attr "type" "ddiv")
349 (eq_attr "cpu" "ppc601,ppc604,ppc620"))
352 (define_function_unit "fpu"
1 0
353 (and (eq_attr "type" "ddiv")
354 (eq_attr "cpu" "ppc603"))
357 (define_function_unit "fpu"
1 0
358 (and (eq_attr "type" "ssqrt")
359 (eq_attr "cpu" "ppc620"))
362 (define_function_unit "fpu"
1 0
363 (and (eq_attr "type" "dsqrt")
364 (eq_attr "cpu" "ppc620"))
367 ; RIOS2 has two symmetric FPUs.
368 (define_function_unit "fpu2"
2 0
369 (and (eq_attr "type" "fp")
370 (eq_attr "cpu" "rios2"))
373 (define_function_unit "fpu2"
2 0
374 (and (eq_attr "type" "dmul")
375 (eq_attr "cpu" "rios2"))
378 (define_function_unit "fpu2"
2 0
379 (and (eq_attr "type" "sdiv,ddiv")
380 (eq_attr "cpu" "rios2"))
383 (define_function_unit "fpu2"
2 0
384 (and (eq_attr "type" "ssqrt,dsqrt")
385 (eq_attr "cpu" "rios2"))
389 ;; Start with fixed-point load and store insns. Here we put only the more
390 ;; complex forms. Basic data transfer is done later.
392 (define_expand "zero_extendqidi2"
393 [(set (match_operand:DI
0 "gpc_reg_operand" "")
394 (zero_extend:DI (match_operand:QI
1 "gpc_reg_operand" "")))]
399 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
400 (zero_extend:DI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
405 [(set_attr "type" "load,*")])
408 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
409 (compare:CC (zero_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
411 (clobber (match_scratch:DI
2 "=r"))]
414 [(set_attr "type" "compare")])
417 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
418 (compare:CC (zero_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
420 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
421 (zero_extend:DI (match_dup
1)))]
424 [(set_attr "type" "compare")])
426 (define_insn "extendqidi2"
427 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
428 (sign_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r")))]
433 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
434 (compare:CC (sign_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
436 (clobber (match_scratch:DI
2 "=r"))]
439 [(set_attr "type" "compare")])
442 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
443 (compare:CC (sign_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
445 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
446 (sign_extend:DI (match_dup
1)))]
449 [(set_attr "type" "compare")])
451 (define_expand "zero_extendhidi2"
452 [(set (match_operand:DI
0 "gpc_reg_operand" "")
453 (zero_extend:DI (match_operand:HI
1 "gpc_reg_operand" "")))]
458 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
459 (zero_extend:DI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
464 [(set_attr "type" "load,*")])
467 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
468 (compare:CC (zero_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
470 (clobber (match_scratch:DI
2 "=r"))]
473 [(set_attr "type" "compare")])
476 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
477 (compare:CC (zero_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
479 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
480 (zero_extend:DI (match_dup
1)))]
483 [(set_attr "type" "compare")])
485 (define_expand "extendhidi2"
486 [(set (match_operand:DI
0 "gpc_reg_operand" "")
487 (sign_extend:DI (match_operand:HI
1 "gpc_reg_operand" "")))]
492 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
498 [(set_attr "type" "load,*")])
501 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
502 (compare:CC (sign_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
504 (clobber (match_scratch:DI
2 "=r"))]
507 [(set_attr "type" "compare")])
510 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
511 (compare:CC (sign_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
513 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
514 (sign_extend:DI (match_dup
1)))]
517 [(set_attr "type" "compare")])
519 (define_expand "zero_extendsidi2"
520 [(set (match_operand:DI
0 "gpc_reg_operand" "")
521 (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "")))]
526 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
527 (zero_extend:DI (match_operand:SI
1 "reg_or_mem_operand" "m,r")))]
532 [(set_attr "type" "load,*")])
535 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
536 (compare:CC (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
538 (clobber (match_scratch:DI
2 "=r"))]
541 [(set_attr "type" "compare")])
544 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
545 (compare:CC (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
547 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
548 (zero_extend:DI (match_dup
1)))]
551 [(set_attr "type" "compare")])
553 (define_expand "extendsidi2"
554 [(set (match_operand:DI
0 "gpc_reg_operand" "")
555 (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "")))]
560 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
561 (sign_extend:DI (match_operand:SI
1 "lwa_operand" "m,r")))]
566 [(set_attr "type" "load,*")])
569 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
570 (compare:CC (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
572 (clobber (match_scratch:DI
2 "=r"))]
575 [(set_attr "type" "compare")])
578 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
579 (compare:CC (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
581 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
582 (sign_extend:DI (match_dup
1)))]
585 [(set_attr "type" "compare")])
587 (define_expand "zero_extendqisi2"
588 [(set (match_operand:SI
0 "gpc_reg_operand" "")
589 (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "")))]
594 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
595 (zero_extend:SI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
599 {rlinm|rlwinm} %
0,%
1,
0,
0xff"
600 [(set_attr "type" "load,*")])
603 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
604 (compare:CC (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
606 (clobber (match_scratch:SI
2 "=r"))]
608 "{andil.|andi.} %
2,%
1,
0xff"
609 [(set_attr "type" "compare")])
612 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
613 (compare:CC (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
615 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
616 (zero_extend:SI (match_dup
1)))]
618 "{andil.|andi.} %
0,%
1,
0xff"
619 [(set_attr "type" "compare")])
621 (define_expand "extendqisi2"
622 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
623 (use (match_operand:QI
1 "gpc_reg_operand" ""))]
628 emit_insn (gen_extendqisi2_ppc (operands[
0], operands[
1]));
629 else if (TARGET_POWER)
630 emit_insn (gen_extendqisi2_power (operands[
0], operands[
1]));
632 emit_insn (gen_extendqisi2_no_power (operands[
0], operands[
1]));
636 (define_insn "extendqisi2_ppc"
637 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
638 (sign_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r")))]
643 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
644 (compare:CC (sign_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
646 (clobber (match_scratch:SI
2 "=r"))]
649 [(set_attr "type" "compare")])
652 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
653 (compare:CC (sign_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
655 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
656 (sign_extend:SI (match_dup
1)))]
659 [(set_attr "type" "compare")])
661 (define_expand "extendqisi2_power"
662 [(parallel [(set (match_dup
2)
663 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
665 (clobber (scratch:SI))])
666 (parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
667 (ashiftrt:SI (match_dup
2)
669 (clobber (scratch:SI))])]
672 { operands[
1] = gen_lowpart (SImode, operands[
1]);
673 operands[
2] = gen_reg_rtx (SImode); }")
675 (define_expand "extendqisi2_no_power"
677 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
679 (set (match_operand:SI
0 "gpc_reg_operand" "")
680 (ashiftrt:SI (match_dup
2)
682 "! TARGET_POWER && ! TARGET_POWERPC"
684 { operands[
1] = gen_lowpart (SImode, operands[
1]);
685 operands[
2] = gen_reg_rtx (SImode); }")
687 (define_expand "zero_extendqihi2"
688 [(set (match_operand:HI
0 "gpc_reg_operand" "")
689 (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "")))]
694 [(set (match_operand:HI
0 "gpc_reg_operand" "=r,r")
695 (zero_extend:HI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
699 {rlinm|rlwinm} %
0,%
1,
0,
0xff"
700 [(set_attr "type" "load,*")])
703 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
704 (compare:CC (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
706 (clobber (match_scratch:HI
2 "=r"))]
708 "{andil.|andi.} %
2,%
1,
0xff"
709 [(set_attr "type" "compare")])
712 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
713 (compare:CC (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
715 (set (match_operand:HI
0 "gpc_reg_operand" "=r")
716 (zero_extend:HI (match_dup
1)))]
718 "{andil.|andi.} %
0,%
1,
0xff"
719 [(set_attr "type" "compare")])
721 (define_expand "extendqihi2"
722 [(use (match_operand:HI
0 "gpc_reg_operand" ""))
723 (use (match_operand:QI
1 "gpc_reg_operand" ""))]
728 emit_insn (gen_extendqihi2_ppc (operands[
0], operands[
1]));
729 else if (TARGET_POWER)
730 emit_insn (gen_extendqihi2_power (operands[
0], operands[
1]));
732 emit_insn (gen_extendqihi2_no_power (operands[
0], operands[
1]));
736 (define_insn "extendqihi2_ppc"
737 [(set (match_operand:HI
0 "gpc_reg_operand" "=r")
738 (sign_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r")))]
743 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
744 (compare:CC (sign_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
746 (clobber (match_scratch:HI
2 "=r"))]
749 [(set_attr "type" "compare")])
752 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
753 (compare:CC (sign_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
755 (set (match_operand:HI
0 "gpc_reg_operand" "=r")
756 (sign_extend:HI (match_dup
1)))]
759 [(set_attr "type" "compare")])
761 (define_expand "extendqihi2_power"
762 [(parallel [(set (match_dup
2)
763 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
765 (clobber (scratch:SI))])
766 (parallel [(set (match_operand:HI
0 "gpc_reg_operand" "")
767 (ashiftrt:SI (match_dup
2)
769 (clobber (scratch:SI))])]
772 { operands[
0] = gen_lowpart (SImode, operands[
0]);
773 operands[
1] = gen_lowpart (SImode, operands[
1]);
774 operands[
2] = gen_reg_rtx (SImode); }")
776 (define_expand "extendqihi2_no_power"
778 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
780 (set (match_operand:HI
0 "gpc_reg_operand" "")
781 (ashiftrt:SI (match_dup
2)
783 "! TARGET_POWER && ! TARGET_POWERPC"
785 { operands[
0] = gen_lowpart (SImode, operands[
0]);
786 operands[
1] = gen_lowpart (SImode, operands[
1]);
787 operands[
2] = gen_reg_rtx (SImode); }")
789 (define_expand "zero_extendhisi2"
790 [(set (match_operand:SI
0 "gpc_reg_operand" "")
791 (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "")))]
796 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
797 (zero_extend:SI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
801 {rlinm|rlwinm} %
0,%
1,
0,
0xffff"
802 [(set_attr "type" "load,*")])
805 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
806 (compare:CC (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
808 (clobber (match_scratch:SI
2 "=r"))]
810 "{andil.|andi.} %
2,%
1,
0xffff"
811 [(set_attr "type" "compare")])
814 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
815 (compare:CC (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
817 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
818 (zero_extend:SI (match_dup
1)))]
820 "{andil.|andi.} %
0,%
1,
0xffff"
821 [(set_attr "type" "compare")])
823 (define_expand "extendhisi2"
824 [(set (match_operand:SI
0 "gpc_reg_operand" "")
825 (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "")))]
830 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
831 (sign_extend:SI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
836 [(set_attr "type" "load,*")])
839 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
840 (compare:CC (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
842 (clobber (match_scratch:SI
2 "=r"))]
844 "{exts.|extsh.} %
2,%
1"
845 [(set_attr "type" "compare")])
848 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
849 (compare:CC (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
851 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
852 (sign_extend:SI (match_dup
1)))]
854 "{exts.|extsh.} %
0,%
1"
855 [(set_attr "type" "compare")])
857 ;; Fixed-point arithmetic insns.
859 ;; Discourage ai/addic because of carry but provide it in an alternative
860 ;; allowing register zero as source.
861 (define_insn "addsi3"
862 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,?r,r")
863 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,b,r,b")
864 (match_operand:SI
2 "add_operand" "r,I,I,J")))]
868 {cal %
0,%
2(%
1)|addi %
0,%
1,%
2}
870 {cau|addis} %
0,%
1,%v2")
873 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
874 (compare:CC (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
875 (match_operand:SI
2 "reg_or_short_operand" "r,I"))
877 (clobber (match_scratch:SI
3 "=r,r"))]
881 {ai.|addic.} %
3,%
1,%
2"
882 [(set_attr "type" "compare")])
885 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
886 (compare:CC (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
887 (match_operand:SI
2 "reg_or_short_operand" "r,I"))
889 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
890 (plus:SI (match_dup
1) (match_dup
2)))]
894 {ai.|addic.} %
0,%
1,%
2"
895 [(set_attr "type" "compare")])
897 ;; Split an add that we can't do in one insn into two insns, each of which
898 ;; does one
16-bit part. This is used by combine. Note that the low-order
899 ;; add should be last in case the result gets used in an address.
902 [(set (match_operand:SI
0 "gpc_reg_operand" "")
903 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "")
904 (match_operand:SI
2 "non_add_cint_operand" "")))]
906 [(set (match_dup
0) (plus:SI (match_dup
1) (match_dup
3)))
907 (set (match_dup
0) (plus:SI (match_dup
0) (match_dup
4)))]
910 HOST_WIDE_INT low = INTVAL (operands[
2]) &
0xffff;
911 HOST_WIDE_INT high = INTVAL (operands[
2]) & (~ (HOST_WIDE_INT)
0xffff);
914 high +=
0x10000, low |= ((HOST_WIDE_INT) -
1) <<
16;
916 operands[
3] = GEN_INT (high);
917 operands[
4] = GEN_INT (low);
920 (define_insn "one_cmplsi2"
921 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
922 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
927 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
928 (compare:CC (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
930 (clobber (match_scratch:SI
2 "=r"))]
933 [(set_attr "type" "compare")])
936 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
937 (compare:CC (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
939 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
940 (not:SI (match_dup
1)))]
943 [(set_attr "type" "compare")])
946 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
947 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "rI")
948 (match_operand:SI
2 "gpc_reg_operand" "r")))]
950 "{sf%I1|subf%I1c} %
0,%
2,%
1")
953 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
954 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "r,I")
955 (match_operand:SI
2 "gpc_reg_operand" "r,r")))]
962 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
963 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
964 (match_operand:SI
2 "gpc_reg_operand" "r"))
966 (clobber (match_scratch:SI
3 "=r"))]
968 "{sf.|subfc.} %
3,%
2,%
1"
969 [(set_attr "type" "compare")])
972 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
973 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
974 (match_operand:SI
2 "gpc_reg_operand" "r"))
976 (clobber (match_scratch:SI
3 "=r"))]
979 [(set_attr "type" "compare")])
982 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
983 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
984 (match_operand:SI
2 "gpc_reg_operand" "r"))
986 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
987 (minus:SI (match_dup
1) (match_dup
2)))]
989 "{sf.|subfc.} %
0,%
2,%
1"
990 [(set_attr "type" "compare")])
993 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
994 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
995 (match_operand:SI
2 "gpc_reg_operand" "r"))
997 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
998 (minus:SI (match_dup
1) (match_dup
2)))]
1001 [(set_attr "type" "compare")])
1003 (define_expand "subsi3"
1004 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1005 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "")
1006 (match_operand:SI
2 "reg_or_cint_operand" "")))]
1010 if (GET_CODE (operands[
2]) == CONST_INT)
1012 emit_insn (gen_addsi3 (operands[
0], operands[
1],
1013 negate_rtx (SImode, operands[
2])));
1018 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1019 ;; instruction and some auxiliary computations. Then we just have a single
1020 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1023 (define_expand "sminsi3"
1025 (if_then_else:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "")
1026 (match_operand:SI
2 "reg_or_short_operand" ""))
1028 (minus:SI (match_dup
2) (match_dup
1))))
1029 (set (match_operand:SI
0 "gpc_reg_operand" "")
1030 (minus:SI (match_dup
2) (match_dup
3)))]
1033 { operands[
3] = gen_reg_rtx (SImode); }")
1036 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1037 (smin:SI (match_operand:SI
1 "gpc_reg_operand" "")
1038 (match_operand:SI
2 "reg_or_short_operand" "")))
1039 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
1042 (if_then_else:SI (gt:SI (match_dup
1) (match_dup
2))
1044 (minus:SI (match_dup
2) (match_dup
1))))
1045 (set (match_dup
0) (minus:SI (match_dup
2) (match_dup
3)))]
1048 (define_expand "smaxsi3"
1050 (if_then_else:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "")
1051 (match_operand:SI
2 "reg_or_short_operand" ""))
1053 (minus:SI (match_dup
2) (match_dup
1))))
1054 (set (match_operand:SI
0 "gpc_reg_operand" "")
1055 (plus:SI (match_dup
3) (match_dup
1)))]
1058 { operands[
3] = gen_reg_rtx (SImode); }")
1061 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1062 (smax:SI (match_operand:SI
1 "gpc_reg_operand" "")
1063 (match_operand:SI
2 "reg_or_short_operand" "")))
1064 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
1067 (if_then_else:SI (gt:SI (match_dup
1) (match_dup
2))
1069 (minus:SI (match_dup
2) (match_dup
1))))
1070 (set (match_dup
0) (plus:SI (match_dup
3) (match_dup
1)))]
1073 (define_expand "uminsi3"
1074 [(set (match_dup
3) (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1076 (set (match_dup
4) (xor:SI (match_operand:SI
2 "gpc_reg_operand" "")
1078 (set (match_dup
3) (if_then_else:SI (gt (match_dup
3) (match_dup
4))
1080 (minus:SI (match_dup
4) (match_dup
3))))
1081 (set (match_operand:SI
0 "gpc_reg_operand" "")
1082 (minus:SI (match_dup
2) (match_dup
3)))]
1086 operands[
3] = gen_reg_rtx (SImode);
1087 operands[
4] = gen_reg_rtx (SImode);
1088 operands[
5] = GEN_INT (-
2147483647 -
1);
1091 (define_expand "umaxsi3"
1092 [(set (match_dup
3) (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1094 (set (match_dup
4) (xor:SI (match_operand:SI
2 "gpc_reg_operand" "")
1096 (set (match_dup
3) (if_then_else:SI (gt (match_dup
3) (match_dup
4))
1098 (minus:SI (match_dup
4) (match_dup
3))))
1099 (set (match_operand:SI
0 "gpc_reg_operand" "")
1100 (plus:SI (match_dup
3) (match_dup
1)))]
1104 operands[
3] = gen_reg_rtx (SImode);
1105 operands[
4] = gen_reg_rtx (SImode);
1106 operands[
5] = GEN_INT (-
2147483647 -
1);
1110 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1111 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
1112 (match_operand:SI
2 "reg_or_short_operand" "rI"))
1114 (minus:SI (match_dup
2) (match_dup
1))))]
1119 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1121 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
1122 (match_operand:SI
2 "reg_or_short_operand" "rI"))
1124 (minus:SI (match_dup
2) (match_dup
1)))
1126 (clobber (match_scratch:SI
3 "=r"))]
1129 [(set_attr "type" "delayed_compare")])
1132 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1134 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
1135 (match_operand:SI
2 "reg_or_short_operand" "rI"))
1137 (minus:SI (match_dup
2) (match_dup
1)))
1139 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1140 (if_then_else:SI (gt (match_dup
1) (match_dup
2))
1142 (minus:SI (match_dup
2) (match_dup
1))))]
1145 [(set_attr "type" "delayed_compare")])
1147 ;; We don't need abs with condition code because such comparisons should
1149 (define_expand "abssi2"
1150 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1151 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "")))]
1157 emit_insn (gen_abssi2_nopower (operands[
0], operands[
1]));
1162 (define_insn "abssi2_power"
1163 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1164 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
1168 (define_insn "abssi2_nopower"
1169 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1170 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0")))
1171 (clobber (match_scratch:SI
2 "=&r,&r"))]
1175 return (TARGET_POWERPC)
1176 ?
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
2,%
0\"
1177 :
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;{sf|subfc} %
0,%
2,%
0\";
1179 [(set_attr "length" "
12")])
1182 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1183 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0")))
1184 (clobber (match_scratch:SI
2 "=&r,&r"))]
1185 "!TARGET_POWER && reload_completed"
1186 [(set (match_dup
2) (ashiftrt:SI (match_dup
1) (const_int
31)))
1187 (set (match_dup
0) (xor:SI (match_dup
2) (match_dup
1)))
1188 (set (match_dup
0) (minus:SI (match_dup
2) (match_dup
0)))]
1192 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1193 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r"))))]
1198 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1199 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0"))))
1200 (clobber (match_scratch:SI
2 "=&r,&r"))]
1204 return (TARGET_POWERPC)
1205 ?
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
0,%
2\"
1206 :
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;{sf|subfc} %
0,%
0,%
2\";
1208 [(set_attr "length" "
12")])
1211 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1212 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0"))))
1213 (clobber (match_scratch:SI
2 "=&r,&r"))]
1214 "!TARGET_POWER && reload_completed"
1215 [(set (match_dup
2) (ashiftrt:SI (match_dup
1) (const_int
31)))
1216 (set (match_dup
0) (xor:SI (match_dup
2) (match_dup
1)))
1217 (set (match_dup
0) (minus:SI (match_dup
0) (match_dup
2)))]
1220 (define_insn "negsi2"
1221 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1222 (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
1227 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1228 (compare:CC (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1230 (clobber (match_scratch:SI
2 "=r"))]
1233 [(set_attr "type" "compare")])
1236 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
1237 (compare:CC (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1239 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1240 (neg:SI (match_dup
1)))]
1243 [(set_attr "type" "compare")])
1245 (define_insn "ffssi2"
1246 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r")
1247 (ffs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
1249 "neg %
0,%
1\;and %
0,%
0,%
1\;{cntlz|cntlzw} %
0,%
0\;{sfi|subfic} %
0,%
0,
32"
1250 [(set_attr "length" "
16")])
1252 (define_expand "mulsi3"
1253 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
1254 (use (match_operand:SI
1 "gpc_reg_operand" ""))
1255 (use (match_operand:SI
2 "reg_or_short_operand" ""))]
1260 emit_insn (gen_mulsi3_mq (operands[
0], operands[
1], operands[
2]));
1262 emit_insn (gen_mulsi3_no_mq (operands[
0], operands[
1], operands[
2]));
1266 (define_insn "mulsi3_mq"
1267 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1268 (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
1269 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
1270 (clobber (match_scratch:SI
3 "=q,q"))]
1273 {muls|mullw} %
0,%
1,%
2
1274 {muli|mulli} %
0,%
1,%
2"
1275 [(set_attr "type" "imul")])
1277 (define_insn "mulsi3_no_mq"
1278 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1279 (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
1280 (match_operand:SI
2 "reg_or_short_operand" "r,I")))]
1283 {muls|mullw} %
0,%
1,%
2
1284 {muli|mulli} %
0,%
1,%
2"
1285 [(set_attr "type" "imul")])
1288 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1289 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1290 (match_operand:SI
2 "gpc_reg_operand" "r"))
1292 (clobber (match_scratch:SI
3 "=r"))
1293 (clobber (match_scratch:SI
4 "=q"))]
1295 "{muls.|mullw.} %
3,%
1,%
2"
1296 [(set_attr "type" "delayed_compare")])
1299 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1300 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1301 (match_operand:SI
2 "gpc_reg_operand" "r"))
1303 (clobber (match_scratch:SI
3 "=r"))]
1305 "{muls.|mullw.} %
3,%
1,%
2"
1306 [(set_attr "type" "delayed_compare")])
1309 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1310 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1311 (match_operand:SI
2 "gpc_reg_operand" "r"))
1313 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1314 (mult:SI (match_dup
1) (match_dup
2)))
1315 (clobber (match_scratch:SI
4 "=q"))]
1317 "{muls.|mullw.} %
0,%
1,%
2"
1318 [(set_attr "type" "delayed_compare")])
1321 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1322 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1323 (match_operand:SI
2 "gpc_reg_operand" "r"))
1325 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1326 (mult:SI (match_dup
1) (match_dup
2)))]
1328 "{muls.|mullw.} %
0,%
1,%
2"
1329 [(set_attr "type" "delayed_compare")])
1331 ;; Operand
1 is divided by operand
2; quotient goes to operand
1332 ;;
0 and remainder to operand
3.
1333 ;; ??? At some point, see what, if anything, we can do about if (x % y ==
0).
1335 (define_expand "divmodsi4"
1336 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
1337 (div:SI (match_operand:SI
1 "gpc_reg_operand" "")
1338 (match_operand:SI
2 "gpc_reg_operand" "")))
1339 (set (match_operand:SI
3 "gpc_reg_operand" "")
1340 (mod:SI (match_dup
1) (match_dup
2)))])]
1341 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1344 if (! TARGET_POWER && ! TARGET_POWERPC)
1346 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1347 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1348 emit_insn (gen_divss_call ());
1349 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1350 emit_move_insn (operands[
3], gen_rtx (REG, SImode,
4));
1356 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1357 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1358 (match_operand:SI
2 "gpc_reg_operand" "r")))
1359 (set (match_operand:SI
3 "gpc_reg_operand" "=q")
1360 (mod:SI (match_dup
1) (match_dup
2)))]
1363 [(set_attr "type" "idiv")])
1366 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1367 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1368 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1371 [(set_attr "type" "idiv")])
1373 (define_expand "udivsi3"
1374 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1375 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "")
1376 (match_operand:SI
2 "gpc_reg_operand" "")))]
1377 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1380 if (! TARGET_POWER && ! TARGET_POWERPC)
1382 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1383 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1384 emit_insn (gen_quous_call ());
1385 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1391 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1392 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1393 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1396 [(set_attr "type" "idiv")])
1398 ;; For powers of two we can do srai/aze for divide and then adjust for
1399 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1400 ;; used; for PowerPC, force operands into register and do a normal divide;
1401 ;; for AIX common-mode, use quoss call on register operands.
1402 (define_expand "divsi3"
1403 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1404 (div:SI (match_operand:SI
1 "gpc_reg_operand" "")
1405 (match_operand:SI
2 "reg_or_cint_operand" "")))]
1409 if (GET_CODE (operands[
2]) == CONST_INT
1410 && exact_log2 (INTVAL (operands[
2])) >=
0)
1412 else if (TARGET_POWERPC)
1413 operands[
2] = force_reg (SImode, operands[
2]);
1414 else if (TARGET_POWER)
1418 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1419 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1420 emit_insn (gen_quoss_call ());
1421 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1426 (define_expand "modsi3"
1427 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
1428 (use (match_operand:SI
1 "gpc_reg_operand" ""))
1429 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
1433 int i = exact_log2 (INTVAL (operands[
2]));
1437 if (GET_CODE (operands[
2]) != CONST_INT || i <
0)
1440 temp1 = gen_reg_rtx (SImode);
1441 temp2 = gen_reg_rtx (SImode);
1443 emit_insn (gen_divsi3 (temp1, operands[
1], operands[
2]));
1444 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1445 emit_insn (gen_subsi3 (operands[
0], operands[
1], temp2));
1450 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1451 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1452 (match_operand:SI
2 "const_int_operand" "N")))]
1453 "exact_log2 (INTVAL (operands[
2])) >=
0"
1454 "{srai|srawi} %
0,%
1,%p2\;{aze|addze} %
0,%
0"
1455 [(set_attr "length" "
8")])
1458 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1459 (compare:CC (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1460 (match_operand:SI
2 "const_int_operand" "N"))
1462 (clobber (match_scratch:SI
3 "=r"))]
1463 "exact_log2 (INTVAL (operands[
2])) >=
0"
1464 "{srai|srawi} %
3,%
1,%p2\;{aze.|addze.} %
3,%
3"
1465 [(set_attr "type" "compare")
1466 (set_attr "length" "
8")])
1469 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1470 (compare:CC (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1471 (match_operand:SI
2 "const_int_operand" "N"))
1473 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1474 (div:SI (match_dup
1) (match_dup
2)))]
1475 "exact_log2 (INTVAL (operands[
2])) >=
0"
1476 "{srai|srawi} %
0,%
1,%p2\;{aze.|addze.} %
0,%
0"
1477 [(set_attr "type" "compare")
1478 (set_attr "length" "
8")])
1481 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1484 (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
1486 (zero_extend:DI (match_operand:SI
4 "register_operand" "
2")))
1487 (match_operand:SI
3 "gpc_reg_operand" "r")))
1488 (set (match_operand:SI
2 "register_operand" "=*q")
1491 (zero_extend:DI (match_dup
1)) (const_int
32))
1492 (zero_extend:DI (match_dup
4)))
1496 [(set_attr "type" "idiv")])
1498 ;; To do unsigned divide we handle the cases of the divisor looking like a
1499 ;; negative number. If it is a constant that is less than
2**
31, we don't
1500 ;; have to worry about the branches. So make a few subroutines here.
1502 ;; First comes the normal case.
1503 (define_expand "udivmodsi4_normal"
1504 [(set (match_dup
4) (const_int
0))
1505 (parallel [(set (match_operand:SI
0 "" "")
1506 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup
4))
1508 (zero_extend:DI (match_operand:SI
1 "" "")))
1509 (match_operand:SI
2 "" "")))
1510 (set (match_operand:SI
3 "" "")
1511 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup
4))
1513 (zero_extend:DI (match_dup
1)))
1517 { operands[
4] = gen_reg_rtx (SImode); }")
1519 ;; This handles the branches.
1520 (define_expand "udivmodsi4_tests"
1521 [(set (match_operand:SI
0 "" "") (const_int
0))
1522 (set (match_operand:SI
3 "" "") (match_operand:SI
1 "" ""))
1523 (set (match_dup
5) (compare:CCUNS (match_dup
1) (match_operand:SI
2 "" "")))
1524 (set (pc) (if_then_else (ltu (match_dup
5) (const_int
0))
1525 (label_ref (match_operand:SI
4 "" "")) (pc)))
1526 (set (match_dup
0) (const_int
1))
1527 (set (match_dup
3) (minus:SI (match_dup
1) (match_dup
2)))
1528 (set (match_dup
6) (compare:CC (match_dup
2) (const_int
0)))
1529 (set (pc) (if_then_else (lt (match_dup
6) (const_int
0))
1530 (label_ref (match_dup
4)) (pc)))]
1533 { operands[
5] = gen_reg_rtx (CCUNSmode);
1534 operands[
6] = gen_reg_rtx (CCmode);
1537 (define_expand "udivmodsi4"
1538 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
1539 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "")
1540 (match_operand:SI
2 "reg_or_cint_operand" "")))
1541 (set (match_operand:SI
3 "gpc_reg_operand" "")
1542 (umod:SI (match_dup
1) (match_dup
2)))])]
1549 if (! TARGET_POWERPC)
1551 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1552 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1553 emit_insn (gen_divus_call ());
1554 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1555 emit_move_insn (operands[
3], gen_rtx (REG, SImode,
4));
1561 if (GET_CODE (operands[
2]) != CONST_INT || INTVAL (operands[
2]) <
0)
1563 operands[
2] = force_reg (SImode, operands[
2]);
1564 label = gen_label_rtx ();
1565 emit (gen_udivmodsi4_tests (operands[
0], operands[
1], operands[
2],
1566 operands[
3], label));
1569 operands[
2] = force_reg (SImode, operands[
2]);
1571 emit (gen_udivmodsi4_normal (operands[
0], operands[
1], operands[
2],
1579 ;; AIX architecture-independent common-mode multiply (DImode),
1580 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1581 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
1582 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1583 ;; assumed unused if generating common-mode, so ignore.
1584 (define_insn "mulh_call"
1587 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI
3))
1588 (sign_extend:DI (reg:SI
4)))
1590 (clobber (match_scratch:SI
0 "=l"))]
1591 "! TARGET_POWER && ! TARGET_POWERPC"
1593 [(set_attr "type" "imul")])
1595 (define_insn "mull_call"
1597 (mult:DI (sign_extend:DI (reg:SI
3))
1598 (sign_extend:DI (reg:SI
4))))
1599 (clobber (match_scratch:SI
0 "=l"))
1600 (clobber (reg:SI
0))]
1601 "! TARGET_POWER && ! TARGET_POWERPC"
1603 [(set_attr "type" "imul")])
1605 (define_insn "divss_call"
1607 (div:SI (reg:SI
3) (reg:SI
4)))
1609 (mod:SI (reg:SI
3) (reg:SI
4)))
1610 (clobber (match_scratch:SI
0 "=l"))
1611 (clobber (reg:SI
0))]
1612 "! TARGET_POWER && ! TARGET_POWERPC"
1614 [(set_attr "type" "idiv")])
1616 (define_insn "divus_call"
1618 (udiv:SI (reg:SI
3) (reg:SI
4)))
1620 (umod:SI (reg:SI
3) (reg:SI
4)))
1621 (clobber (match_scratch:SI
0 "=l"))
1622 (clobber (reg:SI
0))
1623 (clobber (match_scratch:CC
1 "=x"))
1624 (clobber (reg:CC
69))]
1625 "! TARGET_POWER && ! TARGET_POWERPC"
1627 [(set_attr "type" "idiv")])
1629 (define_insn "quoss_call"
1631 (div:SI (reg:SI
3) (reg:SI
4)))
1632 (clobber (match_scratch:SI
0 "=l"))]
1633 "! TARGET_POWER && ! TARGET_POWERPC"
1635 [(set_attr "type" "idiv")])
1637 (define_insn "quous_call"
1639 (udiv:SI (reg:SI
3) (reg:SI
4)))
1640 (clobber (match_scratch:SI
0 "=l"))
1641 (clobber (reg:SI
0))
1642 (clobber (match_scratch:CC
1 "=x"))
1643 (clobber (reg:CC
69))]
1644 "! TARGET_POWER && ! TARGET_POWERPC"
1646 [(set_attr "type" "idiv")])
1648 (define_insn "andsi3"
1649 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
1650 (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
1651 (match_operand:SI
2 "and_operand" "?r,L,K,J")))
1652 (clobber (match_scratch:CC
3 "=X,X,x,x"))]
1656 {rlinm|rlwinm} %
0,%
1,
0,%m2,%M2
1657 {andil.|andi.} %
0,%
1,%b2
1658 {andiu.|andis.} %
0,%
1,%u2")
1661 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x,x")
1662 (compare:CC (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
1663 (match_operand:SI
2 "and_operand" "r,K,J,L"))
1665 (clobber (match_scratch:SI
3 "=r,r,r,r"))]
1669 {andil.|andi.} %
3,%
1,%b2
1670 {andiu.|andis.} %
3,%
1,%u2
1671 {rlinm.|rlwinm.} %
3,%
1,
0,%m2,%M2"
1672 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1675 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x,x,x")
1676 (compare:CC (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
1677 (match_operand:SI
2 "and_operand" "r,K,J,L"))
1679 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
1680 (and:SI (match_dup
1) (match_dup
2)))]
1684 {andil.|andi.} %
0,%
1,%b2
1685 {andiu.|andis.} %
0,%
1,%u2
1686 {rlinm.|rlwinm.} %
0,%
1,
0,%m2,%M2"
1687 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1689 ;; Take a AND with a constant that cannot be done in a single insn and try to
1690 ;; split it into two insns. This does not verify that the insns are valid
1691 ;; since this need not be done as combine will do it.
1694 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1695 (and:SI (match_operand:SI
1 "gpc_reg_operand" "")
1696 (match_operand:SI
2 "non_and_cint_operand" "")))]
1698 [(set (match_dup
0) (and:SI (match_dup
1) (match_dup
3)))
1699 (set (match_dup
0) (and:SI (match_dup
0) (match_dup
4)))]
1702 int maskval = INTVAL (operands[
2]);
1703 int i, transitions, last_bit_value;
1704 int orig = maskval, first_c = maskval, second_c;
1706 /* We know that MASKVAL must have more than
2 bit-transitions. Start at
1707 the low-order bit and count for the third transition. When we get there,
1708 make a first mask that has everything to the left of that position
1709 a one. Then make the second mask to turn off whatever else is needed. */
1711 for (i =
1, transitions =
0, last_bit_value = maskval &
1; i <
32; i++)
1713 if (((maskval >>=
1) &
1) != last_bit_value)
1714 last_bit_value ^=
1, transitions++;
1716 if (transitions >
2)
1718 first_c |= (~
0) << i;
1723 second_c = orig | ~ first_c;
1725 operands[
3] = gen_rtx (CONST_INT, VOIDmode, first_c);
1726 operands[
4] = gen_rtx (CONST_INT, VOIDmode, second_c);
1729 (define_insn "iorsi3"
1730 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
1731 (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r")
1732 (match_operand:SI
2 "logical_operand" "r,K,J")))]
1736 {oril|ori} %
0,%
1,%b2
1737 {oriu|oris} %
0,%
1,%u2")
1740 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1741 (compare:CC (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1742 (match_operand:SI
2 "gpc_reg_operand" "r"))
1744 (clobber (match_scratch:SI
3 "=r"))]
1747 [(set_attr "type" "compare")])
1750 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1751 (compare:CC (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1752 (match_operand:SI
2 "gpc_reg_operand" "r"))
1754 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1755 (ior:SI (match_dup
1) (match_dup
2)))]
1758 [(set_attr "type" "compare")])
1760 ;; Split an IOR that we can't do in one insn into two insns, each of which
1761 ;; does one
16-bit part. This is used by combine.
1764 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1765 (ior:SI (match_operand:SI
1 "gpc_reg_operand" "")
1766 (match_operand:SI
2 "non_logical_cint_operand" "")))]
1768 [(set (match_dup
0) (ior:SI (match_dup
1) (match_dup
3)))
1769 (set (match_dup
0) (ior:SI (match_dup
0) (match_dup
4)))]
1772 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
1773 INTVAL (operands[
2]) &
0xffff0000);
1774 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1777 (define_insn "xorsi3"
1778 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
1779 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r")
1780 (match_operand:SI
2 "logical_operand" "r,K,J")))]
1784 {xoril|xori} %
0,%
1,%b2
1785 {xoriu|xoris} %
0,%
1,%u2")
1788 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1789 (compare:CC (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1790 (match_operand:SI
2 "gpc_reg_operand" "r"))
1792 (clobber (match_scratch:SI
3 "=r"))]
1795 [(set_attr "type" "compare")])
1798 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1799 (compare:CC (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1800 (match_operand:SI
2 "gpc_reg_operand" "r"))
1802 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1803 (xor:SI (match_dup
1) (match_dup
2)))]
1806 [(set_attr "type" "compare")])
1808 ;; Split an XOR that we can't do in one insn into two insns, each of which
1809 ;; does one
16-bit part. This is used by combine.
1812 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1813 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1814 (match_operand:SI
2 "non_logical_cint_operand" "")))]
1816 [(set (match_dup
0) (xor:SI (match_dup
1) (match_dup
3)))
1817 (set (match_dup
0) (xor:SI (match_dup
0) (match_dup
4)))]
1820 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
1821 INTVAL (operands[
2]) &
0xffff0000);
1822 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1826 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1827 (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1828 (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1833 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1834 (compare:CC (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1835 (match_operand:SI
2 "gpc_reg_operand" "r")))
1837 (clobber (match_scratch:SI
3 "=r"))]
1840 [(set_attr "type" "compare")])
1843 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1844 (compare:CC (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1845 (match_operand:SI
2 "gpc_reg_operand" "r")))
1847 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1848 (not:SI (xor:SI (match_dup
1) (match_dup
2))))]
1851 [(set_attr "type" "compare")])
1854 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1855 (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1856 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1861 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1862 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1863 (match_operand:SI
2 "gpc_reg_operand" "r"))
1865 (clobber (match_scratch:SI
3 "=r"))]
1868 [(set_attr "type" "compare")])
1871 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1872 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1873 (match_operand:SI
2 "gpc_reg_operand" "r"))
1875 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1876 (and:SI (not:SI (match_dup
1)) (match_dup
2)))]
1879 [(set_attr "type" "compare")])
1882 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1883 (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1884 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1889 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1890 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1891 (match_operand:SI
2 "gpc_reg_operand" "r"))
1893 (clobber (match_scratch:SI
3 "=r"))]
1896 [(set_attr "type" "compare")])
1899 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1900 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1901 (match_operand:SI
2 "gpc_reg_operand" "r"))
1903 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1904 (ior:SI (not:SI (match_dup
1)) (match_dup
2)))]
1907 [(set_attr "type" "compare")])
1910 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1911 (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1912 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1917 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1918 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1919 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1921 (clobber (match_scratch:SI
3 "=r"))]
1924 [(set_attr "type" "compare")])
1927 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1928 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1929 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1931 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1932 (ior:SI (not:SI (match_dup
1)) (not:SI (match_dup
2))))]
1935 [(set_attr "type" "compare")])
1938 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1939 (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1940 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1945 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1946 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1947 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1949 (clobber (match_scratch:SI
3 "=r"))]
1952 [(set_attr "type" "compare")])
1955 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1956 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1957 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1959 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1960 (and:SI (not:SI (match_dup
1)) (not:SI (match_dup
2))))]
1963 [(set_attr "type" "compare")])
1965 ;; maskir insn. We need four forms because things might be in arbitrary
1966 ;; orders. Don't define forms that only set CR fields because these
1967 ;; would modify an input register.
1970 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1971 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1972 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1973 (and:SI (match_dup
2)
1974 (match_operand:SI
3 "gpc_reg_operand" "r"))))]
1979 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1980 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1981 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1982 (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1988 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1989 (ior:SI (and:SI (match_operand:SI
2 "gpc_reg_operand" "r")
1990 (match_operand:SI
3 "gpc_reg_operand" "r"))
1991 (and:SI (not:SI (match_dup
2))
1992 (match_operand:SI
1 "gpc_reg_operand" "
0"))))]
1997 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1998 (ior:SI (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1999 (match_operand:SI
2 "gpc_reg_operand" "r"))
2000 (and:SI (not:SI (match_dup
2))
2001 (match_operand:SI
1 "gpc_reg_operand" "
0"))))]
2006 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2008 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
2009 (match_operand:SI
1 "gpc_reg_operand" "
0"))
2010 (and:SI (match_dup
2)
2011 (match_operand:SI
3 "gpc_reg_operand" "r")))
2013 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2014 (ior:SI (and:SI (not:SI (match_dup
2)) (match_dup
1))
2015 (and:SI (match_dup
2) (match_dup
3))))]
2018 [(set_attr "type" "compare")])
2021 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2023 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
2024 (match_operand:SI
1 "gpc_reg_operand" "
0"))
2025 (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2028 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2029 (ior:SI (and:SI (not:SI (match_dup
2)) (match_dup
1))
2030 (and:SI (match_dup
3) (match_dup
2))))]
2033 [(set_attr "type" "compare")])
2036 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2038 (ior:SI (and:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2039 (match_operand:SI
3 "gpc_reg_operand" "r"))
2040 (and:SI (not:SI (match_dup
2))
2041 (match_operand:SI
1 "gpc_reg_operand" "
0")))
2043 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2044 (ior:SI (and:SI (match_dup
2) (match_dup
3))
2045 (and:SI (not:SI (match_dup
2)) (match_dup
1))))]
2048 [(set_attr "type" "compare")])
2051 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2053 (ior:SI (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2054 (match_operand:SI
2 "gpc_reg_operand" "r"))
2055 (and:SI (not:SI (match_dup
2))
2056 (match_operand:SI
1 "gpc_reg_operand" "
0")))
2058 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2059 (ior:SI (and:SI (match_dup
3) (match_dup
2))
2060 (and:SI (not:SI (match_dup
2)) (match_dup
1))))]
2063 [(set_attr "type" "compare")])
2065 ;; Rotate and shift insns, in all their variants. These support shifts,
2066 ;; field inserts and extracts, and various combinations thereof.
2067 (define_expand "insv"
2068 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2069 (match_operand:SI
1 "const_int_operand" "i")
2070 (match_operand:SI
2 "const_int_operand" "i"))
2071 (match_operand:SI
3 "gpc_reg_operand" "r"))]
2075 /* Do not handle
16/
8 bit structures that fit in HI/QI modes directly, since
2076 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2077 compiler if the address of the structure is taken later. */
2078 if (GET_CODE (operands[
0]) == SUBREG
2079 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[
0]))) < UNITS_PER_WORD))
2084 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2085 (match_operand:SI
1 "const_int_operand" "i")
2086 (match_operand:SI
2 "const_int_operand" "i"))
2087 (match_operand:SI
3 "gpc_reg_operand" "r"))]
2091 int start = INTVAL (operands[
2]) &
31;
2092 int size = INTVAL (operands[
1]) &
31;
2094 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - start - size);
2095 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2096 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2100 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2101 (match_operand:SI
1 "const_int_operand" "i")
2102 (match_operand:SI
2 "const_int_operand" "i"))
2103 (ashift:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2104 (match_operand:SI
4 "const_int_operand" "i")))]
2108 int shift = INTVAL (operands[
4]) &
31;
2109 int start = INTVAL (operands[
2]) &
31;
2110 int size = INTVAL (operands[
1]) &
31;
2112 operands[
4] = gen_rtx (CONST_INT, VOIDmode, shift - start - size);
2113 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2114 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2118 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2119 (match_operand:SI
1 "const_int_operand" "i")
2120 (match_operand:SI
2 "const_int_operand" "i"))
2121 (ashiftrt:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2122 (match_operand:SI
4 "const_int_operand" "i")))]
2126 int shift = INTVAL (operands[
4]) &
31;
2127 int start = INTVAL (operands[
2]) &
31;
2128 int size = INTVAL (operands[
1]) &
31;
2130 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - shift - start - size);
2131 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2132 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2136 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2137 (match_operand:SI
1 "const_int_operand" "i")
2138 (match_operand:SI
2 "const_int_operand" "i"))
2139 (lshiftrt:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2140 (match_operand:SI
4 "const_int_operand" "i")))]
2144 int shift = INTVAL (operands[
4]) &
31;
2145 int start = INTVAL (operands[
2]) &
31;
2146 int size = INTVAL (operands[
1]) &
31;
2148 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - shift - start - size);
2149 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2150 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2154 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2155 (match_operand:SI
1 "const_int_operand" "i")
2156 (match_operand:SI
2 "const_int_operand" "i"))
2157 (zero_extract:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2158 (match_operand:SI
4 "const_int_operand" "i")
2159 (match_operand:SI
5 "const_int_operand" "i")))]
2160 "INTVAL (operands[
4]) >= INTVAL (operands[
1])"
2163 int extract_start = INTVAL (operands[
5]) &
31;
2164 int extract_size = INTVAL (operands[
4]) &
31;
2165 int insert_start = INTVAL (operands[
2]) &
31;
2166 int insert_size = INTVAL (operands[
1]) &
31;
2168 /* Align extract field with insert field */
2169 operands[
5] = gen_rtx (CONST_INT, VOIDmode,
2170 extract_start + extract_size - insert_start - insert_size);
2171 operands[
1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size -
1);
2172 return
\"{rlimi|rlwimi} %
0,%
3,%h5,%h2,%h1
\";
2176 [(set (zero_extract:DI (match_operand:DI
0 "gpc_reg_operand" "+r")
2177 (match_operand:DI
1 "const_int_operand" "i")
2178 (match_operand:DI
2 "const_int_operand" "i"))
2179 (match_operand:DI
3 "gpc_reg_operand" "r"))]
2183 int start = INTVAL (operands[
2]) &
63;
2184 int size = INTVAL (operands[
1]) &
63;
2186 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - start - size);
2187 return
\"rldimi %
0,%
3,%H2,%H1
\";
2190 (define_expand "extzv"
2191 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2192 (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2193 (match_operand:SI
2 "const_int_operand" "i")
2194 (match_operand:SI
3 "const_int_operand" "i")))]
2198 /* Do not handle
16/
8 bit structures that fit in HI/QI modes directly, since
2199 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2200 compiler if the address of the structure is taken later. */
2201 if (GET_CODE (operands[
0]) == SUBREG
2202 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[
0]))) < UNITS_PER_WORD))
2207 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2208 (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2209 (match_operand:SI
2 "const_int_operand" "i")
2210 (match_operand:SI
3 "const_int_operand" "i")))]
2214 int start = INTVAL (operands[
3]) &
31;
2215 int size = INTVAL (operands[
2]) &
31;
2217 if (start + size >=
32)
2218 operands[
3] = const0_rtx;
2220 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2221 return
\"{rlinm|rlwinm} %
0,%
1,%
3,%s2,
31\";
2225 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2226 (compare:CC (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2227 (match_operand:SI
2 "const_int_operand" "i")
2228 (match_operand:SI
3 "const_int_operand" "i"))
2230 (clobber (match_scratch:SI
4 "=r"))]
2234 int start = INTVAL (operands[
3]) &
31;
2235 int size = INTVAL (operands[
2]) &
31;
2237 /* If the bitfield being tested fits in the upper or lower half of a
2238 word, it is possible to use andiu. or andil. to test it. This is
2239 useful because the condition register set-use delay is smaller for
2240 andi[ul]. than for rlinm. This doesn't work when the starting bit
2241 position is
0 because the LT and GT bits may be set wrong. */
2243 if ((start >
0 && start + size <=
16) || start >=
16)
2245 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
2246 ((
1 << (
16 - (start &
15)))
2247 - (
1 << (
16 - (start &
15) - size))));
2249 return
\"{andiu.|andis.} %
4,%
1,%
3\";
2251 return
\"{andil.|andi.} %
4,%
1,%
3\";
2254 if (start + size >=
32)
2255 operands[
3] = const0_rtx;
2257 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2258 return
\"{rlinm.|rlwinm.} %
4,%
1,%
3,%s2,
31\";
2260 [(set_attr "type" "compare")])
2263 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2264 (compare:CC (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2265 (match_operand:SI
2 "const_int_operand" "i")
2266 (match_operand:SI
3 "const_int_operand" "i"))
2268 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2269 (zero_extract:SI (match_dup
1) (match_dup
2) (match_dup
3)))]
2273 int start = INTVAL (operands[
3]) &
31;
2274 int size = INTVAL (operands[
2]) &
31;
2276 if (start >=
16 && start + size ==
32)
2278 operands[
3] = gen_rtx (CONST_INT, VOIDmode, (
1 << (
32 - start)) -
1);
2279 return
\"{andil.|andi.} %
0,%
1,%
3\";
2282 if (start + size >=
32)
2283 operands[
3] = const0_rtx;
2285 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2286 return
\"{rlinm.|rlwinm.} %
0,%
1,%
3,%s2,
31\";
2288 [(set_attr "type" "delayed_compare")])
2291 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2292 (zero_extract:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2293 (match_operand:DI
2 "const_int_operand" "i")
2294 (match_operand:DI
3 "const_int_operand" "i")))]
2298 int start = INTVAL (operands[
3]) &
63;
2299 int size = INTVAL (operands[
2]) &
63;
2301 if (start + size >=
64)
2302 operands[
3] = const0_rtx;
2304 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2305 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - size);
2306 return
\"rldicl %
0,%
1,%
3,%
2\";
2310 [(set (match_operand:CC
0 "gpc_reg_operand" "=x")
2311 (compare:CC (zero_extract:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2312 (match_operand:DI
2 "const_int_operand" "i")
2313 (match_operand:DI
3 "const_int_operand" "i"))
2315 (clobber (match_scratch:DI
4 "=r"))]
2319 int start = INTVAL (operands[
3]) &
63;
2320 int size = INTVAL (operands[
2]) &
63;
2322 if (start + size >=
64)
2323 operands[
3] = const0_rtx;
2325 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2326 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - size);
2327 return
\"rldicl. %
4,%
1,%
3,%
2\";
2331 [(set (match_operand:CC
4 "gpc_reg_operand" "=x")
2332 (compare:CC (zero_extract:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2333 (match_operand:DI
2 "const_int_operand" "i")
2334 (match_operand:DI
3 "const_int_operand" "i"))
2336 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
2337 (zero_extract:DI (match_dup
1) (match_dup
2) (match_dup
3)))]
2341 int start = INTVAL (operands[
3]) &
63;
2342 int size = INTVAL (operands[
2]) &
63;
2344 if (start + size >=
64)
2345 operands[
3] = const0_rtx;
2347 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2348 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - size);
2349 return
\"rldicl. %
0,%
1,%
3,%
2\";
2352 (define_insn "rotlsi3"
2353 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2354 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2355 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2357 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xffffffff")
2360 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2361 (compare:CC (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2362 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2364 (clobber (match_scratch:SI
3 "=r"))]
2366 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xffffffff"
2367 [(set_attr "type" "delayed_compare")])
2370 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2371 (compare:CC (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2372 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2374 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2375 (rotate:SI (match_dup
1) (match_dup
2)))]
2377 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xffffffff"
2378 [(set_attr "type" "delayed_compare")])
2381 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2382 (and:SI (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2383 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2384 (match_operand:SI
3 "mask_operand" "L")))]
2386 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,%m3,%M3")
2389 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2391 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2392 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2393 (match_operand:SI
3 "mask_operand" "L"))
2395 (clobber (match_scratch:SI
4 "=r"))]
2397 "{rl%I2nm.|rlw%I2nm.} %
4,%
1,%h2,%m3,%M3"
2398 [(set_attr "type" "delayed_compare")])
2401 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2403 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2404 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2405 (match_operand:SI
3 "mask_operand" "L"))
2407 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2408 (and:SI (rotate:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
2410 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,%m3,%M3"
2411 [(set_attr "type" "delayed_compare")])
2414 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2417 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2418 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0)))]
2420 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xff")
2423 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2424 (compare:CC (zero_extend:SI
2426 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2427 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2429 (clobber (match_scratch:SI
3 "=r"))]
2431 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xff"
2432 [(set_attr "type" "delayed_compare")])
2435 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2436 (compare:CC (zero_extend:SI
2438 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2439 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2441 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2442 (zero_extend:SI (subreg:QI (rotate:SI (match_dup
1) (match_dup
2))
0)))]
2444 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xff"
2445 [(set_attr "type" "delayed_compare")])
2448 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2451 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2452 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0)))]
2454 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xffff")
2457 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2458 (compare:CC (zero_extend:SI
2460 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2461 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2463 (clobber (match_scratch:SI
3 "=r"))]
2465 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xffff"
2466 [(set_attr "type" "delayed_compare")])
2469 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2470 (compare:CC (zero_extend:SI
2472 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2473 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2475 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2476 (zero_extend:SI (subreg:HI (rotate:SI (match_dup
1) (match_dup
2))
0)))]
2478 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xffff"
2479 [(set_attr "type" "delayed_compare")])
2481 ;; Note that we use "sle." instead of "sl." so that we can set
2482 ;; SHIFT_COUNT_TRUNCATED.
2484 (define_expand "ashlsi3"
2485 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
2486 (use (match_operand:SI
1 "gpc_reg_operand" ""))
2487 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
2492 emit_insn (gen_ashlsi3_power (operands[
0], operands[
1], operands[
2]));
2494 emit_insn (gen_ashlsi3_no_power (operands[
0], operands[
1], operands[
2]));
2498 (define_insn "ashlsi3_power"
2499 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2500 (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2501 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
2502 (clobber (match_scratch:SI
3 "=q,X"))]
2506 {sli|slwi} %
0,%
1,%h2"
2507 [(set_attr "length" "
8")])
2509 (define_insn "ashlsi3_no_power"
2510 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2511 (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2512 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2514 "{sl|slw}%I2 %
0,%
1,%h2"
2515 [(set_attr "length" "
8")])
2518 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
2519 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2520 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2522 (clobber (match_scratch:SI
3 "=r,r"))
2523 (clobber (match_scratch:SI
4 "=q,X"))]
2527 {sli.|slwi.} %
3,%
1,%h2"
2528 [(set_attr "type" "delayed_compare")])
2531 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2532 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2533 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2535 (clobber (match_scratch:SI
3 "=r"))]
2537 "{sl|slw}%I2. %
3,%
1,%h2"
2538 [(set_attr "type" "delayed_compare")])
2541 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
2542 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2543 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2545 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2546 (ashift:SI (match_dup
1) (match_dup
2)))
2547 (clobber (match_scratch:SI
4 "=q,X"))]
2551 {sli.|slwi.} %
0,%
1,%h2"
2552 [(set_attr "type" "delayed_compare")])
2555 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2556 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2557 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2559 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2560 (ashift:SI (match_dup
1) (match_dup
2)))]
2562 "{sl|slw}%I2. %
0,%
1,%h2"
2563 [(set_attr "type" "delayed_compare")])
2566 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2567 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2568 (match_operand:SI
2 "const_int_operand" "i"))
2569 (match_operand:SI
3 "mask_operand" "L")))]
2570 "includes_lshift_p (operands[
2], operands[
3])"
2571 "{rlinm|rlwinm} %
0,%
1,%h2,%m3,%M3")
2574 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2576 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2577 (match_operand:SI
2 "const_int_operand" "i"))
2578 (match_operand:SI
3 "mask_operand" "L"))
2580 (clobber (match_scratch:SI
4 "=r"))]
2581 "includes_lshift_p (operands[
2], operands[
3])"
2582 "{rlinm.|rlwinm.} %
4,%
1,%h2,%m3,%M3"
2583 [(set_attr "type" "delayed_compare")])
2586 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2588 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2589 (match_operand:SI
2 "const_int_operand" "i"))
2590 (match_operand:SI
3 "mask_operand" "L"))
2592 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2593 (and:SI (ashift:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
2594 "includes_lshift_p (operands[
2], operands[
3])"
2595 "{rlinm.|rlwinm.} %
0,%
1,%h2,%m3,%M3"
2596 [(set_attr "type" "delayed_compare")])
2598 ;; The AIX assembler mis-handles "sri x,x,
0", so write that case as
2600 (define_expand "lshrsi3"
2601 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
2602 (use (match_operand:SI
1 "gpc_reg_operand" ""))
2603 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
2608 emit_insn (gen_lshrsi3_power (operands[
0], operands[
1], operands[
2]));
2610 emit_insn (gen_lshrsi3_no_power (operands[
0], operands[
1], operands[
2]));
2614 (define_insn "lshrsi3_power"
2615 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
2616 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
2617 (match_operand:SI
2 "reg_or_cint_operand" "r,O,i")))
2618 (clobber (match_scratch:SI
3 "=q,X,X"))]
2623 {s%A2i|s%A2wi} %
0,%
1,%h2")
2625 (define_insn "lshrsi3_no_power"
2626 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2627 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2628 (match_operand:SI
2 "reg_or_cint_operand" "O,ri")))]
2632 {sr|srw}%I2 %
0,%
1,%h2")
2635 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x")
2636 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
2637 (match_operand:SI
2 "reg_or_cint_operand" "r,O,i"))
2639 (clobber (match_scratch:SI
3 "=r,X,r"))
2640 (clobber (match_scratch:SI
4 "=q,X,X"))]
2645 {s%A2i.|s%A2wi.} %
3,%
1,%h2"
2646 [(set_attr "type" "delayed_compare")])
2649 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
2650 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2651 (match_operand:SI
2 "reg_or_cint_operand" "O,ri"))
2653 (clobber (match_scratch:SI
3 "=X,r"))]
2657 {sr|srw}%I2. %
3,%
1,%h2"
2658 [(set_attr "type" "delayed_compare")])
2661 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x,x")
2662 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
2663 (match_operand:SI
2 "reg_or_cint_operand" "r,O,i"))
2665 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
2666 (lshiftrt:SI (match_dup
1) (match_dup
2)))
2667 (clobber (match_scratch:SI
4 "=q,X,X"))]
2672 {s%A2i.|s%A2wi.} %
0,%
1,%h2"
2673 [(set_attr "type" "delayed_compare")])
2676 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
2677 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2678 (match_operand:SI
2 "reg_or_cint_operand" "O,ri"))
2680 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2681 (lshiftrt:SI (match_dup
1) (match_dup
2)))]
2685 {sr|srw}%I2. %
0,%
1,%h2"
2686 [(set_attr "type" "delayed_compare")])
2689 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2690 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2691 (match_operand:SI
2 "const_int_operand" "i"))
2692 (match_operand:SI
3 "mask_operand" "L")))]
2693 "includes_rshift_p (operands[
2], operands[
3])"
2694 "{rlinm|rlwinm} %
0,%
1,%s2,%m3,%M3")
2697 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2699 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2700 (match_operand:SI
2 "const_int_operand" "i"))
2701 (match_operand:SI
3 "mask_operand" "L"))
2703 (clobber (match_scratch:SI
4 "=r"))]
2704 "includes_rshift_p (operands[
2], operands[
3])"
2705 "{rlinm.|rlwinm.} %
4,%
1,%s2,%m3,%M3"
2706 [(set_attr "type" "delayed_compare")])
2709 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2711 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2712 (match_operand:SI
2 "const_int_operand" "i"))
2713 (match_operand:SI
3 "mask_operand" "L"))
2715 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2716 (and:SI (lshiftrt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
2717 "includes_rshift_p (operands[
2], operands[
3])"
2718 "{rlinm.|rlwinm.} %
0,%
1,%s2,%m3,%M3"
2719 [(set_attr "type" "delayed_compare")])
2722 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2725 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2726 (match_operand:SI
2 "const_int_operand" "i"))
0)))]
2727 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
2728 "{rlinm|rlwinm} %
0,%
1,%s2,
0xff")
2731 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2735 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2736 (match_operand:SI
2 "const_int_operand" "i"))
0))
2738 (clobber (match_scratch:SI
3 "=r"))]
2739 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
2740 "{rlinm.|rlwinm.} %
3,%
1,%s2,
0xff"
2741 [(set_attr "type" "delayed_compare")])
2744 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2748 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2749 (match_operand:SI
2 "const_int_operand" "i"))
0))
2751 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2752 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup
1) (match_dup
2))
0)))]
2753 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
2754 "{rlinm.|rlwinm.} %
0,%
1,%s2,
0xff"
2755 [(set_attr "type" "delayed_compare")])
2758 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2761 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2762 (match_operand:SI
2 "const_int_operand" "i"))
0)))]
2763 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
2764 "{rlinm|rlwinm} %
0,%
1,%s2,
0xffff")
2767 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2771 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2772 (match_operand:SI
2 "const_int_operand" "i"))
0))
2774 (clobber (match_scratch:SI
3 "=r"))]
2775 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
2776 "{rlinm.|rlwinm.} %
3,%
1,%s2,
0xffff"
2777 [(set_attr "type" "delayed_compare")])
2780 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2784 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2785 (match_operand:SI
2 "const_int_operand" "i"))
0))
2787 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2788 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup
1) (match_dup
2))
0)))]
2789 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
2790 "{rlinm.|rlwinm.} %
0,%
1,%s2,
0xffff"
2791 [(set_attr "type" "delayed_compare")])
2794 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2796 (match_operand:SI
1 "gpc_reg_operand" "r"))
2797 (ashiftrt:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2803 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2805 (match_operand:SI
1 "gpc_reg_operand" "r"))
2806 (lshiftrt:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2812 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2814 (match_operand:SI
1 "gpc_reg_operand" "r"))
2815 (zero_extract:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2821 (define_expand "ashrsi3"
2822 [(set (match_operand:SI
0 "gpc_reg_operand" "")
2823 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "")
2824 (match_operand:SI
2 "reg_or_cint_operand" "")))]
2829 emit_insn (gen_ashrsi3_power (operands[
0], operands[
1], operands[
2]));
2831 emit_insn (gen_ashrsi3_no_power (operands[
0], operands[
1], operands[
2]));
2835 (define_insn "ashrsi3_power"
2836 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2837 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2838 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
2839 (clobber (match_scratch:SI
3 "=q,X"))]
2843 {srai|srawi} %
0,%
1,%h2")
2845 (define_insn "ashrsi3_no_power"
2846 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2847 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2848 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2850 "{sra|sraw}%I2 %
0,%
1,%h2")
2853 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
2854 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2855 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2857 (clobber (match_scratch:SI
3 "=r,r"))
2858 (clobber (match_scratch:SI
4 "=q,X"))]
2862 {srai.|srawi.} %
3,%
1,%h2"
2863 [(set_attr "type" "delayed_compare")])
2866 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2867 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2868 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2870 (clobber (match_scratch:SI
3 "=r"))]
2872 "{sra|sraw}%I2. %
3,%
1,%h2"
2873 [(set_attr "type" "delayed_compare")])
2876 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
2877 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2878 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2880 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2881 (ashiftrt:SI (match_dup
1) (match_dup
2)))
2882 (clobber (match_scratch:SI
4 "=q,X"))]
2886 {srai.|srawi.} %
0,%
1,%h2"
2887 [(set_attr "type" "delayed_compare")])
2890 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2891 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2892 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2894 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2895 (ashiftrt:SI (match_dup
1) (match_dup
2)))]
2897 "{sra|sraw}%I2. %
0,%
1,%h2"
2898 [(set_attr "type" "delayed_compare")])
2900 ;; Floating-point insns, excluding normal data motion.
2902 ;; PowerPC has a full set of single-precision floating point instructions.
2904 ;; For the POWER architecture, we pretend that we have both SFmode and
2905 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2906 ;; The only conversions we will do will be when storing to memory. In that
2907 ;; case, we will use the "frsp" instruction before storing.
2909 ;; Note that when we store into a single-precision memory location, we need to
2910 ;; use the frsp insn first. If the register being stored isn't dead, we
2911 ;; need a scratch register for the frsp. But this is difficult when the store
2912 ;; is done by reload. It is not incorrect to do the frsp on the register in
2913 ;; this case, we just lose precision that we would have otherwise gotten but
2914 ;; is not guaranteed. Perhaps this should be tightened up at some point.
2916 (define_insn "extendsfdf2"
2917 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2918 (float_extend:DF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2922 if (REGNO (operands[
0]) == REGNO (operands[
1]))
2925 return
\"fmr %
0,%
1\";
2927 [(set_attr "type" "fp")])
2929 (define_insn "truncdfsf2"
2930 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2931 (float_truncate:SF (match_operand:DF
1 "gpc_reg_operand" "f")))]
2934 [(set_attr "type" "fp")])
2936 (define_insn "aux_truncdfsf2"
2937 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2938 (unspec:SF [(match_operand:SF
1 "gpc_reg_operand" "f")]
0))]
2939 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2941 [(set_attr "type" "fp")])
2943 (define_insn "negsf2"
2944 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2945 (neg:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2948 [(set_attr "type" "fp")])
2950 (define_insn "abssf2"
2951 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2952 (abs:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2955 [(set_attr "type" "fp")])
2958 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2959 (neg:SF (abs:SF (match_operand:SF
1 "gpc_reg_operand" "f"))))]
2962 [(set_attr "type" "fp")])
2964 (define_expand "addsf3"
2965 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2966 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "")
2967 (match_operand:SF
2 "gpc_reg_operand" "")))]
2972 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2973 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2974 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2975 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2977 [(set_attr "type" "fp")])
2980 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2981 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2982 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2983 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2984 "{fa|fadd} %
0,%
1,%
2"
2985 [(set_attr "type" "fp")])
2987 (define_expand "subsf3"
2988 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2989 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "")
2990 (match_operand:SF
2 "gpc_reg_operand" "")))]
2995 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2996 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "f")
2997 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2998 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3000 [(set_attr "type" "fp")])
3003 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3004 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "f")
3005 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3006 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3007 "{fs|fsub} %
0,%
1,%
2"
3008 [(set_attr "type" "fp")])
3010 (define_expand "mulsf3"
3011 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3012 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "")
3013 (match_operand:SF
2 "gpc_reg_operand" "")))]
3018 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3019 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3020 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3021 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3023 [(set_attr "type" "fp")])
3026 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3027 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3028 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3029 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3030 "{fm|fmul} %
0,%
1,%
2"
3031 [(set_attr "type" "dmul")])
3033 (define_expand "divsf3"
3034 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3035 (div:SF (match_operand:SF
1 "gpc_reg_operand" "")
3036 (match_operand:SF
2 "gpc_reg_operand" "")))]
3041 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3042 (div:SF (match_operand:SF
1 "gpc_reg_operand" "f")
3043 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3044 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3046 [(set_attr "type" "sdiv")])
3049 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3050 (div:SF (match_operand:SF
1 "gpc_reg_operand" "f")
3051 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3052 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3053 "{fd|fdiv} %
0,%
1,%
2"
3054 [(set_attr "type" "ddiv")])
3057 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3058 (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3059 (match_operand:SF
2 "gpc_reg_operand" "f"))
3060 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3061 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3062 "fmadds %
0,%
1,%
2,%
3"
3063 [(set_attr "type" "fp")])
3066 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3067 (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3068 (match_operand:SF
2 "gpc_reg_operand" "f"))
3069 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3070 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3071 "{fma|fmadd} %
0,%
1,%
2,%
3"
3072 [(set_attr "type" "dmul")])
3075 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3076 (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3077 (match_operand:SF
2 "gpc_reg_operand" "f"))
3078 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3079 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3080 "fmsubs %
0,%
1,%
2,%
3"
3081 [(set_attr "type" "fp")])
3084 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3085 (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3086 (match_operand:SF
2 "gpc_reg_operand" "f"))
3087 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3088 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3089 "{fms|fmsub} %
0,%
1,%
2,%
3"
3090 [(set_attr "type" "dmul")])
3093 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3094 (neg:SF (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3095 (match_operand:SF
2 "gpc_reg_operand" "f"))
3096 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3097 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3098 "fnmadds %
0,%
1,%
2,%
3"
3099 [(set_attr "type" "fp")])
3102 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3103 (neg:SF (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3104 (match_operand:SF
2 "gpc_reg_operand" "f"))
3105 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3106 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3107 "{fnma|fnmadd} %
0,%
1,%
2,%
3"
3108 [(set_attr "type" "dmul")])
3111 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3112 (neg:SF (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3113 (match_operand:SF
2 "gpc_reg_operand" "f"))
3114 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3115 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3116 "fnmsubs %
0,%
1,%
2,%
3"
3117 [(set_attr "type" "fp")])
3120 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3121 (neg:SF (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3122 (match_operand:SF
2 "gpc_reg_operand" "f"))
3123 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3124 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3125 "{fnms|fnmsub} %
0,%
1,%
2,%
3"
3126 [(set_attr "type" "dmul")])
3128 (define_expand "sqrtsf2"
3129 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3130 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "")))]
3131 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3135 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3136 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
3137 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
3139 [(set_attr "type" "ssqrt")])
3142 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3143 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
3144 "TARGET_POWER2 && TARGET_HARD_FLOAT"
3146 [(set_attr "type" "dsqrt")])
3148 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3149 ;; fsel instruction and some auxiliary computations. Then we just have a
3150 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3152 (define_expand "maxsf3"
3154 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "")
3155 (match_operand:SF
2 "gpc_reg_operand" "")))
3156 (set (match_operand:SF
0 "gpc_reg_operand" "")
3157 (if_then_else:SF (ge (match_dup
3)
3161 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3163 { operands[
3] = gen_reg_rtx (SFmode); }")
3166 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3167 (smax:SF (match_operand:SF
1 "gpc_reg_operand" "")
3168 (match_operand:SF
2 "gpc_reg_operand" "")))
3169 (clobber (match_operand:SF
3 "gpc_reg_operand" ""))]
3170 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3172 (minus:SF (match_dup
1) (match_dup
2)))
3174 (if_then_else:SF (ge (match_dup
3)
3180 (define_expand "minsf3"
3182 (minus:SF (match_operand:SF
2 "gpc_reg_operand" "")
3183 (match_operand:SF
1 "gpc_reg_operand" "")))
3184 (set (match_operand:SF
0 "gpc_reg_operand" "")
3185 (if_then_else:SF (ge (match_dup
3)
3189 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3191 { operands[
3] = gen_reg_rtx (SFmode); }")
3194 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3195 (smin:SF (match_operand:SF
1 "gpc_reg_operand" "")
3196 (match_operand:SF
2 "gpc_reg_operand" "")))
3197 (clobber (match_operand:SF
3 "gpc_reg_operand" ""))]
3198 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3200 (minus:SF (match_dup
2) (match_dup
1)))
3202 (if_then_else:SF (ge (match_dup
3)
3208 (define_expand "movsfcc"
3209 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3210 (if_then_else:SF (match_operand
1 "comparison_operator" "")
3211 (match_operand:SF
2 "gpc_reg_operand" "f")
3212 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3213 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3217 enum rtx_code code = GET_CODE (operands[
1]);
3218 if (! rs6000_compare_fp_p)
3222 case GE: case EQ: case NE:
3223 op0 = rs6000_compare_op0;
3224 op1 = rs6000_compare_op1;
3227 op0 = rs6000_compare_op1;
3228 op1 = rs6000_compare_op0;
3229 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3232 op0 = rs6000_compare_op1;
3233 op1 = rs6000_compare_op0;
3236 op0 = rs6000_compare_op0;
3237 op1 = rs6000_compare_op1;
3238 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3243 if (GET_MODE (rs6000_compare_op0) == DFmode)
3245 temp = gen_reg_rtx (DFmode);
3246 emit_insn (gen_subdf3 (temp, op0, op1));
3247 emit_insn (gen_fseldfsf4 (operands[
0], temp, operands[
2], operands[
3]));
3250 emit_insn (gen_negdf2 (temp, temp));
3251 emit_insn (gen_fseldfsf4 (operands[
0], temp, operands[
0], operands[
3]));
3255 emit_insn (gen_negdf2 (temp, temp));
3256 emit_insn (gen_fseldfsf4 (operands[
0], temp, operands[
3], operands[
0]));
3261 temp = gen_reg_rtx (SFmode);
3262 emit_insn (gen_subsf3 (temp, op0, op1));
3263 emit_insn (gen_fselsfsf4 (operands[
0], temp, operands[
2], operands[
3]));
3266 emit_insn (gen_negsf2 (temp, temp));
3267 emit_insn (gen_fselsfsf4 (operands[
0], temp, operands[
0], operands[
3]));
3271 emit_insn (gen_negsf2 (temp, temp));
3272 emit_insn (gen_fselsfsf4 (operands[
0], temp, operands[
3], operands[
0]));
3278 (define_insn "fselsfsf4"
3279 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3280 (if_then_else:SF (ge (match_operand:SF
1 "gpc_reg_operand" "f")
3282 (match_operand:SF
2 "gpc_reg_operand" "f")
3283 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3284 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3286 [(set_attr "type" "fp")])
3288 (define_insn "fseldfsf4"
3289 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3290 (if_then_else:SF (ge (match_operand:DF
1 "gpc_reg_operand" "f")
3292 (match_operand:SF
2 "gpc_reg_operand" "f")
3293 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3294 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3296 [(set_attr "type" "fp")])
3298 (define_insn "negdf2"
3299 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3300 (neg:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
3303 [(set_attr "type" "fp")])
3305 (define_insn "absdf2"
3306 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3307 (abs:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
3310 [(set_attr "type" "fp")])
3313 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3314 (neg:DF (abs:DF (match_operand:DF
1 "gpc_reg_operand" "f"))))]
3317 [(set_attr "type" "fp")])
3319 (define_insn "adddf3"
3320 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3321 (plus:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3322 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3324 "{fa|fadd} %
0,%
1,%
2"
3325 [(set_attr "type" "fp")])
3327 (define_insn "subdf3"
3328 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3329 (minus:DF (match_operand:DF
1 "gpc_reg_operand" "f")
3330 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3332 "{fs|fsub} %
0,%
1,%
2"
3333 [(set_attr "type" "fp")])
3335 (define_insn "muldf3"
3336 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3337 (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3338 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3340 "{fm|fmul} %
0,%
1,%
2"
3341 [(set_attr "type" "dmul")])
3343 (define_insn "divdf3"
3344 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3345 (div:DF (match_operand:DF
1 "gpc_reg_operand" "f")
3346 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3348 "{fd|fdiv} %
0,%
1,%
2"
3349 [(set_attr "type" "ddiv")])
3352 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3353 (plus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3354 (match_operand:DF
2 "gpc_reg_operand" "f"))
3355 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3357 "{fma|fmadd} %
0,%
1,%
2,%
3"
3358 [(set_attr "type" "dmul")])
3361 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3362 (minus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3363 (match_operand:DF
2 "gpc_reg_operand" "f"))
3364 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3366 "{fms|fmsub} %
0,%
1,%
2,%
3"
3367 [(set_attr "type" "dmul")])
3370 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3371 (neg:DF (plus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3372 (match_operand:DF
2 "gpc_reg_operand" "f"))
3373 (match_operand:DF
3 "gpc_reg_operand" "f"))))]
3375 "{fnma|fnmadd} %
0,%
1,%
2,%
3"
3376 [(set_attr "type" "dmul")])
3379 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3380 (neg:DF (minus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3381 (match_operand:DF
2 "gpc_reg_operand" "f"))
3382 (match_operand:DF
3 "gpc_reg_operand" "f"))))]
3384 "{fnms|fnmsub} %
0,%
1,%
2,%
3"
3385 [(set_attr "type" "dmul")])
3387 (define_insn "sqrtdf2"
3388 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3389 (sqrt:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
3390 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3392 [(set_attr "type" "dsqrt")])
3394 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3395 ;; fsel instruction and some auxiliary computations. Then we just have a
3396 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3399 (define_expand "maxdf3"
3401 (minus:DF (match_operand:DF
1 "gpc_reg_operand" "")
3402 (match_operand:DF
2 "gpc_reg_operand" "")))
3403 (set (match_operand:DF
0 "gpc_reg_operand" "")
3404 (if_then_else:DF (ge (match_dup
3)
3408 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3410 { operands[
3] = gen_reg_rtx (DFmode); }")
3413 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3414 (smax:DF (match_operand:DF
1 "gpc_reg_operand" "")
3415 (match_operand:DF
2 "gpc_reg_operand" "")))
3416 (clobber (match_operand:DF
3 "gpc_reg_operand" ""))]
3417 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3419 (minus:DF (match_dup
1) (match_dup
2)))
3421 (if_then_else:DF (ge (match_dup
3)
3427 (define_expand "mindf3"
3429 (minus:DF (match_operand:DF
2 "gpc_reg_operand" "")
3430 (match_operand:DF
1 "gpc_reg_operand" "")))
3431 (set (match_operand:DF
0 "gpc_reg_operand" "")
3432 (if_then_else:DF (ge (match_dup
3)
3436 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3438 { operands[
3] = gen_reg_rtx (DFmode); }")
3441 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3442 (smin:DF (match_operand:DF
1 "gpc_reg_operand" "")
3443 (match_operand:DF
2 "gpc_reg_operand" "")))
3444 (clobber (match_operand:DF
3 "gpc_reg_operand" ""))]
3445 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3447 (minus:DF (match_dup
2) (match_dup
1)))
3449 (if_then_else:DF (ge (match_dup
3)
3455 (define_expand "movdfcc"
3456 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3457 (if_then_else:DF (match_operand
1 "comparison_operator" "")
3458 (match_operand:DF
2 "gpc_reg_operand" "f")
3459 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3460 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3464 enum rtx_code code = GET_CODE (operands[
1]);
3465 if (! rs6000_compare_fp_p)
3469 case GE: case EQ: case NE:
3470 op0 = rs6000_compare_op0;
3471 op1 = rs6000_compare_op1;
3474 op0 = rs6000_compare_op1;
3475 op1 = rs6000_compare_op0;
3476 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3479 op0 = rs6000_compare_op1;
3480 op1 = rs6000_compare_op0;
3483 op0 = rs6000_compare_op0;
3484 op1 = rs6000_compare_op1;
3485 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3490 if (GET_MODE (rs6000_compare_op0) == DFmode)
3492 temp = gen_reg_rtx (DFmode);
3493 emit_insn (gen_subdf3 (temp, op0, op1));
3494 emit_insn (gen_fseldfdf4 (operands[
0], temp, operands[
2], operands[
3]));
3497 emit_insn (gen_negdf2 (temp, temp));
3498 emit_insn (gen_fseldfdf4 (operands[
0], temp, operands[
0], operands[
3]));
3502 emit_insn (gen_negdf2 (temp, temp));
3503 emit_insn (gen_fseldfdf4 (operands[
0], temp, operands[
3], operands[
0]));
3508 temp = gen_reg_rtx (SFmode);
3509 emit_insn (gen_subsf3 (temp, op0, op1));
3510 emit_insn (gen_fselsfdf4 (operands[
0], temp, operands[
2], operands[
3]));
3513 emit_insn (gen_negsf2 (temp, temp));
3514 emit_insn (gen_fselsfdf4 (operands[
0], temp, operands[
0], operands[
3]));
3518 emit_insn (gen_negsf2 (temp, temp));
3519 emit_insn (gen_fselsfdf4 (operands[
0], temp, operands[
3], operands[
0]));
3525 (define_insn "fseldfdf4"
3526 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3527 (if_then_else:DF (ge (match_operand:DF
1 "gpc_reg_operand" "f")
3529 (match_operand:DF
2 "gpc_reg_operand" "f")
3530 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3531 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3533 [(set_attr "type" "fp")])
3535 (define_insn "fselsfdf4"
3536 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3537 (if_then_else:DF (ge (match_operand:SF
1 "gpc_reg_operand" "f")
3539 (match_operand:DF
2 "gpc_reg_operand" "f")
3540 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3543 [(set_attr "type" "fp")])
3545 ;; Conversions to and from floating-point.
3547 (define_expand "floatsidf2"
3548 [(parallel [(set (match_operand:DF
0 "gpc_reg_operand" "")
3549 (float:DF (match_operand:SI
1 "gpc_reg_operand" "")))
3552 (clobber (match_dup
4))
3553 (clobber (reg:DF
76))])]
3554 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3557 operands[
2] = force_reg (SImode, GEN_INT (
0x43300000));
3558 operands[
3] = force_reg (DFmode, rs6000_float_const (
\"4503601774854144\", DFmode));
3559 operands[
4] = gen_reg_rtx (SImode);
3562 (define_insn "*floatsidf2_internal"
3563 [(set (match_operand:DF
0 "gpc_reg_operand" "=&f")
3564 (float:DF (match_operand:SI
1 "gpc_reg_operand" "r")))
3565 (use (match_operand:SI
2 "gpc_reg_operand" "r"))
3566 (use (match_operand:DF
3 "gpc_reg_operand" "f"))
3567 (clobber (match_operand:SI
4 "gpc_reg_operand" "=r"))
3568 (clobber (reg:DF
76))]
3569 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3571 [(set_attr "length" "
20")])
3574 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3575 (float:DF (match_operand:SI
1 "gpc_reg_operand" "")))
3576 (use (match_operand:SI
2 "gpc_reg_operand" ""))
3577 (use (match_operand:DF
3 "gpc_reg_operand" ""))
3578 (clobber (match_operand:SI
4 "gpc_reg_operand" ""))
3579 (clobber (reg:DF
76))]
3580 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3582 (xor:SI (match_dup
1)
3585 (unspec [(match_dup
4) ;; low word
3588 (unspec [(match_dup
2) ;; high word
3592 (unspec [(match_dup
6)
3595 (minus:DF (match_dup
0)
3599 operands[
5] = GEN_INT (
0x80000000);
3600 operands[
6] = gen_rtx (REG, DFmode, FPMEM_REGNUM);
3603 (define_expand "floatunssidf2"
3604 [(parallel [(set (match_operand:DF
0 "gpc_reg_operand" "")
3605 (unsigned_float:DF (match_operand:SI
1 "gpc_reg_operand" "")))
3608 (clobber (reg:DF
76))])]
3609 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3612 operands[
2] = force_reg (SImode, GEN_INT (
0x43300000));
3613 operands[
3] = force_reg (DFmode, rs6000_float_const (
\"4503599627370496\", DFmode));
3616 (define_insn "*floatunssidf2_internal"
3617 [(set (match_operand:DF
0 "gpc_reg_operand" "=&f")
3618 (unsigned_float:DF (match_operand:SI
1 "gpc_reg_operand" "r")))
3619 (use (match_operand:SI
2 "gpc_reg_operand" "r"))
3620 (use (match_operand:DF
3 "gpc_reg_operand" "f"))
3621 (clobber (reg:DF
76))]
3622 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3624 [(set_attr "length" "
16")])
3627 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3628 (unsigned_float:DF (match_operand:SI
1 "gpc_reg_operand" "")))
3629 (use (match_operand:SI
2 "gpc_reg_operand" ""))
3630 (use (match_operand:DF
3 "gpc_reg_operand" ""))
3631 (clobber (reg:DF
76))]
3632 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3634 (unspec [(match_dup
1) ;; low word
3637 (unspec [(match_dup
2) ;; high word
3641 (unspec [(match_dup
4)
3644 (minus:DF (match_dup
0)
3646 "operands[
4] = gen_rtx (REG, DFmode, FPMEM_REGNUM);")
3648 ;; Note, we list r1 in the unspec, so that the optimizer is not tempted to optimize
3649 ;; around an alloca call (the memory address is constructed directly from r1).
3651 (define_insn "*floatsidf2_store1"
3653 (unspec [(match_operand:SI
0 "gpc_reg_operand" "r")
3655 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3658 operands[
1] = gen_rtx (MEM, SImode,
3659 gen_rtx (PLUS, Pmode,
3661 GEN_INT (rs6000_fpmem_offset
3662 + ((WORDS_BIG_ENDIAN !=
0) *
4))));
3664 return
\"{st|stw} %
0,%
1\";
3666 [(set_attr "type" "store")])
3668 (define_insn "*floatsidf2_store2"
3670 (unspec [(match_operand:SI
0 "gpc_reg_operand" "r")
3673 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3676 operands[
1] = gen_rtx (MEM, SImode,
3677 gen_rtx (PLUS, Pmode,
3679 GEN_INT (rs6000_fpmem_offset
3680 + ((WORDS_BIG_ENDIAN ==
0) *
4))));
3682 return
\"{st|stw} %
0,%
1\";
3684 [(set_attr "type" "store")])
3686 (define_insn "*floatsidf2_load"
3687 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3688 (unspec [(reg:DF
76)
3690 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3693 operands[
1] = gen_rtx (MEM, SImode,
3694 gen_rtx (PLUS, Pmode,
3696 GEN_INT (rs6000_fpmem_offset)));
3698 return
\"lfd %
0,%
1\";
3700 [(set_attr "type" "fpload")])
3702 (define_expand "fix_truncdfsi2"
3703 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
3704 (fix:SI (match_operand:DF
1 "gpc_reg_operand" "")))
3705 (clobber (match_dup
2))
3706 (clobber (match_dup
3))])]
3710 if (!TARGET_POWER2 && !TARGET_POWERPC)
3712 emit_insn (gen_trunc_call (operands[
0], operands[
1],
3713 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
3717 operands[
2] = gen_reg_rtx (DImode);
3718 operands[
3] = gen_rtx (REG, DImode, FPMEM_REGNUM);
3721 (define_insn "*fix_truncdfsi2_internal"
3722 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
3723 (fix:SI (match_operand:DF
1 "gpc_reg_operand" "f")))
3724 (clobber (match_operand:DI
2 "gpc_reg_operand" "=f"))
3725 (clobber (reg:DI
76))]
3728 [(set_attr "length" "
12")])
3731 [(set (match_operand:SI
0 "gpc_reg_operand" "")
3732 (fix:SI (match_operand:DF
1 "gpc_reg_operand" "f")))
3733 (clobber (match_operand:DI
2 "gpc_reg_operand" ""))
3734 (clobber (reg:DI
76))]
3737 (sign_extend:DI (fix:SI (match_operand:DF
1 "gpc_reg_operand" ""))))
3739 (unspec [(match_dup
2)
3741 (set (match_operand:SI
0 "gpc_reg_operand" "")
3742 (unspec [(match_dup
3)
3744 "operands[
3] = gen_rtx (REG, DImode, FPMEM_REGNUM);")
3746 (define_insn "*fctiwz"
3747 [(set (match_operand:DI
0 "gpc_reg_operand" "=f")
3748 (sign_extend:DI (fix:SI (match_operand:DF
1 "gpc_reg_operand" "f"))))]
3749 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3750 "{fcirz|fctiwz} %
0,%
1"
3751 [(set_attr "type" "fp")])
3753 (define_insn "*fix_truncdfsi2_store"
3755 (unspec [(match_operand:DI
0 "gpc_reg_operand" "f")
3757 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3760 operands[
1] = gen_rtx (MEM, DFmode,
3761 gen_rtx (PLUS, Pmode,
3763 GEN_INT (rs6000_fpmem_offset)));
3765 return
\"stfd %
0,%
1\";
3767 [(set_attr "type" "fpstore")])
3769 (define_insn "*fix_truncdfsi2_load"
3770 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
3771 (unspec [(reg:DI
76)
3773 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3776 operands[
1] = gen_rtx (MEM, DFmode,
3777 gen_rtx (PLUS, Pmode,
3779 GEN_INT (rs6000_fpmem_offset + ((WORDS_BIG_ENDIAN) ?
4 :
0))));
3781 return
\"{l|lwz} %
0,%
1\";
3783 [(set_attr "type" "load")])
3785 (define_expand "fixuns_truncdfsi2"
3786 [(set (match_operand:SI
0 "gpc_reg_operand" "")
3787 (unsigned_fix:SI (match_operand:DF
1 "gpc_reg_operand" "")))]
3788 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
3791 emit_insn (gen_trunc_call (operands[
0], operands[
1],
3792 gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
3796 (define_expand "trunc_call"
3797 [(parallel [(set (match_operand:SI
0 "" "")
3798 (fix:SI (match_operand:DF
1 "" "")))
3799 (use (match_operand:SI
2 "" ""))])]
3803 rtx insns = gen_trunc_call_rtl (operands[
0], operands[
1], operands[
2]);
3804 rtx first = XVECEXP (insns,
0,
0);
3805 rtx last = XVECEXP (insns,
0, XVECLEN (insns,
0) -
1);
3807 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
3809 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
3815 (define_expand "trunc_call_rtl"
3816 [(set (reg:DF
33) (match_operand:DF
1 "gpc_reg_operand" ""))
3818 (parallel [(set (reg:SI
3)
3819 (call (mem:SI (match_operand
2 "" "")) (const_int
0)))
3821 (clobber (scratch:SI))])
3822 (set (match_operand:SI
0 "gpc_reg_operand" "")
3827 rs6000_trunc_used =
1;
3830 (define_insn "floatdidf2"
3831 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3832 (float:DF (match_operand:DI
1 "gpc_reg_operand" "f")))]
3833 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3835 [(set_attr "type" "fp")])
3837 (define_insn "fix_truncdfdi2"
3838 [(set (match_operand:DI
0 "gpc_reg_operand" "=f")
3839 (fix:DI (match_operand:DF
1 "gpc_reg_operand" "f")))]
3840 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3842 [(set_attr "type" "fp")])
3844 ;; Define the DImode operations that can be done in a small number
3845 ;; of instructions. The & constraints are to prevent the register
3846 ;; allocator from allocating registers that overlap with the inputs
3847 ;; (for example, having an input in
7,
8 and an output in
6,
7). We
3848 ;; also allow for the the output being the same as one of the inputs.
3850 (define_insn "*adddi3_noppc64"
3851 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,&r,r,r")
3852 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,
0,
0")
3853 (match_operand:DI
2 "reg_or_short_operand" "r,I,r,I")))]
3854 "! TARGET_POWERPC64"
3857 if (WORDS_BIG_ENDIAN)
3858 return (GET_CODE (operands[
2])) != CONST_INT
3859 ?
\"{a|addc} %L0,%L1,%L2\;{ae|adde} %
0,%
1,%
2\"
3860 :
\"{ai|addic} %L0,%L1,%
2\;{a%G2e|add%G2e} %
0,%
1\";
3862 return (GET_CODE (operands[
2])) != CONST_INT
3863 ?
\"{a|addc} %
0,%
1,%
2\;{ae|adde} %L0,%L1,%L2
\"
3864 :
\"{ai|addic} %
0,%
1,%
2\;{a%G2e|add%G2e} %L0,%L1
\";
3866 [(set_attr "length" "
8")])
3868 (define_insn "*subdi3_noppc64"
3869 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,&r,r,r,r")
3870 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "r,I,
0,r,I")
3871 (match_operand:DI
2 "gpc_reg_operand" "r,r,r,
0,
0")))]
3872 "! TARGET_POWERPC64"
3875 if (WORDS_BIG_ENDIAN)
3876 return (GET_CODE (operands[
1]) != CONST_INT)
3877 ?
\"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %
0,%
2,%
1\"
3878 :
\"{sfi|subfic} %L0,%L2,%
1\;{sf%G1e|subf%G1e} %
0,%
2\";
3880 return (GET_CODE (operands[
1]) != CONST_INT)
3881 ?
\"{sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %L0,%L2,%L1
\"
3882 :
\"{sfi|subfic} %
0,%
2,%
1\;{sf%G1e|subf%G1e} %L0,%L2
\";
3884 [(set_attr "length" "
8")])
3886 (define_insn "*negdi2_noppc64"
3887 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
3888 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0")))]
3889 "! TARGET_POWERPC64"
3892 return (WORDS_BIG_ENDIAN)
3893 ?
\"{sfi|subfic} %L0,%L1,
0\;{sfze|subfze} %
0,%
1\"
3894 :
\"{sfi|subfic} %
0,%
1,
0\;{sfze|subfze} %L0,%L1
\";
3896 [(set_attr "length" "
8")])
3898 (define_expand "mulsidi3"
3899 [(set (match_operand:DI
0 "gpc_reg_operand" "")
3900 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
3901 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" ""))))]
3905 if (! TARGET_POWER && ! TARGET_POWERPC)
3907 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
3908 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
3909 emit_insn (gen_mull_call ());
3910 if (WORDS_BIG_ENDIAN)
3911 emit_move_insn (operands[
0], gen_rtx (REG, DImode,
3));
3914 emit_move_insn (operand_subword (operands[
0],
0,
0, DImode),
3915 gen_rtx (REG, SImode,
3));
3916 emit_move_insn (operand_subword (operands[
0],
1,
0, DImode),
3917 gen_rtx (REG, SImode,
4));
3921 else if (TARGET_POWER)
3923 emit_insn (gen_mulsidi3_mq (operands[
0], operands[
1], operands[
2]));
3928 (define_insn "mulsidi3_mq"
3929 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
3930 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "%r"))
3931 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))
3932 (clobber (match_scratch:SI
3 "=q"))]
3934 "mul %
0,%
1,%
2\;mfmq %L0"
3935 [(set_attr "type" "imul")
3936 (set_attr "length" "
8")])
3938 (define_insn "*mulsidi3_powerpc"
3939 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
3940 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "%r"))
3941 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
3942 "TARGET_POWERPC && ! TARGET_POWERPC64"
3945 return (WORDS_BIG_ENDIAN)
3946 ?
\"mulhw %
0,%
1,%
2\;mullw %L0,%
1,%
2\"
3947 :
\"mulhw %L0,%
1,%
2\;mullw %
0,%
1,%
2\";
3949 [(set_attr "type" "imul")
3950 (set_attr "length" "
8")])
3953 [(set (match_operand:DI
0 "gpc_reg_operand" "")
3954 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
3955 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" ""))))]
3956 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
3959 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup
1))
3960 (sign_extend:DI (match_dup
2)))
3963 (mult:SI (match_dup
1)
3967 int endian = (WORDS_BIG_ENDIAN ==
0);
3968 operands[
3] = operand_subword (operands[
0], endian,
0, DImode);
3969 operands[
4] = operand_subword (operands[
0],
1 - endian,
0, DImode);
3972 (define_insn "umulsidi3"
3973 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
3974 (mult:DI (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "%r"))
3975 (zero_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
3976 "TARGET_POWERPC && ! TARGET_POWERPC64"
3979 return (WORDS_BIG_ENDIAN)
3980 ?
\"mulhwu %
0,%
1,%
2\;mullw %L0,%
1,%
2\"
3981 :
\"mulhwu %L0,%
1,%
2\;mullw %
0,%
1,%
2\";
3983 [(set_attr "type" "imul")
3984 (set_attr "length" "
8")])
3987 [(set (match_operand:DI
0 "gpc_reg_operand" "")
3988 (mult:DI (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
3989 (zero_extend:DI (match_operand:SI
2 "gpc_reg_operand" ""))))]
3990 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
3993 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup
1))
3994 (zero_extend:DI (match_dup
2)))
3997 (mult:SI (match_dup
1)
4001 int endian = (WORDS_BIG_ENDIAN ==
0);
4002 operands[
3] = operand_subword (operands[
0], endian,
0, DImode);
4003 operands[
4] = operand_subword (operands[
0],
1 - endian,
0, DImode);
4006 (define_expand "smulsi3_highpart"
4007 [(set (match_operand:SI
0 "gpc_reg_operand" "")
4009 (lshiftrt:DI (mult:DI (sign_extend:DI
4010 (match_operand:SI
1 "gpc_reg_operand" "%r"))
4012 (match_operand:SI
2 "gpc_reg_operand" "r")))
4017 if (! TARGET_POWER && ! TARGET_POWERPC)
4019 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
4020 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
4021 emit_insn (gen_mulh_call ());
4022 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
4025 else if (TARGET_POWER)
4027 emit_insn (gen_smulsi3_highpart_mq (operands[
0], operands[
1], operands[
2]));
4032 (define_insn "smulsi3_highpart_mq"
4033 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4035 (lshiftrt:DI (mult:DI (sign_extend:DI
4036 (match_operand:SI
1 "gpc_reg_operand" "%r"))
4038 (match_operand:SI
2 "gpc_reg_operand" "r")))
4040 (clobber (match_scratch:SI
3 "=q"))]
4043 [(set_attr "type" "imul")])
4046 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4048 (lshiftrt:DI (mult:DI (sign_extend:DI
4049 (match_operand:SI
1 "gpc_reg_operand" "%r"))
4051 (match_operand:SI
2 "gpc_reg_operand" "r")))
4055 [(set_attr "type" "imul")])
4057 (define_insn "umulsi3_highpart"
4058 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4060 (lshiftrt:DI (mult:DI (zero_extend:DI
4061 (match_operand:SI
1 "gpc_reg_operand" "%r"))
4063 (match_operand:SI
2 "gpc_reg_operand" "r")))
4067 [(set_attr "type" "imul")])
4069 ;; If operands
0 and
2 are in the same register, we have a problem. But
4070 ;; operands
0 and
1 (the usual case) can be in the same register. That's
4071 ;; why we have the strange constraints below.
4072 (define_insn "ashldi3_power"
4073 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r,&r")
4074 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r,r,
0,r")
4075 (match_operand:SI
2 "reg_or_cint_operand" "M,i,r,r")))
4076 (clobber (match_scratch:SI
3 "=X,q,q,q"))]
4079 {sli|slwi} %
0,%L1,%h2\;{cal %L0,
0(
0)|li %L0,
0}
4080 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2
4081 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2
4082 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2"
4083 [(set_attr "length" "
8")])
4085 (define_insn "lshrdi3_power"
4086 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r,r,&r")
4087 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r,r,
0,r")
4088 (match_operand:SI
2 "reg_or_cint_operand" "M,i,r,r")))
4089 (clobber (match_scratch:SI
3 "=X,q,q,q"))]
4092 {cal %
0,
0(
0)|li %
0,
0}\;{s%A2i|s%A2wi} %L0,%
1,%h2
4093 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2
4094 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2
4095 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2"
4096 [(set_attr "length" "
8")])
4098 ;; Shift by a variable amount is too complex to be worth open-coding. We
4099 ;; just handle shifts by constants.
4100 (define_insn "ashrdi3_power"
4101 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
4102 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r,r")
4103 (match_operand:SI
2 "const_int_operand" "M,i")))
4104 (clobber (match_scratch:SI
3 "=X,q"))]
4107 {srai|srawi} %
0,%
1,
31\;{srai|srawi} %L0,%
1,%h2
4108 sraiq %
0,%
1,%h2\;srliq %L0,%L1,%h2"
4109 [(set_attr "length" "
8")])
4111 ;; PowerPC64 DImode operations.
4113 (define_expand "adddi3"
4114 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4115 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "")
4116 (match_operand:DI
2 "add_operand" "")))]
4120 if (! TARGET_POWERPC64 && non_add_cint_operand (operands[
2], DImode))
4124 ;; Discourage ai/addic because of carry but provide it in an alternative
4125 ;; allowing register zero as source.
4128 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,?r,r")
4129 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,b,r,b")
4130 (match_operand:DI
2 "add_operand" "r,I,I,J")))]
4139 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
4140 (compare:CC (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r")
4141 (match_operand:DI
2 "reg_or_short_operand" "r,I"))
4143 (clobber (match_scratch:DI
3 "=r,r"))]
4148 [(set_attr "type" "compare")])
4151 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
4152 (compare:CC (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r")
4153 (match_operand:DI
2 "reg_or_short_operand" "r,I"))
4155 (set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
4156 (plus:DI (match_dup
1) (match_dup
2)))]
4161 [(set_attr "type" "compare")])
4163 ;; Split an add that we can't do in one insn into two insns, each of which
4164 ;; does one
16-bit part. This is used by combine. Note that the low-order
4165 ;; add should be last in case the result gets used in an address.
4168 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4169 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "")
4170 (match_operand:DI
2 "non_add_cint_operand" "")))]
4172 [(set (match_dup
0) (plus:DI (match_dup
1) (match_dup
3)))
4173 (set (match_dup
0) (plus:DI (match_dup
0) (match_dup
4)))]
4176 HOST_WIDE_INT low = INTVAL (operands[
2]) &
0xffff;
4177 HOST_WIDE_INT high = INTVAL (operands[
2]) & (~ (HOST_WIDE_INT)
0xffff);
4180 high+=
0x10000, low |= ((HOST_WIDE_INT) -
1) <<
16;
4182 operands[
3] = GEN_INT (high);
4183 operands[
4] = GEN_INT (low);
4186 (define_insn "one_cmpldi2"
4187 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4188 (not:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
4193 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4194 (compare:CC (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4196 (clobber (match_scratch:DI
2 "=r"))]
4199 [(set_attr "type" "compare")])
4202 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
4203 (compare:CC (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4205 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4206 (not:DI (match_dup
1)))]
4209 [(set_attr "type" "compare")])
4212 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
4213 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "r,I")
4214 (match_operand:DI
2 "gpc_reg_operand" "r,r")))]
4221 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4222 (compare:CC (minus:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4223 (match_operand:DI
2 "gpc_reg_operand" "r"))
4225 (clobber (match_scratch:DI
3 "=r"))]
4228 [(set_attr "type" "compare")])
4231 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4232 (compare:CC (minus:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4233 (match_operand:DI
2 "gpc_reg_operand" "r"))
4235 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4236 (minus:DI (match_dup
1) (match_dup
2)))]
4239 [(set_attr "type" "compare")])
4241 (define_expand "subdi3"
4242 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4243 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "")
4244 (match_operand:DI
2 "reg_or_cint_operand" "")))]
4248 if (GET_CODE (operands[
2]) == CONST_INT)
4250 emit_insn (gen_adddi3 (operands[
0], operands[
1],
4251 negate_rtx (DImode, operands[
2])));
4256 (define_insn "absdi2"
4257 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4258 (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0")))
4259 (clobber (match_scratch:DI
2 "=&r,&r"))]
4261 "sradi %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
2,%
0"
4262 [(set_attr "length" "
12")])
4265 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4266 (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0")))
4267 (clobber (match_scratch:DI
2 "=&r,&r"))]
4268 "TARGET_POWERPC64 && reload_completed"
4269 [(set (match_dup
2) (ashiftrt:DI (match_dup
1) (const_int
31)))
4270 (set (match_dup
0) (xor:DI (match_dup
2) (match_dup
1)))
4271 (set (match_dup
0) (minus:DI (match_dup
2) (match_dup
0)))]
4275 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4276 (neg:DI (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0"))))
4277 (clobber (match_scratch:DI
2 "=&r,&r"))]
4279 "sradi %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
0,%
2"
4280 [(set_attr "length" "
12")])
4283 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4284 (neg:DI (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0"))))
4285 (clobber (match_scratch:DI
2 "=&r,&r"))]
4286 "TARGET_POWERPC64 && reload_completed"
4287 [(set (match_dup
2) (ashiftrt:DI (match_dup
1) (const_int
31)))
4288 (set (match_dup
0) (xor:DI (match_dup
2) (match_dup
1)))
4289 (set (match_dup
0) (minus:DI (match_dup
0) (match_dup
2)))]
4292 (define_expand "negdi2"
4293 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4294 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "")))]
4299 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4300 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
4305 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4306 (compare:CC (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4308 (clobber (match_scratch:DI
2 "=r"))]
4311 [(set_attr "type" "compare")])
4314 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
4315 (compare:CC (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4317 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4318 (neg:DI (match_dup
1)))]
4321 [(set_attr "type" "compare")])
4323 (define_insn "ffsdi2"
4324 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
4325 (ffs:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
4327 "neg %
0,%
1\;and %
0,%
0,%
1\;cntlzd %
0,%
0\;subfic %
0,%
0,
64"
4328 [(set_attr "length" "
16")])
4330 (define_insn "muldi3"
4331 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4332 (mult:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4333 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4336 [(set_attr "type" "imul")])
4338 (define_insn "smuldi3_highpart"
4339 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4341 (lshiftrt:TI (mult:TI (sign_extend:TI
4342 (match_operand:DI
1 "gpc_reg_operand" "%r"))
4344 (match_operand:DI
2 "gpc_reg_operand" "r")))
4348 [(set_attr "type" "imul")])
4350 (define_insn "umuldi3_highpart"
4351 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4353 (lshiftrt:TI (mult:TI (zero_extend:TI
4354 (match_operand:DI
1 "gpc_reg_operand" "%r"))
4356 (match_operand:DI
2 "gpc_reg_operand" "r")))
4360 [(set_attr "type" "imul")])
4362 (define_expand "divdi3"
4363 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4364 (div:DI (match_operand:DI
1 "gpc_reg_operand" "")
4365 (match_operand:DI
2 "reg_or_cint_operand" "")))]
4369 if (GET_CODE (operands[
2]) == CONST_INT
4370 && exact_log2 (INTVAL (operands[
2])) >=
0)
4373 operands[
2] = force_reg (DImode, operands[
2]);
4376 (define_expand "moddi3"
4377 [(use (match_operand:DI
0 "gpc_reg_operand" ""))
4378 (use (match_operand:DI
1 "gpc_reg_operand" ""))
4379 (use (match_operand:DI
2 "reg_or_cint_operand" ""))]
4383 int i = exact_log2 (INTVAL (operands[
2]));
4387 if (GET_CODE (operands[
2]) != CONST_INT || i <
0)
4390 temp1 = gen_reg_rtx (DImode);
4391 temp2 = gen_reg_rtx (DImode);
4393 emit_insn (gen_divdi3 (temp1, operands[
1], operands[
2]));
4394 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
4395 emit_insn (gen_subdi3 (operands[
0], operands[
1], temp2));
4400 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4401 (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4402 (match_operand:DI
2 "const_int_operand" "N")))]
4403 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[
2])) >=
0"
4404 "sradi %
0,%
1,%p2\;addze %
0,%
0"
4405 [(set_attr "length" "
8")])
4408 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4409 (compare:CC (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4410 (match_operand:DI
2 "const_int_operand" "N"))
4412 (clobber (match_scratch:DI
3 "=r"))]
4413 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[
2])) >=
0"
4414 "sradi %
3,%
1,%p2\;addze. %
3,%
3"
4415 [(set_attr "type" "compare")
4416 (set_attr "length" "
8")])
4419 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4420 (compare:CC (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4421 (match_operand:DI
2 "const_int_operand" "N"))
4423 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4424 (div:DI (match_dup
1) (match_dup
2)))]
4425 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[
2])) >=
0"
4426 "sradi %
0,%
1,%p2\;addze. %
0,%
0"
4427 [(set_attr "type" "compare")
4428 (set_attr "length" "
8")])
4431 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4432 (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4433 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4436 [(set_attr "type" "idiv")])
4438 (define_insn "udivdi3"
4439 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4440 (udiv:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4441 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4444 [(set_attr "type" "idiv")])
4446 (define_insn "rotldi3"
4447 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4448 (rotate:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4449 (match_operand:DI
2 "reg_or_cint_operand" "ri")))]
4451 "rld%I2cl %
0,%
1,%H2,
0")
4454 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4455 (compare:CC (rotate:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4456 (match_operand:DI
2 "reg_or_cint_operand" "ri"))
4458 (clobber (match_scratch:DI
3 "=r"))]
4460 "rld%I2cl. %
3,%
1,%H2,
0"
4461 [(set_attr "type" "delayed_compare")])
4464 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4465 (compare:CC (rotate:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4466 (match_operand:DI
2 "reg_or_cint_operand" "ri"))
4468 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4469 (rotate:DI (match_dup
1) (match_dup
2)))]
4471 "rld%I2cl. %
0,%
1,%H2,
0"
4472 [(set_attr "type" "delayed_compare")])
4474 (define_expand "ashldi3"
4475 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4476 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "")
4477 (match_operand:SI
2 "reg_or_cint_operand" "")))]
4478 "TARGET_POWERPC64 || TARGET_POWER"
4481 if (TARGET_POWERPC64)
4483 else if (TARGET_POWER)
4485 emit_insn (gen_ashldi3_power (operands[
0], operands[
1], operands[
2]));
4493 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4494 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4495 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
4498 [(set_attr "length" "
8")])
4501 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4502 (compare:CC (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4503 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4505 (clobber (match_scratch:DI
3 "=r"))]
4508 [(set_attr "type" "delayed_compare")])
4511 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4512 (compare:CC (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4513 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4515 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4516 (ashift:DI (match_dup
1) (match_dup
2)))]
4519 [(set_attr "type" "delayed_compare")])
4521 (define_expand "lshrdi3"
4522 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4523 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "")
4524 (match_operand:SI
2 "reg_or_cint_operand" "")))]
4525 "TARGET_POWERPC64 || TARGET_POWER"
4528 if (TARGET_POWERPC64)
4530 else if (TARGET_POWER)
4532 emit_insn (gen_lshrdi3_power (operands[
0], operands[
1], operands[
2]));
4540 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4541 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4542 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
4547 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4548 (compare:CC (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4549 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4551 (clobber (match_scratch:DI
3 "=r"))]
4554 [(set_attr "type" "delayed_compare")])
4557 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4558 (compare:CC (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4559 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4561 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4562 (lshiftrt:DI (match_dup
1) (match_dup
2)))]
4565 [(set_attr "type" "delayed_compare")])
4567 (define_expand "ashrdi3"
4568 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4569 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "")
4570 (match_operand:SI
2 "reg_or_cint_operand" "")))]
4571 "TARGET_POWERPC64 || TARGET_POWER"
4574 if (TARGET_POWERPC64)
4576 else if (TARGET_POWER && GET_CODE (operands[
2]) == CONST_INT)
4578 emit_insn (gen_ashrdi3_power (operands[
0], operands[
1], operands[
2]));
4586 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4587 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4588 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
4590 "srad%I2 %
0,%
1,%H2")
4593 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4594 (compare:CC (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4595 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4597 (clobber (match_scratch:DI
3 "=r"))]
4599 "srad%I2. %
3,%
1,%H2"
4600 [(set_attr "type" "delayed_compare")])
4603 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4604 (compare:CC (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4605 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4607 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4608 (ashiftrt:DI (match_dup
1) (match_dup
2)))]
4610 "srad%I2. %
0,%
1,%H2"
4611 [(set_attr "type" "delayed_compare")])
4613 (define_insn "anddi3"
4614 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4615 (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4616 (match_operand:DI
2 "and_operand" "?r,K,J")))
4617 (clobber (match_scratch:CC
3 "=X,x,x"))]
4625 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x")
4626 (compare:CC (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4627 (match_operand:DI
2 "and_operand" "r,K,J"))
4629 (clobber (match_scratch:DI
3 "=r,r,r"))]
4635 [(set_attr "type" "compare,compare,compare")])
4638 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x,x")
4639 (compare:CC (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4640 (match_operand:DI
2 "and_operand" "r,K,J"))
4642 (set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4643 (and:DI (match_dup
1) (match_dup
2)))]
4649 [(set_attr "type" "compare,compare,compare")])
4651 ;; Take a AND with a constant that cannot be done in a single insn and try to
4652 ;; split it into two insns. This does not verify that the insns are valid
4653 ;; since this need not be done as combine will do it.
4656 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4657 (and:DI (match_operand:DI
1 "gpc_reg_operand" "")
4658 (match_operand:DI
2 "non_and_cint_operand" "")))]
4660 [(set (match_dup
0) (and:DI (match_dup
1) (match_dup
3)))
4661 (set (match_dup
0) (and:DI (match_dup
0) (match_dup
4)))]
4664 int maskval = INTVAL (operands[
2]);
4665 int i, transitions, last_bit_value;
4666 int orig = maskval, first_c = maskval, second_c;
4668 /* We know that MASKVAL must have more than
2 bit-transitions. Start at
4669 the low-order bit and count for the third transition. When we get there,
4670 make a first mask that has everything to the left of that position
4671 a one. Then make the second mask to turn off whatever else is needed. */
4673 for (i =
1, transitions =
0, last_bit_value = maskval &
1; i <
32; i++)
4675 if (((maskval >>=
1) &
1) != last_bit_value)
4676 last_bit_value ^=
1, transitions++;
4678 if (transitions >
2)
4680 first_c |= (~
0) << i;
4685 second_c = orig | ~ first_c;
4687 operands[
3] = gen_rtx (CONST_INT, VOIDmode, first_c);
4688 operands[
4] = gen_rtx (CONST_INT, VOIDmode, second_c);
4691 (define_insn "iordi3"
4692 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4693 (ior:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4694 (match_operand:DI
2 "logical_operand" "r,K,J")))]
4702 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4703 (compare:CC (ior:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4704 (match_operand:DI
2 "gpc_reg_operand" "r"))
4706 (clobber (match_scratch:DI
3 "=r"))]
4709 [(set_attr "type" "compare")])
4712 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4713 (compare:CC (ior:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4714 (match_operand:DI
2 "gpc_reg_operand" "r"))
4716 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4717 (ior:DI (match_dup
1) (match_dup
2)))]
4720 [(set_attr "type" "compare")])
4722 ;; Split an IOR that we can't do in one insn into two insns, each of which
4723 ;; does one
16-bit part. This is used by combine.
4726 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4727 (ior:DI (match_operand:DI
1 "gpc_reg_operand" "")
4728 (match_operand:DI
2 "non_logical_cint_operand" "")))]
4730 [(set (match_dup
0) (ior:DI (match_dup
1) (match_dup
3)))
4731 (set (match_dup
0) (ior:DI (match_dup
0) (match_dup
4)))]
4734 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
4735 INTVAL (operands[
2]) & (~ (HOST_WIDE_INT)
0xffff));
4736 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
4739 (define_insn "xordi3"
4740 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4741 (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4742 (match_operand:DI
2 "logical_operand" "r,K,J")))]
4750 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4751 (compare:CC (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4752 (match_operand:DI
2 "gpc_reg_operand" "r"))
4754 (clobber (match_scratch:DI
3 "=r"))]
4757 [(set_attr "type" "compare")])
4760 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4761 (compare:CC (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4762 (match_operand:DI
2 "gpc_reg_operand" "r"))
4764 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4765 (xor:DI (match_dup
1) (match_dup
2)))]
4768 [(set_attr "type" "compare")])
4770 ;; Split an XOR that we can't do in one insn into two insns, each of which
4771 ;; does one
16-bit part. This is used by combine.
4774 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4775 (xor:DI (match_operand:DI
1 "gpc_reg_operand" "")
4776 (match_operand:DI
2 "non_logical_cint_operand" "")))]
4778 [(set (match_dup
0) (xor:DI (match_dup
1) (match_dup
3)))
4779 (set (match_dup
0) (xor:DI (match_dup
0) (match_dup
4)))]
4782 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
4783 INTVAL (operands[
2]) &
0xffff0000);
4784 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
4788 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4789 (not:DI (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4790 (match_operand:DI
2 "gpc_reg_operand" "r"))))]
4795 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4796 (compare:CC (not:DI (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4797 (match_operand:DI
2 "gpc_reg_operand" "r")))
4799 (clobber (match_scratch:DI
3 "=r"))]
4802 [(set_attr "type" "compare")])
4805 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4806 (compare:CC (not:DI (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4807 (match_operand:DI
2 "gpc_reg_operand" "r")))
4809 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4810 (not:DI (xor:DI (match_dup
1) (match_dup
2))))]
4813 [(set_attr "type" "compare")])
4816 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4817 (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4818 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4823 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4824 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4825 (match_operand:DI
2 "gpc_reg_operand" "r"))
4827 (clobber (match_scratch:DI
3 "=r"))]
4830 [(set_attr "type" "compare")])
4833 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4834 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4835 (match_operand:DI
2 "gpc_reg_operand" "r"))
4837 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4838 (and:DI (not:DI (match_dup
1)) (match_dup
2)))]
4841 [(set_attr "type" "compare")])
4844 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4845 (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4846 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4851 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4852 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4853 (match_operand:DI
2 "gpc_reg_operand" "r"))
4855 (clobber (match_scratch:DI
3 "=r"))]
4858 [(set_attr "type" "compare")])
4861 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4862 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4863 (match_operand:DI
2 "gpc_reg_operand" "r"))
4865 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4866 (ior:DI (not:DI (match_dup
1)) (match_dup
2)))]
4869 [(set_attr "type" "compare")])
4872 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4873 (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4874 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r"))))]
4879 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4880 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4881 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4883 (clobber (match_scratch:DI
3 "=r"))]
4886 [(set_attr "type" "compare")])
4889 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4890 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4891 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4893 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4894 (ior:DI (not:DI (match_dup
1)) (not:DI (match_dup
2))))]
4897 [(set_attr "type" "compare")])
4900 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4901 (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4902 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r"))))]
4907 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4908 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4909 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4911 (clobber (match_scratch:DI
3 "=r"))]
4914 [(set_attr "type" "compare")])
4917 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4918 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4919 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4921 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4922 (and:DI (not:DI (match_dup
1)) (not:DI (match_dup
2))))]
4925 [(set_attr "type" "compare")])
4927 ;; Now define ways of moving data around.
4929 ;; Elf specific ways of loading addresses for non-PIC code.
4930 ;; The output of this could be r0, but we limit it to base
4931 ;; registers, since almost all uses of this will need it
4932 ;; in a base register shortly.
4933 (define_insn "elf_high"
4934 [(set (match_operand:SI
0 "register_operand" "=b")
4935 (high:SI (match_operand
1 "" "")))]
4936 "TARGET_ELF && !TARGET_64BIT"
4937 "{cau|addis} %
0,
0,%
1@ha")
4939 (define_insn "elf_low"
4940 [(set (match_operand:SI
0 "register_operand" "=r")
4941 (lo_sum:SI (match_operand:SI
1 "register_operand" "b")
4942 (match_operand
2 "" "")))]
4943 "TARGET_ELF && !TARGET_64BIT"
4944 "{cal %
0,%a2@l(%
1)|addi %
0,%
1,%
2@l}")
4946 ;; Set up a register with a value from the GOT table
4948 (define_expand "movsi_got"
4949 [(set (match_operand:SI
0 "register_operand" "")
4950 (unspec [(match_operand:SI
1 "got_operand" "")
4952 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic"
4955 if (!pic_offset_table_rtx)
4956 pic_offset_table_rtx = gen_reg_rtx (SImode);
4958 operands[
2] = pic_offset_table_rtx;
4961 emit_insn (gen_movsi_got_large (operands[
0], operands[
1], operands[
2]));
4966 (define_insn "*movsi_got_internal1"
4967 [(set (match_operand:SI
0 "register_operand" "=r")
4968 (unspec [(match_operand:SI
1 "got_operand" "")
4969 (match_operand:SI
2 "register_operand" "b")]
8))]
4970 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic ==
1"
4971 "{l|lwz} %
0,%a1@got(%
2)"
4972 [(set_attr "type" "load")])
4974 (define_expand "movsi_got_large"
4976 (unspec [(match_operand:SI
1 "got_operand" "")]
9))
4978 (unspec [(match_dup
1)
4980 (set (match_operand:SI
0 "register_operand" "")
4981 (mem:SI (plus:SI (match_dup
3)
4982 (match_operand:SI
2 "register_operand" ""))))]
4983 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic >
1"
4986 if (reload_completed || reload_in_progress)
4989 operands[
3] = gen_reg_rtx (SImode);
4992 (define_insn "*movsi_got_internal2_high"
4993 [(set (match_operand:SI
0 "register_operand" "=b")
4994 (unspec [(match_operand:SI
1 "got_operand" "")]
9))]
4995 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic >
1"
4996 "{cau|addis} %
0,
0,%
1@got@ha")
4998 (define_insn "*movsi_got_internal2_losum"
4999 [(set (match_operand:SI
0 "register_operand" "=r")
5000 (unspec [(match_operand:SI
1 "got_operand" "")
5001 (match_operand:SI
2 "register_operand" "b")]
10))]
5002 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic >
1"
5003 "{cal %
0,%a1@got@l(%
2)|addi %
0,%
2,%a1@got@l}")
5005 ;; For SI, we special-case integers that can't be loaded in one insn. We
5006 ;; do the load
16-bits at a time. We could do this by loading from memory,
5007 ;; and this is even supposed to be faster, but it is simpler not to get
5008 ;; integers in the TOC.
5009 (define_expand "movsi"
5010 [(set (match_operand:SI
0 "general_operand" "")
5011 (match_operand:SI
1 "any_operand" ""))]
5015 if (GET_CODE (operands[
0]) != REG)
5016 operands[
1] = force_reg (SImode, operands[
1]);
5018 /* Convert a move of a CONST_DOUBLE into a CONST_INT */
5019 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
5020 operands[
1] = GEN_INT (CONST_DOUBLE_LOW (operands[
1]));
5022 /* Use default pattern for address of ELF small data */
5024 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5025 && (GET_CODE (operands[
1]) == SYMBOL_REF || GET_CODE (operands[
1]) == CONST)
5026 && small_data_operand (operands[
1], SImode))
5028 emit_insn (gen_rtx (SET, VOIDmode, operands[
0], operands[
1]));
5032 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
5033 && flag_pic && got_operand (operands[
1], SImode))
5035 emit_insn (gen_movsi_got (operands[
0], operands[
1]));
5039 if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
5040 && CONSTANT_P (operands[
1])
5041 && GET_CODE (operands[
1]) != HIGH
5042 && GET_CODE (operands[
1]) != CONST_INT)
5044 rtx target = (reload_completed || reload_in_progress)
5045 ? operands[
0] : gen_reg_rtx (SImode);
5047 /* If this is a function address on -mcall-aixdesc or -mcall-nt,
5048 convert it to the address of the descriptor. */
5049 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
5050 && GET_CODE (operands[
1]) == SYMBOL_REF
5051 && XSTR (operands[
1],
0)[
0] == '.')
5053 char *name = XSTR (operands[
1],
0);
5055 while (*name == '.')
5057 new_ref = gen_rtx (SYMBOL_REF, Pmode, name);
5058 CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[
1]);
5059 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[
1]);
5060 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[
1]);
5061 operands[
1] = new_ref;
5064 emit_insn (gen_elf_high (target, operands[
1]));
5065 emit_insn (gen_elf_low (operands[
0], target, operands[
1]));
5069 if (GET_CODE (operands[
1]) == CONST
5070 && DEFAULT_ABI == ABI_NT
5071 && !side_effects_p (operands[
0]))
5073 rtx const_term = const0_rtx;
5074 rtx sym = eliminate_constant_term (XEXP (operands[
1],
0), &const_term);
5075 if (sym && GET_CODE (const_term) == CONST_INT
5076 && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
5078 unsigned HOST_WIDE_INT value = INTVAL (const_term);
5079 int new_reg_p = (flag_expensive_optimizations
5080 && !reload_completed
5081 && !reload_in_progress);
5082 rtx tmp1 = (new_reg_p && value !=
0) ? gen_reg_rtx (SImode) : operands[
0];
5084 emit_insn (gen_movsi (tmp1, sym));
5085 if (INTVAL (const_term) !=
0)
5087 if (value +
0x8000 <
0x10000)
5088 emit_insn (gen_addsi3 (operands[
0], tmp1, GEN_INT (value)));
5092 HOST_WIDE_INT high_int = value & (~ (HOST_WIDE_INT)
0xffff);
5093 HOST_WIDE_INT low_int = value &
0xffff;
5094 rtx tmp2 = (!new_reg_p || !low_int) ? operands[
0] : gen_reg_rtx (Pmode);
5096 if (low_int &
0x8000)
5097 high_int +=
0x10000, low_int |= ((HOST_WIDE_INT) -
1) <<
16;
5099 emit_insn (gen_addsi3 (tmp2, tmp1, GEN_INT (high_int)));
5101 emit_insn (gen_addsi3 (operands[
0], tmp2, GEN_INT (low_int)));
5107 fatal_insn (
\"bad address
\", operands[
1]);
5110 if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
5111 && CONSTANT_P (operands[
1])
5112 && GET_CODE (operands[
1]) != CONST_INT
5113 && GET_CODE (operands[
1]) != HIGH
5114 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[
1]))
5116 /* If we are to limit the number of things we put in the TOC and
5117 this is a symbol plus a constant we can add in one insn,
5118 just put the symbol in the TOC and add the constant. Don't do
5119 this if reload is in progress. */
5120 if (GET_CODE (operands[
1]) == CONST
5121 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
5122 && GET_CODE (XEXP (operands[
1],
0)) == PLUS
5123 && add_operand (XEXP (XEXP (operands[
1],
0),
1), SImode)
5124 && (GET_CODE (XEXP (XEXP (operands[
1],
0),
0)) == LABEL_REF
5125 || GET_CODE (XEXP (XEXP (operands[
1],
0),
0)) == SYMBOL_REF)
5126 && ! side_effects_p (operands[
0]))
5128 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[
1],
0),
0));
5129 rtx other = XEXP (XEXP (operands[
1],
0),
1);
5131 emit_insn (gen_addsi3 (operands[
0], force_reg (SImode, sym), other));
5135 operands[
1] = force_const_mem (SImode, operands[
1]);
5136 if (! memory_address_p (SImode, XEXP (operands[
1],
0))
5137 && ! reload_in_progress)
5138 operands[
1] = change_address (operands[
1], SImode,
5139 XEXP (operands[
1],
0));
5144 [(set (match_operand:SI
0 "nonimmediate_operand" "=r,r,r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
5145 (match_operand:SI
1 "input_operand" "r,S,T,U,m,r,I,J,n,R,*h,r,r,
0"))]
5146 "gpc_reg_operand (operands[
0], SImode)
5147 || gpc_reg_operand (operands[
1], SImode)"
5150 {l|lwz} %
0,[toc]%
1(
2)
5151 {l|lwz} %
0,[toc]%l1(
2)
5153 {l%U1%X1|lwz%U1%X1} %
0,%
1
5154 {st%U0%X0|stw%U0%X0} %
1,%
0
5163 [(set_attr "type" "*,load,load,*,load,store,*,*,*,*,*,*,mtjmpr,*")
5164 (set_attr "length" "
4,
4,
4,
4,
4,
4,
4,
4,
8,
4,
4,
4,
4,
4")])
5166 ;; Split a load of a large constant into the appropriate two-insn
5170 [(set (match_operand:SI
0 "gpc_reg_operand" "")
5171 (match_operand:SI
1 "const_int_operand" ""))]
5172 "(unsigned) (INTVAL (operands[
1]) +
0x8000) >=
0x10000
5173 && (INTVAL (operands[
1]) &
0xffff) !=
0"
5177 (ior:SI (match_dup
0)
5181 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
5182 INTVAL (operands[
1]) &
0xffff0000);
5183 operands[
3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
1]) &
0xffff);
5187 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
5188 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
5190 (set (match_operand:SI
0 "gpc_reg_operand" "=r") (match_dup
1))]
5193 [(set_attr "type" "compare")])
5195 (define_expand "movhi"
5196 [(set (match_operand:HI
0 "general_operand" "")
5197 (match_operand:HI
1 "any_operand" ""))]
5201 if (GET_CODE (operands[
0]) != REG)
5202 operands[
1] = force_reg (HImode, operands[
1]);
5204 if (CONSTANT_P (operands[
1]) && GET_CODE (operands[
1]) != CONST_INT)
5206 operands[
1] = force_const_mem (HImode, operands[
1]);
5207 if (! memory_address_p (HImode, XEXP (operands[
1],
0))
5208 && ! reload_in_progress)
5209 operands[
1] = change_address (operands[
1], HImode,
5210 XEXP (operands[
1],
0));
5215 [(set (match_operand:HI
0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5216 (match_operand:HI
1 "input_operand" "r,m,r,i,*h,r,r,
0"))]
5217 "gpc_reg_operand (operands[
0], HImode)
5218 || gpc_reg_operand (operands[
1], HImode)"
5228 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5230 (define_expand "movqi"
5231 [(set (match_operand:QI
0 "general_operand" "")
5232 (match_operand:QI
1 "any_operand" ""))]
5236 if (GET_CODE (operands[
0]) != REG)
5237 operands[
1] = force_reg (QImode, operands[
1]);
5239 if (CONSTANT_P (operands[
1]) && GET_CODE (operands[
1]) != CONST_INT)
5241 operands[
1] = force_const_mem (QImode, operands[
1]);
5242 if (! memory_address_p (QImode, XEXP (operands[
1],
0))
5243 && ! reload_in_progress)
5244 operands[
1] = change_address (operands[
1], QImode,
5245 XEXP (operands[
1],
0));
5250 [(set (match_operand:QI
0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5251 (match_operand:QI
1 "input_operand" "r,m,r,i,*h,r,r,
0"))]
5252 "gpc_reg_operand (operands[
0], QImode)
5253 || gpc_reg_operand (operands[
1], QImode)"
5263 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
5265 ;; Here is how to move condition codes around. When we store CC data in
5266 ;; an integer register or memory, we store just the high-order
4 bits.
5267 ;; This lets us not shift in the most common case of CR0.
5268 (define_expand "movcc"
5269 [(set (match_operand:CC
0 "nonimmediate_operand" "")
5270 (match_operand:CC
1 "nonimmediate_operand" ""))]
5275 [(set (match_operand:CC
0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
5276 (match_operand:CC
1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
5277 "register_operand (operands[
0], CCmode)
5278 || register_operand (operands[
1], CCmode)"
5282 {rlinm|rlwinm} %
1,%
1,%F0,
0xffffffff\;mtcrf %R0,%
1\;{rlinm|rlwinm} %
1,%
1,%f0,
0xffffffff
5284 mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%f1,
0xf0000000
5286 {l%U1%X1|lwz%U1%X1} %
0,%
1
5287 {st%U0%U1|stw%U0%U1} %
1,%
0"
5288 [(set_attr "type" "*,*,*,compare,*,*,load,store")
5289 (set_attr "length" "*,*,
12,*,
8,*,*,*")])
5291 ;; For floating-point, we normally deal with the floating-point registers
5292 ;; unless -msoft-float is used. The sole exception is that parameter passing
5293 ;; can produce floating-point values in fixed-point registers. Unless the
5294 ;; value is a simple constant or already in memory, we deal with this by
5295 ;; allocating memory and copying the value explicitly via that memory location.
5296 (define_expand "movsf"
5297 [(set (match_operand:SF
0 "nonimmediate_operand" "")
5298 (match_operand:SF
1 "any_operand" ""))]
5302 /* If we are called from reload, we might be getting a SUBREG of a hard
5303 reg. So expand it. */
5304 if (GET_CODE (operands[
0]) == SUBREG
5305 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5306 && REGNO (SUBREG_REG (operands[
0])) < FIRST_PSEUDO_REGISTER)
5307 operands[
0] = alter_subreg (operands[
0]);
5308 if (GET_CODE (operands[
1]) == SUBREG
5309 && GET_CODE (SUBREG_REG (operands[
1])) == REG
5310 && REGNO (SUBREG_REG (operands[
1])) < FIRST_PSEUDO_REGISTER)
5311 operands[
1] = alter_subreg (operands[
1]);
5313 if (TARGET_SOFT_FLOAT && GET_CODE (operands[
0]) == MEM)
5314 operands[
1] = force_reg (SFmode, operands[
1]);
5316 else if (TARGET_HARD_FLOAT)
5318 if (GET_CODE (operands[
1]) == REG && REGNO (operands[
1]) <
32)
5320 /* If this is a store to memory or another integer register do the
5321 move directly. Otherwise store to a temporary stack slot and
5322 load from there into a floating point register. */
5324 if (GET_CODE (operands[
0]) == MEM
5325 || (GET_CODE (operands[
0]) == REG
5326 && (REGNO (operands[
0]) <
32
5327 || (reload_in_progress
5328 && REGNO (operands[
0]) >= FIRST_PSEUDO_REGISTER))))
5330 emit_move_insn (operand_subword (operands[
0],
0,
0, SFmode),
5331 operand_subword (operands[
1],
0,
0, SFmode));
5336 rtx stack_slot = assign_stack_temp (SFmode,
4,
0);
5338 emit_move_insn (stack_slot, operands[
1]);
5339 emit_move_insn (operands[
0], stack_slot);
5344 if (GET_CODE (operands[
0]) == MEM)
5346 /* If operands[
1] is a register, it may have double-precision data
5347 in it, so truncate it to single precision. We need not do
5348 this for POWERPC. */
5349 if (! TARGET_POWERPC && TARGET_HARD_FLOAT
5350 && GET_CODE (operands[
1]) == REG)
5353 = reload_in_progress ? operands[
1] : gen_reg_rtx (SFmode);
5354 emit_insn (gen_aux_truncdfsf2 (newreg, operands[
1]));
5355 operands[
1] = newreg;
5358 operands[
1] = force_reg (SFmode, operands[
1]);
5361 if (GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <
32)
5363 if (GET_CODE (operands[
1]) == MEM
5364 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
5365 || GET_CODE (operands[
1]) == CONST_DOUBLE
5367 || (GET_CODE (operands[
1]) == REG
5368 && (REGNO (operands[
1]) <
32
5369 || (reload_in_progress
5370 && REGNO (operands[
1]) >= FIRST_PSEUDO_REGISTER))))
5372 emit_move_insn (operand_subword (operands[
0],
0,
0, SFmode),
5373 operand_subword (operands[
1],
0,
0, SFmode));
5378 rtx stack_slot = assign_stack_temp (SFmode,
4,
0);
5380 emit_move_insn (stack_slot, operands[
1]);
5381 emit_move_insn (operands[
0], stack_slot);
5387 if (CONSTANT_P (operands[
1]))
5389 operands[
1] = force_const_mem (SFmode, operands[
1]);
5390 if (! memory_address_p (SFmode, XEXP (operands[
1],
0))
5391 && ! reload_in_progress)
5392 operands[
1] = change_address (operands[
1], SFmode,
5393 XEXP (operands[
1],
0));
5398 [(set (match_operand:SF
0 "gpc_reg_operand" "")
5399 (match_operand:SF
1 "easy_fp_constant" ""))]
5400 "reload_completed && REGNO (operands[
0]) <=
31"
5401 [(set (subreg:SI (match_dup
0)
0) (match_dup
2))]
5407 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[
1]);
5408 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5409 operands[
2] = GEN_INT(l);
5413 [(set (match_operand:SF
0 "fp_reg_or_mem_operand" "=f,f,m")
5414 (match_operand:SF
1 "input_operand" "f,m,f"))]
5415 "(gpc_reg_operand (operands[
0], SFmode)
5416 || gpc_reg_operand (operands[
1], SFmode)) && TARGET_HARD_FLOAT"
5421 [(set_attr "type" "fp,fpload,fpstore")])
5424 [(set (match_operand:SF
0 "nonimmediate_operand" "=r,r,m,r,r,r")
5425 (match_operand:SF
1 "input_operand" "r,m,r,I,J,R"))]
5426 "(gpc_reg_operand (operands[
0], SFmode)
5427 || gpc_reg_operand (operands[
1], SFmode)) && TARGET_SOFT_FLOAT"
5430 {l%U1%X1|lwz%U1%X1} %
0,%
1
5431 {st%U0%X0|stw%U0%X0} %
1,%
0
5435 [(set_attr "type" "*,load,store,*,*,*")])
5438 (define_expand "movdf"
5439 [(set (match_operand:DF
0 "nonimmediate_operand" "")
5440 (match_operand:DF
1 "any_operand" ""))]
5444 if (GET_CODE (operands[
0]) != REG)
5445 operands[
1] = force_reg (DFmode, operands[
1]);
5447 /* Stores between FPR and any non-FPR registers must go through a
5448 temporary stack slot. */
5450 if (TARGET_POWERPC64
5451 && GET_CODE (operands[
0]) == REG && GET_CODE (operands[
1]) == REG
5452 && ((FP_REGNO_P (REGNO (operands[
0]))
5453 && ! FP_REGNO_P (REGNO (operands[
1])))
5454 || (FP_REGNO_P (REGNO (operands[
1]))
5455 && ! FP_REGNO_P (REGNO (operands[
0])))))
5457 rtx stack_slot = assign_stack_temp (DFmode,
8,
0);
5459 emit_move_insn (stack_slot, operands[
1]);
5460 emit_move_insn (operands[
0], stack_slot);
5464 if (CONSTANT_P (operands[
1]) && ! easy_fp_constant (operands[
1], DFmode))
5466 operands[
1] = force_const_mem (DFmode, operands[
1]);
5467 if (! memory_address_p (DFmode, XEXP (operands[
1],
0))
5468 && ! reload_in_progress)
5469 operands[
1] = change_address (operands[
1], DFmode,
5470 XEXP (operands[
1],
0));
5475 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5476 (match_operand:DF
1 "easy_fp_constant" ""))]
5477 "TARGET_32BIT && reload_completed && REGNO (operands[
0]) <=
31"
5478 [(set (match_dup
2) (match_dup
3))
5479 (set (match_dup
4) (match_dup
5))]
5481 { operands[
2] = operand_subword (operands[
0],
0,
0, DFmode);
5482 operands[
3] = operand_subword (operands[
1],
0,
0, DFmode);
5483 operands[
4] = operand_subword (operands[
0],
1,
0, DFmode);
5484 operands[
5] = operand_subword (operands[
1],
1,
0, DFmode); }")
5487 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5488 (match_operand:DF
1 "easy_fp_constant" ""))]
5489 "TARGET_64BIT && reload_completed && REGNO (operands[
0]) <=
31"
5490 [(set (subreg:DI (match_dup
0)
0) (subreg:DI (match_dup
1)
0))]
5493 ;; Don't have reload use general registers to load a constant. First,
5494 ;; it might not work if the output operand has is the equivalent of
5495 ;; a non-offsettable memref, but also it is less efficient than loading
5496 ;; the constant into an FP register, since it will probably be used there.
5497 ;; The "??" is a kludge until we can figure out a more reasonable way
5498 ;; of handling these non-offsettable values.
5500 [(set (match_operand:DF
0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
5501 (match_operand:DF
1 "input_operand" "r,o,r,G,f,m,f"))]
5502 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
5503 && (register_operand (operands[
0], DFmode)
5504 || register_operand (operands[
1], DFmode))"
5507 switch (which_alternative)
5510 /* We normally copy the low-numbered register first. However, if
5511 the first register operand
0 is the same as the second register of
5512 operand
1, we must copy in the opposite order. */
5513 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5514 return
\"mr %L0,%L1\;mr %
0,%
1\";
5516 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5518 /* If the low-address word is used in the address, we must load it
5519 last. Otherwise, load it first. Note that we cannot have
5520 auto-increment in that case since the address register is known to be
5522 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5524 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
5526 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
5528 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
5532 return
\"fmr %
0,%
1\";
5534 return
\"lfd%U1%X1 %
0,%
1\";
5536 return
\"stfd%U0%X0 %
1,%
0\";
5539 [(set_attr "type" "*,load,store,*,fp,fpload,fpstore")
5540 (set_attr "length" "
8,
8,
8,
8,*,*,*")])
5543 [(set (match_operand:DF
0 "nonimmediate_operand" "=r,r,o,r")
5544 (match_operand:DF
1 "input_operand" "r,o,r,G"))]
5545 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5546 && (register_operand (operands[
0], DFmode)
5547 || register_operand (operands[
1], DFmode))"
5550 switch (which_alternative)
5553 /* We normally copy the low-numbered register first. However, if
5554 the first register operand
0 is the same as the second register of
5555 operand
1, we must copy in the opposite order. */
5556 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5557 return
\"mr %L0,%L1\;mr %
0,%
1\";
5559 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5561 /* If the low-address word is used in the address, we must load it
5562 last. Otherwise, load it first. Note that we cannot have
5563 auto-increment in that case since the address register is known to be
5565 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5567 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
5569 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
5571 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
5576 [(set_attr "type" "*,load,store,*")
5577 (set_attr "length" "
8,
8,
8,
8")])
5580 [(set (match_operand:DF
0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
5581 (match_operand:DF
1 "input_operand" "r,o,r,G,f,m,f"))]
5582 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
5583 && (register_operand (operands[
0], DFmode)
5584 || register_operand (operands[
1], DFmode))"
5593 [(set_attr "type" "*,load,store,*,fp,fpload,fpstore")])
5596 [(set (match_operand:DF
0 "nonimmediate_operand" "=r,r,o,r")
5597 (match_operand:DF
1 "input_operand" "r,o,r,G"))]
5598 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5599 && (register_operand (operands[
0], DFmode)
5600 || register_operand (operands[
1], DFmode))"
5606 [(set_attr "type" "*,load,store,*")])
5608 ;; Next come the multi-word integer load and store and the load and store
5610 (define_expand "movdi"
5611 [(set (match_operand:DI
0 "general_operand" "")
5612 (match_operand:DI
1 "any_operand" ""))]
5616 if (GET_CODE (operands[
0]) != REG)
5617 operands[
1] = force_reg (DImode, operands[
1]);
5620 && (GET_CODE (operands[
1]) == CONST_DOUBLE
5621 || GET_CODE (operands[
1]) == CONST_INT))
5626 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
5628 low = CONST_DOUBLE_LOW (operands[
1]);
5629 high = CONST_DOUBLE_HIGH (operands[
1]);
5632 #if HOST_BITS_PER_WIDE_INT == 32
5634 low = INTVAL (operands[
1]);
5635 high = (low <
0) ? ~
0 :
0;
5639 low = INTVAL (operands[
1]) &
0xffffffff;
5640 high = (HOST_WIDE_INT) INTVAL (operands[
1]) >>
32;
5646 emit_move_insn (operands[
0], GEN_INT (high));
5647 emit_insn (gen_ashldi3 (operands[
0], operands[
0], GEN_INT(
32)));
5650 HOST_WIDE_INT low_low = low &
0xffff;
5651 HOST_WIDE_INT low_high = low & (~ (HOST_WIDE_INT)
0xffff);
5653 emit_insn (gen_iordi3 (operands[
0], operands[
0],
5654 GEN_INT (low_high)));
5656 emit_insn (gen_iordi3 (operands[
0], operands[
0],
5657 GEN_INT (low_low)));
5663 /* Stores between FPR and any non-FPR registers must go through a
5664 temporary stack slot. */
5666 if (GET_CODE (operands[
0]) == REG && GET_CODE (operands[
1]) == REG
5667 && ((FP_REGNO_P (REGNO (operands[
0]))
5668 && ! FP_REGNO_P (REGNO (operands[
1])))
5669 || (FP_REGNO_P (REGNO (operands[
1]))
5670 && ! FP_REGNO_P (REGNO (operands[
0])))))
5672 rtx stack_slot = assign_stack_temp (DImode,
8,
0);
5674 emit_move_insn (stack_slot, operands[
1]);
5675 emit_move_insn (operands[
0], stack_slot);
5681 [(set (match_operand:DI
0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
5682 (match_operand:DI
1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
5684 && (gpc_reg_operand (operands[
0], DImode)
5685 || gpc_reg_operand (operands[
1], DImode))"
5688 switch (which_alternative)
5691 /* We normally copy the low-numbered register first. However, if
5692 the first register operand
0 is the same as the second register of
5693 operand
1, we must copy in the opposite order. */
5694 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5695 return
\"mr %L0,%L1\;mr %
0,%
1\";
5697 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5699 /* If the low-address word is used in the address, we must load it
5700 last. Otherwise, load it first. Note that we cannot have
5701 auto-increment in that case since the address register is known to be
5703 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5705 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
5707 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
5709 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
5711 return
\"fmr %
0,%
1\";
5713 return
\"lfd%U1%X1 %
0,%
1\";
5715 return
\"stfd%U0%X0 %
1,%
0\";
5724 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
5725 (set_attr "length" "
8,
8,
8,*,*,*,
8,
12,
8,
12,
16")])
5728 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5729 (match_operand:DI
1 "const_int_operand" ""))]
5730 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) <=
1"
5731 [(set (match_dup
2) (match_dup
4))
5732 (set (match_dup
3) (match_dup
1))]
5735 operands[
2] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
5736 operands[
3] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
5737 operands[
4] = (INTVAL (operands[
1]) &
0x80000000) ? constm1_rtx : const0_rtx;
5741 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5742 (match_operand:DI
1 "const_int_operand" ""))]
5743 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) >=
2"
5744 [(set (match_dup
3) (match_dup
5))
5745 (set (match_dup
2) (match_dup
4))
5746 (set (match_dup
3) (ior:SI (match_dup
3) (match_dup
6)))]
5749 HOST_WIDE_INT value = INTVAL (operands[
1]);
5750 operands[
2] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
5751 operands[
3] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
5752 operands[
4] = (value &
0x80000000) ? constm1_rtx : const0_rtx;
5753 operands[
5] = GEN_INT (value &
0xffff0000);
5754 operands[
6] = GEN_INT (value &
0x0000ffff);
5758 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5759 (match_operand:DI
1 "const_double_operand" ""))]
5760 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) <=
2"
5761 [(set (match_dup
2) (match_dup
4))
5762 (set (match_dup
3) (match_dup
5))]
5765 operands[
2] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
5766 operands[
3] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
5767 operands[
4] = GEN_INT (CONST_DOUBLE_HIGH (operands[
1]));
5768 operands[
5] = GEN_INT (CONST_DOUBLE_LOW (operands[
1]));
5772 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5773 (match_operand:DI
1 "const_double_operand" ""))]
5774 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) ==
3"
5775 [(set (match_dup
2) (match_dup
4))
5776 (set (match_dup
3) (match_dup
5))
5777 (set (match_dup
2) (ior:SI (match_dup
2) (match_dup
6)))]
5780 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[
1]);
5781 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[
1]);
5782 rtx high_reg = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
5783 rtx low_reg = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
5785 if (((unsigned HOST_WIDE_INT) (low +
0x8000) <
0x10000)
5786 || (low &
0xffff) ==
0)
5788 operands[
2] = high_reg;
5789 operands[
3] = low_reg;
5790 operands[
4] = GEN_INT (high &
0xffff0000);
5791 operands[
5] = GEN_INT (low);
5792 operands[
6] = GEN_INT (high &
0x0000ffff);
5796 operands[
2] = low_reg;
5797 operands[
3] = high_reg;
5798 operands[
4] = GEN_INT (low &
0xffff0000);
5799 operands[
5] = GEN_INT (high);
5800 operands[
6] = GEN_INT (low &
0x0000ffff);
5805 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5806 (match_operand:DI
1 "const_double_operand" ""))]
5807 "TARGET_32BIT && reload_completed && num_insns_constant (operands[
1], DImode) >=
4"
5808 [(set (match_dup
2) (match_dup
4))
5809 (set (match_dup
3) (match_dup
5))
5810 (set (match_dup
2) (ior:SI (match_dup
2) (match_dup
6)))
5811 (set (match_dup
3) (ior:SI (match_dup
3) (match_dup
7)))]
5814 HOST_WIDE_INT high = CONST_DOUBLE_HIGH (operands[
1]);
5815 HOST_WIDE_INT low = CONST_DOUBLE_LOW (operands[
1]);
5817 operands[
2] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN ==
0);
5818 operands[
3] = gen_rtx (SUBREG, SImode, operands[
0], WORDS_BIG_ENDIAN !=
0);
5819 operands[
4] = GEN_INT (high &
0xffff0000);
5820 operands[
5] = GEN_INT (low &
0xffff0000);
5821 operands[
6] = GEN_INT (high &
0x0000ffff);
5822 operands[
7] = GEN_INT (low &
0x0000ffff);
5826 [(set (match_operand:DI
0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
5827 (match_operand:DI
1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,
0"))]
5829 && (gpc_reg_operand (operands[
0], DImode)
5830 || gpc_reg_operand (operands[
1], DImode))"
5845 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
5846 (set_attr "length" "
4,
4,
4,
4,
4,
20,
4,
4,
4,
4,
4,
4,
4")])
5848 ;; Split a load of a large constant into the appropriate five-instruction
5849 ;; sequence. The expansion in movdi tries to perform the minimum number of
5850 ;; steps, but here we have to handle anything in a constant number of insns.
5853 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5854 (match_operand:DI
1 "const_double_operand" ""))]
5855 "TARGET_64BIT && num_insns_constant (operands[
1], DImode) >
1"
5859 (ior:DI (match_dup
0)
5862 (ashift:DI (match_dup
0)
5865 (ior:DI (match_dup
0)
5868 (ior:DI (match_dup
0)
5875 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
5877 low = CONST_DOUBLE_LOW (operands[
1]);
5878 high = CONST_DOUBLE_HIGH (operands[
1]);
5881 #if HOST_BITS_PER_WIDE_INT == 32
5883 low = INTVAL (operands[
1]);
5884 high = (low <
0) ? ~
0 :
0;
5888 low = INTVAL (operands[
1]) &
0xffffffff;
5889 high = (HOST_WIDE_INT) INTVAL (operands[
1]) >>
32;
5893 if ((high +
0x8000) <
0x10000
5894 && ((low &
0xffff) ==
0 || (low & (~ (HOST_WIDE_INT)
0xffff)) ==
0))
5897 operands[
2] = GEN_INT (high & (~ (HOST_WIDE_INT)
0xffff));
5898 operands[
3] = GEN_INT (high &
0xffff);
5899 operands[
4] = GEN_INT (low & (~ (HOST_WIDE_INT)
0xffff));
5900 operands[
5] = GEN_INT (low &
0xffff);
5904 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
5905 (compare:CC (match_operand:DI
1 "gpc_reg_operand" "r")
5907 (set (match_operand:DI
0 "gpc_reg_operand" "=r") (match_dup
1))]
5910 [(set_attr "type" "compare")])
5912 ;; TImode is similar, except that we usually want to compute the address into
5913 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
5914 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
5915 (define_expand "movti"
5916 [(parallel [(set (match_operand:TI
0 "general_operand" "")
5917 (match_operand:TI
1 "general_operand" ""))
5918 (clobber (scratch:SI))])]
5919 "TARGET_STRING || TARGET_POWERPC64"
5922 if (GET_CODE (operands[
0]) == MEM)
5923 operands[
1] = force_reg (TImode, operands[
1]);
5925 if (GET_CODE (operands[
0]) == MEM
5926 && GET_CODE (XEXP (operands[
0],
0)) != REG
5927 && ! reload_in_progress)
5928 operands[
0] = change_address (operands[
0], TImode,
5929 copy_addr_to_reg (XEXP (operands[
0],
0)));
5931 if (GET_CODE (operands[
1]) == MEM
5932 && GET_CODE (XEXP (operands[
1],
0)) != REG
5933 && ! reload_in_progress)
5934 operands[
1] = change_address (operands[
1], TImode,
5935 copy_addr_to_reg (XEXP (operands[
1],
0)));
5938 ;; We say that MQ is clobbered in the last alternative because the first
5939 ;; alternative would never get used otherwise since it would need a reload
5940 ;; while the
2nd alternative would not. We put memory cases first so they
5941 ;; are preferred. Otherwise, we'd try to reload the output instead of
5942 ;; giving the SCRATCH mq.
5944 [(set (match_operand:TI
0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
5945 (match_operand:TI
1 "reg_or_mem_operand" "r,r,r,Q,m"))
5946 (clobber (match_scratch:SI
2 "=q,q#X,X,X,X"))]
5947 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
5948 && (gpc_reg_operand (operands[
0], TImode) || gpc_reg_operand (operands[
1], TImode))"
5951 switch (which_alternative)
5957 return
\"{stsi|stswi} %
1,%P0,
16\";
5960 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0
\";
5963 /* Normally copy registers with lowest numbered register copied first.
5964 But copy in the other order if the first register of the output
5965 is the second, third, or fourth register in the input. */
5966 if (REGNO (operands[
0]) >= REGNO (operands[
1]) +
1
5967 && REGNO (operands[
0]) <= REGNO (operands[
1]) +
3)
5968 return
\"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %
0,%
1\";
5970 return
\"mr %
0,%
1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1
\";
5972 /* If the address is not used in the output, we can use lsi. Otherwise,
5973 fall through to generating four loads. */
5974 if (! reg_overlap_mentioned_p (operands[
0], operands[
1]))
5975 return
\"{lsi|lswi} %
0,%P1,
16\";
5976 /* ... fall through ... */
5978 /* If the address register is the same as the register for the lowest-
5979 addressed word, load it last. Similarly for the next two words.
5980 Otherwise load lowest address to highest. */
5981 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5983 return
\"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %
0,%
1\";
5984 else if (refers_to_regno_p (REGNO (operands[
0]) +
1,
5985 REGNO (operands[
0]) +
2, operands[
1],
0))
5986 return
\"{l|lwz} %
0,%
1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1
\";
5987 else if (refers_to_regno_p (REGNO (operands[
0]) +
2,
5988 REGNO (operands[
0]) +
3, operands[
1],
0))
5989 return
\"{l|lwz} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1
\";
5991 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1
\";
5994 [(set_attr "type" "store,store,*,load,load")
5995 (set_attr "length" "*,
16,
16,*,
16")])
5998 [(set (match_operand:TI
0 "reg_or_mem_operand" "=m,????r,????r")
5999 (match_operand:TI
1 "reg_or_mem_operand" "r,r,m"))
6000 (clobber (match_scratch:SI
2 "=X,X,X"))]
6001 "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
6002 && (gpc_reg_operand (operands[
0], TImode) || gpc_reg_operand (operands[
1], TImode))"
6005 switch (which_alternative)
6011 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0
\";
6014 /* Normally copy registers with lowest numbered register copied first.
6015 But copy in the other order if the first register of the output
6016 is the second, third, or fourth register in the input. */
6017 if (REGNO (operands[
0]) >= REGNO (operands[
1]) +
1
6018 && REGNO (operands[
0]) <= REGNO (operands[
1]) +
3)
6019 return
\"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %
0,%
1\";
6021 return
\"mr %
0,%
1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1
\";
6023 /* If the address register is the same as the register for the lowest-
6024 addressed word, load it last. Similarly for the next two words.
6025 Otherwise load lowest address to highest. */
6026 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
6028 return
\"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %
0,%
1\";
6029 else if (refers_to_regno_p (REGNO (operands[
0]) +
1,
6030 REGNO (operands[
0]) +
2, operands[
1],
0))
6031 return
\"{l|lwz} %
0,%
1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1
\";
6032 else if (refers_to_regno_p (REGNO (operands[
0]) +
2,
6033 REGNO (operands[
0]) +
3, operands[
1],
0))
6034 return
\"{l|lwz} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1
\";
6036 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1
\";
6039 [(set_attr "type" "store,*,load")
6040 (set_attr "length" "
16,
16,
16")])
6043 [(set (match_operand:TI
0 "nonimmediate_operand" "=r,r,m")
6044 (match_operand:TI
1 "input_operand" "r,m,r"))]
6045 "TARGET_POWERPC64 && (gpc_reg_operand (operands[
0], TImode)
6046 || gpc_reg_operand (operands[
1], TImode))"
6049 switch (which_alternative)
6052 /* We normally copy the low-numbered register first. However, if
6053 the first register operand
0 is the same as the second register of
6054 operand
1, we must copy in the opposite order. */
6055 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
6056 return
\"mr %L0,%L1\;mr %
0,%
1\";
6058 return
\"mr %
0,%
1\;mr %L0,%L1
\";
6060 /* If the low-address word is used in the address, we must load it
6061 last. Otherwise, load it first. Note that we cannot have
6062 auto-increment in that case since the address register is known to be
6064 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
6066 return
\"ld %L0,%L1\;ld %
0,%
1\";
6068 return
\"ld%U1 %
0,%
1\;ld %L0,%L1
\";
6070 return
\"std%U0 %
1,%
0\;std %L1,%L0
\";
6073 [(set_attr "type" "*,load,store")
6074 (set_attr "length" "
8,
8,
8")])
6076 (define_expand "load_multiple"
6077 [(match_par_dup
3 [(set (match_operand:SI
0 "" "")
6078 (match_operand:SI
1 "" ""))
6079 (use (match_operand:SI
2 "" ""))])]
6088 /* Support only loading a constant number of fixed-point registers from
6089 memory and only bother with this if more than two; the machine
6090 doesn't support more than eight. */
6091 if (GET_CODE (operands[
2]) != CONST_INT
6092 || INTVAL (operands[
2]) <=
2
6093 || INTVAL (operands[
2]) >
8
6094 || GET_CODE (operands[
1]) != MEM
6095 || GET_CODE (operands[
0]) != REG
6096 || REGNO (operands[
0]) >=
32)
6099 count = INTVAL (operands[
2]);
6100 regno = REGNO (operands[
0]);
6102 operands[
3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
6103 from = force_reg (SImode, XEXP (operands[
1],
0));
6105 for (i =
0; i < count; i++)
6106 XVECEXP (operands[
3],
0, i)
6107 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
6108 gen_rtx (MEM, SImode, plus_constant (from, i *
4)));
6112 [(match_parallel
0 "load_multiple_operation"
6113 [(set (match_operand:SI
1 "gpc_reg_operand" "=r")
6114 (mem:SI (match_operand:SI
2 "register_operand" "b")))])]
6118 /* We have to handle the case where the pseudo used to contain the address
6119 is assigned to one of the output registers. */
6121 int words = XVECLEN (operands[
0],
0);
6124 if (XVECLEN (operands[
0],
0) ==
1)
6125 return
\"{l|lwz} %
1,
0(%
2)
\";
6127 for (i =
0; i < words; i++)
6128 if (refers_to_regno_p (REGNO (operands[
1]) + i,
6129 REGNO (operands[
1]) + i +
1, operands[
2],
0))
6133 xop[
0] = operands[
1];
6134 xop[
1] = operands[
2];
6135 xop[
2] = GEN_INT (
4 * (words-
1));
6136 output_asm_insn (
\"{lsi|lswi} %
0,%
1,%
2\;{l|lwz} %
1,%
2(%
1)
\", xop);
6141 xop[
0] = operands[
1];
6142 xop[
1] = gen_rtx (REG, SImode, REGNO (operands[
1]) +
1);
6143 xop[
2] = GEN_INT (
4 * (words-
1));
6144 output_asm_insn (
\"{cal %
0,
4(%
0)|addi %
0,%
0,
4}\;{lsi|lswi} %
1,%
0,%
2\;{l|lwz} %
0,-
4(%
0)
\", xop);
6149 for (j =
0; j < words; j++)
6152 xop[
0] = gen_rtx (REG, SImode, REGNO (operands[
1]) + j);
6153 xop[
1] = operands[
2];
6154 xop[
2] = GEN_INT (j *
4);
6155 output_asm_insn (
\"{l|lwz} %
0,%
2(%
1)
\", xop);
6157 xop[
0] = operands[
2];
6158 xop[
1] = GEN_INT (i *
4);
6159 output_asm_insn (
\"{l|lwz} %
0,%
1(%
0)
\", xop);
6164 return
\"{lsi|lswi} %
1,%
2,%N0
\";
6166 [(set_attr "type" "load")
6167 (set_attr "length" "
32")])
6170 (define_expand "store_multiple"
6171 [(match_par_dup
3 [(set (match_operand:SI
0 "" "")
6172 (match_operand:SI
1 "" ""))
6173 (clobber (scratch:SI))
6174 (use (match_operand:SI
2 "" ""))])]
6183 /* Support only storing a constant number of fixed-point registers to
6184 memory and only bother with this if more than two; the machine
6185 doesn't support more than eight. */
6186 if (GET_CODE (operands[
2]) != CONST_INT
6187 || INTVAL (operands[
2]) <=
2
6188 || INTVAL (operands[
2]) >
8
6189 || GET_CODE (operands[
0]) != MEM
6190 || GET_CODE (operands[
1]) != REG
6191 || REGNO (operands[
1]) >=
32)
6194 count = INTVAL (operands[
2]);
6195 regno = REGNO (operands[
1]);
6197 operands[
3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count +
1));
6198 to = force_reg (SImode, XEXP (operands[
0],
0));
6200 XVECEXP (operands[
3],
0,
0)
6201 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[
1]);
6202 XVECEXP (operands[
3],
0,
1) = gen_rtx (CLOBBER, VOIDmode,
6203 gen_rtx (SCRATCH, SImode));
6205 for (i =
1; i < count; i++)
6206 XVECEXP (operands[
3],
0, i +
1)
6207 = gen_rtx (SET, VOIDmode,
6208 gen_rtx (MEM, SImode, plus_constant (to, i *
4)),
6209 gen_rtx (REG, SImode, regno + i));
6213 [(match_parallel
0 "store_multiple_operation"
6214 [(set (match_operand:SI
1 "indirect_operand" "=Q")
6215 (match_operand:SI
2 "gpc_reg_operand" "r"))
6216 (clobber (match_scratch:SI
3 "=q"))])]
6217 "TARGET_STRING && TARGET_POWER"
6218 "{stsi|stswi} %
2,%P1,%O0"
6219 [(set_attr "type" "store")])
6222 [(match_parallel
0 "store_multiple_operation"
6223 [(set (mem:SI (match_operand:SI
1 "register_operand" "b"))
6224 (match_operand:SI
2 "gpc_reg_operand" "r"))
6225 (clobber (match_scratch:SI
3 "X"))])]
6226 "TARGET_STRING && !TARGET_POWER"
6227 "{stsi|stswi} %
2,%
1,%O0"
6228 [(set_attr "type" "store")])
6231 ;; String/block move insn.
6232 ;; Argument
0 is the destination
6233 ;; Argument
1 is the source
6234 ;; Argument
2 is the length
6235 ;; Argument
3 is the alignment
6237 (define_expand "movstrsi"
6238 [(parallel [(set (match_operand:BLK
0 "" "")
6239 (match_operand:BLK
1 "" ""))
6240 (use (match_operand:SI
2 "" ""))
6241 (use (match_operand:SI
3 "" ""))])]
6245 if (expand_block_move (operands))
6251 ;; Move up to
32 bytes at a time. The fixed registers are needed because the
6252 ;; register allocator doesn't have a clue about allocating
8 word registers
6253 (define_expand "movstrsi_8reg"
6254 [(parallel [(set (match_operand
0 "" "")
6255 (match_operand
1 "" ""))
6256 (use (match_operand
2 "" ""))
6257 (use (match_operand
3 "" ""))
6258 (clobber (reg:SI
5))
6259 (clobber (reg:SI
6))
6260 (clobber (reg:SI
7))
6261 (clobber (reg:SI
8))
6262 (clobber (reg:SI
9))
6263 (clobber (reg:SI
10))
6264 (clobber (reg:SI
11))
6265 (clobber (reg:SI
12))
6266 (clobber (match_scratch:SI
4 ""))])]
6271 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6272 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6273 (use (match_operand:SI
2 "immediate_operand" "i"))
6274 (use (match_operand:SI
3 "immediate_operand" "i"))
6275 (clobber (match_operand:SI
4 "register_operand" "=r"))
6276 (clobber (reg:SI
6))
6277 (clobber (reg:SI
7))
6278 (clobber (reg:SI
8))
6279 (clobber (reg:SI
9))
6280 (clobber (reg:SI
10))
6281 (clobber (reg:SI
11))
6282 (clobber (reg:SI
12))
6283 (clobber (match_scratch:SI
5 "=q"))]
6284 "TARGET_STRING && TARGET_POWER
6285 && ((INTVAL (operands[
2]) >
24 && INTVAL (operands[
2]) <
32) || INTVAL (operands[
2]) ==
0)
6286 && (REGNO (operands[
0]) <
5 || REGNO (operands[
0]) >
12)
6287 && (REGNO (operands[
1]) <
5 || REGNO (operands[
1]) >
12)
6288 && REGNO (operands[
4]) ==
5"
6289 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6290 [(set_attr "type" "load")
6291 (set_attr "length" "
8")])
6294 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6295 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6296 (use (match_operand:SI
2 "immediate_operand" "i"))
6297 (use (match_operand:SI
3 "immediate_operand" "i"))
6298 (clobber (match_operand:SI
4 "register_operand" "=r"))
6299 (clobber (reg:SI
6))
6300 (clobber (reg:SI
7))
6301 (clobber (reg:SI
8))
6302 (clobber (reg:SI
9))
6303 (clobber (reg:SI
10))
6304 (clobber (reg:SI
11))
6305 (clobber (reg:SI
12))
6306 (clobber (match_scratch:SI
5 "X"))]
6307 "TARGET_STRING && !TARGET_POWER
6308 && ((INTVAL (operands[
2]) >
24 && INTVAL (operands[
2]) <
32) || INTVAL (operands[
2]) ==
0)
6309 && (REGNO (operands[
0]) <
5 || REGNO (operands[
0]) >
12)
6310 && (REGNO (operands[
1]) <
5 || REGNO (operands[
1]) >
12)
6311 && REGNO (operands[
4]) ==
5"
6312 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6313 [(set_attr "type" "load")
6314 (set_attr "length" "
8")])
6316 ;; Move up to
24 bytes at a time. The fixed registers are needed because the
6317 ;; register allocator doesn't have a clue about allocating
6 word registers
6318 (define_expand "movstrsi_6reg"
6319 [(parallel [(set (match_operand
0 "" "")
6320 (match_operand
1 "" ""))
6321 (use (match_operand
2 "" ""))
6322 (use (match_operand
3 "" ""))
6323 (clobber (reg:SI
7))
6324 (clobber (reg:SI
8))
6325 (clobber (reg:SI
9))
6326 (clobber (reg:SI
10))
6327 (clobber (reg:SI
11))
6328 (clobber (reg:SI
12))
6329 (clobber (match_scratch:SI
4 ""))])]
6334 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6335 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6336 (use (match_operand:SI
2 "immediate_operand" "i"))
6337 (use (match_operand:SI
3 "immediate_operand" "i"))
6338 (clobber (match_operand:SI
4 "register_operand" "=r"))
6339 (clobber (reg:SI
8))
6340 (clobber (reg:SI
9))
6341 (clobber (reg:SI
10))
6342 (clobber (reg:SI
11))
6343 (clobber (reg:SI
12))
6344 (clobber (match_scratch:SI
5 "=q"))]
6345 "TARGET_STRING && TARGET_POWER
6346 && INTVAL (operands[
2]) >
16 && INTVAL (operands[
2]) <=
24
6347 && (REGNO (operands[
0]) <
7 || REGNO (operands[
0]) >
12)
6348 && (REGNO (operands[
1]) <
7 || REGNO (operands[
1]) >
12)
6349 && REGNO (operands[
4]) ==
7"
6350 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6351 [(set_attr "type" "load")
6352 (set_attr "length" "
8")])
6355 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6356 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6357 (use (match_operand:SI
2 "immediate_operand" "i"))
6358 (use (match_operand:SI
3 "immediate_operand" "i"))
6359 (clobber (match_operand:SI
4 "register_operand" "=r"))
6360 (clobber (reg:SI
8))
6361 (clobber (reg:SI
9))
6362 (clobber (reg:SI
10))
6363 (clobber (reg:SI
11))
6364 (clobber (reg:SI
12))
6365 (clobber (match_scratch:SI
5 "X"))]
6366 "TARGET_STRING && !TARGET_POWER
6367 && INTVAL (operands[
2]) >
16 && INTVAL (operands[
2]) <=
32
6368 && (REGNO (operands[
0]) <
7 || REGNO (operands[
0]) >
12)
6369 && (REGNO (operands[
1]) <
7 || REGNO (operands[
1]) >
12)
6370 && REGNO (operands[
4]) ==
7"
6371 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6372 [(set_attr "type" "load")
6373 (set_attr "length" "
8")])
6375 ;; Move up to
16 bytes at a time, using
4 fixed registers to avoid spill problems
6377 (define_expand "movstrsi_4reg"
6378 [(parallel [(set (match_operand
0 "" "")
6379 (match_operand
1 "" ""))
6380 (use (match_operand
2 "" ""))
6381 (use (match_operand
3 "" ""))
6382 (clobber (reg:SI
9))
6383 (clobber (reg:SI
10))
6384 (clobber (reg:SI
11))
6385 (clobber (reg:SI
12))
6386 (clobber (match_scratch:SI
4 ""))])]
6391 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6392 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6393 (use (match_operand:SI
2 "immediate_operand" "i"))
6394 (use (match_operand:SI
3 "immediate_operand" "i"))
6395 (clobber (match_operand:SI
4 "register_operand" "=r"))
6396 (clobber (reg:SI
10))
6397 (clobber (reg:SI
11))
6398 (clobber (reg:SI
12))
6399 (clobber (match_scratch:SI
5 "=q"))]
6400 "TARGET_STRING && TARGET_POWER
6401 && INTVAL (operands[
2]) >
8 && INTVAL (operands[
2]) <=
16
6402 && (REGNO (operands[
0]) <
9 || REGNO (operands[
0]) >
12)
6403 && (REGNO (operands[
1]) <
9 || REGNO (operands[
1]) >
12)
6404 && REGNO (operands[
4]) ==
9"
6405 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6406 [(set_attr "type" "load")
6407 (set_attr "length" "
8")])
6410 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6411 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6412 (use (match_operand:SI
2 "immediate_operand" "i"))
6413 (use (match_operand:SI
3 "immediate_operand" "i"))
6414 (clobber (match_operand:SI
4 "register_operand" "=r"))
6415 (clobber (reg:SI
10))
6416 (clobber (reg:SI
11))
6417 (clobber (reg:SI
12))
6418 (clobber (match_scratch:SI
5 "X"))]
6419 "TARGET_STRING && !TARGET_POWER
6420 && INTVAL (operands[
2]) >
8 && INTVAL (operands[
2]) <=
16
6421 && (REGNO (operands[
0]) <
9 || REGNO (operands[
0]) >
12)
6422 && (REGNO (operands[
1]) <
9 || REGNO (operands[
1]) >
12)
6423 && REGNO (operands[
4]) ==
9"
6424 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6425 [(set_attr "type" "load")
6426 (set_attr "length" "
8")])
6428 ;; Move up to
8 bytes at a time.
6429 (define_expand "movstrsi_2reg"
6430 [(parallel [(set (match_operand
0 "" "")
6431 (match_operand
1 "" ""))
6432 (use (match_operand
2 "" ""))
6433 (use (match_operand
3 "" ""))
6434 (clobber (match_scratch:DI
4 ""))
6435 (clobber (match_scratch:SI
5 ""))])]
6436 "TARGET_STRING && !TARGET_64BIT"
6440 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6441 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6442 (use (match_operand:SI
2 "immediate_operand" "i"))
6443 (use (match_operand:SI
3 "immediate_operand" "i"))
6444 (clobber (match_scratch:DI
4 "=&r"))
6445 (clobber (match_scratch:SI
5 "=q"))]
6446 "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
6447 && INTVAL (operands[
2]) >
4 && INTVAL (operands[
2]) <=
8"
6448 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6449 [(set_attr "type" "load")
6450 (set_attr "length" "
8")])
6453 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6454 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6455 (use (match_operand:SI
2 "immediate_operand" "i"))
6456 (use (match_operand:SI
3 "immediate_operand" "i"))
6457 (clobber (match_scratch:DI
4 "=&r"))
6458 (clobber (match_scratch:SI
5 "X"))]
6459 "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
6460 && INTVAL (operands[
2]) >
4 && INTVAL (operands[
2]) <=
8"
6461 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6462 [(set_attr "type" "load")
6463 (set_attr "length" "
8")])
6465 ;; Move up to
4 bytes at a time.
6466 (define_expand "movstrsi_1reg"
6467 [(parallel [(set (match_operand
0 "" "")
6468 (match_operand
1 "" ""))
6469 (use (match_operand
2 "" ""))
6470 (use (match_operand
3 "" ""))
6471 (clobber (match_scratch:SI
4 ""))
6472 (clobber (match_scratch:SI
5 ""))])]
6477 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6478 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6479 (use (match_operand:SI
2 "immediate_operand" "i"))
6480 (use (match_operand:SI
3 "immediate_operand" "i"))
6481 (clobber (match_scratch:SI
4 "=&r"))
6482 (clobber (match_scratch:SI
5 "=q"))]
6483 "TARGET_STRING && TARGET_POWER
6484 && INTVAL (operands[
2]) >
0 && INTVAL (operands[
2]) <=
4"
6485 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6486 [(set_attr "type" "load")
6487 (set_attr "length" "
8")])
6490 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6491 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6492 (use (match_operand:SI
2 "immediate_operand" "i"))
6493 (use (match_operand:SI
3 "immediate_operand" "i"))
6494 (clobber (match_scratch:SI
4 "=&r"))
6495 (clobber (match_scratch:SI
5 "X"))]
6496 "TARGET_STRING && !TARGET_POWER
6497 && INTVAL (operands[
2]) >
0 && INTVAL (operands[
2]) <=
4"
6498 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6499 [(set_attr "type" "load")
6500 (set_attr "length" "
8")])
6503 ;; Define insns that do load or store with update. Some of these we can
6504 ;; get by using pre-decrement or pre-increment, but the hardware can also
6505 ;; do cases where the increment is not the size of the object.
6507 ;; In all these cases, we use operands
0 and
1 for the register being
6508 ;; incremented because those are the operands that local-alloc will
6509 ;; tie and these are the pair most likely to be tieable (and the ones
6510 ;; that will benefit the most).
6513 [(set (match_operand:DI
3 "gpc_reg_operand" "=r,r")
6514 (mem:DI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0,
0")
6515 (match_operand:DI
2 "reg_or_short_operand" "r,I"))))
6516 (set (match_operand:DI
0 "gpc_reg_operand" "=b,b")
6517 (plus:DI (match_dup
1) (match_dup
2)))]
6522 [(set_attr "type" "load")])
6525 [(set (match_operand:DI
3 "gpc_reg_operand" "=r")
6527 (mem:SI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0")
6528 (match_operand:DI
2 "gpc_reg_operand" "r")))))
6529 (set (match_operand:DI
0 "gpc_reg_operand" "=b")
6530 (plus:DI (match_dup
1) (match_dup
2)))]
6533 [(set_attr "type" "load")])
6535 (define_insn "movdi_update"
6536 [(set (mem:DI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0,
0")
6537 (match_operand:DI
2 "reg_or_short_operand" "r,I")))
6538 (match_operand:DI
3 "gpc_reg_operand" "r,r"))
6539 (set (match_operand:DI
0 "gpc_reg_operand" "=b,b")
6540 (plus:DI (match_dup
1) (match_dup
2)))]
6545 [(set_attr "type" "store")])
6548 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6549 (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6550 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6551 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6552 (plus:SI (match_dup
1) (match_dup
2)))]
6555 {lux|lwzux} %
3,%
0,%
2
6556 {lu|lwzu} %
3,%
2(%
0)"
6557 [(set_attr "type" "load")])
6559 (define_insn "movsi_update"
6560 [(set (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6561 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6562 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
6563 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6564 (plus:SI (match_dup
1) (match_dup
2)))]
6567 {stux|stwux} %
3,%
0,%
2
6568 {stu|stwu} %
3,%
2(%
0)"
6569 [(set_attr "type" "store")])
6572 [(set (match_operand:HI
3 "gpc_reg_operand" "=r,r")
6573 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6574 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6575 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6576 (plus:SI (match_dup
1) (match_dup
2)))]
6581 [(set_attr "type" "load")])
6584 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6586 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6587 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
6588 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6589 (plus:SI (match_dup
1) (match_dup
2)))]
6594 [(set_attr "type" "load")])
6597 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6599 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6600 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
6601 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6602 (plus:SI (match_dup
1) (match_dup
2)))]
6607 [(set_attr "type" "load")])
6610 [(set (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6611 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6612 (match_operand:HI
3 "gpc_reg_operand" "r,r"))
6613 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6614 (plus:SI (match_dup
1) (match_dup
2)))]
6619 [(set_attr "type" "store")])
6622 [(set (match_operand:QI
3 "gpc_reg_operand" "=r,r")
6623 (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6624 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6625 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6626 (plus:SI (match_dup
1) (match_dup
2)))]
6631 [(set_attr "type" "load")])
6634 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6636 (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6637 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
6638 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6639 (plus:SI (match_dup
1) (match_dup
2)))]
6644 [(set_attr "type" "load")])
6647 [(set (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6648 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6649 (match_operand:QI
3 "gpc_reg_operand" "r,r"))
6650 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6651 (plus:SI (match_dup
1) (match_dup
2)))]
6656 [(set_attr "type" "store")])
6659 [(set (match_operand:SF
3 "gpc_reg_operand" "=f,f")
6660 (mem:SF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6661 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6662 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6663 (plus:SI (match_dup
1) (match_dup
2)))]
6668 [(set_attr "type" "fpload")])
6671 [(set (mem:SF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6672 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6673 (match_operand:SF
3 "gpc_reg_operand" "f,f"))
6674 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6675 (plus:SI (match_dup
1) (match_dup
2)))]
6680 [(set_attr "type" "fpstore")])
6683 [(set (match_operand:DF
3 "gpc_reg_operand" "=f,f")
6684 (mem:DF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6685 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6686 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6687 (plus:SI (match_dup
1) (match_dup
2)))]
6692 [(set_attr "type" "fpload")])
6695 [(set (mem:DF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6696 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6697 (match_operand:DF
3 "gpc_reg_operand" "f,f"))
6698 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6699 (plus:SI (match_dup
1) (match_dup
2)))]
6704 [(set_attr "type" "fpstore")])
6706 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
6709 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
6710 (match_operand:DF
1 "memory_operand" ""))
6711 (set (match_operand:DF
2 "gpc_reg_operand" "=f")
6712 (match_operand:DF
3 "memory_operand" ""))]
6714 && TARGET_HARD_FLOAT
6715 && registers_ok_for_quad_peep (operands[
0], operands[
2])
6716 && ! MEM_VOLATILE_P (operands[
1]) && ! MEM_VOLATILE_P (operands[
3])
6717 && addrs_ok_for_quad_peep (XEXP (operands[
1],
0), XEXP (operands[
3],
0))"
6721 [(set (match_operand:DF
0 "memory_operand" "")
6722 (match_operand:DF
1 "gpc_reg_operand" "f"))
6723 (set (match_operand:DF
2 "memory_operand" "")
6724 (match_operand:DF
3 "gpc_reg_operand" "f"))]
6726 && TARGET_HARD_FLOAT
6727 && registers_ok_for_quad_peep (operands[
1], operands[
3])
6728 && ! MEM_VOLATILE_P (operands[
0]) && ! MEM_VOLATILE_P (operands[
2])
6729 && addrs_ok_for_quad_peep (XEXP (operands[
0],
0), XEXP (operands[
2],
0))"
6732 ;; Next come insns related to the calling sequence.
6734 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
6735 ;; We move the back-chain and decrement the stack pointer.
6737 (define_expand "allocate_stack"
6739 (minus:SI (reg:SI
1) (match_operand:SI
0 "reg_or_short_operand" "")))]
6742 { rtx chain = gen_reg_rtx (Pmode);
6743 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
6746 emit_move_insn (chain, stack_bot);
6748 /* Under Windows NT, we need to add stack probes for large/variable allocations,
6749 so do it via a call to the external function alloca, instead of doing it
6751 if (DEFAULT_ABI == ABI_NT
6752 && (GET_CODE (operands[
0]) != CONST_INT || INTVAL (operands[
0]) >
4096))
6754 rtx tmp = gen_reg_rtx (SImode);
6755 emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode,
\"__allocate_stack
\"),
6756 tmp,
0, SImode,
1, operands[
0], Pmode);
6757 emit_insn (gen_set_sp (tmp));
6761 if (GET_CODE (operands[
0]) != CONST_INT
6762 || INTVAL (operands[
0]) < -
32767
6763 || INTVAL (operands[
0]) >
32768)
6765 neg_op0 = gen_reg_rtx (Pmode);
6767 emit_insn (gen_negsi2 (neg_op0, operands[
0]));
6769 emit_insn (gen_negdi2 (neg_op0, operands[
0]));
6772 neg_op0 = GEN_INT (- INTVAL (operands[
0]));
6775 emit_insn (gen_movsi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
6777 emit_insn (gen_movdi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
6782 ;; Marker to indicate that the stack pointer was changed under NT in
6783 ;; ways not known to the compiler
6785 (define_insn "set_sp"
6787 (unspec [(match_operand:SI
0 "register_operand" "r")]
7))]
6790 [(set_attr "length" "
0")])
6792 ;; These patterns say how to save and restore the stack pointer. We need not
6793 ;; save the stack pointer at function level since we are careful to
6794 ;; preserve the backchain. At block level, we have to restore the backchain
6795 ;; when we restore the stack pointer.
6797 ;; For nonlocal gotos, we must save both the stack pointer and its
6798 ;; backchain and restore both. Note that in the nonlocal case, the
6799 ;; save area is a memory location.
6801 (define_expand "save_stack_function"
6802 [(use (const_int
0))]
6806 (define_expand "restore_stack_function"
6807 [(use (const_int
0))]
6811 (define_expand "restore_stack_block"
6812 [(set (match_dup
2) (mem:SI (match_operand:SI
0 "register_operand" "")))
6813 (set (match_dup
0) (match_operand:SI
1 "register_operand" ""))
6814 (set (mem:SI (match_dup
0)) (match_dup
2))]
6817 { operands[
2] = gen_reg_rtx (SImode); }")
6819 (define_expand "save_stack_nonlocal"
6820 [(match_operand:DI
0 "memory_operand" "")
6821 (match_operand:SI
1 "register_operand" "")]
6825 rtx temp = gen_reg_rtx (SImode);
6827 /* Copy the backchain to the first word, sp to the second. */
6828 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[
1]));
6829 emit_move_insn (operand_subword (operands[
0],
0,
0, DImode), temp);
6830 emit_move_insn (operand_subword (operands[
0],
1,
0, DImode), operands[
1]);
6834 (define_expand "restore_stack_nonlocal"
6835 [(match_operand:SI
0 "register_operand" "")
6836 (match_operand:DI
1 "memory_operand" "")]
6840 rtx temp = gen_reg_rtx (SImode);
6842 /* Restore the backchain from the first word, sp from the second. */
6843 emit_move_insn (temp, operand_subword (operands[
1],
0,
0, DImode));
6844 emit_move_insn (operands[
0], operand_subword (operands[
1],
1,
0, DImode));
6845 emit_move_insn (gen_rtx (MEM, SImode, operands[
0]), temp);
6850 ;; A function pointer under AIX is a pointer to a data area whose first word
6851 ;; contains the actual address of the function, whose second word contains a
6852 ;; pointer to its TOC, and whose third word contains a value to place in the
6853 ;; static chain register (r11). Note that if we load the static chain, our
6854 ;; "trampoline" need not have any executable code.
6856 ;; operands[
0] is a register pointing to the
3 word descriptor (aka, the function address)
6857 ;; operands[
1] is the stack size to clean up
6858 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument (must be
0 for AIX)
6859 ;; operands[
3] is location to store the TOC
6860 ;; operands[
4] is the TOC register
6861 ;; operands[
5] is the static chain register
6863 ;; We do not break this into separate insns, so that the scheduler will not try
6864 ;; to move the load of the new TOC before any loads from the TOC.
6866 (define_insn "call_indirect_aix"
6867 [(call (mem:SI (match_operand:SI
0 "register_operand" "b"))
6868 (match_operand
1 "const_int_operand" "n"))
6869 (use (match_operand
2 "const_int_operand" "n"))
6870 (use (match_operand
3 "offsettable_addr_operand" "p"))
6871 (use (match_operand
4 "register_operand" "r"))
6872 (clobber (match_operand
5 "register_operand" "=r"))
6873 (clobber (match_scratch:SI
6 "=&r"))
6874 (clobber (match_scratch:SI
7 "=l"))]
6875 "DEFAULT_ABI == ABI_AIX
6876 && (INTVAL (operands[
2]) == CALL_NORMAL || (INTVAL (operands[
2]) & CALL_LONG) !=
0)"
6877 "{st|stw} %
4,%a3\;{l|lwz} %
6,
0(%
0)\;{l|lwz} %
4,
4(%
0)\;mt%
7 %
6\;{l|lwz} %
5,
8(%
0)\;{brl|blrl}\;{l|lwz} %
4,%a3"
6878 [(set_attr "type" "load")
6879 (set_attr "length" "
28")])
6881 (define_insn "call_value_indirect_aix"
6882 [(set (match_operand
0 "register_operand" "fg")
6883 (call (mem:SI (match_operand:SI
1 "register_operand" "b"))
6884 (match_operand
2 "const_int_operand" "n")))
6885 (use (match_operand
3 "const_int_operand" "n"))
6886 (use (match_operand
4 "offsettable_addr_operand" "p"))
6887 (use (match_operand
5 "register_operand" "r"))
6888 (clobber (match_operand
6 "register_operand" "=r"))
6889 (clobber (match_scratch:SI
7 "=&r"))
6890 (clobber (match_scratch:SI
8 "=l"))]
6891 "DEFAULT_ABI == ABI_AIX
6892 && (INTVAL (operands[
3]) == CALL_NORMAL || (INTVAL (operands[
3]) & CALL_LONG) !=
0)"
6893 "{st|stw} %
5,%a4\;{l|lwz} %
7,
0(%
1)\;{l|lwz} %
5,
4(%
1);\;mt%
8 %
7\;{l|lwz} %
6,
8(%
1)\;{brl|blrl}\;{l|lwz} %
5,%a4"
6894 [(set_attr "type" "load")
6895 (set_attr "length" "
28")])
6897 ;; A function pointer undef NT is a pointer to a data area whose first word
6898 ;; contains the actual address of the function, whose second word contains a
6899 ;; pointer to its TOC. The static chain is not stored under NT, which means
6900 ;; that we need a trampoline.
6902 ;; operands[
0] is an SImode pseudo in which we place the address of the function.
6903 ;; operands[
1] is the stack size to clean up
6904 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument (must be
0 for NT)
6905 ;; operands[
3] is location to store the TOC
6906 ;; operands[
4] is the TOC register
6908 ;; We do not break this into separate insns, so that the scheduler will not try
6909 ;; to move the load of the new TOC before any loads from the TOC.
6911 (define_insn "call_indirect_nt"
6912 [(call (mem:SI (match_operand:SI
0 "register_operand" "b"))
6913 (match_operand
1 "const_int_operand" "n"))
6914 (use (match_operand
2 "const_int_operand" "n"))
6915 (use (match_operand
3 "offsettable_addr_operand" "p"))
6916 (use (match_operand
4 "register_operand" "r"))
6917 (clobber (match_scratch:SI
5 "=&r"))
6918 (clobber (match_scratch:SI
6 "=l"))]
6919 "DEFAULT_ABI == ABI_NT
6920 && (INTVAL (operands[
2]) == CALL_NORMAL || (INTVAL (operands[
2]) & CALL_LONG) !=
0)"
6921 "{st|stw} %
4,%a3\;{l|lwz} %
5,
0(%
0)\;{l|lwz} %
4,
4(%
0)\;mt%
6 %
5\;{brl|blrl}\;{l|lwz} %
4,%a3"
6922 [(set_attr "type" "load")
6923 (set_attr "length" "
24")])
6925 (define_insn "call_value_indirect_nt"
6926 [(set (match_operand
0 "register_operand" "fg")
6927 (call (mem:SI (match_operand:SI
1 "register_operand" "b"))
6928 (match_operand
2 "const_int_operand" "n")))
6929 (use (match_operand
3 "const_int_operand" "n"))
6930 (use (match_operand
4 "offsettable_addr_operand" "p"))
6931 (use (match_operand
5 "register_operand" "r"))
6932 (clobber (match_scratch:SI
6 "=&r"))
6933 (clobber (match_scratch:SI
7 "=l"))]
6934 "DEFAULT_ABI == ABI_NT
6935 && (INTVAL (operands[
3]) == CALL_NORMAL || (INTVAL (operands[
3]) & CALL_LONG) !=
0)"
6936 "{st|stw} %
5,%a4\;{l|lwz} %
6,
0(%
1)\;{l|lwz} %
5,
4(%
1)\;mt%
7 %
6\;{brl|blrl}\;{l|lwz} %
5,%a4"
6937 [(set_attr "type" "load")
6938 (set_attr "length" "
24")])
6940 ;; A function pointer under System V is just a normal pointer
6941 ;; operands[
0] is the function pointer
6942 ;; operands[
1] is the stack size to clean up
6943 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
6945 (define_insn "call_indirect_sysv"
6946 [(call (mem:SI (match_operand:SI
0 "register_operand" "l,l"))
6947 (match_operand
1 "const_int_operand" "n,n"))
6948 (use (match_operand
2 "const_int_operand" "O,n"))
6949 (clobber (match_scratch:SI
3 "=l,l"))]
6950 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
6953 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
6954 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6956 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
6957 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6959 return
\"{brl|blrl}
\";
6961 [(set_attr "type" "jmpreg")
6962 (set_attr "length" "
4,
8")])
6964 (define_insn "call_value_indirect_sysv"
6965 [(set (match_operand
0 "register_operand" "=fg,fg")
6966 (call (mem:SI (match_operand:SI
1 "register_operand" "l,l"))
6967 (match_operand
2 "const_int_operand" "n,n")))
6968 (use (match_operand
3 "const_int_operand" "O,n"))
6969 (clobber (match_scratch:SI
4 "=l,l"))]
6970 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
6973 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
6974 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6976 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
6977 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6979 return
\"{brl|blrl}
\";
6981 [(set_attr "type" "jmpreg")
6982 (set_attr "length" "
4,
8")])
6984 ;; Now the definitions for the call and call_value insns
6985 (define_expand "call"
6986 [(parallel [(call (mem:SI (match_operand:SI
0 "address_operand" ""))
6987 (match_operand
1 "" ""))
6988 (use (match_operand
2 "" ""))
6989 (clobber (scratch:SI))])]
6993 if (GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != CONST_INT)
6996 operands[
0] = XEXP (operands[
0],
0);
6998 /* Convert NT DLL imports into an indirect call. */
6999 if (GET_CODE (operands[
0]) == SYMBOL_REF
7000 && (INTVAL (operands[
2]) & CALL_NT_DLLIMPORT) !=
0)
7002 operands[
0] = rs6000_dll_import_ref (operands[
0]);
7003 operands[
2] = GEN_INT ((int)CALL_NORMAL);
7006 if (GET_CODE (operands[
0]) != SYMBOL_REF
7007 || (INTVAL (operands[
2]) & CALL_LONG) !=
0)
7009 if (INTVAL (operands[
2]) & CALL_LONG)
7010 operands[
0] = rs6000_longcall_ref (operands[
0]);
7012 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
7013 emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[
0]),
7014 operands[
1], operands[
2]));
7017 rtx toc_reg = gen_rtx (REG, Pmode,
2);
7018 rtx toc_addr = RS6000_SAVE_TOC;
7020 if (DEFAULT_ABI == ABI_AIX)
7022 /* AIX function pointers are really pointers to a three word area */
7023 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
7024 emit_call_insn (gen_call_indirect_aix (force_reg (Pmode, operands[
0]),
7025 operands[
1], operands[
2],
7026 toc_addr, toc_reg, static_chain));
7028 else if (DEFAULT_ABI == ABI_NT)
7030 /* NT function pointers are really pointers to a two word area */
7031 rs6000_save_toc_p =
1;
7032 emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[
0]),
7033 operands[
1], operands[
2],
7034 toc_addr, toc_reg));
7043 (define_expand "call_value"
7044 [(parallel [(set (match_operand
0 "" "")
7045 (call (mem:SI (match_operand:SI
1 "address_operand" ""))
7046 (match_operand
2 "" "")))
7047 (use (match_operand
3 "" ""))
7048 (clobber (scratch:SI))])]
7052 if (GET_CODE (operands[
1]) != MEM || GET_CODE (operands[
2]) != CONST_INT)
7055 operands[
1] = XEXP (operands[
1],
0);
7057 /* Convert NT DLL imports into an indirect call. */
7058 if (GET_CODE (operands[
1]) == SYMBOL_REF
7059 && (INTVAL (operands[
3]) & CALL_NT_DLLIMPORT) !=
0)
7061 operands[
1] = rs6000_dll_import_ref (operands[
1]);
7062 operands[
3] = GEN_INT ((int)CALL_NORMAL);
7065 if (GET_CODE (operands[
1]) != SYMBOL_REF
7066 || (INTVAL (operands[
3]) & CALL_LONG) !=
0)
7068 if (INTVAL (operands[
2]) & CALL_LONG)
7069 operands[
1] = rs6000_longcall_ref (operands[
1]);
7071 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
7072 emit_call_insn (gen_call_value_indirect_sysv (operands[
0], operands[
1],
7073 operands[
2], operands[
3]));
7076 rtx toc_reg = gen_rtx (REG, Pmode,
2);
7077 rtx toc_addr = RS6000_SAVE_TOC;
7079 if (DEFAULT_ABI == ABI_AIX)
7081 /* AIX function pointers are really pointers to a three word area */
7082 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
7083 emit_call_insn (gen_call_value_indirect_aix (operands[
0],
7084 force_reg (Pmode, operands[
1]),
7085 operands[
2], operands[
3],
7086 toc_addr, toc_reg, static_chain));
7088 else if (DEFAULT_ABI == ABI_NT)
7090 /* NT function pointers are really pointers to a two word area */
7091 rs6000_save_toc_p =
1;
7092 emit_call_insn (gen_call_value_indirect_nt (operands[
0],
7093 force_reg (Pmode, operands[
1]),
7094 operands[
2], operands[
3],
7095 toc_addr, toc_reg));
7104 ;; Call to function in current module. No TOC pointer reload needed.
7105 ;; Operand2 is non-zero if we are using the V
.4 calling sequence and
7106 ;; either the function was not prototyped, or it was prototyped as a
7107 ;; variable argument function. It is >
0 if FP registers were passed
7108 ;; and <
0 if they were not.
7111 [(call (mem:SI (match_operand:SI
0 "current_file_function_operand" "s,s"))
7112 (match_operand
1 "" "g,g"))
7113 (use (match_operand:SI
2 "immediate_operand" "O,n"))
7114 (clobber (match_scratch:SI
3 "=l,l"))]
7115 "(INTVAL (operands[
2]) & CALL_LONG) ==
0"
7118 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
7119 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7121 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
7122 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7126 [(set_attr "type" "branch")
7127 (set_attr "length" "
4,
8")])
7129 ;; Call to function which may be in another module. Restore the TOC
7130 ;; pointer (r2) after the call unless this is System V.
7131 ;; Operand2 is non-zero if we are using the V
.4 calling sequence and
7132 ;; either the function was not prototyped, or it was prototyped as a
7133 ;; variable argument function. It is >
0 if FP registers were passed
7134 ;; and <
0 if they were not.
7137 [(call (mem:SI (match_operand:SI
0 "call_operand" "s,s"))
7138 (match_operand
1 "" "fg,fg"))
7139 (use (match_operand:SI
2 "immediate_operand" "O,n"))
7140 (clobber (match_scratch:SI
3 "=l,l"))]
7141 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7142 && (INTVAL (operands[
2]) & CALL_LONG) ==
0"
7145 /* Indirect calls should go through call_indirect */
7146 if (GET_CODE (operands[
0]) == REG)
7149 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
7150 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7152 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
7153 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7155 return (TARGET_WINDOWS_NT) ?
\"bl %z0\;.znop %z0
\" :
\"bl %z0\;%.
\";
7157 [(set_attr "type" "branch")
7158 (set_attr "length" "
8,
12")])
7161 [(call (mem:SI (match_operand:SI
0 "call_operand" "s,s"))
7162 (match_operand
1 "" "fg,fg"))
7163 (use (match_operand:SI
2 "immediate_operand" "O,n"))
7164 (clobber (match_scratch:SI
3 "=l,l"))]
7165 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7166 && (INTVAL (operands[
2]) & CALL_LONG) ==
0"
7169 /* Indirect calls should go through call_indirect */
7170 if (GET_CODE (operands[
0]) == REG)
7173 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
7174 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7176 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
7177 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7181 [(set_attr "type" "branch")
7182 (set_attr "length" "
4,
8")])
7185 [(set (match_operand
0 "" "=fg,fg")
7186 (call (mem:SI (match_operand:SI
1 "current_file_function_operand" "s,s"))
7187 (match_operand
2 "" "g,g")))
7188 (use (match_operand:SI
3 "immediate_operand" "O,n"))
7189 (clobber (match_scratch:SI
4 "=l,l"))]
7190 "(INTVAL (operands[
3]) & CALL_LONG) ==
0"
7193 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
7194 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7196 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
7197 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7201 [(set_attr "type" "branch")
7202 (set_attr "length" "
4,
8")])
7205 [(set (match_operand
0 "" "=fg,fg")
7206 (call (mem:SI (match_operand:SI
1 "call_operand" "s,s"))
7207 (match_operand
2 "" "fg,fg")))
7208 (use (match_operand:SI
3 "immediate_operand" "O,n"))
7209 (clobber (match_scratch:SI
4 "=l,l"))]
7210 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
7211 && (INTVAL (operands[
3]) & CALL_LONG) ==
0"
7214 /* This should be handled by call_value_indirect */
7215 if (GET_CODE (operands[
1]) == REG)
7218 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
7219 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7221 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
7222 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7224 return (TARGET_WINDOWS_NT) ?
\"bl %z1\;.znop %z1
\" :
\"bl %z1\;%.
\";
7226 [(set_attr "type" "branch")
7227 (set_attr "length" "
8,
12")])
7230 [(set (match_operand
0 "" "=fg,fg")
7231 (call (mem:SI (match_operand:SI
1 "call_operand" "s,s"))
7232 (match_operand
2 "" "fg,fg")))
7233 (use (match_operand:SI
3 "immediate_operand" "O,n"))
7234 (clobber (match_scratch:SI
4 "=l,l"))]
7235 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7236 && (INTVAL (operands[
3]) & CALL_LONG) ==
0"
7239 /* This should be handled by call_value_indirect */
7240 if (GET_CODE (operands[
1]) == REG)
7243 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
7244 output_asm_insn (
\"crxor
6,
6,
6\", operands);
7246 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
7247 output_asm_insn (
\"creqv
6,
6,
6\", operands);
7251 [(set_attr "type" "branch")
7252 (set_attr "length" "
4,
8")])
7254 ;; Call subroutine returning any type.
7255 (define_expand "untyped_call"
7256 [(parallel [(call (match_operand
0 "" "")
7258 (match_operand
1 "" "")
7259 (match_operand
2 "" "")])]
7265 emit_call_insn (gen_call (operands[
0], const0_rtx, const0_rtx, const0_rtx));
7267 for (i =
0; i < XVECLEN (operands[
2],
0); i++)
7269 rtx set = XVECEXP (operands[
2],
0, i);
7270 emit_move_insn (SET_DEST (set), SET_SRC (set));
7273 /* The optimizer does not know that the call sets the function value
7274 registers we stored in the result block. We avoid problems by
7275 claiming that all hard registers are used and clobbered at this
7277 emit_insn (gen_blockage ());
7282 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7283 ;; all of memory. This blocks insns from being moved across this point.
7285 (define_insn "blockage"
7286 [(unspec_volatile [(const_int
0)]
0)]
7290 ;; Synchronize instructions/data caches for V
.4 trampolines
7291 ;; The extra memory_operand is to prevent the optimizer from
7292 ;; deleting insns with "no" effect.
7294 [(unspec [(match_operand
0 "memory_operand" "=m")
7295 (match_operand
1 "register_operand" "b")
7296 (match_operand
2 "register_operand" "r")]
3)]
7300 (define_insn "dcbst"
7301 [(unspec [(match_operand
0 "memory_operand" "=m")
7302 (match_operand
1 "register_operand" "b")
7303 (match_operand
2 "register_operand" "r")]
4)]
7308 [(unspec [(match_operand
0 "memory_operand" "=m")]
5)]
7312 (define_insn "isync"
7313 [(unspec [(match_operand
0 "memory_operand" "=m")]
6)]
7318 ;; V
.4 specific code to initialize the PIC register
7320 (define_insn "init_v4_pic"
7321 [(set (match_operand:SI
0 "register_operand" "=l")
7322 (unspec [(const_int
0)]
7))]
7323 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS"
7324 "bl _GLOBAL_OFFSET_TABLE_-
4"
7325 [(set_attr "type" "branch")])
7328 ;; Compare insns are next. Note that the RS/
6000 has two types of compares,
7329 ;; signed & unsigned, and one type of branch.
7331 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
7332 ;; insns, and branches. We store the operands of compares until we see
7334 (define_expand "cmpsi"
7336 (compare (match_operand:SI
0 "gpc_reg_operand" "")
7337 (match_operand:SI
1 "reg_or_short_operand" "")))]
7341 /* Take care of the possibility that operands[
1] might be negative but
7342 this might be a logical operation. That insn doesn't exist. */
7343 if (GET_CODE (operands[
1]) == CONST_INT
7344 && INTVAL (operands[
1]) <
0)
7345 operands[
1] = force_reg (SImode, operands[
1]);
7347 rs6000_compare_op0 = operands[
0];
7348 rs6000_compare_op1 = operands[
1];
7349 rs6000_compare_fp_p =
0;
7353 (define_expand "cmpdi"
7355 (compare (match_operand:DI
0 "gpc_reg_operand" "")
7356 (match_operand:DI
1 "reg_or_short_operand" "")))]
7360 /* Take care of the possibility that operands[
1] might be negative but
7361 this might be a logical operation. That insn doesn't exist. */
7362 if (GET_CODE (operands[
1]) == CONST_INT
7363 && INTVAL (operands[
1]) <
0)
7364 operands[
1] = force_reg (DImode, operands[
1]);
7366 rs6000_compare_op0 = operands[
0];
7367 rs6000_compare_op1 = operands[
1];
7368 rs6000_compare_fp_p =
0;
7372 (define_expand "cmpsf"
7373 [(set (cc0) (compare (match_operand:SF
0 "gpc_reg_operand" "")
7374 (match_operand:SF
1 "gpc_reg_operand" "")))]
7378 rs6000_compare_op0 = operands[
0];
7379 rs6000_compare_op1 = operands[
1];
7380 rs6000_compare_fp_p =
1;
7384 (define_expand "cmpdf"
7385 [(set (cc0) (compare (match_operand:DF
0 "gpc_reg_operand" "")
7386 (match_operand:DF
1 "gpc_reg_operand" "")))]
7390 rs6000_compare_op0 = operands[
0];
7391 rs6000_compare_op1 = operands[
1];
7392 rs6000_compare_fp_p =
1;
7396 (define_expand "beq"
7397 [(set (match_dup
2) (match_dup
1))
7399 (if_then_else (eq (match_dup
2)
7401 (label_ref (match_operand
0 "" ""))
7405 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7406 operands[
1] = gen_rtx (COMPARE, mode,
7407 rs6000_compare_op0, rs6000_compare_op1);
7408 operands[
2] = gen_reg_rtx (mode);
7411 (define_expand "bne"
7412 [(set (match_dup
2) (match_dup
1))
7414 (if_then_else (ne (match_dup
2)
7416 (label_ref (match_operand
0 "" ""))
7420 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7421 operands[
1] = gen_rtx (COMPARE, mode,
7422 rs6000_compare_op0, rs6000_compare_op1);
7423 operands[
2] = gen_reg_rtx (mode);
7426 (define_expand "blt"
7427 [(set (match_dup
2) (match_dup
1))
7429 (if_then_else (lt (match_dup
2)
7431 (label_ref (match_operand
0 "" ""))
7435 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7436 operands[
1] = gen_rtx (COMPARE, mode,
7437 rs6000_compare_op0, rs6000_compare_op1);
7438 operands[
2] = gen_reg_rtx (mode);
7441 (define_expand "bgt"
7442 [(set (match_dup
2) (match_dup
1))
7444 (if_then_else (gt (match_dup
2)
7446 (label_ref (match_operand
0 "" ""))
7450 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7451 operands[
1] = gen_rtx (COMPARE, mode,
7452 rs6000_compare_op0, rs6000_compare_op1);
7453 operands[
2] = gen_reg_rtx (mode);
7456 (define_expand "ble"
7457 [(set (match_dup
2) (match_dup
1))
7459 (if_then_else (le (match_dup
2)
7461 (label_ref (match_operand
0 "" ""))
7465 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7466 operands[
1] = gen_rtx (COMPARE, mode,
7467 rs6000_compare_op0, rs6000_compare_op1);
7468 operands[
2] = gen_reg_rtx (mode);
7471 (define_expand "bge"
7472 [(set (match_dup
2) (match_dup
1))
7474 (if_then_else (ge (match_dup
2)
7476 (label_ref (match_operand
0 "" ""))
7480 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7481 operands[
1] = gen_rtx (COMPARE, mode,
7482 rs6000_compare_op0, rs6000_compare_op1);
7483 operands[
2] = gen_reg_rtx (mode);
7486 (define_expand "bgtu"
7487 [(set (match_dup
2) (match_dup
1))
7489 (if_then_else (gtu (match_dup
2)
7491 (label_ref (match_operand
0 "" ""))
7495 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7496 rs6000_compare_op0, rs6000_compare_op1);
7497 operands[
2] = gen_reg_rtx (CCUNSmode);
7500 (define_expand "bltu"
7501 [(set (match_dup
2) (match_dup
1))
7503 (if_then_else (ltu (match_dup
2)
7505 (label_ref (match_operand
0 "" ""))
7509 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7510 rs6000_compare_op0, rs6000_compare_op1);
7511 operands[
2] = gen_reg_rtx (CCUNSmode);
7514 (define_expand "bgeu"
7515 [(set (match_dup
2) (match_dup
1))
7517 (if_then_else (geu (match_dup
2)
7519 (label_ref (match_operand
0 "" ""))
7523 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7524 rs6000_compare_op0, rs6000_compare_op1);
7525 operands[
2] = gen_reg_rtx (CCUNSmode);
7528 (define_expand "bleu"
7529 [(set (match_dup
2) (match_dup
1))
7531 (if_then_else (leu (match_dup
2)
7533 (label_ref (match_operand
0 "" ""))
7537 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7538 rs6000_compare_op0, rs6000_compare_op1);
7539 operands[
2] = gen_reg_rtx (CCUNSmode);
7542 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
7543 ;; For SEQ, likewise, except that comparisons with zero should be done
7544 ;; with an scc insns. However, due to the order that combine see the
7545 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
7546 ;; the cases we don't want to handle.
7547 (define_expand "seq"
7548 [(set (match_dup
2) (match_dup
1))
7549 (set (match_operand:SI
0 "gpc_reg_operand" "")
7550 (eq:SI (match_dup
2) (const_int
0)))]
7553 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7554 operands[
1] = gen_rtx (COMPARE, mode,
7555 rs6000_compare_op0, rs6000_compare_op1);
7556 operands[
2] = gen_reg_rtx (mode);
7559 (define_expand "sne"
7560 [(set (match_dup
2) (match_dup
1))
7561 (set (match_operand:SI
0 "gpc_reg_operand" "")
7562 (ne:SI (match_dup
2) (const_int
0)))]
7565 { if (! rs6000_compare_fp_p)
7568 operands[
1] = gen_rtx (COMPARE, CCFPmode,
7569 rs6000_compare_op0, rs6000_compare_op1);
7570 operands[
2] = gen_reg_rtx (CCFPmode);
7573 ;; A >
0 is best done using the portable sequence, so fail in that case.
7574 (define_expand "sgt"
7575 [(set (match_dup
2) (match_dup
1))
7576 (set (match_operand:SI
0 "gpc_reg_operand" "")
7577 (gt:SI (match_dup
2) (const_int
0)))]
7580 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7582 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7585 operands[
1] = gen_rtx (COMPARE, mode,
7586 rs6000_compare_op0, rs6000_compare_op1);
7587 operands[
2] = gen_reg_rtx (mode);
7590 ;; A <
0 is best done in the portable way for A an integer.
7591 (define_expand "slt"
7592 [(set (match_dup
2) (match_dup
1))
7593 (set (match_operand:SI
0 "gpc_reg_operand" "")
7594 (lt:SI (match_dup
2) (const_int
0)))]
7597 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7599 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7602 operands[
1] = gen_rtx (COMPARE, mode,
7603 rs6000_compare_op0, rs6000_compare_op1);
7604 operands[
2] = gen_reg_rtx (mode);
7607 (define_expand "sge"
7608 [(set (match_dup
2) (match_dup
1))
7609 (set (match_operand:SI
0 "gpc_reg_operand" "")
7610 (ge:SI (match_dup
2) (const_int
0)))]
7613 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7614 operands[
1] = gen_rtx (COMPARE, mode,
7615 rs6000_compare_op0, rs6000_compare_op1);
7616 operands[
2] = gen_reg_rtx (mode);
7619 ;; A <=
0 is best done the portable way for A an integer.
7620 (define_expand "sle"
7621 [(set (match_dup
2) (match_dup
1))
7622 (set (match_operand:SI
0 "gpc_reg_operand" "")
7623 (le:SI (match_dup
2) (const_int
0)))]
7626 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7628 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7631 operands[
1] = gen_rtx (COMPARE, mode,
7632 rs6000_compare_op0, rs6000_compare_op1);
7633 operands[
2] = gen_reg_rtx (mode);
7636 (define_expand "sgtu"
7637 [(set (match_dup
2) (match_dup
1))
7638 (set (match_operand:SI
0 "gpc_reg_operand" "")
7639 (gtu:SI (match_dup
2) (const_int
0)))]
7642 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7643 rs6000_compare_op0, rs6000_compare_op1);
7644 operands[
2] = gen_reg_rtx (CCUNSmode);
7647 (define_expand "sltu"
7648 [(set (match_dup
2) (match_dup
1))
7649 (set (match_operand:SI
0 "gpc_reg_operand" "")
7650 (ltu:SI (match_dup
2) (const_int
0)))]
7653 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7654 rs6000_compare_op0, rs6000_compare_op1);
7655 operands[
2] = gen_reg_rtx (CCUNSmode);
7658 (define_expand "sgeu"
7659 [(set (match_dup
2) (match_dup
1))
7660 (set (match_operand:SI
0 "gpc_reg_operand" "")
7661 (geu:SI (match_dup
2) (const_int
0)))]
7664 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7665 rs6000_compare_op0, rs6000_compare_op1);
7666 operands[
2] = gen_reg_rtx (CCUNSmode);
7669 (define_expand "sleu"
7670 [(set (match_dup
2) (match_dup
1))
7671 (set (match_operand:SI
0 "gpc_reg_operand" "")
7672 (leu:SI (match_dup
2) (const_int
0)))]
7675 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7676 rs6000_compare_op0, rs6000_compare_op1);
7677 operands[
2] = gen_reg_rtx (CCUNSmode);
7680 ;; Here are the actual compare insns.
7682 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
7683 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
7684 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
7686 "{cmp%I2|cmpw%I2} %
0,%
1,%
2"
7687 [(set_attr "type" "compare")])
7690 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
7691 (compare:CC (match_operand:DI
1 "gpc_reg_operand" "r")
7692 (match_operand:DI
2 "reg_or_short_operand" "rI")))]
7695 [(set_attr "type" "compare")])
7697 ;; If we are comparing a register for equality with a large constant,
7698 ;; we can do this with an XOR followed by a compare. But we need a scratch
7699 ;; register for the result of the XOR.
7702 [(set (match_operand:CC
0 "cc_reg_operand" "")
7703 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "")
7704 (match_operand:SI
2 "non_short_cint_operand" "")))
7705 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
7706 "find_single_use (operands[
0], insn,
0)
7707 && (GET_CODE (*find_single_use (operands[
0], insn,
0)) == EQ
7708 || GET_CODE (*find_single_use (operands[
0], insn,
0)) == NE)"
7709 [(set (match_dup
3) (xor:SI (match_dup
1) (match_dup
4)))
7710 (set (match_dup
0) (compare:CC (match_dup
3) (match_dup
5)))]
7713 /* Get the constant we are comparing against, C, and see what it looks like
7714 sign-extended to
16 bits. Then see what constant could be XOR'ed
7715 with C to get the sign-extended value. */
7717 int c = INTVAL (operands[
2]);
7718 int sextc = (c <<
16) >>
16;
7719 int xorv = c ^ sextc;
7721 operands[
4] = gen_rtx (CONST_INT, VOIDmode, xorv);
7722 operands[
5] = gen_rtx (CONST_INT, VOIDmode, sextc);
7726 [(set (match_operand:CCUNS
0 "cc_reg_operand" "=y")
7727 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "r")
7728 (match_operand:SI
2 "reg_or_u_short_operand" "rI")))]
7730 "{cmpl%I2|cmplw%I2} %
0,%
1,%W2"
7731 [(set_attr "type" "compare")])
7734 [(set (match_operand:CCUNS
0 "cc_reg_operand" "=y")
7735 (compare:CCUNS (match_operand:DI
1 "gpc_reg_operand" "r")
7736 (match_operand:DI
2 "reg_or_u_short_operand" "rI")))]
7738 "cmpld%I2 %
0,%
1,%W2"
7739 [(set_attr "type" "compare")])
7741 ;; The following two insns don't exist as single insns, but if we provide
7742 ;; them, we can swap an add and compare, which will enable us to overlap more
7743 ;; of the required delay between a compare and branch. We generate code for
7744 ;; them by splitting.
7747 [(set (match_operand:CC
3 "cc_reg_operand" "=y")
7748 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
7749 (match_operand:SI
2 "short_cint_operand" "i")))
7750 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7751 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "i")))]
7754 [(set_attr "length" "
8")])
7757 [(set (match_operand:CCUNS
3 "cc_reg_operand" "=y")
7758 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "r")
7759 (match_operand:SI
2 "u_short_cint_operand" "i")))
7760 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7761 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "i")))]
7764 [(set_attr "length" "
8")])
7767 [(set (match_operand:CC
3 "cc_reg_operand" "")
7768 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "")
7769 (match_operand:SI
2 "short_cint_operand" "")))
7770 (set (match_operand:SI
0 "gpc_reg_operand" "")
7771 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "")))]
7773 [(set (match_dup
3) (compare:CC (match_dup
1) (match_dup
2)))
7774 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
4)))])
7777 [(set (match_operand:CCUNS
3 "cc_reg_operand" "")
7778 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "")
7779 (match_operand:SI
2 "u_short_cint_operand" "")))
7780 (set (match_operand:SI
0 "gpc_reg_operand" "")
7781 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "")))]
7783 [(set (match_dup
3) (compare:CCUNS (match_dup
1) (match_dup
2)))
7784 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
4)))])
7787 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
7788 (compare:CCFP (match_operand:SF
1 "gpc_reg_operand" "f")
7789 (match_operand:SF
2 "gpc_reg_operand" "f")))]
7792 [(set_attr "type" "fpcompare")])
7795 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
7796 (compare:CCFP (match_operand:DF
1 "gpc_reg_operand" "f")
7797 (match_operand:DF
2 "gpc_reg_operand" "f")))]
7800 [(set_attr "type" "fpcompare")])
7802 ;; Now we have the scc insns. We can do some combinations because of the
7803 ;; way the machine works.
7805 ;; Note that this is probably faster if we can put an insn between the
7806 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
7807 ;; cases the insns below which don't use an intermediate CR field will
7810 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7811 (match_operator:SI
1 "scc_comparison_operator"
7812 [(match_operand
2 "cc_reg_operand" "y")
7815 "%D1mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%J1,
1"
7816 [(set_attr "length" "
12")])
7819 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
7820 (compare:CC (match_operator:SI
1 "scc_comparison_operator"
7821 [(match_operand
2 "cc_reg_operand" "y")
7824 (set (match_operand:SI
3 "gpc_reg_operand" "=r")
7825 (match_op_dup
1 [(match_dup
2) (const_int
0)]))]
7827 "%D1mfcr %
3\;{rlinm.|rlwinm.} %
3,%
3,%J1,
1"
7828 [(set_attr "type" "delayed_compare")
7829 (set_attr "length" "
12")])
7832 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7833 (ashift:SI (match_operator:SI
1 "scc_comparison_operator"
7834 [(match_operand
2 "cc_reg_operand" "y")
7836 (match_operand:SI
3 "const_int_operand" "n")))]
7840 int is_bit = ccr_bit (operands[
1],
1);
7841 int put_bit =
31 - (INTVAL (operands[
3]) &
31);
7844 if (is_bit >= put_bit)
7845 count = is_bit - put_bit;
7847 count =
32 - (put_bit - is_bit);
7849 operands[
4] = gen_rtx (CONST_INT, VOIDmode, count);
7850 operands[
5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
7852 return
\"%D1mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%
4,%
5,%
5\";
7854 [(set_attr "length" "
12")])
7857 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
7859 (ashift:SI (match_operator:SI
1 "scc_comparison_operator"
7860 [(match_operand
2 "cc_reg_operand" "y")
7862 (match_operand:SI
3 "const_int_operand" "n"))
7864 (set (match_operand:SI
4 "gpc_reg_operand" "=r")
7865 (ashift:SI (match_op_dup
1 [(match_dup
2) (const_int
0)])
7870 int is_bit = ccr_bit (operands[
1],
1);
7871 int put_bit =
31 - (INTVAL (operands[
3]) &
31);
7874 if (is_bit >= put_bit)
7875 count = is_bit - put_bit;
7877 count =
32 - (put_bit - is_bit);
7879 operands[
5] = gen_rtx (CONST_INT, VOIDmode, count);
7880 operands[
6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
7882 return
\"%D1mfcr %
4\;{rlinm.|rlwinm.} %
4,%
4,%
5,%
6,%
6\";
7884 [(set_attr "type" "delayed_compare")
7885 (set_attr "length" "
12")])
7887 ;; If we are comparing the result of two comparisons, this can be done
7888 ;; using creqv or crxor.
7891 [(set (match_operand:CCEQ
0 "cc_reg_operand" "=y")
7892 (compare:CCEQ (match_operator
1 "scc_comparison_operator"
7893 [(match_operand
2 "cc_reg_operand" "y")
7895 (match_operator
3 "scc_comparison_operator"
7896 [(match_operand
4 "cc_reg_operand" "y")
7898 "REGNO (operands[
2]) != REGNO (operands[
4])"
7901 enum rtx_code code1, code2;
7903 code1 = GET_CODE (operands[
1]);
7904 code2 = GET_CODE (operands[
3]);
7906 if ((code1 == EQ || code1 == LT || code1 == GT
7907 || code1 == LTU || code1 == GTU
7908 || (code1 != NE && GET_MODE (operands[
2]) == CCFPmode))
7910 (code2 == EQ || code2 == LT || code2 == GT
7911 || code2 == LTU || code2 == GTU
7912 || (code2 != NE && GET_MODE (operands[
4]) == CCFPmode)))
7913 return
\"%C1%C3crxor %E0,%j1,%j3
\";
7915 return
\"%C1%C3creqv %E0,%j1,%j3
\";
7917 [(set_attr "length" "
12")])
7919 ;; There is a
3 cycle delay between consecutive mfcr instructions
7920 ;; so it is useful to combine
2 scc instructions to use only one mfcr.
7923 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7924 (match_operator:SI
1 "scc_comparison_operator"
7925 [(match_operand
2 "cc_reg_operand" "y")
7927 (set (match_operand:SI
3 "gpc_reg_operand" "=r")
7928 (match_operator:SI
4 "scc_comparison_operator"
7929 [(match_operand
5 "cc_reg_operand" "y")
7931 "REGNO (operands[
2]) != REGNO (operands[
5])"
7932 "%D1%D4mfcr %
3\;{rlinm|rlwinm} %
0,%
3,%J1,
1\;{rlinm|rlwinm} %
3,%
3,%J4,
1"
7933 [(set_attr "length" "
20")])
7935 ;; There are some scc insns that can be done directly, without a compare.
7936 ;; These are faster because they don't involve the communications between
7937 ;; the FXU and branch units. In fact, we will be replacing all of the
7938 ;; integer scc insns here or in the portable methods in emit_store_flag.
7940 ;; Also support (neg (scc ..)) since that construct is used to replace
7941 ;; branches, (plus (scc ..) ..) since that construct is common and
7942 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
7943 ;; cases where it is no more expensive than (neg (scc ..)).
7945 ;; Have reload force a constant into a register for the simple insns that
7946 ;; otherwise won't accept constants. We do this because it is faster than
7947 ;; the cmp/mfcr sequence we would otherwise generate.
7950 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
7951 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
7952 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I")))
7953 (clobber (match_scratch:SI
3 "=r,&r,r,r,r"))]
7956 xor %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
7957 {sfi|subfic} %
3,%
1,
0\;{ae|adde} %
0,%
3,%
1
7958 {xoril|xori} %
0,%
1,%b2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
7959 {xoriu|xoris} %
0,%
1,%u2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
7960 {sfi|subfic} %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0"
7961 [(set_attr "length" "
12,
8,
12,
12,
12")])
7964 [(set (match_operand:CC
4 "cc_reg_operand" "=x,x,x,x,x")
7966 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
7967 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
7969 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
7970 (eq:SI (match_dup
1) (match_dup
2)))
7971 (clobber (match_scratch:SI
3 "=r,&r,r,r,r"))]
7974 xor %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
7975 {sfi|subfic} %
3,%
1,
0\;{ae.|adde.} %
0,%
3,%
1
7976 {xoril|xori} %
0,%
1,%b2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
7977 {xoriu|xoris} %
0,%
1,%u2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
7978 {sfi|subfic} %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0"
7979 [(set_attr "type" "compare")
7980 (set_attr "length" "
12,
8,
12,
12,
12")])
7982 ;; We have insns of the form shown by the first define_insn below. If
7983 ;; there is something inside the comparison operation, we must split it.
7985 [(set (match_operand:SI
0 "gpc_reg_operand" "")
7986 (plus:SI (match_operator
1 "comparison_operator"
7987 [(match_operand:SI
2 "" "")
7989 "reg_or_cint_operand" "")])
7990 (match_operand:SI
4 "gpc_reg_operand" "")))
7991 (clobber (match_operand:SI
5 "register_operand" ""))]
7992 "! gpc_reg_operand (operands[
2], SImode)"
7993 [(set (match_dup
5) (match_dup
2))
7994 (set (match_dup
2) (plus:SI (match_op_dup
1 [(match_dup
2) (match_dup
3)])
7998 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
7999 (plus:SI (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8000 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
8001 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r")))
8002 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
8005 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
8006 {sfi|subfic} %
4,%
1,
0\;{aze|addze} %
0,%
3
8007 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
8008 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
8009 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3"
8010 [(set_attr "length" "
12,
8,
12,
12,
12")])
8013 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x,x,x")
8016 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8017 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
8018 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r"))
8020 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
8023 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
8024 {sfi|subfic} %
4,%
1,
0\;{aze.|addze.} %
0,%
3
8025 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
8026 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
8027 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3"
8028 [(set_attr "type" "compare")
8029 (set_attr "length" "
12,
8,
12,
12,
12")])
8032 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x,x,x,x")
8035 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8036 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
8037 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r"))
8039 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
8040 (plus:SI (eq:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8041 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
8044 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
8045 {sfi|subfic} %
4,%
1,
0\;{aze.|addze.} %
4,%
3
8046 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
8047 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
8048 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3"
8049 [(set_attr "type" "compare")
8050 (set_attr "length" "
12,
8,
12,
12,
12")])
8053 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
8054 (neg:SI (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
8055 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))))]
8058 xor %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
8059 {ai|addic} %
0,%
1,-
1\;{sfe|subfe} %
0,%
0,%
0
8060 {xoril|xori} %
0,%
1,%b2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
8061 {xoriu|xoris} %
0,%
1,%u2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
8062 {sfi|subfic} %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0"
8063 [(set_attr "length" "
12,
8,
12,
12,
12")])
8065 ;; Simplify (ne X (const_int
0)) on the PowerPC. No need to on the Power,
8066 ;; since it nabs/sr is just as fast.
8068 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8069 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
8071 (clobber (match_scratch:SI
2 "=&r"))]
8073 "{ai|addic} %
2,%
1,-
1\;{sfe|subfe} %
0,%
2,%
1"
8074 [(set_attr "length" "
8")])
8076 ;; This is what (plus (ne X (const_int
0)) Y) looks like.
8078 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8079 (plus:SI (lshiftrt:SI
8080 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
8082 (match_operand:SI
2 "gpc_reg_operand" "r")))
8083 (clobber (match_scratch:SI
3 "=&r"))]
8085 "{ai|addic} %
3,%
1,-
1\;{aze|addze} %
0,%
2"
8086 [(set_attr "length" "
8")])
8089 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8091 (plus:SI (lshiftrt:SI
8092 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
8094 (match_operand:SI
2 "gpc_reg_operand" "r"))
8096 (clobber (match_scratch:SI
3 "=&r"))]
8098 "{ai|addic} %
3,%
1,-
1\;{aze.|addze.} %
3,%
2"
8099 [(set_attr "type" "compare")
8100 (set_attr "length" "
8")])
8103 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8105 (plus:SI (lshiftrt:SI
8106 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
8108 (match_operand:SI
2 "gpc_reg_operand" "r"))
8110 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8111 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup
1))) (const_int
31))
8113 (clobber (match_scratch:SI
3 "=&r"))]
8115 "{ai|addic} %
3,%
1,-
1\;{aze.|addze.} %
0,%
2"
8116 [(set_attr "type" "compare")
8117 (set_attr "length" "
8")])
8120 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8121 (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8122 (match_operand:SI
2 "reg_or_short_operand" "r,O")))
8123 (clobber (match_scratch:SI
3 "=r,X"))]
8126 doz %
3,%
2,%
1\;{sfi|subfic} %
0,%
3,
0\;{ae|adde} %
0,%
0,%
3
8127 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8128 [(set_attr "length" "
12")])
8131 [(set (match_operand:CC
4 "cc_reg_operand" "=x,x")
8133 (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8134 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
8136 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8137 (le:SI (match_dup
1) (match_dup
2)))
8138 (clobber (match_scratch:SI
3 "=r,X"))]
8141 doz %
3,%
2,%
1\;{sfi|subfic} %
0,%
3,
0\;{ae.|adde.} %
0,%
0,%
3
8142 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8143 [(set_attr "type" "compare,delayed_compare")
8144 (set_attr "length" "
12")])
8147 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8148 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8149 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
8150 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
8151 (clobber (match_scratch:SI
4 "=&r,&r"))]
8154 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
8155 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze|addze} %
0,%
3"
8156 [(set_attr "length" "
12")])
8159 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8161 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8162 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
8163 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8165 (clobber (match_scratch:SI
4 "=&r,&r"))]
8168 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
8169 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze.|addze.} %
4,%
3"
8170 [(set_attr "type" "compare")
8171 (set_attr "length" "
12")])
8174 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8176 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8177 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
8178 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8180 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8181 (plus:SI (le:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8182 (clobber (match_scratch:SI
4 "=&r,&r"))]
8185 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
8186 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze.|addze.} %
0,%
3"
8187 [(set_attr "type" "compare")
8188 (set_attr "length" "
12")])
8191 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8192 (neg:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8193 (match_operand:SI
2 "reg_or_short_operand" "r,O"))))]
8196 doz %
0,%
2,%
1\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
8197 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{srai|srawi} %
0,%
0,
31"
8198 [(set_attr "length" "
12")])
8201 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8202 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8203 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
8205 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0"
8206 [(set_attr "length" "
12")])
8209 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
8211 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8212 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8214 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8215 (leu:SI (match_dup
1) (match_dup
2)))]
8217 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0"
8218 [(set_attr "type" "compare")
8219 (set_attr "length" "
12")])
8222 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8223 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8224 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8225 (match_operand:SI
3 "gpc_reg_operand" "r")))
8226 (clobber (match_scratch:SI
4 "=&r"))]
8228 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze|addze} %
0,%
3"
8229 [(set_attr "length" "
8")])
8232 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8234 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8235 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8236 (match_operand:SI
3 "gpc_reg_operand" "r"))
8238 (clobber (match_scratch:SI
4 "=&r"))]
8240 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze.|addze.} %
4,%
3"
8241 [(set_attr "type" "compare")
8242 (set_attr "length" "
8")])
8245 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8247 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8248 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8249 (match_operand:SI
3 "gpc_reg_operand" "r"))
8251 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8252 (plus:SI (leu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8253 (clobber (match_scratch:SI
4 "=&r"))]
8255 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze.|addze.} %
0,%
3"
8256 [(set_attr "type" "compare")
8257 (set_attr "length" "
8")])
8260 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8261 (neg:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8262 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8264 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;nand %
0,%
0,%
0"
8265 [(set_attr "length" "
12")])
8268 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8270 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8271 (match_operand:SI
2 "reg_or_short_operand" "rI")))
8272 (match_operand:SI
3 "gpc_reg_operand" "r")))
8273 (clobber (match_scratch:SI
4 "=&r"))]
8275 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4"
8276 [(set_attr "length" "
12")])
8279 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8282 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8283 (match_operand:SI
2 "reg_or_short_operand" "rI")))
8284 (match_operand:SI
3 "gpc_reg_operand" "r"))
8286 (clobber (match_scratch:SI
4 "=&r"))]
8288 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4"
8289 [(set_attr "type" "compare")
8290 (set_attr "length" "
12")])
8293 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8296 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8297 (match_operand:SI
2 "reg_or_short_operand" "rI")))
8298 (match_operand:SI
3 "gpc_reg_operand" "r"))
8300 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8301 (and:SI (neg:SI (leu:SI (match_dup
1) (match_dup
2))) (match_dup
3)))
8302 (clobber (match_scratch:SI
4 "=&r"))]
8304 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4"
8305 [(set_attr "type" "compare")
8306 (set_attr "length" "
12")])
8309 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8310 (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8311 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
8313 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8314 [(set_attr "length" "
12")])
8317 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
8319 (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8320 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8322 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8323 (lt:SI (match_dup
1) (match_dup
2)))]
8325 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8326 [(set_attr "type" "delayed_compare")
8327 (set_attr "length" "
12")])
8330 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8331 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8332 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8333 (match_operand:SI
3 "gpc_reg_operand" "r")))
8334 (clobber (match_scratch:SI
4 "=&r"))]
8336 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze|addze} %
0,%
3"
8337 [(set_attr "length" "
12")])
8340 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8342 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8343 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8344 (match_operand:SI
3 "gpc_reg_operand" "r"))
8346 (clobber (match_scratch:SI
4 "=&r"))]
8348 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
4,%
3"
8349 [(set_attr "type" "compare")
8350 (set_attr "length" "
12")])
8353 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8355 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8356 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8357 (match_operand:SI
3 "gpc_reg_operand" "r"))
8359 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8360 (plus:SI (lt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8361 (clobber (match_scratch:SI
4 "=&r"))]
8363 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
0,%
3"
8364 [(set_attr "type" "compare")
8365 (set_attr "length" "
12")])
8368 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8369 (neg:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8370 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8372 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{srai|srawi} %
0,%
0,
31"
8373 [(set_attr "length" "
12")])
8376 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8377 (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8378 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))]
8381 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0
8382 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0"
8383 [(set_attr "length" "
12")])
8386 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
8388 (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8389 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8391 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8392 (ltu:SI (match_dup
1) (match_dup
2)))]
8395 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0
8396 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0"
8397 [(set_attr "type" "compare")
8398 (set_attr "length" "
12")])
8401 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
8402 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r,r")
8403 (match_operand:SI
2 "reg_or_neg_short_operand" "r,r,P,P"))
8404 (match_operand:SI
3 "reg_or_short_operand" "r,I,r,I")))
8405 (clobber (match_scratch:SI
4 "=&r,r,&r,r"))]
8408 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8409 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8410 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8411 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3"
8412 [(set_attr "length" "
12")])
8415 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8417 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8418 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8419 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8421 (clobber (match_scratch:SI
4 "=&r,&r"))]
8424 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
4,%
4,%
3
8425 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
4,%
4,%
3"
8426 [(set_attr "type" "compare")
8427 (set_attr "length" "
12")])
8430 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8432 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8433 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8434 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8436 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8437 (plus:SI (ltu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8438 (clobber (match_scratch:SI
4 "=&r,&r"))]
8441 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3
8442 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
8443 [(set_attr "type" "compare")
8444 (set_attr "length" "
12")])
8447 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8448 (neg:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8449 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))))]
8452 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0
8453 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0"
8454 [(set_attr "length" "
8")])
8457 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8458 (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8459 (match_operand:SI
2 "reg_or_short_operand" "rI")))
8460 (clobber (match_scratch:SI
3 "=r"))]
8462 "doz%I2 %
3,%
1,%
2\;{sfi|subfic} %
0,%
3,
0\;{ae|adde} %
0,%
0,%
3"
8463 [(set_attr "length" "
12")])
8466 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8468 (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8469 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8471 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8472 (ge:SI (match_dup
1) (match_dup
2)))
8473 (clobber (match_scratch:SI
3 "=r"))]
8475 "doz%I2 %
3,%
1,%
2\;{sfi|subfic} %
0,%
3,
0\;{ae.|adde.} %
0,%
0,%
3"
8476 [(set_attr "type" "compare")
8477 (set_attr "length" "
12")])
8480 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8481 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8482 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8483 (match_operand:SI
3 "gpc_reg_operand" "r")))
8484 (clobber (match_scratch:SI
4 "=&r"))]
8486 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3"
8487 [(set_attr "length" "
12")])
8490 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8492 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8493 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8494 (match_operand:SI
3 "gpc_reg_operand" "r"))
8496 (clobber (match_scratch:SI
4 "=&r"))]
8498 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3"
8499 [(set_attr "type" "compare")
8500 (set_attr "length" "
12")])
8503 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8505 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8506 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8507 (match_operand:SI
3 "gpc_reg_operand" "r"))
8509 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8510 (plus:SI (ge:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8511 (clobber (match_scratch:SI
4 "=&r"))]
8513 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3"
8514 [(set_attr "type" "compare")
8515 (set_attr "length" "
12")])
8518 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8519 (neg:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8520 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8522 "doz%I2 %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0"
8523 [(set_attr "length" "
12")])
8525 ;; This is (and (neg (ge X (const_int
0))) Y).
8527 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8530 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
8532 (match_operand:SI
2 "gpc_reg_operand" "r")))
8533 (clobber (match_scratch:SI
3 "=&r"))]
8535 "{srai|srawi} %
3,%
1,
31\;andc %
0,%
2,%
3"
8536 [(set_attr "length" "
8")])
8539 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8543 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
8545 (match_operand:SI
2 "gpc_reg_operand" "r"))
8547 (clobber (match_scratch:SI
3 "=&r"))]
8549 "{srai|srawi} %
3,%
1,
31\;andc. %
3,%
2,%
3"
8550 [(set_attr "type" "compare")
8551 (set_attr "length" "
8")])
8554 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8558 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
8560 (match_operand:SI
2 "gpc_reg_operand" "r"))
8562 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8563 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup
1))
8566 (clobber (match_scratch:SI
3 "=&r"))]
8568 "{srai|srawi} %
3,%
1,
31\;andc. %
0,%
2,%
3"
8569 [(set_attr "type" "compare")
8570 (set_attr "length" "
8")])
8573 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8574 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8575 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))]
8578 {sf|subfc} %
0,%
2,%
1\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0
8579 {ai|addic} %
0,%
1,%n2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0"
8580 [(set_attr "length" "
12")])
8583 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
8585 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8586 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8588 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8589 (geu:SI (match_dup
1) (match_dup
2)))]
8592 {sf|subfc} %
0,%
2,%
1\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0
8593 {ai|addic} %
0,%
1,%n2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0"
8594 [(set_attr "type" "compare")
8595 (set_attr "length" "
12")])
8598 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8599 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8600 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8601 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
8602 (clobber (match_scratch:SI
4 "=&r,&r"))]
8605 {sf|subfc} %
4,%
2,%
1\;{aze|addze} %
0,%
3
8606 {ai|addic} %
4,%
1,%n2\;{aze|addze} %
0,%
3"
8607 [(set_attr "length" "
8")])
8610 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8612 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8613 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8614 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8616 (clobber (match_scratch:SI
4 "=&r,&r"))]
8619 {sf|subfc} %
4,%
2,%
1\;{aze.|addze.} %
4,%
3
8620 {ai|addic} %
4,%
1,%n2\;{aze.|addze.} %
4,%
3"
8621 [(set_attr "type" "compare")
8622 (set_attr "length" "
8")])
8625 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8627 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8628 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8629 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8631 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8632 (plus:SI (geu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8633 (clobber (match_scratch:SI
4 "=&r,&r"))]
8636 {sf|subfc} %
4,%
2,%
1\;{aze.|addze.} %
0,%
3
8637 {ai|addic} %
4,%
1,%n2\;{aze.|addze.} %
4,%
3"
8638 [(set_attr "type" "compare")
8639 (set_attr "length" "
8")])
8642 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8643 (neg:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8644 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))]
8647 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;nand %
0,%
0,%
0
8648 {sfi|subfic} %
0,%
1,-
1\;{a%I2|add%I2c} %
0,%
0,%
2\;{sfe|subfe} %
0,%
0,%
0"
8649 [(set_attr "length" "
12")])
8652 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8654 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8655 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
8656 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
8657 (clobber (match_scratch:SI
4 "=&r,&r"))]
8660 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4
8661 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4"
8662 [(set_attr "length" "
12")])
8665 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8668 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8669 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
8670 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8672 (clobber (match_scratch:SI
4 "=&r,&r"))]
8675 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4
8676 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4"
8677 [(set_attr "type" "compare")
8678 (set_attr "length" "
12")])
8681 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8684 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8685 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
8686 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8688 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8689 (and:SI (neg:SI (geu:SI (match_dup
1) (match_dup
2))) (match_dup
3)))
8690 (clobber (match_scratch:SI
4 "=&r,&r"))]
8693 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4
8694 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4"
8695 [(set_attr "type" "compare")
8696 (set_attr "length" "
12")])
8699 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8700 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8703 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8704 [(set_attr "length" "
12")])
8707 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
8709 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8712 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8713 (gt:SI (match_dup
1) (const_int
0)))]
8715 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8716 [(set_attr "type" "delayed_compare")
8717 (set_attr "length" "
12")])
8720 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8721 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8722 (match_operand:SI
2 "reg_or_short_operand" "r")))]
8724 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8725 [(set_attr "length" "
12")])
8728 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
8730 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8731 (match_operand:SI
2 "reg_or_short_operand" "r"))
8733 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8734 (gt:SI (match_dup
1) (match_dup
2)))]
8736 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8737 [(set_attr "type" "delayed_compare")
8738 (set_attr "length" "
12")])
8741 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8742 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8744 (match_operand:SI
2 "gpc_reg_operand" "r")))
8745 (clobber (match_scratch:SI
3 "=&r"))]
8747 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze|addze} %
0,%
2"
8748 [(set_attr "length" "
12")])
8751 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8753 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8755 (match_operand:SI
2 "gpc_reg_operand" "r"))
8757 (clobber (match_scratch:SI
3 "=&r"))]
8759 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze.|addze.} %
0,%
2"
8760 [(set_attr "type" "compare")
8761 (set_attr "length" "
12")])
8764 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8766 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8768 (match_operand:SI
2 "gpc_reg_operand" "r"))
8770 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8771 (plus:SI (gt:SI (match_dup
1) (const_int
0)) (match_dup
2)))
8772 (clobber (match_scratch:SI
3 "=&r"))]
8774 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze.|addze.} %
3,%
2"
8775 [(set_attr "type" "compare")
8776 (set_attr "length" "
12")])
8779 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8780 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8781 (match_operand:SI
2 "reg_or_short_operand" "r"))
8782 (match_operand:SI
3 "gpc_reg_operand" "r")))
8783 (clobber (match_scratch:SI
4 "=&r"))]
8785 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze|addze} %
0,%
3"
8786 [(set_attr "length" "
12")])
8789 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8791 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8792 (match_operand:SI
2 "reg_or_short_operand" "r"))
8793 (match_operand:SI
3 "gpc_reg_operand" "r"))
8795 (clobber (match_scratch:SI
4 "=&r"))]
8797 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
4,%
3"
8798 [(set_attr "type" "compare")
8799 (set_attr "length" "
12")])
8802 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8804 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8805 (match_operand:SI
2 "reg_or_short_operand" "r"))
8806 (match_operand:SI
3 "gpc_reg_operand" "r"))
8808 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8809 (plus:SI (gt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8810 (clobber (match_scratch:SI
4 "=&r"))]
8812 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
0,%
3"
8813 [(set_attr "type" "compare")
8814 (set_attr "length" "
12")])
8817 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8818 (neg:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8821 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{srai|srawi} %
0,%
0,
31"
8822 [(set_attr "length" "
12")])
8825 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8826 (neg:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8827 (match_operand:SI
2 "reg_or_short_operand" "r"))))]
8829 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{srai|srawi} %
0,%
0,
31"
8830 [(set_attr "length" "
12")])
8833 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8834 (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8835 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
8837 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0"
8838 [(set_attr "length" "
12")])
8841 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
8843 (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8844 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8846 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8847 (gtu:SI (match_dup
1) (match_dup
2)))]
8849 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0"
8850 [(set_attr "type" "compare")
8851 (set_attr "length" "
12")])
8854 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
8855 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
8856 (match_operand:SI
2 "reg_or_short_operand" "I,r,rI"))
8857 (match_operand:SI
3 "reg_or_short_operand" "r,r,I")))
8858 (clobber (match_scratch:SI
4 "=&r,&r,&r"))]
8861 {ai|addic} %
4,%
1,%k2\;{aze|addze} %
0,%
3
8862 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8863 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3"
8864 [(set_attr "length" "
8,
12,
12")])
8867 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8869 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8870 (match_operand:SI
2 "reg_or_short_operand" "I,r"))
8871 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8873 (clobber (match_scratch:SI
4 "=&r,&r"))]
8876 {ai|addic} %
4,%
1,%k2\;{aze.|addze.} %
0,%
3
8877 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
8878 [(set_attr "type" "compare")
8879 (set_attr "length" "
8,
12")])
8882 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8884 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8885 (match_operand:SI
2 "reg_or_short_operand" "I,r"))
8886 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8888 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8889 (plus:SI (gtu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8890 (clobber (match_scratch:SI
4 "=&r,&r"))]
8893 {ai|addic} %
4,%
1,%k2\;{aze.|addze.} %
0,%
3
8894 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
8895 [(set_attr "type" "compare")
8896 (set_attr "length" "
8,
12")])
8899 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8900 (neg:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8901 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8903 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0"
8904 [(set_attr "length" "
8")])
8906 ;; Define both directions of branch and return. If we need a reload
8907 ;; register, we'd rather use CR0 since it is much easier to copy a
8908 ;; register CC value to there.
8912 (if_then_else (match_operator
1 "branch_comparison_operator"
8914 "cc_reg_operand" "x,?y")
8916 (label_ref (match_operand
0 "" ""))
8921 if (get_attr_length (insn) ==
8)
8922 return
\"%C1bc %t1,%j1,%l0
\";
8924 return
\"%C1bc %T1,%j1,%$+
8\;b %l0
\";
8927 [(set_attr "type" "branch")])
8931 (if_then_else (match_operator
0 "branch_comparison_operator"
8933 "cc_reg_operand" "x,?y")
8938 "{%C0bcr|%C0bclr} %t0,%j0"
8939 [(set_attr "type" "branch")
8940 (set_attr "length" "
8")])
8944 (if_then_else (match_operator
1 "branch_comparison_operator"
8946 "cc_reg_operand" "x,?y")
8949 (label_ref (match_operand
0 "" ""))))]
8953 if (get_attr_length (insn) ==
8)
8954 return
\"%C1bc %T1,%j1,%l0
\";
8956 return
\"%C1bc %t1,%j1,%$+
8\;b %l0
\";
8958 [(set_attr "type" "branch")])
8962 (if_then_else (match_operator
0 "branch_comparison_operator"
8964 "cc_reg_operand" "x,?y")
8969 "{%C0bcr|%C0bclr} %T0,%j0"
8970 [(set_attr "type" "branch")
8971 (set_attr "length" "
8")])
8973 ;; Unconditional branch and return.
8977 (label_ref (match_operand
0 "" "")))]
8980 [(set_attr "type" "branch")])
8982 (define_insn "return"
8986 [(set_attr "type" "jmpreg")])
8988 (define_insn "indirect_jump"
8989 [(set (pc) (match_operand:SI
0 "register_operand" "c,l"))]
8994 [(set_attr "type" "jmpreg")])
8997 [(set (pc) (match_operand:DI
0 "register_operand" "c,l"))]
9002 [(set_attr "type" "jmpreg")])
9004 ;; Table jump for switch statements:
9005 (define_expand "tablejump"
9006 [(use (match_operand
0 "" ""))
9007 (use (label_ref (match_operand
1 "" "")))]
9012 emit_jump_insn (gen_tablejumpsi (operands[
0], operands[
1]));
9014 emit_jump_insn (gen_tablejumpdi (operands[
0], operands[
1]));
9018 (define_expand "tablejumpsi"
9020 (plus:SI (match_operand:SI
0 "" "")
9022 (parallel [(set (pc) (match_dup
3))
9023 (use (label_ref (match_operand
1 "" "")))])]
9026 { operands[
0] = force_reg (SImode, operands[
0]);
9027 operands[
2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[
1]));
9028 operands[
3] = gen_reg_rtx (SImode);
9031 (define_expand "tablejumpdi"
9033 (plus:DI (match_operand:DI
0 "" "")
9035 (parallel [(set (pc) (match_dup
3))
9036 (use (label_ref (match_operand
1 "" "")))])]
9039 { operands[
0] = force_reg (DImode, operands[
0]);
9040 operands[
2] = force_reg (DImode, gen_rtx (LABEL_REF, VOIDmode, operands[
1]));
9041 operands[
3] = gen_reg_rtx (DImode);
9046 (match_operand:SI
0 "register_operand" "c,l"))
9047 (use (label_ref (match_operand
1 "" "")))]
9052 [(set_attr "type" "jmpreg")])
9056 (match_operand:DI
0 "register_operand" "c,l"))
9057 (use (label_ref (match_operand
1 "" "")))]
9062 [(set_attr "type" "jmpreg")])
9069 ;; Define the subtract-one-and-jump insns, starting with the template
9070 ;; so loop.c knows what to generate.
9072 (define_expand "decrement_and_branch_on_count"
9073 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI
0 "register_operand" "")
9075 (label_ref (match_operand
1 "" ""))
9078 (plus:SI (match_dup
0)
9080 (clobber (match_scratch:CC
2 ""))
9081 (clobber (match_scratch:SI
3 ""))])]
9085 ;; We need to be able to do this for any operand, including MEM, or we
9086 ;; will cause reload to blow up since we don't allow output reloads on
9088 ;; In order that the length attribute is calculated correctly, the
9089 ;; label MUST be operand
0.
9093 (if_then_else (ne (match_operand:SI
1 "register_operand" "c,*r,*r")
9095 (label_ref (match_operand
0 "" ""))
9097 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9098 (plus:SI (match_dup
1)
9100 (clobber (match_scratch:CC
3 "=X,&x,&x"))
9101 (clobber (match_scratch:SI
4 "=X,X,r"))]
9105 if (which_alternative !=
0)
9107 else if (get_attr_length (insn) ==
8)
9108 return
\"{bdn|bdnz} %l0
\";
9110 return
\"bdz %$+
8\;b %l0
\";
9112 [(set_attr "type" "branch")
9113 (set_attr "length" "*,
12,
16")])
9117 (if_then_else (ne (match_operand:SI
1 "register_operand" "c,*r,*r")
9120 (label_ref (match_operand
0 "" ""))))
9121 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9122 (plus:SI (match_dup
1)
9124 (clobber (match_scratch:CC
3 "=X,&x,&x"))
9125 (clobber (match_scratch:SI
4 "=X,X,r"))]
9129 if (which_alternative !=
0)
9131 else if (get_attr_length (insn) ==
8)
9134 return
\"{bdn|bdnz} %$+
8\;b %l0
\";
9136 [(set_attr "type" "branch")
9137 (set_attr "length" "*,
12,
16")])
9139 ;; Similar, but we can use GE since we have a REG_NONNEG.
9142 (if_then_else (ge (match_operand:SI
1 "register_operand" "c,*r,*r")
9144 (label_ref (match_operand
0 "" ""))
9146 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9147 (plus:SI (match_dup
1)
9149 (clobber (match_scratch:CC
3 "=X,&x,&X"))
9150 (clobber (match_scratch:SI
4 "=X,X,r"))]
9151 "find_reg_note (insn, REG_NONNEG,
0)"
9154 if (which_alternative !=
0)
9156 else if (get_attr_length (insn) ==
8)
9157 return
\"{bdn|bdnz} %l0
\";
9159 return
\"bdz %$+
8\;b %l0
\";
9161 [(set_attr "type" "branch")
9162 (set_attr "length" "*,
12,
16")])
9166 (if_then_else (ge (match_operand:SI
1 "register_operand" "c,*r,*r")
9169 (label_ref (match_operand
0 "" ""))))
9170 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9171 (plus:SI (match_dup
1)
9173 (clobber (match_scratch:CC
3 "=X,&x,&X"))
9174 (clobber (match_scratch:SI
4 "=X,X,r"))]
9175 "find_reg_note (insn, REG_NONNEG,
0)"
9178 if (which_alternative !=
0)
9180 else if (get_attr_length (insn) ==
8)
9183 return
\"{bdn|bdnz} %$+
8\;b %l0
\";
9185 [(set_attr "type" "branch")
9186 (set_attr "length" "*,
12,
16")])
9190 (if_then_else (eq (match_operand:SI
1 "register_operand" "c,*r,*r")
9192 (label_ref (match_operand
0 "" ""))
9194 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9195 (plus:SI (match_dup
1)
9197 (clobber (match_scratch:CC
3 "=X,&x,&x"))
9198 (clobber (match_scratch:SI
4 "=X,X,r"))]
9202 if (which_alternative !=
0)
9204 else if (get_attr_length (insn) ==
8)
9207 return
\"{bdn|bdnz} %$+
8\;b %l0
\";
9209 [(set_attr "type" "branch")
9210 (set_attr "length" "*,
12,
16")])
9214 (if_then_else (eq (match_operand:SI
1 "register_operand" "c,*r,*r")
9217 (label_ref (match_operand
0 "" ""))))
9218 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
9219 (plus:SI (match_dup
1)
9221 (clobber (match_scratch:CC
3 "=X,&x,&x"))
9222 (clobber (match_scratch:SI
4 "=X,X,r"))]
9226 if (which_alternative !=
0)
9228 else if (get_attr_length (insn) ==
8)
9229 return
\"{bdn|bdnz} %l0
\";
9231 return
\"bdz %$+
8\;b %l0
\";
9233 [(set_attr "type" "branch")
9234 (set_attr "length" "*,
12,
16")])
9238 (if_then_else (match_operator
2 "comparison_operator"
9239 [(match_operand:SI
1 "gpc_reg_operand" "")
9241 (match_operand
5 "" "")
9242 (match_operand
6 "" "")))
9243 (set (match_operand:SI
0 "gpc_reg_operand" "")
9244 (plus:SI (match_dup
1)
9246 (clobber (match_scratch:CC
3 ""))
9247 (clobber (match_scratch:SI
4 ""))]
9249 [(parallel [(set (match_dup
3)
9250 (compare:CC (plus:SI (match_dup
1)
9254 (plus:SI (match_dup
1)
9256 (set (pc) (if_then_else (match_dup
7)
9260 { operands[
7] = gen_rtx (GET_CODE (operands[
2]), VOIDmode, operands[
3],
9265 (if_then_else (match_operator
2 "comparison_operator"
9266 [(match_operand:SI
1 "gpc_reg_operand" "")
9268 (match_operand
5 "" "")
9269 (match_operand
6 "" "")))
9270 (set (match_operand:SI
0 "general_operand" "")
9271 (plus:SI (match_dup
1) (const_int -
1)))
9272 (clobber (match_scratch:CC
3 ""))
9273 (clobber (match_scratch:SI
4 ""))]
9274 "reload_completed && ! gpc_reg_operand (operands[
0], SImode)"
9275 [(parallel [(set (match_dup
3)
9276 (compare:CC (plus:SI (match_dup
1)
9280 (plus:SI (match_dup
1)
9284 (set (pc) (if_then_else (match_dup
7)
9288 { operands[
7] = gen_rtx (GET_CODE (operands[
2]), VOIDmode, operands[
3],