1 ;;- Machine description for IBM RISC System
6000 (POWER) for GNU C compiler
2 ;; Copyright (C)
1990,
1991,
1992,
1993 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version
2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation,
675 Mass Ave, Cambridge, MA
02139, USA.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;; Define an insn type attribute. This is used in function unit delay
25 (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtlr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt"
26 (const_string "integer"))
29 (define_attr "length" ""
30 (if_then_else (eq_attr "type" "branch")
31 (if_then_else (and (ge (minus (pc) (match_dup
0))
33 (lt (minus (pc) (match_dup
0))
39 ;; Processor type -- this attribute must exactly match the processor_type
40 ;; enumeration in rs6000.h.
42 (define_attr "cpu" "rios1,rios2,ppc601,ppc603,ppc604,ppc620"
43 (const (symbol_ref "rs6000_cpu_attr")))
45 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
46 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
48 (define_function_unit "lsu"
1 0
49 (and (eq_attr "type" "load")
50 (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
53 (define_function_unit "lsu"
1 0
54 (and (eq_attr "type" "fpload")
55 (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
58 (define_function_unit "iu"
1 0
59 (and (eq_attr "type" "load")
60 (eq_attr "cpu" "rios1"))
63 (define_function_unit "iu"
1 0
64 (and (eq_attr "type" "fpload")
65 (eq_attr "cpu" "rios1"))
68 (define_function_unit "iu"
1 0
69 (and (eq_attr "type" "imul")
70 (eq_attr "cpu" "rios1"))
73 (define_function_unit "iu"
1 0
74 (and (eq_attr "type" "imul")
75 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
78 (define_function_unit "iu"
1 0
79 (and (eq_attr "type" "idiv")
80 (eq_attr "cpu" "rios1"))
83 (define_function_unit "iu"
1 0
84 (and (eq_attr "type" "idiv")
85 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
88 (define_function_unit "bpu"
1 0
89 (eq_attr "type" "compare")
92 (define_function_unit "bpu"
1 0
93 (eq_attr "type" "delayed_compare")
96 (define_function_unit "bpu"
1 0
97 (and (eq_attr "type" "fpcompare")
98 (eq_attr "cpu" "rios1,rios2"))
101 (define_function_unit "bpu"
1 0
102 (and (eq_attr "type" "fpcompare")
103 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
106 (define_function_unit "bpu"
1 0
107 (and (eq_attr "type" "mtlr")
108 (eq_attr "cpu" "rios1,rios2"))
111 (define_function_unit "bpu"
1 0
112 (and (eq_attr "type" "mtlr")
113 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
116 (define_function_unit "fpu"
1 0
117 (and (eq_attr "type" "fp")
118 (eq_attr "cpu" "rios1"))
121 (define_function_unit "fpu"
1 0
122 (and (eq_attr "type" "fp")
123 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
126 (define_function_unit "fpu"
1 0
127 (and (eq_attr "type" "dmul")
128 (eq_attr "cpu" "rios1"))
131 (define_function_unit "fpu"
1 0
132 (and (eq_attr "type" "dmul")
133 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
136 (define_function_unit "fpu"
1 0
137 (and (eq_attr "type" "sdiv")
138 (eq_attr "cpu" "rios1"))
141 (define_function_unit "fpu"
1 0
142 (and (eq_attr "type" "sdiv")
143 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
146 (define_function_unit "fpu"
1 0
147 (and (eq_attr "type" "ddiv")
148 (eq_attr "cpu" "rios1"))
151 (define_function_unit "fpu"
1 0
152 (and (eq_attr "type" "ddiv")
153 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
156 (define_function_unit "fpu"
1 0
157 (and (eq_attr "type" "ssqrt")
158 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
161 (define_function_unit "fpu"
1 0
162 (and (eq_attr "type" "dsqrt")
163 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
166 (define_function_unit "iu2"
2 0
167 (and (eq_attr "type" "integer")
168 (eq_attr "cpu" "rios2"))
170 [(eq_attr "type" "imul,idiv")])
172 (define_function_unit "imuldiv"
1 0
173 (and (eq_attr "type" "imul")
174 (eq_attr "cpu" "rios2"))
176 [(eq_attr "type" "integer")])
178 (define_function_unit "imuldiv"
1 0
179 (and (eq_attr "type" "idiv")
180 (eq_attr "cpu" "rios2"))
182 [(eq_attr "type" "integer")])
184 (define_function_unit "fpu2"
2 0
185 (and (eq_attr "type" "fp")
186 (eq_attr "cpu" "rios2"))
189 (define_function_unit "fpu2"
2 0
190 (and (eq_attr "type" "dmul")
191 (eq_attr "cpu" "rios2"))
194 (define_function_unit "fpu2"
2 0
195 (and (eq_attr "type" "sdiv")
196 (eq_attr "cpu" "rios2"))
199 (define_function_unit "fpu2"
2 0
200 (and (eq_attr "type" "ddiv")
201 (eq_attr "cpu" "rios2"))
204 (define_function_unit "fpu2"
2 0
205 (and (eq_attr "type" "ssqrt")
206 (eq_attr "cpu" "rios2"))
209 (define_function_unit "fpu2"
2 0
210 (and (eq_attr "type" "dsqrt")
211 (eq_attr "cpu" "rios2"))
214 ;; Start with fixed-point load and store insns. Here we put only the more
215 ;; complex forms. Basic data transfer is done later.
217 (define_expand "zero_extendqisi2"
218 [(set (match_operand:SI
0 "gpc_reg_operand" "")
219 (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "")))]
224 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
225 (zero_extend:SI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
229 {rlinm|rlwinm} %
0,%
1,
0,
0xff"
230 [(set_attr "type" "load,*")])
233 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
234 (compare:CC (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
236 (clobber (match_scratch:SI
2 "=r"))]
238 "{andil.|andi.} %
2,%
1,
0xff"
239 [(set_attr "type" "compare")])
242 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
243 (compare:CC (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
245 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
246 (zero_extend:SI (match_dup
1)))]
248 "{andil.|andi.} %
0,%
1,
0xff"
249 [(set_attr "type" "compare")])
251 (define_expand "zero_extendqihi2"
252 [(set (match_operand:HI
0 "gpc_reg_operand" "")
253 (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "")))]
258 [(set (match_operand:HI
0 "gpc_reg_operand" "=r,r")
259 (zero_extend:HI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
263 {rlinm|rlwinm} %
0,%
1,
0,
0xff"
264 [(set_attr "type" "load,*")])
266 (define_expand "zero_extendhisi2"
267 [(set (match_operand:SI
0 "gpc_reg_operand" "")
268 (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "")))]
273 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
274 (zero_extend:SI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
278 {rlinm|rlwinm} %
0,%
1,
0,
0xffff"
279 [(set_attr "type" "load,*")])
282 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
283 (compare:CC (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
285 (clobber (match_scratch:SI
2 "=r"))]
287 "{andil.|andi.} %
2,%
1,
0xffff"
288 [(set_attr "type" "compare")])
291 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
292 (compare:CC (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
294 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
295 (zero_extend:SI (match_dup
1)))]
297 "{andil.|andi.} %
0,%
1,
0xffff"
298 [(set_attr "type" "compare")])
300 (define_expand "extendhisi2"
301 [(set (match_operand:SI
0 "gpc_reg_operand" "")
302 (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "")))]
307 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
308 (sign_extend:SI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
313 [(set_attr "type" "load,*")])
316 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
317 (compare:CC (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
319 (clobber (match_scratch:SI
2 "=r"))]
321 "{exts.|extsh.} %
2,%
1"
322 [(set_attr "type" "compare")])
325 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
326 (compare:CC (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
328 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
329 (sign_extend:SI (match_dup
1)))]
331 "{exts.|extsh.} %
0,%
1"
332 [(set_attr "type" "compare")])
334 ;; Fixed-point arithmetic insns.
335 (define_insn "addsi3"
336 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
337 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,b")
338 (match_operand:SI
2 "add_operand" "rI,J")))]
341 {a%I2|add%I2c} %
0,%
1,%
2
342 {cau|addis} %
0,%
1,%u2")
345 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
346 (compare:CC (plus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
347 (match_operand:SI
2 "reg_or_short_operand" "rI"))
349 (clobber (match_scratch:SI
3 "=r"))]
351 "{a%I2.|add%I2c.} %
3,%
1,%
2"
352 [(set_attr "type" "compare")])
355 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
356 (compare:CC (plus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
357 (match_operand:SI
2 "reg_or_short_operand" "rI"))
359 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
360 (plus:SI (match_dup
1) (match_dup
2)))]
362 "{a%I2.|add%I2c.} %
0,%
1,%
2"
363 [(set_attr "type" "compare")])
365 ;; Split an add that we can't do in one insn into two insns, each of which
366 ;; does one
16-bit part. This is used by combine. Note that the low-order
367 ;; add should be last in case the result gets used in an address.
370 [(set (match_operand:SI
0 "gpc_reg_operand" "")
371 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "")
372 (match_operand:SI
2 "non_add_cint_operand" "")))]
374 [(set (match_dup
0) (plus:SI (match_dup
1) (match_dup
3)))
375 (set (match_dup
0) (plus:SI (match_dup
0) (match_dup
4)))]
378 int low = INTVAL (operands[
2]) &
0xffff;
379 int high = (unsigned) INTVAL (operands[
2]) >>
16;
382 high++, low |=
0xffff0000;
384 operands[
3] = gen_rtx (CONST_INT, VOIDmode, high <<
16);
385 operands[
4] = gen_rtx (CONST_INT, VOIDmode, low);
388 (define_expand "one_cmplsi2"
389 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
390 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
395 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
396 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
398 "{sfi|subfic} %
0,%
1,-
1")
401 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
402 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
407 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
408 (compare:CC (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
410 (clobber (match_scratch:SI
2 "=r"))]
413 [(set_attr "type" "compare")])
416 [(set (match_operand:CC
2 "cc_reg_operand" "=-x")
417 (compare:CC (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
419 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
420 (not:SI (match_dup
1)))]
423 [(set_attr "type" "compare")])
426 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
427 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "rI")
428 (match_operand:SI
2 "gpc_reg_operand" "r")))]
430 "{sf%I1|subf%I1c} %
0,%
2,%
1")
433 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
434 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
435 (match_operand:SI
2 "gpc_reg_operand" "r"))
437 (clobber (match_scratch:SI
3 "=r"))]
439 "{sf.|subfc.} %
3,%
2,%
1"
440 [(set_attr "type" "compare")])
443 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
444 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
445 (match_operand:SI
2 "gpc_reg_operand" "r"))
447 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
448 (minus:SI (match_dup
1) (match_dup
2)))]
450 "{sf.|subfc.} %
0,%
2,%
1"
451 [(set_attr "type" "compare")])
453 (define_expand "subsi3"
454 [(set (match_operand:SI
0 "gpc_reg_operand" "")
455 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "")
456 (match_operand:SI
2 "reg_or_cint_operand" "")))]
460 if (GET_CODE (operands[
2]) == CONST_INT)
462 emit_insn (gen_addsi3 (operands[
0], operands[
1],
463 negate_rtx (SImode, operands[
2])));
468 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
469 ;; instruction and some auxiliary computations. Then we just have a single
470 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
473 (define_expand "sminsi3"
475 (if_then_else:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "")
476 (match_operand:SI
2 "reg_or_short_operand" ""))
478 (minus:SI (match_dup
2) (match_dup
1))))
479 (set (match_operand:SI
0 "gpc_reg_operand" "")
480 (minus:SI (match_dup
2) (match_dup
3)))]
483 { operands[
3] = gen_reg_rtx (SImode); }")
486 [(set (match_operand:SI
0 "gpc_reg_operand" "")
487 (smin:SI (match_operand:SI
1 "gpc_reg_operand" "")
488 (match_operand:SI
2 "reg_or_short_operand" "")))
489 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
492 (if_then_else:SI (gt:SI (match_dup
1) (match_dup
2))
494 (minus:SI (match_dup
2) (match_dup
1))))
495 (set (match_dup
0) (minus:SI (match_dup
2) (match_dup
3)))]
498 (define_expand "smaxsi3"
500 (if_then_else:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "")
501 (match_operand:SI
2 "reg_or_short_operand" ""))
503 (minus:SI (match_dup
2) (match_dup
1))))
504 (set (match_operand:SI
0 "gpc_reg_operand" "")
505 (plus:SI (match_dup
3) (match_dup
1)))]
508 { operands[
3] = gen_reg_rtx (SImode); }")
511 [(set (match_operand:SI
0 "gpc_reg_operand" "")
512 (smax:SI (match_operand:SI
1 "gpc_reg_operand" "")
513 (match_operand:SI
2 "reg_or_short_operand" "")))
514 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
517 (if_then_else:SI (gt:SI (match_dup
1) (match_dup
2))
519 (minus:SI (match_dup
2) (match_dup
1))))
520 (set (match_dup
0) (plus:SI (match_dup
3) (match_dup
1)))]
523 (define_expand "uminsi3"
524 [(set (match_dup
3) (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
525 (const_int -
2147483648)))
526 (set (match_dup
4) (xor:SI (match_operand:SI
2 "gpc_reg_operand" "")
527 (const_int -
2147483648)))
528 (set (match_dup
3) (if_then_else:SI (gt (match_dup
3) (match_dup
4))
530 (minus:SI (match_dup
4) (match_dup
3))))
531 (set (match_operand:SI
0 "gpc_reg_operand" "")
532 (minus:SI (match_dup
2) (match_dup
3)))]
535 { operands[
3] = gen_reg_rtx (SImode); operands[
4] = gen_reg_rtx (SImode); }")
537 (define_expand "umaxsi3"
538 [(set (match_dup
3) (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
539 (const_int -
2147483648)))
540 (set (match_dup
4) (xor:SI (match_operand:SI
2 "gpc_reg_operand" "")
541 (const_int -
2147483648)))
542 (set (match_dup
3) (if_then_else:SI (gt (match_dup
3) (match_dup
4))
544 (minus:SI (match_dup
4) (match_dup
3))))
545 (set (match_operand:SI
0 "gpc_reg_operand" "")
546 (plus:SI (match_dup
3) (match_dup
1)))]
549 { operands[
3] = gen_reg_rtx (SImode); operands[
4] = gen_reg_rtx (SImode); }")
552 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
553 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
554 (match_operand:SI
2 "reg_or_short_operand" "rI"))
556 (minus:SI (match_dup
2) (match_dup
1))))]
561 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
563 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
564 (match_operand:SI
2 "reg_or_short_operand" "rI"))
566 (minus:SI (match_dup
2) (match_dup
1)))
568 (clobber (match_scratch:SI
3 "=r"))]
571 [(set_attr "type" "delayed_compare")])
574 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
576 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
577 (match_operand:SI
2 "reg_or_short_operand" "rI"))
579 (minus:SI (match_dup
2) (match_dup
1)))
581 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
582 (if_then_else:SI (gt (match_dup
1) (match_dup
2))
584 (minus:SI (match_dup
2) (match_dup
1))))]
587 [(set_attr "type" "delayed_compare")])
589 ;; We don't need abs with condition code because such comparisons should
591 (define_insn "abssi2"
592 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
593 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
598 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
599 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r"))))]
603 (define_insn "negsi2"
604 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
605 (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
610 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
611 (compare:CC (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
613 (clobber (match_scratch:SI
2 "=r"))]
616 [(set_attr "type" "compare")])
619 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
620 (compare:CC (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
622 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
623 (neg:SI (match_dup
1)))]
626 [(set_attr "type" "compare")])
628 (define_insn "ffssi2"
629 [(set (match_operand:SI
0 "register_operand" "=&r")
630 (ffs:SI (match_operand:SI
1 "register_operand" "r")))]
632 "neg %
0,%
1\;and %
0,%
0,%
1\;cntlz %
0,%
0\;{sfi|subfic} %
0,%
0,
32"
633 [(set_attr "length" "
16")])
635 (define_expand "mulsi3"
636 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
637 (use (match_operand:SI
1 "gpc_reg_operand" ""))
638 (use (match_operand:SI
2 "reg_or_short_operand" ""))]
643 emit_insn (gen_mulsi3_mq (operands[
0], operands[
1], operands[
2]));
645 emit_insn (gen_mulsi3_no_mq (operands[
0], operands[
1], operands[
2]));
649 (define_insn "mulsi3_mq"
650 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
651 (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
652 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
653 (clobber (match_scratch:SI
3 "=q,q"))]
656 {muls|mullw} %
0,%
1,%
2
657 {muli|mulli} %
0,%
1,%
2"
658 [(set_attr "type" "imul")])
660 (define_insn "mulsi3_no_mq"
661 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
662 (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
663 (match_operand:SI
2 "reg_or_short_operand" "r,I")))]
668 [(set_attr "type" "imul")])
671 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
672 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "r")
673 (match_operand:SI
2 "gpc_reg_operand" "r"))
675 (clobber (match_scratch:SI
3 "=r"))
676 (clobber (match_scratch:SI
4 "=q"))]
678 "{muls.|mullw.} %
3,%
1,%
2"
679 [(set_attr "type" "delayed_compare")])
682 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
683 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "r")
684 (match_operand:SI
2 "gpc_reg_operand" "r"))
686 (clobber (match_scratch:SI
3 "=r"))]
689 [(set_attr "type" "delayed_compare")])
692 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
693 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "r")
694 (match_operand:SI
2 "gpc_reg_operand" "r"))
696 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
697 (mult:SI (match_dup
1) (match_dup
2)))
698 (clobber (match_scratch:SI
4 "=q"))]
700 "{muls.|mullw.} %
0,%
1,%
2"
701 [(set_attr "type" "delayed_compare")])
704 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
705 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "r")
706 (match_operand:SI
2 "gpc_reg_operand" "r"))
708 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
709 (mult:SI (match_dup
1) (match_dup
2)))]
712 [(set_attr "type" "delayed_compare")])
714 ;; Operand
1 is divided by operand
2; quotient goes to operand
715 ;;
0 and remainder to operand
3.
716 ;; ??? At some point, see what, if anything, we can do about if (x % y ==
0).
718 (define_insn "divmodsi4"
719 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
720 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
721 (match_operand:SI
2 "gpc_reg_operand" "r")))
722 (set (match_operand:SI
3 "gpc_reg_operand" "=q")
723 (mod:SI (match_dup
1) (match_dup
2)))]
726 [(set_attr "type" "idiv")])
729 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
730 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
731 (match_operand:SI
2 "gpc_reg_operand" "r")))]
734 [(set_attr "type" "idiv")])
736 (define_insn "udivsi3"
737 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
738 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "r")
739 (match_operand:SI
2 "gpc_reg_operand" "r")))]
742 [(set_attr "type" "idiv")])
744 ;; For powers of two we can do srai/aze for divide and then adjust for
745 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
746 ;; used; for PowerPC, force operands into register and do a normal divide.
747 (define_expand "divsi3"
748 [(set (match_operand:SI
0 "gpc_reg_operand" "")
749 (div:SI (match_operand:SI
1 "gpc_reg_operand" "")
750 (match_operand:SI
2 "reg_or_cint_operand" "")))]
754 if (GET_CODE (operands[
2]) == CONST_INT
755 && exact_log2 (INTVAL (operands[
2])) >=
0)
758 else if (TARGET_POWER)
761 else if (TARGET_POWERPC)
762 operands[
2] = force_reg (SImode, operands[
2]);
765 (define_expand "modsi3"
767 (div:SI (match_operand:SI
1 "gpc_reg_operand" "")
768 (match_operand:SI
2 "reg_or_cint_operand" "")))
769 (parallel [(set (match_dup
4) (ashift:SI (match_dup
3) (match_dup
5)))
770 (clobber (scratch:SI))])
771 (set (match_operand:SI
0 "gpc_reg_operand" "")
772 (minus:SI (match_dup
1) (match_dup
4)))]
776 int i = exact_log2 (INTVAL (operands[
2]));
778 if (GET_CODE (operands[
2]) != CONST_INT || i <
0)
781 operands[
3] = gen_reg_rtx (SImode);
782 operands[
4] = gen_reg_rtx (SImode);
783 operands[
5] = gen_rtx (CONST_INT, VOIDmode, i);
787 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
788 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
789 (match_operand:SI
2 "const_int_operand" "N")))]
790 "exact_log2 (INTVAL (operands[
2])) >=
0"
791 "{srai|srawi} %
0,%
1,%p2\;{aze|addze} %
0,%
0"
792 [(set_attr "length" "
8")])
795 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
796 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
797 (match_operand:SI
2 "const_int_operand" "N")))
798 (clobber (match_scratch:SI
3 "=r"))]
799 "exact_log2 (INTVAL (operands[
2])) >=
0"
800 "{srai|srawi} %
3,%
1,%p2\;{aze.|addze.} %
3,%
3"
801 [(set_attr "type" "compare")
802 (set_attr "length" "
8")])
805 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
806 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
807 (match_operand:SI
2 "const_int_operand" "N")))
808 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
809 (div:SI (match_dup
1) (match_dup
2)))]
810 "exact_log2 (INTVAL (operands[
2])) >=
0"
811 "{srai|srawi} %
0,%
1,%p2\;{aze.|addze.} %
0,%
0"
812 [(set_attr "type" "compare")
813 (set_attr "length" "
8")])
816 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
819 (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
821 (zero_extend:DI (match_operand:SI
4 "register_operand" "
2")))
822 (match_operand:SI
3 "gpc_reg_operand" "r")))
823 (set (match_operand:SI
2 "register_operand" "=*q")
826 (zero_extend:DI (match_dup
1)) (const_int
32))
827 (zero_extend:DI (match_dup
4)))
832 [(set_attr "type" "idiv")])
834 ;; To do unsigned divide we handle the cases of the divisor looking like a
835 ;; negative number. If it is a constant that is less than
2**
31, we don't
836 ;; have to worry about the branches. So make a few subroutines here.
838 ;; First comes the normal case.
839 (define_expand "udivmodsi4_normal"
840 [(set (match_dup
4) (const_int
0))
841 (parallel [(set (match_operand:SI
0 "" "")
842 (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup
4))
844 (zero_extend:DI (match_operand:SI
1 "" "")))
845 (match_operand:SI
2 "" "")))
846 (set (match_operand:SI
3 "" "")
847 (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup
4))
849 (zero_extend:DI (match_dup
1)))
853 { operands[
4] = gen_reg_rtx (SImode); }")
855 ;; This handles the branches.
856 (define_expand "udivmodsi4_tests"
857 [(set (match_operand:SI
0 "" "") (const_int
0))
858 (set (match_operand:SI
3 "" "") (match_operand:SI
1 "" ""))
859 (set (match_dup
5) (compare:CCUNS (match_dup
1) (match_operand:SI
2 "" "")))
860 (set (pc) (if_then_else (ltu (match_dup
5) (const_int
0))
861 (label_ref (match_operand:SI
4 "" "")) (pc)))
862 (set (match_dup
0) (const_int
1))
863 (set (match_dup
3) (minus:SI (match_dup
1) (match_dup
2)))
864 (set (match_dup
6) (compare:CC (match_dup
2) (const_int
0)))
865 (set (pc) (if_then_else (lt (match_dup
6) (const_int
0))
866 (label_ref (match_dup
4)) (pc)))]
869 { operands[
5] = gen_reg_rtx (CCUNSmode);
870 operands[
6] = gen_reg_rtx (CCmode);
873 (define_expand "udivmodsi4"
874 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
875 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "")
876 (match_operand:SI
2 "reg_or_cint_operand" "")))
877 (set (match_operand:SI
3 "gpc_reg_operand" "")
878 (umod:SI (match_dup
1) (match_dup
2)))])]
884 if (GET_CODE (operands[
2]) != CONST_INT || INTVAL (operands[
2]) <
0)
886 operands[
2] = force_reg (SImode, operands[
2]);
887 label = gen_label_rtx ();
888 emit (gen_udivmodsi4_tests (operands[
0], operands[
1], operands[
2],
889 operands[
3], label));
892 operands[
2] = force_reg (SImode, operands[
2]);
894 emit (gen_udivmodsi4_normal (operands[
0], operands[
1], operands[
2],
902 (define_insn "andsi3"
903 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
904 (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
905 (match_operand:SI
2 "and_operand" "?r,L,K,J")))
906 (clobber (match_scratch:CC
3 "=X,X,x,x"))]
910 {rlinm|rlwinm} %
0,%
1,
0,%m2,%M2
911 {andil.|andi.} %
0,%
1,%b2
912 {andiu.|andis.} %
0,%
1,%u2")
915 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x,x")
916 (compare:CC (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
917 (match_operand:SI
2 "and_operand" "r,K,J,L"))
919 (clobber (match_scratch:SI
3 "=r,r,r,r"))]
923 {andil.|andi.} %
3,%
1,%b2
924 {andiu.|andis.} %
3,%
1,%u2
925 {rlinm.|rlwinm.} %
3,%
1,
0,%m2,%M2"
926 [(set_attr "type" "compare,compare,compare,delayed_compare")])
929 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x,x,x")
930 (compare:CC (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
931 (match_operand:SI
2 "and_operand" "r,K,J,L"))
933 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
934 (and:SI (match_dup
1) (match_dup
2)))]
938 {andil.|andi.} %
0,%
1,%b2
939 {andiu.|andis.} %
0,%
1,%u2
940 {rlinm.|rlwinm.} %
0,%
1,
0,%m2,%M2"
941 [(set_attr "type" "compare,compare,compare,delayed_compare")])
943 ;; Take a AND with a constant that cannot be done in a single insn and try to
944 ;; split it into two insns. This does not verify that the insns are valid
945 ;; since this need not be done as combine will do it.
948 [(set (match_operand:SI
0 "gpc_reg_operand" "")
949 (and:SI (match_operand:SI
1 "gpc_reg_operand" "")
950 (match_operand:SI
2 "non_and_cint_operand" "")))]
952 [(set (match_dup
0) (and:SI (match_dup
1) (match_dup
3)))
953 (set (match_dup
0) (and:SI (match_dup
0) (match_dup
4)))]
956 int maskval = INTVAL (operands[
2]);
957 int i, transitions, last_bit_value;
958 int orig = maskval, first_c = maskval, second_c;
960 /* We know that MASKVAL must have more than
2 bit-transitions. Start at
961 the low-order bit and count for the third transition. When we get there,
962 make a first mask that has everything to the left of that position
963 a one. Then make the second mask to turn off whatever else is needed. */
965 for (i =
1, transitions =
0, last_bit_value = maskval &
1; i <
32; i++)
967 if (((maskval >>=
1) &
1) != last_bit_value)
968 last_bit_value ^=
1, transitions++;
972 first_c |= (~
0) << i;
977 second_c = orig | ~ first_c;
979 operands[
3] = gen_rtx (CONST_INT, VOIDmode, first_c);
980 operands[
4] = gen_rtx (CONST_INT, VOIDmode, second_c);
983 (define_insn "iorsi3"
984 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
985 (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r")
986 (match_operand:SI
2 "logical_operand" "r,K,J")))]
991 {oriu|oris} %
0,%
1,%u2")
994 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
995 (compare:CC (ior:SI (match_operand:SI
1 "gpc_reg_operand" "r")
996 (match_operand:SI
2 "gpc_reg_operand" "r"))
998 (clobber (match_scratch:SI
3 "=r"))]
1001 [(set_attr "type" "compare")])
1004 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1005 (compare:CC (ior:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1006 (match_operand:SI
2 "gpc_reg_operand" "r"))
1008 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1009 (ior:SI (match_dup
1) (match_dup
2)))]
1012 [(set_attr "type" "compare")])
1014 ;; Split an IOR that we can't do in one insn into two insns, each of which
1015 ;; does one
16-bit part. This is used by combine.
1018 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1019 (ior:SI (match_operand:SI
1 "gpc_reg_operand" "")
1020 (match_operand:SI
2 "non_logical_cint_operand" "")))]
1022 [(set (match_dup
0) (ior:SI (match_dup
1) (match_dup
3)))
1023 (set (match_dup
0) (ior:SI (match_dup
0) (match_dup
4)))]
1026 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
1027 INTVAL (operands[
2]) &
0xffff0000);
1028 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1031 (define_insn "xorsi3"
1032 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
1033 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r")
1034 (match_operand:SI
2 "logical_operand" "r,K,J")))]
1038 {xoril|xori} %
0,%
1,%b2
1039 {xoriu|xoris} %
0,%
1,%u2")
1042 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1043 (compare:CC (xor:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1044 (match_operand:SI
2 "gpc_reg_operand" "r"))
1046 (clobber (match_scratch:SI
3 "=r"))]
1049 [(set_attr "type" "compare")])
1052 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1053 (compare:CC (xor:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1054 (match_operand:SI
2 "gpc_reg_operand" "r"))
1056 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1057 (xor:SI (match_dup
1) (match_dup
2)))]
1060 [(set_attr "type" "compare")])
1062 ;; Split an XOR that we can't do in one insn into two insns, each of which
1063 ;; does one
16-bit part. This is used by combine.
1066 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1067 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1068 (match_operand:SI
2 "non_logical_cint_operand" "")))]
1070 [(set (match_dup
0) (xor:SI (match_dup
1) (match_dup
3)))
1071 (set (match_dup
0) (xor:SI (match_dup
0) (match_dup
4)))]
1074 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
1075 INTVAL (operands[
2]) &
0xffff0000);
1076 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1080 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1081 (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1082 (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1087 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1088 (compare:CC (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1089 (match_operand:SI
2 "gpc_reg_operand" "r")))
1091 (clobber (match_scratch:SI
3 "=r"))]
1094 [(set_attr "type" "compare")])
1097 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1098 (compare:CC (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1099 (match_operand:SI
2 "gpc_reg_operand" "r")))
1101 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1102 (not:SI (xor:SI (match_dup
1) (match_dup
2))))]
1105 [(set_attr "type" "compare")])
1108 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1109 (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1110 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1115 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1116 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1117 (match_operand:SI
2 "gpc_reg_operand" "r"))
1119 (clobber (match_scratch:SI
3 "=r"))]
1122 [(set_attr "type" "compare")])
1125 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1126 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1127 (match_operand:SI
2 "gpc_reg_operand" "r"))
1129 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1130 (and:SI (not:SI (match_dup
1)) (match_dup
2)))]
1133 [(set_attr "type" "compare")])
1136 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1137 (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1138 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1143 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1144 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1145 (match_operand:SI
2 "gpc_reg_operand" "r"))
1147 (clobber (match_scratch:SI
3 "=r"))]
1150 [(set_attr "type" "compare")])
1153 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1154 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1155 (match_operand:SI
2 "gpc_reg_operand" "r"))
1157 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1158 (ior:SI (not:SI (match_dup
1)) (match_dup
2)))]
1161 [(set_attr "type" "compare")])
1164 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1165 (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1166 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1171 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1172 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1173 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1175 (clobber (match_scratch:SI
3 "=r"))]
1178 [(set_attr "type" "compare")])
1181 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1182 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1183 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1185 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1186 (ior:SI (not:SI (match_dup
1)) (not:SI (match_dup
2))))]
1189 [(set_attr "type" "compare")])
1192 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1193 (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1194 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1199 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1200 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1201 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1203 (clobber (match_scratch:SI
3 "=r"))]
1206 [(set_attr "type" "compare")])
1209 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1210 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1211 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1213 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1214 (and:SI (not:SI (match_dup
1)) (not:SI (match_dup
2))))]
1217 [(set_attr "type" "compare")])
1219 ;; maskir insn. We need four forms because things might be in arbitrary
1220 ;; orders. Don't define forms that only set CR fields because these
1221 ;; would modify an input register.
1224 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1225 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1226 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1227 (and:SI (match_dup
2)
1228 (match_operand:SI
3 "gpc_reg_operand" "r"))))]
1233 [(set (match_operand:SI
0 "register_operand" "=r")
1234 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1235 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1236 (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1242 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1243 (ior:SI (and:SI (match_operand:SI
2 "gpc_reg_operand" "r")
1244 (match_operand:SI
3 "gpc_reg_operand" "r"))
1245 (and:SI (not:SI (match_dup
2))
1246 (match_operand:SI
1 "gpc_reg_operand" "
0"))))]
1251 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1252 (ior:SI (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1253 (match_operand:SI
2 "gpc_reg_operand" "r"))
1254 (and:SI (not:SI (match_dup
2))
1255 (match_operand:SI
1 "gpc_reg_operand" "
0"))))]
1260 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1262 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1263 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1264 (and:SI (match_dup
2)
1265 (match_operand:SI
3 "gpc_reg_operand" "r")))
1267 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1268 (ior:SI (and:SI (not:SI (match_dup
2)) (match_dup
1))
1269 (and:SI (match_dup
2) (match_dup
3))))]
1272 [(set_attr "type" "compare")])
1275 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1277 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1278 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1279 (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1282 (set (match_operand:SI
0 "register_operand" "=r")
1283 (ior:SI (and:SI (not:SI (match_dup
2)) (match_dup
1))
1284 (and:SI (match_dup
3) (match_dup
2))))]
1287 [(set_attr "type" "compare")])
1290 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1292 (ior:SI (and:SI (match_operand:SI
2 "gpc_reg_operand" "r")
1293 (match_operand:SI
3 "gpc_reg_operand" "r"))
1294 (and:SI (not:SI (match_dup
2))
1295 (match_operand:SI
1 "gpc_reg_operand" "
0")))
1297 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1298 (ior:SI (and:SI (match_dup
2) (match_dup
3))
1299 (and:SI (not:SI (match_dup
2)) (match_dup
1))))]
1302 [(set_attr "type" "compare")])
1305 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1307 (ior:SI (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1308 (match_operand:SI
2 "gpc_reg_operand" "r"))
1309 (and:SI (not:SI (match_dup
2))
1310 (match_operand:SI
1 "gpc_reg_operand" "
0")))
1312 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1313 (ior:SI (and:SI (match_dup
3) (match_dup
2))
1314 (and:SI (not:SI (match_dup
2)) (match_dup
1))))]
1317 [(set_attr "type" "compare")])
1319 ;; Rotate and shift insns, in all their variants. These support shifts,
1320 ;; field inserts and extracts, and various combinations thereof.
1322 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
1323 (match_operand:SI
1 "const_int_operand" "i")
1324 (match_operand:SI
2 "const_int_operand" "i"))
1325 (match_operand:SI
3 "gpc_reg_operand" "r"))]
1329 int start = INTVAL (operands[
2]) &
31;
1330 int size = INTVAL (operands[
1]) &
31;
1332 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - start - size);
1333 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
1334 return
\"{rlimi|rlwimi} %
0,%
3,%
4,%h2,%h1
\";
1337 (define_insn "extzv"
1338 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1339 (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1340 (match_operand:SI
2 "const_int_operand" "i")
1341 (match_operand:SI
3 "const_int_operand" "i")))]
1345 int start = INTVAL (operands[
3]) &
31;
1346 int size = INTVAL (operands[
2]) &
31;
1348 if (start + size >=
32)
1349 operands[
3] = const0_rtx;
1351 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1352 return
\"{rlinm|rlwinm} %
0,%
1,%
3,%s2,
31\";
1356 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1357 (compare:CC (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1358 (match_operand:SI
2 "const_int_operand" "i")
1359 (match_operand:SI
3 "const_int_operand" "i"))
1361 (clobber (match_scratch:SI
4 "=r"))]
1365 int start = INTVAL (operands[
3]) &
31;
1366 int size = INTVAL (operands[
2]) &
31;
1368 /* If the bitfield being tested fits in the upper or lower half of a
1369 word, it is possible to use andiu. or andil. to test it. This is
1370 useful because the condition register set-use delay is smaller for
1371 andi[ul]. than for rlinm. This doesn't work when the starting bit
1372 position is
0 because the LT and GT bits may be set wrong. */
1374 if ((start >
0 && start + size <=
16) || start >=
16)
1376 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
1377 ((
1 << (
16 - (start &
15)))
1378 - (
1 << (
16 - (start &
15) - size))));
1380 return
\"{andiu.|andis.} %
4,%
1,%
3\";
1382 return
\"{andil.|andi.} %
4,%
1,%
3\";
1385 if (start + size >=
32)
1386 operands[
3] = const0_rtx;
1388 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1389 return
\"{rlinm.|rlwinm.} %
4,%
1,%
3,%s2,
31\";
1391 [(set_attr "type" "compare")])
1394 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1395 (compare:CC (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1396 (match_operand:SI
2 "const_int_operand" "i")
1397 (match_operand:SI
3 "const_int_operand" "i"))
1399 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1400 (zero_extract:SI (match_dup
1) (match_dup
2) (match_dup
3)))]
1404 int start = INTVAL (operands[
3]) &
31;
1405 int size = INTVAL (operands[
2]) &
31;
1407 if (start >=
16 && start + size ==
32)
1409 operands[
3] = gen_rtx (CONST_INT, VOIDmode, (
1 << (
32 - start)) -
1);
1410 return
\"{andil.|andi.} %
0,%
1,%
3\";
1413 if (start + size >=
32)
1414 operands[
3] = const0_rtx;
1416 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1417 return
\"{rlinm.|rlwinm.} %
0,%
1,%
3,%s2,
31\";
1419 [(set_attr "type" "delayed_compare")])
1421 (define_insn "rotlsi3"
1422 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1423 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1424 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
1426 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xffffffff")
1429 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1430 (compare:CC (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1431 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1433 (clobber (match_scratch:SI
3 "=r"))]
1435 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xffffffff"
1436 [(set_attr "type" "delayed_compare")])
1439 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1440 (compare:CC (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1441 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1443 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1444 (rotate:SI (match_dup
1) (match_dup
2)))]
1446 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xffffffff"
1447 [(set_attr "type" "delayed_compare")])
1450 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1451 (and:SI (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1452 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1453 (match_operand:SI
3 "mask_operand" "L")))]
1455 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,%m3,%M3")
1458 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1460 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1461 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1462 (match_operand:SI
3 "mask_operand" "L"))
1464 (clobber (match_scratch:SI
4 "=r"))]
1466 "{rl%I2nm.|rlw%I2nm.} %
4,%
1,%h2,%m3,%M3"
1467 [(set_attr "type" "delayed_compare")])
1470 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1472 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1473 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1474 (match_operand:SI
3 "mask_operand" "L"))
1476 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1477 (and:SI (rotate:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
1479 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,%m3,%M3"
1480 [(set_attr "type" "delayed_compare")])
1483 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1486 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1487 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0)))]
1489 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xff")
1492 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1493 (compare:CC (zero_extend:SI
1495 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1496 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
1498 (clobber (match_scratch:SI
3 "=r"))]
1500 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xff"
1501 [(set_attr "type" "delayed_compare")])
1504 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1505 (compare:CC (zero_extend:SI
1507 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1508 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
1510 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1511 (zero_extend:SI (subreg:QI (rotate:SI (match_dup
1) (match_dup
2))
0)))]
1513 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xff"
1514 [(set_attr "type" "delayed_compare")])
1517 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1520 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1521 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0)))]
1523 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xffff")
1526 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1527 (compare:CC (zero_extend:SI
1529 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1530 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
1532 (clobber (match_scratch:SI
3 "=r"))]
1534 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xffff"
1535 [(set_attr "type" "delayed_compare")])
1538 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1539 (compare:CC (zero_extend:SI
1541 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1542 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
1544 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1545 (zero_extend:SI (subreg:HI (rotate:SI (match_dup
1) (match_dup
2))
0)))]
1547 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xffff"
1548 [(set_attr "type" "delayed_compare")])
1550 ;; Note that we use "sle." instead of "sl." so that we can set
1551 ;; SHIFT_COUNT_TRUNCATED.
1553 (define_expand "ashlsi3"
1554 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
1555 (use (match_operand:SI
1 "gpc_reg_operand" ""))
1556 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
1561 emit_insn (gen_ashlsi3_power (operands[
0], operands[
1], operands[
2]));
1563 emit_insn (gen_ashlsi3_powerpc (operands[
0], operands[
1], operands[
2]));
1567 (define_insn "ashlsi3_power"
1568 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1569 (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
1570 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
1571 (clobber (match_scratch:SI
3 "=q,X"))]
1575 {sli|slwi} %
0,%
1,%h2"
1576 [(set_attr "length" "
8")])
1578 (define_insn "ashlsi3_powerpc"
1579 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1580 (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1581 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
1584 [(set_attr "length" "
8")])
1587 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
1588 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
1589 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
1591 (clobber (match_scratch:SI
3 "=r,r"))
1592 (clobber (match_scratch:SI
4 "=q,X"))]
1596 {sli.|slwi.} %
3,%
1,%h2"
1597 [(set_attr "type" "delayed_compare")])
1599 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1600 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1601 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1603 (clobber (match_scratch:SI
3 "=r"))]
1606 [(set_attr "type" "delayed_compare")])
1609 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
1610 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
1611 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
1613 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1614 (ashift:SI (match_dup
1) (match_dup
2)))
1615 (clobber (match_scratch:SI
4 "=q,X"))]
1619 {sli.|slwi.} %
0,%
1,%h2"
1620 [(set_attr "type" "delayed_compare")])
1622 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1623 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1624 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1626 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1627 (ashift:SI (match_dup
1) (match_dup
2)))]
1630 [(set_attr "type" "delayed_compare")])
1633 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1634 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1635 (match_operand:SI
2 "const_int_operand" "i"))
1636 (match_operand:SI
3 "mask_operand" "L")))]
1637 "includes_lshift_p (operands[
2], operands[
3])"
1638 "{rlinm|rlwinm} %
0,%h1,%h2,%m3,%M3")
1641 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1643 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1644 (match_operand:SI
2 "const_int_operand" "i"))
1645 (match_operand:SI
3 "mask_operand" "L"))
1647 (clobber (match_scratch:SI
4 "=r"))]
1648 "includes_lshift_p (operands[
2], operands[
3])"
1649 "{rlinm.|rlwinm.} %
4,%h1,%h2,%m3,%M3"
1650 [(set_attr "type" "delayed_compare")])
1653 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1655 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1656 (match_operand:SI
2 "const_int_operand" "i"))
1657 (match_operand:SI
3 "mask_operand" "L"))
1659 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1660 (and:SI (ashift:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
1661 "includes_lshift_p (operands[
2], operands[
3])"
1662 "{rlinm.|rlwinm.} %
0,%h1,%h2,%m3,%M3"
1663 [(set_attr "type" "delayed_compare")])
1665 ;; The AIX assembler mis-handles "sri x,x,
0", so write that case as
1667 (define_expand "lshrsi3"
1668 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
1669 (use (match_operand:SI
1 "gpc_reg_operand" ""))
1670 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
1675 emit_insn (gen_lshrsi3_power (operands[
0], operands[
1], operands[
2]));
1677 emit_insn (gen_lshrsi3_powerpc (operands[
0], operands[
1], operands[
2]));
1681 (define_insn "lshrsi3_power"
1682 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1683 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
1684 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
1685 (clobber (match_scratch:SI
3 "=q,X"))]
1689 {s%A2i|s%A2wi} %
0,%
1,%h2")
1691 (define_insn "lshrsi3_powerpc"
1692 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1693 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1694 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
1699 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
1700 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
1701 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
1703 (clobber (match_scratch:SI
3 "=r,r"))
1704 (clobber (match_scratch:SI
4 "=q,X"))]
1708 {s%A2i.|s%A2wi.} %
3,%
1,%h2"
1709 [(set_attr "type" "delayed_compare")])
1712 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1713 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1714 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1716 (clobber (match_scratch:SI
3 "=r"))]
1719 [(set_attr "type" "delayed_compare")])
1722 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
1723 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
1724 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
1726 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1727 (lshiftrt:SI (match_dup
1) (match_dup
2)))
1728 (clobber (match_scratch:SI
4 "=q,X"))]
1732 {s%A2i.|s%A2wi.} %
0,%
1,%h2"
1733 [(set_attr "type" "delayed_compare")])
1736 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1737 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1738 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1740 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1741 (lshiftrt:SI (match_dup
1) (match_dup
2)))]
1744 [(set_attr "type" "delayed_compare")])
1747 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1748 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1749 (match_operand:SI
2 "const_int_operand" "i"))
1750 (match_operand:SI
3 "mask_operand" "L")))]
1751 "includes_rshift_p (operands[
2], operands[
3])"
1752 "{rlinm|rlwinm} %
0,%
1,%s2,%m3,%M3")
1755 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1757 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1758 (match_operand:SI
2 "const_int_operand" "i"))
1759 (match_operand:SI
3 "mask_operand" "L"))
1761 (clobber (match_scratch:SI
4 "=r"))]
1762 "includes_rshift_p (operands[
2], operands[
3])"
1763 "{rlinm.|rlwinm.} %
4,%
1,%s2,%m3,%M3"
1764 [(set_attr "type" "delayed_compare")])
1767 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1769 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1770 (match_operand:SI
2 "const_int_operand" "i"))
1771 (match_operand:SI
3 "mask_operand" "L"))
1773 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1774 (and:SI (lshiftrt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
1775 "includes_rshift_p (operands[
2], operands[
3])"
1776 "{rlinm.|rlwinm.} %
0,%
1,%s2,%m3,%M3"
1777 [(set_attr "type" "delayed_compare")])
1780 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1783 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1784 (match_operand:SI
2 "const_int_operand" "i"))
0)))]
1785 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
1786 "{rlinm|rlwinm} %
0,%
1,%s2,
0xff")
1789 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1793 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1794 (match_operand:SI
2 "const_int_operand" "i"))
0))
1796 (clobber (match_scratch:SI
3 "=r"))]
1797 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
1798 "{rlinm.|rlwinm.} %
3,%
1,%s2,
0xff"
1799 [(set_attr "type" "delayed_compare")])
1802 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1806 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1807 (match_operand:SI
2 "const_int_operand" "i"))
0))
1809 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1810 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup
1) (match_dup
2))
0)))]
1811 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
1812 "{rlinm.|rlwinm.} %
0,%
1,%s2,
0xff"
1813 [(set_attr "type" "delayed_compare")])
1816 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1819 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1820 (match_operand:SI
2 "const_int_operand" "i"))
0)))]
1821 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
1822 "{rlinm|rlwinm} %
0,%
1,%s2,
0xffff")
1825 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1829 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1830 (match_operand:SI
2 "const_int_operand" "i"))
0))
1832 (clobber (match_scratch:SI
3 "=r"))]
1833 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
1834 "{rlinm.|rlwinm.} %
3,%
1,%s2,
0xffff"
1835 [(set_attr "type" "delayed_compare")])
1838 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1842 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1843 (match_operand:SI
2 "const_int_operand" "i"))
0))
1845 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1846 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup
1) (match_dup
2))
0)))]
1847 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
1848 "{rlinm.|rlwinm.} %
0,%
1,%s2,
0xffff"
1849 [(set_attr "type" "delayed_compare")])
1852 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
1854 (match_operand:SI
1 "gpc_reg_operand" "r"))
1855 (ashiftrt:SI (match_operand:SI
2 "gpc_reg_operand" "r")
1861 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
1863 (match_operand:SI
1 "gpc_reg_operand" "r"))
1864 (lshiftrt:SI (match_operand:SI
2 "gpc_reg_operand" "r")
1870 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
1872 (match_operand:SI
1 "gpc_reg_operand" "r"))
1873 (zero_extract:SI (match_operand:SI
2 "gpc_reg_operand" "r")
1879 (define_expand "ashrsi3"
1880 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1881 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "")
1882 (match_operand:SI
2 "reg_or_cint_operand" "")))]
1887 emit_insn (gen_ashrsi3_power (operands[
0], operands[
1], operands[
2]));
1889 emit_insn (gen_ashrsi3_powerpc (operands[
0], operands[
1], operands[
2]));
1893 (define_insn "ashrsi3_power"
1894 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1895 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
1896 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
1897 (clobber (match_scratch:SI
3 "=q,X"))]
1901 {srai|srawi} %
0,%
1,%h2")
1903 (define_insn "ashrsi3_powerpc"
1904 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1905 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1906 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
1911 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
1912 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
1913 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
1915 (clobber (match_scratch:SI
3 "=r,r"))
1916 (clobber (match_scratch:SI
4 "=q,X"))]
1920 {srai.|srawi.} %
3,%
1,%h2"
1921 [(set_attr "type" "delayed_compare")])
1924 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1925 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1926 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1928 (clobber (match_scratch:SI
3 "=r"))]
1931 [(set_attr "type" "delayed_compare")])
1934 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
1935 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
1936 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
1938 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1939 (ashiftrt:SI (match_dup
1) (match_dup
2)))
1940 (clobber (match_scratch:SI
4 "=q,X"))]
1945 [(set_attr "type" "delayed_compare")])
1948 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1949 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1950 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
1952 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1953 (ashiftrt:SI (match_dup
1) (match_dup
2)))]
1956 [(set_attr "type" "delayed_compare")])
1958 (define_expand "extendqisi2"
1959 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
1960 (use (match_operand:QI
1 "gpc_reg_operand" ""))]
1965 emit_insn (gen_extendqisi2_power (operands[
0], operands[
1]));
1967 emit_insn (gen_extendqisi2_powerpc (operands[
0], operands[
1]));
1971 (define_expand "extendqisi2_power"
1972 [(parallel [(set (match_dup
2)
1973 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
1975 (clobber (scratch:SI))])
1976 (parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
1977 (ashiftrt:SI (match_dup
2)
1979 (clobber (scratch:SI))])]
1982 { operands[
1] = gen_lowpart (SImode, operands[
1]);
1983 operands[
2] = gen_reg_rtx (SImode); }")
1985 (define_expand "extendqisi2_powerpc"
1987 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
1989 (set (match_operand:SI
0 "gpc_reg_operand" "")
1990 (ashiftrt:SI (match_dup
2)
1994 { operands[
1] = gen_lowpart (SImode, operands[
1]);
1995 operands[
2] = gen_reg_rtx (SImode); }")
1997 (define_expand "extendqihi2"
1998 [(use (match_operand:HI
0 "gpc_reg_operand" ""))
1999 (use (match_operand:QI
1 "gpc_reg_operand" ""))]
2004 emit_insn (gen_extendqihi2_power (operands[
0], operands[
1]));
2006 emit_insn (gen_extendqihi2_powerpc (operands[
0], operands[
1]));
2010 (define_expand "extendqihi2_power"
2011 [(parallel [(set (match_dup
2)
2012 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
2014 (clobber (scratch:SI))])
2015 (parallel [(set (match_operand:HI
0 "gpc_reg_operand" "")
2016 (ashiftrt:SI (match_dup
2)
2018 (clobber (scratch:SI))])]
2021 { operands[
0] = gen_lowpart (SImode, operands[
0]);
2022 operands[
1] = gen_lowpart (SImode, operands[
1]);
2023 operands[
2] = gen_reg_rtx (SImode); }")
2025 (define_expand "extendqihi2_powerpc"
2027 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
2029 (set (match_operand:HI
0 "gpc_reg_operand" "")
2030 (ashiftrt:SI (match_dup
2)
2034 { operands[
0] = gen_lowpart (SImode, operands[
0]);
2035 operands[
1] = gen_lowpart (SImode, operands[
1]);
2036 operands[
2] = gen_reg_rtx (SImode); }")
2038 ;; Floating-point insns, excluding normal data motion.
2040 ;; PowerPC has a full set of single-precision floating point instructions.
2042 ;; For the POWER architecture, we pretend that we have both SFmode and
2043 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2044 ;; The only conversions we will do will be when storing to memory. In that
2045 ;; case, we will use the "frsp" instruction before storing.
2047 ;; Note that when we store into a single-precision memory location, we need to
2048 ;; use the frsp insn first. If the register being stored isn't dead, we
2049 ;; need a scratch register for the frsp. But this is difficult when the store
2050 ;; is done by reload. It is not incorrect to do the frsp on the register in
2051 ;; this case, we just lose precision that we would have otherwise gotten but
2052 ;; is not guaranteed. Perhaps this should be tightened up at some point.
2054 (define_insn "extendsfdf2"
2055 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2056 (float_extend:DF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2060 if (REGNO (operands[
0]) == REGNO (operands[
1]))
2063 return
\"fmr %
0,%
1\";
2065 [(set_attr "type" "fp")])
2067 (define_insn "truncdfsf2"
2068 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2069 (float_truncate:SF (match_operand:DF
1 "gpc_reg_operand" "f")))]
2072 [(set_attr "type" "fp")])
2074 (define_insn "negsf2"
2075 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2076 (neg:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2079 [(set_attr "type" "fp")])
2081 (define_insn "abssf2"
2082 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2083 (abs:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2086 [(set_attr "type" "fp")])
2089 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2090 (neg:SF (abs:SF (match_operand:SF
1 "gpc_reg_operand" "f"))))]
2093 [(set_attr "type" "fp")])
2095 (define_expand "addsf3"
2096 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2097 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "")
2098 (match_operand:SF
2 "gpc_reg_operand" "")))]
2103 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2104 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2105 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2108 [(set_attr "type" "fp")])
2111 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2112 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2113 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2115 "{fa|fadd} %
0,%
1,%
2"
2116 [(set_attr "type" "fp")])
2118 (define_expand "subsf3"
2119 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2120 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "")
2121 (match_operand:SF
2 "gpc_reg_operand" "")))]
2126 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2127 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "f")
2128 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2131 [(set_attr "type" "fp")])
2134 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2135 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "f")
2136 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2138 "{fs|fsub} %
0,%
1,%
2"
2139 [(set_attr "type" "fp")])
2141 (define_expand "mulsf3"
2142 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2143 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "")
2144 (match_operand:SF
2 "gpc_reg_operand" "")))]
2149 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2150 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2151 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2154 [(set_attr "type" "fp")])
2157 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2158 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2159 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2161 "{fm|fmul} %
0,%
1,%
2"
2162 [(set_attr "type" "fp")])
2164 (define_expand "divsf3"
2165 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2166 (div:SF (match_operand:SF
1 "gpc_reg_operand" "")
2167 (match_operand:SF
2 "gpc_reg_operand" "")))]
2172 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2173 (div:SF (match_operand:SF
1 "gpc_reg_operand" "f")
2174 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2177 [(set_attr "type" "sdiv")])
2180 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2181 (div:SF (match_operand:SF
1 "gpc_reg_operand" "f")
2182 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2184 "{fd|fdiv} %
0,%
1,%
2"
2185 [(set_attr "type" "sdiv")])
2188 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2189 (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2190 (match_operand:SF
2 "gpc_reg_operand" "f"))
2191 (match_operand:SF
3 "gpc_reg_operand" "f")))]
2193 "fmadds %
0,%
1,%
2,%
3"
2194 [(set_attr "type" "fp")])
2197 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2198 (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2199 (match_operand:SF
2 "gpc_reg_operand" "f"))
2200 (match_operand:SF
3 "gpc_reg_operand" "f")))]
2202 "{fma|fmadd} %
0,%
1,%
2,%
3"
2203 [(set_attr "type" "fp")])
2206 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2207 (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2208 (match_operand:SF
2 "gpc_reg_operand" "f"))
2209 (match_operand:SF
3 "gpc_reg_operand" "f")))]
2211 "fmsubs %
0,%
1,%
2,%
3"
2212 [(set_attr "type" "fp")])
2215 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2216 (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2217 (match_operand:SF
2 "gpc_reg_operand" "f"))
2218 (match_operand:SF
3 "gpc_reg_operand" "f")))]
2220 "{fms|fmsub} %
0,%
1,%
2,%
3"
2221 [(set_attr "type" "fp")])
2224 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2225 (neg:SF (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2226 (match_operand:SF
2 "gpc_reg_operand" "f"))
2227 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
2229 "fnmadds %
0,%
1,%
2,%
3"
2230 [(set_attr "type" "fp")])
2233 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2234 (neg:SF (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2235 (match_operand:SF
2 "gpc_reg_operand" "f"))
2236 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
2238 "{fnma|fnmadd} %
0,%
1,%
2,%
3"
2239 [(set_attr "type" "fp")])
2242 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2243 (neg:SF (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2244 (match_operand:SF
2 "gpc_reg_operand" "f"))
2245 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
2247 "fnmsubs %
0,%
1,%
2,%
3"
2248 [(set_attr "type" "fp")])
2251 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2252 (neg:SF (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2253 (match_operand:SF
2 "gpc_reg_operand" "f"))
2254 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
2256 "{fnms|fnmsub} %
0,%
1,%
2,%
3"
2257 [(set_attr "type" "fp")])
2259 (define_expand "sqrtsf2"
2260 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2261 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "")))]
2262 "TARGET_POWERPCSQR || TARGET_POWER2"
2266 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2267 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2270 [(set_attr "type" "ssqrt")])
2273 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2274 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2277 [(set_attr "type" "dsqrt")])
2279 (define_insn "negdf2"
2280 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2281 (neg:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
2284 [(set_attr "type" "fp")])
2286 (define_insn "absdf2"
2287 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2288 (abs:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
2291 [(set_attr "type" "fp")])
2294 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2295 (neg:DF (abs:DF (match_operand:DF
1 "gpc_reg_operand" "f"))))]
2298 [(set_attr "type" "fp")])
2300 (define_insn "adddf3"
2301 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2302 (plus:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
2303 (match_operand:DF
2 "gpc_reg_operand" "f")))]
2305 "{fa|fadd} %
0,%
1,%
2"
2306 [(set_attr "type" "fp")])
2308 (define_insn "subdf3"
2309 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2310 (minus:DF (match_operand:DF
1 "gpc_reg_operand" "f")
2311 (match_operand:DF
2 "gpc_reg_operand" "f")))]
2313 "{fs|fsub} %
0,%
1,%
2"
2314 [(set_attr "type" "fp")])
2316 (define_insn "muldf3"
2317 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2318 (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
2319 (match_operand:DF
2 "gpc_reg_operand" "f")))]
2321 "{fm|fmul} %
0,%
1,%
2"
2322 [(set_attr "type" "dmul")])
2324 (define_insn "divdf3"
2325 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2326 (div:DF (match_operand:DF
1 "gpc_reg_operand" "f")
2327 (match_operand:DF
2 "gpc_reg_operand" "f")))]
2329 "{fd|fdiv} %
0,%
1,%
2"
2330 [(set_attr "type" "ddiv")])
2333 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2334 (plus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
2335 (match_operand:DF
2 "gpc_reg_operand" "f"))
2336 (match_operand:DF
3 "gpc_reg_operand" "f")))]
2338 "{fma|fmadd} %
0,%
1,%
2,%
3"
2339 [(set_attr "type" "dmul")])
2342 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2343 (minus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
2344 (match_operand:DF
2 "gpc_reg_operand" "f"))
2345 (match_operand:DF
3 "gpc_reg_operand" "f")))]
2347 "{fms|fmsub} %
0,%
1,%
2,%
3"
2348 [(set_attr "type" "dmul")])
2351 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2352 (neg:DF (plus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
2353 (match_operand:DF
2 "gpc_reg_operand" "f"))
2354 (match_operand:DF
3 "gpc_reg_operand" "f"))))]
2356 "{fnma|fnmadd} %
0,%
1,%
2,%
3"
2357 [(set_attr "type" "dmul")])
2360 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2361 (neg:DF (minus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
2362 (match_operand:DF
2 "gpc_reg_operand" "f"))
2363 (match_operand:DF
3 "gpc_reg_operand" "f"))))]
2365 "{fnms|fnmsub} %
0,%
1,%
2,%
3"
2366 [(set_attr "type" "dmul")])
2368 (define_insn "sqrtdf2"
2369 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2370 (sqrt:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
2371 "TARGET_POWERPCSQR | TARGET_POWER2"
2373 [(set_attr "type" "dsqrt")])
2375 ;; Conversions to and from floating-point.
2376 (define_expand "floatsidf2"
2378 (plus:DI (zero_extend:DI
2379 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
2382 (set (match_operand:DF
0 "gpc_reg_operand" "")
2383 (minus:DF (subreg:DF (match_dup
2)
0)
2388 #if HOST_BITS_PER_INT != BITS_PER_WORD
2389 /* Maybe someone can figure out how to do this in that case. I don't
2390 want to right now. */
2394 operands[
2] = gen_reg_rtx (DImode);
2395 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
0x80000000);
2396 operands[
4] = immed_double_const (
0,
0x43300000, DImode);
2397 operands[
5] = force_reg (DFmode, immed_double_const (
0x43300000,
2398 0x80000000, DFmode));
2401 (define_expand "floatunssidf2"
2403 (plus:DI (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
2405 (set (match_operand:DF
0 "gpc_reg_operand" "")
2406 (minus:DF (subreg:DF (match_dup
2)
0)
2411 #if HOST_BITS_PER_INT != BITS_PER_WORD
2412 /* Maybe someone can figure out how to do this in that case. I don't
2413 want to right now. */
2417 operands[
2] = gen_reg_rtx (DImode);
2418 operands[
3] = immed_double_const (
0,
0x43300000, DImode);
2419 operands[
4] = force_reg (DFmode, immed_double_const (
0x43300000,
0, DFmode));
2422 ;; For the above two cases, we always split.
2424 [(set (match_operand:DI
0 "gpc_reg_operand" "")
2425 (plus:DI (zero_extend:DI
2426 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
2427 (match_operand:SI
2 "logical_operand" "")))
2428 (match_operand:DI
3 "immediate_operand" "")))]
2429 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
2430 && GET_CODE (operands[
3]) == CONST_DOUBLE
2431 && CONST_DOUBLE_LOW (operands[
3]) ==
0"
2432 [(set (match_dup
6) (xor:SI (match_dup
1) (match_dup
2)))
2433 (set (match_dup
4) (match_dup
5))]
2435 { operands[
4] = operand_subword (operands[
0],
0,
0, DImode);
2436 operands[
5] = operand_subword (operands[
3],
0,
0, DImode);
2437 operands[
6] = operand_subword (operands[
0],
1,
0, DImode);
2441 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2442 (plus:DI (zero_extend:DI
2443 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
2444 (match_operand:SI
2 "logical_operand" "rKJ")))
2445 (match_operand:DI
3 "immediate_operand" "n")))]
2446 "HOST_BITS_PER_INT == BITS_PER_WORD
2447 && GET_CODE (operands[
3]) == CONST_DOUBLE
2448 && CONST_DOUBLE_LOW (operands[
3]) ==
0"
2452 [(set (match_operand:DI
0 "gpc_reg_operand" "=")
2453 (plus:DI (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
2454 (match_operand:DI
2 "immediate_operand" "")))]
2455 "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
2456 && GET_CODE (operands[
2]) == CONST_DOUBLE
2457 && CONST_DOUBLE_LOW (operands[
2]) ==
0"
2458 [(set (match_dup
3) (match_dup
4))
2459 (set (match_dup
5) (match_dup
1))]
2461 { operands[
3] = operand_subword (operands[
0],
0,
0, DImode);
2462 operands[
4] = operand_subword (operands[
2],
0,
0, DImode);
2463 operands[
5] = operand_subword (operands[
0],
1,
0, DImode);
2465 if (rtx_equal_p (operands[
1], operands[
5]))
2467 emit_move_insn (operands[
3], operands[
4]);
2471 if (rtx_equal_p (operands[
1], operands[
3]))
2475 temp = operands[
3]; operands[
3] = operands[
5]; operands[
5] = temp;
2476 temp = operands[
4]; operands[
4] = operands[
1]; operands[
1] = temp;
2481 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2482 (plus:DI (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
2483 (match_operand:DI
2 "immediate_operand" "n")))]
2484 "HOST_BITS_PER_INT == BITS_PER_WORD
2485 && GET_CODE (operands[
2]) == CONST_DOUBLE
2486 && CONST_DOUBLE_LOW (operands[
2]) ==
0"
2489 (define_expand "fix_truncdfsi2"
2490 [(set (match_operand:SI
0 "gpc_reg_operand" "")
2491 (fix:SI (match_operand:DF
1 "gpc_reg_operand" "")))]
2495 emit_insn (gen_trunc_call (operands[
0], operands[
1],
2496 gen_rtx (SYMBOL_REF, Pmode,
\"itrunc
\")));
2500 (define_expand "fixuns_truncdfsi2"
2501 [(set (match_operand:SI
0 "gpc_reg_operand" "")
2502 (unsigned_fix:SI (match_operand:DF
1 "gpc_reg_operand" "")))]
2506 emit_insn (gen_trunc_call (operands[
0], operands[
1],
2507 gen_rtx (SYMBOL_REF, Pmode,
\"uitrunc
\")));
2512 (define_expand "trunc_call"
2513 [(parallel [(set (match_operand:SI
0 "" "")
2514 (fix:SI (match_operand:DF
1 "" "")))
2515 (use (match_operand:SI
2 "" ""))])]
2519 rtx insns = gen_trunc_call_rtl (operands[
0], operands[
1], operands[
2]);
2520 rtx first = XVECEXP (insns,
0,
0);
2521 rtx last = XVECEXP (insns,
0, XVECLEN (insns,
0) -
1);
2523 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
2525 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
2531 (define_expand "trunc_call_rtl"
2532 [(set (reg:DF
33) (match_operand:DF
1 "gpc_reg_operand" ""))
2534 (parallel [(set (reg:SI
3)
2535 (call (mem:SI (match_operand
2 "" "")) (const_int
0)))
2536 (clobber (scratch:SI))])
2537 (set (match_operand:SI
0 "gpc_reg_operand" "")
2542 rs6000_trunc_used =
1;
2545 ;; Define the DImode operations that can be done in a small number
2547 (define_expand "adddi3"
2548 [(set (match_operand:DI
0 "gpc_reg_operand" "")
2549 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "")
2550 (match_operand:DI
2 "reg_or_short_operand" "")))]
2555 && short_cint_operand (operands[
2], DImode))
2560 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
2561 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r")
2562 (match_operand:DI
2 "reg_or_short_operand" "r,I")))]
2565 {a|addc} %L0,%L1,%L2\;{ae|adde} %
0,%
1,%
2
2566 {ai|addic} %L0,%L1,%
2\;{a%G2e|add%G2e} %
0,%
1"
2567 [(set_attr "length" "
8")])
2570 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2571 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
2572 (match_operand:DI
2 "gpc_reg_operand" "r")))]
2574 "addc %L0,%L1,%L2\;adde %
0,%
1,%
2"
2575 [(set_attr "length" "
8")])
2577 (define_expand "subdi3"
2578 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
2579 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "r,I")
2580 (match_operand:DI
2 "gpc_reg_operand" "r,r")))]
2585 && short_cint_operand (operands[
1], DImode))
2590 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
2591 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "r,I")
2592 (match_operand:DI
2 "gpc_reg_operand" "r,r")))]
2595 {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %
0,%
2,%
1
2596 {sfi|subfic} %L0,%L2,%
1\;{sf%G1e|subf%G1e} %
0,%
2"
2597 [(set_attr "length" "
8")])
2600 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2601 (minus:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2602 (match_operand:DI
2 "gpc_reg_operand" "r")))]
2604 "subfc %L0,%L2,%L1\;subfe %
0,%
2,%
1"
2605 [(set_attr "length" "
8")])
2607 (define_expand "negdi2"
2608 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2609 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
2614 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2615 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
2617 "{sfi|subfic} %L0,%L1,
0\;{sfze|subfze} %
0,%
1"
2618 [(set_attr "length" "
8")])
2621 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2622 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
2624 "subfic %L0,%L1,
0\;subfze %
0,%
1"
2625 [(set_attr "length" "
8")])
2627 (define_insn "mulsidi3"
2628 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2629 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
2630 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))
2631 (clobber (match_scratch:SI
3 "=q"))]
2633 "mul %
0,%
1,%
2\;mfmq %L0"
2634 [(set_attr "length" "
8")])
2636 ;; If operands
0 and
2 are in the same register, we have a problem. But
2637 ;; operands
0 and
1 (the usual case) can be in the same register. That's
2638 ;; why we have the strange constraints below.
2639 (define_insn "ashldi3"
2640 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r,&r")
2641 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r,r,
0,r")
2642 (match_operand:SI
2 "reg_or_cint_operand" "M,i,r,r")))
2643 (clobber (match_scratch:SI
3 "=X,q,q,q"))]
2646 {sli|slwi} %
0,%L1,%h2\;{cal %L0,
0(
0)|li %L0,
0}
2647 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2
2648 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2
2649 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2"
2650 [(set_attr "length" "
8")])
2652 (define_insn "lshrdi3"
2653 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r,r,&r")
2654 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r,r,
0,r")
2655 (match_operand:SI
2 "reg_or_cint_operand" "M,i,r,r")))
2656 (clobber (match_scratch:SI
3 "=X,q,q,q"))]
2659 {cal %
0,
0(
0)|li %
0,
0}\;{s%A2i|s%A2wi} %L0,%
1,%h2
2660 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2
2661 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2
2662 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2"
2663 [(set_attr "length" "
8")])
2665 ;; Shift by a variable amount is too complex to be worth open-coding. We
2666 ;; just handle shifts by constants.
2668 (define_expand "ashrdi3"
2669 [(parallel [(set (match_operand:DI
0 "gpc_reg_operand" "=")
2670 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "")
2671 (match_operand:SI
2 "general_operand" "")))
2672 (clobber (match_scratch:SI
3 ""))])]
2675 { if (GET_CODE (operands[
2]) != CONST_INT)
2680 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
2681 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r,r")
2682 (match_operand:SI
2 "const_int_operand" "M,i")))
2683 (clobber (match_scratch:SI
3 "=X,q"))]
2686 {srai|srawi} %
0,%
1,
31\;{srai|srawi} %L0,%
1,%h2
2687 sraiq %
0,%
1,%h2\;srliq %L0,%L1,%h2"
2688 [(set_attr "length" "
8")])
2690 ;; Now define ways of moving data around.
2692 ;; For SI, we special-case integers that can't be loaded in one insn. We
2693 ;; do the load
16-bits at a time. We could do this by loading from memory,
2694 ;; and this is even supposed to be faster, but it is simpler not to get
2695 ;; integers in the TOC.
2696 (define_expand "movsi"
2697 [(set (match_operand:SI
0 "general_operand" "")
2698 (match_operand:SI
1 "any_operand" ""))]
2702 if (GET_CODE (operands[
0]) != REG)
2703 operands[
1] = force_reg (SImode, operands[
1]);
2705 if (CONSTANT_P (operands[
1]) && GET_CODE (operands[
1]) != CONST_INT
2706 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[
1]))
2708 operands[
1] = force_const_mem (SImode, operands[
1]);
2709 if (! memory_address_p (SImode, XEXP (operands[
1],
0))
2710 && ! reload_in_progress)
2711 operands[
1] = change_address (operands[
1], SImode,
2712 XEXP (operands[
1],
0));
2715 if (GET_CODE (operands[
1]) == CONST_INT
2716 && (unsigned) (INTVAL (operands[
1]) +
0x8000) >=
0x10000
2717 && (INTVAL (operands[
1]) &
0xffff) !=
0)
2719 emit_move_insn (operands[
0],
2720 gen_rtx (CONST_INT, VOIDmode,
2721 INTVAL (operands[
1]) &
0xffff0000));
2722 emit_insn (gen_iorsi3 (operands[
0], operands[
0],
2723 gen_rtx (CONST_INT, VOIDmode,
2724 INTVAL (operands[
1]) &
0xffff)));
2730 [(set (match_operand:SI
0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l,*h")
2731 (match_operand:SI
1 "input_operand" "r,m,r,I,J,*h,r,r,
0"))]
2732 "TARGET_POWER && (gpc_reg_operand (operands[
0], SImode)
2733 || gpc_reg_operand (operands[
1], SImode))"
2736 {l%U1%X1|lwz%U1%X1} %
0,%
1
2737 {st%U0%X0|stw%U0%X0} %
1,%
0
2738 {cal %
0,%
1(
0)|li %
0,%
1}
2739 {cau %
0,
0,%u1|lis %
0,%u1}
2744 [(set_attr "type" "*,load,*,*,*,*,*,mtlr,*")])
2747 [(set (match_operand:SI
0 "nonimmediate_operand" "=r,r,m,r,r,r,*h")
2748 (match_operand:SI
1 "input_operand" "r,m,r,I,J,*h,r"))]
2749 "TARGET_POWERPC && (gpc_reg_operand (operands[
0], SImode)
2750 || gpc_reg_operand (operands[
1], SImode))"
2759 [(set_attr "type" "*,load,*,*,*,*,*")])
2761 ;; Split a load of a large constant into the appropriate two-insn
2765 [(set (match_operand:SI
0 "gpc_reg_operand" "")
2766 (match_operand:SI
1 "const_int_operand" ""))]
2767 "(unsigned) (INTVAL (operands[
1]) +
0x8000) >=
0x10000
2768 && (INTVAL (operands[
1]) &
0xffff) !=
0"
2772 (ior:SI (match_dup
0)
2776 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
2777 INTVAL (operands[
1]) &
0xffff0000);
2778 operands[
3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
1]) &
0xffff);
2782 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
2783 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
2785 (set (match_operand:SI
0 "gpc_reg_operand" "=r") (match_dup
1))]
2787 "{ai.|addic.} %
0,%
1,
0"
2788 [(set_attr "type" "compare")])
2790 (define_expand "movhi"
2791 [(set (match_operand:HI
0 "general_operand" "")
2792 (match_operand:HI
1 "any_operand" ""))]
2796 if (GET_CODE (operands[
0]) != REG)
2797 operands[
1] = force_reg (HImode, operands[
1]);
2799 if (CONSTANT_P (operands[
1]) && GET_CODE (operands[
1]) != CONST_INT)
2801 operands[
1] = force_const_mem (HImode, operands[
1]);
2802 if (! memory_address_p (HImode, XEXP (operands[
1],
0))
2803 && ! reload_in_progress)
2804 operands[
1] = change_address (operands[
1], HImode,
2805 XEXP (operands[
1],
0));
2810 [(set (match_operand:HI
0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
2811 (match_operand:HI
1 "input_operand" "r,m,r,i,*h,r,
0"))]
2812 "TARGET_POWER && (gpc_reg_operand (operands[
0], HImode)
2813 || gpc_reg_operand (operands[
1], HImode))"
2818 {cal %
0,%w1(
0)|li %
0,%w1}
2822 [(set_attr "type" "*,load,*,*,*,*,*")])
2825 [(set (match_operand:HI
0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2826 (match_operand:HI
1 "input_operand" "r,m,r,i,*h,r"))]
2827 "TARGET_POWERPC && (gpc_reg_operand (operands[
0], HImode)
2828 || gpc_reg_operand (operands[
1], HImode))"
2836 [(set_attr "type" "*,load,*,*,*,*")])
2838 (define_expand "movqi"
2839 [(set (match_operand:QI
0 "general_operand" "")
2840 (match_operand:QI
1 "any_operand" ""))]
2844 if (GET_CODE (operands[
0]) != REG)
2845 operands[
1] = force_reg (QImode, operands[
1]);
2847 if (CONSTANT_P (operands[
1]) && GET_CODE (operands[
1]) != CONST_INT)
2849 operands[
1] = force_const_mem (QImode, operands[
1]);
2850 if (! memory_address_p (QImode, XEXP (operands[
1],
0))
2851 && ! reload_in_progress)
2852 operands[
1] = change_address (operands[
1], QImode,
2853 XEXP (operands[
1],
0));
2858 [(set (match_operand:QI
0 "nonimmediate_operand" "=r,r,m,r,r,*h,*h")
2859 (match_operand:QI
1 "input_operand" "r,m,r,i,*h,r,
0"))]
2860 "TARGET_POWER && (gpc_reg_operand (operands[
0], QImode)
2861 || gpc_reg_operand (operands[
1], QImode))"
2866 {cal %
0,%
1(
0)|li %
0,%
1}
2870 [(set_attr "type" "*,load,*,*,*,*,*")])
2873 [(set (match_operand:QI
0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2874 (match_operand:QI
1 "input_operand" "r,m,r,i,*h,r"))]
2875 "TARGET_POWERPC && (gpc_reg_operand (operands[
0], QImode)
2876 || gpc_reg_operand (operands[
1], QImode))"
2884 [(set_attr "type" "*,load,*,*,*,*")])
2886 ;; Here is how to move condition codes around. When we store CC data in
2887 ;; an integer register or memory, we store just the high-order
4 bits.
2888 ;; This lets us not shift in the most common case of CR0.
2889 (define_expand "movcc"
2890 [(set (match_operand:CC
0 "nonimmediate_operand" "")
2891 (match_operand:CC
1 "nonimmediate_operand" ""))]
2896 [(set (match_operand:CC
0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
2897 (match_operand:CC
1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
2898 "register_operand (operands[
0], CCmode)
2899 || register_operand (operands[
1], CCmode)"
2903 {rlinm|rlwinm} %
1,%
1,%F0,
0xffffffff\;mtcrf %R0,%
1\;{rlinm|rlwinm} %
1,%
1,%f0,
0xffffffff
2905 mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%f1,
0xf0000000
2906 {ai %
0,%
1,
0|mr %
0,%
1}
2907 {l%U1%X1|lwz%U1%X1} %
0,%
1
2908 {st%U0%U1|stw%U0%U1} %
1,%
0"
2909 [(set_attr "type" "*,*,*,compare,*,*,load,*")
2910 (set_attr "length" "*,*,
12,*,
8,*,*,*")])
2912 ;; For floating-point, we normally deal with the floating-point registers.
2913 ;; The sole exception is that parameter passing can produce floating-point
2914 ;; values in fixed-point registers. Unless the value is a simple constant
2915 ;; or already in memory, we deal with this by allocating memory and copying
2916 ;; the value explicitly via that memory location.
2917 (define_expand "movsf"
2918 [(set (match_operand:SF
0 "nonimmediate_operand" "")
2919 (match_operand:SF
1 "any_operand" ""))]
2923 /* If we are called from reload, we might be getting a SUBREG of a hard
2924 reg. So expand it. */
2925 if (GET_CODE (operands[
0]) == SUBREG
2926 && GET_CODE (SUBREG_REG (operands[
0])) == REG
2927 && REGNO (SUBREG_REG (operands[
0])) < FIRST_PSEUDO_REGISTER)
2928 operands[
0] = alter_subreg (operands[
0]);
2929 if (GET_CODE (operands[
1]) == SUBREG
2930 && GET_CODE (SUBREG_REG (operands[
1])) == REG
2931 && REGNO (SUBREG_REG (operands[
1])) < FIRST_PSEUDO_REGISTER)
2932 operands[
1] = alter_subreg (operands[
1]);
2934 if (GET_CODE (operands[
1]) == REG && REGNO (operands[
1]) <
32)
2938 /* If this is a store to memory or another integer register do the
2939 move directly. Otherwise store to a temporary stack slot and
2940 load from there into a floating point register. */
2942 if (GET_CODE (operands[
0]) == MEM
2943 || (GET_CODE (operands[
0]) == REG
2944 && (REGNO (operands[
0]) <
32
2945 || (reload_in_progress
2946 && REGNO (operands[
0]) >= FIRST_PSEUDO_REGISTER))))
2948 emit_move_insn (operand_subword (operands[
0],
0,
0, SFmode),
2949 operand_subword (operands[
1],
0,
0, SFmode));
2953 stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx,
4));
2954 emit_move_insn (stack_slot, operands[
1]);
2955 emit_move_insn (operands[
0], stack_slot);
2959 if (GET_CODE (operands[
0]) == MEM)
2960 operands[
1] = force_reg (SFmode, operands[
1]);
2962 if (GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <
32)
2966 if (GET_CODE (operands[
1]) == MEM
2967 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2968 || GET_CODE (operands[
1]) == CONST_DOUBLE
2970 || (GET_CODE (operands[
1]) == REG && REGNO (operands[
1]) <
32)
2971 || (reload_in_progress && GET_CODE (operands[
1]) == REG
2972 && REGNO (operands[
1]) >= FIRST_PSEUDO_REGISTER))
2974 emit_move_insn (operand_subword (operands[
0],
0,
0, SFmode),
2975 operand_subword (operands[
1],
0,
0, SFmode));
2979 if (reload_in_progress)
2980 stack_slot = gen_rtx (MEM, SFmode,
2981 plus_constant (stack_pointer_rtx,
4));
2983 stack_slot = assign_stack_temp (SFmode,
4,
0);
2984 emit_move_insn (stack_slot, operands[
1]);
2985 emit_move_insn (operands[
0], stack_slot);
2989 if (CONSTANT_P (operands[
1]))
2991 operands[
1] = force_const_mem (SFmode, operands[
1]);
2992 if (! memory_address_p (SFmode, XEXP (operands[
1],
0))
2993 && ! reload_in_progress)
2994 operands[
1] = change_address (operands[
1], SFmode,
2995 XEXP (operands[
1],
0));
3000 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3001 (match_operand:SF
1 "easy_fp_constant" ""))]
3002 "reload_completed && REGNO (operands[
0]) <=
31"
3003 [(set (match_dup
2) (match_dup
3))]
3005 { operands[
2] = operand_subword (operands[
0],
0,
0, SFmode);
3006 operands[
3] = operand_subword (operands[
1],
0,
0, SFmode); }")
3009 [(set (match_operand:SF
0 "fp_reg_or_mem_operand" "=f,f,m")
3010 (match_operand:SF
1 "input_operand" "f,m,f"))]
3011 "gpc_reg_operand (operands[
0], SFmode)
3012 || gpc_reg_operand (operands[
1], SFmode)"
3016 frsp %
1,%
1\;stfs%U0%X0 %
1,%
0"
3017 [(set_attr "type" "fp,fpload,*")
3018 (set_attr "length" "*,*,
8")])
3020 (define_expand "movdf"
3021 [(set (match_operand:DF
0 "nonimmediate_operand" "")
3022 (match_operand:DF
1 "any_operand" ""))]
3026 if (GET_CODE (operands[
0]) == MEM && GET_CODE (operands[
1]) == MEM)
3028 emit_move_insn (operand_subword (operands[
0],
1,
1, DFmode),
3029 operand_subword_force (operands[
1],
1, DFmode));
3030 emit_move_insn (operand_subword (operands[
0],
0,
1, DFmode),
3031 operand_subword_force (operands[
1],
0, DFmode));
3035 if (GET_CODE (operands[
0]) != REG)
3036 operands[
1] = force_reg (DFmode, operands[
1]);
3038 if (CONSTANT_P (operands[
1]) && ! easy_fp_constant (operands[
1], DFmode))
3040 operands[
1] = force_const_mem (DFmode, operands[
1]);
3041 if (! memory_address_p (DFmode, XEXP (operands[
1],
0))
3042 && ! reload_in_progress)
3043 operands[
1] = change_address (operands[
1], DFmode,
3044 XEXP (operands[
1],
0));
3049 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3050 (match_operand:DF
1 "easy_fp_constant" ""))]
3051 "reload_completed && REGNO (operands[
0]) <=
31"
3052 [(set (match_dup
2) (match_dup
3))
3053 (set (match_dup
4) (match_dup
5))]
3055 { operands[
2] = operand_subword (operands[
0],
0,
0, DFmode);
3056 operands[
3] = operand_subword (operands[
1],
0,
0, DFmode);
3057 operands[
4] = operand_subword (operands[
0],
1,
0, DFmode);
3058 operands[
5] = operand_subword (operands[
1],
1,
0, DFmode); }")
3061 [(set (match_operand:DF
0 "nonimmediate_operand" "=!r,r,o,r,f,f,m")
3062 (match_operand:DF
1 "input_operand" "r,o,r,G,f,m,f"))]
3063 "register_operand (operands[
0], DFmode)
3064 || register_operand (operands[
1], DFmode)"
3067 switch (which_alternative)
3070 /* We normally copy the low-numbered register first. However, if
3071 the first register operand
0 is the same as the second register of
3072 operand
1, we must copy in the opposite order. */
3073 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
3074 return
\"{oril %L0,%L1,
0|mr %L0,%L1}\;{oril %
0,%
1,
0|mr %
0,%
1}
\";
3076 return
\"{oril %
0,%
1,
0|mr %
0,%
1}\;{oril %L0,%L1,
0|mr %L0,%L1}
\";
3078 /* If the low-address word is used in the address, we must load it
3079 last. Otherwise, load it first. Note that we cannot have
3080 auto-increment in that case since the address register is known to be
3082 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
3084 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
3086 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
3088 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
3092 return
\"fmr %
0,%
1\";
3094 return
\"lfd%U1%X1 %
0,%
1\";
3096 return
\"stfd%U0%X0 %
1,%
0\";
3099 [(set_attr "type" "*,load,*,*,fp,fpload,*")
3100 (set_attr "length" "
8,
8,
8,
8,*,*,*")])
3102 ;; Next come the multi-word integer load and store and the load and store
3104 (define_expand "movdi"
3105 [(set (match_operand:DI
0 "general_operand" "")
3106 (match_operand:DI
1 "general_operand" ""))]
3110 if (GET_CODE (operands[
1]) == CONST_DOUBLE
3111 || GET_CODE (operands[
1]) == CONST_INT)
3113 emit_move_insn (operand_subword (operands[
0],
0,
0, DImode),
3114 operand_subword (operands[
1],
0,
0, DImode));
3115 emit_move_insn (operand_subword (operands[
0],
1,
0, DImode),
3116 operand_subword (operands[
1],
1,
0, DImode));
3120 if (GET_CODE (operands[
0]) == MEM)
3121 operands[
1] = force_reg (DImode, operands[
1]);
3125 [(set (match_operand:DI
0 "nonimmediate_operand" "=r,r,m")
3126 (match_operand:DI
1 "input_operand" "r,m,r"))]
3127 "gpc_reg_operand (operands[
0], DImode)
3128 || gpc_reg_operand (operands[
1], DImode)"
3131 switch (which_alternative)
3134 /* We normally copy the low-numbered register first. However, if
3135 the first register operand
0 is the same as the second register of
3136 operand
1, we must copy in the opposite order. */
3137 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
3138 return
\"{oril %L0,%L1,
0|mr %L0,%L1}\;{oril %
0,%
1,
0|mr %
0,%
1}
\";
3140 return
\"{oril %
0,%
1,
0|mr %
0,%
1}\;{oril %L0,%L1,
0|mr %L0,%L1}
\";
3142 /* If the low-address word is used in the address, we must load it
3143 last. Otherwise, load it first. Note that we cannot have
3144 auto-increment in that case since the address register is known to be
3146 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
3148 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
3150 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
3152 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
3155 [(set_attr "type" "*,load,*")
3156 (set_attr "length" "
8")])
3158 ;; TImode is similar, except that we usually want to compute the address into
3159 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
3160 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
3161 (define_expand "movti"
3162 [(parallel [(set (match_operand:TI
0 "general_operand" "")
3163 (match_operand:TI
1 "general_operand" ""))
3164 (clobber (scratch:SI))])]
3168 if (GET_CODE (operands[
0]) == MEM)
3169 operands[
1] = force_reg (TImode, operands[
1]);
3171 if (GET_CODE (operands[
0]) == MEM
3172 && GET_CODE (XEXP (operands[
0],
0)) != REG
3173 && ! reload_in_progress)
3174 operands[
0] = change_address (operands[
0], TImode,
3175 copy_addr_to_reg (XEXP (operands[
0],
0)));
3177 if (GET_CODE (operands[
1]) == MEM
3178 && GET_CODE (XEXP (operands[
1],
0)) != REG
3179 && ! reload_in_progress)
3180 operands[
1] = change_address (operands[
1], TImode,
3181 copy_addr_to_reg (XEXP (operands[
1],
0)));
3184 ;; We say that MQ is clobbered in the last alternative because the first
3185 ;; alternative would never get used otherwise since it would need a reload
3186 ;; while the
2nd alternative would not. We put memory cases first so they
3187 ;; are preferred. Otherwise, we'd try to reload the output instead of
3188 ;; giving the SCRATCH mq.
3190 [(set (match_operand:TI
0 "reg_or_mem_operand" "=Q,m,r,r,r")
3191 (match_operand:TI
1 "reg_or_mem_operand" "r,r,r,Q,m"))
3192 (clobber (match_scratch:SI
2 "=q,q#X,X,X,X"))]
3193 "TARGET_POWER && (gpc_reg_operand (operands[
0], TImode)
3194 || gpc_reg_operand (operands[
1], TImode))"
3197 switch (which_alternative)
3200 return
\"{stsi|stswi} %
1,%P0,
16\";
3203 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0
\";
3206 /* Normally copy registers with lowest numbered register copied first.
3207 But copy in the other order if the first register of the output
3208 is the second, third, or fourth register in the input. */
3209 if (REGNO (operands[
0]) >= REGNO (operands[
1]) +
1
3210 && REGNO (operands[
0]) <= REGNO (operands[
1]) +
3)
3211 return
\"{oril %Z0,%Z1,
0|mr %Z0,%Z1}\;{oril %Y0,%Y1,
0|mr %Y0,%Y1}\;{oril %L0,%L1,
0|mr %L0,%L1}\;{oril %
0,%
1,
0|mr %
0,%
1}
\";
3213 return
\"{oril %
0,%
1,
0|mr %
0,%
1}\;{oril %L0,%L1,
0|mr %L0,%L1}\;{oril %Y0,%Y1,
0|mr %Y0,%Y1}\;{oril %Z0,%Z1,
0|mr %Z0,%Z1}
\";
3215 /* If the address is not used in the output, we can use lsi. Otherwise,
3216 fall through to generating four loads. */
3217 if (! reg_overlap_mentioned_p (operands[
0], operands[
1]))
3218 return
\"{lsi|lswi} %
0,%P1,
16\";
3219 /* ... fall through ... */
3221 /* If the address register is the same as the register for the lowest-
3222 addressed word, load it last. Similarly for the next two words.
3223 Otherwise load lowest address to highest. */
3224 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
3226 return
\"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %
0,%
1\";
3227 else if (refers_to_regno_p (REGNO (operands[
0]) +
1,
3228 REGNO (operands[
0]) +
2, operands[
1],
0))
3229 return
\"{l|lwz} %
0,%
1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1
\";
3230 else if (refers_to_regno_p (REGNO (operands[
0]) +
2,
3231 REGNO (operands[
0]) +
3, operands[
1],
0))
3232 return
\"{l|lwz} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1
\";
3234 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1
\";
3237 [(set_attr "type" "*,load,load,*,*")
3238 (set_attr "length" "*,
16,
16,*,
16")])
3240 (define_expand "load_multiple"
3241 [(match_par_dup
3 [(set (match_operand:SI
0 "" "")
3242 (match_operand:SI
1 "" ""))
3243 (use (match_operand:SI
2 "" ""))])]
3252 /* Support only loading a constant number of fixed-point registers from
3253 memory and only bother with this if more than two; the machine
3254 doesn't support more than eight. */
3255 if (GET_CODE (operands[
2]) != CONST_INT
3256 || INTVAL (operands[
2]) <=
2
3257 || INTVAL (operands[
2]) >
8
3258 || GET_CODE (operands[
1]) != MEM
3259 || GET_CODE (operands[
0]) != REG
3260 || REGNO (operands[
0]) >=
32)
3263 count = INTVAL (operands[
2]);
3264 regno = REGNO (operands[
0]);
3266 operands[
3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
3267 from = force_reg (SImode, XEXP (operands[
1],
0));
3269 for (i =
0; i < count; i++)
3270 XVECEXP (operands[
3],
0, i)
3271 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
3272 gen_rtx (MEM, SImode, plus_constant (from, i *
4)));
3276 [(match_parallel
0 "load_multiple_operation"
3277 [(set (match_operand:SI
1 "gpc_reg_operand" "=r")
3278 (match_operand:SI
2 "indirect_operand" "Q"))])]
3282 /* We have to handle the case where the pseudo used to contain the address
3283 is assigned to one of the output registers. In that case, do the
3284 lsi, but then load the correct value. This is a bit of a mess, but is
3286 We set the length attribute to the maximum possible size (
8 bytes). */
3287 static char result[
100];
3291 strcpy (result,
\"{lsi|lswi} %
1,%P2,%N0
\");
3292 for (i =
0; i < XVECLEN (operands[
0],
0); i++)
3293 if (refers_to_regno_p (REGNO (operands[
1]) + i,
3294 REGNO (operands[
1]) + i +
1, operands[
2],
0))
3296 sprintf (newload,
\"\;{l|lwz} %d,%d(%d)
\",
3297 REGNO (operands[
1]) + i,
3298 i *
4, REGNO (XEXP (operands[
2],
0)));
3299 strcat (result, newload);
3304 [(set_attr "type" "load")
3305 (set_attr "length" "
8")])
3308 (define_expand "store_multiple"
3309 [(match_par_dup
3 [(set (match_operand:SI
0 "" "")
3310 (match_operand:SI
1 "" ""))
3311 (clobber (scratch:SI))
3312 (use (match_operand:SI
2 "" ""))])]
3321 /* Support only storing a constant number of fixed-point registers to
3322 memory and only bother with this if more than two; the machine
3323 doesn't support more than eight. */
3324 if (GET_CODE (operands[
2]) != CONST_INT
3325 || INTVAL (operands[
2]) <=
2
3326 || INTVAL (operands[
2]) >
8
3327 || GET_CODE (operands[
0]) != MEM
3328 || GET_CODE (operands[
1]) != REG
3329 || REGNO (operands[
1]) >=
32)
3332 count = INTVAL (operands[
2]);
3333 regno = REGNO (operands[
1]);
3335 operands[
3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count +
1));
3336 to = force_reg (SImode, XEXP (operands[
0],
0));
3338 XVECEXP (operands[
3],
0,
0)
3339 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[
1]);
3340 XVECEXP (operands[
3],
0,
1) = gen_rtx (CLOBBER, VOIDmode,
3341 gen_rtx (SCRATCH, SImode));
3343 for (i =
1; i < count; i++)
3344 XVECEXP (operands[
3],
0, i +
1)
3345 = gen_rtx (SET, VOIDmode,
3346 gen_rtx (MEM, SImode, plus_constant (to, i *
4)),
3347 gen_rtx (REG, SImode, regno + i));
3351 [(match_parallel
0 "store_multiple_operation"
3352 [(set (match_operand:SI
1 "indirect_operand" "=Q")
3353 (match_operand:SI
2 "gpc_reg_operand" "r"))
3354 (clobber (match_scratch:SI
3 "=q"))])]
3356 "{stsi|stswi} %
2,%P1,%O0")
3358 ;; Define insns that do load or store with update. Some of these we can
3359 ;; get by using pre-decrement or pre-increment, but the hardware can also
3360 ;; do cases where the increment is not the size of the object.
3362 ;; In all these cases, we use operands
0 and
1 for the register being
3363 ;; incremented because those are the operands that local-alloc will
3364 ;; tie and these are the pair most likely to be tieable (and the ones
3365 ;; that will benefit the most).
3368 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
3369 (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3370 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
3371 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3372 (plus:SI (match_dup
1) (match_dup
2)))]
3375 {lux|lwzux} %
3,%
0,%
2
3376 {lu|lwzu} %
3,%
2(%
0)"
3377 [(set_attr "type" "load")])
3380 [(set (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3381 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
3382 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
3383 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3384 (plus:SI (match_dup
1) (match_dup
2)))]
3387 {stux|stwux} %
3,%
0,%
2
3388 {stu|stwu} %
3,%
2(%
0)")
3391 [(set (match_operand:HI
3 "gpc_reg_operand" "=r,r")
3392 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3393 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
3394 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3395 (plus:SI (match_dup
1) (match_dup
2)))]
3400 [(set_attr "type" "load")])
3403 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
3405 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3406 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
3407 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3408 (plus:SI (match_dup
1) (match_dup
2)))]
3413 [(set_attr "type" "load")])
3416 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
3418 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3419 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
3420 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3421 (plus:SI (match_dup
1) (match_dup
2)))]
3426 [(set_attr "type" "load")])
3429 [(set (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3430 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
3431 (match_operand:HI
3 "gpc_reg_operand" "r,r"))
3432 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3433 (plus:SI (match_dup
1) (match_dup
2)))]
3440 [(set (match_operand:QI
3 "gpc_reg_operand" "=r,r")
3441 (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3442 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
3443 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3444 (plus:SI (match_dup
1) (match_dup
2)))]
3449 [(set_attr "type" "load")])
3452 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
3454 (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3455 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
3456 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3457 (plus:SI (match_dup
1) (match_dup
2)))]
3462 [(set_attr "type" "load")])
3465 [(set (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3466 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
3467 (match_operand:QI
3 "gpc_reg_operand" "r,r"))
3468 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3469 (plus:SI (match_dup
1) (match_dup
2)))]
3476 [(set (match_operand:SF
3 "gpc_reg_operand" "=f,f")
3477 (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3478 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
3479 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3480 (plus:SI (match_dup
1) (match_dup
2)))]
3485 [(set_attr "type" "fpload")])
3488 [(set (mem:SF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3489 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
3490 (match_operand:SF
3 "gpc_reg_operand" "f,f"))
3491 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3492 (plus:SI (match_dup
1) (match_dup
2)))]
3495 frsp %
3,%
3\;stfsux %
3,%
0,%
2
3496 frsp %
3,%
3\;stfsu %
3,%
2(%
0)")
3499 [(set (match_operand:DF
3 "gpc_reg_operand" "=f,f")
3500 (mem:DF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3501 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
3502 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3503 (plus:SI (match_dup
1) (match_dup
2)))]
3508 [(set_attr "type" "fpload")])
3511 [(set (mem:DF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
3512 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
3513 (match_operand:DF
3 "gpc_reg_operand" "f,f"))
3514 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
3515 (plus:SI (match_dup
1) (match_dup
2)))]
3521 ;; Next come insns related to the calling sequence.
3523 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
3524 ;; We move the back-chain and decrement the stack pointer.
3526 (define_expand "allocate_stack"
3528 (minus:SI (reg:SI
1) (match_operand:SI
0 "reg_or_short_operand" "")))]
3531 { rtx chain = gen_reg_rtx (SImode);
3532 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
3534 emit_move_insn (chain, stack_bot);
3535 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[
0]));
3536 emit_move_insn (stack_bot, chain);
3540 ;; These patterns say how to save and restore the stack pointer. We need not
3541 ;; save the stack pointer at function level since we are careful to
3542 ;; preserve the backchain. At block level, we have to restore the backchain
3543 ;; when we restore the stack pointer.
3545 ;; For nonlocal gotos, we must save both the stack pointer and its
3546 ;; backchain and restore both. Note that in the nonlocal case, the
3547 ;; save area is a memory location.
3549 (define_expand "save_stack_function"
3550 [(use (const_int
0))]
3554 (define_expand "restore_stack_function"
3555 [(use (const_int
0))]
3559 (define_expand "restore_stack_block"
3560 [(set (match_dup
2) (mem:SI (match_operand:SI
0 "register_operand" "")))
3561 (set (match_dup
0) (match_operand:SI
1 "register_operand" ""))
3562 (set (mem:SI (match_dup
0)) (match_dup
2))]
3565 { operands[
2] = gen_reg_rtx (SImode); }")
3567 (define_expand "save_stack_nonlocal"
3568 [(match_operand:DI
0 "memory_operand" "")
3569 (match_operand:SI
1 "register_operand" "")]
3573 rtx temp = gen_reg_rtx (SImode);
3575 /* Copy the backchain to the first word, sp to the second. */
3576 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[
1]));
3577 emit_move_insn (operand_subword (operands[
0],
0,
0, DImode), temp);
3578 emit_move_insn (operand_subword (operands[
0],
1,
0, DImode), operands[
1]);
3582 (define_expand "restore_stack_nonlocal"
3583 [(match_operand:SI
0 "register_operand" "")
3584 (match_operand:DI
1 "memory_operand" "")]
3588 rtx temp = gen_reg_rtx (SImode);
3590 /* Restore the backchain from the first word, sp from the second. */
3591 emit_move_insn (temp, operand_subword (operands[
1],
0,
0, DImode));
3592 emit_move_insn (operands[
0], operand_subword (operands[
1],
1,
0, DImode));
3593 emit_move_insn (gen_rtx (MEM, SImode, operands[
0]), temp);
3597 ;; A function pointer is a pointer to a data area whose first word contains
3598 ;; the actual address of the function, whose second word contains a pointer
3599 ;; to its TOC, and whose third word contains a value to place in the static
3600 ;; chain register (r11). Note that if we load the static chain, our
3601 ;; "trampoline" need not have any executable code.
3603 ;; operands[
0] is an SImode pseudo in which we place the address of the
3605 ;; operands[
1] is the address of data area of the function to call
3607 (define_expand "call_via_ptr"
3608 [(set (match_operand:SI
0 "gpc_reg_operand" "")
3609 (mem:SI (match_operand:SI
1 "gpc_reg_operand" "")))
3610 (set (mem:SI (plus:SI (reg:SI
1) (const_int
20)))
3613 (mem:SI (plus:SI (match_dup
1)
3616 (mem:SI (plus:SI (match_dup
1)
3623 (define_expand "call"
3624 [(parallel [(call (mem:SI (match_operand:SI
0 "address_operand" ""))
3625 (match_operand
1 "" ""))
3626 (clobber (scratch:SI))])]
3630 if (GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != CONST_INT)
3633 operands[
0] = XEXP (operands[
0],
0);
3634 if (GET_CODE (operands[
0]) != SYMBOL_REF)
3636 rtx temp = gen_reg_rtx (SImode);
3638 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[
0])));
3643 (define_expand "call_value"
3644 [(parallel [(set (match_operand
0 "" "")
3645 (call (mem:SI (match_operand:SI
1 "address_operand" ""))
3646 (match_operand
2 "" "")))
3647 (clobber (scratch:SI))])]
3651 if (GET_CODE (operands[
1]) != MEM || GET_CODE (operands[
2]) != CONST_INT)
3654 operands[
1] = XEXP (operands[
1],
0);
3655 if (GET_CODE (operands[
1]) != SYMBOL_REF)
3657 rtx temp = gen_reg_rtx (SImode);
3659 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[
1])));
3664 ;; Call to function in current module. No TOC pointer reload needed.
3667 [(call (mem:SI (match_operand:SI
0 "current_file_function_operand" "s"))
3668 (match_operand
1 "" "g"))
3669 (clobber (match_scratch:SI
2 "=l"))]
3673 ;; Call to function which may be in another module. Restore the TOC
3674 ;; pointer (r2) after the call.
3677 [(call (mem:SI (match_operand:SI
0 "call_operand" "l,s"))
3678 (match_operand
1 "" "fg,fg"))
3679 (clobber (match_scratch:SI
2 "=l,l"))]
3682 {brl|blrl}\;{l|lwz}
2,
20(
1)
3684 [(set_attr "length" "
8")])
3687 [(set (match_operand
0 "" "=fg")
3688 (call (mem:SI (match_operand:SI
1 "current_file_function_operand" "s"))
3689 (match_operand
2 "" "g")))
3690 (clobber (match_scratch:SI
3 "=l"))]
3695 [(set (match_operand
0 "" "=fg,fg")
3696 (call (mem:SI (match_operand:SI
1 "call_operand" "l,s"))
3697 (match_operand
2 "" "fg,fg")))
3698 (clobber (match_scratch:SI
3 "=l,l"))]
3701 {brl|blrl}\;{l|lwz}
2,
20(
1)
3703 [(set_attr "length" "
8")])
3705 ;; Call subroutine returning any type.
3707 (define_expand "untyped_call"
3708 [(parallel [(call (match_operand
0 "" "")
3710 (match_operand
1 "" "")
3711 (match_operand
2 "" "")])]
3717 emit_call_insn (gen_call (operands[
0], const0_rtx, NULL, const0_rtx));
3719 for (i =
0; i < XVECLEN (operands[
2],
0); i++)
3721 rtx set = XVECEXP (operands[
2],
0, i);
3722 emit_move_insn (SET_DEST (set), SET_SRC (set));
3725 /* The optimizer does not know that the call sets the function value
3726 registers we stored in the result block. We avoid problems by
3727 claiming that all hard registers are used and clobbered at this
3729 emit_insn (gen_blockage ());
3734 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
3735 ;; all of memory. This blocks insns from being moved across this point.
3737 (define_insn "blockage"
3738 [(unspec_volatile [(const_int
0)]
0)]
3742 ;; Compare insns are next. Note that the RS/
6000 has two types of compares,
3743 ;; signed & unsigned, and one type of branch.
3745 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
3746 ;; insns, and branches. We store the operands of compares until we see
3748 (define_expand "cmpsi"
3750 (compare (match_operand:SI
0 "gpc_reg_operand" "")
3751 (match_operand:SI
1 "reg_or_short_operand" "")))]
3755 /* Take care of the possibility that operands[
1] might be negative but
3756 this might be a logical operation. That insn doesn't exist. */
3757 if (GET_CODE (operands[
1]) == CONST_INT
3758 && INTVAL (operands[
1]) <
0)
3759 operands[
1] = force_reg (SImode, operands[
1]);
3761 rs6000_compare_op0 = operands[
0];
3762 rs6000_compare_op1 = operands[
1];
3763 rs6000_compare_fp_p =
0;
3767 (define_expand "cmpsf"
3768 [(set (cc0) (compare (match_operand:SF
0 "gpc_reg_operand" "")
3769 (match_operand:SF
1 "gpc_reg_operand" "")))]
3773 rs6000_compare_op0 = operands[
0];
3774 rs6000_compare_op1 = operands[
1];
3775 rs6000_compare_fp_p =
1;
3779 (define_expand "cmpdf"
3780 [(set (cc0) (compare (match_operand:DF
0 "gpc_reg_operand" "")
3781 (match_operand:DF
1 "gpc_reg_operand" "")))]
3785 rs6000_compare_op0 = operands[
0];
3786 rs6000_compare_op1 = operands[
1];
3787 rs6000_compare_fp_p =
1;
3791 (define_expand "beq"
3792 [(set (match_dup
2) (match_dup
1))
3794 (if_then_else (eq (match_dup
2)
3796 (label_ref (match_operand
0 "" ""))
3800 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3801 operands[
1] = gen_rtx (COMPARE, mode,
3802 rs6000_compare_op0, rs6000_compare_op1);
3803 operands[
2] = gen_reg_rtx (mode);
3806 (define_expand "bne"
3807 [(set (match_dup
2) (match_dup
1))
3809 (if_then_else (ne (match_dup
2)
3811 (label_ref (match_operand
0 "" ""))
3815 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3816 operands[
1] = gen_rtx (COMPARE, mode,
3817 rs6000_compare_op0, rs6000_compare_op1);
3818 operands[
2] = gen_reg_rtx (mode);
3821 (define_expand "blt"
3822 [(set (match_dup
2) (match_dup
1))
3824 (if_then_else (lt (match_dup
2)
3826 (label_ref (match_operand
0 "" ""))
3830 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3831 operands[
1] = gen_rtx (COMPARE, mode,
3832 rs6000_compare_op0, rs6000_compare_op1);
3833 operands[
2] = gen_reg_rtx (mode);
3836 (define_expand "bgt"
3837 [(set (match_dup
2) (match_dup
1))
3839 (if_then_else (gt (match_dup
2)
3841 (label_ref (match_operand
0 "" ""))
3845 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3846 operands[
1] = gen_rtx (COMPARE, mode,
3847 rs6000_compare_op0, rs6000_compare_op1);
3848 operands[
2] = gen_reg_rtx (mode);
3851 (define_expand "ble"
3852 [(set (match_dup
2) (match_dup
1))
3854 (if_then_else (le (match_dup
2)
3856 (label_ref (match_operand
0 "" ""))
3860 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3861 operands[
1] = gen_rtx (COMPARE, mode,
3862 rs6000_compare_op0, rs6000_compare_op1);
3863 operands[
2] = gen_reg_rtx (mode);
3866 (define_expand "bge"
3867 [(set (match_dup
2) (match_dup
1))
3869 (if_then_else (ge (match_dup
2)
3871 (label_ref (match_operand
0 "" ""))
3875 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3876 operands[
1] = gen_rtx (COMPARE, mode,
3877 rs6000_compare_op0, rs6000_compare_op1);
3878 operands[
2] = gen_reg_rtx (mode);
3881 (define_expand "bgtu"
3882 [(set (match_dup
2) (match_dup
1))
3884 (if_then_else (gtu (match_dup
2)
3886 (label_ref (match_operand
0 "" ""))
3890 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
3891 rs6000_compare_op0, rs6000_compare_op1);
3892 operands[
2] = gen_reg_rtx (CCUNSmode);
3895 (define_expand "bltu"
3896 [(set (match_dup
2) (match_dup
1))
3898 (if_then_else (ltu (match_dup
2)
3900 (label_ref (match_operand
0 "" ""))
3904 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
3905 rs6000_compare_op0, rs6000_compare_op1);
3906 operands[
2] = gen_reg_rtx (CCUNSmode);
3909 (define_expand "bgeu"
3910 [(set (match_dup
2) (match_dup
1))
3912 (if_then_else (geu (match_dup
2)
3914 (label_ref (match_operand
0 "" ""))
3918 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
3919 rs6000_compare_op0, rs6000_compare_op1);
3920 operands[
2] = gen_reg_rtx (CCUNSmode);
3923 (define_expand "bleu"
3924 [(set (match_dup
2) (match_dup
1))
3926 (if_then_else (leu (match_dup
2)
3928 (label_ref (match_operand
0 "" ""))
3932 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
3933 rs6000_compare_op0, rs6000_compare_op1);
3934 operands[
2] = gen_reg_rtx (CCUNSmode);
3937 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
3938 ;; For SEQ, likewise, except that comparisons with zero should be done
3939 ;; with an scc insns. However, due to the order that combine see the
3940 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
3941 ;; the cases we don't want to handle.
3942 (define_expand "seq"
3943 [(set (match_dup
2) (match_dup
1))
3944 (set (match_operand:SI
0 "gpc_reg_operand" "")
3945 (eq:SI (match_dup
2) (const_int
0)))]
3948 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3949 operands[
1] = gen_rtx (COMPARE, mode,
3950 rs6000_compare_op0, rs6000_compare_op1);
3951 operands[
2] = gen_reg_rtx (mode);
3954 (define_expand "sne"
3955 [(set (match_dup
2) (match_dup
1))
3956 (set (match_operand:SI
0 "gpc_reg_operand" "")
3957 (ne:SI (match_dup
2) (const_int
0)))]
3960 { if (! rs6000_compare_fp_p)
3963 operands[
1] = gen_rtx (COMPARE, CCFPmode,
3964 rs6000_compare_op0, rs6000_compare_op1);
3965 operands[
2] = gen_reg_rtx (CCFPmode);
3968 ;; A >
0 is best done using the portable sequence, so fail in that case.
3969 (define_expand "sgt"
3970 [(set (match_dup
2) (match_dup
1))
3971 (set (match_operand:SI
0 "gpc_reg_operand" "")
3972 (gt:SI (match_dup
2) (const_int
0)))]
3975 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3977 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3980 operands[
1] = gen_rtx (COMPARE, mode,
3981 rs6000_compare_op0, rs6000_compare_op1);
3982 operands[
2] = gen_reg_rtx (mode);
3985 ;; A <
0 is best done in the portable way for A an integer.
3986 (define_expand "slt"
3987 [(set (match_dup
2) (match_dup
1))
3988 (set (match_operand:SI
0 "gpc_reg_operand" "")
3989 (lt:SI (match_dup
2) (const_int
0)))]
3992 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3994 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3997 operands[
1] = gen_rtx (COMPARE, mode,
3998 rs6000_compare_op0, rs6000_compare_op1);
3999 operands[
2] = gen_reg_rtx (mode);
4002 (define_expand "sge"
4003 [(set (match_dup
2) (match_dup
1))
4004 (set (match_operand:SI
0 "gpc_reg_operand" "")
4005 (ge:SI (match_dup
2) (const_int
0)))]
4008 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4009 operands[
1] = gen_rtx (COMPARE, mode,
4010 rs6000_compare_op0, rs6000_compare_op1);
4011 operands[
2] = gen_reg_rtx (mode);
4014 ;; A <=
0 is best done the portable way for A an integer.
4015 (define_expand "sle"
4016 [(set (match_dup
2) (match_dup
1))
4017 (set (match_operand:SI
0 "gpc_reg_operand" "")
4018 (le:SI (match_dup
2) (const_int
0)))]
4021 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
4023 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
4026 operands[
1] = gen_rtx (COMPARE, mode,
4027 rs6000_compare_op0, rs6000_compare_op1);
4028 operands[
2] = gen_reg_rtx (mode);
4031 (define_expand "sgtu"
4032 [(set (match_dup
2) (match_dup
1))
4033 (set (match_operand:SI
0 "gpc_reg_operand" "")
4034 (gtu:SI (match_dup
2) (const_int
0)))]
4037 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
4038 rs6000_compare_op0, rs6000_compare_op1);
4039 operands[
2] = gen_reg_rtx (CCUNSmode);
4042 (define_expand "sltu"
4043 [(set (match_dup
2) (match_dup
1))
4044 (set (match_operand:SI
0 "gpc_reg_operand" "")
4045 (ltu:SI (match_dup
2) (const_int
0)))]
4048 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
4049 rs6000_compare_op0, rs6000_compare_op1);
4050 operands[
2] = gen_reg_rtx (CCUNSmode);
4053 (define_expand "sgeu"
4054 [(set (match_dup
2) (match_dup
1))
4055 (set (match_operand:SI
0 "gpc_reg_operand" "")
4056 (geu:SI (match_dup
2) (const_int
0)))]
4059 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
4060 rs6000_compare_op0, rs6000_compare_op1);
4061 operands[
2] = gen_reg_rtx (CCUNSmode);
4064 (define_expand "sleu"
4065 [(set (match_dup
2) (match_dup
1))
4066 (set (match_operand:SI
0 "gpc_reg_operand" "")
4067 (leu:SI (match_dup
2) (const_int
0)))]
4070 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
4071 rs6000_compare_op0, rs6000_compare_op1);
4072 operands[
2] = gen_reg_rtx (CCUNSmode);
4075 ;; Here are the actual compare insns.
4077 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
4078 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
4079 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
4082 [(set_attr "type" "compare")])
4084 ;; If we are comparing a register for equality with a large constant,
4085 ;; we can do this with an XOR followed by a compare. But we need a scratch
4086 ;; register for the result of the XOR.
4089 [(set (match_operand:CC
0 "cc_reg_operand" "")
4090 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "")
4091 (match_operand:SI
2 "non_short_cint_operand" "")))
4092 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
4093 "find_single_use (operands[
0], insn,
0)
4094 && (GET_CODE (*find_single_use (operands[
0], insn,
0)) == EQ
4095 || GET_CODE (*find_single_use (operands[
0], insn,
0)) == NE)"
4096 [(set (match_dup
3) (xor:SI (match_dup
1) (match_dup
4)))
4097 (set (match_dup
0) (compare:CC (match_dup
3) (match_dup
5)))]
4100 /* Get the constant we are comparing against, C, and see what it looks like
4101 sign-extended to
16 bits. Then see what constant could be XOR'ed
4102 with C to get the sign-extended value. */
4104 int c = INTVAL (operands[
2]);
4105 int sextc = (c <<
16) >>
16;
4106 int xorv = c ^ sextc;
4108 operands[
4] = gen_rtx (CONST_INT, VOIDmode, xorv);
4109 operands[
5] = gen_rtx (CONST_INT, VOIDmode, sextc);
4113 [(set (match_operand:CCUNS
0 "cc_reg_operand" "=y")
4114 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "r")
4115 (match_operand:SI
2 "reg_or_u_short_operand" "rI")))]
4118 [(set_attr "type" "compare")])
4120 ;; The following two insns don't exist as single insns, but if we provide
4121 ;; them, we can swap an add and compare, which will enable us to overlap more
4122 ;; of the required delay between a compare and branch. We generate code for
4123 ;; them by splitting.
4126 [(set (match_operand:CC
3 "cc_reg_operand" "=y")
4127 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
4128 (match_operand:SI
2 "short_cint_operand" "i")))
4129 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4130 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "i")))]
4135 [(set (match_operand:CCUNS
3 "cc_reg_operand" "=y")
4136 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "r")
4137 (match_operand:SI
2 "u_short_cint_operand" "i")))
4138 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4139 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "i")))]
4144 [(set (match_operand:CC
3 "cc_reg_operand" "")
4145 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "")
4146 (match_operand:SI
2 "short_cint_operand" "")))
4147 (set (match_operand:SI
0 "gpc_reg_operand" "")
4148 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "")))]
4150 [(set (match_dup
3) (compare:CC (match_dup
1) (match_dup
2)))
4151 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
4)))])
4154 [(set (match_operand:CCUNS
3 "cc_reg_operand" "")
4155 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "")
4156 (match_operand:SI
2 "u_short_cint_operand" "")))
4157 (set (match_operand:SI
0 "gpc_reg_operand" "")
4158 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "")))]
4160 [(set (match_dup
3) (compare:CCUNS (match_dup
1) (match_dup
2)))
4161 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
4)))])
4164 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
4165 (compare:CCFP (match_operand:SF
1 "gpc_reg_operand" "f")
4166 (match_operand:SF
2 "gpc_reg_operand" "f")))]
4169 [(set_attr "type" "fpcompare")])
4172 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
4173 (compare:CCFP (match_operand:DF
1 "gpc_reg_operand" "f")
4174 (match_operand:DF
2 "gpc_reg_operand" "f")))]
4177 [(set_attr "type" "fpcompare")])
4179 ;; Now we have the scc insns. We can do some combinations because of the
4180 ;; way the machine works.
4182 ;; Note that this is probably faster if we can put an insn between the
4183 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
4184 ;; cases the insns below which don't use an intermediate CR field will
4187 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4188 (match_operator:SI
1 "scc_comparison_operator"
4189 [(match_operand
2 "cc_reg_operand" "y")
4192 "%D1mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%J1,
1"
4193 [(set_attr "length" "
12")])
4196 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4197 (compare:CC (match_operator:SI
1 "scc_comparison_operator"
4198 [(match_operand
2 "cc_reg_operand" "y")
4201 (set (match_operand:SI
3 "gpc_reg_operand" "=r")
4202 (match_op_dup
1 [(match_dup
2) (const_int
0)]))]
4204 "%D1mfcr %
3\;{rlinm.|rlwinm.} %
3,%
3,%J1,
1"
4205 [(set_attr "type" "delayed_compare")
4206 (set_attr "length" "
12")])
4209 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4210 (ashift:SI (match_operator:SI
1 "scc_comparison_operator"
4211 [(match_operand
2 "cc_reg_operand" "y")
4213 (match_operand:SI
3 "const_int_operand" "n")))]
4217 int is_bit = ccr_bit (operands[
1],
1);
4218 int put_bit =
31 - (INTVAL (operands[
3]) &
31);
4221 if (is_bit >= put_bit)
4222 count = is_bit - put_bit;
4224 count =
32 - (put_bit - is_bit);
4226 operands[
4] = gen_rtx (CONST_INT, VOIDmode, count);
4227 operands[
5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
4229 return
\"%D1mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%
4,%
5,%
5\";
4231 [(set_attr "length" "
12")])
4234 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4236 (ashift:SI (match_operator:SI
1 "scc_comparison_operator"
4237 [(match_operand
2 "cc_reg_operand" "y")
4239 (match_operand:SI
3 "const_int_operand" "n"))
4241 (set (match_operand:SI
4 "gpc_reg_operand" "=r")
4242 (ashift:SI (match_op_dup
1 [(match_dup
2) (const_int
0)])
4247 int is_bit = ccr_bit (operands[
1],
1);
4248 int put_bit =
31 - (INTVAL (operands[
3]) &
31);
4251 if (is_bit >= put_bit)
4252 count = is_bit - put_bit;
4254 count =
32 - (put_bit - is_bit);
4256 operands[
5] = gen_rtx (CONST_INT, VOIDmode, count);
4257 operands[
6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
4259 return
\"%D1mfcr %
4\;{rlinm.|rlwinm.} %
4,%
4,%
5,%
6,%
6\";
4261 [(set_attr "type" "delayed_compare")
4262 (set_attr "length" "
12")])
4264 ;; If we are comparing the result of two comparisons, this can be done
4265 ;; using creqv or crxor.
4268 [(set (match_operand:CCEQ
0 "cc_reg_operand" "=y")
4269 (compare:CCEQ (match_operator
1 "scc_comparison_operator"
4270 [(match_operand
2 "cc_reg_operand" "y")
4272 (match_operator
3 "scc_comparison_operator"
4273 [(match_operand
4 "cc_reg_operand" "y")
4275 "REGNO (operands[
2]) != REGNO (operands[
4])"
4278 enum rtx_code code1, code2;
4280 code1 = GET_CODE (operands[
1]);
4281 code2 = GET_CODE (operands[
3]);
4283 if ((code1 == EQ || code1 == LT || code1 == GT
4284 || code1 == LTU || code1 == GTU
4285 || (code1 != NE && GET_MODE (operands[
2]) == CCFPmode))
4287 (code2 == EQ || code2 == LT || code2 == GT
4288 || code2 == LTU || code2 == GTU
4289 || (code2 != NE && GET_MODE (operands[
4]) == CCFPmode)))
4290 return
\"%C1%C3crxor %E0,%j1,%j3
\";
4292 return
\"%C1%C3creqv %E0,%j1,%j3
\";
4294 [(set_attr "length" "
12")])
4296 ;; There is a
3 cycle delay between consecutive mfcr instructions
4297 ;; so it is useful to combine
2 scc instructions to use only one mfcr.
4300 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4301 (match_operator:SI
1 "scc_comparison_operator"
4302 [(match_operand
2 "cc_reg_operand" "y")
4304 (set (match_operand:SI
3 "gpc_reg_operand" "=r")
4305 (match_operator:SI
4 "scc_comparison_operator"
4306 [(match_operand
5 "cc_reg_operand" "y")
4308 "REGNO (operands[
2]) != REGNO (operands[
5])"
4309 "%D1%D4mfcr %
3\;{rlinm|rlwinm} %
0,%
3,%J1,
1\;{rlinm|rlwinm} %
3,%
3,%J4,
1"
4310 [(set_attr "length" "
20")])
4312 ;; There are some scc insns that can be done directly, without a compare.
4313 ;; These are faster because they don't involve the communications between
4314 ;; the FXU and branch units. In fact, we will be replacing all of the
4315 ;; integer scc insns here or in the portable methods in emit_store_flag.
4317 ;; Also support (neg (scc ..)) since that construct is used to replace
4318 ;; branches, (plus (scc ..) ..) since that construct is common and
4319 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
4320 ;; cases where it is no more expensive than (neg (scc ..)).
4322 ;; Have reload force a constant into a register for the simple insns that
4323 ;; otherwise won't accept constants. We do this because it is faster than
4324 ;; the cmp/mfcr sequence we would otherwise generate.
4327 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
4328 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
4329 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I")))
4330 (clobber (match_scratch:SI
3 "=r,&r,r,r,r"))]
4333 xor %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
4334 {sfi|subfic} %
3,%
1,
0\;{ae|adde} %
0,%
3,%
1
4335 {xoril|xori} %
0,%
1,%b2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
4336 {xoriu|xoris} %
0,%
1,%u2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
4337 {sfi|subfic} %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0"
4338 [(set_attr "length" "
12,
8,
12,
12,
12")])
4341 [(set (match_operand:CC
4 "cc_reg_operand" "=x,x,x,x,x")
4343 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
4344 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
4346 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
4347 (eq:SI (match_dup
1) (match_dup
2)))
4348 (clobber (match_scratch:SI
3 "=r,&r,r,r,r"))]
4351 xor %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
4352 {sfi|subfic} %
3,%
1,
0\;{ae.|adde.} %
0,%
3,%
1
4353 {xoril|xori} %
0,%
1,%b2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
4354 {xoriu|xoris} %
0,%
1,%u2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
4355 {sfi|subfic} %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0"
4356 [(set_attr "type" "compare")
4357 (set_attr "length" "
12,
8,
12,
12,
12")])
4359 ;; We have insns of the form shown by the first define_insn below. If
4360 ;; there is something inside the comparison operation, we must split it.
4362 [(set (match_operand:SI
0 "gpc_reg_operand" "")
4363 (plus:SI (match_operator
1 "comparison_operator"
4364 [(match_operand:SI
2 "" "")
4366 "reg_or_cint_operand" "")])
4367 (match_operand:SI
4 "gpc_reg_operand" "")))
4368 (clobber (match_operand:SI
5 "register_operand" ""))]
4369 "! gpc_reg_operand (operands[
2], SImode)"
4370 [(set (match_dup
5) (match_dup
2))
4371 (set (match_dup
2) (plus:SI (match_op_dup
1 [(match_dup
2) (match_dup
3)])
4375 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
4376 (plus:SI (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
4377 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
4378 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r")))
4379 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
4382 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
4383 {sfi|subfic} %
4,%
1,
0\;{aze|addze} %
0,%
3
4384 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
4385 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
4386 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|adddze} %
0,%
3"
4387 [(set_attr "length" "
12,
8,
12,
12,
12")])
4390 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x,x,x")
4393 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
4394 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
4395 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r"))
4397 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
4400 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
4401 {sfi|subfic} %
4,%
1,
0\;{aze.|addze.} %
0,%
3
4402 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
4403 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
4404 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3"
4405 [(set_attr "type" "compare")
4406 (set_attr "length" "
12,
8,
12,
12,
12")])
4409 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x,x,x,x")
4412 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
4413 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
4414 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r"))
4416 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
4417 (plus:SI (eq:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
4418 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
4421 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
4422 {sfi|subfic} %
4,%
1,
0\;{aze.|addze.} %
4,%
3
4423 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
4424 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
4425 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3"
4426 [(set_attr "type" "compare")
4427 (set_attr "length" "
12,
8,
12,
12,
12")])
4430 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
4431 (neg:SI (eq:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r,r,r")
4432 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))))]
4435 xor %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
4436 {ai|addic} %
0,%
1,-
1\;{sfe|subfe} %
0,%
0,%
0
4437 {xoril|xori} %
0,%
1,%b2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
4438 {xoriu|xoris} %
0,%
1,%u2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
4439 {sfi|subfic} %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0"
4440 [(set_attr "length" "
12,
8,
12,
12,
12")])
4442 ;; This is what (plus (ne X (const_int
0)) Y) looks like.
4444 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4445 (plus:SI (lshiftrt:SI
4446 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
4448 (match_operand:SI
2 "gpc_reg_operand" "r")))
4449 (clobber (match_scratch:SI
3 "=&r"))]
4451 "{ai|addic} %
3,%
1,-
1\;{aze|addze} %
0,%
2"
4452 [(set_attr "length" "
8")])
4455 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4457 (plus:SI (lshiftrt:SI
4458 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
4460 (match_operand:SI
2 "gpc_reg_operand" "r"))
4462 (clobber (match_scratch:SI
3 "=&r"))]
4464 "{ai|addic} %
3,%
1,-
1\;{aze.|addze.} %
3,%
2"
4465 [(set_attr "type" "compare")
4466 (set_attr "length" "
8")])
4469 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
4471 (plus:SI (lshiftrt:SI
4472 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
4474 (match_operand:SI
2 "gpc_reg_operand" "r"))
4476 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4477 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup
1))) (const_int
31))
4479 (clobber (match_scratch:SI
3 "=&r"))]
4481 "{ai|addic} %
3,%
1,-
1\;{aze.|addze.} %
0,%
2"
4482 [(set_attr "type" "compare")
4483 (set_attr "length" "
8")])
4486 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4487 (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4488 (match_operand:SI
2 "reg_or_short_operand" "r,O")))
4489 (clobber (match_scratch:SI
3 "=r,X"))]
4492 doz %
3,%
2,%
1\;{sfi|subfic} %
0,%
3,
0\;{ae|adde} %
0,%
0,%
3
4493 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;sri %
0,%
0,
31"
4494 [(set_attr "length" "
12")])
4497 [(set (match_operand:CC
4 "cc_reg_operand" "=x,x")
4499 (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4500 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
4502 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4503 (le:SI (match_dup
1) (match_dup
2)))
4504 (clobber (match_scratch:SI
3 "=r,X"))]
4507 doz %
3,%
2,%
1\;{sfi|subfic} %
0,%
3,
0\;{ae.|adde.} %
0,%
0,%
3
4508 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;sri. %
0,%
0,
31"
4509 [(set_attr "type" "delayed_compare,compare")
4510 (set_attr "length" "
12")])
4513 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4514 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4515 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
4516 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
4517 (clobber (match_scratch:SI
4 "=&r,&r"))]
4520 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
4521 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze|addze} %
0,%
3"
4522 [(set_attr "length" "
12")])
4525 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
4527 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4528 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
4529 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
4531 (clobber (match_scratch:SI
4 "=&r,&r"))]
4534 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
4535 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze.|addze.} %
4,%
3"
4536 [(set_attr "type" "compare")
4537 (set_attr "length" "
12")])
4540 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
4542 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4543 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
4544 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
4546 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4547 (plus:SI (le:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
4548 (clobber (match_scratch:SI
4 "=&r,&r"))]
4551 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
4552 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze.|addze.} %
0,%
3"
4553 [(set_attr "type" "compare")
4554 (set_attr "length" "
12")])
4557 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4558 (neg:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4559 (match_operand:SI
2 "reg_or_short_operand" "r,O"))))]
4562 doz %
0,%
2,%
1\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
4563 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{srai|srawi} %
0,%
0,
31"
4564 [(set_attr "length" "
12")])
4567 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4568 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4569 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
4571 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0"
4572 [(set_attr "length" "
12")])
4575 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4577 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4578 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4580 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4581 (leu:SI (match_dup
1) (match_dup
2)))]
4583 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0"
4584 [(set_attr "type" "compare")
4585 (set_attr "length" "
12")])
4588 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4589 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4590 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4591 (match_operand:SI
3 "gpc_reg_operand" "r")))
4592 (clobber (match_scratch:SI
4 "=&r"))]
4594 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze|addze} %
0,%
3"
4595 [(set_attr "length" "
8")])
4598 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4600 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4601 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4602 (match_operand:SI
3 "gpc_reg_operand" "r"))
4604 (clobber (match_scratch:SI
4 "=&r"))]
4606 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze.|addze.} %
4,%
3"
4607 [(set_attr "type" "compare")
4608 (set_attr "length" "
8")])
4611 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
4613 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4614 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4615 (match_operand:SI
3 "gpc_reg_operand" "r"))
4617 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4618 (plus:SI (leu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
4619 (clobber (match_scratch:SI
4 "=&r"))]
4621 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze.|addze.} %
0,%
3"
4622 [(set_attr "type" "compare")
4623 (set_attr "length" "
8")])
4626 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4627 (neg:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4628 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
4630 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;nand %
0,%
0,%
0"
4631 [(set_attr "length" "
12")])
4634 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4636 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4637 (match_operand:SI
2 "reg_or_short_operand" "rI")))
4638 (match_operand:SI
3 "gpc_reg_operand" "r")))
4639 (clobber (match_scratch:SI
4 "=&r"))]
4641 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4"
4642 [(set_attr "length" "
12")])
4645 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4648 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4649 (match_operand:SI
2 "reg_or_short_operand" "rI")))
4650 (match_operand:SI
3 "gpc_reg_operand" "r"))
4652 (clobber (match_scratch:SI
4 "=&r"))]
4654 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4"
4655 [(set_attr "type" "compare")
4656 (set_attr "length" "
12")])
4659 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
4662 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4663 (match_operand:SI
2 "reg_or_short_operand" "rI")))
4664 (match_operand:SI
3 "gpc_reg_operand" "r"))
4666 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4667 (and:SI (neg:SI (leu:SI (match_dup
1) (match_dup
2))) (match_dup
3)))
4668 (clobber (match_scratch:SI
4 "=&r"))]
4670 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4"
4671 [(set_attr "type" "compare")
4672 (set_attr "length" "
12")])
4675 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4676 (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4677 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
4679 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;sri %
0,%
0,
31"
4680 [(set_attr "length" "
12")])
4683 [(set (match_operand:SI
3 "cc_reg_operand" "=x")
4685 (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4686 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4688 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4689 (lt:SI (match_dup
1) (match_dup
2)))]
4691 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;sri. %
0,%
0,
31"
4692 [(set_attr "type" "delayed_compare")
4693 (set_attr "length" "
12")])
4696 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4697 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4698 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4699 (match_operand:SI
3 "gpc_reg_operand" "r")))
4700 (clobber (match_scratch:SI
4 "=&r"))]
4702 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze|addze} %
0,%
3"
4703 [(set_attr "length" "
12")])
4706 [(set (match_operand:SI
0 "cc_reg_operand" "=x")
4708 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4709 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4710 (match_operand:SI
3 "gpc_reg_operand" "r"))
4712 (clobber (match_scratch:SI
4 "=&r"))]
4714 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
4,%
3"
4715 [(set_attr "type" "compare")
4716 (set_attr "length" "
12")])
4719 [(set (match_operand:SI
5 "cc_reg_operand" "=x")
4721 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4722 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4723 (match_operand:SI
3 "gpc_reg_operand" "r"))
4725 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4726 (plus:SI (lt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
4727 (clobber (match_scratch:SI
4 "=&r"))]
4729 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
0,%
3"
4730 [(set_attr "type" "compare")
4731 (set_attr "length" "
12")])
4734 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4735 (neg:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4736 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
4738 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{srai|srawi} %
0,%
0,
31"
4739 [(set_attr "length" "
12")])
4742 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4743 (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4744 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))]
4747 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0
4748 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0"
4749 [(set_attr "length" "
12")])
4752 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
4754 (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4755 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
4757 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4758 (ltu:SI (match_dup
1) (match_dup
2)))]
4761 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0
4762 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0"
4763 [(set_attr "type" "compare")
4764 (set_attr "length" "
12")])
4767 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
4768 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r,r")
4769 (match_operand:SI
2 "reg_or_neg_short_operand" "r,r,P,P"))
4770 (match_operand:SI
3 "reg_or_short_operand" "r,I,r,I")))
4771 (clobber (match_scratch:SI
4 "=&r,r,&r,r"))]
4774 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
4775 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
4776 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
4777 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3"
4778 [(set_attr "length" "
12")])
4781 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
4783 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4784 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
4785 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
4787 (clobber (match_scratch:SI
4 "=&r,&r"))]
4790 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
4,%
4,%
3
4791 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
4,%
4,%
3"
4792 [(set_attr "type" "compare")
4793 (set_attr "length" "
12")])
4796 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
4798 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4799 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
4800 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
4802 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4803 (plus:SI (ltu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
4804 (clobber (match_scratch:SI
4 "=&r,&r"))]
4807 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3
4808 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
4809 [(set_attr "type" "compare")
4810 (set_attr "length" "
12")])
4813 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4814 (neg:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4815 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))))]
4818 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0
4819 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0"
4820 [(set_attr "length" "
8")])
4823 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4824 (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4825 (match_operand:SI
2 "reg_or_short_operand" "rI")))
4826 (clobber (match_scratch:SI
3 "=r"))]
4828 "doz%I2 %
3,%
1,%
2\;{sfi|subfic} %
0,%
3,
0\;{ae|adde} %
0,%
0,%
3"
4829 [(set_attr "length" "
12")])
4832 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
4834 (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4835 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4837 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4838 (ge:SI (match_dup
1) (match_dup
2)))
4839 (clobber (match_scratch:SI
3 "=r"))]
4841 "doz%I2 %
3,%
1,%
2\;{sfi|subfic} %
0,%
3,
0\;{ae.|adde.} %
0,%
0,%
3"
4842 [(set_attr "type" "compare")
4843 (set_attr "length" "
12")])
4846 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4847 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4848 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4849 (match_operand:SI
3 "gpc_reg_operand" "r")))
4850 (clobber (match_scratch:SI
4 "=&r"))]
4852 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3"
4853 [(set_attr "length" "
12")])
4856 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4858 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4859 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4860 (match_operand:SI
3 "gpc_reg_operand" "r"))
4862 (clobber (match_scratch:SI
4 "=&r"))]
4864 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3"
4865 [(set_attr "type" "compare")
4866 (set_attr "length" "
12")])
4869 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
4871 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4872 (match_operand:SI
2 "reg_or_short_operand" "rI"))
4873 (match_operand:SI
3 "gpc_reg_operand" "r"))
4875 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4876 (plus:SI (ge:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
4877 (clobber (match_scratch:SI
4 "=&r"))]
4879 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3"
4880 [(set_attr "type" "compare")
4881 (set_attr "length" "
12")])
4884 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4885 (neg:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
4886 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
4888 "doz%I2 %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0"
4889 [(set_attr "length" "
12")])
4891 ;; This is (and (neg (ge X (const_int
0))) Y).
4893 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
4896 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
4898 (match_operand:SI
2 "gpc_reg_operand" "r")))
4899 (clobber (match_scratch:SI
3 "=&r"))]
4901 "{srai|srawi} %
3,%
1,
31\;andc %
0,%
2,%
3"
4902 [(set_attr "length" "
8")])
4905 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4909 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
4911 (match_operand:SI
2 "gpc_reg_operand" "r"))
4913 (clobber (match_scratch:SI
3 "=&r"))]
4915 "{srai|srawi} %
3,%
1,
31\;andc. %
3,%
2,%
3"
4916 [(set_attr "type" "compare")
4917 (set_attr "length" "
8")])
4920 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
4924 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
4926 (match_operand:SI
2 "gpc_reg_operand" "r"))
4928 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
4929 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup
1))
4932 (clobber (match_scratch:SI
3 "=&r"))]
4934 "{srai|srawi} %
3,%
1,
31\;andc. %
0,%
2,%
3"
4935 [(set_attr "type" "compare")
4936 (set_attr "length" "
8")])
4939 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4940 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4941 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))]
4944 {sf|subfc} %
0,%
2,%
1\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0
4945 {ai|addic} %
0,%
1,%n2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0"
4946 [(set_attr "length" "
12")])
4949 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
4951 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4952 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
4954 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4955 (geu:SI (match_dup
1) (match_dup
2)))]
4958 {sf|subfc} %
0,%
2,%
1\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0
4959 {ai|addic} %
0,%
1,%n2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0"
4960 [(set_attr "type" "compare")
4961 (set_attr "length" "
12")])
4964 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4965 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4966 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
4967 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
4968 (clobber (match_scratch:SI
4 "=&r,&r"))]
4971 {sf|subfc} %
4,%
2,%
1\;{aze|addze} %
0,%
3
4972 {ai|addic} %
4,%
1,%n2\;{aze|addze} %
0,%
3"
4973 [(set_attr "length" "
8")])
4976 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
4978 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4979 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
4980 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
4982 (clobber (match_scratch:SI
4 "=&r,&r"))]
4985 {sf|subfc} %
4,%
2,%
1\;{aze.|addze.} %
4,%
3
4986 {ai|addic} %
4,%
1,%n2\;{aze.|addze.} %
4,%
3"
4987 [(set_attr "type" "compare")
4988 (set_attr "length" "
8")])
4991 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
4993 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
4994 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
4995 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
4997 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
4998 (plus:SI (geu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
4999 (clobber (match_scratch:SI
4 "=&r,&r"))]
5002 {sf|subfc} %
4,%
2,%
1\;{aze.|addze.} %
0,%
3
5003 {ai|addic} %
4,%
1,%n2\;{aze.|addze.} %
4,%
3"
5004 [(set_attr "type" "compare")
5005 (set_attr "length" "
8")])
5008 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
5009 (neg:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
5010 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))]
5013 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;nand %
0,%
0,%
0
5014 {sfi|subfic} %
0,%
1,-
1\;a%I2 %
0,%
0,%
2\;{sfe|subfe} %
0,%
0,%
0"
5015 [(set_attr "length" "
12")])
5018 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
5020 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
5021 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
5022 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
5023 (clobber (match_scratch:SI
4 "=&r,&r"))]
5026 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4
5027 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4"
5028 [(set_attr "length" "
12")])
5031 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
5034 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
5035 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
5036 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
5038 (clobber (match_scratch:SI
4 "=&r,&r"))]
5041 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4
5042 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4"
5043 [(set_attr "type" "compare")
5044 (set_attr "length" "
12")])
5047 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
5050 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
5051 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
5052 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
5054 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
5055 (and:SI (neg:SI (geu:SI (match_dup
1) (match_dup
2))) (match_dup
3)))
5056 (clobber (match_scratch:SI
4 "=&r,&r"))]
5059 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4
5060 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4"
5061 [(set_attr "type" "compare")
5062 (set_attr "length" "
12")])
5065 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
5066 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5069 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{sri|srwi} %
0,%
0,
31"
5070 [(set_attr "length" "
12")])
5073 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
5075 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5078 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
5079 (gt:SI (match_dup
1) (const_int
0)))]
5081 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
5082 [(set_attr "type" "delayed_compare")
5083 (set_attr "length" "
12")])
5086 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
5087 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5088 (match_operand:SI
2 "reg_or_short_operand" "r")))]
5090 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{sri|srwi} %
0,%
0,
31"
5091 [(set_attr "length" "
12")])
5094 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
5096 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5097 (match_operand:SI
2 "reg_or_short_operand" "r"))
5099 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
5100 (gt:SI (match_dup
1) (match_dup
2)))]
5102 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
5103 [(set_attr "type" "delayed_compare")
5104 (set_attr "length" "
12")])
5107 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
5108 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5110 (match_operand:SI
2 "gpc_reg_operand" "r")))
5111 (clobber (match_scratch:SI
3 "=&r"))]
5113 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze|addze} %
0,%
2"
5114 [(set_attr "length" "
12")])
5117 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
5119 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5121 (match_operand:SI
2 "gpc_reg_operand" "r"))
5123 (clobber (match_scratch:SI
3 "=&r"))]
5125 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze.|addze.} %
0,%
2"
5126 [(set_attr "type" "compare")
5127 (set_attr "length" "
12")])
5130 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
5132 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5134 (match_operand:SI
2 "gpc_reg_operand" "r"))
5136 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
5137 (plus:SI (gt:SI (match_dup
1) (const_int
0)) (match_dup
2)))
5138 (clobber (match_scratch:SI
3 "=&r"))]
5140 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze.|addze.} %
3,%
2"
5141 [(set_attr "type" "compare")
5142 (set_attr "length" "
12")])
5145 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
5146 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5147 (match_operand:SI
2 "reg_or_short_operand" "r"))
5148 (match_operand:SI
3 "gpc_reg_operand" "r")))
5149 (clobber (match_scratch:SI
4 "=&r"))]
5151 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze|addze} %
0,%
3"
5152 [(set_attr "length" "
12")])
5155 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
5157 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5158 (match_operand:SI
2 "reg_or_short_operand" "r"))
5159 (match_operand:SI
3 "gpc_reg_operand" "r"))
5161 (clobber (match_scratch:SI
4 "=&r"))]
5163 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
4,%
3"
5164 [(set_attr "type" "compare")
5165 (set_attr "length" "
12")])
5168 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
5170 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5171 (match_operand:SI
2 "reg_or_short_operand" "r"))
5172 (match_operand:SI
3 "gpc_reg_operand" "r"))
5174 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
5175 (plus:SI (gt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
5176 (clobber (match_scratch:SI
4 "=&r"))]
5178 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
0,%
3"
5179 [(set_attr "type" "compare")
5180 (set_attr "length" "
12")])
5183 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
5184 (neg:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5187 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{srai|srawi} %
0,%
0,
31"
5188 [(set_attr "length" "
12")])
5191 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
5192 (neg:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5193 (match_operand:SI
2 "reg_or_short_operand" "r"))))]
5195 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{srai|srawi} %
0,%
0,
31"
5196 [(set_attr "length" "
12")])
5199 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
5200 (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5201 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
5203 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0"
5204 [(set_attr "length" "
12")])
5207 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
5209 (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5210 (match_operand:SI
2 "reg_or_short_operand" "rI"))
5212 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
5213 (gtu:SI (match_dup
1) (match_dup
2)))]
5215 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0"
5216 [(set_attr "type" "compare")
5217 (set_attr "length" "
12")])
5220 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
5221 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
5222 (match_operand:SI
2 "reg_or_short_operand" "I,r,rI"))
5223 (match_operand:SI
3 "reg_or_short_operand" "r,r,I")))
5224 (clobber (match_scratch:SI
4 "=&r,&r,&r"))]
5227 {ai|addic} %
4,%
1,%k2\;{aze|addze} %
0,%
3
5228 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
5229 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3"
5230 [(set_attr "length" "
8,
12,
12")])
5233 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
5235 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
5236 (match_operand:SI
2 "reg_or_short_operand" "I,r"))
5237 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
5239 (clobber (match_scratch:SI
4 "=&r,&r"))]
5242 {ai|addic} %
4,%
1,%k2\;{aze.|addze.} %
0,%
3
5243 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
5244 [(set_attr "type" "compare")
5245 (set_attr "length" "
8,
12")])
5248 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
5250 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
5251 (match_operand:SI
2 "reg_or_short_operand" "I,r"))
5252 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
5254 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
5255 (plus:SI (gtu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
5256 (clobber (match_scratch:SI
4 "=&r,&r"))]
5259 {ai|addic} %
4,%
1,%k2\;{aze.|addze.} %
0,%
3
5260 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
5261 [(set_attr "type" "compare")
5262 (set_attr "length" "
8,
12")])
5265 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
5266 (neg:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
5267 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
5269 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0"
5270 [(set_attr "length" "
8")])
5272 ;; Define both directions of branch and return. If we need a reload
5273 ;; register, we'd rather use CR0 since it is much easier to copy a
5274 ;; register CC value to there.
5278 (if_then_else (match_operator
1 "branch_comparison_operator"
5280 "cc_reg_operand" "x,?y")
5282 (label_ref (match_operand
0 "" ""))
5287 if (get_attr_length (insn) ==
8)
5288 return
\"%C1bc %t1,%j1,%l0
\";
5290 return
\"%C1bc %T1,%j1,$+
8\;b %l0
\";
5292 [(set_attr "type" "branch")])
5297 (if_then_else (match_operator
0 "branch_comparison_operator"
5299 "cc_reg_operand" "x,?y")
5304 "{%C0bcr|%C0bclr} %t0,%j0"
5305 [(set_attr "length" "
8")])
5309 (if_then_else (match_operator
1 "branch_comparison_operator"
5311 "cc_reg_operand" "x,?y")
5314 (label_ref (match_operand
0 "" ""))))]
5318 if (get_attr_length (insn) ==
8)
5319 return
\"%C1bc %T1,%j1,%l0
\";
5321 return
\"%C1bc %t1,%j1,$+
8\;b %l0
\";
5323 [(set_attr "type" "branch")])
5327 (if_then_else (match_operator
0 "branch_comparison_operator"
5329 "cc_reg_operand" "x,?y")
5334 "{%C0bcr|%C0bclr} %T0,%j0"
5335 [(set_attr "length" "
8")])
5337 ;; Unconditional branch and return.
5341 (label_ref (match_operand
0 "" "")))]
5345 (define_insn "return"
5350 (define_insn "indirect_jump"
5351 [(set (pc) (match_operand:SI
0 "register_operand" "c,l"))]
5357 ;; Table jump for switch statements:
5358 (define_expand "tablejump"
5360 (plus:SI (match_operand:SI
0 "" "")
5362 (parallel [(set (pc) (match_dup
3))
5363 (use (label_ref (match_operand
1 "" "")))])]
5366 { operands[
0] = force_reg (SImode, operands[
0]);
5367 operands[
2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[
1]));
5368 operands[
3] = gen_reg_rtx (SImode);
5373 (match_operand:SI
0 "register_operand" "c,l"))
5374 (use (label_ref (match_operand
1 "" "")))]
5385 ;; Define the subtract-one-and-jump insns, starting with the template
5386 ;; so loop.c knows what to generate.
5388 (define_expand "decrement_and_branchsi"
5389 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI
0 "register_operand" "c")
5391 (label_ref (match_operand
1 "" ""))
5393 (set (match_dup
0) (plus:SI (match_dup
0) (const_int -
1)))])]
5397 ;; We need to be able to do this for any operand, including MEM, or we
5398 ;; will cause reload to blow up since we don't allow output reloads on
5402 (if_then_else (ne (match_operand:SI
1 "register_operand" "
0,*r,*r")
5404 (label_ref (match_operand
2 "" ""))
5406 (set (match_operand:SI
0 "register_operand" "=c,*r,m*q*c*l")
5407 (plus:SI (match_dup
1) (const_int -
1)))
5408 (clobber (match_scratch:CC
3 "=X,&x,&x"))
5409 (clobber (match_scratch:SI
4 "=X,X,r"))]
5413 if (which_alternative !=
0)
5415 else if (get_attr_length (insn) ==
8)
5416 return
\"{bdn|bdnz} %l2
\";
5418 return
\"bdz $+
8\;b %l2
\";
5420 [(set_attr "type" "branch")])
5422 ;; Similar, but we can use GE since we have a REG_NONNEG.
5425 (if_then_else (ge (match_operand:SI
1 "register_operand" "
0,*r,*r")
5427 (label_ref (match_operand
2 "" ""))
5429 (set (match_operand:SI
0 "register_operand" "=c,*r,m*q*c*l")
5430 (plus:SI (match_dup
1) (const_int -
1)))
5431 (clobber (match_scratch:CC
3 "=X,&x,&X"))
5432 (clobber (match_scratch:SI
4 "=X,X,r"))]
5433 "find_reg_note (insn, REG_NONNEG,
0)"
5436 if (which_alternative !=
0)
5438 else if (get_attr_length (insn) ==
8)
5439 return
\"{bdn|bdnz} %l2
\";
5441 return
\"bdz $+
8\;b %l2
\";
5443 [(set_attr "type" "branch")])
5447 (if_then_else (eq (match_operand:SI
1 "register_operand" "
0,*r,*r")
5449 (label_ref (match_operand
2 "" ""))
5451 (set (match_operand:SI
0 "register_operand" "=c,*r,m*q*c*l")
5452 (plus:SI (match_dup
1) (const_int -
1)))
5453 (clobber (match_scratch:CC
3 "=X,&x,&x"))
5454 (clobber (match_scratch:SI
4 "=X,X,r"))]
5458 if (which_alternative !=
0)
5460 else if (get_attr_length (insn) ==
8)
5463 return
\"{bdn|bdnz} $+
8\;b %l2
\";
5465 [(set_attr "type" "branch")])
5469 (if_then_else (match_operator
2 "comparison_operator"
5470 [(match_operand:SI
1 "gpc_reg_operand" "")
5472 (match_operand
5 "" "")
5473 (match_operand
6 "" "")))
5474 (set (match_operand:SI
0 "gpc_reg_operand" "")
5475 (plus:SI (match_dup
1) (const_int -
1)))
5476 (clobber (match_scratch:CC
3 ""))
5477 (clobber (match_scratch:SI
4 ""))]
5479 [(parallel [(set (match_dup
3)
5480 (compare:CC (plus:SI (match_dup
1) (const_int -
1))
5482 (set (match_dup
0) (plus:SI (match_dup
1) (const_int -
1)))])
5483 (set (pc) (if_then_else (match_dup
7) (match_dup
5) (match_dup
6)))]
5485 { operands[
7] = gen_rtx (GET_CODE (operands[
2]), VOIDmode, operands[
3],
5490 (if_then_else (match_operator
2 "comparison_operator"
5491 [(match_operand:SI
1 "gpc_reg_operand" "")
5493 (match_operand
5 "" "")
5494 (match_operand
6 "" "")))
5495 (set (match_operand:SI
0 "general_operand" "")
5496 (plus:SI (match_dup
1) (const_int -
1)))
5497 (clobber (match_scratch:CC
3 ""))
5498 (clobber (match_scratch:SI
4 ""))]
5499 "reload_completed && ! gpc_reg_operand (operands[
0], SImode)"
5500 [(parallel [(set (match_dup
3)
5501 (compare:CC (plus:SI (match_dup
1) (const_int -
1))
5503 (set (match_dup
4) (plus:SI (match_dup
1) (const_int -
1)))])
5504 (set (match_dup
0) (match_dup
4))
5505 (set (pc) (if_then_else (match_dup
7) (match_dup
5) (match_dup
6)))]
5507 { operands[
7] = gen_rtx (GET_CODE (operands[
2]), VOIDmode, operands[
3],