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Add little endian PowerPC support.
[gcc.git] / gcc / config / rs6000 / rs6000.md
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
4
5 ;; This file is part of GNU CC.
6
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
11
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
16
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22 \f
23 ;; Define an insn type attribute. This is used in function unit delay
24 ;; computations.
25 (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
26 (const_string "integer"))
27
28 ;; Length (in bytes).
29 (define_attr "length" ""
30 (if_then_else (eq_attr "type" "branch")
31 (if_then_else (and (ge (minus (pc) (match_dup 0))
32 (const_int -32768))
33 (lt (minus (pc) (match_dup 0))
34 (const_int 32767)))
35 (const_int 8)
36 (const_int 12))
37 (const_int 4)))
38
39 ;; Processor type -- this attribute must exactly match the processor_type
40 ;; enumeration in rs6000.h.
41
42 (define_attr "cpu" "rios1,rios2,ppc403,ppc601,ppc603,ppc604,ppc620"
43 (const (symbol_ref "rs6000_cpu_attr")))
44
45 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
46 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
47
48 ; Load/Store Unit -- POWER/2 and pure PowerPC only
49 ; (POWER and 601 use Integer Unit)
50 (define_function_unit "lsu" 1 0
51 (and (eq_attr "type" "load")
52 (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
53 2 0)
54
55 (define_function_unit "lsu" 1 0
56 (and (eq_attr "type" "fpload")
57 (eq_attr "cpu" "rios2,ppc603,ppc604,ppc620"))
58 2 0)
59
60 (define_function_unit "iu" 1 0
61 (and (eq_attr "type" "load")
62 (eq_attr "cpu" "rios1,ppc403,ppc601"))
63 2 0)
64
65 (define_function_unit "iu" 1 0
66 (and (eq_attr "type" "fpload")
67 (eq_attr "cpu" "rios1,ppc601"))
68 3 0)
69
70 ; Integer Unit (RIOS1, PPC601, PPC603)
71 ; Trivial operations take one cycle which need not be listed here.
72 (define_function_unit "iu" 1 0
73 (and (eq_attr "type" "imul")
74 (eq_attr "cpu" "rios1"))
75 3 3)
76
77 (define_function_unit "iu" 1 0
78 (and (eq_attr "type" "imul")
79 (eq_attr "cpu" "ppc403"))
80 4 4)
81
82 (define_function_unit "iu" 1 0
83 (and (eq_attr "type" "imul")
84 (eq_attr "cpu" "ppc601,ppc603"))
85 5 5)
86
87 (define_function_unit "iu" 1 0
88 (and (eq_attr "type" "idiv")
89 (eq_attr "cpu" "rios1"))
90 19 19)
91
92 (define_function_unit "iu" 1 0
93 (and (eq_attr "type" "idiv")
94 (eq_attr "cpu" "ppc403"))
95 33 33)
96
97 (define_function_unit "iu" 1 0
98 (and (eq_attr "type" "idiv")
99 (eq_attr "cpu" "ppc601"))
100 36 36)
101
102 (define_function_unit "iu" 1 0
103 (and (eq_attr "type" "idiv")
104 (eq_attr "cpu" "ppc603"))
105 37 36)
106
107 ; RIOS2 has two integer units: a primary one which can perform all
108 ; operations and a secondary one which is fed in lock step with the first
109 ; and can perform "simple" integer operations.
110 (define_function_unit "iu2" 2 0
111 (and (eq_attr "type" "integer")
112 (eq_attr "cpu" "rios2"))
113 1 0
114 [(eq_attr "type" "imul,idiv")])
115
116 (define_function_unit "imuldiv" 1 0
117 (and (eq_attr "type" "imul")
118 (eq_attr "cpu" "rios2"))
119 2 2
120 [(eq_attr "type" "integer")])
121
122 (define_function_unit "imuldiv" 1 0
123 (and (eq_attr "type" "idiv")
124 (eq_attr "cpu" "rios2"))
125 13 13
126 [(eq_attr "type" "integer")])
127
128 ; PPC604 has three integer units: one primary and two secondary.
129 (define_function_unit "iu3" 3 0
130 (and (eq_attr "type" "integer")
131 (eq_attr "cpu" "ppc604,ppc620"))
132 1 0
133 [(eq_attr "type" "imul,idiv")])
134
135 (define_function_unit "imuldiv" 1 0
136 (and (eq_attr "type" "imul")
137 (eq_attr "cpu" "ppc604,ppc620"))
138 4 2
139 [(eq_attr "type" "integer")])
140
141 (define_function_unit "imuldiv" 1 0
142 (and (eq_attr "type" "idiv")
143 (eq_attr "cpu" "ppc604,ppc620"))
144 20 19
145 [(eq_attr "type" "integer")])
146
147 ; Branch Processing Unit
148 (define_function_unit "bpu" 1 0
149 (eq_attr "type" "compare")
150 4 0)
151
152 (define_function_unit "bpu" 1 0
153 (eq_attr "type" "delayed_compare")
154 5 0)
155
156 (define_function_unit "bpu" 1 0
157 (and (eq_attr "type" "fpcompare")
158 (eq_attr "cpu" "rios1,rios2"))
159 8 0)
160
161 (define_function_unit "bpu" 1 0
162 (and (eq_attr "type" "fpcompare")
163 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc620"))
164 4 0)
165
166 (define_function_unit "bpu" 1 0
167 (and (eq_attr "type" "mtjmpr")
168 (eq_attr "cpu" "rios1,rios2"))
169 5 0)
170
171 (define_function_unit "bpu" 1 0
172 (and (eq_attr "type" "mtjmpr")
173 (eq_attr "cpu" "ppc403,ppc601,ppc603,ppc604,ppc620"))
174 4 0)
175
176 ; Floating Point Unit (RIOS1, PPC601, PPC603, PPC604).
177 (define_function_unit "fpu" 1 0
178 (and (eq_attr "type" "fp,dmul")
179 (eq_attr "cpu" "rios1"))
180 2 0)
181
182 (define_function_unit "fpu" 1 0
183 (and (eq_attr "type" "fp")
184 (eq_attr "cpu" "ppc601"))
185 4 0)
186
187 (define_function_unit "fpu" 1 0
188 (and (eq_attr "type" "fp")
189 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
190 3 0)
191
192 (define_function_unit "fpu" 1 0
193 (and (eq_attr "type" "dmul")
194 (eq_attr "cpu" "ppc601"))
195 5 5)
196
197 (define_function_unit "fpu" 1 0
198 (and (eq_attr "type" "dmul")
199 (eq_attr "cpu" "ppc603"))
200 4 2)
201
202 (define_function_unit "fpu" 1 0
203 (and (eq_attr "type" "dmul")
204 (eq_attr "cpu" "ppc604,ppc620"))
205 3 0)
206
207 (define_function_unit "fpu" 1 0
208 (and (eq_attr "type" "sdiv,ddiv")
209 (eq_attr "cpu" "rios1"))
210 19 19)
211
212 (define_function_unit "fpu" 1 0
213 (and (eq_attr "type" "sdiv")
214 (eq_attr "cpu" "ppc601"))
215 17 17)
216
217 (define_function_unit "fpu" 1 0
218 (and (eq_attr "type" "sdiv")
219 (eq_attr "cpu" "ppc603,ppc604,ppc620"))
220 18 18)
221
222 (define_function_unit "fpu" 1 0
223 (and (eq_attr "type" "ddiv")
224 (eq_attr "cpu" "ppc601,ppc604,ppc620"))
225 31 31)
226
227 (define_function_unit "fpu" 1 0
228 (and (eq_attr "type" "ddiv")
229 (eq_attr "cpu" "ppc603"))
230 33 33)
231
232 (define_function_unit "fpu" 1 0
233 (and (eq_attr "type" "ssqrt")
234 (eq_attr "cpu" "ppc620"))
235 31 31)
236
237 (define_function_unit "fpu" 1 0
238 (and (eq_attr "type" "dsqrt")
239 (eq_attr "cpu" "ppc620"))
240 31 31)
241
242 ; RIOS2 has two symmetric FPUs.
243 (define_function_unit "fpu2" 2 0
244 (and (eq_attr "type" "fp")
245 (eq_attr "cpu" "rios2"))
246 2 0)
247
248 (define_function_unit "fpu2" 2 0
249 (and (eq_attr "type" "dmul")
250 (eq_attr "cpu" "rios2"))
251 2 0)
252
253 (define_function_unit "fpu2" 2 0
254 (and (eq_attr "type" "sdiv,ddiv")
255 (eq_attr "cpu" "rios2"))
256 17 17)
257
258 (define_function_unit "fpu2" 2 0
259 (and (eq_attr "type" "ssqrt,dsqrt")
260 (eq_attr "cpu" "rios2"))
261 26 26)
262 \f
263 ;; Start with fixed-point load and store insns. Here we put only the more
264 ;; complex forms. Basic data transfer is done later.
265
266 (define_expand "zero_extendqidi2"
267 [(set (match_operand:DI 0 "gpc_reg_operand" "")
268 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
269 "TARGET_POWERPC64"
270 "")
271
272 (define_insn ""
273 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
274 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
275 "TARGET_POWERPC64"
276 "@
277 lbz%U1%X1 %0,%1
278 rldicl %0,%1,0,56"
279 [(set_attr "type" "load,*")])
280
281 (define_insn ""
282 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
283 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
284 (const_int 0)))
285 (clobber (match_scratch:DI 2 "=r"))]
286 "TARGET_POWERPC64"
287 "rldicl. %2,%1,0,56"
288 [(set_attr "type" "compare")])
289
290 (define_insn ""
291 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
292 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
293 (const_int 0)))
294 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
295 (zero_extend:DI (match_dup 1)))]
296 "TARGET_POWERPC64"
297 "rldicl. %0,%1,0,56"
298 [(set_attr "type" "compare")])
299
300 (define_insn "extendqidi2"
301 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
302 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
303 "TARGET_POWERPC64"
304 "extsb %0,%1")
305
306 (define_insn ""
307 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
308 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
309 (const_int 0)))
310 (clobber (match_scratch:DI 2 "=r"))]
311 "TARGET_POWERPC64"
312 "extsb. %2,%1"
313 [(set_attr "type" "compare")])
314
315 (define_insn ""
316 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
317 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r"))
318 (const_int 0)))
319 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
320 (sign_extend:DI (match_dup 1)))]
321 "TARGET_POWERPC64"
322 "extsb. %0,%1"
323 [(set_attr "type" "compare")])
324
325 (define_expand "zero_extendhidi2"
326 [(set (match_operand:DI 0 "gpc_reg_operand" "")
327 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
328 "TARGET_POWERPC64"
329 "")
330
331 (define_insn ""
332 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
333 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
334 "TARGET_POWERPC64"
335 "@
336 lhz%U1%X1 %0,%1
337 rldicl %0,%1,0,48"
338 [(set_attr "type" "load,*")])
339
340 (define_insn ""
341 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
342 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
343 (const_int 0)))
344 (clobber (match_scratch:DI 2 "=r"))]
345 "TARGET_POWERPC64"
346 "rldicl. %2,%1,0,48"
347 [(set_attr "type" "compare")])
348
349 (define_insn ""
350 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
351 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
352 (const_int 0)))
353 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
354 (zero_extend:DI (match_dup 1)))]
355 "TARGET_POWERPC64"
356 "rldicl. %0,%1,0,48"
357 [(set_attr "type" "compare")])
358
359 (define_expand "extendhidi2"
360 [(set (match_operand:DI 0 "gpc_reg_operand" "")
361 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
362 "TARGET_POWERPC64"
363 "")
364
365 (define_insn ""
366 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
367 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
368 "TARGET_POWERPC64"
369 "@
370 lha%U1%X1 %0,%1
371 extsh %0,%1"
372 [(set_attr "type" "load,*")])
373
374 (define_insn ""
375 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
376 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
377 (const_int 0)))
378 (clobber (match_scratch:DI 2 "=r"))]
379 "TARGET_POWERPC64"
380 "extsh. %2,%1"
381 [(set_attr "type" "compare")])
382
383 (define_insn ""
384 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
385 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r"))
386 (const_int 0)))
387 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
388 (sign_extend:DI (match_dup 1)))]
389 "TARGET_POWERPC64"
390 "extsh. %0,%1"
391 [(set_attr "type" "compare")])
392
393 (define_expand "zero_extendsidi2"
394 [(set (match_operand:DI 0 "gpc_reg_operand" "")
395 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
396 "TARGET_POWERPC64"
397 "")
398
399 (define_insn ""
400 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
401 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
402 "TARGET_POWERPC64"
403 "@
404 lwz%U1%X1 %0,%1
405 rldicl %0,%1,0,32"
406 [(set_attr "type" "load,*")])
407
408 (define_insn ""
409 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
410 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
411 (const_int 0)))
412 (clobber (match_scratch:DI 2 "=r"))]
413 "TARGET_POWERPC64"
414 "rldicl. %2,%1,0,32"
415 [(set_attr "type" "compare")])
416
417 (define_insn ""
418 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
419 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
420 (const_int 0)))
421 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
422 (zero_extend:DI (match_dup 1)))]
423 "TARGET_POWERPC64"
424 "rldicl. %0,%1,0,32"
425 [(set_attr "type" "compare")])
426
427 (define_expand "extendsidi2"
428 [(set (match_operand:DI 0 "gpc_reg_operand" "")
429 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
430 "TARGET_POWERPC64"
431 "")
432
433 (define_insn ""
434 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
435 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
436 "TARGET_POWERPC64"
437 "@
438 lwa%U1%X1 %0,%1
439 extsw %0,%1"
440 [(set_attr "type" "load,*")])
441
442 (define_insn ""
443 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
444 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
445 (const_int 0)))
446 (clobber (match_scratch:DI 2 "=r"))]
447 "TARGET_POWERPC64"
448 "extsw. %2,%1"
449 [(set_attr "type" "compare")])
450
451 (define_insn ""
452 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
453 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
454 (const_int 0)))
455 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
456 (sign_extend:DI (match_dup 1)))]
457 "TARGET_POWERPC64"
458 "extsw. %0,%1"
459 [(set_attr "type" "compare")])
460
461 (define_expand "zero_extendqisi2"
462 [(set (match_operand:SI 0 "gpc_reg_operand" "")
463 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
464 ""
465 "")
466
467 (define_insn ""
468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
469 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
470 ""
471 "@
472 lbz%U1%X1 %0,%1
473 {rlinm|rlwinm} %0,%1,0,0xff"
474 [(set_attr "type" "load,*")])
475
476 (define_insn ""
477 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
478 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
479 (const_int 0)))
480 (clobber (match_scratch:SI 2 "=r"))]
481 ""
482 "{andil.|andi.} %2,%1,0xff"
483 [(set_attr "type" "compare")])
484
485 (define_insn ""
486 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
487 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
488 (const_int 0)))
489 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
490 (zero_extend:SI (match_dup 1)))]
491 ""
492 "{andil.|andi.} %0,%1,0xff"
493 [(set_attr "type" "compare")])
494
495 (define_expand "extendqisi2"
496 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
497 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
498 ""
499 "
500 {
501 if (TARGET_POWERPC)
502 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
503 else if (TARGET_POWER)
504 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
505 else
506 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
507 DONE;
508 }")
509
510 (define_insn "extendqisi2_ppc"
511 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
512 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
513 "TARGET_POWERPC"
514 "extsb %0,%1")
515
516 (define_insn ""
517 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
518 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
519 (const_int 0)))
520 (clobber (match_scratch:SI 2 "=r"))]
521 "TARGET_POWERPC"
522 "extsb. %2,%1"
523 [(set_attr "type" "compare")])
524
525 (define_insn ""
526 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
527 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
528 (const_int 0)))
529 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
530 (sign_extend:SI (match_dup 1)))]
531 "TARGET_POWERPC"
532 "extsb. %0,%1"
533 [(set_attr "type" "compare")])
534
535 (define_expand "extendqisi2_power"
536 [(parallel [(set (match_dup 2)
537 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
538 (const_int 24)))
539 (clobber (scratch:SI))])
540 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
541 (ashiftrt:SI (match_dup 2)
542 (const_int 24)))
543 (clobber (scratch:SI))])]
544 "TARGET_POWER"
545 "
546 { operands[1] = gen_lowpart (SImode, operands[1]);
547 operands[2] = gen_reg_rtx (SImode); }")
548
549 (define_expand "extendqisi2_no_power"
550 [(set (match_dup 2)
551 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
552 (const_int 24)))
553 (set (match_operand:SI 0 "gpc_reg_operand" "")
554 (ashiftrt:SI (match_dup 2)
555 (const_int 24)))]
556 "! TARGET_POWER && ! TARGET_POWERPC"
557 "
558 { operands[1] = gen_lowpart (SImode, operands[1]);
559 operands[2] = gen_reg_rtx (SImode); }")
560
561 (define_expand "zero_extendqihi2"
562 [(set (match_operand:HI 0 "gpc_reg_operand" "")
563 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
564 ""
565 "")
566
567 (define_insn ""
568 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
569 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
570 ""
571 "@
572 lbz%U1%X1 %0,%1
573 {rlinm|rlwinm} %0,%1,0,0xff"
574 [(set_attr "type" "load,*")])
575
576 (define_insn ""
577 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
578 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
579 (const_int 0)))
580 (clobber (match_scratch:HI 2 "=r"))]
581 ""
582 "{andil.|andi.} %2,%1,0xff"
583 [(set_attr "type" "compare")])
584
585 (define_insn ""
586 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
587 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
588 (const_int 0)))
589 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
590 (zero_extend:HI (match_dup 1)))]
591 ""
592 "{andil.|andi.} %0,%1,0xff"
593 [(set_attr "type" "compare")])
594
595 (define_expand "extendqihi2"
596 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
597 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
598 ""
599 "
600 {
601 if (TARGET_POWERPC)
602 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
603 else if (TARGET_POWER)
604 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
605 else
606 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
607 DONE;
608 }")
609
610 (define_insn "extendqihi2_ppc"
611 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
612 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
613 "TARGET_POWERPC"
614 "extsb %0,%1")
615
616 (define_insn ""
617 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
618 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
619 (const_int 0)))
620 (clobber (match_scratch:HI 2 "=r"))]
621 "TARGET_POWERPC"
622 "extsb. %2,%1"
623 [(set_attr "type" "compare")])
624
625 (define_insn ""
626 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
627 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r"))
628 (const_int 0)))
629 (set (match_operand:HI 0 "gpc_reg_operand" "=r")
630 (sign_extend:HI (match_dup 1)))]
631 "TARGET_POWERPC"
632 "extsb. %0,%1"
633 [(set_attr "type" "compare")])
634
635 (define_expand "extendqihi2_power"
636 [(parallel [(set (match_dup 2)
637 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
638 (const_int 24)))
639 (clobber (scratch:SI))])
640 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
641 (ashiftrt:SI (match_dup 2)
642 (const_int 24)))
643 (clobber (scratch:SI))])]
644 "TARGET_POWER"
645 "
646 { operands[0] = gen_lowpart (SImode, operands[0]);
647 operands[1] = gen_lowpart (SImode, operands[1]);
648 operands[2] = gen_reg_rtx (SImode); }")
649
650 (define_expand "extendqihi2_no_power"
651 [(set (match_dup 2)
652 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
653 (const_int 24)))
654 (set (match_operand:HI 0 "gpc_reg_operand" "")
655 (ashiftrt:SI (match_dup 2)
656 (const_int 24)))]
657 "! TARGET_POWER && ! TARGET_POWERPC"
658 "
659 { operands[0] = gen_lowpart (SImode, operands[0]);
660 operands[1] = gen_lowpart (SImode, operands[1]);
661 operands[2] = gen_reg_rtx (SImode); }")
662
663 (define_expand "zero_extendhisi2"
664 [(set (match_operand:SI 0 "gpc_reg_operand" "")
665 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
666 ""
667 "")
668
669 (define_insn ""
670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
671 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
672 ""
673 "@
674 lhz%U1%X1 %0,%1
675 {rlinm|rlwinm} %0,%1,0,0xffff"
676 [(set_attr "type" "load,*")])
677
678 (define_insn ""
679 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
680 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
681 (const_int 0)))
682 (clobber (match_scratch:SI 2 "=r"))]
683 ""
684 "{andil.|andi.} %2,%1,0xffff"
685 [(set_attr "type" "compare")])
686
687 (define_insn ""
688 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
689 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
690 (const_int 0)))
691 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
692 (zero_extend:SI (match_dup 1)))]
693 ""
694 "{andil.|andi.} %0,%1,0xffff"
695 [(set_attr "type" "compare")])
696
697 (define_expand "extendhisi2"
698 [(set (match_operand:SI 0 "gpc_reg_operand" "")
699 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
700 ""
701 "")
702
703 (define_insn ""
704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
705 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
706 ""
707 "@
708 lha%U1%X1 %0,%1
709 {exts|extsh} %0,%1"
710 [(set_attr "type" "load,*")])
711
712 (define_insn ""
713 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
714 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
715 (const_int 0)))
716 (clobber (match_scratch:SI 2 "=r"))]
717 ""
718 "{exts.|extsh.} %2,%1"
719 [(set_attr "type" "compare")])
720
721 (define_insn ""
722 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
723 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
724 (const_int 0)))
725 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
726 (sign_extend:SI (match_dup 1)))]
727 ""
728 "{exts.|extsh.} %0,%1"
729 [(set_attr "type" "compare")])
730 \f
731 ;; Fixed-point arithmetic insns.
732
733 ;; Discourage ai/addic because of carry but provide it in an alternative
734 ;; allowing register zero as source.
735 (define_insn "addsi3"
736 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
737 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
738 (match_operand:SI 2 "add_operand" "r,I,I,J")))]
739 ""
740 "@
741 {cax|add} %0,%1,%2
742 {cal %0,%2(%1)|addi %0,%1,%2}
743 {ai|addic} %0,%1,%2
744 {cau|addis} %0,%1,%u2")
745
746 (define_insn ""
747 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
748 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
749 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
750 (const_int 0)))
751 (clobber (match_scratch:SI 3 "=r,r"))]
752 ""
753 "@
754 {cax.|add.} %3,%1,%2
755 {ai.|addic.} %3,%1,%2"
756 [(set_attr "type" "compare")])
757
758 (define_insn ""
759 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
760 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
761 (match_operand:SI 2 "reg_or_short_operand" "r,I"))
762 (const_int 0)))
763 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
764 (plus:SI (match_dup 1) (match_dup 2)))]
765 ""
766 "@
767 {cax.|add.} %0,%1,%2
768 {ai.|addic.} %0,%1,%2"
769 [(set_attr "type" "compare")])
770
771 ;; Split an add that we can't do in one insn into two insns, each of which
772 ;; does one 16-bit part. This is used by combine. Note that the low-order
773 ;; add should be last in case the result gets used in an address.
774
775 (define_split
776 [(set (match_operand:SI 0 "gpc_reg_operand" "")
777 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
778 (match_operand:SI 2 "non_add_cint_operand" "")))]
779 ""
780 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
781 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
782 "
783 {
784 int low = INTVAL (operands[2]) & 0xffff;
785 int high = (unsigned) INTVAL (operands[2]) >> 16;
786
787 if (low & 0x8000)
788 high++, low |= 0xffff0000;
789
790 operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
791 operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
792 }")
793
794 (define_insn "one_cmplsi2"
795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
796 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
797 ""
798 "nor %0,%1,%1")
799
800 (define_insn ""
801 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
802 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
803 (const_int 0)))
804 (clobber (match_scratch:SI 2 "=r"))]
805 ""
806 "nor. %2,%1,%1"
807 [(set_attr "type" "compare")])
808
809 (define_insn ""
810 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
811 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
812 (const_int 0)))
813 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
814 (not:SI (match_dup 1)))]
815 ""
816 "nor. %0,%2,%1"
817 [(set_attr "type" "compare")])
818
819 (define_insn ""
820 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
821 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
822 (match_operand:SI 2 "gpc_reg_operand" "r")))]
823 "! TARGET_POWERPC"
824 "{sf%I1|subf%I1c} %0,%2,%1")
825
826 (define_insn ""
827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
828 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
829 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
830 "TARGET_POWERPC"
831 "@
832 subf %0,%2,%1
833 subfic %0,%2,%1")
834
835 (define_insn ""
836 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
837 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
838 (match_operand:SI 2 "gpc_reg_operand" "r"))
839 (const_int 0)))
840 (clobber (match_scratch:SI 3 "=r"))]
841 "! TARGET_POWERPC"
842 "{sf.|subfc.} %3,%2,%1"
843 [(set_attr "type" "compare")])
844
845 (define_insn ""
846 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
847 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
848 (match_operand:SI 2 "gpc_reg_operand" "r"))
849 (const_int 0)))
850 (clobber (match_scratch:SI 3 "=r"))]
851 "TARGET_POWERPC"
852 "subf. %3,%2,%1"
853 [(set_attr "type" "compare")])
854
855 (define_insn ""
856 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
857 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
858 (match_operand:SI 2 "gpc_reg_operand" "r"))
859 (const_int 0)))
860 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
861 (minus:SI (match_dup 1) (match_dup 2)))]
862 "! TARGET_POWERPC"
863 "{sf.|subfc.} %0,%2,%1"
864 [(set_attr "type" "compare")])
865
866 (define_insn ""
867 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
868 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
869 (match_operand:SI 2 "gpc_reg_operand" "r"))
870 (const_int 0)))
871 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
872 (minus:SI (match_dup 1) (match_dup 2)))]
873 "TARGET_POWERPC"
874 "subf. %0,%2,%1"
875 [(set_attr "type" "compare")])
876
877 (define_expand "subsi3"
878 [(set (match_operand:SI 0 "gpc_reg_operand" "")
879 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
880 (match_operand:SI 2 "reg_or_cint_operand" "")))]
881 ""
882 "
883 {
884 if (GET_CODE (operands[2]) == CONST_INT)
885 {
886 emit_insn (gen_addsi3 (operands[0], operands[1],
887 negate_rtx (SImode, operands[2])));
888 DONE;
889 }
890 }")
891
892 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
893 ;; instruction and some auxiliary computations. Then we just have a single
894 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
895 ;; combine.
896
897 (define_expand "sminsi3"
898 [(set (match_dup 3)
899 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
900 (match_operand:SI 2 "reg_or_short_operand" ""))
901 (const_int 0)
902 (minus:SI (match_dup 2) (match_dup 1))))
903 (set (match_operand:SI 0 "gpc_reg_operand" "")
904 (minus:SI (match_dup 2) (match_dup 3)))]
905 "TARGET_POWER"
906 "
907 { operands[3] = gen_reg_rtx (SImode); }")
908
909 (define_split
910 [(set (match_operand:SI 0 "gpc_reg_operand" "")
911 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
912 (match_operand:SI 2 "reg_or_short_operand" "")))
913 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
914 "TARGET_POWER"
915 [(set (match_dup 3)
916 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
917 (const_int 0)
918 (minus:SI (match_dup 2) (match_dup 1))))
919 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
920 "")
921
922 (define_expand "smaxsi3"
923 [(set (match_dup 3)
924 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
925 (match_operand:SI 2 "reg_or_short_operand" ""))
926 (const_int 0)
927 (minus:SI (match_dup 2) (match_dup 1))))
928 (set (match_operand:SI 0 "gpc_reg_operand" "")
929 (plus:SI (match_dup 3) (match_dup 1)))]
930 "TARGET_POWER"
931 "
932 { operands[3] = gen_reg_rtx (SImode); }")
933
934 (define_split
935 [(set (match_operand:SI 0 "gpc_reg_operand" "")
936 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
937 (match_operand:SI 2 "reg_or_short_operand" "")))
938 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
939 "TARGET_POWER"
940 [(set (match_dup 3)
941 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
942 (const_int 0)
943 (minus:SI (match_dup 2) (match_dup 1))))
944 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
945 "")
946
947 (define_expand "uminsi3"
948 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
949 (match_dup 5)))
950 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
951 (match_dup 5)))
952 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
953 (const_int 0)
954 (minus:SI (match_dup 4) (match_dup 3))))
955 (set (match_operand:SI 0 "gpc_reg_operand" "")
956 (minus:SI (match_dup 2) (match_dup 3)))]
957 "TARGET_POWER"
958 "
959 {
960 operands[3] = gen_reg_rtx (SImode);
961 operands[4] = gen_reg_rtx (SImode);
962 operands[5] = GEN_INT (-2147483647 - 1);
963 }")
964
965 (define_expand "umaxsi3"
966 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
967 (match_dup 5)))
968 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
969 (match_dup 5)))
970 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
971 (const_int 0)
972 (minus:SI (match_dup 4) (match_dup 3))))
973 (set (match_operand:SI 0 "gpc_reg_operand" "")
974 (plus:SI (match_dup 3) (match_dup 1)))]
975 "TARGET_POWER"
976 "
977 {
978 operands[3] = gen_reg_rtx (SImode);
979 operands[4] = gen_reg_rtx (SImode);
980 operands[5] = GEN_INT (-2147483647 - 1);
981 }")
982
983 (define_insn ""
984 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
985 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
986 (match_operand:SI 2 "reg_or_short_operand" "rI"))
987 (const_int 0)
988 (minus:SI (match_dup 2) (match_dup 1))))]
989 "TARGET_POWER"
990 "doz%I2 %0,%1,%2")
991
992 (define_insn ""
993 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
994 (compare:CC
995 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
996 (match_operand:SI 2 "reg_or_short_operand" "rI"))
997 (const_int 0)
998 (minus:SI (match_dup 2) (match_dup 1)))
999 (const_int 0)))
1000 (clobber (match_scratch:SI 3 "=r"))]
1001 "TARGET_POWER"
1002 "doz%I2. %3,%1,%2"
1003 [(set_attr "type" "delayed_compare")])
1004
1005 (define_insn ""
1006 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1007 (compare:CC
1008 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1009 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1010 (const_int 0)
1011 (minus:SI (match_dup 2) (match_dup 1)))
1012 (const_int 0)))
1013 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1014 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1015 (const_int 0)
1016 (minus:SI (match_dup 2) (match_dup 1))))]
1017 "TARGET_POWER"
1018 "doz%I2. %0,%1,%2"
1019 [(set_attr "type" "delayed_compare")])
1020
1021 ;; We don't need abs with condition code because such comparisons should
1022 ;; never be done.
1023 (define_expand "abssi2"
1024 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1025 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1026 ""
1027 "
1028 {
1029 if (!TARGET_POWER)
1030 {
1031 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1032 DONE;
1033 }
1034 }")
1035
1036 (define_insn "abssi2_power"
1037 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1038 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1039 "TARGET_POWER"
1040 "abs %0,%1")
1041
1042 (define_insn "abssi2_nopower"
1043 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1044 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1045 (clobber (match_scratch:SI 2 "=&r,&r"))]
1046 "!TARGET_POWER"
1047 "*
1048 {
1049 return (TARGET_POWERPC)
1050 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
1051 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
1052 }"
1053 [(set_attr "length" "12")])
1054
1055 (define_split
1056 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1057 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1058 (clobber (match_scratch:SI 2 "=&r,&r"))]
1059 "!TARGET_POWER && reload_completed"
1060 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1061 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1062 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1063 "")
1064
1065 (define_insn ""
1066 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1067 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1068 "TARGET_POWER"
1069 "nabs %0,%1")
1070
1071 (define_insn ""
1072 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1073 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1074 (clobber (match_scratch:SI 2 "=&r,&r"))]
1075 "!TARGET_POWER"
1076 "*
1077 {
1078 return (TARGET_POWERPC)
1079 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
1080 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
1081 }"
1082 [(set_attr "length" "12")])
1083
1084 (define_split
1085 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1086 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1087 (clobber (match_scratch:SI 2 "=&r,&r"))]
1088 "!TARGET_POWER && reload_completed"
1089 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1090 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1091 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1092 "")
1093
1094 (define_insn "negsi2"
1095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1096 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1097 ""
1098 "neg %0,%1")
1099
1100 (define_insn ""
1101 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1102 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1103 (const_int 0)))
1104 (clobber (match_scratch:SI 2 "=r"))]
1105 ""
1106 "neg. %2,%1"
1107 [(set_attr "type" "compare")])
1108
1109 (define_insn ""
1110 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
1111 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1112 (const_int 0)))
1113 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1114 (neg:SI (match_dup 1)))]
1115 ""
1116 "neg. %0,%1"
1117 [(set_attr "type" "compare")])
1118
1119 (define_insn "ffssi2"
1120 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1121 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1122 ""
1123 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
1124 [(set_attr "length" "16")])
1125
1126 (define_expand "mulsi3"
1127 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1128 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1129 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1130 ""
1131 "
1132 {
1133 if (TARGET_POWER)
1134 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
1135 else
1136 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
1137 DONE;
1138 }")
1139
1140 (define_insn "mulsi3_mq"
1141 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1142 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1143 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
1144 (clobber (match_scratch:SI 3 "=q,q"))]
1145 "TARGET_POWER"
1146 "@
1147 {muls|mullw} %0,%1,%2
1148 {muli|mulli} %0,%1,%2"
1149 [(set_attr "type" "imul")])
1150
1151 (define_insn "mulsi3_no_mq"
1152 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1153 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
1154 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
1155 "! TARGET_POWER"
1156 "@
1157 mullw %0,%1,%2
1158 mulli %0,%1,%2"
1159 [(set_attr "type" "imul")])
1160
1161 (define_insn ""
1162 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1163 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1164 (match_operand:SI 2 "gpc_reg_operand" "r"))
1165 (const_int 0)))
1166 (clobber (match_scratch:SI 3 "=r"))
1167 (clobber (match_scratch:SI 4 "=q"))]
1168 "TARGET_POWER"
1169 "{muls.|mullw.} %3,%1,%2"
1170 [(set_attr "type" "delayed_compare")])
1171
1172 (define_insn ""
1173 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1174 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1175 (match_operand:SI 2 "gpc_reg_operand" "r"))
1176 (const_int 0)))
1177 (clobber (match_scratch:SI 3 "=r"))]
1178 "! TARGET_POWER"
1179 "mullw. %3,%1,%2"
1180 [(set_attr "type" "delayed_compare")])
1181
1182 (define_insn ""
1183 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1184 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1185 (match_operand:SI 2 "gpc_reg_operand" "r"))
1186 (const_int 0)))
1187 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1188 (mult:SI (match_dup 1) (match_dup 2)))
1189 (clobber (match_scratch:SI 4 "=q"))]
1190 "TARGET_POWER"
1191 "{muls.|mullw.} %0,%1,%2"
1192 [(set_attr "type" "delayed_compare")])
1193
1194 (define_insn ""
1195 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1196 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1197 (match_operand:SI 2 "gpc_reg_operand" "r"))
1198 (const_int 0)))
1199 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1200 (mult:SI (match_dup 1) (match_dup 2)))]
1201 "! TARGET_POWER"
1202 "mullw. %0,%1,%2"
1203 [(set_attr "type" "delayed_compare")])
1204
1205 ;; Operand 1 is divided by operand 2; quotient goes to operand
1206 ;; 0 and remainder to operand 3.
1207 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
1208
1209 (define_expand "divmodsi4"
1210 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1211 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1212 (match_operand:SI 2 "gpc_reg_operand" "")))
1213 (set (match_operand:SI 3 "gpc_reg_operand" "")
1214 (mod:SI (match_dup 1) (match_dup 2)))])]
1215 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1216 "
1217 {
1218 if (! TARGET_POWER && ! TARGET_POWERPC)
1219 {
1220 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1221 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1222 emit_insn (gen_divss_call ());
1223 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1224 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1225 DONE;
1226 }
1227 }")
1228
1229 (define_insn ""
1230 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1231 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1232 (match_operand:SI 2 "gpc_reg_operand" "r")))
1233 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
1234 (mod:SI (match_dup 1) (match_dup 2)))]
1235 "TARGET_POWER"
1236 "divs %0,%1,%2"
1237 [(set_attr "type" "idiv")])
1238
1239 (define_insn ""
1240 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1241 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1242 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1243 "TARGET_POWERPC"
1244 "divw %0,%1,%2"
1245 [(set_attr "type" "idiv")])
1246
1247 (define_expand "udivsi3"
1248 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1249 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1250 (match_operand:SI 2 "gpc_reg_operand" "")))]
1251 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1252 "
1253 {
1254 if (! TARGET_POWER && ! TARGET_POWERPC)
1255 {
1256 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1257 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1258 emit_insn (gen_quous_call ());
1259 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1260 DONE;
1261 }
1262 }")
1263
1264 (define_insn ""
1265 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1266 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1267 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1268 "TARGET_POWERPC"
1269 "divwu %0,%1,%2"
1270 [(set_attr "type" "idiv")])
1271
1272 ;; For powers of two we can do srai/aze for divide and then adjust for
1273 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1274 ;; used; for PowerPC, force operands into register and do a normal divide;
1275 ;; for AIX common-mode, use quoss call on register operands.
1276 (define_expand "divsi3"
1277 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1278 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
1279 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1280 ""
1281 "
1282 {
1283 if (GET_CODE (operands[2]) == CONST_INT
1284 && exact_log2 (INTVAL (operands[2])) >= 0)
1285 ;
1286 else if (TARGET_POWER && ! TARGET_POWERPC)
1287 FAIL;
1288 else
1289 operands[2] = force_reg (SImode, operands[2]);
1290
1291 if (! TARGET_POWER && ! TARGET_POWERPC)
1292 {
1293 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1294 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1295 emit_insn (gen_quoss_call ());
1296 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1297 DONE;
1298 }
1299 }")
1300
1301 (define_expand "modsi3"
1302 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1303 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1304 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
1305 ""
1306 "
1307 {
1308 int i = exact_log2 (INTVAL (operands[2]));
1309 rtx temp1;
1310 rtx temp2;
1311
1312 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
1313 FAIL;
1314
1315 temp1 = gen_reg_rtx (SImode);
1316 temp2 = gen_reg_rtx (SImode);
1317
1318 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
1319 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1320 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
1321 DONE;
1322 }")
1323
1324 (define_insn ""
1325 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1326 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1327 (match_operand:SI 2 "const_int_operand" "N")))]
1328 "exact_log2 (INTVAL (operands[2])) >= 0"
1329 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
1330 [(set_attr "length" "8")])
1331
1332 (define_insn ""
1333 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1334 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1335 (match_operand:SI 2 "const_int_operand" "N"))
1336 (const_int 0)))
1337 (clobber (match_scratch:SI 3 "=r"))]
1338 "exact_log2 (INTVAL (operands[2])) >= 0"
1339 "{srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3"
1340 [(set_attr "type" "compare")
1341 (set_attr "length" "8")])
1342
1343 (define_insn ""
1344 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1345 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
1346 (match_operand:SI 2 "const_int_operand" "N"))
1347 (const_int 0)))
1348 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1349 (div:SI (match_dup 1) (match_dup 2)))]
1350 "exact_log2 (INTVAL (operands[2])) >= 0"
1351 "{srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0"
1352 [(set_attr "type" "compare")
1353 (set_attr "length" "8")])
1354
1355 (define_insn ""
1356 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1357 (udiv:SI
1358 (plus:DI (ashift:DI
1359 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
1360 (const_int 32))
1361 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
1362 (match_operand:SI 3 "gpc_reg_operand" "r")))
1363 (set (match_operand:SI 2 "register_operand" "=*q")
1364 (umod:SI
1365 (plus:DI (ashift:DI
1366 (zero_extend:DI (match_dup 1)) (const_int 32))
1367 (zero_extend:DI (match_dup 4)))
1368 (match_dup 3)))]
1369 "TARGET_POWER"
1370 "div %0,%1,%3"
1371 [(set_attr "type" "idiv")])
1372
1373 ;; To do unsigned divide we handle the cases of the divisor looking like a
1374 ;; negative number. If it is a constant that is less than 2**31, we don't
1375 ;; have to worry about the branches. So make a few subroutines here.
1376 ;;
1377 ;; First comes the normal case.
1378 (define_expand "udivmodsi4_normal"
1379 [(set (match_dup 4) (const_int 0))
1380 (parallel [(set (match_operand:SI 0 "" "")
1381 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1382 (const_int 32))
1383 (zero_extend:DI (match_operand:SI 1 "" "")))
1384 (match_operand:SI 2 "" "")))
1385 (set (match_operand:SI 3 "" "")
1386 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
1387 (const_int 32))
1388 (zero_extend:DI (match_dup 1)))
1389 (match_dup 2)))])]
1390 "TARGET_POWER"
1391 "
1392 { operands[4] = gen_reg_rtx (SImode); }")
1393
1394 ;; This handles the branches.
1395 (define_expand "udivmodsi4_tests"
1396 [(set (match_operand:SI 0 "" "") (const_int 0))
1397 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
1398 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
1399 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
1400 (label_ref (match_operand:SI 4 "" "")) (pc)))
1401 (set (match_dup 0) (const_int 1))
1402 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
1403 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
1404 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
1405 (label_ref (match_dup 4)) (pc)))]
1406 "TARGET_POWER"
1407 "
1408 { operands[5] = gen_reg_rtx (CCUNSmode);
1409 operands[6] = gen_reg_rtx (CCmode);
1410 }")
1411
1412 (define_expand "udivmodsi4"
1413 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1414 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
1415 (match_operand:SI 2 "reg_or_cint_operand" "")))
1416 (set (match_operand:SI 3 "gpc_reg_operand" "")
1417 (umod:SI (match_dup 1) (match_dup 2)))])]
1418 ""
1419 "
1420 {
1421 rtx label = 0;
1422
1423 if (! TARGET_POWER)
1424 if (! TARGET_POWERPC)
1425 {
1426 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
1427 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
1428 emit_insn (gen_divus_call ());
1429 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
1430 emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
1431 DONE;
1432 }
1433 else
1434 FAIL;
1435
1436 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
1437 {
1438 operands[2] = force_reg (SImode, operands[2]);
1439 label = gen_label_rtx ();
1440 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
1441 operands[3], label));
1442 }
1443 else
1444 operands[2] = force_reg (SImode, operands[2]);
1445
1446 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
1447 operands[3]));
1448 if (label)
1449 emit_label (label);
1450
1451 DONE;
1452 }")
1453
1454 ;; AIX architecture-independent common-mode multiply (DImode),
1455 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1456 ;; R4; results in R3 and somtimes R4; link register always clobbered by bla
1457 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1458 ;; assumed unused if generating common-mode, so ignore.
1459 (define_insn "mulh_call"
1460 [(set (reg:SI 3)
1461 (truncate:SI
1462 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
1463 (sign_extend:DI (reg:SI 4)))
1464 (const_int 32))))
1465 (clobber (match_scratch:SI 0 "=l"))]
1466 "! TARGET_POWER && ! TARGET_POWERPC"
1467 "bla __mulh")
1468
1469 (define_insn "mull_call"
1470 [(set (reg:DI 3)
1471 (mult:DI (sign_extend:DI (reg:SI 3))
1472 (sign_extend:DI (reg:SI 4))))
1473 (clobber (match_scratch:SI 0 "=l"))
1474 (clobber (reg:SI 0))]
1475 "! TARGET_POWER && ! TARGET_POWERPC"
1476 "bla __mull")
1477
1478 (define_insn "divss_call"
1479 [(set (reg:SI 3)
1480 (div:SI (reg:SI 3) (reg:SI 4)))
1481 (set (reg:SI 4)
1482 (mod:SI (reg:SI 3) (reg:SI 4)))
1483 (clobber (match_scratch:SI 0 "=l"))
1484 (clobber (reg:SI 0))]
1485 "! TARGET_POWER && ! TARGET_POWERPC"
1486 "bla __divss")
1487
1488 (define_insn "divus_call"
1489 [(set (reg:SI 3)
1490 (udiv:SI (reg:SI 3) (reg:SI 4)))
1491 (set (reg:SI 4)
1492 (umod:SI (reg:SI 3) (reg:SI 4)))
1493 (clobber (match_scratch:SI 0 "=l"))
1494 (clobber (reg:SI 0))]
1495 "! TARGET_POWER && ! TARGET_POWERPC"
1496 "bla __divus")
1497
1498 (define_insn "quoss_call"
1499 [(set (reg:SI 3)
1500 (div:SI (reg:SI 3) (reg:SI 4)))
1501 (clobber (match_scratch:SI 0 "=l"))]
1502 "! TARGET_POWER && ! TARGET_POWERPC"
1503 "bla __quoss")
1504
1505 (define_insn "quous_call"
1506 [(set (reg:SI 3)
1507 (udiv:SI (reg:SI 3) (reg:SI 4)))
1508 (clobber (match_scratch:SI 0 "=l"))
1509 (clobber (reg:SI 0))]
1510 "! TARGET_POWER && ! TARGET_POWERPC"
1511 "bla __quous")
1512 \f
1513 (define_insn "andsi3"
1514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1515 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1516 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
1517 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
1518 ""
1519 "@
1520 and %0,%1,%2
1521 {rlinm|rlwinm} %0,%1,0,%m2,%M2
1522 {andil.|andi.} %0,%1,%b2
1523 {andiu.|andis.} %0,%1,%u2")
1524
1525 (define_insn ""
1526 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
1527 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1528 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1529 (const_int 0)))
1530 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1531 ""
1532 "@
1533 and. %3,%1,%2
1534 {andil.|andi.} %3,%1,%b2
1535 {andiu.|andis.} %3,%1,%u2
1536 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2"
1537 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1538
1539 (define_insn ""
1540 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
1541 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1542 (match_operand:SI 2 "and_operand" "r,K,J,L"))
1543 (const_int 0)))
1544 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1545 (and:SI (match_dup 1) (match_dup 2)))]
1546 ""
1547 "@
1548 and. %0,%1,%2
1549 {andil.|andi.} %0,%1,%b2
1550 {andiu.|andis.} %0,%1,%u2
1551 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2"
1552 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1553
1554 ;; Take a AND with a constant that cannot be done in a single insn and try to
1555 ;; split it into two insns. This does not verify that the insns are valid
1556 ;; since this need not be done as combine will do it.
1557
1558 (define_split
1559 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1560 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
1561 (match_operand:SI 2 "non_and_cint_operand" "")))]
1562 ""
1563 [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
1564 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
1565 "
1566 {
1567 int maskval = INTVAL (operands[2]);
1568 int i, transitions, last_bit_value;
1569 int orig = maskval, first_c = maskval, second_c;
1570
1571 /* We know that MASKVAL must have more than 2 bit-transitions. Start at
1572 the low-order bit and count for the third transition. When we get there,
1573 make a first mask that has everything to the left of that position
1574 a one. Then make the second mask to turn off whatever else is needed. */
1575
1576 for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
1577 {
1578 if (((maskval >>= 1) & 1) != last_bit_value)
1579 last_bit_value ^= 1, transitions++;
1580
1581 if (transitions > 2)
1582 {
1583 first_c |= (~0) << i;
1584 break;
1585 }
1586 }
1587
1588 second_c = orig | ~ first_c;
1589
1590 operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
1591 operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
1592 }")
1593
1594 (define_insn "iorsi3"
1595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1596 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1597 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1598 ""
1599 "@
1600 or %0,%1,%2
1601 {oril|ori} %0,%1,%b2
1602 {oriu|oris} %0,%1,%u2")
1603
1604 (define_insn ""
1605 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1606 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1607 (match_operand:SI 2 "gpc_reg_operand" "r"))
1608 (const_int 0)))
1609 (clobber (match_scratch:SI 3 "=r"))]
1610 ""
1611 "or. %3,%1,%2"
1612 [(set_attr "type" "compare")])
1613
1614 (define_insn ""
1615 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1616 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1617 (match_operand:SI 2 "gpc_reg_operand" "r"))
1618 (const_int 0)))
1619 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1620 (ior:SI (match_dup 1) (match_dup 2)))]
1621 ""
1622 "or. %0,%1,%2"
1623 [(set_attr "type" "compare")])
1624
1625 ;; Split an IOR that we can't do in one insn into two insns, each of which
1626 ;; does one 16-bit part. This is used by combine.
1627
1628 (define_split
1629 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1630 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
1631 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1632 ""
1633 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
1634 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
1635 "
1636 {
1637 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1638 INTVAL (operands[2]) & 0xffff0000);
1639 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1640 }")
1641
1642 (define_insn "xorsi3"
1643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
1644 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
1645 (match_operand:SI 2 "logical_operand" "r,K,J")))]
1646 ""
1647 "@
1648 xor %0,%1,%2
1649 {xoril|xori} %0,%1,%b2
1650 {xoriu|xoris} %0,%1,%u2")
1651
1652 (define_insn ""
1653 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1654 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1655 (match_operand:SI 2 "gpc_reg_operand" "r"))
1656 (const_int 0)))
1657 (clobber (match_scratch:SI 3 "=r"))]
1658 ""
1659 "xor. %3,%1,%2"
1660 [(set_attr "type" "compare")])
1661
1662 (define_insn ""
1663 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1664 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1665 (match_operand:SI 2 "gpc_reg_operand" "r"))
1666 (const_int 0)))
1667 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1668 (xor:SI (match_dup 1) (match_dup 2)))]
1669 ""
1670 "xor. %0,%1,%2"
1671 [(set_attr "type" "compare")])
1672
1673 ;; Split an XOR that we can't do in one insn into two insns, each of which
1674 ;; does one 16-bit part. This is used by combine.
1675
1676 (define_split
1677 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1678 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1679 (match_operand:SI 2 "non_logical_cint_operand" "")))]
1680 ""
1681 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
1682 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
1683 "
1684 {
1685 operands[3] = gen_rtx (CONST_INT, VOIDmode,
1686 INTVAL (operands[2]) & 0xffff0000);
1687 operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
1688 }")
1689
1690 (define_insn ""
1691 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1692 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1693 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1694 ""
1695 "eqv %0,%1,%2")
1696
1697 (define_insn ""
1698 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1699 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1700 (match_operand:SI 2 "gpc_reg_operand" "r")))
1701 (const_int 0)))
1702 (clobber (match_scratch:SI 3 "=r"))]
1703 ""
1704 "eqv. %3,%1,%2"
1705 [(set_attr "type" "compare")])
1706
1707 (define_insn ""
1708 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1709 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
1710 (match_operand:SI 2 "gpc_reg_operand" "r")))
1711 (const_int 0)))
1712 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1713 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
1714 ""
1715 "eqv. %0,%1,%2"
1716 [(set_attr "type" "compare")])
1717
1718 (define_insn ""
1719 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1720 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1721 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1722 ""
1723 "andc %0,%2,%1")
1724
1725 (define_insn ""
1726 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1727 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1728 (match_operand:SI 2 "gpc_reg_operand" "r"))
1729 (const_int 0)))
1730 (clobber (match_scratch:SI 3 "=r"))]
1731 ""
1732 "andc. %3,%2,%1"
1733 [(set_attr "type" "compare")])
1734
1735 (define_insn ""
1736 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1737 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1738 (match_operand:SI 2 "gpc_reg_operand" "r"))
1739 (const_int 0)))
1740 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1741 (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
1742 ""
1743 "andc. %0,%2,%1"
1744 [(set_attr "type" "compare")])
1745
1746 (define_insn ""
1747 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1748 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1749 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1750 ""
1751 "orc %0,%2,%1")
1752
1753 (define_insn ""
1754 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1755 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1756 (match_operand:SI 2 "gpc_reg_operand" "r"))
1757 (const_int 0)))
1758 (clobber (match_scratch:SI 3 "=r"))]
1759 ""
1760 "orc. %3,%2,%1"
1761 [(set_attr "type" "compare")])
1762
1763 (define_insn ""
1764 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1765 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
1766 (match_operand:SI 2 "gpc_reg_operand" "r"))
1767 (const_int 0)))
1768 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1769 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
1770 ""
1771 "orc. %0,%2,%1"
1772 [(set_attr "type" "compare")])
1773
1774 (define_insn ""
1775 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1776 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1777 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1778 ""
1779 "nand %0,%1,%2")
1780
1781 (define_insn ""
1782 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1783 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1784 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1785 (const_int 0)))
1786 (clobber (match_scratch:SI 3 "=r"))]
1787 ""
1788 "nand. %3,%1,%2"
1789 [(set_attr "type" "compare")])
1790
1791 (define_insn ""
1792 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1793 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1794 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1795 (const_int 0)))
1796 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1797 (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1798 ""
1799 "nand. %0,%1,%2"
1800 [(set_attr "type" "compare")])
1801
1802 (define_insn ""
1803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1804 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1805 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
1806 ""
1807 "nor %0,%1,%2")
1808
1809 (define_insn ""
1810 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1811 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1812 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1813 (const_int 0)))
1814 (clobber (match_scratch:SI 3 "=r"))]
1815 ""
1816 "nor. %3,%1,%2"
1817 [(set_attr "type" "compare")])
1818
1819 (define_insn ""
1820 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1821 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "%r"))
1822 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
1823 (const_int 0)))
1824 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1825 (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
1826 ""
1827 "nor. %0,%1,%2"
1828 [(set_attr "type" "compare")])
1829
1830 ;; maskir insn. We need four forms because things might be in arbitrary
1831 ;; orders. Don't define forms that only set CR fields because these
1832 ;; would modify an input register.
1833
1834 (define_insn ""
1835 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1836 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1837 (match_operand:SI 1 "gpc_reg_operand" "0"))
1838 (and:SI (match_dup 2)
1839 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
1840 "TARGET_POWER"
1841 "maskir %0,%3,%2")
1842
1843 (define_insn ""
1844 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1845 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1846 (match_operand:SI 1 "gpc_reg_operand" "0"))
1847 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1848 (match_dup 2))))]
1849 "TARGET_POWER"
1850 "maskir %0,%3,%2")
1851
1852 (define_insn ""
1853 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1854 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1855 (match_operand:SI 3 "gpc_reg_operand" "r"))
1856 (and:SI (not:SI (match_dup 2))
1857 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1858 "TARGET_POWER"
1859 "maskir %0,%3,%2")
1860
1861 (define_insn ""
1862 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1863 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1864 (match_operand:SI 2 "gpc_reg_operand" "r"))
1865 (and:SI (not:SI (match_dup 2))
1866 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
1867 "TARGET_POWER"
1868 "maskir %0,%3,%2")
1869
1870 (define_insn ""
1871 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1872 (compare:CC
1873 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1874 (match_operand:SI 1 "gpc_reg_operand" "0"))
1875 (and:SI (match_dup 2)
1876 (match_operand:SI 3 "gpc_reg_operand" "r")))
1877 (const_int 0)))
1878 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1879 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
1880 (and:SI (match_dup 2) (match_dup 3))))]
1881 "TARGET_POWER"
1882 "maskir. %0,%3,%2"
1883 [(set_attr "type" "compare")])
1884
1885 (define_insn ""
1886 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1887 (compare:CC
1888 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
1889 (match_operand:SI 1 "gpc_reg_operand" "0"))
1890 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1891 (match_dup 2)))
1892 (const_int 0)))
1893 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1894 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
1895 (and:SI (match_dup 3) (match_dup 2))))]
1896 "TARGET_POWER"
1897 "maskir. %0,%3,%2"
1898 [(set_attr "type" "compare")])
1899
1900 (define_insn ""
1901 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1902 (compare:CC
1903 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
1904 (match_operand:SI 3 "gpc_reg_operand" "r"))
1905 (and:SI (not:SI (match_dup 2))
1906 (match_operand:SI 1 "gpc_reg_operand" "0")))
1907 (const_int 0)))
1908 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1909 (ior:SI (and:SI (match_dup 2) (match_dup 3))
1910 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
1911 "TARGET_POWER"
1912 "maskir. %0,%3,%2"
1913 [(set_attr "type" "compare")])
1914
1915 (define_insn ""
1916 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1917 (compare:CC
1918 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1919 (match_operand:SI 2 "gpc_reg_operand" "r"))
1920 (and:SI (not:SI (match_dup 2))
1921 (match_operand:SI 1 "gpc_reg_operand" "0")))
1922 (const_int 0)))
1923 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1924 (ior:SI (and:SI (match_dup 3) (match_dup 2))
1925 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
1926 "TARGET_POWER"
1927 "maskir. %0,%3,%2"
1928 [(set_attr "type" "compare")])
1929 \f
1930 ;; Rotate and shift insns, in all their variants. These support shifts,
1931 ;; field inserts and extracts, and various combinations thereof.
1932 (define_insn "insv"
1933 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1934 (match_operand:SI 1 "const_int_operand" "i")
1935 (match_operand:SI 2 "const_int_operand" "i"))
1936 (match_operand:SI 3 "gpc_reg_operand" "r"))]
1937 ""
1938 "*
1939 {
1940 int start = INTVAL (operands[2]) & 31;
1941 int size = INTVAL (operands[1]) & 31;
1942
1943 operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1944 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1945 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
1946 }")
1947
1948 (define_insn ""
1949 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1950 (match_operand:SI 1 "const_int_operand" "i")
1951 (match_operand:SI 2 "const_int_operand" "i"))
1952 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1953 (match_operand:SI 4 "const_int_operand" "i")))]
1954 ""
1955 "*
1956 {
1957 int shift = INTVAL (operands[4]) & 31;
1958 int start = INTVAL (operands[2]) & 31;
1959 int size = INTVAL (operands[1]) & 31;
1960
1961 operands[4] = gen_rtx (CONST_INT, VOIDmode, (shift - start - size) & 31);
1962 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1963 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
1964 }")
1965
1966 (define_insn ""
1967 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1968 (match_operand:SI 1 "const_int_operand" "i")
1969 (match_operand:SI 2 "const_int_operand" "i"))
1970 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1971 (match_operand:SI 4 "const_int_operand" "i")))]
1972 ""
1973 "*
1974 {
1975 int shift = INTVAL (operands[4]) & 31;
1976 int start = INTVAL (operands[2]) & 31;
1977 int size = INTVAL (operands[1]) & 31;
1978
1979 operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
1980 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1981 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
1982 }")
1983
1984 (define_insn ""
1985 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
1986 (match_operand:SI 1 "const_int_operand" "i")
1987 (match_operand:SI 2 "const_int_operand" "i"))
1988 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
1989 (match_operand:SI 4 "const_int_operand" "i")))]
1990 ""
1991 "*
1992 {
1993 int shift = INTVAL (operands[4]) & 31;
1994 int start = INTVAL (operands[2]) & 31;
1995 int size = INTVAL (operands[1]) & 31;
1996
1997 operands[4] = gen_rtx (CONST_INT, VOIDmode, (32 - shift - start - size) & 31);
1998 operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1999 return \"{rlimi|rlwimi} %0,%3,%4,%h2,%h1\";
2000 }")
2001
2002 (define_insn ""
2003 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2004 (match_operand:SI 1 "const_int_operand" "i")
2005 (match_operand:SI 2 "const_int_operand" "i"))
2006 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
2007 (match_operand:SI 4 "const_int_operand" "i")
2008 (match_operand:SI 5 "const_int_operand" "i")))]
2009 "INTVAL (operands[4]) >= INTVAL (operands[1])"
2010 "*
2011 {
2012 int extract_start = INTVAL (operands[5]) & 31;
2013 int extract_size = INTVAL (operands[4]) & 31;
2014 int insert_start = INTVAL (operands[2]) & 31;
2015 int insert_size = INTVAL (operands[1]) & 31;
2016
2017 /* Align extract field with insert field */
2018 operands[5] = gen_rtx (CONST_INT, VOIDmode,
2019 (extract_start + extract_size - insert_start - insert_size) & 31);
2020 operands[1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size - 1);
2021 return \"{rlimi|rlwimi} %0,%3,%5,%h2,%h1\";
2022 }")
2023
2024 (define_insn "extzv"
2025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2026 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2027 (match_operand:SI 2 "const_int_operand" "i")
2028 (match_operand:SI 3 "const_int_operand" "i")))]
2029 ""
2030 "*
2031 {
2032 int start = INTVAL (operands[3]) & 31;
2033 int size = INTVAL (operands[2]) & 31;
2034
2035 if (start + size >= 32)
2036 operands[3] = const0_rtx;
2037 else
2038 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2039 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
2040 }")
2041
2042 (define_insn ""
2043 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2044 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2045 (match_operand:SI 2 "const_int_operand" "i")
2046 (match_operand:SI 3 "const_int_operand" "i"))
2047 (const_int 0)))
2048 (clobber (match_scratch:SI 4 "=r"))]
2049 ""
2050 "*
2051 {
2052 int start = INTVAL (operands[3]) & 31;
2053 int size = INTVAL (operands[2]) & 31;
2054
2055 /* If the bitfield being tested fits in the upper or lower half of a
2056 word, it is possible to use andiu. or andil. to test it. This is
2057 useful because the condition register set-use delay is smaller for
2058 andi[ul]. than for rlinm. This doesn't work when the starting bit
2059 position is 0 because the LT and GT bits may be set wrong. */
2060
2061 if ((start > 0 && start + size <= 16) || start >= 16)
2062 {
2063 operands[3] = gen_rtx (CONST_INT, VOIDmode,
2064 ((1 << (16 - (start & 15)))
2065 - (1 << (16 - (start & 15) - size))));
2066 if (start < 16)
2067 return \"{andiu.|andis.} %4,%1,%3\";
2068 else
2069 return \"{andil.|andi.} %4,%1,%3\";
2070 }
2071
2072 if (start + size >= 32)
2073 operands[3] = const0_rtx;
2074 else
2075 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2076 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
2077 }"
2078 [(set_attr "type" "compare")])
2079
2080 (define_insn ""
2081 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2082 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2083 (match_operand:SI 2 "const_int_operand" "i")
2084 (match_operand:SI 3 "const_int_operand" "i"))
2085 (const_int 0)))
2086 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2087 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
2088 ""
2089 "*
2090 {
2091 int start = INTVAL (operands[3]) & 31;
2092 int size = INTVAL (operands[2]) & 31;
2093
2094 if (start >= 16 && start + size == 32)
2095 {
2096 operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
2097 return \"{andil.|andi.} %0,%1,%3\";
2098 }
2099
2100 if (start + size >= 32)
2101 operands[3] = const0_rtx;
2102 else
2103 operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2104 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
2105 }"
2106 [(set_attr "type" "delayed_compare")])
2107
2108 (define_insn "rotlsi3"
2109 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2110 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2111 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2112 ""
2113 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
2114
2115 (define_insn ""
2116 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2117 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2118 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2119 (const_int 0)))
2120 (clobber (match_scratch:SI 3 "=r"))]
2121 ""
2122 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff"
2123 [(set_attr "type" "delayed_compare")])
2124
2125 (define_insn ""
2126 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2127 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2128 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2129 (const_int 0)))
2130 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2131 (rotate:SI (match_dup 1) (match_dup 2)))]
2132 ""
2133 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff"
2134 [(set_attr "type" "delayed_compare")])
2135
2136 (define_insn ""
2137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2138 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2139 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2140 (match_operand:SI 3 "mask_operand" "L")))]
2141 ""
2142 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
2143
2144 (define_insn ""
2145 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2146 (compare:CC (and:SI
2147 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2148 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2149 (match_operand:SI 3 "mask_operand" "L"))
2150 (const_int 0)))
2151 (clobber (match_scratch:SI 4 "=r"))]
2152 ""
2153 "{rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3"
2154 [(set_attr "type" "delayed_compare")])
2155
2156 (define_insn ""
2157 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2158 (compare:CC (and:SI
2159 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2160 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2161 (match_operand:SI 3 "mask_operand" "L"))
2162 (const_int 0)))
2163 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2164 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2165 ""
2166 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3"
2167 [(set_attr "type" "delayed_compare")])
2168
2169 (define_insn ""
2170 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2171 (zero_extend:SI
2172 (subreg:QI
2173 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2174 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2175 ""
2176 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
2177
2178 (define_insn ""
2179 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2180 (compare:CC (zero_extend:SI
2181 (subreg:QI
2182 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2183 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2184 (const_int 0)))
2185 (clobber (match_scratch:SI 3 "=r"))]
2186 ""
2187 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff"
2188 [(set_attr "type" "delayed_compare")])
2189
2190 (define_insn ""
2191 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2192 (compare:CC (zero_extend:SI
2193 (subreg:QI
2194 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2195 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2196 (const_int 0)))
2197 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2198 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2199 ""
2200 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff"
2201 [(set_attr "type" "delayed_compare")])
2202
2203 (define_insn ""
2204 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2205 (zero_extend:SI
2206 (subreg:HI
2207 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2208 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
2209 ""
2210 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
2211
2212 (define_insn ""
2213 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2214 (compare:CC (zero_extend:SI
2215 (subreg:HI
2216 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2217 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2218 (const_int 0)))
2219 (clobber (match_scratch:SI 3 "=r"))]
2220 ""
2221 "{rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff"
2222 [(set_attr "type" "delayed_compare")])
2223
2224 (define_insn ""
2225 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2226 (compare:CC (zero_extend:SI
2227 (subreg:HI
2228 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2229 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
2230 (const_int 0)))
2231 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2232 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
2233 ""
2234 "{rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff"
2235 [(set_attr "type" "delayed_compare")])
2236
2237 ;; Note that we use "sle." instead of "sl." so that we can set
2238 ;; SHIFT_COUNT_TRUNCATED.
2239
2240 (define_expand "ashlsi3"
2241 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2242 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2243 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2244 ""
2245 "
2246 {
2247 if (TARGET_POWER)
2248 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
2249 else
2250 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
2251 DONE;
2252 }")
2253
2254 (define_insn "ashlsi3_power"
2255 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2256 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2257 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2258 (clobber (match_scratch:SI 3 "=q,X"))]
2259 "TARGET_POWER"
2260 "@
2261 sle %0,%1,%2
2262 {sli|slwi} %0,%1,%h2"
2263 [(set_attr "length" "8")])
2264
2265 (define_insn "ashlsi3_no_power"
2266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2267 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2268 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2269 "! TARGET_POWER"
2270 "slw%I2 %0,%1,%h2"
2271 [(set_attr "length" "8")])
2272
2273 (define_insn ""
2274 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2275 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2276 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2277 (const_int 0)))
2278 (clobber (match_scratch:SI 3 "=r,r"))
2279 (clobber (match_scratch:SI 4 "=q,X"))]
2280 "TARGET_POWER"
2281 "@
2282 sle. %3,%1,%2
2283 {sli.|slwi.} %3,%1,%h2"
2284 [(set_attr "type" "delayed_compare")])
2285
2286 (define_insn ""
2287 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2288 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2289 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2290 (const_int 0)))
2291 (clobber (match_scratch:SI 3 "=r"))]
2292 "! TARGET_POWER"
2293 "slw%I2. %3,%1,%h2"
2294 [(set_attr "type" "delayed_compare")])
2295
2296 (define_insn ""
2297 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2298 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2299 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2300 (const_int 0)))
2301 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2302 (ashift:SI (match_dup 1) (match_dup 2)))
2303 (clobber (match_scratch:SI 4 "=q,X"))]
2304 "TARGET_POWER"
2305 "@
2306 sle. %0,%1,%2
2307 {sli.|slwi.} %0,%1,%h2"
2308 [(set_attr "type" "delayed_compare")])
2309
2310 (define_insn ""
2311 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2312 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2313 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2314 (const_int 0)))
2315 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2316 (ashift:SI (match_dup 1) (match_dup 2)))]
2317 "! TARGET_POWER"
2318 "slw%I2. %0,%1,%h2"
2319 [(set_attr "type" "delayed_compare")])
2320
2321 (define_insn ""
2322 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2323 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2324 (match_operand:SI 2 "const_int_operand" "i"))
2325 (match_operand:SI 3 "mask_operand" "L")))]
2326 "includes_lshift_p (operands[2], operands[3])"
2327 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
2328
2329 (define_insn ""
2330 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2331 (compare:CC
2332 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2333 (match_operand:SI 2 "const_int_operand" "i"))
2334 (match_operand:SI 3 "mask_operand" "L"))
2335 (const_int 0)))
2336 (clobber (match_scratch:SI 4 "=r"))]
2337 "includes_lshift_p (operands[2], operands[3])"
2338 "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
2339 [(set_attr "type" "delayed_compare")])
2340
2341 (define_insn ""
2342 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2343 (compare:CC
2344 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2345 (match_operand:SI 2 "const_int_operand" "i"))
2346 (match_operand:SI 3 "mask_operand" "L"))
2347 (const_int 0)))
2348 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2349 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2350 "includes_lshift_p (operands[2], operands[3])"
2351 "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
2352 [(set_attr "type" "delayed_compare")])
2353
2354 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
2355 ;; "sli x,x,0".
2356 (define_expand "lshrsi3"
2357 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2358 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2359 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2360 ""
2361 "
2362 {
2363 if (TARGET_POWER)
2364 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
2365 else
2366 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
2367 DONE;
2368 }")
2369
2370 (define_insn "lshrsi3_power"
2371 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2372 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2373 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2374 (clobber (match_scratch:SI 3 "=q,X"))]
2375 "TARGET_POWER"
2376 "@
2377 sre %0,%1,%2
2378 {s%A2i|s%A2wi} %0,%1,%h2")
2379
2380 (define_insn "lshrsi3_no_power"
2381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2382 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2383 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2384 "! TARGET_POWER"
2385 "srw%I2 %0,%1,%h2")
2386
2387 (define_insn ""
2388 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2389 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2390 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2391 (const_int 0)))
2392 (clobber (match_scratch:SI 3 "=r,r"))
2393 (clobber (match_scratch:SI 4 "=q,X"))]
2394 "TARGET_POWER"
2395 "@
2396 sre. %3,%1,%2
2397 {s%A2i.|s%A2wi.} %3,%1,%h2"
2398 [(set_attr "type" "delayed_compare")])
2399
2400 (define_insn ""
2401 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2402 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2403 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2404 (const_int 0)))
2405 (clobber (match_scratch:SI 3 "=r"))]
2406 "! TARGET_POWER"
2407 "srw%I2. %3,%1,%h2"
2408 [(set_attr "type" "delayed_compare")])
2409
2410 (define_insn ""
2411 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2412 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2413 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2414 (const_int 0)))
2415 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2416 (lshiftrt:SI (match_dup 1) (match_dup 2)))
2417 (clobber (match_scratch:SI 4 "=q,X"))]
2418 "TARGET_POWER"
2419 "@
2420 sre. %0,%1,%2
2421 {s%A2i.|s%A2wi.} %0,%1,%h2"
2422 [(set_attr "type" "delayed_compare")])
2423
2424 (define_insn ""
2425 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2426 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2427 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2428 (const_int 0)))
2429 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2430 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
2431 "! TARGET_POWER"
2432 "srw%I2. %0,%1,%h2"
2433 [(set_attr "type" "delayed_compare")])
2434
2435 (define_insn ""
2436 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2437 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2438 (match_operand:SI 2 "const_int_operand" "i"))
2439 (match_operand:SI 3 "mask_operand" "L")))]
2440 "includes_rshift_p (operands[2], operands[3])"
2441 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
2442
2443 (define_insn ""
2444 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2445 (compare:CC
2446 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2447 (match_operand:SI 2 "const_int_operand" "i"))
2448 (match_operand:SI 3 "mask_operand" "L"))
2449 (const_int 0)))
2450 (clobber (match_scratch:SI 4 "=r"))]
2451 "includes_rshift_p (operands[2], operands[3])"
2452 "{rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3"
2453 [(set_attr "type" "delayed_compare")])
2454
2455 (define_insn ""
2456 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
2457 (compare:CC
2458 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2459 (match_operand:SI 2 "const_int_operand" "i"))
2460 (match_operand:SI 3 "mask_operand" "L"))
2461 (const_int 0)))
2462 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2463 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
2464 "includes_rshift_p (operands[2], operands[3])"
2465 "{rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3"
2466 [(set_attr "type" "delayed_compare")])
2467
2468 (define_insn ""
2469 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2470 (zero_extend:SI
2471 (subreg:QI
2472 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2473 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2474 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2475 "{rlinm|rlwinm} %0,%1,%s2,0xff")
2476
2477 (define_insn ""
2478 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2479 (compare:CC
2480 (zero_extend:SI
2481 (subreg:QI
2482 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2483 (match_operand:SI 2 "const_int_operand" "i")) 0))
2484 (const_int 0)))
2485 (clobber (match_scratch:SI 3 "=r"))]
2486 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2487 "{rlinm.|rlwinm.} %3,%1,%s2,0xff"
2488 [(set_attr "type" "delayed_compare")])
2489
2490 (define_insn ""
2491 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2492 (compare:CC
2493 (zero_extend:SI
2494 (subreg:QI
2495 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2496 (match_operand:SI 2 "const_int_operand" "i")) 0))
2497 (const_int 0)))
2498 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2499 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2500 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
2501 "{rlinm.|rlwinm.} %0,%1,%s2,0xff"
2502 [(set_attr "type" "delayed_compare")])
2503
2504 (define_insn ""
2505 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2506 (zero_extend:SI
2507 (subreg:HI
2508 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2509 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
2510 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2511 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
2512
2513 (define_insn ""
2514 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2515 (compare:CC
2516 (zero_extend:SI
2517 (subreg:HI
2518 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2519 (match_operand:SI 2 "const_int_operand" "i")) 0))
2520 (const_int 0)))
2521 (clobber (match_scratch:SI 3 "=r"))]
2522 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2523 "{rlinm.|rlwinm.} %3,%1,%s2,0xffff"
2524 [(set_attr "type" "delayed_compare")])
2525
2526 (define_insn ""
2527 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2528 (compare:CC
2529 (zero_extend:SI
2530 (subreg:HI
2531 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2532 (match_operand:SI 2 "const_int_operand" "i")) 0))
2533 (const_int 0)))
2534 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2535 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
2536 "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
2537 "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
2538 [(set_attr "type" "delayed_compare")])
2539
2540 (define_insn ""
2541 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2542 (const_int 1)
2543 (match_operand:SI 1 "gpc_reg_operand" "r"))
2544 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2545 (const_int 31)))]
2546 "TARGET_POWER"
2547 "rrib %0,%1,%2")
2548
2549 (define_insn ""
2550 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2551 (const_int 1)
2552 (match_operand:SI 1 "gpc_reg_operand" "r"))
2553 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2554 (const_int 31)))]
2555 "TARGET_POWER"
2556 "rrib %0,%1,%2")
2557
2558 (define_insn ""
2559 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
2560 (const_int 1)
2561 (match_operand:SI 1 "gpc_reg_operand" "r"))
2562 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
2563 (const_int 1)
2564 (const_int 0)))]
2565 "TARGET_POWER"
2566 "rrib %0,%1,%2")
2567
2568 (define_expand "ashrsi3"
2569 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2570 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
2571 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2572 ""
2573 "
2574 {
2575 if (TARGET_POWER)
2576 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
2577 else
2578 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
2579 DONE;
2580 }")
2581
2582 (define_insn "ashrsi3_power"
2583 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2584 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2585 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
2586 (clobber (match_scratch:SI 3 "=q,X"))]
2587 "TARGET_POWER"
2588 "@
2589 srea %0,%1,%2
2590 {srai|srawi} %0,%1,%h2")
2591
2592 (define_insn "ashrsi3_no_power"
2593 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2594 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2595 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
2596 "! TARGET_POWER"
2597 "sraw%I2 %0,%1,%h2")
2598
2599 (define_insn ""
2600 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
2601 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2602 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2603 (const_int 0)))
2604 (clobber (match_scratch:SI 3 "=r,r"))
2605 (clobber (match_scratch:SI 4 "=q,X"))]
2606 "TARGET_POWER"
2607 "@
2608 srea. %3,%1,%2
2609 {srai.|srawi.} %3,%1,%h2"
2610 [(set_attr "type" "delayed_compare")])
2611
2612 (define_insn ""
2613 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
2614 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2615 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2616 (const_int 0)))
2617 (clobber (match_scratch:SI 3 "=r"))]
2618 "! TARGET_POWER"
2619 "sraw%I2. %3,%1,%h2"
2620 [(set_attr "type" "delayed_compare")])
2621
2622 (define_insn ""
2623 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
2624 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2625 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
2626 (const_int 0)))
2627 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2628 (ashiftrt:SI (match_dup 1) (match_dup 2)))
2629 (clobber (match_scratch:SI 4 "=q,X"))]
2630 "TARGET_POWER"
2631 "@
2632 srea. %0,%1,%2
2633 {srai.|srawi.} %0,%1,%h2"
2634 [(set_attr "type" "delayed_compare")])
2635
2636 (define_insn ""
2637 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
2638 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2639 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
2640 (const_int 0)))
2641 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2642 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
2643 "! TARGET_POWER"
2644 "sraw%I2. %0,%1,%h2"
2645 [(set_attr "type" "delayed_compare")])
2646 \f
2647 ;; Floating-point insns, excluding normal data motion.
2648 ;;
2649 ;; PowerPC has a full set of single-precision floating point instructions.
2650 ;;
2651 ;; For the POWER architecture, we pretend that we have both SFmode and
2652 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2653 ;; The only conversions we will do will be when storing to memory. In that
2654 ;; case, we will use the "frsp" instruction before storing.
2655 ;;
2656 ;; Note that when we store into a single-precision memory location, we need to
2657 ;; use the frsp insn first. If the register being stored isn't dead, we
2658 ;; need a scratch register for the frsp. But this is difficult when the store
2659 ;; is done by reload. It is not incorrect to do the frsp on the register in
2660 ;; this case, we just lose precision that we would have otherwise gotten but
2661 ;; is not guaranteed. Perhaps this should be tightened up at some point.
2662
2663 (define_insn "extendsfdf2"
2664 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
2665 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2666 "TARGET_HARD_FLOAT"
2667 "*
2668 {
2669 if (REGNO (operands[0]) == REGNO (operands[1]))
2670 return \"\";
2671 else
2672 return \"fmr %0,%1\";
2673 }"
2674 [(set_attr "type" "fp")])
2675
2676 (define_insn "truncdfsf2"
2677 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2678 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
2679 "TARGET_HARD_FLOAT"
2680 "frsp %0,%1"
2681 [(set_attr "type" "fp")])
2682
2683 (define_insn "negsf2"
2684 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2685 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2686 "TARGET_HARD_FLOAT"
2687 "fneg %0,%1"
2688 [(set_attr "type" "fp")])
2689
2690 (define_insn "abssf2"
2691 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2692 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2693 "TARGET_HARD_FLOAT"
2694 "fabs %0,%1"
2695 [(set_attr "type" "fp")])
2696
2697 (define_insn ""
2698 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2699 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
2700 "TARGET_HARD_FLOAT"
2701 "fnabs %0,%1"
2702 [(set_attr "type" "fp")])
2703
2704 (define_expand "addsf3"
2705 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2706 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2707 (match_operand:SF 2 "gpc_reg_operand" "")))]
2708 "TARGET_HARD_FLOAT"
2709 "")
2710
2711 (define_insn ""
2712 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2713 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2714 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2715 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2716 "fadds %0,%1,%2"
2717 [(set_attr "type" "fp")])
2718
2719 (define_insn ""
2720 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2721 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2722 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2723 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2724 "{fa|fadd} %0,%1,%2"
2725 [(set_attr "type" "fp")])
2726
2727 (define_expand "subsf3"
2728 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2729 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2730 (match_operand:SF 2 "gpc_reg_operand" "")))]
2731 "TARGET_HARD_FLOAT"
2732 "")
2733
2734 (define_insn ""
2735 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2736 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2737 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2738 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2739 "fsubs %0,%1,%2"
2740 [(set_attr "type" "fp")])
2741
2742 (define_insn ""
2743 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2744 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2745 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2746 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2747 "{fs|fsub} %0,%1,%2"
2748 [(set_attr "type" "fp")])
2749
2750 (define_expand "mulsf3"
2751 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2752 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
2753 (match_operand:SF 2 "gpc_reg_operand" "")))]
2754 "TARGET_HARD_FLOAT"
2755 "")
2756
2757 (define_insn ""
2758 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2759 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2760 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2761 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2762 "fmuls %0,%1,%2"
2763 [(set_attr "type" "fp")])
2764
2765 (define_insn ""
2766 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2767 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2768 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2769 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2770 "{fm|fmul} %0,%1,%2"
2771 [(set_attr "type" "fp")])
2772
2773 (define_expand "divsf3"
2774 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2775 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
2776 (match_operand:SF 2 "gpc_reg_operand" "")))]
2777 "TARGET_HARD_FLOAT"
2778 "")
2779
2780 (define_insn ""
2781 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2782 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2783 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2784 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2785 "fdivs %0,%1,%2"
2786 [(set_attr "type" "sdiv")])
2787
2788 (define_insn ""
2789 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2790 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
2791 (match_operand:SF 2 "gpc_reg_operand" "f")))]
2792 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2793 "{fd|fdiv} %0,%1,%2"
2794 [(set_attr "type" "sdiv")])
2795
2796 (define_insn ""
2797 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2798 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2799 (match_operand:SF 2 "gpc_reg_operand" "f"))
2800 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2801 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2802 "fmadds %0,%1,%2,%3"
2803 [(set_attr "type" "fp")])
2804
2805 (define_insn ""
2806 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2807 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2808 (match_operand:SF 2 "gpc_reg_operand" "f"))
2809 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2810 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2811 "{fma|fmadd} %0,%1,%2,%3"
2812 [(set_attr "type" "fp")])
2813
2814 (define_insn ""
2815 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2816 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2817 (match_operand:SF 2 "gpc_reg_operand" "f"))
2818 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2819 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2820 "fmsubs %0,%1,%2,%3"
2821 [(set_attr "type" "fp")])
2822
2823 (define_insn ""
2824 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2825 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2826 (match_operand:SF 2 "gpc_reg_operand" "f"))
2827 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2828 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2829 "{fms|fmsub} %0,%1,%2,%3"
2830 [(set_attr "type" "fp")])
2831
2832 (define_insn ""
2833 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2834 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2835 (match_operand:SF 2 "gpc_reg_operand" "f"))
2836 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2837 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2838 "fnmadds %0,%1,%2,%3"
2839 [(set_attr "type" "fp")])
2840
2841 (define_insn ""
2842 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2843 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2844 (match_operand:SF 2 "gpc_reg_operand" "f"))
2845 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2846 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2847 "{fnma|fnmadd} %0,%1,%2,%3"
2848 [(set_attr "type" "fp")])
2849
2850 (define_insn ""
2851 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2852 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2853 (match_operand:SF 2 "gpc_reg_operand" "f"))
2854 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2855 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2856 "fnmsubs %0,%1,%2,%3"
2857 [(set_attr "type" "fp")])
2858
2859 (define_insn ""
2860 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2861 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
2862 (match_operand:SF 2 "gpc_reg_operand" "f"))
2863 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
2864 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2865 "{fnms|fnmsub} %0,%1,%2,%3"
2866 [(set_attr "type" "fp")])
2867
2868 (define_expand "sqrtsf2"
2869 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2870 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
2871 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
2872 "")
2873
2874 (define_insn ""
2875 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2876 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2877 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
2878 "fsqrts %0,%1"
2879 [(set_attr "type" "ssqrt")])
2880
2881 (define_insn ""
2882 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2883 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
2884 "TARGET_POWER2 && TARGET_HARD_FLOAT"
2885 "fsqrt %0,%1"
2886 [(set_attr "type" "dsqrt")])
2887
2888 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
2889 ;; fsel instruction and some auxiliary computations. Then we just have a
2890 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
2891 ;; combine.
2892 (define_expand "maxsf3"
2893 [(set (match_dup 3)
2894 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
2895 (match_operand:SF 2 "gpc_reg_operand" "")))
2896 (set (match_operand:SF 0 "gpc_reg_operand" "")
2897 (if_then_else:SF (ge (match_dup 3)
2898 (const_int 0))
2899 (match_dup 1)
2900 (match_dup 2)))]
2901 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2902 "
2903 { operands[3] = gen_reg_rtx (SFmode); }")
2904
2905 (define_split
2906 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2907 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
2908 (match_operand:SF 2 "gpc_reg_operand" "")))
2909 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
2910 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2911 [(set (match_dup 3)
2912 (minus:SF (match_dup 1) (match_dup 2)))
2913 (set (match_dup 0)
2914 (if_then_else:SF (ge (match_dup 3)
2915 (const_int 0))
2916 (match_dup 1)
2917 (match_dup 2)))]
2918 "")
2919
2920 (define_expand "minsf3"
2921 [(set (match_dup 3)
2922 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
2923 (match_operand:SF 1 "gpc_reg_operand" "")))
2924 (set (match_operand:SF 0 "gpc_reg_operand" "")
2925 (if_then_else:SF (ge (match_dup 3)
2926 (const_int 0))
2927 (match_dup 1)
2928 (match_dup 2)))]
2929 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2930 "
2931 { operands[3] = gen_reg_rtx (SFmode); }")
2932
2933 (define_split
2934 [(set (match_operand:SF 0 "gpc_reg_operand" "")
2935 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
2936 (match_operand:SF 2 "gpc_reg_operand" "")))
2937 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
2938 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2939 [(set (match_dup 3)
2940 (minus:SF (match_dup 2) (match_dup 1)))
2941 (set (match_dup 0)
2942 (if_then_else:SF (ge (match_dup 3)
2943 (const_int 0))
2944 (match_dup 1)
2945 (match_dup 2)))]
2946 "")
2947
2948 (define_expand "movsfcc"
2949 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
2950 (if_then_else:SF (match_operand 1 "comparison_operator" "")
2951 (match_operand:SF 2 "gpc_reg_operand" "f")
2952 (match_operand:SF 3 "gpc_reg_operand" "f")))]
2953 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
2954 "
2955 {
2956 rtx temp, op0, op1;
2957 enum rtx_code code = GET_CODE (operands[1]);
2958 if (! rs6000_compare_fp_p)
2959 FAIL;
2960 switch (code)
2961 {
2962 case GE: case EQ: case NE:
2963 op0 = rs6000_compare_op0;
2964 op1 = rs6000_compare_op1;
2965 break;
2966 case GT:
2967 op0 = rs6000_compare_op1;
2968 op1 = rs6000_compare_op0;
2969 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
2970 break;
2971 case LE:
2972 op0 = rs6000_compare_op1;
2973 op1 = rs6000_compare_op0;
2974 break;
2975 case LT:
2976 op0 = rs6000_compare_op0;
2977 op1 = rs6000_compare_op1;
2978 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
2979 break;
2980 default:
2981 FAIL;
2982 }
2983 if (GET_MODE (rs6000_compare_op0) == DFmode)
2984 {
2985 temp = gen_reg_rtx (DFmode);
2986 emit_insn (gen_subdf3 (temp, op0, op1));
2987 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
2988 if (code == EQ)
2989 {
2990 emit_insn (gen_negdf2 (temp, temp));
2991 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
2992 }
2993 if (code == NE)
2994 {
2995 emit_insn (gen_negdf2 (temp, temp));
2996 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0]));
2997 }
2998 }
2999 else
3000 {
3001 temp = gen_reg_rtx (SFmode);
3002 emit_insn (gen_subsf3 (temp, op0, op1));
3003 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
3004 if (code == EQ)
3005 {
3006 emit_insn (gen_negsf2 (temp, temp));
3007 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
3008 }
3009 if (code == NE)
3010 {
3011 emit_insn (gen_negsf2 (temp, temp));
3012 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0]));
3013 }
3014 }
3015 DONE;
3016 }")
3017
3018 (define_insn "fselsfsf4"
3019 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3020 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3021 (const_int 0))
3022 (match_operand:SF 2 "gpc_reg_operand" "f")
3023 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3024 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3025 "fsel %0,%1,%2,%3"
3026 [(set_attr "type" "fp")])
3027
3028 (define_insn "fseldfsf4"
3029 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
3030 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3031 (const_int 0))
3032 (match_operand:SF 2 "gpc_reg_operand" "f")
3033 (match_operand:SF 3 "gpc_reg_operand" "f")))]
3034 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3035 "fsel %0,%1,%2,%3"
3036 [(set_attr "type" "fp")])
3037
3038 (define_insn "negdf2"
3039 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3040 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3041 "TARGET_HARD_FLOAT"
3042 "fneg %0,%1"
3043 [(set_attr "type" "fp")])
3044
3045 (define_insn "absdf2"
3046 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3047 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3048 "TARGET_HARD_FLOAT"
3049 "fabs %0,%1"
3050 [(set_attr "type" "fp")])
3051
3052 (define_insn ""
3053 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3054 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3055 "TARGET_HARD_FLOAT"
3056 "fnabs %0,%1"
3057 [(set_attr "type" "fp")])
3058
3059 (define_insn "adddf3"
3060 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3061 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3062 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3063 "TARGET_HARD_FLOAT"
3064 "{fa|fadd} %0,%1,%2"
3065 [(set_attr "type" "fp")])
3066
3067 (define_insn "subdf3"
3068 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3069 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3070 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3071 "TARGET_HARD_FLOAT"
3072 "{fs|fsub} %0,%1,%2"
3073 [(set_attr "type" "fp")])
3074
3075 (define_insn "muldf3"
3076 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3077 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3078 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3079 "TARGET_HARD_FLOAT"
3080 "{fm|fmul} %0,%1,%2"
3081 [(set_attr "type" "dmul")])
3082
3083 (define_insn "divdf3"
3084 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3085 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
3086 (match_operand:DF 2 "gpc_reg_operand" "f")))]
3087 "TARGET_HARD_FLOAT"
3088 "{fd|fdiv} %0,%1,%2"
3089 [(set_attr "type" "ddiv")])
3090
3091 (define_insn ""
3092 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3093 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3094 (match_operand:DF 2 "gpc_reg_operand" "f"))
3095 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3096 "TARGET_HARD_FLOAT"
3097 "{fma|fmadd} %0,%1,%2,%3"
3098 [(set_attr "type" "dmul")])
3099
3100 (define_insn ""
3101 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3102 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3103 (match_operand:DF 2 "gpc_reg_operand" "f"))
3104 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3105 "TARGET_HARD_FLOAT"
3106 "{fms|fmsub} %0,%1,%2,%3"
3107 [(set_attr "type" "dmul")])
3108
3109 (define_insn ""
3110 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3111 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3112 (match_operand:DF 2 "gpc_reg_operand" "f"))
3113 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3114 "TARGET_HARD_FLOAT"
3115 "{fnma|fnmadd} %0,%1,%2,%3"
3116 [(set_attr "type" "dmul")])
3117
3118 (define_insn ""
3119 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3120 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
3121 (match_operand:DF 2 "gpc_reg_operand" "f"))
3122 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
3123 "TARGET_HARD_FLOAT"
3124 "{fnms|fnmsub} %0,%1,%2,%3"
3125 [(set_attr "type" "dmul")])
3126
3127 (define_insn "sqrtdf2"
3128 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3129 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
3130 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3131 "fsqrt %0,%1"
3132 [(set_attr "type" "dsqrt")])
3133
3134 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3135 ;; fsel instruction and some auxiliary computations. Then we just have a
3136 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3137 ;; combine.
3138
3139 (define_expand "maxdf3"
3140 [(set (match_dup 3)
3141 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
3142 (match_operand:DF 2 "gpc_reg_operand" "")))
3143 (set (match_operand:DF 0 "gpc_reg_operand" "")
3144 (if_then_else:DF (ge (match_dup 3)
3145 (const_int 0))
3146 (match_dup 1)
3147 (match_dup 2)))]
3148 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3149 "
3150 { operands[3] = gen_reg_rtx (DFmode); }")
3151
3152 (define_split
3153 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3154 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
3155 (match_operand:DF 2 "gpc_reg_operand" "")))
3156 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3157 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3158 [(set (match_dup 3)
3159 (minus:DF (match_dup 1) (match_dup 2)))
3160 (set (match_dup 0)
3161 (if_then_else:DF (ge (match_dup 3)
3162 (const_int 0))
3163 (match_dup 1)
3164 (match_dup 2)))]
3165 "")
3166
3167 (define_expand "mindf3"
3168 [(set (match_dup 3)
3169 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
3170 (match_operand:DF 1 "gpc_reg_operand" "")))
3171 (set (match_operand:DF 0 "gpc_reg_operand" "")
3172 (if_then_else:DF (ge (match_dup 3)
3173 (const_int 0))
3174 (match_dup 1)
3175 (match_dup 2)))]
3176 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3177 "
3178 { operands[3] = gen_reg_rtx (DFmode); }")
3179
3180 (define_split
3181 [(set (match_operand:DF 0 "gpc_reg_operand" "")
3182 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
3183 (match_operand:DF 2 "gpc_reg_operand" "")))
3184 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
3185 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3186 [(set (match_dup 3)
3187 (minus:DF (match_dup 2) (match_dup 1)))
3188 (set (match_dup 0)
3189 (if_then_else:DF (ge (match_dup 3)
3190 (const_int 0))
3191 (match_dup 1)
3192 (match_dup 2)))]
3193 "")
3194
3195 (define_expand "movdfcc"
3196 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3197 (if_then_else:DF (match_operand 1 "comparison_operator" "")
3198 (match_operand:DF 2 "gpc_reg_operand" "f")
3199 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3200 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3201 "
3202 {
3203 rtx temp, op0, op1;
3204 enum rtx_code code = GET_CODE (operands[1]);
3205 if (! rs6000_compare_fp_p)
3206 FAIL;
3207 switch (code)
3208 {
3209 case GE: case EQ: case NE:
3210 op0 = rs6000_compare_op0;
3211 op1 = rs6000_compare_op1;
3212 break;
3213 case GT:
3214 op0 = rs6000_compare_op1;
3215 op1 = rs6000_compare_op0;
3216 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3217 break;
3218 case LE:
3219 op0 = rs6000_compare_op1;
3220 op1 = rs6000_compare_op0;
3221 break;
3222 case LT:
3223 op0 = rs6000_compare_op0;
3224 op1 = rs6000_compare_op1;
3225 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
3226 break;
3227 default:
3228 FAIL;
3229 }
3230 if (GET_MODE (rs6000_compare_op0) == DFmode)
3231 {
3232 temp = gen_reg_rtx (DFmode);
3233 emit_insn (gen_subdf3 (temp, op0, op1));
3234 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
3235 if (code == EQ)
3236 {
3237 emit_insn (gen_negdf2 (temp, temp));
3238 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
3239 }
3240 if (code == NE)
3241 {
3242 emit_insn (gen_negdf2 (temp, temp));
3243 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0]));
3244 }
3245 }
3246 else
3247 {
3248 temp = gen_reg_rtx (SFmode);
3249 emit_insn (gen_subsf3 (temp, op0, op1));
3250 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
3251 if (code == EQ)
3252 {
3253 emit_insn (gen_negsf2 (temp, temp));
3254 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
3255 }
3256 if (code == NE)
3257 {
3258 emit_insn (gen_negsf2 (temp, temp));
3259 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0]));
3260 }
3261 }
3262 DONE;
3263 }")
3264
3265 (define_insn "fseldfdf4"
3266 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3267 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
3268 (const_int 0))
3269 (match_operand:DF 2 "gpc_reg_operand" "f")
3270 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3271 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3272 "fsel %0,%1,%2,%3"
3273 [(set_attr "type" "fp")])
3274
3275 (define_insn "fselsfdf4"
3276 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3277 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
3278 (const_int 0))
3279 (match_operand:DF 2 "gpc_reg_operand" "f")
3280 (match_operand:DF 3 "gpc_reg_operand" "f")))]
3281 "TARGET_PPC_GFXOPT"
3282 "fsel %0,%1,%2,%3"
3283 [(set_attr "type" "fp")])
3284 \f
3285 ;; Conversions to and from floating-point.
3286 (define_expand "floatsidf2"
3287 [(set (match_dup 2)
3288 (plus:DI (zero_extend:DI
3289 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3290 (match_dup 3)))
3291 (match_dup 4)))
3292 (set (match_operand:DF 0 "gpc_reg_operand" "")
3293 (minus:DF (subreg:DF (match_dup 2) 0)
3294 (match_dup 5)))]
3295 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3296 "
3297 {
3298 operands[2] = gen_reg_rtx (DImode);
3299 operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
3300 operands[4] = rs6000_immed_double_const (0, 0x43300000, DImode);
3301 operands[5] = force_reg (DFmode, rs6000_immed_double_const (0x43300000,
3302 0x80000000,
3303 DFmode));
3304 }")
3305
3306 (define_expand "floatunssidf2"
3307 [(set (match_dup 2)
3308 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3309 (match_dup 3)))
3310 (set (match_operand:DF 0 "gpc_reg_operand" "")
3311 (minus:DF (subreg:DF (match_dup 2) 0)
3312 (match_dup 4)))]
3313 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3314 "
3315 {
3316 operands[2] = gen_reg_rtx (DImode);
3317 operands[3] = rs6000_immed_double_const (0, 0x43300000, DImode);
3318 operands[4] = force_reg (DFmode, rs6000_immed_double_const (0x43300000, 0, DFmode));
3319 }")
3320
3321 ;; For the above two cases, we always split.
3322 (define_split
3323 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3324 (plus:DI (zero_extend:DI
3325 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3326 (match_operand:SI 2 "logical_operand" "")))
3327 (match_operand:DI 3 "low_32_bit_operand" "")))]
3328 "reload_completed"
3329 [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
3330 (set (match_dup 4) (match_dup 5))]
3331 "
3332 { operands[4] = operand_subword (operands[0], 0, 0, DImode);
3333 operands[5] = operand_subword (operands[3], 0, 0, DImode);
3334 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3335 }")
3336
3337 (define_insn ""
3338 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3339 (plus:DI (zero_extend:DI
3340 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
3341 (match_operand:SI 2 "logical_operand" "rKJ")))
3342 (match_operand:DI 3 "low_32_bit_operand" "n")))]
3343 ""
3344 "#"
3345 [(set_attr "length" "8")])
3346
3347 (define_split
3348 [(set (match_operand:DI 0 "gpc_reg_operand" "=")
3349 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3350 (match_operand:DI 2 "low_32_bit_operand" "")))]
3351 "reload_completed"
3352 [(set (match_dup 3) (match_dup 4))
3353 (set (match_dup 5) (match_dup 1))]
3354 "
3355 { operands[3] = operand_subword (operands[0], 0, 0, DImode);
3356 operands[4] = operand_subword (operands[2], 0, 0, DImode);
3357 operands[5] = operand_subword (operands[0], 1, 0, DImode);
3358
3359 if (rtx_equal_p (operands[1], operands[5]))
3360 {
3361 emit_move_insn (operands[3], operands[4]);
3362 DONE;
3363 }
3364
3365 if (rtx_equal_p (operands[1], operands[3]))
3366 {
3367 rtx temp;
3368
3369 temp = operands[3]; operands[3] = operands[5]; operands[5] = temp;
3370 temp = operands[4]; operands[4] = operands[1]; operands[1] = temp;
3371 }
3372 }")
3373
3374 (define_insn ""
3375 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3376 (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3377 (match_operand:DI 2 "low_32_bit_operand" "n")))]
3378 ""
3379 "#"
3380 [(set_attr "length" "8")])
3381
3382 (define_expand "fix_truncdfsi2"
3383 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3384 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
3385 "TARGET_HARD_FLOAT"
3386 "
3387 {
3388 if (TARGET_POWER2 || TARGET_POWERPC)
3389 {
3390 rtx stack_slot = assign_stack_temp (DImode, 8, 0),
3391 temp = gen_reg_rtx (DImode);
3392
3393 emit_insn (gen_fpcvtsi (temp, operands[1]));
3394 emit_move_insn (stack_slot, temp);
3395 emit_move_insn (operands[0],
3396 operand_subword (stack_slot, 1, 0, DImode));
3397 DONE;
3398 }
3399 else
3400 {
3401 emit_insn (gen_trunc_call (operands[0], operands[1],
3402 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
3403 DONE;
3404 }
3405 }")
3406
3407 (define_insn "fpcvtsi"
3408 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3409 (sign_extend:DI
3410 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
3411 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3412 "{fcirz|fctiwz} %0,%1"
3413 [(set_attr "type" "fp")])
3414
3415 (define_expand "fixuns_truncdfsi2"
3416 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3417 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
3418 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
3419 "
3420 {
3421 emit_insn (gen_trunc_call (operands[0], operands[1],
3422 gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
3423 DONE;
3424 }")
3425
3426 (define_expand "trunc_call"
3427 [(parallel [(set (match_operand:SI 0 "" "")
3428 (fix:SI (match_operand:DF 1 "" "")))
3429 (use (match_operand:SI 2 "" ""))])]
3430 "TARGET_HARD_FLOAT"
3431 "
3432 {
3433 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
3434 rtx first = XVECEXP (insns, 0, 0);
3435 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
3436
3437 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
3438 REG_NOTES (first));
3439 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
3440
3441 emit_insn (insns);
3442 DONE;
3443 }")
3444
3445 (define_expand "trunc_call_rtl"
3446 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
3447 (use (reg:DF 33))
3448 (parallel [(set (reg:SI 3)
3449 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
3450 (clobber (scratch:SI))])
3451 (set (match_operand:SI 0 "gpc_reg_operand" "")
3452 (reg:SI 3))]
3453 "TARGET_HARD_FLOAT"
3454 "
3455 {
3456 rs6000_trunc_used = 1;
3457 }")
3458
3459 (define_insn "floatdidf2"
3460 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
3461 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
3462 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3463 "fcfid %0,%1"
3464 [(set_attr "type" "fp")])
3465
3466 (define_insn "fix_truncdfdi2"
3467 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
3468 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
3469 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3470 "fctidz %0,%1"
3471 [(set_attr "type" "fp")])
3472 \f
3473 ;; Define the DImode operations that can be done in a small number
3474 ;; of instructions.
3475 (define_expand "adddi3"
3476 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3477 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
3478 (match_operand:DI 2 "reg_or_short_operand" "")))]
3479 ""
3480 "
3481 {
3482 if (! TARGET_POWER && ! TARGET_POWERPC64
3483 && short_cint_operand (operands[2], DImode))
3484 FAIL;
3485 }")
3486
3487 (define_insn ""
3488 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3489 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
3490 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
3491 "TARGET_POWER && ! TARGET_POWERPC64"
3492 "@
3493 {a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2
3494 {ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1"
3495 [(set_attr "length" "8")])
3496
3497 (define_insn ""
3498 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3499 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
3500 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3501 "! TARGET_POWER && ! TARGET_POWERPC64"
3502 "addc %L0,%L1,%L2\;adde %0,%1,%2"
3503 [(set_attr "length" "8")])
3504
3505 (define_expand "subdi3"
3506 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3507 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
3508 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
3509 ""
3510 "
3511 {
3512 if (! TARGET_POWER && ! TARGET_POWERPC64
3513 && short_cint_operand (operands[1], DImode))
3514 FAIL;
3515 }")
3516
3517 (define_insn ""
3518 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3519 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
3520 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
3521 "TARGET_POWER && ! TARGET_POWERPC64"
3522 "@
3523 {sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1
3524 {sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2"
3525 [(set_attr "length" "8")])
3526
3527 (define_insn ""
3528 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3529 (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3530 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3531 "! TARGET_POWER && ! TARGET_POWERPC64"
3532 "subfc %L0,%L2,%L1\;subfe %0,%2,%1"
3533 [(set_attr "length" "8")])
3534
3535 (define_expand "negdi2"
3536 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3537 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
3538 ""
3539 "")
3540
3541 (define_insn ""
3542 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3543 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
3544 "! TARGET_POWERPC64"
3545 "{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1"
3546 [(set_attr "length" "8")])
3547
3548 (define_expand "mulsidi3"
3549 [(set (match_operand:DI 0 "gpc_reg_operand" "")
3550 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
3551 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
3552 ""
3553 "
3554 {
3555 if (! TARGET_POWER && ! TARGET_POWERPC)
3556 {
3557 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
3558 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
3559 emit_insn (gen_mull_call ());
3560 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
3561 gen_rtx (REG, SImode, 3));
3562 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
3563 gen_rtx (REG, SImode, 4));
3564 DONE;
3565 }
3566 else if (TARGET_POWER)
3567 {
3568 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
3569 DONE;
3570 }
3571 }")
3572
3573 (define_insn "mulsidi3_mq"
3574 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3575 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
3576 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
3577 (clobber (match_scratch:SI 3 "=q"))]
3578 "TARGET_POWER"
3579 "mul %0,%1,%2\;mfmq %L0"
3580 [(set_attr "type" "imul")
3581 (set_attr "length" "8")])
3582
3583 (define_insn ""
3584 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
3585 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
3586 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
3587 "TARGET_POWERPC && ! TARGET_POWERPC64"
3588 "mulhw %0,%1,%2\;mullw %L0,%1,%2"
3589 [(set_attr "type" "imul")
3590 (set_attr "length" "8")])
3591
3592 (define_expand "smulsi3_highpart"
3593 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3594 (truncate:SI
3595 (lshiftrt:DI (mult:DI (sign_extend:DI
3596 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3597 (sign_extend:DI
3598 (match_operand:SI 2 "gpc_reg_operand" "r")))
3599 (const_int 32))))]
3600 ""
3601 "
3602 {
3603 if (! TARGET_POWER && ! TARGET_POWERPC)
3604 {
3605 emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
3606 emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
3607 emit_insn (gen_mulh_call ());
3608 emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
3609 DONE;
3610 }
3611 else if (TARGET_POWER)
3612 {
3613 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
3614 DONE;
3615 }
3616 }")
3617
3618 (define_insn "smulsi3_highpart_mq"
3619 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3620 (truncate:SI
3621 (lshiftrt:DI (mult:DI (sign_extend:DI
3622 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3623 (sign_extend:DI
3624 (match_operand:SI 2 "gpc_reg_operand" "r")))
3625 (const_int 32))))
3626 (clobber (match_scratch:SI 3 "=q"))]
3627 "TARGET_POWER"
3628 "mul %0,%1,%2"
3629 [(set_attr "type" "imul")])
3630
3631 (define_insn ""
3632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3633 (truncate:SI
3634 (lshiftrt:DI (mult:DI (sign_extend:DI
3635 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3636 (sign_extend:DI
3637 (match_operand:SI 2 "gpc_reg_operand" "r")))
3638 (const_int 32))))]
3639 "TARGET_POWERPC"
3640 "mulhw %0,%1,%2"
3641 [(set_attr "type" "imul")])
3642
3643 (define_insn "umulsi3_highpart"
3644 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3645 (truncate:SI
3646 (lshiftrt:DI (mult:DI (zero_extend:DI
3647 (match_operand:SI 1 "gpc_reg_operand" "%r"))
3648 (zero_extend:DI
3649 (match_operand:SI 2 "gpc_reg_operand" "r")))
3650 (const_int 32))))]
3651 "TARGET_POWERPC"
3652 "mulhwu %0,%1,%2"
3653 [(set_attr "type" "imul")])
3654
3655 ;; If operands 0 and 2 are in the same register, we have a problem. But
3656 ;; operands 0 and 1 (the usual case) can be in the same register. That's
3657 ;; why we have the strange constraints below.
3658 (define_insn "ashldi3"
3659 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
3660 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
3661 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
3662 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
3663 "TARGET_POWER"
3664 "@
3665 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
3666 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
3667 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
3668 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
3669 [(set_attr "length" "8")])
3670
3671 (define_insn "lshrdi3"
3672 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
3673 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
3674 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
3675 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
3676 "TARGET_POWER"
3677 "@
3678 {cal %0,0(0)|li %0,0}\;{s%A2i|s%A2wi} %L0,%1,%h2
3679 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
3680 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
3681 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
3682 [(set_attr "length" "8")])
3683
3684 ;; Shift by a variable amount is too complex to be worth open-coding. We
3685 ;; just handle shifts by constants.
3686
3687 (define_expand "ashrdi3"
3688 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "")
3689 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
3690 (match_operand:SI 2 "general_operand" "")))
3691 (clobber (match_scratch:SI 3 ""))])]
3692 "TARGET_POWER"
3693 "
3694 { if (GET_CODE (operands[2]) != CONST_INT)
3695 FAIL;
3696 }")
3697
3698 (define_insn ""
3699 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3700 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
3701 (match_operand:SI 2 "const_int_operand" "M,i")))
3702 (clobber (match_scratch:SI 3 "=X,q"))]
3703 "TARGET_POWER"
3704 "@
3705 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
3706 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
3707 [(set_attr "length" "8")])
3708 \f
3709 ;; PowerPC64 DImode operations.
3710
3711 (define_insn "ffsdi2"
3712 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
3713 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
3714 "TARGET_POWERPC64"
3715 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
3716 [(set_attr "length" "16")])
3717
3718 (define_insn "muldi3"
3719 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3720 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
3721 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3722 "TARGET_POWERPC64"
3723 "mulld %0,%1,%2"
3724 [(set_attr "type" "imul")])
3725
3726 (define_insn "smuldi3_highpart"
3727 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3728 (truncate:DI
3729 (lshiftrt:TI (mult:TI (sign_extend:TI
3730 (match_operand:DI 1 "gpc_reg_operand" "%r"))
3731 (sign_extend:TI
3732 (match_operand:DI 2 "gpc_reg_operand" "r")))
3733 (const_int 64))))]
3734 "TARGET_POWERPC64"
3735 "mulhd %0,%1,%2"
3736 [(set_attr "type" "imul")])
3737
3738 (define_insn "umuldi3_highpart"
3739 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3740 (truncate:DI
3741 (lshiftrt:TI (mult:TI (zero_extend:TI
3742 (match_operand:DI 1 "gpc_reg_operand" "%r"))
3743 (zero_extend:TI
3744 (match_operand:DI 2 "gpc_reg_operand" "r")))
3745 (const_int 64))))]
3746 "TARGET_POWERPC64"
3747 "mulhdu %0,%1,%2"
3748 [(set_attr "type" "imul")])
3749
3750 (define_insn "divdi3"
3751 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3752 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3753 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3754 "TARGET_POWERPC64"
3755 "divd %0,%1,%2"
3756 [(set_attr "type" "idiv")])
3757
3758 (define_insn "udivdi3"
3759 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3760 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3761 (match_operand:DI 2 "gpc_reg_operand" "r")))]
3762 "TARGET_POWERPC64"
3763 "divdu %0,%1,%2"
3764 [(set_attr "type" "idiv")])
3765
3766 (define_insn "rotldi3"
3767 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3768 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3769 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
3770 "TARGET_POWERPC64"
3771 "rld%I2cl %0,%1,%h2,0")
3772
3773 (define_insn ""
3774 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3775 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3776 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
3777 (const_int 0)))
3778 (clobber (match_scratch:DI 3 "=r"))]
3779 "TARGET_POWERPC64"
3780 "rld%I2cl. %3,%1,%h2,0"
3781 [(set_attr "type" "delayed_compare")])
3782
3783 (define_insn ""
3784 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3785 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3786 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
3787 (const_int 0)))
3788 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3789 (rotate:DI (match_dup 1) (match_dup 2)))]
3790 "TARGET_POWERPC64"
3791 "rld%I2cl. %0,%1,%h2,0"
3792 [(set_attr "type" "delayed_compare")])
3793 \f
3794 ;; Now define ways of moving data around.
3795 ;;
3796 ;; For SI, we special-case integers that can't be loaded in one insn. We
3797 ;; do the load 16-bits at a time. We could do this by loading from memory,
3798 ;; and this is even supposed to be faster, but it is simpler not to get
3799 ;; integers in the TOC.
3800 (define_expand "movsi"
3801 [(set (match_operand:SI 0 "general_operand" "")
3802 (match_operand:SI 1 "any_operand" ""))]
3803 ""
3804 "
3805 {
3806 if (GET_CODE (operands[0]) != REG)
3807 operands[1] = force_reg (SImode, operands[1]);
3808
3809 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT
3810 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
3811 {
3812 /* If we are to limit the number of things we put in the TOC and
3813 this is a symbol plus a constant we can add in one insn,
3814 just put the sumbol in the TOC and add the constant. Don't do
3815 this if reload is in progress. */
3816 if (GET_CODE (operands[1]) == CONST
3817 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3818 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3819 && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
3820 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3821 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3822 && ! side_effects_p (operands[0]))
3823 {
3824 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
3825 rtx other = XEXP (XEXP (operands[1], 0), 1);
3826
3827 emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
3828 DONE;
3829 }
3830
3831 operands[1] = force_const_mem (SImode, operands[1]);
3832 if (! memory_address_p (SImode, XEXP (operands[1], 0))
3833 && ! reload_in_progress)
3834 operands[1] = change_address (operands[1], SImode,
3835 XEXP (operands[1], 0));
3836 }
3837
3838 if (GET_CODE (operands[1]) == CONST_INT
3839 && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
3840 && (INTVAL (operands[1]) & 0xffff) != 0)
3841 {
3842 emit_move_insn (operands[0],
3843 gen_rtx (CONST_INT, VOIDmode,
3844 INTVAL (operands[1]) & 0xffff0000));
3845 emit_insn (gen_iorsi3 (operands[0], operands[0],
3846 gen_rtx (CONST_INT, VOIDmode,
3847 INTVAL (operands[1]) & 0xffff)));
3848 DONE;
3849 }
3850 }")
3851
3852 (define_insn ""
3853 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*q,*c*l,*h")
3854 (match_operand:SI 1 "input_operand" "r,m,r,I,J,R,*h,r,r,0"))]
3855 "gpc_reg_operand (operands[0], SImode)
3856 || gpc_reg_operand (operands[1], SImode)"
3857 "@
3858 mr %0,%1
3859 {l%U1%X1|lwz%U1%X1} %0,%1
3860 {st%U0%X0|stw%U0%X0} %1,%0
3861 {lil|li} %0,%1
3862 {liu|lis} %0,%u1
3863 {cal|la} %0,%1(%*)
3864 mf%1 %0
3865 mt%0 %1
3866 mt%0 %1
3867 cror 0,0,0"
3868 [(set_attr "type" "*,load,*,*,*,*,*,*,mtjmpr,*")])
3869
3870 ;; Split a load of a large constant into the appropriate two-insn
3871 ;; sequence.
3872
3873 (define_split
3874 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3875 (match_operand:SI 1 "const_int_operand" ""))]
3876 "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
3877 && (INTVAL (operands[1]) & 0xffff) != 0"
3878 [(set (match_dup 0)
3879 (match_dup 2))
3880 (set (match_dup 0)
3881 (ior:SI (match_dup 0)
3882 (match_dup 3)))]
3883 "
3884 {
3885 operands[2] = gen_rtx (CONST_INT, VOIDmode,
3886 INTVAL (operands[1]) & 0xffff0000);
3887 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
3888 }")
3889
3890 (define_insn ""
3891 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
3892 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
3893 (const_int 0)))
3894 (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
3895 ""
3896 "mr. %0,%1"
3897 [(set_attr "type" "compare")])
3898 \f
3899 (define_expand "movhi"
3900 [(set (match_operand:HI 0 "general_operand" "")
3901 (match_operand:HI 1 "any_operand" ""))]
3902 ""
3903 "
3904 {
3905 if (GET_CODE (operands[0]) != REG)
3906 operands[1] = force_reg (HImode, operands[1]);
3907
3908 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
3909 {
3910 operands[1] = force_const_mem (HImode, operands[1]);
3911 if (! memory_address_p (HImode, XEXP (operands[1], 0))
3912 && ! reload_in_progress)
3913 operands[1] = change_address (operands[1], HImode,
3914 XEXP (operands[1], 0));
3915 }
3916 }")
3917
3918 (define_insn ""
3919 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
3920 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
3921 "gpc_reg_operand (operands[0], HImode)
3922 || gpc_reg_operand (operands[1], HImode)"
3923 "@
3924 mr %0,%1
3925 lhz%U1%X1 %0,%1
3926 sth%U0%X0 %1,%0
3927 {lil|li} %0,%w1
3928 mf%1 %0
3929 mt%0 %1
3930 mt%0 %1
3931 cror 0,0,0"
3932 [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
3933
3934 (define_expand "movqi"
3935 [(set (match_operand:QI 0 "general_operand" "")
3936 (match_operand:QI 1 "any_operand" ""))]
3937 ""
3938 "
3939 {
3940 if (GET_CODE (operands[0]) != REG)
3941 operands[1] = force_reg (QImode, operands[1]);
3942
3943 if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
3944 {
3945 operands[1] = force_const_mem (QImode, operands[1]);
3946 if (! memory_address_p (QImode, XEXP (operands[1], 0))
3947 && ! reload_in_progress)
3948 operands[1] = change_address (operands[1], QImode,
3949 XEXP (operands[1], 0));
3950 }
3951 }")
3952
3953 (define_insn ""
3954 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
3955 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
3956 "gpc_reg_operand (operands[0], QImode)
3957 || gpc_reg_operand (operands[1], QImode)"
3958 "@
3959 mr %0,%1
3960 lbz%U1%X1 %0,%1
3961 stb%U0%X0 %1,%0
3962 {lil|li} %0,%1
3963 mf%1 %0
3964 mt%0 %1
3965 mt%0 %1
3966 cror 0,0,0"
3967 [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
3968 \f
3969 ;; Here is how to move condition codes around. When we store CC data in
3970 ;; an integer register or memory, we store just the high-order 4 bits.
3971 ;; This lets us not shift in the most common case of CR0.
3972 (define_expand "movcc"
3973 [(set (match_operand:CC 0 "nonimmediate_operand" "")
3974 (match_operand:CC 1 "nonimmediate_operand" ""))]
3975 ""
3976 "")
3977
3978 (define_insn ""
3979 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
3980 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
3981 "register_operand (operands[0], CCmode)
3982 || register_operand (operands[1], CCmode)"
3983 "@
3984 mcrf %0,%1
3985 mtcrf 128,%1
3986 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
3987 mfcr %0
3988 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
3989 mr %0,%1
3990 {l%U1%X1|lwz%U1%X1} %0,%1
3991 {st%U0%U1|stw%U0%U1} %1,%0"
3992 [(set_attr "type" "*,*,*,compare,*,*,load,*")
3993 (set_attr "length" "*,*,12,*,8,*,*,*")])
3994 \f
3995 ;; For floating-point, we normally deal with the floating-point registers
3996 ;; unless -msoft-float is used. The sole exception is that parameter passing
3997 ;; can produce floating-point values in fixed-point registers. Unless the
3998 ;; value is a simple constant or already in memory, we deal with this by
3999 ;; allocating memory and copying the value explicitly via that memory location.
4000 (define_expand "movsf"
4001 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4002 (match_operand:SF 1 "any_operand" ""))]
4003 ""
4004 "
4005 {
4006 /* If we are called from reload, we might be getting a SUBREG of a hard
4007 reg. So expand it. */
4008 if (GET_CODE (operands[0]) == SUBREG
4009 && GET_CODE (SUBREG_REG (operands[0])) == REG
4010 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
4011 operands[0] = alter_subreg (operands[0]);
4012 if (GET_CODE (operands[1]) == SUBREG
4013 && GET_CODE (SUBREG_REG (operands[1])) == REG
4014 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
4015 operands[1] = alter_subreg (operands[1]);
4016
4017 if (TARGET_SOFT_FLOAT && GET_CODE (operands[0]) == MEM)
4018 operands[1] = force_reg (SFmode, operands[1]);
4019
4020 else if (TARGET_HARD_FLOAT)
4021 {
4022 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
4023 {
4024 /* If this is a store to memory or another integer register do the
4025 move directly. Otherwise store to a temporary stack slot and
4026 load from there into a floating point register. */
4027
4028 if (GET_CODE (operands[0]) == MEM
4029 || (GET_CODE (operands[0]) == REG
4030 && (REGNO (operands[0]) < 32
4031 || (reload_in_progress
4032 && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
4033 {
4034 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
4035 operand_subword (operands[1], 0, 0, SFmode));
4036 DONE;
4037 }
4038 else
4039 {
4040 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
4041
4042 emit_move_insn (stack_slot, operands[1]);
4043 emit_move_insn (operands[0], stack_slot);
4044 DONE;
4045 }
4046 }
4047
4048 if (GET_CODE (operands[0]) == MEM)
4049 {
4050 /* If operands[1] is a register, it may have double-precision data
4051 in it, so truncate it to single precision. We need not do
4052 this for POWERPC. */
4053 if (! TARGET_POWERPC && GET_CODE (operands[1]) == REG)
4054 {
4055 rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
4056 emit_insn (gen_truncdfsf2 (newreg,
4057 gen_rtx (SUBREG, DFmode, operands[1], 0)));
4058 operands[1] = newreg;
4059 }
4060
4061 operands[1] = force_reg (SFmode, operands[1]);
4062 }
4063
4064 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
4065 {
4066 if (GET_CODE (operands[1]) == MEM
4067 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
4068 || GET_CODE (operands[1]) == CONST_DOUBLE
4069 #endif
4070 || (GET_CODE (operands[1]) == REG
4071 && (REGNO (operands[1]) < 32
4072 || (reload_in_progress
4073 && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
4074 {
4075 emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
4076 operand_subword (operands[1], 0, 0, SFmode));
4077 DONE;
4078 }
4079 else
4080 {
4081 rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
4082
4083 emit_move_insn (stack_slot, operands[1]);
4084 emit_move_insn (operands[0], stack_slot);
4085 DONE;
4086 }
4087 }
4088 }
4089
4090 if (CONSTANT_P (operands[1]))
4091 {
4092 operands[1] = force_const_mem (SFmode, operands[1]);
4093 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
4094 && ! reload_in_progress)
4095 operands[1] = change_address (operands[1], SFmode,
4096 XEXP (operands[1], 0));
4097 }
4098 }")
4099
4100 (define_split
4101 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4102 (match_operand:SF 1 "easy_fp_constant" ""))]
4103 "reload_completed && REGNO (operands[0]) <= 31"
4104 [(set (match_dup 2) (match_dup 3))]
4105 "
4106 { operands[2] = operand_subword (operands[0], 0, 0, SFmode);
4107 operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
4108
4109 (define_insn ""
4110 [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
4111 (match_operand:SF 1 "input_operand" "f,m,f"))]
4112 "(gpc_reg_operand (operands[0], SFmode)
4113 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
4114 "@
4115 fmr %0,%1
4116 lfs%U1%X1 %0,%1
4117 stfs%U0%X0 %1,%0"
4118 [(set_attr "type" "fp,fpload,*")])
4119
4120 (define_insn ""
4121 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
4122 (match_operand:SF 1 "input_operand" "r,m,r,I,J,R"))]
4123 "(gpc_reg_operand (operands[0], SFmode)
4124 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
4125 "@
4126 mr %0,%1
4127 {l%U1%X1|lwz%U1%X1} %0,%1
4128 {st%U0%X0|stw%U0%X0} %1,%0
4129 {lil|li} %0,%1
4130 {liu|lis} %0,%u1
4131 {cal|la} %0,%1(%*)"
4132 [(set_attr "type" "*,load,*,*,*,*")])
4133
4134 \f
4135 (define_expand "movdf"
4136 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4137 (match_operand:DF 1 "any_operand" ""))]
4138 ""
4139 "
4140 {
4141 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
4142 {
4143 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4144 operand_subword_force (operands[1], 1, DFmode));
4145 emit_move_insn (operand_subword (operands[0], 0, 1, DFmode),
4146 operand_subword_force (operands[1], 0, DFmode));
4147 DONE;
4148 }
4149
4150 if (GET_CODE (operands[0]) != REG)
4151 operands[1] = force_reg (DFmode, operands[1]);
4152
4153 if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
4154 {
4155 operands[1] = force_const_mem (DFmode, operands[1]);
4156 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
4157 && ! reload_in_progress)
4158 operands[1] = change_address (operands[1], DFmode,
4159 XEXP (operands[1], 0));
4160 }
4161 }")
4162
4163 (define_split
4164 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4165 (match_operand:DF 1 "easy_fp_constant" ""))]
4166 "reload_completed && REGNO (operands[0]) <= 31"
4167 [(set (match_dup 2) (match_dup 3))
4168 (set (match_dup 4) (match_dup 5))]
4169 "
4170 { operands[2] = operand_subword (operands[0], 0, 0, DFmode);
4171 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
4172 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
4173 operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
4174
4175 ;; Don't have reload use general registers to load a constant. First,
4176 ;; it might not work if the output operand has is the equivalent of
4177 ;; a non-offsettable memref, but also it is less efficient than loading
4178 ;; the constant into an FP register, since it will probably be used there.
4179 ;; The "??" is a kludge until we can figure out a more reasonable way
4180 ;; of handling these non-offsettable values.
4181 (define_insn ""
4182 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
4183 (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
4184 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
4185 && (register_operand (operands[0], DFmode)
4186 || register_operand (operands[1], DFmode))"
4187 "*
4188 {
4189 switch (which_alternative)
4190 {
4191 case 0:
4192 /* We normally copy the low-numbered register first. However, if
4193 the first register operand 0 is the same as the second register of
4194 operand 1, we must copy in the opposite order. */
4195 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
4196 return \"mr %L0,%L1\;mr %0,%1\";
4197 else
4198 return \"mr %0,%1\;mr %L0,%L1\";
4199 case 1:
4200 /* If the low-address word is used in the address, we must load it
4201 last. Otherwise, load it first. Note that we cannot have
4202 auto-increment in that case since the address register is known to be
4203 dead. */
4204 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4205 operands [1], 0))
4206 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
4207 else
4208 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
4209 case 2:
4210 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
4211 case 3:
4212 return \"#\";
4213 case 4:
4214 return \"fmr %0,%1\";
4215 case 5:
4216 return \"lfd%U1%X1 %0,%1\";
4217 case 6:
4218 return \"stfd%U0%X0 %1,%0\";
4219 }
4220 }"
4221 [(set_attr "type" "*,load,*,*,fp,fpload,*")
4222 (set_attr "length" "8,8,8,8,*,*,*")])
4223
4224 (define_insn ""
4225 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
4226 (match_operand:DF 1 "input_operand" "r,o,r,G"))]
4227 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
4228 && (register_operand (operands[0], DFmode)
4229 || register_operand (operands[1], DFmode))"
4230 "*
4231 {
4232 switch (which_alternative)
4233 {
4234 case 0:
4235 /* We normally copy the low-numbered register first. However, if
4236 the first register operand 0 is the same as the second register of
4237 operand 1, we must copy in the opposite order. */
4238 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
4239 return \"mr %L0,%L1\;mr %0,%1\";
4240 else
4241 return \"mr %0,%1\;mr %L0,%L1\";
4242 case 1:
4243 /* If the low-address word is used in the address, we must load it
4244 last. Otherwise, load it first. Note that we cannot have
4245 auto-increment in that case since the address register is known to be
4246 dead. */
4247 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4248 operands [1], 0))
4249 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
4250 else
4251 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
4252 case 2:
4253 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
4254 case 3:
4255 return \"#\";
4256 }
4257 }"
4258 [(set_attr "type" "*,load,*,*")
4259 (set_attr "length" "8,8,8,8")])
4260
4261 (define_insn ""
4262 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
4263 (match_operand:DF 1 "input_operand" "r,o,r,G,f,m,f"))]
4264 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
4265 && (register_operand (operands[0], DFmode)
4266 || register_operand (operands[1], DFmode))"
4267 "@
4268 mr %0,%1
4269 ld%U1%X1 %0,%1
4270 sd%U0%X0 %1,%0
4271 #
4272 fmr %0,%1
4273 lfd%U1%X1 %0,%1
4274 stfd%U0%X0 %1,%0"
4275 [(set_attr "type" "*,load,*,*,fp,fpload,*")])
4276
4277 (define_insn ""
4278 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,o,r")
4279 (match_operand:DF 1 "input_operand" "r,o,r,G"))]
4280 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
4281 && (register_operand (operands[0], DFmode)
4282 || register_operand (operands[1], DFmode))"
4283 "@
4284 mr %0,%1
4285 ld%U1%X1 %0,%1
4286 sd%U0%X0 %1,%0
4287 #"
4288 [(set_attr "type" "*,load,*,*")])
4289 \f
4290 ;; Next come the multi-word integer load and store and the load and store
4291 ;; multiple insns.
4292 (define_expand "movdi"
4293 [(set (match_operand:DI 0 "general_operand" "")
4294 (match_operand:DI 1 "general_operand" ""))]
4295 ""
4296 "
4297 {
4298 if (GET_CODE (operands[1]) == CONST_DOUBLE
4299 || GET_CODE (operands[1]) == CONST_INT)
4300 {
4301 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
4302 operand_subword (operands[1], 0, 0, DImode));
4303 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
4304 operand_subword (operands[1], 1, 0, DImode));
4305 DONE;
4306 }
4307
4308 if (GET_CODE (operands[0]) == MEM)
4309 operands[1] = force_reg (DImode, operands[1]);
4310
4311 /* Stores between FPR and any non-FPR registers must go through a
4312 temporary stack slot. */
4313
4314 if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
4315 && ((FP_REGNO_P (REGNO (operands[0]))
4316 && ! FP_REGNO_P (REGNO (operands[1])))
4317 || (FP_REGNO_P (REGNO (operands[1]))
4318 && ! FP_REGNO_P (REGNO (operands[0])))))
4319 {
4320 rtx stack_slot = assign_stack_temp (DImode, 8, 0);
4321
4322 emit_move_insn (stack_slot, operands[1]);
4323 emit_move_insn (operands[0], stack_slot);
4324 DONE;
4325 }
4326 }")
4327
4328 (define_insn ""
4329 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m")
4330 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f"))]
4331 "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
4332 || gpc_reg_operand (operands[1], DImode))"
4333 "*
4334 {
4335 switch (which_alternative)
4336 {
4337 case 0:
4338 /* We normally copy the low-numbered register first. However, if
4339 the first register operand 0 is the same as the second register of
4340 operand 1, we must copy in the opposite order. */
4341 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
4342 return \"mr %L0,%L1\;mr %0,%1\";
4343 else
4344 return \"mr %0,%1\;mr %L0,%L1\";
4345 case 1:
4346 /* If the low-address word is used in the address, we must load it
4347 last. Otherwise, load it first. Note that we cannot have
4348 auto-increment in that case since the address register is known to be
4349 dead. */
4350 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4351 operands [1], 0))
4352 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
4353 else
4354 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
4355 case 2:
4356 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
4357 case 3:
4358 return \"fmr %0,%1\";
4359 case 4:
4360 return \"lfd%U1%X1 %0,%1\";
4361 case 5:
4362 return \"stfd%U0%X0 %1,%0\";
4363 }
4364 }"
4365 [(set_attr "type" "*,load,*,fp,fpload,*")
4366 (set_attr "length" "8,8,8,*,*,*")])
4367
4368 (define_insn ""
4369 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,f,f,m,r,*h")
4370 (match_operand:DI 1 "input_operand" "r,m,r,I,J,R,f,m,f,*h,r"))]
4371 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode)
4372 || gpc_reg_operand (operands[1], DImode))"
4373 "@
4374 mr %0,%1
4375 ld%U1%X1 %0,%1
4376 sd%U0%X0 %1,%0
4377 li %0,%1
4378 lis %0,%u1
4379 {cal|la} %0,%1(%*)
4380 fmr %0,%1
4381 lfd%U1%X1 %0,%1
4382 stfd%U0%X0 %1,%0
4383 mf%1 %0
4384 mt%0 %1"
4385 [(set_attr "type" "*,load,*,*,*,*,fp,fpload,*,*,mtjmpr")])
4386 \f
4387 ;; TImode is similar, except that we usually want to compute the address into
4388 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
4389 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
4390 (define_expand "movti"
4391 [(parallel [(set (match_operand:TI 0 "general_operand" "")
4392 (match_operand:TI 1 "general_operand" ""))
4393 (clobber (scratch:SI))])]
4394 "TARGET_MULTIPLE || TARGET_POWERPC64"
4395 "
4396 {
4397 if (GET_CODE (operands[0]) == MEM)
4398 operands[1] = force_reg (TImode, operands[1]);
4399
4400 if (GET_CODE (operands[0]) == MEM
4401 && GET_CODE (XEXP (operands[0], 0)) != REG
4402 && ! reload_in_progress)
4403 operands[0] = change_address (operands[0], TImode,
4404 copy_addr_to_reg (XEXP (operands[0], 0)));
4405
4406 if (GET_CODE (operands[1]) == MEM
4407 && GET_CODE (XEXP (operands[1], 0)) != REG
4408 && ! reload_in_progress)
4409 operands[1] = change_address (operands[1], TImode,
4410 copy_addr_to_reg (XEXP (operands[1], 0)));
4411 }")
4412
4413 ;; We say that MQ is clobbered in the last alternative because the first
4414 ;; alternative would never get used otherwise since it would need a reload
4415 ;; while the 2nd alternative would not. We put memory cases first so they
4416 ;; are preferred. Otherwise, we'd try to reload the output instead of
4417 ;; giving the SCRATCH mq.
4418 (define_insn ""
4419 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
4420 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
4421 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
4422 "TARGET_MULTIPLE && TARGET_POWER && ! TARGET_POWERPC64
4423 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
4424 "*
4425 {
4426 switch (which_alternative)
4427 {
4428 default:
4429 abort ();
4430
4431 case 0:
4432 return \"{stsi|stswi} %1,%P0,16\";
4433
4434 case 1:
4435 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
4436
4437 case 2:
4438 /* Normally copy registers with lowest numbered register copied first.
4439 But copy in the other order if the first register of the output
4440 is the second, third, or fourth register in the input. */
4441 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
4442 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
4443 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
4444 else
4445 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
4446 case 3:
4447 /* If the address is not used in the output, we can use lsi. Otherwise,
4448 fall through to generating four loads. */
4449 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
4450 return \"{lsi|lswi} %0,%P1,16\";
4451 /* ... fall through ... */
4452 case 4:
4453 /* If the address register is the same as the register for the lowest-
4454 addressed word, load it last. Similarly for the next two words.
4455 Otherwise load lowest address to highest. */
4456 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4457 operands[1], 0))
4458 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
4459 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
4460 REGNO (operands[0]) + 2, operands[1], 0))
4461 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
4462 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
4463 REGNO (operands[0]) + 3, operands[1], 0))
4464 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
4465 else
4466 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
4467 }
4468 }"
4469 [(set_attr "type" "*,load,load,*,*")
4470 (set_attr "length" "*,16,16,*,16")])
4471
4472 (define_insn ""
4473 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
4474 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
4475 (clobber (match_scratch:SI 2 "=X,X,X"))]
4476 "TARGET_MULTIPLE && !TARGET_POWER && ! TARGET_POWERPC64
4477 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
4478 "*
4479 {
4480 switch (which_alternative)
4481 {
4482 default:
4483 abort ();
4484
4485 case 0:
4486 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
4487
4488 case 1:
4489 /* Normally copy registers with lowest numbered register copied first.
4490 But copy in the other order if the first register of the output
4491 is the second, third, or fourth register in the input. */
4492 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
4493 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
4494 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
4495 else
4496 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
4497 case 2:
4498 /* If the address register is the same as the register for the lowest-
4499 addressed word, load it last. Similarly for the next two words.
4500 Otherwise load lowest address to highest. */
4501 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4502 operands[1], 0))
4503 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
4504 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
4505 REGNO (operands[0]) + 2, operands[1], 0))
4506 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
4507 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
4508 REGNO (operands[0]) + 3, operands[1], 0))
4509 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
4510 else
4511 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
4512 }
4513 }"
4514 [(set_attr "type" "load,*,*")
4515 (set_attr "length" "16,16,16")])
4516
4517 (define_insn ""
4518 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
4519 (match_operand:TI 1 "input_operand" "r,m,r"))]
4520 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
4521 || gpc_reg_operand (operands[1], TImode))"
4522 "*
4523 {
4524 switch (which_alternative)
4525 {
4526 case 0:
4527 /* We normally copy the low-numbered register first. However, if
4528 the first register operand 0 is the same as the second register of
4529 operand 1, we must copy in the opposite order. */
4530 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
4531 return \"mr %L0,%L1\;mr %0,%1\";
4532 else
4533 return \"mr %0,%1\;mr %L0,%L1\";
4534 case 1:
4535 /* If the low-address word is used in the address, we must load it
4536 last. Otherwise, load it first. Note that we cannot have
4537 auto-increment in that case since the address register is known to be
4538 dead. */
4539 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
4540 operands [1], 0))
4541 return \"ld %L0,%L1\;ld %0,%1\";
4542 else
4543 return \"ld%U1 %0,%1\;ld %L0,%L1\";
4544 case 2:
4545 return \"std%U0 %1,%0\;std %L1,%L0\";
4546 }
4547 }"
4548 [(set_attr "type" "*,load,*")
4549 (set_attr "length" "8,8,8")])
4550 \f
4551 (define_expand "load_multiple"
4552 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
4553 (match_operand:SI 1 "" ""))
4554 (use (match_operand:SI 2 "" ""))])]
4555 "TARGET_MULTIPLE"
4556 "
4557 {
4558 int regno;
4559 int count;
4560 rtx from;
4561 int i;
4562
4563 /* Support only loading a constant number of fixed-point registers from
4564 memory and only bother with this if more than two; the machine
4565 doesn't support more than eight. */
4566 if (GET_CODE (operands[2]) != CONST_INT
4567 || INTVAL (operands[2]) <= 2
4568 || INTVAL (operands[2]) > 8
4569 || GET_CODE (operands[1]) != MEM
4570 || GET_CODE (operands[0]) != REG
4571 || REGNO (operands[0]) >= 32)
4572 FAIL;
4573
4574 count = INTVAL (operands[2]);
4575 regno = REGNO (operands[0]);
4576
4577 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
4578 from = force_reg (SImode, XEXP (operands[1], 0));
4579
4580 for (i = 0; i < count; i++)
4581 XVECEXP (operands[3], 0, i)
4582 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
4583 gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
4584 }")
4585
4586 (define_insn ""
4587 [(match_parallel 0 "load_multiple_operation"
4588 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
4589 (match_operand:SI 2 "indirect_operand" "Q"))])]
4590 "TARGET_MULTIPLE"
4591 "*
4592 {
4593 /* We have to handle the case where the pseudo used to contain the address
4594 is assigned to one of the output registers. In that case, do the
4595 lsi, but then load the correct value. This is a bit of a mess, but is
4596 the best we can do.
4597 We set the length attribute to the maximum possible size (8 bytes). */
4598 static char result[100];
4599 char newload[40];
4600 int i;
4601
4602 strcpy (result, \"{lsi|lswi} %1,%P2,%N0\");
4603 for (i = 0; i < XVECLEN (operands[0], 0); i++)
4604 if (refers_to_regno_p (REGNO (operands[1]) + i,
4605 REGNO (operands[1]) + i + 1, operands[2], 0))
4606 {
4607 sprintf (newload, \"\;{l|lwz} %d,%d(%d)\",
4608 REGNO (operands[1]) + i,
4609 i * 4, REGNO (XEXP (operands[2], 0)));
4610 strcat (result, newload);
4611 }
4612
4613 return result;
4614 }"
4615 [(set_attr "type" "load")
4616 (set_attr "length" "8")])
4617 \f
4618
4619 (define_expand "store_multiple"
4620 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
4621 (match_operand:SI 1 "" ""))
4622 (clobber (scratch:SI))
4623 (use (match_operand:SI 2 "" ""))])]
4624 "TARGET_MULTIPLE"
4625 "
4626 {
4627 int regno;
4628 int count;
4629 rtx to;
4630 int i;
4631
4632 /* Support only storing a constant number of fixed-point registers to
4633 memory and only bother with this if more than two; the machine
4634 doesn't support more than eight. */
4635 if (GET_CODE (operands[2]) != CONST_INT
4636 || INTVAL (operands[2]) <= 2
4637 || INTVAL (operands[2]) > 8
4638 || GET_CODE (operands[0]) != MEM
4639 || GET_CODE (operands[1]) != REG
4640 || REGNO (operands[1]) >= 32)
4641 FAIL;
4642
4643 count = INTVAL (operands[2]);
4644 regno = REGNO (operands[1]);
4645
4646 operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
4647 to = force_reg (SImode, XEXP (operands[0], 0));
4648
4649 XVECEXP (operands[3], 0, 0)
4650 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
4651 XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
4652 gen_rtx (SCRATCH, SImode));
4653
4654 for (i = 1; i < count; i++)
4655 XVECEXP (operands[3], 0, i + 1)
4656 = gen_rtx (SET, VOIDmode,
4657 gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
4658 gen_rtx (REG, SImode, regno + i));
4659 }")
4660
4661 (define_insn ""
4662 [(match_parallel 0 "store_multiple_operation"
4663 [(set (match_operand:SI 1 "indirect_operand" "=Q")
4664 (match_operand:SI 2 "gpc_reg_operand" "r"))
4665 (clobber (match_scratch:SI 3 "=q"))])]
4666 "TARGET_MULTIPLE && TARGET_POWER"
4667 "{stsi|stswi} %2,%P1,%O0")
4668
4669 (define_insn ""
4670 [(match_parallel 0 "store_multiple_operation"
4671 [(set (match_operand:SI 1 "indirect_operand" "=Q")
4672 (match_operand:SI 2 "gpc_reg_operand" "r"))
4673 (clobber (match_scratch:SI 3 "X"))])]
4674 "TARGET_MULTIPLE && !TARGET_POWER"
4675 "{stsi|stswi} %2,%P1,%O0")
4676 \f
4677 ;; Define insns that do load or store with update. Some of these we can
4678 ;; get by using pre-decrement or pre-increment, but the hardware can also
4679 ;; do cases where the increment is not the size of the object.
4680 ;;
4681 ;; In all these cases, we use operands 0 and 1 for the register being
4682 ;; incremented because those are the operands that local-alloc will
4683 ;; tie and these are the pair most likely to be tieable (and the ones
4684 ;; that will benefit the most).
4685
4686 (define_insn ""
4687 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
4688 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
4689 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
4690 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
4691 (plus:DI (match_dup 1) (match_dup 2)))]
4692 "TARGET_POWERPC64"
4693 "@
4694 ldux %3,%0,%2
4695 ldu %3,%2(%0)"
4696 [(set_attr "type" "load")])
4697
4698 (define_insn ""
4699 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
4700 (sign_extend:DI
4701 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
4702 (match_operand:DI 2 "gpc_reg_operand" "r")))))
4703 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
4704 (plus:DI (match_dup 1) (match_dup 2)))]
4705 "TARGET_POWERPC64"
4706 "lwaux %3,%0,%2"
4707 [(set_attr "type" "load")])
4708
4709 (define_insn ""
4710 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
4711 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
4712 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
4713 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
4714 (plus:DI (match_dup 1) (match_dup 2)))]
4715 "TARGET_POWERPC64"
4716 "@
4717 stdux %3,%0,%2
4718 stdu %3,%2(%0)")
4719
4720 (define_insn ""
4721 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
4722 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4723 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4724 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4725 (plus:SI (match_dup 1) (match_dup 2)))]
4726 ""
4727 "@
4728 {lux|lwzux} %3,%0,%2
4729 {lu|lwzu} %3,%2(%0)"
4730 [(set_attr "type" "load")])
4731
4732 (define_insn ""
4733 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4734 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4735 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
4736 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4737 (plus:SI (match_dup 1) (match_dup 2)))]
4738 ""
4739 "@
4740 {stux|stwux} %3,%0,%2
4741 {stu|stwu} %3,%2(%0)")
4742
4743 (define_insn ""
4744 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
4745 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4746 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4747 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4748 (plus:SI (match_dup 1) (match_dup 2)))]
4749 ""
4750 "@
4751 lhzux %3,%0,%2
4752 lhzu %3,%2(%0)"
4753 [(set_attr "type" "load")])
4754
4755 (define_insn ""
4756 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
4757 (zero_extend:SI
4758 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4759 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
4760 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4761 (plus:SI (match_dup 1) (match_dup 2)))]
4762 ""
4763 "@
4764 lhzux %3,%0,%2
4765 lhzu %3,%2(%0)"
4766 [(set_attr "type" "load")])
4767
4768 (define_insn ""
4769 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
4770 (sign_extend:SI
4771 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4772 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
4773 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4774 (plus:SI (match_dup 1) (match_dup 2)))]
4775 ""
4776 "@
4777 lhaux %3,%0,%2
4778 lhau %3,%2(%0)"
4779 [(set_attr "type" "load")])
4780
4781 (define_insn ""
4782 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4783 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4784 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
4785 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4786 (plus:SI (match_dup 1) (match_dup 2)))]
4787 ""
4788 "@
4789 sthux %3,%0,%2
4790 sthu %3,%2(%0)")
4791
4792 (define_insn ""
4793 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
4794 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4795 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4796 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4797 (plus:SI (match_dup 1) (match_dup 2)))]
4798 ""
4799 "@
4800 lbzux %3,%0,%2
4801 lbzu %3,%2(%0)"
4802 [(set_attr "type" "load")])
4803
4804 (define_insn ""
4805 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
4806 (zero_extend:SI
4807 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4808 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
4809 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4810 (plus:SI (match_dup 1) (match_dup 2)))]
4811 ""
4812 "@
4813 lbzux %3,%0,%2
4814 lbzu %3,%2(%0)"
4815 [(set_attr "type" "load")])
4816
4817 (define_insn ""
4818 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4819 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4820 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
4821 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4822 (plus:SI (match_dup 1) (match_dup 2)))]
4823 ""
4824 "@
4825 stbux %3,%0,%2
4826 stbu %3,%2(%0)")
4827
4828 (define_insn ""
4829 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
4830 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4831 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4832 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4833 (plus:SI (match_dup 1) (match_dup 2)))]
4834 "TARGET_HARD_FLOAT"
4835 "@
4836 lfsux %3,%0,%2
4837 lfsu %3,%2(%0)"
4838 [(set_attr "type" "fpload")])
4839
4840 (define_insn ""
4841 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4842 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4843 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
4844 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4845 (plus:SI (match_dup 1) (match_dup 2)))]
4846 "TARGET_HARD_FLOAT"
4847 "@
4848 stfsux %3,%0,%2
4849 stfsu %3,%2(%0)")
4850
4851 (define_insn ""
4852 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
4853 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4854 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
4855 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4856 (plus:SI (match_dup 1) (match_dup 2)))]
4857 "TARGET_HARD_FLOAT"
4858 "@
4859 lfdux %3,%0,%2
4860 lfdu %3,%2(%0)"
4861 [(set_attr "type" "fpload")])
4862
4863 (define_insn ""
4864 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
4865 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
4866 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
4867 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
4868 (plus:SI (match_dup 1) (match_dup 2)))]
4869 "TARGET_HARD_FLOAT"
4870 "@
4871 stfdux %3,%0,%2
4872 stfdu %3,%2(%0)")
4873
4874 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
4875
4876 (define_peephole
4877 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4878 (match_operand:DF 1 "memory_operand" ""))
4879 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
4880 (match_operand:DF 3 "memory_operand" ""))]
4881 "TARGET_POWER2
4882 && TARGET_HARD_FLOAT
4883 && registers_ok_for_quad_peep (operands[0], operands[2])
4884 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
4885 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
4886 "lfq%U1%X1 %0,%1")
4887
4888 (define_peephole
4889 [(set (match_operand:DF 0 "memory_operand" "")
4890 (match_operand:DF 1 "gpc_reg_operand" "f"))
4891 (set (match_operand:DF 2 "memory_operand" "")
4892 (match_operand:DF 3 "gpc_reg_operand" "f"))]
4893 "TARGET_POWER2
4894 && TARGET_HARD_FLOAT
4895 && registers_ok_for_quad_peep (operands[1], operands[3])
4896 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
4897 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
4898 "stfq%U0%X0 %1,%0")
4899 \f
4900 ;; Next come insns related to the calling sequence.
4901 ;;
4902 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
4903 ;; We move the back-chain and decrement the stack pointer.
4904
4905 (define_expand "allocate_stack"
4906 [(set (reg:SI 1)
4907 (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))]
4908 ""
4909 "
4910 { rtx chain = gen_reg_rtx (SImode);
4911 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
4912
4913 emit_move_insn (chain, stack_bot);
4914 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
4915 emit_move_insn (stack_bot, chain);
4916 DONE;
4917 }")
4918
4919 ;; These patterns say how to save and restore the stack pointer. We need not
4920 ;; save the stack pointer at function level since we are careful to
4921 ;; preserve the backchain. At block level, we have to restore the backchain
4922 ;; when we restore the stack pointer.
4923 ;;
4924 ;; For nonlocal gotos, we must save both the stack pointer and its
4925 ;; backchain and restore both. Note that in the nonlocal case, the
4926 ;; save area is a memory location.
4927
4928 (define_expand "save_stack_function"
4929 [(use (const_int 0))]
4930 ""
4931 "")
4932
4933 (define_expand "restore_stack_function"
4934 [(use (const_int 0))]
4935 ""
4936 "")
4937
4938 (define_expand "restore_stack_block"
4939 [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
4940 (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
4941 (set (mem:SI (match_dup 0)) (match_dup 2))]
4942 ""
4943 "
4944 { operands[2] = gen_reg_rtx (SImode); }")
4945
4946 (define_expand "save_stack_nonlocal"
4947 [(match_operand:DI 0 "memory_operand" "")
4948 (match_operand:SI 1 "register_operand" "")]
4949 ""
4950 "
4951 {
4952 rtx temp = gen_reg_rtx (SImode);
4953
4954 /* Copy the backchain to the first word, sp to the second. */
4955 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
4956 emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
4957 emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
4958 DONE;
4959 }")
4960
4961 (define_expand "restore_stack_nonlocal"
4962 [(match_operand:SI 0 "register_operand" "")
4963 (match_operand:DI 1 "memory_operand" "")]
4964 ""
4965 "
4966 {
4967 rtx temp = gen_reg_rtx (SImode);
4968
4969 /* Restore the backchain from the first word, sp from the second. */
4970 emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
4971 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
4972 emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
4973 DONE;
4974 }")
4975 \f
4976 ;; A function pointer is a pointer to a data area whose first word contains
4977 ;; the actual address of the function, whose second word contains a pointer
4978 ;; to its TOC, and whose third word contains a value to place in the static
4979 ;; chain register (r11). Note that if we load the static chain, our
4980 ;; "trampoline" need not have any executable code.
4981 ;;
4982 ;; operands[0] is an SImode pseudo in which we place the address of the
4983 ;; function.
4984 ;; operands[1] is the address of data area of the function to call
4985
4986 (define_expand "call_via_ptr"
4987 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4988 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
4989 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
4990 (reg:SI 2))
4991 (set (reg:SI 2)
4992 (mem:SI (plus:SI (match_dup 1)
4993 (const_int 4))))
4994 (set (reg:SI 11)
4995 (mem:SI (plus:SI (match_dup 1)
4996 (const_int 8))))
4997 (use (reg:SI 2))
4998 (use (reg:SI 11))]
4999 ""
5000 "")
5001
5002 (define_expand "call"
5003 [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
5004 (match_operand 1 "" ""))
5005 (clobber (scratch:SI))])]
5006 ""
5007 "
5008 {
5009 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
5010 abort ();
5011
5012 operands[0] = XEXP (operands[0], 0);
5013 if (GET_CODE (operands[0]) != SYMBOL_REF)
5014 {
5015 #ifndef USING_SVR4_H
5016 /* AIX function pointers are really pointers to a three word area */
5017 rtx temp = gen_reg_rtx (SImode);
5018
5019 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
5020 operands[0] = temp;
5021 #endif /* !USING_SVR4_H */
5022 }
5023 }")
5024
5025 (define_expand "call_value"
5026 [(parallel [(set (match_operand 0 "" "")
5027 (call (mem:SI (match_operand:SI 1 "address_operand" ""))
5028 (match_operand 2 "" "")))
5029 (clobber (scratch:SI))])]
5030 ""
5031 "
5032 {
5033 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
5034 abort ();
5035
5036 operands[1] = XEXP (operands[1], 0);
5037 if (GET_CODE (operands[1]) != SYMBOL_REF)
5038 {
5039 #ifndef USING_SVR4_H
5040 /* AIX function pointers are really pointers to a three word area */
5041 rtx temp = gen_reg_rtx (SImode);
5042
5043 emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
5044 operands[1] = temp;
5045 #endif /* !USING_SVR4_H */
5046 }
5047 }")
5048
5049 ;; Call to function in current module. No TOC pointer reload needed.
5050
5051 (define_insn ""
5052 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s"))
5053 (match_operand 1 "" "g"))
5054 (clobber (match_scratch:SI 2 "=l"))]
5055 ""
5056 "bl %z0")
5057
5058 ;; Call to function which may be in another module. Restore the TOC
5059 ;; pointer (r2) after the call unless this is System V.
5060
5061 (define_insn ""
5062 [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
5063 (match_operand 1 "" "fg,fg"))
5064 (clobber (match_scratch:SI 2 "=l,l"))]
5065 ""
5066 "*
5067 {
5068 #ifndef USING_SVR4_H
5069 if (GET_CODE (operands[0]) == REG)
5070 return \"{brl|blrl}\;{l|lwz} 2,20(1)\";
5071
5072 return \"bl %z0\;%.\";
5073
5074 #else
5075 if (GET_CODE (operands[0]) == REG)
5076 return \"{brl|blrl}\";
5077
5078 return \"bl %z0\";
5079 #endif
5080 }"
5081 [(set_attr "length" "8")])
5082
5083 (define_insn ""
5084 [(set (match_operand 0 "" "=fg")
5085 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s"))
5086 (match_operand 2 "" "g")))
5087 (clobber (match_scratch:SI 3 "=l"))]
5088 ""
5089 "bl %z1")
5090
5091 (define_insn ""
5092 [(set (match_operand 0 "" "=fg,fg")
5093 (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
5094 (match_operand 2 "" "fg,fg")))
5095 (clobber (match_scratch:SI 3 "=l,l"))]
5096 ""
5097 "*
5098 {
5099 #ifndef USING_SVR4_H
5100 if (GET_CODE (operands[1]) == REG)
5101 return \"{brl|blrl}\;{l|lwz} 2,20(1)\";
5102
5103 return \"bl %z1\;%.\";
5104
5105 #else
5106 if (GET_CODE (operands[1]) == REG)
5107 return \"{brl|blrl}\";
5108
5109 return \"bl %z1\";
5110 #endif
5111 }"
5112 [(set_attr "length" "8")])
5113
5114 ;; Call subroutine returning any type.
5115
5116 (define_expand "untyped_call"
5117 [(parallel [(call (match_operand 0 "" "")
5118 (const_int 0))
5119 (match_operand 1 "" "")
5120 (match_operand 2 "" "")])]
5121 ""
5122 "
5123 {
5124 int i;
5125
5126 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
5127
5128 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5129 {
5130 rtx set = XVECEXP (operands[2], 0, i);
5131 emit_move_insn (SET_DEST (set), SET_SRC (set));
5132 }
5133
5134 /* The optimizer does not know that the call sets the function value
5135 registers we stored in the result block. We avoid problems by
5136 claiming that all hard registers are used and clobbered at this
5137 point. */
5138 emit_insn (gen_blockage ());
5139
5140 DONE;
5141 }")
5142
5143 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
5144 ;; all of memory. This blocks insns from being moved across this point.
5145
5146 (define_insn "blockage"
5147 [(unspec_volatile [(const_int 0)] 0)]
5148 ""
5149 "")
5150 \f
5151 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
5152 ;; signed & unsigned, and one type of branch.
5153 ;;
5154 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
5155 ;; insns, and branches. We store the operands of compares until we see
5156 ;; how it is used.
5157 (define_expand "cmpsi"
5158 [(set (cc0)
5159 (compare (match_operand:SI 0 "gpc_reg_operand" "")
5160 (match_operand:SI 1 "reg_or_short_operand" "")))]
5161 ""
5162 "
5163 {
5164 /* Take care of the possibility that operands[1] might be negative but
5165 this might be a logical operation. That insn doesn't exist. */
5166 if (GET_CODE (operands[1]) == CONST_INT
5167 && INTVAL (operands[1]) < 0)
5168 operands[1] = force_reg (SImode, operands[1]);
5169
5170 rs6000_compare_op0 = operands[0];
5171 rs6000_compare_op1 = operands[1];
5172 rs6000_compare_fp_p = 0;
5173 DONE;
5174 }")
5175
5176 (define_expand "cmpsf"
5177 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
5178 (match_operand:SF 1 "gpc_reg_operand" "")))]
5179 "TARGET_HARD_FLOAT"
5180 "
5181 {
5182 rs6000_compare_op0 = operands[0];
5183 rs6000_compare_op1 = operands[1];
5184 rs6000_compare_fp_p = 1;
5185 DONE;
5186 }")
5187
5188 (define_expand "cmpdf"
5189 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
5190 (match_operand:DF 1 "gpc_reg_operand" "")))]
5191 "TARGET_HARD_FLOAT"
5192 "
5193 {
5194 rs6000_compare_op0 = operands[0];
5195 rs6000_compare_op1 = operands[1];
5196 rs6000_compare_fp_p = 1;
5197 DONE;
5198 }")
5199
5200 (define_expand "beq"
5201 [(set (match_dup 2) (match_dup 1))
5202 (set (pc)
5203 (if_then_else (eq (match_dup 2)
5204 (const_int 0))
5205 (label_ref (match_operand 0 "" ""))
5206 (pc)))]
5207 ""
5208 "
5209 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5210 operands[1] = gen_rtx (COMPARE, mode,
5211 rs6000_compare_op0, rs6000_compare_op1);
5212 operands[2] = gen_reg_rtx (mode);
5213 }")
5214
5215 (define_expand "bne"
5216 [(set (match_dup 2) (match_dup 1))
5217 (set (pc)
5218 (if_then_else (ne (match_dup 2)
5219 (const_int 0))
5220 (label_ref (match_operand 0 "" ""))
5221 (pc)))]
5222 ""
5223 "
5224 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5225 operands[1] = gen_rtx (COMPARE, mode,
5226 rs6000_compare_op0, rs6000_compare_op1);
5227 operands[2] = gen_reg_rtx (mode);
5228 }")
5229
5230 (define_expand "blt"
5231 [(set (match_dup 2) (match_dup 1))
5232 (set (pc)
5233 (if_then_else (lt (match_dup 2)
5234 (const_int 0))
5235 (label_ref (match_operand 0 "" ""))
5236 (pc)))]
5237 ""
5238 "
5239 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5240 operands[1] = gen_rtx (COMPARE, mode,
5241 rs6000_compare_op0, rs6000_compare_op1);
5242 operands[2] = gen_reg_rtx (mode);
5243 }")
5244
5245 (define_expand "bgt"
5246 [(set (match_dup 2) (match_dup 1))
5247 (set (pc)
5248 (if_then_else (gt (match_dup 2)
5249 (const_int 0))
5250 (label_ref (match_operand 0 "" ""))
5251 (pc)))]
5252 ""
5253 "
5254 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5255 operands[1] = gen_rtx (COMPARE, mode,
5256 rs6000_compare_op0, rs6000_compare_op1);
5257 operands[2] = gen_reg_rtx (mode);
5258 }")
5259
5260 (define_expand "ble"
5261 [(set (match_dup 2) (match_dup 1))
5262 (set (pc)
5263 (if_then_else (le (match_dup 2)
5264 (const_int 0))
5265 (label_ref (match_operand 0 "" ""))
5266 (pc)))]
5267 ""
5268 "
5269 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5270 operands[1] = gen_rtx (COMPARE, mode,
5271 rs6000_compare_op0, rs6000_compare_op1);
5272 operands[2] = gen_reg_rtx (mode);
5273 }")
5274
5275 (define_expand "bge"
5276 [(set (match_dup 2) (match_dup 1))
5277 (set (pc)
5278 (if_then_else (ge (match_dup 2)
5279 (const_int 0))
5280 (label_ref (match_operand 0 "" ""))
5281 (pc)))]
5282 ""
5283 "
5284 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5285 operands[1] = gen_rtx (COMPARE, mode,
5286 rs6000_compare_op0, rs6000_compare_op1);
5287 operands[2] = gen_reg_rtx (mode);
5288 }")
5289
5290 (define_expand "bgtu"
5291 [(set (match_dup 2) (match_dup 1))
5292 (set (pc)
5293 (if_then_else (gtu (match_dup 2)
5294 (const_int 0))
5295 (label_ref (match_operand 0 "" ""))
5296 (pc)))]
5297 ""
5298 "
5299 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5300 rs6000_compare_op0, rs6000_compare_op1);
5301 operands[2] = gen_reg_rtx (CCUNSmode);
5302 }")
5303
5304 (define_expand "bltu"
5305 [(set (match_dup 2) (match_dup 1))
5306 (set (pc)
5307 (if_then_else (ltu (match_dup 2)
5308 (const_int 0))
5309 (label_ref (match_operand 0 "" ""))
5310 (pc)))]
5311 ""
5312 "
5313 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5314 rs6000_compare_op0, rs6000_compare_op1);
5315 operands[2] = gen_reg_rtx (CCUNSmode);
5316 }")
5317
5318 (define_expand "bgeu"
5319 [(set (match_dup 2) (match_dup 1))
5320 (set (pc)
5321 (if_then_else (geu (match_dup 2)
5322 (const_int 0))
5323 (label_ref (match_operand 0 "" ""))
5324 (pc)))]
5325 ""
5326 "
5327 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5328 rs6000_compare_op0, rs6000_compare_op1);
5329 operands[2] = gen_reg_rtx (CCUNSmode);
5330 }")
5331
5332 (define_expand "bleu"
5333 [(set (match_dup 2) (match_dup 1))
5334 (set (pc)
5335 (if_then_else (leu (match_dup 2)
5336 (const_int 0))
5337 (label_ref (match_operand 0 "" ""))
5338 (pc)))]
5339 ""
5340 "
5341 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5342 rs6000_compare_op0, rs6000_compare_op1);
5343 operands[2] = gen_reg_rtx (CCUNSmode);
5344 }")
5345
5346 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
5347 ;; For SEQ, likewise, except that comparisons with zero should be done
5348 ;; with an scc insns. However, due to the order that combine see the
5349 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
5350 ;; the cases we don't want to handle.
5351 (define_expand "seq"
5352 [(set (match_dup 2) (match_dup 1))
5353 (set (match_operand:SI 0 "gpc_reg_operand" "")
5354 (eq:SI (match_dup 2) (const_int 0)))]
5355 ""
5356 "
5357 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5358 operands[1] = gen_rtx (COMPARE, mode,
5359 rs6000_compare_op0, rs6000_compare_op1);
5360 operands[2] = gen_reg_rtx (mode);
5361 }")
5362
5363 (define_expand "sne"
5364 [(set (match_dup 2) (match_dup 1))
5365 (set (match_operand:SI 0 "gpc_reg_operand" "")
5366 (ne:SI (match_dup 2) (const_int 0)))]
5367 ""
5368 "
5369 { if (! rs6000_compare_fp_p)
5370 FAIL;
5371
5372 operands[1] = gen_rtx (COMPARE, CCFPmode,
5373 rs6000_compare_op0, rs6000_compare_op1);
5374 operands[2] = gen_reg_rtx (CCFPmode);
5375 }")
5376
5377 ;; A > 0 is best done using the portable sequence, so fail in that case.
5378 (define_expand "sgt"
5379 [(set (match_dup 2) (match_dup 1))
5380 (set (match_operand:SI 0 "gpc_reg_operand" "")
5381 (gt:SI (match_dup 2) (const_int 0)))]
5382 ""
5383 "
5384 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5385
5386 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5387 FAIL;
5388
5389 operands[1] = gen_rtx (COMPARE, mode,
5390 rs6000_compare_op0, rs6000_compare_op1);
5391 operands[2] = gen_reg_rtx (mode);
5392 }")
5393
5394 ;; A < 0 is best done in the portable way for A an integer.
5395 (define_expand "slt"
5396 [(set (match_dup 2) (match_dup 1))
5397 (set (match_operand:SI 0 "gpc_reg_operand" "")
5398 (lt:SI (match_dup 2) (const_int 0)))]
5399 ""
5400 "
5401 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5402
5403 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5404 FAIL;
5405
5406 operands[1] = gen_rtx (COMPARE, mode,
5407 rs6000_compare_op0, rs6000_compare_op1);
5408 operands[2] = gen_reg_rtx (mode);
5409 }")
5410
5411 (define_expand "sge"
5412 [(set (match_dup 2) (match_dup 1))
5413 (set (match_operand:SI 0 "gpc_reg_operand" "")
5414 (ge:SI (match_dup 2) (const_int 0)))]
5415 ""
5416 "
5417 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5418 operands[1] = gen_rtx (COMPARE, mode,
5419 rs6000_compare_op0, rs6000_compare_op1);
5420 operands[2] = gen_reg_rtx (mode);
5421 }")
5422
5423 ;; A <= 0 is best done the portable way for A an integer.
5424 (define_expand "sle"
5425 [(set (match_dup 2) (match_dup 1))
5426 (set (match_operand:SI 0 "gpc_reg_operand" "")
5427 (le:SI (match_dup 2) (const_int 0)))]
5428 ""
5429 "
5430 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
5431
5432 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
5433 FAIL;
5434
5435 operands[1] = gen_rtx (COMPARE, mode,
5436 rs6000_compare_op0, rs6000_compare_op1);
5437 operands[2] = gen_reg_rtx (mode);
5438 }")
5439
5440 (define_expand "sgtu"
5441 [(set (match_dup 2) (match_dup 1))
5442 (set (match_operand:SI 0 "gpc_reg_operand" "")
5443 (gtu:SI (match_dup 2) (const_int 0)))]
5444 ""
5445 "
5446 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5447 rs6000_compare_op0, rs6000_compare_op1);
5448 operands[2] = gen_reg_rtx (CCUNSmode);
5449 }")
5450
5451 (define_expand "sltu"
5452 [(set (match_dup 2) (match_dup 1))
5453 (set (match_operand:SI 0 "gpc_reg_operand" "")
5454 (ltu:SI (match_dup 2) (const_int 0)))]
5455 ""
5456 "
5457 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5458 rs6000_compare_op0, rs6000_compare_op1);
5459 operands[2] = gen_reg_rtx (CCUNSmode);
5460 }")
5461
5462 (define_expand "sgeu"
5463 [(set (match_dup 2) (match_dup 1))
5464 (set (match_operand:SI 0 "gpc_reg_operand" "")
5465 (geu:SI (match_dup 2) (const_int 0)))]
5466 ""
5467 "
5468 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5469 rs6000_compare_op0, rs6000_compare_op1);
5470 operands[2] = gen_reg_rtx (CCUNSmode);
5471 }")
5472
5473 (define_expand "sleu"
5474 [(set (match_dup 2) (match_dup 1))
5475 (set (match_operand:SI 0 "gpc_reg_operand" "")
5476 (leu:SI (match_dup 2) (const_int 0)))]
5477 ""
5478 "
5479 { operands[1] = gen_rtx (COMPARE, CCUNSmode,
5480 rs6000_compare_op0, rs6000_compare_op1);
5481 operands[2] = gen_reg_rtx (CCUNSmode);
5482 }")
5483 \f
5484 ;; Here are the actual compare insns.
5485 (define_insn ""
5486 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
5487 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
5488 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
5489 ""
5490 "{cmp%I2|cmpw%I2} %0,%1,%2"
5491 [(set_attr "type" "compare")])
5492
5493 ;; If we are comparing a register for equality with a large constant,
5494 ;; we can do this with an XOR followed by a compare. But we need a scratch
5495 ;; register for the result of the XOR.
5496
5497 (define_split
5498 [(set (match_operand:CC 0 "cc_reg_operand" "")
5499 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
5500 (match_operand:SI 2 "non_short_cint_operand" "")))
5501 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
5502 "find_single_use (operands[0], insn, 0)
5503 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
5504 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
5505 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
5506 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
5507 "
5508 {
5509 /* Get the constant we are comparing against, C, and see what it looks like
5510 sign-extended to 16 bits. Then see what constant could be XOR'ed
5511 with C to get the sign-extended value. */
5512
5513 int c = INTVAL (operands[2]);
5514 int sextc = (c << 16) >> 16;
5515 int xorv = c ^ sextc;
5516
5517 operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
5518 operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
5519 }")
5520
5521 (define_insn ""
5522 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
5523 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
5524 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
5525 ""
5526 "{cmpl%I2|cmplw%I2} %0,%1,%W2"
5527 [(set_attr "type" "compare")])
5528
5529 ;; The following two insns don't exist as single insns, but if we provide
5530 ;; them, we can swap an add and compare, which will enable us to overlap more
5531 ;; of the required delay between a compare and branch. We generate code for
5532 ;; them by splitting.
5533
5534 (define_insn ""
5535 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
5536 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
5537 (match_operand:SI 2 "short_cint_operand" "i")))
5538 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
5539 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
5540 ""
5541 "#"
5542 [(set_attr "length" "8")])
5543
5544 (define_insn ""
5545 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
5546 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
5547 (match_operand:SI 2 "u_short_cint_operand" "i")))
5548 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
5549 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
5550 ""
5551 "#"
5552 [(set_attr "length" "8")])
5553
5554 (define_split
5555 [(set (match_operand:CC 3 "cc_reg_operand" "")
5556 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
5557 (match_operand:SI 2 "short_cint_operand" "")))
5558 (set (match_operand:SI 0 "gpc_reg_operand" "")
5559 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
5560 ""
5561 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
5562 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
5563
5564 (define_split
5565 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
5566 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
5567 (match_operand:SI 2 "u_short_cint_operand" "")))
5568 (set (match_operand:SI 0 "gpc_reg_operand" "")
5569 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
5570 ""
5571 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
5572 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
5573
5574 (define_insn ""
5575 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
5576 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
5577 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5578 "TARGET_HARD_FLOAT"
5579 "fcmpu %0,%1,%2"
5580 [(set_attr "type" "fpcompare")])
5581
5582 (define_insn ""
5583 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
5584 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
5585 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5586 "TARGET_HARD_FLOAT"
5587 "fcmpu %0,%1,%2"
5588 [(set_attr "type" "fpcompare")])
5589 \f
5590 ;; Now we have the scc insns. We can do some combinations because of the
5591 ;; way the machine works.
5592 ;;
5593 ;; Note that this is probably faster if we can put an insn between the
5594 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
5595 ;; cases the insns below which don't use an intermediate CR field will
5596 ;; be used instead.
5597 (define_insn ""
5598 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5599 (match_operator:SI 1 "scc_comparison_operator"
5600 [(match_operand 2 "cc_reg_operand" "y")
5601 (const_int 0)]))]
5602 ""
5603 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
5604 [(set_attr "length" "12")])
5605
5606 (define_insn ""
5607 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5608 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
5609 [(match_operand 2 "cc_reg_operand" "y")
5610 (const_int 0)])
5611 (const_int 0)))
5612 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
5613 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
5614 ""
5615 "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
5616 [(set_attr "type" "delayed_compare")
5617 (set_attr "length" "12")])
5618
5619 (define_insn ""
5620 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5621 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
5622 [(match_operand 2 "cc_reg_operand" "y")
5623 (const_int 0)])
5624 (match_operand:SI 3 "const_int_operand" "n")))]
5625 ""
5626 "*
5627 {
5628 int is_bit = ccr_bit (operands[1], 1);
5629 int put_bit = 31 - (INTVAL (operands[3]) & 31);
5630 int count;
5631
5632 if (is_bit >= put_bit)
5633 count = is_bit - put_bit;
5634 else
5635 count = 32 - (put_bit - is_bit);
5636
5637 operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
5638 operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
5639
5640 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
5641 }"
5642 [(set_attr "length" "12")])
5643
5644 (define_insn ""
5645 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5646 (compare:CC
5647 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
5648 [(match_operand 2 "cc_reg_operand" "y")
5649 (const_int 0)])
5650 (match_operand:SI 3 "const_int_operand" "n"))
5651 (const_int 0)))
5652 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
5653 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
5654 (match_dup 3)))]
5655 ""
5656 "*
5657 {
5658 int is_bit = ccr_bit (operands[1], 1);
5659 int put_bit = 31 - (INTVAL (operands[3]) & 31);
5660 int count;
5661
5662 if (is_bit >= put_bit)
5663 count = is_bit - put_bit;
5664 else
5665 count = 32 - (put_bit - is_bit);
5666
5667 operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
5668 operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
5669
5670 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
5671 }"
5672 [(set_attr "type" "delayed_compare")
5673 (set_attr "length" "12")])
5674
5675 ;; If we are comparing the result of two comparisons, this can be done
5676 ;; using creqv or crxor.
5677
5678 (define_insn ""
5679 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
5680 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
5681 [(match_operand 2 "cc_reg_operand" "y")
5682 (const_int 0)])
5683 (match_operator 3 "scc_comparison_operator"
5684 [(match_operand 4 "cc_reg_operand" "y")
5685 (const_int 0)])))]
5686 "REGNO (operands[2]) != REGNO (operands[4])"
5687 "*
5688 {
5689 enum rtx_code code1, code2;
5690
5691 code1 = GET_CODE (operands[1]);
5692 code2 = GET_CODE (operands[3]);
5693
5694 if ((code1 == EQ || code1 == LT || code1 == GT
5695 || code1 == LTU || code1 == GTU
5696 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
5697 !=
5698 (code2 == EQ || code2 == LT || code2 == GT
5699 || code2 == LTU || code2 == GTU
5700 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
5701 return \"%C1%C3crxor %E0,%j1,%j3\";
5702 else
5703 return \"%C1%C3creqv %E0,%j1,%j3\";
5704 }"
5705 [(set_attr "length" "12")])
5706
5707 ;; There is a 3 cycle delay between consecutive mfcr instructions
5708 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
5709
5710 (define_peephole
5711 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5712 (match_operator:SI 1 "scc_comparison_operator"
5713 [(match_operand 2 "cc_reg_operand" "y")
5714 (const_int 0)]))
5715 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
5716 (match_operator:SI 4 "scc_comparison_operator"
5717 [(match_operand 5 "cc_reg_operand" "y")
5718 (const_int 0)]))]
5719 "REGNO (operands[2]) != REGNO (operands[5])"
5720 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
5721 [(set_attr "length" "20")])
5722
5723 ;; There are some scc insns that can be done directly, without a compare.
5724 ;; These are faster because they don't involve the communications between
5725 ;; the FXU and branch units. In fact, we will be replacing all of the
5726 ;; integer scc insns here or in the portable methods in emit_store_flag.
5727 ;;
5728 ;; Also support (neg (scc ..)) since that construct is used to replace
5729 ;; branches, (plus (scc ..) ..) since that construct is common and
5730 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
5731 ;; cases where it is no more expensive than (neg (scc ..)).
5732
5733 ;; Have reload force a constant into a register for the simple insns that
5734 ;; otherwise won't accept constants. We do this because it is faster than
5735 ;; the cmp/mfcr sequence we would otherwise generate.
5736
5737 (define_insn ""
5738 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5739 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5740 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
5741 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
5742 ""
5743 "@
5744 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
5745 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
5746 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
5747 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
5748 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
5749 [(set_attr "length" "12,8,12,12,12")])
5750
5751 (define_insn ""
5752 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
5753 (compare:CC
5754 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5755 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
5756 (const_int 0)))
5757 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5758 (eq:SI (match_dup 1) (match_dup 2)))
5759 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
5760 ""
5761 "@
5762 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
5763 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
5764 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
5765 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
5766 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0"
5767 [(set_attr "type" "compare")
5768 (set_attr "length" "12,8,12,12,12")])
5769
5770 ;; We have insns of the form shown by the first define_insn below. If
5771 ;; there is something inside the comparison operation, we must split it.
5772 (define_split
5773 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5774 (plus:SI (match_operator 1 "comparison_operator"
5775 [(match_operand:SI 2 "" "")
5776 (match_operand:SI 3
5777 "reg_or_cint_operand" "")])
5778 (match_operand:SI 4 "gpc_reg_operand" "")))
5779 (clobber (match_operand:SI 5 "register_operand" ""))]
5780 "! gpc_reg_operand (operands[2], SImode)"
5781 [(set (match_dup 5) (match_dup 2))
5782 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
5783 (match_dup 4)))])
5784
5785 (define_insn ""
5786 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5787 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5788 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
5789 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
5790 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
5791 ""
5792 "@
5793 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
5794 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
5795 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
5796 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
5797 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
5798 [(set_attr "length" "12,8,12,12,12")])
5799
5800 (define_insn ""
5801 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
5802 (compare:CC
5803 (plus:SI
5804 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5805 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
5806 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
5807 (const_int 0)))
5808 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
5809 ""
5810 "@
5811 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
5812 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
5813 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
5814 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
5815 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
5816 [(set_attr "type" "compare")
5817 (set_attr "length" "12,8,12,12,12")])
5818
5819 (define_insn ""
5820 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
5821 (compare:CC
5822 (plus:SI
5823 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5824 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
5825 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
5826 (const_int 0)))
5827 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5828 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5829 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
5830 ""
5831 "@
5832 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
5833 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
5834 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
5835 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
5836 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
5837 [(set_attr "type" "compare")
5838 (set_attr "length" "12,8,12,12,12")])
5839
5840 (define_insn ""
5841 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
5842 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
5843 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
5844 ""
5845 "@
5846 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
5847 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
5848 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
5849 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
5850 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
5851 [(set_attr "length" "12,8,12,12,12")])
5852
5853 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
5854 ;; since it nabs/sr is just as fast.
5855 (define_insn ""
5856 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5857 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
5858 (const_int 31)))
5859 (clobber (match_scratch:SI 2 "=&r"))]
5860 "!TARGET_POWER"
5861 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
5862 [(set_attr "length" "8")])
5863
5864 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
5865 (define_insn ""
5866 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5867 (plus:SI (lshiftrt:SI
5868 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
5869 (const_int 31))
5870 (match_operand:SI 2 "gpc_reg_operand" "r")))
5871 (clobber (match_scratch:SI 3 "=&r"))]
5872 ""
5873 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
5874 [(set_attr "length" "8")])
5875
5876 (define_insn ""
5877 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
5878 (compare:CC
5879 (plus:SI (lshiftrt:SI
5880 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
5881 (const_int 31))
5882 (match_operand:SI 2 "gpc_reg_operand" "r"))
5883 (const_int 0)))
5884 (clobber (match_scratch:SI 3 "=&r"))]
5885 ""
5886 "{ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2"
5887 [(set_attr "type" "compare")
5888 (set_attr "length" "8")])
5889
5890 (define_insn ""
5891 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
5892 (compare:CC
5893 (plus:SI (lshiftrt:SI
5894 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
5895 (const_int 31))
5896 (match_operand:SI 2 "gpc_reg_operand" "r"))
5897 (const_int 0)))
5898 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
5899 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
5900 (match_dup 2)))
5901 (clobber (match_scratch:SI 3 "=&r"))]
5902 ""
5903 "{ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2"
5904 [(set_attr "type" "compare")
5905 (set_attr "length" "8")])
5906
5907 (define_insn ""
5908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5909 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5910 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
5911 (clobber (match_scratch:SI 3 "=r,X"))]
5912 "TARGET_POWER"
5913 "@
5914 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
5915 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
5916 [(set_attr "length" "12")])
5917
5918 (define_insn ""
5919 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
5920 (compare:CC
5921 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5922 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
5923 (const_int 0)))
5924 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5925 (le:SI (match_dup 1) (match_dup 2)))
5926 (clobber (match_scratch:SI 3 "=r,X"))]
5927 "TARGET_POWER"
5928 "@
5929 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
5930 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31"
5931 [(set_attr "type" "compare,delayed_compare")
5932 (set_attr "length" "12")])
5933
5934 (define_insn ""
5935 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5936 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5937 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
5938 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
5939 (clobber (match_scratch:SI 4 "=&r,&r"))]
5940 "TARGET_POWER"
5941 "@
5942 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
5943 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
5944 [(set_attr "length" "12")])
5945
5946 (define_insn ""
5947 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
5948 (compare:CC
5949 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5950 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
5951 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
5952 (const_int 0)))
5953 (clobber (match_scratch:SI 4 "=&r,&r"))]
5954 "TARGET_POWER"
5955 "@
5956 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
5957 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3"
5958 [(set_attr "type" "compare")
5959 (set_attr "length" "12")])
5960
5961 (define_insn ""
5962 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
5963 (compare:CC
5964 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5965 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
5966 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
5967 (const_int 0)))
5968 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5969 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5970 (clobber (match_scratch:SI 4 "=&r,&r"))]
5971 "TARGET_POWER"
5972 "@
5973 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
5974 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3"
5975 [(set_attr "type" "compare")
5976 (set_attr "length" "12")])
5977
5978 (define_insn ""
5979 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5980 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5981 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
5982 "TARGET_POWER"
5983 "@
5984 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
5985 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
5986 [(set_attr "length" "12")])
5987
5988 (define_insn ""
5989 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5990 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5991 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
5992 ""
5993 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
5994 [(set_attr "length" "12")])
5995
5996 (define_insn ""
5997 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
5998 (compare:CC
5999 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6000 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6001 (const_int 0)))
6002 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6003 (leu:SI (match_dup 1) (match_dup 2)))]
6004 ""
6005 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
6006 [(set_attr "type" "compare")
6007 (set_attr "length" "12")])
6008
6009 (define_insn ""
6010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6011 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6012 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6013 (match_operand:SI 3 "gpc_reg_operand" "r")))
6014 (clobber (match_scratch:SI 4 "=&r"))]
6015 ""
6016 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
6017 [(set_attr "length" "8")])
6018
6019 (define_insn ""
6020 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6021 (compare:CC
6022 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6023 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6024 (match_operand:SI 3 "gpc_reg_operand" "r"))
6025 (const_int 0)))
6026 (clobber (match_scratch:SI 4 "=&r"))]
6027 ""
6028 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3"
6029 [(set_attr "type" "compare")
6030 (set_attr "length" "8")])
6031
6032 (define_insn ""
6033 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6034 (compare:CC
6035 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6036 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6037 (match_operand:SI 3 "gpc_reg_operand" "r"))
6038 (const_int 0)))
6039 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6040 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6041 (clobber (match_scratch:SI 4 "=&r"))]
6042 ""
6043 "{sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3"
6044 [(set_attr "type" "compare")
6045 (set_attr "length" "8")])
6046
6047 (define_insn ""
6048 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6049 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6050 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
6051 ""
6052 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
6053 [(set_attr "length" "12")])
6054
6055 (define_insn ""
6056 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6057 (and:SI (neg:SI
6058 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6059 (match_operand:SI 2 "reg_or_short_operand" "rI")))
6060 (match_operand:SI 3 "gpc_reg_operand" "r")))
6061 (clobber (match_scratch:SI 4 "=&r"))]
6062 ""
6063 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
6064 [(set_attr "length" "12")])
6065
6066 (define_insn ""
6067 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6068 (compare:CC
6069 (and:SI (neg:SI
6070 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6071 (match_operand:SI 2 "reg_or_short_operand" "rI")))
6072 (match_operand:SI 3 "gpc_reg_operand" "r"))
6073 (const_int 0)))
6074 (clobber (match_scratch:SI 4 "=&r"))]
6075 ""
6076 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
6077 [(set_attr "type" "compare")
6078 (set_attr "length" "12")])
6079
6080 (define_insn ""
6081 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6082 (compare:CC
6083 (and:SI (neg:SI
6084 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6085 (match_operand:SI 2 "reg_or_short_operand" "rI")))
6086 (match_operand:SI 3 "gpc_reg_operand" "r"))
6087 (const_int 0)))
6088 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6089 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
6090 (clobber (match_scratch:SI 4 "=&r"))]
6091 ""
6092 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
6093 [(set_attr "type" "compare")
6094 (set_attr "length" "12")])
6095
6096 (define_insn ""
6097 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6098 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6099 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
6100 "TARGET_POWER"
6101 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
6102 [(set_attr "length" "12")])
6103
6104 (define_insn ""
6105 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
6106 (compare:CC
6107 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6108 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6109 (const_int 0)))
6110 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6111 (lt:SI (match_dup 1) (match_dup 2)))]
6112 "TARGET_POWER"
6113 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
6114 [(set_attr "type" "delayed_compare")
6115 (set_attr "length" "12")])
6116
6117 (define_insn ""
6118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6119 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6120 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6121 (match_operand:SI 3 "gpc_reg_operand" "r")))
6122 (clobber (match_scratch:SI 4 "=&r"))]
6123 "TARGET_POWER"
6124 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
6125 [(set_attr "length" "12")])
6126
6127 (define_insn ""
6128 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6129 (compare:CC
6130 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6131 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6132 (match_operand:SI 3 "gpc_reg_operand" "r"))
6133 (const_int 0)))
6134 (clobber (match_scratch:SI 4 "=&r"))]
6135 "TARGET_POWER"
6136 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
6137 [(set_attr "type" "compare")
6138 (set_attr "length" "12")])
6139
6140 (define_insn ""
6141 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6142 (compare:CC
6143 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6144 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6145 (match_operand:SI 3 "gpc_reg_operand" "r"))
6146 (const_int 0)))
6147 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6148 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6149 (clobber (match_scratch:SI 4 "=&r"))]
6150 "TARGET_POWER"
6151 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
6152 [(set_attr "type" "compare")
6153 (set_attr "length" "12")])
6154
6155 (define_insn ""
6156 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6157 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6158 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
6159 "TARGET_POWER"
6160 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
6161 [(set_attr "length" "12")])
6162
6163 (define_insn ""
6164 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6165 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6166 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
6167 ""
6168 "@
6169 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
6170 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
6171 [(set_attr "length" "12")])
6172
6173 (define_insn ""
6174 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
6175 (compare:CC
6176 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6177 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6178 (const_int 0)))
6179 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6180 (ltu:SI (match_dup 1) (match_dup 2)))]
6181 ""
6182 "@
6183 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
6184 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
6185 [(set_attr "type" "compare")
6186 (set_attr "length" "12")])
6187
6188 (define_insn ""
6189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
6190 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
6191 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
6192 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
6193 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
6194 ""
6195 "@
6196 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
6197 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
6198 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
6199 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
6200 [(set_attr "length" "12")])
6201
6202 (define_insn ""
6203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
6204 (compare:CC
6205 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6206 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6207 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6208 (const_int 0)))
6209 (clobber (match_scratch:SI 4 "=&r,&r"))]
6210 ""
6211 "@
6212 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
6213 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3"
6214 [(set_attr "type" "compare")
6215 (set_attr "length" "12")])
6216
6217 (define_insn ""
6218 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
6219 (compare:CC
6220 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6221 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6222 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6223 (const_int 0)))
6224 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6225 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6226 (clobber (match_scratch:SI 4 "=&r,&r"))]
6227 ""
6228 "@
6229 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
6230 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
6231 [(set_attr "type" "compare")
6232 (set_attr "length" "12")])
6233
6234 (define_insn ""
6235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6236 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6237 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
6238 ""
6239 "@
6240 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
6241 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
6242 [(set_attr "length" "8")])
6243
6244 (define_insn ""
6245 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6246 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6247 (match_operand:SI 2 "reg_or_short_operand" "rI")))
6248 (clobber (match_scratch:SI 3 "=r"))]
6249 "TARGET_POWER"
6250 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
6251 [(set_attr "length" "12")])
6252
6253 (define_insn ""
6254 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
6255 (compare:CC
6256 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6257 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6258 (const_int 0)))
6259 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6260 (ge:SI (match_dup 1) (match_dup 2)))
6261 (clobber (match_scratch:SI 3 "=r"))]
6262 "TARGET_POWER"
6263 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3"
6264 [(set_attr "type" "compare")
6265 (set_attr "length" "12")])
6266
6267 (define_insn ""
6268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6269 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6270 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6271 (match_operand:SI 3 "gpc_reg_operand" "r")))
6272 (clobber (match_scratch:SI 4 "=&r"))]
6273 "TARGET_POWER"
6274 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
6275 [(set_attr "length" "12")])
6276
6277 (define_insn ""
6278 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6279 (compare:CC
6280 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6281 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6282 (match_operand:SI 3 "gpc_reg_operand" "r"))
6283 (const_int 0)))
6284 (clobber (match_scratch:SI 4 "=&r"))]
6285 "TARGET_POWER"
6286 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3"
6287 [(set_attr "type" "compare")
6288 (set_attr "length" "12")])
6289
6290 (define_insn ""
6291 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6292 (compare:CC
6293 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6294 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6295 (match_operand:SI 3 "gpc_reg_operand" "r"))
6296 (const_int 0)))
6297 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6298 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6299 (clobber (match_scratch:SI 4 "=&r"))]
6300 "TARGET_POWER"
6301 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3"
6302 [(set_attr "type" "compare")
6303 (set_attr "length" "12")])
6304
6305 (define_insn ""
6306 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6307 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6308 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
6309 "TARGET_POWER"
6310 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
6311 [(set_attr "length" "12")])
6312
6313 ;; This is (and (neg (ge X (const_int 0))) Y).
6314 (define_insn ""
6315 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6316 (and:SI (neg:SI
6317 (lshiftrt:SI
6318 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
6319 (const_int 31)))
6320 (match_operand:SI 2 "gpc_reg_operand" "r")))
6321 (clobber (match_scratch:SI 3 "=&r"))]
6322 ""
6323 "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
6324 [(set_attr "length" "8")])
6325
6326 (define_insn ""
6327 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6328 (compare:CC
6329 (and:SI (neg:SI
6330 (lshiftrt:SI
6331 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
6332 (const_int 31)))
6333 (match_operand:SI 2 "gpc_reg_operand" "r"))
6334 (const_int 0)))
6335 (clobber (match_scratch:SI 3 "=&r"))]
6336 ""
6337 "{srai|srawi} %3,%1,31\;andc. %3,%2,%3"
6338 [(set_attr "type" "compare")
6339 (set_attr "length" "8")])
6340
6341 (define_insn ""
6342 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
6343 (compare:CC
6344 (and:SI (neg:SI
6345 (lshiftrt:SI
6346 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
6347 (const_int 31)))
6348 (match_operand:SI 2 "gpc_reg_operand" "r"))
6349 (const_int 0)))
6350 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6351 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
6352 (const_int 31)))
6353 (match_dup 2)))
6354 (clobber (match_scratch:SI 3 "=&r"))]
6355 ""
6356 "{srai|srawi} %3,%1,31\;andc. %0,%2,%3"
6357 [(set_attr "type" "compare")
6358 (set_attr "length" "8")])
6359
6360 (define_insn ""
6361 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6362 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6363 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
6364 ""
6365 "@
6366 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
6367 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
6368 [(set_attr "length" "12")])
6369
6370 (define_insn ""
6371 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
6372 (compare:CC
6373 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6374 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6375 (const_int 0)))
6376 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6377 (geu:SI (match_dup 1) (match_dup 2)))]
6378 ""
6379 "@
6380 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
6381 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0"
6382 [(set_attr "type" "compare")
6383 (set_attr "length" "12")])
6384
6385 (define_insn ""
6386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6387 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6388 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6389 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
6390 (clobber (match_scratch:SI 4 "=&r,&r"))]
6391 ""
6392 "@
6393 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
6394 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
6395 [(set_attr "length" "8")])
6396
6397 (define_insn ""
6398 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
6399 (compare:CC
6400 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6401 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6402 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6403 (const_int 0)))
6404 (clobber (match_scratch:SI 4 "=&r,&r"))]
6405 ""
6406 "@
6407 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
6408 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
6409 [(set_attr "type" "compare")
6410 (set_attr "length" "8")])
6411
6412 (define_insn ""
6413 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
6414 (compare:CC
6415 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6416 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
6417 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6418 (const_int 0)))
6419 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6420 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6421 (clobber (match_scratch:SI 4 "=&r,&r"))]
6422 ""
6423 "@
6424 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
6425 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3"
6426 [(set_attr "type" "compare")
6427 (set_attr "length" "8")])
6428
6429 (define_insn ""
6430 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6431 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6432 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
6433 ""
6434 "@
6435 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
6436 {sfi|subfic} %0,%1,-1\;a%I2 %0,%0,%2\;{sfe|subfe} %0,%0,%0"
6437 [(set_attr "length" "12")])
6438
6439 (define_insn ""
6440 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6441 (and:SI (neg:SI
6442 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6443 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
6444 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
6445 (clobber (match_scratch:SI 4 "=&r,&r"))]
6446 ""
6447 "@
6448 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
6449 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
6450 [(set_attr "length" "12")])
6451
6452 (define_insn ""
6453 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
6454 (compare:CC
6455 (and:SI (neg:SI
6456 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6457 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
6458 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6459 (const_int 0)))
6460 (clobber (match_scratch:SI 4 "=&r,&r"))]
6461 ""
6462 "@
6463 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
6464 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4"
6465 [(set_attr "type" "compare")
6466 (set_attr "length" "12")])
6467
6468 (define_insn ""
6469 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
6470 (compare:CC
6471 (and:SI (neg:SI
6472 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6473 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
6474 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6475 (const_int 0)))
6476 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6477 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
6478 (clobber (match_scratch:SI 4 "=&r,&r"))]
6479 ""
6480 "@
6481 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
6482 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4"
6483 [(set_attr "type" "compare")
6484 (set_attr "length" "12")])
6485
6486 (define_insn ""
6487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6488 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6489 (const_int 0)))]
6490 ""
6491 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
6492 [(set_attr "length" "12")])
6493
6494 (define_insn ""
6495 [(set (match_operand:CC 2 "cc_reg_operand" "=x")
6496 (compare:CC
6497 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6498 (const_int 0))
6499 (const_int 0)))
6500 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6501 (gt:SI (match_dup 1) (const_int 0)))]
6502 ""
6503 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31"
6504 [(set_attr "type" "delayed_compare")
6505 (set_attr "length" "12")])
6506
6507 (define_insn ""
6508 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6509 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6510 (match_operand:SI 2 "reg_or_short_operand" "r")))]
6511 "TARGET_POWER"
6512 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
6513 [(set_attr "length" "12")])
6514
6515 (define_insn ""
6516 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
6517 (compare:CC
6518 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6519 (match_operand:SI 2 "reg_or_short_operand" "r"))
6520 (const_int 0)))
6521 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6522 (gt:SI (match_dup 1) (match_dup 2)))]
6523 "TARGET_POWER"
6524 "doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31"
6525 [(set_attr "type" "delayed_compare")
6526 (set_attr "length" "12")])
6527
6528 (define_insn ""
6529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6530 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6531 (const_int 0))
6532 (match_operand:SI 2 "gpc_reg_operand" "r")))
6533 (clobber (match_scratch:SI 3 "=&r"))]
6534 ""
6535 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
6536 [(set_attr "length" "12")])
6537
6538 (define_insn ""
6539 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6540 (compare:CC
6541 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6542 (const_int 0))
6543 (match_operand:SI 2 "gpc_reg_operand" "r"))
6544 (const_int 0)))
6545 (clobber (match_scratch:SI 3 "=&r"))]
6546 ""
6547 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2"
6548 [(set_attr "type" "compare")
6549 (set_attr "length" "12")])
6550
6551 (define_insn ""
6552 [(set (match_operand:CC 4 "cc_reg_operand" "=x")
6553 (compare:CC
6554 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6555 (const_int 0))
6556 (match_operand:SI 2 "gpc_reg_operand" "r"))
6557 (const_int 0)))
6558 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6559 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
6560 (clobber (match_scratch:SI 3 "=&r"))]
6561 ""
6562 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2"
6563 [(set_attr "type" "compare")
6564 (set_attr "length" "12")])
6565
6566 (define_insn ""
6567 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6568 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6569 (match_operand:SI 2 "reg_or_short_operand" "r"))
6570 (match_operand:SI 3 "gpc_reg_operand" "r")))
6571 (clobber (match_scratch:SI 4 "=&r"))]
6572 "TARGET_POWER"
6573 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
6574 [(set_attr "length" "12")])
6575
6576 (define_insn ""
6577 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
6578 (compare:CC
6579 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6580 (match_operand:SI 2 "reg_or_short_operand" "r"))
6581 (match_operand:SI 3 "gpc_reg_operand" "r"))
6582 (const_int 0)))
6583 (clobber (match_scratch:SI 4 "=&r"))]
6584 "TARGET_POWER"
6585 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3"
6586 [(set_attr "type" "compare")
6587 (set_attr "length" "12")])
6588
6589 (define_insn ""
6590 [(set (match_operand:CC 5 "cc_reg_operand" "=x")
6591 (compare:CC
6592 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6593 (match_operand:SI 2 "reg_or_short_operand" "r"))
6594 (match_operand:SI 3 "gpc_reg_operand" "r"))
6595 (const_int 0)))
6596 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6597 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6598 (clobber (match_scratch:SI 4 "=&r"))]
6599 "TARGET_POWER"
6600 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3"
6601 [(set_attr "type" "compare")
6602 (set_attr "length" "12")])
6603
6604 (define_insn ""
6605 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6606 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6607 (const_int 0))))]
6608 ""
6609 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
6610 [(set_attr "length" "12")])
6611
6612 (define_insn ""
6613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6614 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6615 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
6616 "TARGET_POWER"
6617 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
6618 [(set_attr "length" "12")])
6619
6620 (define_insn ""
6621 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6622 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6623 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
6624 ""
6625 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
6626 [(set_attr "length" "12")])
6627
6628 (define_insn ""
6629 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
6630 (compare:CC
6631 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6632 (match_operand:SI 2 "reg_or_short_operand" "rI"))
6633 (const_int 0)))
6634 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
6635 (gtu:SI (match_dup 1) (match_dup 2)))]
6636 ""
6637 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0"
6638 [(set_attr "type" "compare")
6639 (set_attr "length" "12")])
6640
6641 (define_insn ""
6642 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
6643 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
6644 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
6645 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
6646 (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
6647 ""
6648 "@
6649 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
6650 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
6651 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
6652 [(set_attr "length" "8,12,12")])
6653
6654 (define_insn ""
6655 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
6656 (compare:CC
6657 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6658 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
6659 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6660 (const_int 0)))
6661 (clobber (match_scratch:SI 4 "=&r,&r"))]
6662 ""
6663 "@
6664 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
6665 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
6666 [(set_attr "type" "compare")
6667 (set_attr "length" "8,12")])
6668
6669 (define_insn ""
6670 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
6671 (compare:CC
6672 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
6673 (match_operand:SI 2 "reg_or_short_operand" "I,r"))
6674 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
6675 (const_int 0)))
6676 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
6677 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
6678 (clobber (match_scratch:SI 4 "=&r,&r"))]
6679 ""
6680 "@
6681 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
6682 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3"
6683 [(set_attr "type" "compare")
6684 (set_attr "length" "8,12")])
6685
6686 (define_insn ""
6687 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6688 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
6689 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
6690 ""
6691 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
6692 [(set_attr "length" "8")])
6693 \f
6694 ;; Define both directions of branch and return. If we need a reload
6695 ;; register, we'd rather use CR0 since it is much easier to copy a
6696 ;; register CC value to there.
6697
6698 (define_insn ""
6699 [(set (pc)
6700 (if_then_else (match_operator 1 "branch_comparison_operator"
6701 [(match_operand 2
6702 "cc_reg_operand" "x,?y")
6703 (const_int 0)])
6704 (label_ref (match_operand 0 "" ""))
6705 (pc)))]
6706 ""
6707 "*
6708 {
6709 if (get_attr_length (insn) == 8)
6710 return \"%C1bc %t1,%j1,%l0\";
6711 else
6712 return \"%C1bc %T1,%j1,$+8\;b %l0\";
6713 }"
6714 [(set_attr "type" "branch")])
6715
6716 (define_insn ""
6717 [(set (pc)
6718 (if_then_else (match_operator 0 "branch_comparison_operator"
6719 [(match_operand 1
6720 "cc_reg_operand" "x,?y")
6721 (const_int 0)])
6722 (return)
6723 (pc)))]
6724 "direct_return ()"
6725 "{%C0bcr|%C0bclr} %t0,%j0"
6726 [(set_attr "length" "8")])
6727
6728 (define_insn ""
6729 [(set (pc)
6730 (if_then_else (match_operator 1 "branch_comparison_operator"
6731 [(match_operand 2
6732 "cc_reg_operand" "x,?y")
6733 (const_int 0)])
6734 (pc)
6735 (label_ref (match_operand 0 "" ""))))]
6736 ""
6737 "*
6738 {
6739 if (get_attr_length (insn) == 8)
6740 return \"%C1bc %T1,%j1,%l0\";
6741 else
6742 return \"%C1bc %t1,%j1,$+8\;b %l0\";
6743 }"
6744 [(set_attr "type" "branch")])
6745
6746 (define_insn ""
6747 [(set (pc)
6748 (if_then_else (match_operator 0 "branch_comparison_operator"
6749 [(match_operand 1
6750 "cc_reg_operand" "x,?y")
6751 (const_int 0)])
6752 (pc)
6753 (return)))]
6754 "direct_return ()"
6755 "{%C0bcr|%C0bclr} %T0,%j0"
6756 [(set_attr "length" "8")])
6757
6758 ;; Unconditional branch and return.
6759
6760 (define_insn "jump"
6761 [(set (pc)
6762 (label_ref (match_operand 0 "" "")))]
6763 ""
6764 "b %l0")
6765
6766 (define_insn "return"
6767 [(return)]
6768 "direct_return ()"
6769 "{br|blr}"
6770 [(set_attr "type" "jmpreg")])
6771
6772 (define_insn "indirect_jump"
6773 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
6774 ""
6775 "@
6776 bctr
6777 {br|blr}"
6778 [(set_attr "type" "jmpreg")])
6779
6780 ;; Table jump for switch statements:
6781 (define_expand "tablejump"
6782 [(set (match_dup 3)
6783 (plus:SI (match_operand:SI 0 "" "")
6784 (match_dup 2)))
6785 (parallel [(set (pc) (match_dup 3))
6786 (use (label_ref (match_operand 1 "" "")))])]
6787 ""
6788 "
6789 { operands[0] = force_reg (SImode, operands[0]);
6790 operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
6791 operands[3] = gen_reg_rtx (SImode);
6792 }")
6793
6794 (define_insn ""
6795 [(set (pc)
6796 (match_operand:SI 0 "register_operand" "c,l"))
6797 (use (label_ref (match_operand 1 "" "")))]
6798 ""
6799 "@
6800 bctr
6801 {br|blr}")
6802
6803 (define_insn "nop"
6804 [(const_int 0)]
6805 ""
6806 "{cror 0,0,0|nop}")
6807 \f
6808 ;; Define the subtract-one-and-jump insns, starting with the template
6809 ;; so loop.c knows what to generate.
6810
6811 (define_expand "decrement_and_branchsi"
6812 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "c")
6813 (const_int 1))
6814 (label_ref (match_operand 1 "" ""))
6815 (pc)))
6816 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))])]
6817 ""
6818 "")
6819
6820 ;; We need to be able to do this for any operand, including MEM, or we
6821 ;; will cause reload to blow up since we don't allow output reloads on
6822 ;; JUMP_INSNs.
6823 (define_insn ""
6824 [(set (pc)
6825 (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
6826 (const_int 1))
6827 (label_ref (match_operand 2 "" ""))
6828 (pc)))
6829 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
6830 (plus:SI (match_dup 1) (const_int -1)))
6831 (clobber (match_scratch:CC 3 "=X,&x,&x"))
6832 (clobber (match_scratch:SI 4 "=X,X,r"))]
6833 ""
6834 "*
6835 {
6836 if (which_alternative != 0)
6837 return \"#\";
6838 else if (get_attr_length (insn) == 8)
6839 return \"{bdn|bdnz} %l2\";
6840 else
6841 return \"bdz $+8\;b %l2\";
6842 }"
6843 [(set_attr "type" "branch")
6844 (set_attr "length" "*,12,16")])
6845
6846 ;; Similar, but we can use GE since we have a REG_NONNEG.
6847 (define_insn ""
6848 [(set (pc)
6849 (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
6850 (const_int 0))
6851 (label_ref (match_operand 2 "" ""))
6852 (pc)))
6853 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
6854 (plus:SI (match_dup 1) (const_int -1)))
6855 (clobber (match_scratch:CC 3 "=X,&x,&X"))
6856 (clobber (match_scratch:SI 4 "=X,X,r"))]
6857 "find_reg_note (insn, REG_NONNEG, 0)"
6858 "*
6859 {
6860 if (which_alternative != 0)
6861 return \"#\";
6862 else if (get_attr_length (insn) == 8)
6863 return \"{bdn|bdnz} %l2\";
6864 else
6865 return \"bdz $+8\;b %l2\";
6866 }"
6867 [(set_attr "type" "branch")
6868 (set_attr "length" "*,12,16")])
6869
6870 (define_insn ""
6871 [(set (pc)
6872 (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
6873 (const_int 1))
6874 (label_ref (match_operand 2 "" ""))
6875 (pc)))
6876 (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
6877 (plus:SI (match_dup 1) (const_int -1)))
6878 (clobber (match_scratch:CC 3 "=X,&x,&x"))
6879 (clobber (match_scratch:SI 4 "=X,X,r"))]
6880 ""
6881 "*
6882 {
6883 if (which_alternative != 0)
6884 return \"#\";
6885 else if (get_attr_length (insn) == 8)
6886 return \"bdz %l2\";
6887 else
6888 return \"{bdn|bdnz} $+8\;b %l2\";
6889 }"
6890 [(set_attr "type" "branch")
6891 (set_attr "length" "*,12,16")])
6892
6893 (define_split
6894 [(set (pc)
6895 (if_then_else (match_operator 2 "comparison_operator"
6896 [(match_operand:SI 1 "gpc_reg_operand" "")
6897 (const_int 1)])
6898 (match_operand 5 "" "")
6899 (match_operand 6 "" "")))
6900 (set (match_operand:SI 0 "gpc_reg_operand" "")
6901 (plus:SI (match_dup 1) (const_int -1)))
6902 (clobber (match_scratch:CC 3 ""))
6903 (clobber (match_scratch:SI 4 ""))]
6904 "reload_completed"
6905 [(parallel [(set (match_dup 3)
6906 (compare:CC (plus:SI (match_dup 1) (const_int -1))
6907 (const_int 0)))
6908 (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
6909 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
6910 "
6911 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
6912 const0_rtx); }")
6913
6914 (define_split
6915 [(set (pc)
6916 (if_then_else (match_operator 2 "comparison_operator"
6917 [(match_operand:SI 1 "gpc_reg_operand" "")
6918 (const_int 1)])
6919 (match_operand 5 "" "")
6920 (match_operand 6 "" "")))
6921 (set (match_operand:SI 0 "general_operand" "")
6922 (plus:SI (match_dup 1) (const_int -1)))
6923 (clobber (match_scratch:CC 3 ""))
6924 (clobber (match_scratch:SI 4 ""))]
6925 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
6926 [(parallel [(set (match_dup 3)
6927 (compare:CC (plus:SI (match_dup 1) (const_int -1))
6928 (const_int 0)))
6929 (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
6930 (set (match_dup 0) (match_dup 4))
6931 (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
6932 "
6933 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
6934 const0_rtx); }")
GNU Compiler Collection
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