1 ;; Machine description for IBM RISC System
6000 (POWER) for GNU C compiler
2 ;; Copyright (C)
1990,
91,
92,
93,
94,
95,
1996 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version
2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation,
59 Temple Place - Suite
330,
20 ;; Boston, MA
02111-
1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ;; Define an insn type attribute. This is used in function unit delay
26 (define_attr "type" "integer,load,fpload,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
27 (const_string "integer"))
30 (define_attr "length" ""
31 (if_then_else (eq_attr "type" "branch")
32 (if_then_else (and (ge (minus (pc) (match_dup
0))
34 (lt (minus (pc) (match_dup
0))
40 ;; Processor type -- this attribute must exactly match the processor_type
41 ;; enumeration in rs6000.h.
43 (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc602,ppc603,ppc604,ppc620"
44 (const (symbol_ref "rs6000_cpu_attr")))
46 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
47 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
49 ; Load/Store Unit -- POWER/
2 and pure PowerPC only
50 ; (POWER and
601 use Integer Unit)
51 (define_function_unit "lsu"
1 0
52 (and (eq_attr "type" "load")
53 (eq_attr "cpu" "mpccore,ppc602,ppc603,ppc604,ppc620"))
56 (define_function_unit "lsu"
1 0
57 (and (eq_attr "type" "fpload")
58 (eq_attr "cpu" "ppc604,ppc620"))
61 (define_function_unit "lsu"
1 0
62 (and (eq_attr "type" "fpload")
63 (eq_attr "cpu" "mpccore,ppc602,ppc603"))
66 (define_function_unit "iu"
1 0
67 (and (eq_attr "type" "load")
68 (eq_attr "cpu" "rios1,ppc601,ppc403"))
71 (define_function_unit "iu"
1 0
72 (and (eq_attr "type" "fpload")
73 (eq_attr "cpu" "rios1,ppc601"))
76 ; Integer Unit (RIOS1, PPC601, PPC603)
77 ; Trivial operations take one cycle which need not be listed here.
78 (define_function_unit "iu"
1 0
79 (and (eq_attr "type" "imul")
80 (eq_attr "cpu" "rios1"))
83 (define_function_unit "iu"
1 0
84 (and (eq_attr "type" "imul")
85 (eq_attr "cpu" "ppc403"))
88 (define_function_unit "iu"
1 0
89 (and (eq_attr "type" "imul")
90 (eq_attr "cpu" "ppc601,ppc602,ppc603"))
93 (define_function_unit "iu"
1 0
94 (and (eq_attr "type" "idiv")
95 (eq_attr "cpu" "rios1"))
98 (define_function_unit "iu"
1 0
99 (and (eq_attr "type" "idiv")
100 (eq_attr "cpu" "ppc601"))
103 (define_function_unit "iu"
1 0
104 (and (eq_attr "type" "idiv")
105 (eq_attr "cpu" "ppc403"))
108 (define_function_unit "iu"
1 0
109 (and (eq_attr "type" "idiv")
110 (eq_attr "cpu" "ppc602,ppc603"))
113 ; RIOS2 has two integer units: a primary one which can perform all
114 ; operations and a secondary one which is fed in lock step with the first
115 ; and can perform "simple" integer operations.
116 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
117 ; for the complex insns.
118 (define_function_unit "iu2"
2 0
119 (and (eq_attr "type" "integer")
120 (eq_attr "cpu" "rios2"))
123 (define_function_unit "iu2"
2 0
124 (and (eq_attr "type" "imul")
125 (eq_attr "cpu" "rios2"))
128 (define_function_unit "iu2"
2 0
129 (and (eq_attr "type" "idiv")
130 (eq_attr "cpu" "rios2"))
133 (define_function_unit "imuldiv"
1 0
134 (and (eq_attr "type" "imul")
135 (eq_attr "cpu" "rios2"))
139 (define_function_unit "imuldiv"
1 0
140 (and (eq_attr "type" "idiv")
141 (eq_attr "cpu" "rios2"))
144 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
145 ; Divide latency varies greatly from
2-
11, use
6 as average
146 (define_function_unit "imuldiv"
1 0
147 (and (eq_attr "type" "imul")
148 (eq_attr "cpu" "mpccore"))
151 (define_function_unit "imuldiv"
1 0
152 (and (eq_attr "type" "idiv")
153 (eq_attr "cpu" "mpccore"))
156 ; PPC604 has two units that perform integer operations
157 ; and one unit for divide/multiply operations (and move
159 (define_function_unit "iu2"
2 0
160 (and (eq_attr "type" "integer")
161 (eq_attr "cpu" "ppc604,ppc620"))
163 [(eq_attr "type" "imul,idiv")])
165 (define_function_unit "imuldiv"
1 0
166 (and (eq_attr "type" "imul")
167 (eq_attr "cpu" "ppc604,ppc620"))
169 [(eq_attr "type" "integer")])
171 (define_function_unit "imuldiv"
1 0
172 (and (eq_attr "type" "idiv")
173 (eq_attr "cpu" "ppc604,ppc620"))
175 [(eq_attr "type" "integer")])
177 ; compare is done on integer unit, but feeds insns which
178 ; execute on the branch unit. Ready-delay of the compare
179 ; on the branch unit is large (
3-
5 cycles). On the iu/fpu
180 ; it is
1. One drawback is that the compare will also be
181 ; assigned to the bpu, but this inaccuracy is worth for being
182 ; able to fill the compare-branch delay, with insns on iu/fpu.
183 (define_function_unit "iu"
1 0
184 (and (eq_attr "type" "compare")
185 (eq_attr "cpu" "rios1,mpccore,ppc601"))
188 (define_function_unit "iu2"
2 0
189 (and (eq_attr "type" "compare")
190 (eq_attr "cpu" "rios2"))
193 (define_function_unit "bpu"
1 0
194 (and (eq_attr "type" "compare")
195 (eq_attr "cpu" "rios1,rios2,ppc403,mpccore,ppc601,ppc603,ppc604,ppc620"))
198 ; different machines have different compare timings
199 ; in ppc604, compare is done on the one of the two
200 ; main integer units.
201 (define_function_unit "iu2"
2 0
202 (and (eq_attr "type" "compare")
203 (eq_attr "cpu" "ppc604,ppc620"))
206 (define_function_unit "bpu"
1 0
207 (eq_attr "type" "delayed_compare")
210 ; fp compare uses fp unit
211 (define_function_unit "fpu"
1 0
212 (and (eq_attr "type" "fpcompare")
213 (eq_attr "cpu" "rios1"))
216 ; rios1 and rios2 have different fpcompare delays
217 (define_function_unit "fpu2"
2 0
218 (and (eq_attr "type" "fpcompare")
219 (eq_attr "cpu" "rios2"))
222 ; on ppc601 and ppc603, fpcompare takes also
2 cycles from
224 ; here we do not define delays, just occupy the unit. The dependencies
225 ; will be signed by the fpcompare definition in the fpu.
226 (define_function_unit "iu"
1 0
227 (and (eq_attr "type" "fpcompare")
228 (eq_attr "cpu" "ppc601,ppc602,ppc603"))
231 ; fp compare uses fp unit
232 (define_function_unit "fpu"
1 0
233 (and (eq_attr "type" "fpcompare")
234 (eq_attr "cpu" "ppc601,ppc602,ppc603,ppc604,ppc620"))
237 (define_function_unit "fpu"
1 0
238 (and (eq_attr "type" "fpcompare")
239 (eq_attr "cpu" "mpccore"))
242 (define_function_unit "bpu"
1 0
243 (and (eq_attr "type" "mtjmpr")
244 (eq_attr "cpu" "rios1,rios2"))
247 (define_function_unit "bpu"
1 0
248 (and (eq_attr "type" "mtjmpr")
249 (eq_attr "cpu" "ppc403,mpccore,ppc601,ppc602,ppc603,ppc604,ppc620"))
252 ; all jumps/branches are executing on the bpu, in
1 cycle, for all machines.
253 (define_function_unit "bpu"
1 0
254 (eq_attr "type" "jmpreg")
257 (define_function_unit "bpu"
1 0
258 (eq_attr "type" "branch")
261 ; Floating Point Unit
262 (define_function_unit "fpu"
1 0
263 (and (eq_attr "type" "fp,dmul")
264 (eq_attr "cpu" "rios1"))
267 (define_function_unit "fpu"
1 0
268 (and (eq_attr "type" "fp")
269 (eq_attr "cpu" "mpccore"))
272 (define_function_unit "fpu"
1 0
273 (and (eq_attr "type" "fp")
274 (eq_attr "cpu" "ppc601"))
277 (define_function_unit "fpu"
1 0
278 (and (eq_attr "type" "fp")
279 (eq_attr "cpu" "ppc602,ppc603,ppc604,ppc620"))
282 (define_function_unit "fpu"
1 0
283 (and (eq_attr "type" "dmul")
284 (eq_attr "cpu" "mpccore"))
287 (define_function_unit "fpu"
1 0
288 (and (eq_attr "type" "dmul")
289 (eq_attr "cpu" "ppc601"))
293 (define_function_unit "fpu"
1 0
294 (and (eq_attr "type" "dmul")
295 (eq_attr "cpu" "ppc602,ppc603"))
298 (define_function_unit "fpu"
1 0
299 (and (eq_attr "type" "dmul")
300 (eq_attr "cpu" "ppc604,ppc620"))
303 (define_function_unit "fpu"
1 0
304 (and (eq_attr "type" "sdiv,ddiv")
305 (eq_attr "cpu" "rios1"))
308 (define_function_unit "fpu"
1 0
309 (and (eq_attr "type" "sdiv")
310 (eq_attr "cpu" "ppc601"))
313 (define_function_unit "fpu"
1 0
314 (and (eq_attr "type" "sdiv")
315 (eq_attr "cpu" "mpccore"))
318 (define_function_unit "fpu"
1 0
319 (and (eq_attr "type" "sdiv")
320 (eq_attr "cpu" "ppc602,ppc603,ppc604,ppc620"))
323 (define_function_unit "fpu"
1 0
324 (and (eq_attr "type" "ddiv")
325 (eq_attr "cpu" "mpccore"))
328 (define_function_unit "fpu"
1 0
329 (and (eq_attr "type" "ddiv")
330 (eq_attr "cpu" "ppc601,ppc604,ppc620"))
333 (define_function_unit "fpu"
1 0
334 (and (eq_attr "type" "ddiv")
335 (eq_attr "cpu" "ppc602,ppc603"))
338 (define_function_unit "fpu"
1 0
339 (and (eq_attr "type" "ssqrt")
340 (eq_attr "cpu" "ppc620"))
343 (define_function_unit "fpu"
1 0
344 (and (eq_attr "type" "dsqrt")
345 (eq_attr "cpu" "ppc620"))
348 ; RIOS2 has two symmetric FPUs.
349 (define_function_unit "fpu2"
2 0
350 (and (eq_attr "type" "fp")
351 (eq_attr "cpu" "rios2"))
354 (define_function_unit "fpu2"
2 0
355 (and (eq_attr "type" "dmul")
356 (eq_attr "cpu" "rios2"))
359 (define_function_unit "fpu2"
2 0
360 (and (eq_attr "type" "sdiv,ddiv")
361 (eq_attr "cpu" "rios2"))
364 (define_function_unit "fpu2"
2 0
365 (and (eq_attr "type" "ssqrt,dsqrt")
366 (eq_attr "cpu" "rios2"))
370 ;; Start with fixed-point load and store insns. Here we put only the more
371 ;; complex forms. Basic data transfer is done later.
373 (define_expand "zero_extendqidi2"
374 [(set (match_operand:DI
0 "gpc_reg_operand" "")
375 (zero_extend:DI (match_operand:QI
1 "gpc_reg_operand" "")))]
380 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
381 (zero_extend:DI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
386 [(set_attr "type" "load,*")])
389 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
390 (compare:CC (zero_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
392 (clobber (match_scratch:DI
2 "=r"))]
395 [(set_attr "type" "compare")])
398 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
399 (compare:CC (zero_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
401 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
402 (zero_extend:DI (match_dup
1)))]
405 [(set_attr "type" "compare")])
407 (define_insn "extendqidi2"
408 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
409 (sign_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r")))]
414 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
415 (compare:CC (sign_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
417 (clobber (match_scratch:DI
2 "=r"))]
420 [(set_attr "type" "compare")])
423 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
424 (compare:CC (sign_extend:DI (match_operand:QI
1 "gpc_reg_operand" "r"))
426 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
427 (sign_extend:DI (match_dup
1)))]
430 [(set_attr "type" "compare")])
432 (define_expand "zero_extendhidi2"
433 [(set (match_operand:DI
0 "gpc_reg_operand" "")
434 (zero_extend:DI (match_operand:HI
1 "gpc_reg_operand" "")))]
439 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
440 (zero_extend:DI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
445 [(set_attr "type" "load,*")])
448 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
449 (compare:CC (zero_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
451 (clobber (match_scratch:DI
2 "=r"))]
454 [(set_attr "type" "compare")])
457 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
458 (compare:CC (zero_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
460 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
461 (zero_extend:DI (match_dup
1)))]
464 [(set_attr "type" "compare")])
466 (define_expand "extendhidi2"
467 [(set (match_operand:DI
0 "gpc_reg_operand" "")
468 (sign_extend:DI (match_operand:HI
1 "gpc_reg_operand" "")))]
473 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
474 (sign_extend:DI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
479 [(set_attr "type" "load,*")])
482 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
483 (compare:CC (sign_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
485 (clobber (match_scratch:DI
2 "=r"))]
488 [(set_attr "type" "compare")])
491 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
492 (compare:CC (sign_extend:DI (match_operand:HI
1 "gpc_reg_operand" "r"))
494 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
495 (sign_extend:DI (match_dup
1)))]
498 [(set_attr "type" "compare")])
500 (define_expand "zero_extendsidi2"
501 [(set (match_operand:DI
0 "gpc_reg_operand" "")
502 (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "")))]
507 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
508 (zero_extend:DI (match_operand:SI
1 "reg_or_mem_operand" "m,r")))]
513 [(set_attr "type" "load,*")])
516 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
517 (compare:CC (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
519 (clobber (match_scratch:DI
2 "=r"))]
522 [(set_attr "type" "compare")])
525 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
526 (compare:CC (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
528 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
529 (zero_extend:DI (match_dup
1)))]
532 [(set_attr "type" "compare")])
534 (define_expand "extendsidi2"
535 [(set (match_operand:DI
0 "gpc_reg_operand" "")
536 (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "")))]
541 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
542 (sign_extend:DI (match_operand:SI
1 "lwa_operand" "m,r")))]
547 [(set_attr "type" "load,*")])
550 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
551 (compare:CC (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
553 (clobber (match_scratch:DI
2 "=r"))]
556 [(set_attr "type" "compare")])
559 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
560 (compare:CC (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
562 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
563 (sign_extend:DI (match_dup
1)))]
566 [(set_attr "type" "compare")])
568 (define_expand "zero_extendqisi2"
569 [(set (match_operand:SI
0 "gpc_reg_operand" "")
570 (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "")))]
575 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
576 (zero_extend:SI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
580 {rlinm|rlwinm} %
0,%
1,
0,
0xff"
581 [(set_attr "type" "load,*")])
584 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
585 (compare:CC (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
587 (clobber (match_scratch:SI
2 "=r"))]
589 "{andil.|andi.} %
2,%
1,
0xff"
590 [(set_attr "type" "compare")])
593 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
594 (compare:CC (zero_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
596 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
597 (zero_extend:SI (match_dup
1)))]
599 "{andil.|andi.} %
0,%
1,
0xff"
600 [(set_attr "type" "compare")])
602 (define_expand "extendqisi2"
603 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
604 (use (match_operand:QI
1 "gpc_reg_operand" ""))]
609 emit_insn (gen_extendqisi2_ppc (operands[
0], operands[
1]));
610 else if (TARGET_POWER)
611 emit_insn (gen_extendqisi2_power (operands[
0], operands[
1]));
613 emit_insn (gen_extendqisi2_no_power (operands[
0], operands[
1]));
617 (define_insn "extendqisi2_ppc"
618 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
619 (sign_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r")))]
624 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
625 (compare:CC (sign_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
627 (clobber (match_scratch:SI
2 "=r"))]
630 [(set_attr "type" "compare")])
633 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
634 (compare:CC (sign_extend:SI (match_operand:QI
1 "gpc_reg_operand" "r"))
636 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
637 (sign_extend:SI (match_dup
1)))]
640 [(set_attr "type" "compare")])
642 (define_expand "extendqisi2_power"
643 [(parallel [(set (match_dup
2)
644 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
646 (clobber (scratch:SI))])
647 (parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
648 (ashiftrt:SI (match_dup
2)
650 (clobber (scratch:SI))])]
653 { operands[
1] = gen_lowpart (SImode, operands[
1]);
654 operands[
2] = gen_reg_rtx (SImode); }")
656 (define_expand "extendqisi2_no_power"
658 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
660 (set (match_operand:SI
0 "gpc_reg_operand" "")
661 (ashiftrt:SI (match_dup
2)
663 "! TARGET_POWER && ! TARGET_POWERPC"
665 { operands[
1] = gen_lowpart (SImode, operands[
1]);
666 operands[
2] = gen_reg_rtx (SImode); }")
668 (define_expand "zero_extendqihi2"
669 [(set (match_operand:HI
0 "gpc_reg_operand" "")
670 (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "")))]
675 [(set (match_operand:HI
0 "gpc_reg_operand" "=r,r")
676 (zero_extend:HI (match_operand:QI
1 "reg_or_mem_operand" "m,r")))]
680 {rlinm|rlwinm} %
0,%
1,
0,
0xff"
681 [(set_attr "type" "load,*")])
684 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
685 (compare:CC (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
687 (clobber (match_scratch:HI
2 "=r"))]
689 "{andil.|andi.} %
2,%
1,
0xff"
690 [(set_attr "type" "compare")])
693 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
694 (compare:CC (zero_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
696 (set (match_operand:HI
0 "gpc_reg_operand" "=r")
697 (zero_extend:HI (match_dup
1)))]
699 "{andil.|andi.} %
0,%
1,
0xff"
700 [(set_attr "type" "compare")])
702 (define_expand "extendqihi2"
703 [(use (match_operand:HI
0 "gpc_reg_operand" ""))
704 (use (match_operand:QI
1 "gpc_reg_operand" ""))]
709 emit_insn (gen_extendqihi2_ppc (operands[
0], operands[
1]));
710 else if (TARGET_POWER)
711 emit_insn (gen_extendqihi2_power (operands[
0], operands[
1]));
713 emit_insn (gen_extendqihi2_no_power (operands[
0], operands[
1]));
717 (define_insn "extendqihi2_ppc"
718 [(set (match_operand:HI
0 "gpc_reg_operand" "=r")
719 (sign_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r")))]
724 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
725 (compare:CC (sign_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
727 (clobber (match_scratch:HI
2 "=r"))]
730 [(set_attr "type" "compare")])
733 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
734 (compare:CC (sign_extend:HI (match_operand:QI
1 "gpc_reg_operand" "r"))
736 (set (match_operand:HI
0 "gpc_reg_operand" "=r")
737 (sign_extend:HI (match_dup
1)))]
740 [(set_attr "type" "compare")])
742 (define_expand "extendqihi2_power"
743 [(parallel [(set (match_dup
2)
744 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
746 (clobber (scratch:SI))])
747 (parallel [(set (match_operand:HI
0 "gpc_reg_operand" "")
748 (ashiftrt:SI (match_dup
2)
750 (clobber (scratch:SI))])]
753 { operands[
0] = gen_lowpart (SImode, operands[
0]);
754 operands[
1] = gen_lowpart (SImode, operands[
1]);
755 operands[
2] = gen_reg_rtx (SImode); }")
757 (define_expand "extendqihi2_no_power"
759 (ashift:SI (match_operand:QI
1 "gpc_reg_operand" "")
761 (set (match_operand:HI
0 "gpc_reg_operand" "")
762 (ashiftrt:SI (match_dup
2)
764 "! TARGET_POWER && ! TARGET_POWERPC"
766 { operands[
0] = gen_lowpart (SImode, operands[
0]);
767 operands[
1] = gen_lowpart (SImode, operands[
1]);
768 operands[
2] = gen_reg_rtx (SImode); }")
770 (define_expand "zero_extendhisi2"
771 [(set (match_operand:SI
0 "gpc_reg_operand" "")
772 (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "")))]
777 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
778 (zero_extend:SI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
782 {rlinm|rlwinm} %
0,%
1,
0,
0xffff"
783 [(set_attr "type" "load,*")])
786 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
787 (compare:CC (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
789 (clobber (match_scratch:SI
2 "=r"))]
791 "{andil.|andi.} %
2,%
1,
0xffff"
792 [(set_attr "type" "compare")])
795 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
796 (compare:CC (zero_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
798 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
799 (zero_extend:SI (match_dup
1)))]
801 "{andil.|andi.} %
0,%
1,
0xffff"
802 [(set_attr "type" "compare")])
804 (define_expand "extendhisi2"
805 [(set (match_operand:SI
0 "gpc_reg_operand" "")
806 (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "")))]
811 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
812 (sign_extend:SI (match_operand:HI
1 "reg_or_mem_operand" "m,r")))]
817 [(set_attr "type" "load,*")])
820 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
821 (compare:CC (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
823 (clobber (match_scratch:SI
2 "=r"))]
825 "{exts.|extsh.} %
2,%
1"
826 [(set_attr "type" "compare")])
829 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
830 (compare:CC (sign_extend:SI (match_operand:HI
1 "gpc_reg_operand" "r"))
832 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
833 (sign_extend:SI (match_dup
1)))]
835 "{exts.|extsh.} %
0,%
1"
836 [(set_attr "type" "compare")])
838 ;; Fixed-point arithmetic insns.
840 ;; Discourage ai/addic because of carry but provide it in an alternative
841 ;; allowing register zero as source.
842 (define_insn "addsi3"
843 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,?r,r")
844 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,b,r,b")
845 (match_operand:SI
2 "add_operand" "r,I,I,J")))]
849 {cal %
0,%
2(%
1)|addi %
0,%
1,%
2}
851 {cau|addis} %
0,%
1,%u2")
854 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
855 (compare:CC (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
856 (match_operand:SI
2 "reg_or_short_operand" "r,I"))
858 (clobber (match_scratch:SI
3 "=r,r"))]
862 {ai.|addic.} %
3,%
1,%
2"
863 [(set_attr "type" "compare")])
866 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
867 (compare:CC (plus:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
868 (match_operand:SI
2 "reg_or_short_operand" "r,I"))
870 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
871 (plus:SI (match_dup
1) (match_dup
2)))]
875 {ai.|addic.} %
0,%
1,%
2"
876 [(set_attr "type" "compare")])
878 ;; Split an add that we can't do in one insn into two insns, each of which
879 ;; does one
16-bit part. This is used by combine. Note that the low-order
880 ;; add should be last in case the result gets used in an address.
883 [(set (match_operand:SI
0 "gpc_reg_operand" "")
884 (plus:SI (match_operand:SI
1 "gpc_reg_operand" "")
885 (match_operand:SI
2 "non_add_cint_operand" "")))]
887 [(set (match_dup
0) (plus:SI (match_dup
1) (match_dup
3)))
888 (set (match_dup
0) (plus:SI (match_dup
0) (match_dup
4)))]
891 HOST_WIDE_INT low = INTVAL (operands[
2]) &
0xffff;
892 HOST_WIDE_INT high = INTVAL (operands[
2]) & (~ (HOST_WIDE_INT)
0xffff);
895 high +=
0x10000, low |= ((HOST_WIDE_INT) -
1) <<
16;
897 operands[
3] = GEN_INT (high);
898 operands[
4] = GEN_INT (low);
901 (define_insn "one_cmplsi2"
902 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
903 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
908 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
909 (compare:CC (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
911 (clobber (match_scratch:SI
2 "=r"))]
914 [(set_attr "type" "compare")])
917 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
918 (compare:CC (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
920 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
921 (not:SI (match_dup
1)))]
924 [(set_attr "type" "compare")])
927 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
928 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "rI")
929 (match_operand:SI
2 "gpc_reg_operand" "r")))]
931 "{sf%I1|subf%I1c} %
0,%
2,%
1")
934 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
935 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "r,I")
936 (match_operand:SI
2 "gpc_reg_operand" "r,r")))]
943 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
944 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
945 (match_operand:SI
2 "gpc_reg_operand" "r"))
947 (clobber (match_scratch:SI
3 "=r"))]
949 "{sf.|subfc.} %
3,%
2,%
1"
950 [(set_attr "type" "compare")])
953 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
954 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
955 (match_operand:SI
2 "gpc_reg_operand" "r"))
957 (clobber (match_scratch:SI
3 "=r"))]
960 [(set_attr "type" "compare")])
963 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
964 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
965 (match_operand:SI
2 "gpc_reg_operand" "r"))
967 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
968 (minus:SI (match_dup
1) (match_dup
2)))]
970 "{sf.|subfc.} %
0,%
2,%
1"
971 [(set_attr "type" "compare")])
974 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
975 (compare:CC (minus:SI (match_operand:SI
1 "gpc_reg_operand" "r")
976 (match_operand:SI
2 "gpc_reg_operand" "r"))
978 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
979 (minus:SI (match_dup
1) (match_dup
2)))]
982 [(set_attr "type" "compare")])
984 (define_expand "subsi3"
985 [(set (match_operand:SI
0 "gpc_reg_operand" "")
986 (minus:SI (match_operand:SI
1 "reg_or_short_operand" "")
987 (match_operand:SI
2 "reg_or_cint_operand" "")))]
991 if (GET_CODE (operands[
2]) == CONST_INT)
993 emit_insn (gen_addsi3 (operands[
0], operands[
1],
994 negate_rtx (SImode, operands[
2])));
999 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1000 ;; instruction and some auxiliary computations. Then we just have a single
1001 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1004 (define_expand "sminsi3"
1006 (if_then_else:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "")
1007 (match_operand:SI
2 "reg_or_short_operand" ""))
1009 (minus:SI (match_dup
2) (match_dup
1))))
1010 (set (match_operand:SI
0 "gpc_reg_operand" "")
1011 (minus:SI (match_dup
2) (match_dup
3)))]
1014 { operands[
3] = gen_reg_rtx (SImode); }")
1017 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1018 (smin:SI (match_operand:SI
1 "gpc_reg_operand" "")
1019 (match_operand:SI
2 "reg_or_short_operand" "")))
1020 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
1023 (if_then_else:SI (gt:SI (match_dup
1) (match_dup
2))
1025 (minus:SI (match_dup
2) (match_dup
1))))
1026 (set (match_dup
0) (minus:SI (match_dup
2) (match_dup
3)))]
1029 (define_expand "smaxsi3"
1031 (if_then_else:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "")
1032 (match_operand:SI
2 "reg_or_short_operand" ""))
1034 (minus:SI (match_dup
2) (match_dup
1))))
1035 (set (match_operand:SI
0 "gpc_reg_operand" "")
1036 (plus:SI (match_dup
3) (match_dup
1)))]
1039 { operands[
3] = gen_reg_rtx (SImode); }")
1042 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1043 (smax:SI (match_operand:SI
1 "gpc_reg_operand" "")
1044 (match_operand:SI
2 "reg_or_short_operand" "")))
1045 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
1048 (if_then_else:SI (gt:SI (match_dup
1) (match_dup
2))
1050 (minus:SI (match_dup
2) (match_dup
1))))
1051 (set (match_dup
0) (plus:SI (match_dup
3) (match_dup
1)))]
1054 (define_expand "uminsi3"
1055 [(set (match_dup
3) (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1057 (set (match_dup
4) (xor:SI (match_operand:SI
2 "gpc_reg_operand" "")
1059 (set (match_dup
3) (if_then_else:SI (gt (match_dup
3) (match_dup
4))
1061 (minus:SI (match_dup
4) (match_dup
3))))
1062 (set (match_operand:SI
0 "gpc_reg_operand" "")
1063 (minus:SI (match_dup
2) (match_dup
3)))]
1067 operands[
3] = gen_reg_rtx (SImode);
1068 operands[
4] = gen_reg_rtx (SImode);
1069 operands[
5] = GEN_INT (-
2147483647 -
1);
1072 (define_expand "umaxsi3"
1073 [(set (match_dup
3) (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1075 (set (match_dup
4) (xor:SI (match_operand:SI
2 "gpc_reg_operand" "")
1077 (set (match_dup
3) (if_then_else:SI (gt (match_dup
3) (match_dup
4))
1079 (minus:SI (match_dup
4) (match_dup
3))))
1080 (set (match_operand:SI
0 "gpc_reg_operand" "")
1081 (plus:SI (match_dup
3) (match_dup
1)))]
1085 operands[
3] = gen_reg_rtx (SImode);
1086 operands[
4] = gen_reg_rtx (SImode);
1087 operands[
5] = GEN_INT (-
2147483647 -
1);
1091 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1092 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
1093 (match_operand:SI
2 "reg_or_short_operand" "rI"))
1095 (minus:SI (match_dup
2) (match_dup
1))))]
1100 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1102 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
1103 (match_operand:SI
2 "reg_or_short_operand" "rI"))
1105 (minus:SI (match_dup
2) (match_dup
1)))
1107 (clobber (match_scratch:SI
3 "=r"))]
1110 [(set_attr "type" "delayed_compare")])
1113 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1115 (if_then_else:SI (gt (match_operand:SI
1 "gpc_reg_operand" "r")
1116 (match_operand:SI
2 "reg_or_short_operand" "rI"))
1118 (minus:SI (match_dup
2) (match_dup
1)))
1120 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1121 (if_then_else:SI (gt (match_dup
1) (match_dup
2))
1123 (minus:SI (match_dup
2) (match_dup
1))))]
1126 [(set_attr "type" "delayed_compare")])
1128 ;; We don't need abs with condition code because such comparisons should
1130 (define_expand "abssi2"
1131 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1132 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "")))]
1138 emit_insn (gen_abssi2_nopower (operands[
0], operands[
1]));
1143 (define_insn "abssi2_power"
1144 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1145 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
1149 (define_insn "abssi2_nopower"
1150 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1151 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0")))
1152 (clobber (match_scratch:SI
2 "=&r,&r"))]
1156 return (TARGET_POWERPC)
1157 ?
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
2,%
0\"
1158 :
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;{sf|subfc} %
0,%
2,%
0\";
1160 [(set_attr "length" "
12")])
1163 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1164 (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0")))
1165 (clobber (match_scratch:SI
2 "=&r,&r"))]
1166 "!TARGET_POWER && reload_completed"
1167 [(set (match_dup
2) (ashiftrt:SI (match_dup
1) (const_int
31)))
1168 (set (match_dup
0) (xor:SI (match_dup
2) (match_dup
1)))
1169 (set (match_dup
0) (minus:SI (match_dup
2) (match_dup
0)))]
1173 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1174 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r"))))]
1179 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1180 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0"))))
1181 (clobber (match_scratch:SI
2 "=&r,&r"))]
1185 return (TARGET_POWERPC)
1186 ?
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
0,%
2\"
1187 :
\"{srai|srawi} %
2,%
1,
31\;xor %
0,%
2,%
1\;{sf|subfc} %
0,%
0,%
2\";
1189 [(set_attr "length" "
12")])
1192 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r,r")
1193 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r,
0"))))
1194 (clobber (match_scratch:SI
2 "=&r,&r"))]
1195 "!TARGET_POWER && reload_completed"
1196 [(set (match_dup
2) (ashiftrt:SI (match_dup
1) (const_int
31)))
1197 (set (match_dup
0) (xor:SI (match_dup
2) (match_dup
1)))
1198 (set (match_dup
0) (minus:SI (match_dup
0) (match_dup
2)))]
1201 (define_insn "negsi2"
1202 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1203 (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
1208 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1209 (compare:CC (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1211 (clobber (match_scratch:SI
2 "=r"))]
1214 [(set_attr "type" "compare")])
1217 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
1218 (compare:CC (neg:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1220 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1221 (neg:SI (match_dup
1)))]
1224 [(set_attr "type" "compare")])
1226 (define_insn "ffssi2"
1227 [(set (match_operand:SI
0 "gpc_reg_operand" "=&r")
1228 (ffs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))]
1230 "neg %
0,%
1\;and %
0,%
0,%
1\;{cntlz|cntlzw} %
0,%
0\;{sfi|subfic} %
0,%
0,
32"
1231 [(set_attr "length" "
16")])
1233 (define_expand "mulsi3"
1234 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
1235 (use (match_operand:SI
1 "gpc_reg_operand" ""))
1236 (use (match_operand:SI
2 "reg_or_short_operand" ""))]
1241 emit_insn (gen_mulsi3_mq (operands[
0], operands[
1], operands[
2]));
1243 emit_insn (gen_mulsi3_no_mq (operands[
0], operands[
1], operands[
2]));
1247 (define_insn "mulsi3_mq"
1248 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1249 (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
1250 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
1251 (clobber (match_scratch:SI
3 "=q,q"))]
1254 {muls|mullw} %
0,%
1,%
2
1255 {muli|mulli} %
0,%
1,%
2"
1256 [(set_attr "type" "imul")])
1258 (define_insn "mulsi3_no_mq"
1259 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
1260 (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r")
1261 (match_operand:SI
2 "reg_or_short_operand" "r,I")))]
1264 {muls|mullw} %
0,%
1,%
2
1265 {muli|mulli} %
0,%
1,%
2"
1266 [(set_attr "type" "imul")])
1269 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1270 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1271 (match_operand:SI
2 "gpc_reg_operand" "r"))
1273 (clobber (match_scratch:SI
3 "=r"))
1274 (clobber (match_scratch:SI
4 "=q"))]
1276 "{muls.|mullw.} %
3,%
1,%
2"
1277 [(set_attr "type" "delayed_compare")])
1280 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1281 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1282 (match_operand:SI
2 "gpc_reg_operand" "r"))
1284 (clobber (match_scratch:SI
3 "=r"))]
1286 "{muls.|mullw.} %
3,%
1,%
2"
1287 [(set_attr "type" "delayed_compare")])
1290 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1291 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1292 (match_operand:SI
2 "gpc_reg_operand" "r"))
1294 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1295 (mult:SI (match_dup
1) (match_dup
2)))
1296 (clobber (match_scratch:SI
4 "=q"))]
1298 "{muls.|mullw.} %
0,%
1,%
2"
1299 [(set_attr "type" "delayed_compare")])
1302 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1303 (compare:CC (mult:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1304 (match_operand:SI
2 "gpc_reg_operand" "r"))
1306 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1307 (mult:SI (match_dup
1) (match_dup
2)))]
1309 "{muls.|mullw.} %
0,%
1,%
2"
1310 [(set_attr "type" "delayed_compare")])
1312 ;; Operand
1 is divided by operand
2; quotient goes to operand
1313 ;;
0 and remainder to operand
3.
1314 ;; ??? At some point, see what, if anything, we can do about if (x % y ==
0).
1316 (define_expand "divmodsi4"
1317 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
1318 (div:SI (match_operand:SI
1 "gpc_reg_operand" "")
1319 (match_operand:SI
2 "gpc_reg_operand" "")))
1320 (set (match_operand:SI
3 "gpc_reg_operand" "")
1321 (mod:SI (match_dup
1) (match_dup
2)))])]
1322 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
1325 if (! TARGET_POWER && ! TARGET_POWERPC)
1327 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1328 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1329 emit_insn (gen_divss_call ());
1330 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1331 emit_move_insn (operands[
3], gen_rtx (REG, SImode,
4));
1337 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1338 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1339 (match_operand:SI
2 "gpc_reg_operand" "r")))
1340 (set (match_operand:SI
3 "gpc_reg_operand" "=q")
1341 (mod:SI (match_dup
1) (match_dup
2)))]
1344 [(set_attr "type" "idiv")])
1347 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1348 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1349 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1352 [(set_attr "type" "idiv")])
1354 (define_expand "udivsi3"
1355 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1356 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "")
1357 (match_operand:SI
2 "gpc_reg_operand" "")))]
1358 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
1361 if (! TARGET_POWER && ! TARGET_POWERPC)
1363 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1364 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1365 emit_insn (gen_quous_call ());
1366 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1372 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1373 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1374 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1377 [(set_attr "type" "idiv")])
1379 ;; For powers of two we can do srai/aze for divide and then adjust for
1380 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
1381 ;; used; for PowerPC, force operands into register and do a normal divide;
1382 ;; for AIX common-mode, use quoss call on register operands.
1383 (define_expand "divsi3"
1384 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1385 (div:SI (match_operand:SI
1 "gpc_reg_operand" "")
1386 (match_operand:SI
2 "reg_or_cint_operand" "")))]
1390 if (GET_CODE (operands[
2]) == CONST_INT
1391 && exact_log2 (INTVAL (operands[
2])) >=
0)
1393 else if (TARGET_POWERPC)
1394 operands[
2] = force_reg (SImode, operands[
2]);
1395 else if (TARGET_POWER)
1399 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1400 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1401 emit_insn (gen_quoss_call ());
1402 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1407 (define_expand "modsi3"
1408 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
1409 (use (match_operand:SI
1 "gpc_reg_operand" ""))
1410 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
1414 int i = exact_log2 (INTVAL (operands[
2]));
1418 if (GET_CODE (operands[
2]) != CONST_INT || i <
0)
1421 temp1 = gen_reg_rtx (SImode);
1422 temp2 = gen_reg_rtx (SImode);
1424 emit_insn (gen_divsi3 (temp1, operands[
1], operands[
2]));
1425 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
1426 emit_insn (gen_subsi3 (operands[
0], operands[
1], temp2));
1431 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1432 (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1433 (match_operand:SI
2 "const_int_operand" "N")))]
1434 "exact_log2 (INTVAL (operands[
2])) >=
0"
1435 "{srai|srawi} %
0,%
1,%p2\;{aze|addze} %
0,%
0"
1436 [(set_attr "length" "
8")])
1439 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1440 (compare:CC (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1441 (match_operand:SI
2 "const_int_operand" "N"))
1443 (clobber (match_scratch:SI
3 "=r"))]
1444 "exact_log2 (INTVAL (operands[
2])) >=
0"
1445 "{srai|srawi} %
3,%
1,%p2\;{aze.|addze.} %
3,%
3"
1446 [(set_attr "type" "compare")
1447 (set_attr "length" "
8")])
1450 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1451 (compare:CC (div:SI (match_operand:SI
1 "gpc_reg_operand" "r")
1452 (match_operand:SI
2 "const_int_operand" "N"))
1454 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1455 (div:SI (match_dup
1) (match_dup
2)))]
1456 "exact_log2 (INTVAL (operands[
2])) >=
0"
1457 "{srai|srawi} %
0,%
1,%p2\;{aze.|addze.} %
0,%
0"
1458 [(set_attr "type" "compare")
1459 (set_attr "length" "
8")])
1462 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1465 (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "r"))
1467 (zero_extend:DI (match_operand:SI
4 "register_operand" "
2")))
1468 (match_operand:SI
3 "gpc_reg_operand" "r")))
1469 (set (match_operand:SI
2 "register_operand" "=*q")
1472 (zero_extend:DI (match_dup
1)) (const_int
32))
1473 (zero_extend:DI (match_dup
4)))
1477 [(set_attr "type" "idiv")])
1479 ;; To do unsigned divide we handle the cases of the divisor looking like a
1480 ;; negative number. If it is a constant that is less than
2**
31, we don't
1481 ;; have to worry about the branches. So make a few subroutines here.
1483 ;; First comes the normal case.
1484 (define_expand "udivmodsi4_normal"
1485 [(set (match_dup
4) (const_int
0))
1486 (parallel [(set (match_operand:SI
0 "" "")
1487 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup
4))
1489 (zero_extend:DI (match_operand:SI
1 "" "")))
1490 (match_operand:SI
2 "" "")))
1491 (set (match_operand:SI
3 "" "")
1492 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup
4))
1494 (zero_extend:DI (match_dup
1)))
1498 { operands[
4] = gen_reg_rtx (SImode); }")
1500 ;; This handles the branches.
1501 (define_expand "udivmodsi4_tests"
1502 [(set (match_operand:SI
0 "" "") (const_int
0))
1503 (set (match_operand:SI
3 "" "") (match_operand:SI
1 "" ""))
1504 (set (match_dup
5) (compare:CCUNS (match_dup
1) (match_operand:SI
2 "" "")))
1505 (set (pc) (if_then_else (ltu (match_dup
5) (const_int
0))
1506 (label_ref (match_operand:SI
4 "" "")) (pc)))
1507 (set (match_dup
0) (const_int
1))
1508 (set (match_dup
3) (minus:SI (match_dup
1) (match_dup
2)))
1509 (set (match_dup
6) (compare:CC (match_dup
2) (const_int
0)))
1510 (set (pc) (if_then_else (lt (match_dup
6) (const_int
0))
1511 (label_ref (match_dup
4)) (pc)))]
1514 { operands[
5] = gen_reg_rtx (CCUNSmode);
1515 operands[
6] = gen_reg_rtx (CCmode);
1518 (define_expand "udivmodsi4"
1519 [(parallel [(set (match_operand:SI
0 "gpc_reg_operand" "")
1520 (udiv:SI (match_operand:SI
1 "gpc_reg_operand" "")
1521 (match_operand:SI
2 "reg_or_cint_operand" "")))
1522 (set (match_operand:SI
3 "gpc_reg_operand" "")
1523 (umod:SI (match_dup
1) (match_dup
2)))])]
1530 if (! TARGET_POWERPC)
1532 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
1533 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
1534 emit_insn (gen_divus_call ());
1535 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
1536 emit_move_insn (operands[
3], gen_rtx (REG, SImode,
4));
1542 if (GET_CODE (operands[
2]) != CONST_INT || INTVAL (operands[
2]) <
0)
1544 operands[
2] = force_reg (SImode, operands[
2]);
1545 label = gen_label_rtx ();
1546 emit (gen_udivmodsi4_tests (operands[
0], operands[
1], operands[
2],
1547 operands[
3], label));
1550 operands[
2] = force_reg (SImode, operands[
2]);
1552 emit (gen_udivmodsi4_normal (operands[
0], operands[
1], operands[
2],
1560 ;; AIX architecture-independent common-mode multiply (DImode),
1561 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
1562 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
1563 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
1564 ;; assumed unused if generating common-mode, so ignore.
1565 (define_insn "mulh_call"
1568 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI
3))
1569 (sign_extend:DI (reg:SI
4)))
1571 (clobber (match_scratch:SI
0 "=l"))]
1572 "! TARGET_POWER && ! TARGET_POWERPC"
1575 (define_insn "mull_call"
1577 (mult:DI (sign_extend:DI (reg:SI
3))
1578 (sign_extend:DI (reg:SI
4))))
1579 (clobber (match_scratch:SI
0 "=l"))
1580 (clobber (reg:SI
0))]
1581 "! TARGET_POWER && ! TARGET_POWERPC"
1584 (define_insn "divss_call"
1586 (div:SI (reg:SI
3) (reg:SI
4)))
1588 (mod:SI (reg:SI
3) (reg:SI
4)))
1589 (clobber (match_scratch:SI
0 "=l"))
1590 (clobber (reg:SI
0))]
1591 "! TARGET_POWER && ! TARGET_POWERPC"
1594 (define_insn "divus_call"
1596 (udiv:SI (reg:SI
3) (reg:SI
4)))
1598 (umod:SI (reg:SI
3) (reg:SI
4)))
1599 (clobber (match_scratch:SI
0 "=l"))
1600 (clobber (reg:SI
0))
1601 (clobber (match_scratch:CC
1 "=x"))
1602 (clobber (reg:CC
69))]
1603 "! TARGET_POWER && ! TARGET_POWERPC"
1606 (define_insn "quoss_call"
1608 (div:SI (reg:SI
3) (reg:SI
4)))
1609 (clobber (match_scratch:SI
0 "=l"))]
1610 "! TARGET_POWER && ! TARGET_POWERPC"
1613 (define_insn "quous_call"
1615 (udiv:SI (reg:SI
3) (reg:SI
4)))
1616 (clobber (match_scratch:SI
0 "=l"))
1617 (clobber (reg:SI
0))
1618 (clobber (match_scratch:CC
1 "=x"))
1619 (clobber (reg:CC
69))]
1620 "! TARGET_POWER && ! TARGET_POWERPC"
1623 (define_insn "andsi3"
1624 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
1625 (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
1626 (match_operand:SI
2 "and_operand" "?r,L,K,J")))
1627 (clobber (match_scratch:CC
3 "=X,X,x,x"))]
1631 {rlinm|rlwinm} %
0,%
1,
0,%m2,%M2
1632 {andil.|andi.} %
0,%
1,%b2
1633 {andiu.|andis.} %
0,%
1,%u2")
1636 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x,x")
1637 (compare:CC (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
1638 (match_operand:SI
2 "and_operand" "r,K,J,L"))
1640 (clobber (match_scratch:SI
3 "=r,r,r,r"))]
1644 {andil.|andi.} %
3,%
1,%b2
1645 {andiu.|andis.} %
3,%
1,%u2
1646 {rlinm.|rlwinm.} %
3,%
1,
0,%m2,%M2"
1647 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1650 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x,x,x")
1651 (compare:CC (and:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r")
1652 (match_operand:SI
2 "and_operand" "r,K,J,L"))
1654 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
1655 (and:SI (match_dup
1) (match_dup
2)))]
1659 {andil.|andi.} %
0,%
1,%b2
1660 {andiu.|andis.} %
0,%
1,%u2
1661 {rlinm.|rlwinm.} %
0,%
1,
0,%m2,%M2"
1662 [(set_attr "type" "compare,compare,compare,delayed_compare")])
1664 ;; Take a AND with a constant that cannot be done in a single insn and try to
1665 ;; split it into two insns. This does not verify that the insns are valid
1666 ;; since this need not be done as combine will do it.
1669 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1670 (and:SI (match_operand:SI
1 "gpc_reg_operand" "")
1671 (match_operand:SI
2 "non_and_cint_operand" "")))]
1673 [(set (match_dup
0) (and:SI (match_dup
1) (match_dup
3)))
1674 (set (match_dup
0) (and:SI (match_dup
0) (match_dup
4)))]
1677 int maskval = INTVAL (operands[
2]);
1678 int i, transitions, last_bit_value;
1679 int orig = maskval, first_c = maskval, second_c;
1681 /* We know that MASKVAL must have more than
2 bit-transitions. Start at
1682 the low-order bit and count for the third transition. When we get there,
1683 make a first mask that has everything to the left of that position
1684 a one. Then make the second mask to turn off whatever else is needed. */
1686 for (i =
1, transitions =
0, last_bit_value = maskval &
1; i <
32; i++)
1688 if (((maskval >>=
1) &
1) != last_bit_value)
1689 last_bit_value ^=
1, transitions++;
1691 if (transitions >
2)
1693 first_c |= (~
0) << i;
1698 second_c = orig | ~ first_c;
1700 operands[
3] = gen_rtx (CONST_INT, VOIDmode, first_c);
1701 operands[
4] = gen_rtx (CONST_INT, VOIDmode, second_c);
1704 (define_insn "iorsi3"
1705 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
1706 (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r")
1707 (match_operand:SI
2 "logical_operand" "r,K,J")))]
1711 {oril|ori} %
0,%
1,%b2
1712 {oriu|oris} %
0,%
1,%u2")
1715 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1716 (compare:CC (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1717 (match_operand:SI
2 "gpc_reg_operand" "r"))
1719 (clobber (match_scratch:SI
3 "=r"))]
1722 [(set_attr "type" "compare")])
1725 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1726 (compare:CC (ior:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1727 (match_operand:SI
2 "gpc_reg_operand" "r"))
1729 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1730 (ior:SI (match_dup
1) (match_dup
2)))]
1733 [(set_attr "type" "compare")])
1735 ;; Split an IOR that we can't do in one insn into two insns, each of which
1736 ;; does one
16-bit part. This is used by combine.
1739 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1740 (ior:SI (match_operand:SI
1 "gpc_reg_operand" "")
1741 (match_operand:SI
2 "non_logical_cint_operand" "")))]
1743 [(set (match_dup
0) (ior:SI (match_dup
1) (match_dup
3)))
1744 (set (match_dup
0) (ior:SI (match_dup
0) (match_dup
4)))]
1747 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
1748 INTVAL (operands[
2]) &
0xffff0000);
1749 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1752 (define_insn "xorsi3"
1753 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
1754 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r")
1755 (match_operand:SI
2 "logical_operand" "r,K,J")))]
1759 {xoril|xori} %
0,%
1,%b2
1760 {xoriu|xoris} %
0,%
1,%u2")
1763 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1764 (compare:CC (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1765 (match_operand:SI
2 "gpc_reg_operand" "r"))
1767 (clobber (match_scratch:SI
3 "=r"))]
1770 [(set_attr "type" "compare")])
1773 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1774 (compare:CC (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1775 (match_operand:SI
2 "gpc_reg_operand" "r"))
1777 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1778 (xor:SI (match_dup
1) (match_dup
2)))]
1781 [(set_attr "type" "compare")])
1783 ;; Split an XOR that we can't do in one insn into two insns, each of which
1784 ;; does one
16-bit part. This is used by combine.
1787 [(set (match_operand:SI
0 "gpc_reg_operand" "")
1788 (xor:SI (match_operand:SI
1 "gpc_reg_operand" "")
1789 (match_operand:SI
2 "non_logical_cint_operand" "")))]
1791 [(set (match_dup
0) (xor:SI (match_dup
1) (match_dup
3)))
1792 (set (match_dup
0) (xor:SI (match_dup
0) (match_dup
4)))]
1795 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
1796 INTVAL (operands[
2]) &
0xffff0000);
1797 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
1801 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1802 (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1803 (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1808 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1809 (compare:CC (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1810 (match_operand:SI
2 "gpc_reg_operand" "r")))
1812 (clobber (match_scratch:SI
3 "=r"))]
1815 [(set_attr "type" "compare")])
1818 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1819 (compare:CC (not:SI (xor:SI (match_operand:SI
1 "gpc_reg_operand" "%r")
1820 (match_operand:SI
2 "gpc_reg_operand" "r")))
1822 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1823 (not:SI (xor:SI (match_dup
1) (match_dup
2))))]
1826 [(set_attr "type" "compare")])
1829 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1830 (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1831 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1836 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1837 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1838 (match_operand:SI
2 "gpc_reg_operand" "r"))
1840 (clobber (match_scratch:SI
3 "=r"))]
1843 [(set_attr "type" "compare")])
1846 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1847 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1848 (match_operand:SI
2 "gpc_reg_operand" "r"))
1850 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1851 (and:SI (not:SI (match_dup
1)) (match_dup
2)))]
1854 [(set_attr "type" "compare")])
1857 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1858 (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1859 (match_operand:SI
2 "gpc_reg_operand" "r")))]
1864 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1865 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1866 (match_operand:SI
2 "gpc_reg_operand" "r"))
1868 (clobber (match_scratch:SI
3 "=r"))]
1871 [(set_attr "type" "compare")])
1874 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1875 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
1876 (match_operand:SI
2 "gpc_reg_operand" "r"))
1878 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1879 (ior:SI (not:SI (match_dup
1)) (match_dup
2)))]
1882 [(set_attr "type" "compare")])
1885 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1886 (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1887 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1892 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1893 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1894 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1896 (clobber (match_scratch:SI
3 "=r"))]
1899 [(set_attr "type" "compare")])
1902 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1903 (compare:CC (ior:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1904 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1906 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1907 (ior:SI (not:SI (match_dup
1)) (not:SI (match_dup
2))))]
1910 [(set_attr "type" "compare")])
1913 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1914 (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1915 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
1920 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
1921 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1922 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1924 (clobber (match_scratch:SI
3 "=r"))]
1927 [(set_attr "type" "compare")])
1930 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
1931 (compare:CC (and:SI (not:SI (match_operand:SI
1 "gpc_reg_operand" "%r"))
1932 (not:SI (match_operand:SI
2 "gpc_reg_operand" "r")))
1934 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1935 (and:SI (not:SI (match_dup
1)) (not:SI (match_dup
2))))]
1938 [(set_attr "type" "compare")])
1940 ;; maskir insn. We need four forms because things might be in arbitrary
1941 ;; orders. Don't define forms that only set CR fields because these
1942 ;; would modify an input register.
1945 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1946 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1947 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1948 (and:SI (match_dup
2)
1949 (match_operand:SI
3 "gpc_reg_operand" "r"))))]
1954 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1955 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1956 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1957 (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1963 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1964 (ior:SI (and:SI (match_operand:SI
2 "gpc_reg_operand" "r")
1965 (match_operand:SI
3 "gpc_reg_operand" "r"))
1966 (and:SI (not:SI (match_dup
2))
1967 (match_operand:SI
1 "gpc_reg_operand" "
0"))))]
1972 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
1973 (ior:SI (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
1974 (match_operand:SI
2 "gpc_reg_operand" "r"))
1975 (and:SI (not:SI (match_dup
2))
1976 (match_operand:SI
1 "gpc_reg_operand" "
0"))))]
1981 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1983 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1984 (match_operand:SI
1 "gpc_reg_operand" "
0"))
1985 (and:SI (match_dup
2)
1986 (match_operand:SI
3 "gpc_reg_operand" "r")))
1988 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
1989 (ior:SI (and:SI (not:SI (match_dup
2)) (match_dup
1))
1990 (and:SI (match_dup
2) (match_dup
3))))]
1993 [(set_attr "type" "compare")])
1996 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
1998 (ior:SI (and:SI (not:SI (match_operand:SI
2 "gpc_reg_operand" "r"))
1999 (match_operand:SI
1 "gpc_reg_operand" "
0"))
2000 (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2003 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2004 (ior:SI (and:SI (not:SI (match_dup
2)) (match_dup
1))
2005 (and:SI (match_dup
3) (match_dup
2))))]
2008 [(set_attr "type" "compare")])
2011 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2013 (ior:SI (and:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2014 (match_operand:SI
3 "gpc_reg_operand" "r"))
2015 (and:SI (not:SI (match_dup
2))
2016 (match_operand:SI
1 "gpc_reg_operand" "
0")))
2018 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2019 (ior:SI (and:SI (match_dup
2) (match_dup
3))
2020 (and:SI (not:SI (match_dup
2)) (match_dup
1))))]
2023 [(set_attr "type" "compare")])
2026 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2028 (ior:SI (and:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2029 (match_operand:SI
2 "gpc_reg_operand" "r"))
2030 (and:SI (not:SI (match_dup
2))
2031 (match_operand:SI
1 "gpc_reg_operand" "
0")))
2033 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2034 (ior:SI (and:SI (match_dup
3) (match_dup
2))
2035 (and:SI (not:SI (match_dup
2)) (match_dup
1))))]
2038 [(set_attr "type" "compare")])
2040 ;; Rotate and shift insns, in all their variants. These support shifts,
2041 ;; field inserts and extracts, and various combinations thereof.
2042 (define_expand "insv"
2043 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2044 (match_operand:SI
1 "const_int_operand" "i")
2045 (match_operand:SI
2 "const_int_operand" "i"))
2046 (match_operand:SI
3 "gpc_reg_operand" "r"))]
2050 /* Do not handle
16/
8 bit structures that fit in HI/QI modes directly, since
2051 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2052 compiler if the address of the structure is taken later. */
2053 if (GET_CODE (operands[
0]) == SUBREG
2054 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[
0]))) < UNITS_PER_WORD))
2059 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2060 (match_operand:SI
1 "const_int_operand" "i")
2061 (match_operand:SI
2 "const_int_operand" "i"))
2062 (match_operand:SI
3 "gpc_reg_operand" "r"))]
2066 int start = INTVAL (operands[
2]) &
31;
2067 int size = INTVAL (operands[
1]) &
31;
2069 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - start - size);
2070 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2071 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2075 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2076 (match_operand:SI
1 "const_int_operand" "i")
2077 (match_operand:SI
2 "const_int_operand" "i"))
2078 (ashift:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2079 (match_operand:SI
4 "const_int_operand" "i")))]
2083 int shift = INTVAL (operands[
4]) &
31;
2084 int start = INTVAL (operands[
2]) &
31;
2085 int size = INTVAL (operands[
1]) &
31;
2087 operands[
4] = gen_rtx (CONST_INT, VOIDmode, shift - start - size);
2088 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2089 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2093 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2094 (match_operand:SI
1 "const_int_operand" "i")
2095 (match_operand:SI
2 "const_int_operand" "i"))
2096 (ashiftrt:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2097 (match_operand:SI
4 "const_int_operand" "i")))]
2101 int shift = INTVAL (operands[
4]) &
31;
2102 int start = INTVAL (operands[
2]) &
31;
2103 int size = INTVAL (operands[
1]) &
31;
2105 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - shift - start - size);
2106 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2107 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2111 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2112 (match_operand:SI
1 "const_int_operand" "i")
2113 (match_operand:SI
2 "const_int_operand" "i"))
2114 (lshiftrt:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2115 (match_operand:SI
4 "const_int_operand" "i")))]
2119 int shift = INTVAL (operands[
4]) &
31;
2120 int start = INTVAL (operands[
2]) &
31;
2121 int size = INTVAL (operands[
1]) &
31;
2123 operands[
4] = gen_rtx (CONST_INT, VOIDmode,
32 - shift - start - size);
2124 operands[
1] = gen_rtx (CONST_INT, VOIDmode, start + size -
1);
2125 return
\"{rlimi|rlwimi} %
0,%
3,%h4,%h2,%h1
\";
2129 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2130 (match_operand:SI
1 "const_int_operand" "i")
2131 (match_operand:SI
2 "const_int_operand" "i"))
2132 (zero_extract:SI (match_operand:SI
3 "gpc_reg_operand" "r")
2133 (match_operand:SI
4 "const_int_operand" "i")
2134 (match_operand:SI
5 "const_int_operand" "i")))]
2135 "INTVAL (operands[
4]) >= INTVAL (operands[
1])"
2138 int extract_start = INTVAL (operands[
5]) &
31;
2139 int extract_size = INTVAL (operands[
4]) &
31;
2140 int insert_start = INTVAL (operands[
2]) &
31;
2141 int insert_size = INTVAL (operands[
1]) &
31;
2143 /* Align extract field with insert field */
2144 operands[
5] = gen_rtx (CONST_INT, VOIDmode,
2145 extract_start + extract_size - insert_start - insert_size);
2146 operands[
1] = gen_rtx (CONST_INT, VOIDmode, insert_start + insert_size -
1);
2147 return
\"{rlimi|rlwimi} %
0,%
3,%h5,%h2,%h1
\";
2151 [(set (zero_extract:DI (match_operand:DI
0 "gpc_reg_operand" "+r")
2152 (match_operand:DI
1 "const_int_operand" "i")
2153 (match_operand:DI
2 "const_int_operand" "i"))
2154 (match_operand:DI
3 "gpc_reg_operand" "r"))]
2158 int start = INTVAL (operands[
2]) &
63;
2159 int size = INTVAL (operands[
1]) &
63;
2161 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - start - size);
2162 return
\"rldimi %
0,%
3,%H2,%H1
\";
2165 (define_expand "extzv"
2166 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2167 (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2168 (match_operand:SI
2 "const_int_operand" "i")
2169 (match_operand:SI
3 "const_int_operand" "i")))]
2173 /* Do not handle
16/
8 bit structures that fit in HI/QI modes directly, since
2174 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
2175 compiler if the address of the structure is taken later. */
2176 if (GET_CODE (operands[
0]) == SUBREG
2177 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[
0]))) < UNITS_PER_WORD))
2182 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2183 (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2184 (match_operand:SI
2 "const_int_operand" "i")
2185 (match_operand:SI
3 "const_int_operand" "i")))]
2189 int start = INTVAL (operands[
3]) &
31;
2190 int size = INTVAL (operands[
2]) &
31;
2192 if (start + size >=
32)
2193 operands[
3] = const0_rtx;
2195 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2196 return
\"{rlinm|rlwinm} %
0,%
1,%
3,%s2,
31\";
2200 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2201 (compare:CC (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2202 (match_operand:SI
2 "const_int_operand" "i")
2203 (match_operand:SI
3 "const_int_operand" "i"))
2205 (clobber (match_scratch:SI
4 "=r"))]
2209 int start = INTVAL (operands[
3]) &
31;
2210 int size = INTVAL (operands[
2]) &
31;
2212 /* If the bitfield being tested fits in the upper or lower half of a
2213 word, it is possible to use andiu. or andil. to test it. This is
2214 useful because the condition register set-use delay is smaller for
2215 andi[ul]. than for rlinm. This doesn't work when the starting bit
2216 position is
0 because the LT and GT bits may be set wrong. */
2218 if ((start >
0 && start + size <=
16) || start >=
16)
2220 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
2221 ((
1 << (
16 - (start &
15)))
2222 - (
1 << (
16 - (start &
15) - size))));
2224 return
\"{andiu.|andis.} %
4,%
1,%
3\";
2226 return
\"{andil.|andi.} %
4,%
1,%
3\";
2229 if (start + size >=
32)
2230 operands[
3] = const0_rtx;
2232 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2233 return
\"{rlinm.|rlwinm.} %
4,%
1,%
3,%s2,
31\";
2235 [(set_attr "type" "compare")])
2238 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2239 (compare:CC (zero_extract:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2240 (match_operand:SI
2 "const_int_operand" "i")
2241 (match_operand:SI
3 "const_int_operand" "i"))
2243 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2244 (zero_extract:SI (match_dup
1) (match_dup
2) (match_dup
3)))]
2248 int start = INTVAL (operands[
3]) &
31;
2249 int size = INTVAL (operands[
2]) &
31;
2251 if (start >=
16 && start + size ==
32)
2253 operands[
3] = gen_rtx (CONST_INT, VOIDmode, (
1 << (
32 - start)) -
1);
2254 return
\"{andil.|andi.} %
0,%
1,%
3\";
2257 if (start + size >=
32)
2258 operands[
3] = const0_rtx;
2260 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2261 return
\"{rlinm.|rlwinm.} %
0,%
1,%
3,%s2,
31\";
2263 [(set_attr "type" "delayed_compare")])
2266 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
2267 (zero_extract:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2268 (match_operand:DI
2 "const_int_operand" "i")
2269 (match_operand:DI
3 "const_int_operand" "i")))]
2273 int start = INTVAL (operands[
3]) &
63;
2274 int size = INTVAL (operands[
2]) &
63;
2276 if (start + size >=
64)
2277 operands[
3] = const0_rtx;
2279 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2280 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - size);
2281 return
\"rldicl %
0,%
1,%
3,%
2\";
2285 [(set (match_operand:CC
0 "gpc_reg_operand" "=x")
2286 (compare:CC (zero_extract:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2287 (match_operand:DI
2 "const_int_operand" "i")
2288 (match_operand:DI
3 "const_int_operand" "i"))
2290 (clobber (match_scratch:DI
4 "=r"))]
2294 int start = INTVAL (operands[
3]) &
63;
2295 int size = INTVAL (operands[
2]) &
63;
2297 if (start + size >=
64)
2298 operands[
3] = const0_rtx;
2300 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2301 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - size);
2302 return
\"rldicl. %
4,%
1,%
3,%
2\";
2306 [(set (match_operand:CC
4 "gpc_reg_operand" "=x")
2307 (compare:CC (zero_extract:DI (match_operand:DI
1 "gpc_reg_operand" "r")
2308 (match_operand:DI
2 "const_int_operand" "i")
2309 (match_operand:DI
3 "const_int_operand" "i"))
2311 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
2312 (zero_extract:DI (match_dup
1) (match_dup
2) (match_dup
3)))]
2316 int start = INTVAL (operands[
3]) &
63;
2317 int size = INTVAL (operands[
2]) &
63;
2319 if (start + size >=
64)
2320 operands[
3] = const0_rtx;
2322 operands[
3] = gen_rtx (CONST_INT, VOIDmode, start + size);
2323 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
64 - size);
2324 return
\"rldicl. %
0,%
1,%
3,%
2\";
2327 (define_insn "rotlsi3"
2328 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2329 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2330 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2332 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xffffffff")
2335 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2336 (compare:CC (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2337 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2339 (clobber (match_scratch:SI
3 "=r"))]
2341 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xffffffff"
2342 [(set_attr "type" "delayed_compare")])
2345 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2346 (compare:CC (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2347 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2349 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2350 (rotate:SI (match_dup
1) (match_dup
2)))]
2352 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xffffffff"
2353 [(set_attr "type" "delayed_compare")])
2356 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2357 (and:SI (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2358 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2359 (match_operand:SI
3 "mask_operand" "L")))]
2361 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,%m3,%M3")
2364 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2366 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2367 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2368 (match_operand:SI
3 "mask_operand" "L"))
2370 (clobber (match_scratch:SI
4 "=r"))]
2372 "{rl%I2nm.|rlw%I2nm.} %
4,%
1,%h2,%m3,%M3"
2373 [(set_attr "type" "delayed_compare")])
2376 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2378 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2379 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2380 (match_operand:SI
3 "mask_operand" "L"))
2382 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2383 (and:SI (rotate:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
2385 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,%m3,%M3"
2386 [(set_attr "type" "delayed_compare")])
2389 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2392 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2393 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0)))]
2395 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xff")
2398 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2399 (compare:CC (zero_extend:SI
2401 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2402 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2404 (clobber (match_scratch:SI
3 "=r"))]
2406 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xff"
2407 [(set_attr "type" "delayed_compare")])
2410 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2411 (compare:CC (zero_extend:SI
2413 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2414 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2416 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2417 (zero_extend:SI (subreg:QI (rotate:SI (match_dup
1) (match_dup
2))
0)))]
2419 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xff"
2420 [(set_attr "type" "delayed_compare")])
2423 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2426 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2427 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0)))]
2429 "{rl%I2nm|rlw%I2nm} %
0,%
1,%h2,
0xffff")
2432 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2433 (compare:CC (zero_extend:SI
2435 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2436 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2438 (clobber (match_scratch:SI
3 "=r"))]
2440 "{rl%I2nm.|rlw%I2nm.} %
3,%
1,%h2,
0xffff"
2441 [(set_attr "type" "delayed_compare")])
2444 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2445 (compare:CC (zero_extend:SI
2447 (rotate:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2448 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
0))
2450 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2451 (zero_extend:SI (subreg:HI (rotate:SI (match_dup
1) (match_dup
2))
0)))]
2453 "{rl%I2nm.|rlw%I2nm.} %
0,%
1,%h2,
0xffff"
2454 [(set_attr "type" "delayed_compare")])
2456 ;; Note that we use "sle." instead of "sl." so that we can set
2457 ;; SHIFT_COUNT_TRUNCATED.
2459 (define_expand "ashlsi3"
2460 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
2461 (use (match_operand:SI
1 "gpc_reg_operand" ""))
2462 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
2467 emit_insn (gen_ashlsi3_power (operands[
0], operands[
1], operands[
2]));
2469 emit_insn (gen_ashlsi3_no_power (operands[
0], operands[
1], operands[
2]));
2473 (define_insn "ashlsi3_power"
2474 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2475 (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2476 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
2477 (clobber (match_scratch:SI
3 "=q,X"))]
2481 {sli|slwi} %
0,%
1,%h2"
2482 [(set_attr "length" "
8")])
2484 (define_insn "ashlsi3_no_power"
2485 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2486 (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2487 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2489 "{sl|slw}%I2 %
0,%
1,%h2"
2490 [(set_attr "length" "
8")])
2493 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
2494 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2495 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2497 (clobber (match_scratch:SI
3 "=r,r"))
2498 (clobber (match_scratch:SI
4 "=q,X"))]
2502 {sli.|slwi.} %
3,%
1,%h2"
2503 [(set_attr "type" "delayed_compare")])
2506 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2507 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2508 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2510 (clobber (match_scratch:SI
3 "=r"))]
2512 "{sl|slw}%I2. %
3,%
1,%h2"
2513 [(set_attr "type" "delayed_compare")])
2516 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
2517 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2518 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2520 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2521 (ashift:SI (match_dup
1) (match_dup
2)))
2522 (clobber (match_scratch:SI
4 "=q,X"))]
2526 {sli.|slwi.} %
0,%
1,%h2"
2527 [(set_attr "type" "delayed_compare")])
2530 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2531 (compare:CC (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2532 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2534 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2535 (ashift:SI (match_dup
1) (match_dup
2)))]
2537 "{sl|slw}%I2. %
0,%
1,%h2"
2538 [(set_attr "type" "delayed_compare")])
2541 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2542 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2543 (match_operand:SI
2 "const_int_operand" "i"))
2544 (match_operand:SI
3 "mask_operand" "L")))]
2545 "includes_lshift_p (operands[
2], operands[
3])"
2546 "{rlinm|rlwinm} %
0,%
1,%h2,%m3,%M3")
2549 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2551 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2552 (match_operand:SI
2 "const_int_operand" "i"))
2553 (match_operand:SI
3 "mask_operand" "L"))
2555 (clobber (match_scratch:SI
4 "=r"))]
2556 "includes_lshift_p (operands[
2], operands[
3])"
2557 "{rlinm.|rlwinm.} %
4,%
1,%h2,%m3,%M3"
2558 [(set_attr "type" "delayed_compare")])
2561 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2563 (and:SI (ashift:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2564 (match_operand:SI
2 "const_int_operand" "i"))
2565 (match_operand:SI
3 "mask_operand" "L"))
2567 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2568 (and:SI (ashift:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
2569 "includes_lshift_p (operands[
2], operands[
3])"
2570 "{rlinm.|rlwinm.} %
0,%
1,%h2,%m3,%M3"
2571 [(set_attr "type" "delayed_compare")])
2573 ;; The AIX assembler mis-handles "sri x,x,
0", so write that case as
2575 (define_expand "lshrsi3"
2576 [(use (match_operand:SI
0 "gpc_reg_operand" ""))
2577 (use (match_operand:SI
1 "gpc_reg_operand" ""))
2578 (use (match_operand:SI
2 "reg_or_cint_operand" ""))]
2583 emit_insn (gen_lshrsi3_power (operands[
0], operands[
1], operands[
2]));
2585 emit_insn (gen_lshrsi3_no_power (operands[
0], operands[
1], operands[
2]));
2589 (define_insn "lshrsi3_power"
2590 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2591 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2592 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
2593 (clobber (match_scratch:SI
3 "=q,X"))]
2597 {s%A2i|s%A2wi} %
0,%
1,%h2")
2599 (define_insn "lshrsi3_no_power"
2600 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2601 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2602 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2604 "{sr|srw}%I2 %
0,%
1,%h2")
2607 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
2608 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2609 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2611 (clobber (match_scratch:SI
3 "=r,r"))
2612 (clobber (match_scratch:SI
4 "=q,X"))]
2616 {s%A2i.|s%A2wi.} %
3,%
1,%h2"
2617 [(set_attr "type" "delayed_compare")])
2620 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2621 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2622 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2624 (clobber (match_scratch:SI
3 "=r"))]
2626 "{sr|srw}%I2. %
3,%
1,%h2"
2627 [(set_attr "type" "delayed_compare")])
2630 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
2631 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2632 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2634 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2635 (lshiftrt:SI (match_dup
1) (match_dup
2)))
2636 (clobber (match_scratch:SI
4 "=q,X"))]
2640 {s%A2i.|s%A2wi.} %
0,%
1,%h2"
2641 [(set_attr "type" "delayed_compare")])
2644 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2645 (compare:CC (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2646 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2648 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2649 (lshiftrt:SI (match_dup
1) (match_dup
2)))]
2651 "{sr|srw}%I2. %
0,%
1,%h2"
2652 [(set_attr "type" "delayed_compare")])
2655 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2656 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2657 (match_operand:SI
2 "const_int_operand" "i"))
2658 (match_operand:SI
3 "mask_operand" "L")))]
2659 "includes_rshift_p (operands[
2], operands[
3])"
2660 "{rlinm|rlwinm} %
0,%
1,%s2,%m3,%M3")
2663 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2665 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2666 (match_operand:SI
2 "const_int_operand" "i"))
2667 (match_operand:SI
3 "mask_operand" "L"))
2669 (clobber (match_scratch:SI
4 "=r"))]
2670 "includes_rshift_p (operands[
2], operands[
3])"
2671 "{rlinm.|rlwinm.} %
4,%
1,%s2,%m3,%M3"
2672 [(set_attr "type" "delayed_compare")])
2675 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
2677 (and:SI (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2678 (match_operand:SI
2 "const_int_operand" "i"))
2679 (match_operand:SI
3 "mask_operand" "L"))
2681 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2682 (and:SI (lshiftrt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))]
2683 "includes_rshift_p (operands[
2], operands[
3])"
2684 "{rlinm.|rlwinm.} %
0,%
1,%s2,%m3,%M3"
2685 [(set_attr "type" "delayed_compare")])
2688 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2691 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2692 (match_operand:SI
2 "const_int_operand" "i"))
0)))]
2693 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
2694 "{rlinm|rlwinm} %
0,%
1,%s2,
0xff")
2697 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2701 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2702 (match_operand:SI
2 "const_int_operand" "i"))
0))
2704 (clobber (match_scratch:SI
3 "=r"))]
2705 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
2706 "{rlinm.|rlwinm.} %
3,%
1,%s2,
0xff"
2707 [(set_attr "type" "delayed_compare")])
2710 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2714 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2715 (match_operand:SI
2 "const_int_operand" "i"))
0))
2717 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2718 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup
1) (match_dup
2))
0)))]
2719 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
255))"
2720 "{rlinm.|rlwinm.} %
0,%
1,%s2,
0xff"
2721 [(set_attr "type" "delayed_compare")])
2724 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2727 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2728 (match_operand:SI
2 "const_int_operand" "i"))
0)))]
2729 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
2730 "{rlinm|rlwinm} %
0,%
1,%s2,
0xffff")
2733 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2737 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2738 (match_operand:SI
2 "const_int_operand" "i"))
0))
2740 (clobber (match_scratch:SI
3 "=r"))]
2741 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
2742 "{rlinm.|rlwinm.} %
3,%
1,%s2,
0xffff"
2743 [(set_attr "type" "delayed_compare")])
2746 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2750 (lshiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2751 (match_operand:SI
2 "const_int_operand" "i"))
0))
2753 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2754 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup
1) (match_dup
2))
0)))]
2755 "includes_rshift_p (operands[
2], gen_rtx (CONST_INT, VOIDmode,
65535))"
2756 "{rlinm.|rlwinm.} %
0,%
1,%s2,
0xffff"
2757 [(set_attr "type" "delayed_compare")])
2760 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2762 (match_operand:SI
1 "gpc_reg_operand" "r"))
2763 (ashiftrt:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2769 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2771 (match_operand:SI
1 "gpc_reg_operand" "r"))
2772 (lshiftrt:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2778 [(set (zero_extract:SI (match_operand:SI
0 "gpc_reg_operand" "+r")
2780 (match_operand:SI
1 "gpc_reg_operand" "r"))
2781 (zero_extract:SI (match_operand:SI
2 "gpc_reg_operand" "r")
2787 (define_expand "ashrsi3"
2788 [(set (match_operand:SI
0 "gpc_reg_operand" "")
2789 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "")
2790 (match_operand:SI
2 "reg_or_cint_operand" "")))]
2795 emit_insn (gen_ashrsi3_power (operands[
0], operands[
1], operands[
2]));
2797 emit_insn (gen_ashrsi3_no_power (operands[
0], operands[
1], operands[
2]));
2801 (define_insn "ashrsi3_power"
2802 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2803 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2804 (match_operand:SI
2 "reg_or_cint_operand" "r,i")))
2805 (clobber (match_scratch:SI
3 "=q,X"))]
2809 {srai|srawi} %
0,%
1,%h2")
2811 (define_insn "ashrsi3_no_power"
2812 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
2813 (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2814 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
2816 "{sra|sraw}%I2 %
0,%
1,%h2")
2819 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
2820 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2821 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2823 (clobber (match_scratch:SI
3 "=r,r"))
2824 (clobber (match_scratch:SI
4 "=q,X"))]
2828 {srai.|srawi.} %
3,%
1,%h2"
2829 [(set_attr "type" "delayed_compare")])
2832 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
2833 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2834 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2836 (clobber (match_scratch:SI
3 "=r"))]
2838 "{sra|sraw}%I2. %
3,%
1,%h2"
2839 [(set_attr "type" "delayed_compare")])
2842 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
2843 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
2844 (match_operand:SI
2 "reg_or_cint_operand" "r,i"))
2846 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
2847 (ashiftrt:SI (match_dup
1) (match_dup
2)))
2848 (clobber (match_scratch:SI
4 "=q,X"))]
2852 {srai.|srawi.} %
0,%
1,%h2"
2853 [(set_attr "type" "delayed_compare")])
2856 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
2857 (compare:CC (ashiftrt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
2858 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
2860 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
2861 (ashiftrt:SI (match_dup
1) (match_dup
2)))]
2863 "{sra|sraw}%I2. %
0,%
1,%h2"
2864 [(set_attr "type" "delayed_compare")])
2866 ;; Floating-point insns, excluding normal data motion.
2868 ;; PowerPC has a full set of single-precision floating point instructions.
2870 ;; For the POWER architecture, we pretend that we have both SFmode and
2871 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
2872 ;; The only conversions we will do will be when storing to memory. In that
2873 ;; case, we will use the "frsp" instruction before storing.
2875 ;; Note that when we store into a single-precision memory location, we need to
2876 ;; use the frsp insn first. If the register being stored isn't dead, we
2877 ;; need a scratch register for the frsp. But this is difficult when the store
2878 ;; is done by reload. It is not incorrect to do the frsp on the register in
2879 ;; this case, we just lose precision that we would have otherwise gotten but
2880 ;; is not guaranteed. Perhaps this should be tightened up at some point.
2882 (define_insn "extendsfdf2"
2883 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
2884 (float_extend:DF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2888 if (REGNO (operands[
0]) == REGNO (operands[
1]))
2891 return
\"fmr %
0,%
1\";
2893 [(set_attr "type" "fp")])
2895 (define_insn "truncdfsf2"
2896 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2897 (float_truncate:SF (match_operand:DF
1 "gpc_reg_operand" "f")))]
2900 [(set_attr "type" "fp")])
2902 (define_insn "aux_truncdfsf2"
2903 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2904 (unspec:SF [(match_operand:SF
1 "gpc_reg_operand" "f")]
0))]
2905 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2907 [(set_attr "type" "fp")])
2909 (define_insn "negsf2"
2910 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2911 (neg:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2914 [(set_attr "type" "fp")])
2916 (define_insn "abssf2"
2917 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2918 (abs:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
2921 [(set_attr "type" "fp")])
2924 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2925 (neg:SF (abs:SF (match_operand:SF
1 "gpc_reg_operand" "f"))))]
2928 [(set_attr "type" "fp")])
2930 (define_expand "addsf3"
2931 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2932 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "")
2933 (match_operand:SF
2 "gpc_reg_operand" "")))]
2938 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2939 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2940 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2941 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2943 [(set_attr "type" "fp")])
2946 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2947 (plus:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2948 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2949 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2950 "{fa|fadd} %
0,%
1,%
2"
2951 [(set_attr "type" "fp")])
2953 (define_expand "subsf3"
2954 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2955 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "")
2956 (match_operand:SF
2 "gpc_reg_operand" "")))]
2961 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2962 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "f")
2963 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2964 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2966 [(set_attr "type" "fp")])
2969 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2970 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "f")
2971 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2972 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2973 "{fs|fsub} %
0,%
1,%
2"
2974 [(set_attr "type" "fp")])
2976 (define_expand "mulsf3"
2977 [(set (match_operand:SF
0 "gpc_reg_operand" "")
2978 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "")
2979 (match_operand:SF
2 "gpc_reg_operand" "")))]
2984 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2985 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2986 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2987 "TARGET_POWERPC && TARGET_HARD_FLOAT"
2989 [(set_attr "type" "fp")])
2992 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
2993 (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
2994 (match_operand:SF
2 "gpc_reg_operand" "f")))]
2995 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
2996 "{fm|fmul} %
0,%
1,%
2"
2997 [(set_attr "type" "dmul")])
2999 (define_expand "divsf3"
3000 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3001 (div:SF (match_operand:SF
1 "gpc_reg_operand" "")
3002 (match_operand:SF
2 "gpc_reg_operand" "")))]
3007 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3008 (div:SF (match_operand:SF
1 "gpc_reg_operand" "f")
3009 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3010 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3012 [(set_attr "type" "sdiv")])
3015 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3016 (div:SF (match_operand:SF
1 "gpc_reg_operand" "f")
3017 (match_operand:SF
2 "gpc_reg_operand" "f")))]
3018 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3019 "{fd|fdiv} %
0,%
1,%
2"
3020 [(set_attr "type" "ddiv")])
3023 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3024 (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3025 (match_operand:SF
2 "gpc_reg_operand" "f"))
3026 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3027 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3028 "fmadds %
0,%
1,%
2,%
3"
3029 [(set_attr "type" "fp")])
3032 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3033 (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3034 (match_operand:SF
2 "gpc_reg_operand" "f"))
3035 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3036 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3037 "{fma|fmadd} %
0,%
1,%
2,%
3"
3038 [(set_attr "type" "dmul")])
3041 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3042 (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3043 (match_operand:SF
2 "gpc_reg_operand" "f"))
3044 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3045 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3046 "fmsubs %
0,%
1,%
2,%
3"
3047 [(set_attr "type" "fp")])
3050 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3051 (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3052 (match_operand:SF
2 "gpc_reg_operand" "f"))
3053 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3054 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3055 "{fms|fmsub} %
0,%
1,%
2,%
3"
3056 [(set_attr "type" "dmul")])
3059 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3060 (neg:SF (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3061 (match_operand:SF
2 "gpc_reg_operand" "f"))
3062 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3063 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3064 "fnmadds %
0,%
1,%
2,%
3"
3065 [(set_attr "type" "fp")])
3068 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3069 (neg:SF (plus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3070 (match_operand:SF
2 "gpc_reg_operand" "f"))
3071 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3072 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3073 "{fnma|fnmadd} %
0,%
1,%
2,%
3"
3074 [(set_attr "type" "dmul")])
3077 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3078 (neg:SF (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3079 (match_operand:SF
2 "gpc_reg_operand" "f"))
3080 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3081 "TARGET_POWERPC && TARGET_HARD_FLOAT"
3082 "fnmsubs %
0,%
1,%
2,%
3"
3083 [(set_attr "type" "fp")])
3086 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3087 (neg:SF (minus:SF (mult:SF (match_operand:SF
1 "gpc_reg_operand" "%f")
3088 (match_operand:SF
2 "gpc_reg_operand" "f"))
3089 (match_operand:SF
3 "gpc_reg_operand" "f"))))]
3090 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
3091 "{fnms|fnmsub} %
0,%
1,%
2,%
3"
3092 [(set_attr "type" "dmul")])
3094 (define_expand "sqrtsf2"
3095 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3096 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "")))]
3097 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3101 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3102 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
3103 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
3105 [(set_attr "type" "ssqrt")])
3108 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3109 (sqrt:SF (match_operand:SF
1 "gpc_reg_operand" "f")))]
3110 "TARGET_POWER2 && TARGET_HARD_FLOAT"
3112 [(set_attr "type" "dsqrt")])
3114 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3115 ;; fsel instruction and some auxiliary computations. Then we just have a
3116 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3118 (define_expand "maxsf3"
3120 (minus:SF (match_operand:SF
1 "gpc_reg_operand" "")
3121 (match_operand:SF
2 "gpc_reg_operand" "")))
3122 (set (match_operand:SF
0 "gpc_reg_operand" "")
3123 (if_then_else:SF (ge (match_dup
3)
3127 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3129 { operands[
3] = gen_reg_rtx (SFmode); }")
3132 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3133 (smax:SF (match_operand:SF
1 "gpc_reg_operand" "")
3134 (match_operand:SF
2 "gpc_reg_operand" "")))
3135 (clobber (match_operand:SF
3 "gpc_reg_operand" ""))]
3136 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3138 (minus:SF (match_dup
1) (match_dup
2)))
3140 (if_then_else:SF (ge (match_dup
3)
3146 (define_expand "minsf3"
3148 (minus:SF (match_operand:SF
2 "gpc_reg_operand" "")
3149 (match_operand:SF
1 "gpc_reg_operand" "")))
3150 (set (match_operand:SF
0 "gpc_reg_operand" "")
3151 (if_then_else:SF (ge (match_dup
3)
3155 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3157 { operands[
3] = gen_reg_rtx (SFmode); }")
3160 [(set (match_operand:SF
0 "gpc_reg_operand" "")
3161 (smin:SF (match_operand:SF
1 "gpc_reg_operand" "")
3162 (match_operand:SF
2 "gpc_reg_operand" "")))
3163 (clobber (match_operand:SF
3 "gpc_reg_operand" ""))]
3164 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3166 (minus:SF (match_dup
2) (match_dup
1)))
3168 (if_then_else:SF (ge (match_dup
3)
3174 (define_expand "movsfcc"
3175 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3176 (if_then_else:SF (match_operand
1 "comparison_operator" "")
3177 (match_operand:SF
2 "gpc_reg_operand" "f")
3178 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3179 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3183 enum rtx_code code = GET_CODE (operands[
1]);
3184 if (! rs6000_compare_fp_p)
3188 case GE: case EQ: case NE:
3189 op0 = rs6000_compare_op0;
3190 op1 = rs6000_compare_op1;
3193 op0 = rs6000_compare_op1;
3194 op1 = rs6000_compare_op0;
3195 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3198 op0 = rs6000_compare_op1;
3199 op1 = rs6000_compare_op0;
3202 op0 = rs6000_compare_op0;
3203 op1 = rs6000_compare_op1;
3204 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3209 if (GET_MODE (rs6000_compare_op0) == DFmode)
3211 temp = gen_reg_rtx (DFmode);
3212 emit_insn (gen_subdf3 (temp, op0, op1));
3213 emit_insn (gen_fseldfsf4 (operands[
0], temp, operands[
2], operands[
3]));
3216 emit_insn (gen_negdf2 (temp, temp));
3217 emit_insn (gen_fseldfsf4 (operands[
0], temp, operands[
0], operands[
3]));
3221 emit_insn (gen_negdf2 (temp, temp));
3222 emit_insn (gen_fseldfsf4 (operands[
0], temp, operands[
3], operands[
0]));
3227 temp = gen_reg_rtx (SFmode);
3228 emit_insn (gen_subsf3 (temp, op0, op1));
3229 emit_insn (gen_fselsfsf4 (operands[
0], temp, operands[
2], operands[
3]));
3232 emit_insn (gen_negsf2 (temp, temp));
3233 emit_insn (gen_fselsfsf4 (operands[
0], temp, operands[
0], operands[
3]));
3237 emit_insn (gen_negsf2 (temp, temp));
3238 emit_insn (gen_fselsfsf4 (operands[
0], temp, operands[
3], operands[
0]));
3244 (define_insn "fselsfsf4"
3245 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3246 (if_then_else:SF (ge (match_operand:SF
1 "gpc_reg_operand" "f")
3248 (match_operand:SF
2 "gpc_reg_operand" "f")
3249 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3250 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3252 [(set_attr "type" "fp")])
3254 (define_insn "fseldfsf4"
3255 [(set (match_operand:SF
0 "gpc_reg_operand" "=f")
3256 (if_then_else:SF (ge (match_operand:DF
1 "gpc_reg_operand" "f")
3258 (match_operand:SF
2 "gpc_reg_operand" "f")
3259 (match_operand:SF
3 "gpc_reg_operand" "f")))]
3260 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3262 [(set_attr "type" "fp")])
3264 (define_insn "negdf2"
3265 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3266 (neg:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
3269 [(set_attr "type" "fp")])
3271 (define_insn "absdf2"
3272 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3273 (abs:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
3276 [(set_attr "type" "fp")])
3279 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3280 (neg:DF (abs:DF (match_operand:DF
1 "gpc_reg_operand" "f"))))]
3283 [(set_attr "type" "fp")])
3285 (define_insn "adddf3"
3286 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3287 (plus:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3288 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3290 "{fa|fadd} %
0,%
1,%
2"
3291 [(set_attr "type" "fp")])
3293 (define_insn "subdf3"
3294 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3295 (minus:DF (match_operand:DF
1 "gpc_reg_operand" "f")
3296 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3298 "{fs|fsub} %
0,%
1,%
2"
3299 [(set_attr "type" "fp")])
3301 (define_insn "muldf3"
3302 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3303 (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3304 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3306 "{fm|fmul} %
0,%
1,%
2"
3307 [(set_attr "type" "dmul")])
3309 (define_insn "divdf3"
3310 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3311 (div:DF (match_operand:DF
1 "gpc_reg_operand" "f")
3312 (match_operand:DF
2 "gpc_reg_operand" "f")))]
3314 "{fd|fdiv} %
0,%
1,%
2"
3315 [(set_attr "type" "ddiv")])
3318 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3319 (plus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3320 (match_operand:DF
2 "gpc_reg_operand" "f"))
3321 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3323 "{fma|fmadd} %
0,%
1,%
2,%
3"
3324 [(set_attr "type" "dmul")])
3327 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3328 (minus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3329 (match_operand:DF
2 "gpc_reg_operand" "f"))
3330 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3332 "{fms|fmsub} %
0,%
1,%
2,%
3"
3333 [(set_attr "type" "dmul")])
3336 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3337 (neg:DF (plus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3338 (match_operand:DF
2 "gpc_reg_operand" "f"))
3339 (match_operand:DF
3 "gpc_reg_operand" "f"))))]
3341 "{fnma|fnmadd} %
0,%
1,%
2,%
3"
3342 [(set_attr "type" "dmul")])
3345 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3346 (neg:DF (minus:DF (mult:DF (match_operand:DF
1 "gpc_reg_operand" "%f")
3347 (match_operand:DF
2 "gpc_reg_operand" "f"))
3348 (match_operand:DF
3 "gpc_reg_operand" "f"))))]
3350 "{fnms|fnmsub} %
0,%
1,%
2,%
3"
3351 [(set_attr "type" "dmul")])
3353 (define_insn "sqrtdf2"
3354 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3355 (sqrt:DF (match_operand:DF
1 "gpc_reg_operand" "f")))]
3356 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
3358 [(set_attr "type" "dsqrt")])
3360 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
3361 ;; fsel instruction and some auxiliary computations. Then we just have a
3362 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
3365 (define_expand "maxdf3"
3367 (minus:DF (match_operand:DF
1 "gpc_reg_operand" "")
3368 (match_operand:DF
2 "gpc_reg_operand" "")))
3369 (set (match_operand:DF
0 "gpc_reg_operand" "")
3370 (if_then_else:DF (ge (match_dup
3)
3374 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3376 { operands[
3] = gen_reg_rtx (DFmode); }")
3379 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3380 (smax:DF (match_operand:DF
1 "gpc_reg_operand" "")
3381 (match_operand:DF
2 "gpc_reg_operand" "")))
3382 (clobber (match_operand:DF
3 "gpc_reg_operand" ""))]
3383 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3385 (minus:DF (match_dup
1) (match_dup
2)))
3387 (if_then_else:DF (ge (match_dup
3)
3393 (define_expand "mindf3"
3395 (minus:DF (match_operand:DF
2 "gpc_reg_operand" "")
3396 (match_operand:DF
1 "gpc_reg_operand" "")))
3397 (set (match_operand:DF
0 "gpc_reg_operand" "")
3398 (if_then_else:DF (ge (match_dup
3)
3402 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3404 { operands[
3] = gen_reg_rtx (DFmode); }")
3407 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3408 (smin:DF (match_operand:DF
1 "gpc_reg_operand" "")
3409 (match_operand:DF
2 "gpc_reg_operand" "")))
3410 (clobber (match_operand:DF
3 "gpc_reg_operand" ""))]
3411 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3413 (minus:DF (match_dup
2) (match_dup
1)))
3415 (if_then_else:DF (ge (match_dup
3)
3421 (define_expand "movdfcc"
3422 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3423 (if_then_else:DF (match_operand
1 "comparison_operator" "")
3424 (match_operand:DF
2 "gpc_reg_operand" "f")
3425 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3426 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3430 enum rtx_code code = GET_CODE (operands[
1]);
3431 if (! rs6000_compare_fp_p)
3435 case GE: case EQ: case NE:
3436 op0 = rs6000_compare_op0;
3437 op1 = rs6000_compare_op1;
3440 op0 = rs6000_compare_op1;
3441 op1 = rs6000_compare_op0;
3442 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3445 op0 = rs6000_compare_op1;
3446 op1 = rs6000_compare_op0;
3449 op0 = rs6000_compare_op0;
3450 op1 = rs6000_compare_op1;
3451 temp = operands[
2]; operands[
2] = operands[
3]; operands[
3] = temp;
3456 if (GET_MODE (rs6000_compare_op0) == DFmode)
3458 temp = gen_reg_rtx (DFmode);
3459 emit_insn (gen_subdf3 (temp, op0, op1));
3460 emit_insn (gen_fseldfdf4 (operands[
0], temp, operands[
2], operands[
3]));
3463 emit_insn (gen_negdf2 (temp, temp));
3464 emit_insn (gen_fseldfdf4 (operands[
0], temp, operands[
0], operands[
3]));
3468 emit_insn (gen_negdf2 (temp, temp));
3469 emit_insn (gen_fseldfdf4 (operands[
0], temp, operands[
3], operands[
0]));
3474 temp = gen_reg_rtx (SFmode);
3475 emit_insn (gen_subsf3 (temp, op0, op1));
3476 emit_insn (gen_fselsfdf4 (operands[
0], temp, operands[
2], operands[
3]));
3479 emit_insn (gen_negsf2 (temp, temp));
3480 emit_insn (gen_fselsfdf4 (operands[
0], temp, operands[
0], operands[
3]));
3484 emit_insn (gen_negsf2 (temp, temp));
3485 emit_insn (gen_fselsfdf4 (operands[
0], temp, operands[
3], operands[
0]));
3491 (define_insn "fseldfdf4"
3492 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3493 (if_then_else:DF (ge (match_operand:DF
1 "gpc_reg_operand" "f")
3495 (match_operand:DF
2 "gpc_reg_operand" "f")
3496 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3497 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
3499 [(set_attr "type" "fp")])
3501 (define_insn "fselsfdf4"
3502 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3503 (if_then_else:DF (ge (match_operand:SF
1 "gpc_reg_operand" "f")
3505 (match_operand:DF
2 "gpc_reg_operand" "f")
3506 (match_operand:DF
3 "gpc_reg_operand" "f")))]
3509 [(set_attr "type" "fp")])
3511 ;; Conversions to and from floating-point.
3512 (define_expand "floatsidf2"
3513 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3514 (float:DF (match_operand:SI
1 "gpc_reg_operand" "")))]
3515 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3519 { /* prevent unused warning messages */
3520 rtx high = force_reg (SImode, GEN_INT (
0x43300000));
3521 rtx low = gen_reg_rtx (SImode);
3522 rtx df = gen_reg_rtx (DFmode);
3523 rtx adjust = force_reg (DFmode, rs6000_float_const (
\"4503601774854144\", DFmode));
3525 emit_insn (gen_xorsi3 (low, operands[
1], GEN_INT (
0x80000000)));
3526 emit_insn (gen_move_to_float (df, low, high));
3527 emit_insn (gen_subdf3 (operands[
0], df, adjust));
3532 (define_expand "floatunssidf2"
3533 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3534 (unsigned_float:DF (match_operand:SI
1 "gpc_reg_operand" "")))]
3535 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3539 { /* prevent unused warning messages */
3540 rtx high = force_reg (SImode, GEN_INT (
0x43300000));
3541 rtx df = gen_reg_rtx (DFmode);
3542 rtx adjust = force_reg (DFmode, rs6000_float_const (
\"4503599627370496\", DFmode));
3544 emit_insn (gen_move_to_float (df, operands[
1], high));
3545 emit_insn (gen_subdf3 (operands[
0], df, adjust));
3550 (define_expand "move_to_float"
3551 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3552 (unspec [(match_operand:SI
1 "gpc_reg_operand" "")
3553 (match_operand:SI
2 "gpc_reg_operand" "")
3555 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3558 operands[
3] = XEXP (rs6000_stack_temp (DFmode,
8,
1),
0);
3562 [(set (match_operand:DF
0 "gpc_reg_operand" "")
3563 (unspec [(match_operand:SI
1 "gpc_reg_operand" "")
3564 (match_operand:SI
2 "gpc_reg_operand" "")
3565 (match_operand:SI
3 "offsettable_addr_operand" "")]
2))]
3567 [(set (match_dup
4) (match_dup
1))
3568 (set (match_dup
5) (match_dup
2))
3569 (set (match_dup
0) (mem:DF (match_dup
3)))]
3572 rtx word1 = gen_rtx (MEM, SImode, operands[
3]);
3573 rtx word2 = gen_rtx (MEM, SImode, plus_constant (operands[
3],
4));
3575 MEM_IN_STRUCT_P (word1) =
1;
3576 MEM_IN_STRUCT_P (word2) =
1;
3578 if (WORDS_BIG_ENDIAN)
3580 operands[
4] = word2;
3581 operands[
5] = word1;
3585 operands[
4] = word1;
3586 operands[
5] = word2;
3591 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3592 (unspec [(match_operand:SI
1 "gpc_reg_operand" "r")
3593 (match_operand:SI
2 "gpc_reg_operand" "r")
3594 (match_operand:SI
3 "offsettable_addr_operand" "p")]
2))]
3595 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3597 [(set_attr "length" "
12")])
3599 (define_expand "fix_truncdfsi2"
3600 [(set (match_operand:SI
0 "gpc_reg_operand" "")
3601 (fix:SI (match_operand:DF
1 "gpc_reg_operand" "")))]
3605 if (TARGET_POWER2 || TARGET_POWERPC)
3607 rtx stack_slot = rs6000_stack_temp (DImode,
8,
1);
3608 rtx temp = gen_reg_rtx (DImode);
3610 emit_insn (gen_fpcvtsi (temp, operands[
1]));
3611 emit_move_insn (stack_slot, temp);
3612 emit_move_insn (operands[
0],
3613 gen_rtx (SUBREG, SImode, stack_slot, WORDS_BIG_ENDIAN));
3618 emit_insn (gen_trunc_call (operands[
0], operands[
1],
3619 gen_rtx (SYMBOL_REF, Pmode, RS6000_ITRUNC)));
3624 (define_insn "fpcvtsi"
3625 [(set (match_operand:DI
0 "gpc_reg_operand" "=f")
3627 (fix:SI (match_operand:DF
1 "gpc_reg_operand" "f"))))]
3628 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
3629 "{fcirz|fctiwz} %
0,%
1"
3630 [(set_attr "type" "fp")])
3632 (define_expand "fixuns_truncdfsi2"
3633 [(set (match_operand:SI
0 "gpc_reg_operand" "")
3634 (unsigned_fix:SI (match_operand:DF
1 "gpc_reg_operand" "")))]
3635 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
3638 emit_insn (gen_trunc_call (operands[
0], operands[
1],
3639 gen_rtx (SYMBOL_REF, Pmode, RS6000_UITRUNC)));
3643 (define_expand "trunc_call"
3644 [(parallel [(set (match_operand:SI
0 "" "")
3645 (fix:SI (match_operand:DF
1 "" "")))
3646 (use (match_operand:SI
2 "" ""))])]
3650 rtx insns = gen_trunc_call_rtl (operands[
0], operands[
1], operands[
2]);
3651 rtx first = XVECEXP (insns,
0,
0);
3652 rtx last = XVECEXP (insns,
0, XVECLEN (insns,
0) -
1);
3654 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
3656 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
3662 (define_expand "trunc_call_rtl"
3663 [(set (reg:DF
33) (match_operand:DF
1 "gpc_reg_operand" ""))
3665 (parallel [(set (reg:SI
3)
3666 (call (mem:SI (match_operand
2 "" "")) (const_int
0)))
3668 (clobber (scratch:SI))])
3669 (set (match_operand:SI
0 "gpc_reg_operand" "")
3674 rs6000_trunc_used =
1;
3677 (define_insn "floatdidf2"
3678 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
3679 (float:DF (match_operand:DI
1 "gpc_reg_operand" "f")))]
3680 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3682 [(set_attr "type" "fp")])
3684 (define_insn "fix_truncdfdi2"
3685 [(set (match_operand:DI
0 "gpc_reg_operand" "=f")
3686 (fix:DI (match_operand:DF
1 "gpc_reg_operand" "f")))]
3687 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
3689 [(set_attr "type" "fp")])
3691 ;; Define the DImode operations that can be done in a small number
3692 ;; of instructions. The & constraints are to prevent the register
3693 ;; allocator from allocating registers that overlap with the inputs
3694 ;; (for example, having an input in
7,
8 and an output in
6,
7). We
3695 ;; also allow for the the output being the same as one of the inputs.
3697 (define_insn "*adddi3_noppc64"
3698 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,&r,r,r")
3699 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,
0,
0")
3700 (match_operand:DI
2 "reg_or_short_operand" "r,I,r,I")))]
3701 "! TARGET_POWERPC64"
3704 if (WORDS_BIG_ENDIAN)
3705 return (GET_CODE (operands[
2])) != CONST_INT
3706 ?
\"{a|addc} %L0,%L1,%L2\;{ae|adde} %
0,%
1,%
2\"
3707 :
\"{ai|addic} %L0,%L1,%
2\;{a%G2e|add%G2e} %
0,%
1\";
3709 return (GET_CODE (operands[
2])) != CONST_INT
3710 ?
\"{a|addc} %
0,%
1,%
2\;{ae|adde} %L0,%L1,%L2
\"
3711 :
\"{ai|addic} %
0,%
1,%
2\;{a%G2e|add%G2e} %L0,%L1
\";
3713 [(set_attr "length" "
8")])
3715 (define_insn "*subdi3_noppc64"
3716 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,&r,r,r,r")
3717 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "r,I,
0,r,I")
3718 (match_operand:DI
2 "gpc_reg_operand" "r,r,r,
0,
0")))]
3719 "! TARGET_POWERPC64"
3722 if (WORDS_BIG_ENDIAN)
3723 return (GET_CODE (operands[
1]) != CONST_INT)
3724 ?
\"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %
0,%
2,%
1\"
3725 :
\"{sfi|subfic} %L0,%L2,%
1\;{sf%G1e|subf%G1e} %
0,%
2\";
3727 return (GET_CODE (operands[
1]) != CONST_INT)
3728 ?
\"{sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %L0,%L2,%L1
\"
3729 :
\"{sfi|subfic} %
0,%
2,%
1\;{sf%G1e|subf%G1e} %L0,%L2
\";
3731 [(set_attr "length" "
8")])
3733 (define_insn "*negdi2_noppc64"
3734 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
3735 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0")))]
3736 "! TARGET_POWERPC64"
3739 return (WORDS_BIG_ENDIAN)
3740 ?
\"{sfi|subfic} %L0,%L1,
0\;{sfze|subfze} %
0,%
1\"
3741 :
\"{sfi|subfic} %
0,%
1,
0\;{sfze|subfze} %L0,%L1
\";
3743 [(set_attr "length" "
8")])
3745 (define_expand "mulsidi3"
3746 [(set (match_operand:DI
0 "gpc_reg_operand" "")
3747 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
3748 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" ""))))]
3752 if (! TARGET_POWER && ! TARGET_POWERPC)
3754 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
3755 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
3756 emit_insn (gen_mull_call ());
3757 if (WORDS_BIG_ENDIAN)
3758 emit_move_insn (operands[
0], gen_rtx (REG, DImode,
3));
3761 emit_move_insn (operand_subword (operands[
0],
0,
0, DImode),
3762 gen_rtx (REG, SImode,
3));
3763 emit_move_insn (operand_subword (operands[
0],
1,
0, DImode),
3764 gen_rtx (REG, SImode,
4));
3768 else if (TARGET_POWER)
3770 emit_insn (gen_mulsidi3_mq (operands[
0], operands[
1], operands[
2]));
3775 (define_insn "mulsidi3_mq"
3776 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
3777 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "%r"))
3778 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))
3779 (clobber (match_scratch:SI
3 "=q"))]
3781 "mul %
0,%
1,%
2\;mfmq %L0"
3782 [(set_attr "type" "imul")
3783 (set_attr "length" "
8")])
3785 (define_insn "*mulsidi3_powerpc"
3786 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
3787 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" "%r"))
3788 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
3789 "TARGET_POWERPC && ! TARGET_POWERPC64"
3792 return (WORDS_BIG_ENDIAN)
3793 ?
\"mulhw %
0,%
1,%
2\;mullw %L0,%
1,%
2\"
3794 :
\"mulhw %L0,%
1,%
2\;mullw %
0,%
1,%
2\";
3796 [(set_attr "type" "imul")
3797 (set_attr "length" "
8")])
3800 [(set (match_operand:DI
0 "gpc_reg_operand" "")
3801 (mult:DI (sign_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
3802 (sign_extend:DI (match_operand:SI
2 "gpc_reg_operand" ""))))]
3803 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
3806 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup
1))
3807 (sign_extend:DI (match_dup
2)))
3810 (mult:SI (match_dup
1)
3814 int endian = (WORDS_BIG_ENDIAN ==
0);
3815 operands[
3] = operand_subword (operands[
0], endian,
0, DImode);
3816 operands[
4] = operand_subword (operands[
0],
1 - endian,
0, DImode);
3819 (define_insn "umulsidi3"
3820 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
3821 (mult:DI (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" "%r"))
3822 (zero_extend:DI (match_operand:SI
2 "gpc_reg_operand" "r"))))]
3823 "TARGET_POWERPC && ! TARGET_POWERPC64"
3826 return (WORDS_BIG_ENDIAN)
3827 ?
\"mulhwu %
0,%
1,%
2\;mullw %L0,%
1,%
2\"
3828 :
\"mulhwu %L0,%
1,%
2\;mullw %
0,%
1,%
2\";
3830 [(set_attr "type" "imul")
3831 (set_attr "length" "
8")])
3834 [(set (match_operand:DI
0 "gpc_reg_operand" "")
3835 (mult:DI (zero_extend:DI (match_operand:SI
1 "gpc_reg_operand" ""))
3836 (zero_extend:DI (match_operand:SI
2 "gpc_reg_operand" ""))))]
3837 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
3840 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup
1))
3841 (zero_extend:DI (match_dup
2)))
3844 (mult:SI (match_dup
1)
3848 int endian = (WORDS_BIG_ENDIAN ==
0);
3849 operands[
3] = operand_subword (operands[
0], endian,
0, DImode);
3850 operands[
4] = operand_subword (operands[
0],
1 - endian,
0, DImode);
3853 (define_expand "smulsi3_highpart"
3854 [(set (match_operand:SI
0 "gpc_reg_operand" "")
3856 (lshiftrt:DI (mult:DI (sign_extend:DI
3857 (match_operand:SI
1 "gpc_reg_operand" "%r"))
3859 (match_operand:SI
2 "gpc_reg_operand" "r")))
3864 if (! TARGET_POWER && ! TARGET_POWERPC)
3866 emit_move_insn (gen_rtx (REG, SImode,
3), operands[
1]);
3867 emit_move_insn (gen_rtx (REG, SImode,
4), operands[
2]);
3868 emit_insn (gen_mulh_call ());
3869 emit_move_insn (operands[
0], gen_rtx (REG, SImode,
3));
3872 else if (TARGET_POWER)
3874 emit_insn (gen_smulsi3_highpart_mq (operands[
0], operands[
1], operands[
2]));
3879 (define_insn "smulsi3_highpart_mq"
3880 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
3882 (lshiftrt:DI (mult:DI (sign_extend:DI
3883 (match_operand:SI
1 "gpc_reg_operand" "%r"))
3885 (match_operand:SI
2 "gpc_reg_operand" "r")))
3887 (clobber (match_scratch:SI
3 "=q"))]
3890 [(set_attr "type" "imul")])
3893 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
3895 (lshiftrt:DI (mult:DI (sign_extend:DI
3896 (match_operand:SI
1 "gpc_reg_operand" "%r"))
3898 (match_operand:SI
2 "gpc_reg_operand" "r")))
3902 [(set_attr "type" "imul")])
3904 (define_insn "umulsi3_highpart"
3905 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
3907 (lshiftrt:DI (mult:DI (zero_extend:DI
3908 (match_operand:SI
1 "gpc_reg_operand" "%r"))
3910 (match_operand:SI
2 "gpc_reg_operand" "r")))
3914 [(set_attr "type" "imul")])
3916 ;; If operands
0 and
2 are in the same register, we have a problem. But
3917 ;; operands
0 and
1 (the usual case) can be in the same register. That's
3918 ;; why we have the strange constraints below.
3919 (define_insn "ashldi3_power"
3920 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r,&r")
3921 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r,r,
0,r")
3922 (match_operand:SI
2 "reg_or_cint_operand" "M,i,r,r")))
3923 (clobber (match_scratch:SI
3 "=X,q,q,q"))]
3926 {sli|slwi} %
0,%L1,%h2\;{cal %L0,
0(
0)|li %L0,
0}
3927 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2
3928 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2
3929 sl%I2q %L0,%L1,%h2\;sll%I2q %
0,%
1,%h2"
3930 [(set_attr "length" "
8")])
3932 (define_insn "lshrdi3_power"
3933 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r,r,&r")
3934 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r,r,
0,r")
3935 (match_operand:SI
2 "reg_or_cint_operand" "M,i,r,r")))
3936 (clobber (match_scratch:SI
3 "=X,q,q,q"))]
3939 {cal %
0,
0(
0)|li %
0,
0}\;{s%A2i|s%A2wi} %L0,%
1,%h2
3940 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2
3941 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2
3942 sr%I2q %
0,%
1,%h2\;srl%I2q %L0,%L1,%h2"
3943 [(set_attr "length" "
8")])
3945 ;; Shift by a variable amount is too complex to be worth open-coding. We
3946 ;; just handle shifts by constants.
3947 (define_insn "ashrdi3_power"
3948 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
3949 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r,r")
3950 (match_operand:SI
2 "const_int_operand" "M,i")))
3951 (clobber (match_scratch:SI
3 "=X,q"))]
3954 {srai|srawi} %
0,%
1,
31\;{srai|srawi} %L0,%
1,%h2
3955 sraiq %
0,%
1,%h2\;srliq %L0,%L1,%h2"
3956 [(set_attr "length" "
8")])
3958 ;; PowerPC64 DImode operations.
3960 (define_expand "adddi3"
3961 [(set (match_operand:DI
0 "gpc_reg_operand" "")
3962 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "")
3963 (match_operand:DI
2 "add_operand" "")))]
3967 if (! TARGET_POWERPC64 && non_add_cint_operand (operands[
2], DImode))
3971 ;; Discourage ai/addic because of carry but provide it in an alternative
3972 ;; allowing register zero as source.
3975 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,?r,r")
3976 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,b,r,b")
3977 (match_operand:DI
2 "add_operand" "r,I,I,J")))]
3986 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
3987 (compare:CC (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r")
3988 (match_operand:DI
2 "reg_or_short_operand" "r,I"))
3990 (clobber (match_scratch:DI
3 "=r,r"))]
3995 [(set_attr "type" "compare")])
3998 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
3999 (compare:CC (plus:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r")
4000 (match_operand:DI
2 "reg_or_short_operand" "r,I"))
4002 (set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
4003 (plus:DI (match_dup
1) (match_dup
2)))]
4008 [(set_attr "type" "compare")])
4010 ;; Split an add that we can't do in one insn into two insns, each of which
4011 ;; does one
16-bit part. This is used by combine. Note that the low-order
4012 ;; add should be last in case the result gets used in an address.
4015 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4016 (plus:DI (match_operand:DI
1 "gpc_reg_operand" "")
4017 (match_operand:DI
2 "non_add_cint_operand" "")))]
4019 [(set (match_dup
0) (plus:DI (match_dup
1) (match_dup
3)))
4020 (set (match_dup
0) (plus:DI (match_dup
0) (match_dup
4)))]
4023 HOST_WIDE_INT low = INTVAL (operands[
2]) &
0xffff;
4024 HOST_WIDE_INT high = INTVAL (operands[
2]) & (~ (HOST_WIDE_INT)
0xffff);
4027 high+=
0x10000, low |= ((HOST_WIDE_INT) -
1) <<
16;
4029 operands[
3] = GEN_INT (high);
4030 operands[
4] = GEN_INT (low);
4033 (define_insn "one_cmpldi2"
4034 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4035 (not:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
4040 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4041 (compare:CC (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4043 (clobber (match_scratch:DI
2 "=r"))]
4046 [(set_attr "type" "compare")])
4049 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
4050 (compare:CC (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4052 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4053 (not:DI (match_dup
1)))]
4056 [(set_attr "type" "compare")])
4059 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r")
4060 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "r,I")
4061 (match_operand:DI
2 "gpc_reg_operand" "r,r")))]
4068 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4069 (compare:CC (minus:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4070 (match_operand:DI
2 "gpc_reg_operand" "r"))
4072 (clobber (match_scratch:DI
3 "=r"))]
4075 [(set_attr "type" "compare")])
4078 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4079 (compare:CC (minus:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4080 (match_operand:DI
2 "gpc_reg_operand" "r"))
4082 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4083 (minus:DI (match_dup
1) (match_dup
2)))]
4086 [(set_attr "type" "compare")])
4088 (define_expand "subdi3"
4089 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4090 (minus:DI (match_operand:DI
1 "reg_or_short_operand" "")
4091 (match_operand:DI
2 "reg_or_cint_operand" "")))]
4095 if (GET_CODE (operands[
2]) == CONST_INT)
4097 emit_insn (gen_adddi3 (operands[
0], operands[
1],
4098 negate_rtx (DImode, operands[
2])));
4103 (define_insn "absdi2"
4104 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4105 (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0")))
4106 (clobber (match_scratch:DI
2 "=&r,&r"))]
4108 "sradi %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
2,%
0"
4109 [(set_attr "length" "
12")])
4112 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4113 (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0")))
4114 (clobber (match_scratch:DI
2 "=&r,&r"))]
4115 "TARGET_POWERPC64 && reload_completed"
4116 [(set (match_dup
2) (ashiftrt:DI (match_dup
1) (const_int
31)))
4117 (set (match_dup
0) (xor:DI (match_dup
2) (match_dup
1)))
4118 (set (match_dup
0) (minus:DI (match_dup
2) (match_dup
0)))]
4122 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4123 (neg:DI (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0"))))
4124 (clobber (match_scratch:DI
2 "=&r,&r"))]
4126 "sradi %
2,%
1,
31\;xor %
0,%
2,%
1\;subf %
0,%
0,%
2"
4127 [(set_attr "length" "
12")])
4130 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r,r")
4131 (neg:DI (abs:DI (match_operand:DI
1 "gpc_reg_operand" "r,
0"))))
4132 (clobber (match_scratch:DI
2 "=&r,&r"))]
4133 "TARGET_POWERPC64 && reload_completed"
4134 [(set (match_dup
2) (ashiftrt:DI (match_dup
1) (const_int
31)))
4135 (set (match_dup
0) (xor:DI (match_dup
2) (match_dup
1)))
4136 (set (match_dup
0) (minus:DI (match_dup
0) (match_dup
2)))]
4139 (define_expand "negdi2"
4140 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4141 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "")))]
4146 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4147 (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
4152 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4153 (compare:CC (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4155 (clobber (match_scratch:DI
2 "=r"))]
4158 [(set_attr "type" "compare")])
4161 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
4162 (compare:CC (neg:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4164 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4165 (neg:DI (match_dup
1)))]
4168 [(set_attr "type" "compare")])
4170 (define_insn "ffsdi2"
4171 [(set (match_operand:DI
0 "gpc_reg_operand" "=&r")
4172 (ffs:DI (match_operand:DI
1 "gpc_reg_operand" "r")))]
4174 "neg %
0,%
1\;and %
0,%
0,%
1\;cntlzd %
0,%
0\;subfic %
0,%
0,
64"
4175 [(set_attr "length" "
16")])
4177 (define_insn "muldi3"
4178 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4179 (mult:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4180 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4183 [(set_attr "type" "imul")])
4185 (define_insn "smuldi3_highpart"
4186 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4188 (lshiftrt:TI (mult:TI (sign_extend:TI
4189 (match_operand:DI
1 "gpc_reg_operand" "%r"))
4191 (match_operand:DI
2 "gpc_reg_operand" "r")))
4195 [(set_attr "type" "imul")])
4197 (define_insn "umuldi3_highpart"
4198 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4200 (lshiftrt:TI (mult:TI (zero_extend:TI
4201 (match_operand:DI
1 "gpc_reg_operand" "%r"))
4203 (match_operand:DI
2 "gpc_reg_operand" "r")))
4207 [(set_attr "type" "imul")])
4209 (define_expand "divdi3"
4210 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4211 (div:DI (match_operand:DI
1 "gpc_reg_operand" "")
4212 (match_operand:DI
2 "reg_or_cint_operand" "")))]
4216 if (GET_CODE (operands[
2]) == CONST_INT
4217 && exact_log2 (INTVAL (operands[
2])) >=
0)
4220 operands[
2] = force_reg (DImode, operands[
2]);
4223 (define_expand "moddi3"
4224 [(use (match_operand:DI
0 "gpc_reg_operand" ""))
4225 (use (match_operand:DI
1 "gpc_reg_operand" ""))
4226 (use (match_operand:DI
2 "reg_or_cint_operand" ""))]
4230 int i = exact_log2 (INTVAL (operands[
2]));
4234 if (GET_CODE (operands[
2]) != CONST_INT || i <
0)
4237 temp1 = gen_reg_rtx (DImode);
4238 temp2 = gen_reg_rtx (DImode);
4240 emit_insn (gen_divdi3 (temp1, operands[
1], operands[
2]));
4241 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
4242 emit_insn (gen_subdi3 (operands[
0], operands[
1], temp2));
4247 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4248 (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4249 (match_operand:DI
2 "const_int_operand" "N")))]
4250 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[
2])) >=
0"
4251 "sradi %
0,%
1,%p2\;addze %
0,%
0"
4252 [(set_attr "length" "
8")])
4255 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4256 (compare:CC (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4257 (match_operand:DI
2 "const_int_operand" "N"))
4259 (clobber (match_scratch:DI
3 "=r"))]
4260 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[
2])) >=
0"
4261 "sradi %
3,%
1,%p2\;addze. %
3,%
3"
4262 [(set_attr "type" "compare")
4263 (set_attr "length" "
8")])
4266 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4267 (compare:CC (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4268 (match_operand:DI
2 "const_int_operand" "N"))
4270 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4271 (div:DI (match_dup
1) (match_dup
2)))]
4272 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[
2])) >=
0"
4273 "sradi %
0,%
1,%p2\;addze. %
0,%
0"
4274 [(set_attr "type" "compare")
4275 (set_attr "length" "
8")])
4278 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4279 (div:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4280 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4283 [(set_attr "type" "idiv")])
4285 (define_insn "udivdi3"
4286 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4287 (udiv:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4288 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4291 [(set_attr "type" "idiv")])
4293 (define_insn "rotldi3"
4294 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4295 (rotate:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4296 (match_operand:DI
2 "reg_or_cint_operand" "ri")))]
4298 "rld%I2cl %
0,%
1,%H2,
0")
4301 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4302 (compare:CC (rotate:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4303 (match_operand:DI
2 "reg_or_cint_operand" "ri"))
4305 (clobber (match_scratch:DI
3 "=r"))]
4307 "rld%I2cl. %
3,%
1,%H2,
0"
4308 [(set_attr "type" "delayed_compare")])
4311 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4312 (compare:CC (rotate:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4313 (match_operand:DI
2 "reg_or_cint_operand" "ri"))
4315 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4316 (rotate:DI (match_dup
1) (match_dup
2)))]
4318 "rld%I2cl. %
0,%
1,%H2,
0"
4319 [(set_attr "type" "delayed_compare")])
4321 (define_expand "ashldi3"
4322 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4323 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "")
4324 (match_operand:SI
2 "reg_or_cint_operand" "")))]
4325 "TARGET_POWERPC64 || TARGET_POWER"
4328 if (TARGET_POWERPC64)
4330 else if (TARGET_POWER)
4332 emit_insn (gen_ashldi3_power (operands[
0], operands[
1], operands[
2]));
4340 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4341 (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4342 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
4345 [(set_attr "length" "
8")])
4348 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4349 (compare:CC (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4350 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4352 (clobber (match_scratch:DI
3 "=r"))]
4355 [(set_attr "type" "delayed_compare")])
4358 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4359 (compare:CC (ashift:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4360 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4362 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4363 (ashift:DI (match_dup
1) (match_dup
2)))]
4366 [(set_attr "type" "delayed_compare")])
4368 (define_expand "lshrdi3"
4369 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4370 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "")
4371 (match_operand:SI
2 "reg_or_cint_operand" "")))]
4372 "TARGET_POWERPC64 || TARGET_POWER"
4375 if (TARGET_POWERPC64)
4377 else if (TARGET_POWER)
4379 emit_insn (gen_lshrdi3_power (operands[
0], operands[
1], operands[
2]));
4387 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4388 (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4389 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
4394 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4395 (compare:CC (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4396 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4398 (clobber (match_scratch:DI
3 "=r"))]
4401 [(set_attr "type" "delayed_compare")])
4404 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4405 (compare:CC (lshiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4406 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4408 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4409 (lshiftrt:DI (match_dup
1) (match_dup
2)))]
4412 [(set_attr "type" "delayed_compare")])
4414 (define_expand "ashrdi3"
4415 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4416 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "")
4417 (match_operand:SI
2 "reg_or_cint_operand" "")))]
4418 "TARGET_POWERPC64 || TARGET_POWER"
4421 if (TARGET_POWERPC64)
4423 else if (TARGET_POWER && GET_CODE (operands[
2]) == CONST_INT)
4425 emit_insn (gen_ashrdi3_power (operands[
0], operands[
1], operands[
2]));
4433 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4434 (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4435 (match_operand:SI
2 "reg_or_cint_operand" "ri")))]
4437 "srad%I2 %
0,%
1,%H2")
4440 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4441 (compare:CC (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4442 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4444 (clobber (match_scratch:DI
3 "=r"))]
4446 "srad%I2. %
3,%
1,%H2"
4447 [(set_attr "type" "delayed_compare")])
4450 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4451 (compare:CC (ashiftrt:DI (match_operand:DI
1 "gpc_reg_operand" "r")
4452 (match_operand:SI
2 "reg_or_cint_operand" "ri"))
4454 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4455 (ashiftrt:DI (match_dup
1) (match_dup
2)))]
4457 "srad%I2. %
0,%
1,%H2"
4458 [(set_attr "type" "delayed_compare")])
4460 (define_insn "anddi3"
4461 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4462 (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4463 (match_operand:DI
2 "and_operand" "?r,K,J")))
4464 (clobber (match_scratch:CC
3 "=X,x,x"))]
4472 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x")
4473 (compare:CC (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4474 (match_operand:DI
2 "and_operand" "r,K,J"))
4476 (clobber (match_scratch:DI
3 "=r,r,r"))]
4482 [(set_attr "type" "compare,compare,compare")])
4485 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x,x")
4486 (compare:CC (and:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4487 (match_operand:DI
2 "and_operand" "r,K,J"))
4489 (set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4490 (and:DI (match_dup
1) (match_dup
2)))]
4496 [(set_attr "type" "compare,compare,compare")])
4498 ;; Take a AND with a constant that cannot be done in a single insn and try to
4499 ;; split it into two insns. This does not verify that the insns are valid
4500 ;; since this need not be done as combine will do it.
4503 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4504 (and:DI (match_operand:DI
1 "gpc_reg_operand" "")
4505 (match_operand:DI
2 "non_and_cint_operand" "")))]
4507 [(set (match_dup
0) (and:DI (match_dup
1) (match_dup
3)))
4508 (set (match_dup
0) (and:DI (match_dup
0) (match_dup
4)))]
4511 int maskval = INTVAL (operands[
2]);
4512 int i, transitions, last_bit_value;
4513 int orig = maskval, first_c = maskval, second_c;
4515 /* We know that MASKVAL must have more than
2 bit-transitions. Start at
4516 the low-order bit and count for the third transition. When we get there,
4517 make a first mask that has everything to the left of that position
4518 a one. Then make the second mask to turn off whatever else is needed. */
4520 for (i =
1, transitions =
0, last_bit_value = maskval &
1; i <
32; i++)
4522 if (((maskval >>=
1) &
1) != last_bit_value)
4523 last_bit_value ^=
1, transitions++;
4525 if (transitions >
2)
4527 first_c |= (~
0) << i;
4532 second_c = orig | ~ first_c;
4534 operands[
3] = gen_rtx (CONST_INT, VOIDmode, first_c);
4535 operands[
4] = gen_rtx (CONST_INT, VOIDmode, second_c);
4538 (define_insn "iordi3"
4539 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4540 (ior:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4541 (match_operand:DI
2 "logical_operand" "r,K,J")))]
4549 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4550 (compare:CC (ior:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4551 (match_operand:DI
2 "gpc_reg_operand" "r"))
4553 (clobber (match_scratch:DI
3 "=r"))]
4556 [(set_attr "type" "compare")])
4559 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4560 (compare:CC (ior:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4561 (match_operand:DI
2 "gpc_reg_operand" "r"))
4563 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4564 (ior:DI (match_dup
1) (match_dup
2)))]
4567 [(set_attr "type" "compare")])
4569 ;; Split an IOR that we can't do in one insn into two insns, each of which
4570 ;; does one
16-bit part. This is used by combine.
4573 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4574 (ior:DI (match_operand:DI
1 "gpc_reg_operand" "")
4575 (match_operand:DI
2 "non_logical_cint_operand" "")))]
4577 [(set (match_dup
0) (ior:DI (match_dup
1) (match_dup
3)))
4578 (set (match_dup
0) (ior:DI (match_dup
0) (match_dup
4)))]
4581 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
4582 INTVAL (operands[
2]) & (~ (HOST_WIDE_INT)
0xffff));
4583 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
4586 (define_insn "xordi3"
4587 [(set (match_operand:DI
0 "gpc_reg_operand" "=r,r,r")
4588 (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r,r,r")
4589 (match_operand:DI
2 "logical_operand" "r,K,J")))]
4597 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4598 (compare:CC (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4599 (match_operand:DI
2 "gpc_reg_operand" "r"))
4601 (clobber (match_scratch:DI
3 "=r"))]
4604 [(set_attr "type" "compare")])
4607 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4608 (compare:CC (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4609 (match_operand:DI
2 "gpc_reg_operand" "r"))
4611 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4612 (xor:DI (match_dup
1) (match_dup
2)))]
4615 [(set_attr "type" "compare")])
4617 ;; Split an XOR that we can't do in one insn into two insns, each of which
4618 ;; does one
16-bit part. This is used by combine.
4621 [(set (match_operand:DI
0 "gpc_reg_operand" "")
4622 (xor:DI (match_operand:DI
1 "gpc_reg_operand" "")
4623 (match_operand:DI
2 "non_logical_cint_operand" "")))]
4625 [(set (match_dup
0) (xor:DI (match_dup
1) (match_dup
3)))
4626 (set (match_dup
0) (xor:DI (match_dup
0) (match_dup
4)))]
4629 operands[
3] = gen_rtx (CONST_INT, VOIDmode,
4630 INTVAL (operands[
2]) &
0xffff0000);
4631 operands[
4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
2]) &
0xffff);
4635 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4636 (not:DI (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4637 (match_operand:DI
2 "gpc_reg_operand" "r"))))]
4642 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4643 (compare:CC (not:DI (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4644 (match_operand:DI
2 "gpc_reg_operand" "r")))
4646 (clobber (match_scratch:DI
3 "=r"))]
4649 [(set_attr "type" "compare")])
4652 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4653 (compare:CC (not:DI (xor:DI (match_operand:DI
1 "gpc_reg_operand" "%r")
4654 (match_operand:DI
2 "gpc_reg_operand" "r")))
4656 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4657 (not:DI (xor:DI (match_dup
1) (match_dup
2))))]
4660 [(set_attr "type" "compare")])
4663 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4664 (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4665 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4670 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4671 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4672 (match_operand:DI
2 "gpc_reg_operand" "r"))
4674 (clobber (match_scratch:DI
3 "=r"))]
4677 [(set_attr "type" "compare")])
4680 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4681 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4682 (match_operand:DI
2 "gpc_reg_operand" "r"))
4684 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4685 (and:DI (not:DI (match_dup
1)) (match_dup
2)))]
4688 [(set_attr "type" "compare")])
4691 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4692 (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4693 (match_operand:DI
2 "gpc_reg_operand" "r")))]
4698 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4699 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4700 (match_operand:DI
2 "gpc_reg_operand" "r"))
4702 (clobber (match_scratch:DI
3 "=r"))]
4705 [(set_attr "type" "compare")])
4708 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4709 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "r"))
4710 (match_operand:DI
2 "gpc_reg_operand" "r"))
4712 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4713 (ior:DI (not:DI (match_dup
1)) (match_dup
2)))]
4716 [(set_attr "type" "compare")])
4719 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4720 (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4721 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r"))))]
4726 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4727 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4728 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4730 (clobber (match_scratch:DI
3 "=r"))]
4733 [(set_attr "type" "compare")])
4736 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4737 (compare:CC (ior:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4738 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4740 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4741 (ior:DI (not:DI (match_dup
1)) (not:DI (match_dup
2))))]
4744 [(set_attr "type" "compare")])
4747 [(set (match_operand:DI
0 "gpc_reg_operand" "=r")
4748 (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4749 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r"))))]
4754 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
4755 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4756 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4758 (clobber (match_scratch:DI
3 "=r"))]
4761 [(set_attr "type" "compare")])
4764 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
4765 (compare:CC (and:DI (not:DI (match_operand:DI
1 "gpc_reg_operand" "%r"))
4766 (not:DI (match_operand:DI
2 "gpc_reg_operand" "r")))
4768 (set (match_operand:DI
0 "gpc_reg_operand" "=r")
4769 (and:DI (not:DI (match_dup
1)) (not:DI (match_dup
2))))]
4772 [(set_attr "type" "compare")])
4774 ;; Now define ways of moving data around.
4776 ;; Elf specific ways of loading addresses for non-PIC code.
4777 ;; The output of this could be r0, but we limit it to base
4778 ;; registers, since almost all uses of this will need it
4779 ;; in a base register shortly.
4780 (define_insn "elf_high"
4781 [(set (match_operand:SI
0 "register_operand" "=b")
4782 (high:SI (match_operand
1 "" "")))]
4783 "TARGET_ELF && !TARGET_64BIT"
4784 "{cau|addis} %
0,
0,%
1@ha")
4786 (define_insn "elf_low"
4787 [(set (match_operand:SI
0 "register_operand" "=r")
4788 (lo_sum:SI (match_operand:SI
1 "register_operand" "b")
4789 (match_operand
2 "" "")))]
4790 "TARGET_ELF && !TARGET_64BIT"
4791 "{cal %
0,%a2@l(%
1)|addi %
0,%
1,%
2@l}")
4793 ;; For SI, we special-case integers that can't be loaded in one insn. We
4794 ;; do the load
16-bits at a time. We could do this by loading from memory,
4795 ;; and this is even supposed to be faster, but it is simpler not to get
4796 ;; integers in the TOC.
4797 (define_expand "movsi"
4798 [(set (match_operand:SI
0 "general_operand" "")
4799 (match_operand:SI
1 "any_operand" ""))]
4803 if (GET_CODE (operands[
0]) != REG)
4804 operands[
1] = force_reg (SImode, operands[
1]);
4806 /* Convert a move of a CONST_DOUBLE into a CONST_INT */
4807 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
4808 operands[
1] = GEN_INT (CONST_DOUBLE_LOW (operands[
1]));
4810 /* Use default pattern for address of ELF small data */
4812 && DEFAULT_ABI == ABI_V4
4813 && (GET_CODE (operands[
1]) == SYMBOL_REF || GET_CODE (operands[
1]) == CONST)
4814 && small_data_operand (operands[
1], SImode))
4816 emit_insn (gen_rtx (SET, VOIDmode, operands[
0], operands[
1]));
4820 if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
4821 && CONSTANT_P (operands[
1])
4822 && GET_CODE (operands[
1]) != HIGH
4823 && GET_CODE (operands[
1]) != CONST_INT)
4825 rtx target = (reload_completed || reload_in_progress)
4826 ? operands[
0] : gen_reg_rtx (SImode);
4828 /* If this is a function address on -mcall-aixdesc or -mcall-nt,
4829 convert it to the address of the descriptor. */
4830 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
4831 && GET_CODE (operands[
1]) == SYMBOL_REF
4832 && XSTR (operands[
1],
0)[
0] == '.')
4834 char *name = XSTR (operands[
1],
0);
4836 while (*name == '.')
4838 new_ref = gen_rtx (SYMBOL_REF, Pmode, name);
4839 CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[
1]);
4840 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[
1]);
4841 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[
1]);
4842 operands[
1] = new_ref;
4845 emit_insn (gen_elf_high (target, operands[
1]));
4846 emit_insn (gen_elf_low (operands[
0], target, operands[
1]));
4850 if (GET_CODE (operands[
1]) == CONST
4851 && DEFAULT_ABI == ABI_NT
4852 && !side_effects_p (operands[
0]))
4854 rtx const_term = const0_rtx;
4855 rtx sym = eliminate_constant_term (XEXP (operands[
1],
0), &const_term);
4856 if (sym && GET_CODE (const_term) == CONST_INT
4857 && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
4859 unsigned HOST_WIDE_INT value = INTVAL (const_term);
4860 int new_reg_p = (flag_expensive_optimizations
4861 && !reload_completed
4862 && !reload_in_progress);
4863 rtx tmp1 = (new_reg_p && value !=
0) ? gen_reg_rtx (SImode) : operands[
0];
4865 emit_insn (gen_movsi (tmp1, sym));
4866 if (INTVAL (const_term) !=
0)
4868 if (value +
0x8000 <
0x10000)
4869 emit_insn (gen_addsi3 (operands[
0], tmp1, GEN_INT (value)));
4873 HOST_WIDE_INT high_int = value & (~ (HOST_WIDE_INT)
0xffff);
4874 HOST_WIDE_INT low_int = value &
0xffff;
4875 rtx tmp2 = (!new_reg_p || !low_int) ? operands[
0] : gen_reg_rtx (Pmode);
4877 if (low_int &
0x8000)
4878 high_int +=
0x10000, low_int |= ((HOST_WIDE_INT) -
1) <<
16;
4880 emit_insn (gen_addsi3 (tmp2, tmp1, GEN_INT (high_int)));
4882 emit_insn (gen_addsi3 (operands[
0], tmp2, GEN_INT (low_int)));
4888 fatal_insn (
\"bad address
\", operands[
1]);
4891 if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
4892 && CONSTANT_P (operands[
1])
4893 && GET_CODE (operands[
1]) != CONST_INT
4894 && GET_CODE (operands[
1]) != HIGH
4895 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[
1]))
4897 /* If we are to limit the number of things we put in the TOC and
4898 this is a symbol plus a constant we can add in one insn,
4899 just put the symbol in the TOC and add the constant. Don't do
4900 this if reload is in progress. */
4901 if (GET_CODE (operands[
1]) == CONST
4902 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4903 && GET_CODE (XEXP (operands[
1],
0)) == PLUS
4904 && add_operand (XEXP (XEXP (operands[
1],
0),
1), SImode)
4905 && (GET_CODE (XEXP (XEXP (operands[
1],
0),
0)) == LABEL_REF
4906 || GET_CODE (XEXP (XEXP (operands[
1],
0),
0)) == SYMBOL_REF)
4907 && ! side_effects_p (operands[
0]))
4909 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[
1],
0),
0));
4910 rtx other = XEXP (XEXP (operands[
1],
0),
1);
4912 emit_insn (gen_addsi3 (operands[
0], force_reg (SImode, sym), other));
4916 operands[
1] = force_const_mem (SImode, operands[
1]);
4917 if (! memory_address_p (SImode, XEXP (operands[
1],
0))
4918 && ! reload_in_progress)
4919 operands[
1] = change_address (operands[
1], SImode,
4920 XEXP (operands[
1],
0));
4925 [(set (match_operand:SI
0 "nonimmediate_operand" "=r,r,r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
4926 (match_operand:SI
1 "input_operand" "r,S,T,U,m,r,I,J,n,R,*h,r,r,
0"))]
4927 "gpc_reg_operand (operands[
0], SImode)
4928 || gpc_reg_operand (operands[
1], SImode)"
4931 {l|lwz} %
0,[toc]%
1(
2)
4932 {l|lwz} %
0,[toc]%l1(
2)
4934 {l%U1%X1|lwz%U1%X1} %
0,%
1
4935 {st%U0%X0|stw%U0%X0} %
1,%
0
4944 [(set_attr "type" "*,load,load,*,load,*,*,*,*,*,*,*,mtjmpr,*")
4945 (set_attr "length" "
4,
4,
4,
4,
4,
4,
4,
4,
8,
4,
4,
4,
4,
4")])
4947 ;; Split a load of a large constant into the appropriate two-insn
4951 [(set (match_operand:SI
0 "gpc_reg_operand" "")
4952 (match_operand:SI
1 "const_int_operand" ""))]
4953 "(unsigned) (INTVAL (operands[
1]) +
0x8000) >=
0x10000
4954 && (INTVAL (operands[
1]) &
0xffff) !=
0"
4958 (ior:SI (match_dup
0)
4962 operands[
2] = gen_rtx (CONST_INT, VOIDmode,
4963 INTVAL (operands[
1]) &
0xffff0000);
4964 operands[
3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[
1]) &
0xffff);
4968 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
4969 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
4971 (set (match_operand:SI
0 "gpc_reg_operand" "=r") (match_dup
1))]
4974 [(set_attr "type" "compare")])
4976 (define_expand "movhi"
4977 [(set (match_operand:HI
0 "general_operand" "")
4978 (match_operand:HI
1 "any_operand" ""))]
4982 if (GET_CODE (operands[
0]) != REG)
4983 operands[
1] = force_reg (HImode, operands[
1]);
4985 if (CONSTANT_P (operands[
1]) && GET_CODE (operands[
1]) != CONST_INT)
4987 operands[
1] = force_const_mem (HImode, operands[
1]);
4988 if (! memory_address_p (HImode, XEXP (operands[
1],
0))
4989 && ! reload_in_progress)
4990 operands[
1] = change_address (operands[
1], HImode,
4991 XEXP (operands[
1],
0));
4996 [(set (match_operand:HI
0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
4997 (match_operand:HI
1 "input_operand" "r,m,r,i,*h,r,r,
0"))]
4998 "gpc_reg_operand (operands[
0], HImode)
4999 || gpc_reg_operand (operands[
1], HImode)"
5009 [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
5011 (define_expand "movqi"
5012 [(set (match_operand:QI
0 "general_operand" "")
5013 (match_operand:QI
1 "any_operand" ""))]
5017 if (GET_CODE (operands[
0]) != REG)
5018 operands[
1] = force_reg (QImode, operands[
1]);
5020 if (CONSTANT_P (operands[
1]) && GET_CODE (operands[
1]) != CONST_INT)
5022 operands[
1] = force_const_mem (QImode, operands[
1]);
5023 if (! memory_address_p (QImode, XEXP (operands[
1],
0))
5024 && ! reload_in_progress)
5025 operands[
1] = change_address (operands[
1], QImode,
5026 XEXP (operands[
1],
0));
5031 [(set (match_operand:QI
0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
5032 (match_operand:QI
1 "input_operand" "r,m,r,i,*h,r,r,
0"))]
5033 "gpc_reg_operand (operands[
0], QImode)
5034 || gpc_reg_operand (operands[
1], QImode)"
5044 [(set_attr "type" "*,load,*,*,*,*,mtjmpr,*")])
5046 ;; Here is how to move condition codes around. When we store CC data in
5047 ;; an integer register or memory, we store just the high-order
4 bits.
5048 ;; This lets us not shift in the most common case of CR0.
5049 (define_expand "movcc"
5050 [(set (match_operand:CC
0 "nonimmediate_operand" "")
5051 (match_operand:CC
1 "nonimmediate_operand" ""))]
5056 [(set (match_operand:CC
0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
5057 (match_operand:CC
1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
5058 "register_operand (operands[
0], CCmode)
5059 || register_operand (operands[
1], CCmode)"
5063 {rlinm|rlwinm} %
1,%
1,%F0,
0xffffffff\;mtcrf %R0,%
1\;{rlinm|rlwinm} %
1,%
1,%f0,
0xffffffff
5065 mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%f1,
0xf0000000
5067 {l%U1%X1|lwz%U1%X1} %
0,%
1
5068 {st%U0%U1|stw%U0%U1} %
1,%
0"
5069 [(set_attr "type" "*,*,*,compare,*,*,load,*")
5070 (set_attr "length" "*,*,
12,*,
8,*,*,*")])
5072 ;; For floating-point, we normally deal with the floating-point registers
5073 ;; unless -msoft-float is used. The sole exception is that parameter passing
5074 ;; can produce floating-point values in fixed-point registers. Unless the
5075 ;; value is a simple constant or already in memory, we deal with this by
5076 ;; allocating memory and copying the value explicitly via that memory location.
5077 (define_expand "movsf"
5078 [(set (match_operand:SF
0 "nonimmediate_operand" "")
5079 (match_operand:SF
1 "any_operand" ""))]
5083 /* If we are called from reload, we might be getting a SUBREG of a hard
5084 reg. So expand it. */
5085 if (GET_CODE (operands[
0]) == SUBREG
5086 && GET_CODE (SUBREG_REG (operands[
0])) == REG
5087 && REGNO (SUBREG_REG (operands[
0])) < FIRST_PSEUDO_REGISTER)
5088 operands[
0] = alter_subreg (operands[
0]);
5089 if (GET_CODE (operands[
1]) == SUBREG
5090 && GET_CODE (SUBREG_REG (operands[
1])) == REG
5091 && REGNO (SUBREG_REG (operands[
1])) < FIRST_PSEUDO_REGISTER)
5092 operands[
1] = alter_subreg (operands[
1]);
5094 if (TARGET_SOFT_FLOAT && GET_CODE (operands[
0]) == MEM)
5095 operands[
1] = force_reg (SFmode, operands[
1]);
5097 else if (TARGET_HARD_FLOAT)
5099 if (GET_CODE (operands[
1]) == REG && REGNO (operands[
1]) <
32)
5101 /* If this is a store to memory or another integer register do the
5102 move directly. Otherwise store to a temporary stack slot and
5103 load from there into a floating point register. */
5105 if (GET_CODE (operands[
0]) == MEM
5106 || (GET_CODE (operands[
0]) == REG
5107 && (REGNO (operands[
0]) <
32
5108 || (reload_in_progress
5109 && REGNO (operands[
0]) >= FIRST_PSEUDO_REGISTER))))
5111 emit_move_insn (operand_subword (operands[
0],
0,
0, SFmode),
5112 operand_subword (operands[
1],
0,
0, SFmode));
5117 rtx stack_slot = assign_stack_temp (SFmode,
4,
0);
5119 emit_move_insn (stack_slot, operands[
1]);
5120 emit_move_insn (operands[
0], stack_slot);
5125 if (GET_CODE (operands[
0]) == MEM)
5127 /* If operands[
1] is a register, it may have double-precision data
5128 in it, so truncate it to single precision. We need not do
5129 this for POWERPC. */
5130 if (! TARGET_POWERPC && TARGET_HARD_FLOAT
5131 && GET_CODE (operands[
1]) == REG)
5134 = reload_in_progress ? operands[
1] : gen_reg_rtx (SFmode);
5135 emit_insn (gen_aux_truncdfsf2 (newreg, operands[
1]));
5136 operands[
1] = newreg;
5139 operands[
1] = force_reg (SFmode, operands[
1]);
5142 if (GET_CODE (operands[
0]) == REG && REGNO (operands[
0]) <
32)
5144 if (GET_CODE (operands[
1]) == MEM
5145 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
5146 || GET_CODE (operands[
1]) == CONST_DOUBLE
5148 || (GET_CODE (operands[
1]) == REG
5149 && (REGNO (operands[
1]) <
32
5150 || (reload_in_progress
5151 && REGNO (operands[
1]) >= FIRST_PSEUDO_REGISTER))))
5153 emit_move_insn (operand_subword (operands[
0],
0,
0, SFmode),
5154 operand_subword (operands[
1],
0,
0, SFmode));
5159 rtx stack_slot = assign_stack_temp (SFmode,
4,
0);
5161 emit_move_insn (stack_slot, operands[
1]);
5162 emit_move_insn (operands[
0], stack_slot);
5168 if (CONSTANT_P (operands[
1]))
5170 operands[
1] = force_const_mem (SFmode, operands[
1]);
5171 if (! memory_address_p (SFmode, XEXP (operands[
1],
0))
5172 && ! reload_in_progress)
5173 operands[
1] = change_address (operands[
1], SFmode,
5174 XEXP (operands[
1],
0));
5179 [(set (match_operand:SF
0 "gpc_reg_operand" "")
5180 (match_operand:SF
1 "easy_fp_constant" ""))]
5181 "reload_completed && REGNO (operands[
0]) <=
31"
5182 [(set (subreg:SI (match_dup
0)
0) (match_dup
2))]
5188 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[
1]);
5189 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
5190 operands[
2] = GEN_INT(l);
5194 [(set (match_operand:SF
0 "fp_reg_or_mem_operand" "=f,f,m")
5195 (match_operand:SF
1 "input_operand" "f,m,f"))]
5196 "(gpc_reg_operand (operands[
0], SFmode)
5197 || gpc_reg_operand (operands[
1], SFmode)) && TARGET_HARD_FLOAT"
5202 [(set_attr "type" "fp,fpload,*")])
5205 [(set (match_operand:SF
0 "nonimmediate_operand" "=r,r,m,r,r,r")
5206 (match_operand:SF
1 "input_operand" "r,m,r,I,J,R"))]
5207 "(gpc_reg_operand (operands[
0], SFmode)
5208 || gpc_reg_operand (operands[
1], SFmode)) && TARGET_SOFT_FLOAT"
5211 {l%U1%X1|lwz%U1%X1} %
0,%
1
5212 {st%U0%X0|stw%U0%X0} %
1,%
0
5216 [(set_attr "type" "*,load,*,*,*,*")])
5219 (define_expand "movdf"
5220 [(set (match_operand:DF
0 "nonimmediate_operand" "")
5221 (match_operand:DF
1 "any_operand" ""))]
5225 if (GET_CODE (operands[
0]) != REG)
5226 operands[
1] = force_reg (DFmode, operands[
1]);
5228 /* Stores between FPR and any non-FPR registers must go through a
5229 temporary stack slot. */
5231 if (TARGET_POWERPC64
5232 && GET_CODE (operands[
0]) == REG && GET_CODE (operands[
1]) == REG
5233 && ((FP_REGNO_P (REGNO (operands[
0]))
5234 && ! FP_REGNO_P (REGNO (operands[
1])))
5235 || (FP_REGNO_P (REGNO (operands[
1]))
5236 && ! FP_REGNO_P (REGNO (operands[
0])))))
5238 rtx stack_slot = assign_stack_temp (DFmode,
8,
0);
5240 emit_move_insn (stack_slot, operands[
1]);
5241 emit_move_insn (operands[
0], stack_slot);
5245 if (CONSTANT_P (operands[
1]) && ! easy_fp_constant (operands[
1], DFmode))
5247 operands[
1] = force_const_mem (DFmode, operands[
1]);
5248 if (! memory_address_p (DFmode, XEXP (operands[
1],
0))
5249 && ! reload_in_progress)
5250 operands[
1] = change_address (operands[
1], DFmode,
5251 XEXP (operands[
1],
0));
5256 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5257 (match_operand:DF
1 "easy_fp_constant" ""))]
5258 "TARGET_32BIT && reload_completed && REGNO (operands[
0]) <=
31"
5259 [(set (match_dup
2) (match_dup
3))
5260 (set (match_dup
4) (match_dup
5))]
5262 { operands[
2] = operand_subword (operands[
0],
0,
0, DFmode);
5263 operands[
3] = operand_subword (operands[
1],
0,
0, DFmode);
5264 operands[
4] = operand_subword (operands[
0],
1,
0, DFmode);
5265 operands[
5] = operand_subword (operands[
1],
1,
0, DFmode); }")
5268 [(set (match_operand:DF
0 "gpc_reg_operand" "")
5269 (match_operand:DF
1 "easy_fp_constant" ""))]
5270 "TARGET_64BIT && reload_completed && REGNO (operands[
0]) <=
31"
5271 [(set (subreg:DI (match_dup
0)
0) (subreg:DI (match_dup
1)
0))]
5274 ;; Don't have reload use general registers to load a constant. First,
5275 ;; it might not work if the output operand has is the equivalent of
5276 ;; a non-offsettable memref, but also it is less efficient than loading
5277 ;; the constant into an FP register, since it will probably be used there.
5278 ;; The "??" is a kludge until we can figure out a more reasonable way
5279 ;; of handling these non-offsettable values.
5281 [(set (match_operand:DF
0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
5282 (match_operand:DF
1 "input_operand" "r,o,r,G,f,m,f"))]
5283 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
5284 && (register_operand (operands[
0], DFmode)
5285 || register_operand (operands[
1], DFmode))"
5288 switch (which_alternative)
5291 /* We normally copy the low-numbered register first. However, if
5292 the first register operand
0 is the same as the second register of
5293 operand
1, we must copy in the opposite order. */
5294 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5295 return
\"mr %L0,%L1\;mr %
0,%
1\";
5297 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5299 /* If the low-address word is used in the address, we must load it
5300 last. Otherwise, load it first. Note that we cannot have
5301 auto-increment in that case since the address register is known to be
5303 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5305 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
5307 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
5309 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
5313 return
\"fmr %
0,%
1\";
5315 return
\"lfd%U1%X1 %
0,%
1\";
5317 return
\"stfd%U0%X0 %
1,%
0\";
5320 [(set_attr "type" "*,load,*,*,fp,fpload,*")
5321 (set_attr "length" "
8,
8,
8,
8,*,*,*")])
5324 [(set (match_operand:DF
0 "nonimmediate_operand" "=r,r,o,r")
5325 (match_operand:DF
1 "input_operand" "r,o,r,G"))]
5326 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5327 && (register_operand (operands[
0], DFmode)
5328 || register_operand (operands[
1], DFmode))"
5331 switch (which_alternative)
5334 /* We normally copy the low-numbered register first. However, if
5335 the first register operand
0 is the same as the second register of
5336 operand
1, we must copy in the opposite order. */
5337 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5338 return
\"mr %L0,%L1\;mr %
0,%
1\";
5340 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5342 /* If the low-address word is used in the address, we must load it
5343 last. Otherwise, load it first. Note that we cannot have
5344 auto-increment in that case since the address register is known to be
5346 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5348 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
5350 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
5352 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
5357 [(set_attr "type" "*,load,*,*")
5358 (set_attr "length" "
8,
8,
8,
8")])
5361 [(set (match_operand:DF
0 "nonimmediate_operand" "=!r,??r,o,!r,f,f,m")
5362 (match_operand:DF
1 "input_operand" "r,o,r,G,f,m,f"))]
5363 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
5364 && (register_operand (operands[
0], DFmode)
5365 || register_operand (operands[
1], DFmode))"
5374 [(set_attr "type" "*,load,*,*,fp,fpload,*")])
5377 [(set (match_operand:DF
0 "nonimmediate_operand" "=r,r,o,r")
5378 (match_operand:DF
1 "input_operand" "r,o,r,G"))]
5379 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
5380 && (register_operand (operands[
0], DFmode)
5381 || register_operand (operands[
1], DFmode))"
5387 [(set_attr "type" "*,load,*,*")])
5389 ;; Next come the multi-word integer load and store and the load and store
5391 (define_expand "movdi"
5392 [(set (match_operand:DI
0 "general_operand" "")
5393 (match_operand:DI
1 "any_operand" ""))]
5397 if (! TARGET_64BIT && ! general_operand (operands[
1], DImode))
5400 if (GET_CODE (operands[
0]) != REG)
5401 operands[
1] = force_reg (DImode, operands[
1]);
5403 if (GET_CODE (operands[
1]) == CONST_DOUBLE
5404 || GET_CODE (operands[
1]) == CONST_INT)
5409 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
5411 low = CONST_DOUBLE_LOW (operands[
1]);
5412 high = CONST_DOUBLE_HIGH (operands[
1]);
5415 #if HOST_BITS_PER_WIDE_INT == 32
5417 low = INTVAL (operands[
1]);
5418 high = (low <
0) ? ~
0 :
0;
5422 low = INTVAL (operands[
1]) &
0xffffffff;
5423 high = (HOST_WIDE_INT) INTVAL (operands[
1]) >>
32;
5427 if (! TARGET_POWERPC64)
5429 emit_move_insn (gen_rtx (SUBREG, SImode, operands[
0],
5430 WORDS_BIG_ENDIAN), GEN_INT (low));
5432 emit_move_insn (gen_rtx (SUBREG, SImode, operands[
0],
5433 ! WORDS_BIG_ENDIAN), GEN_INT (high));
5438 if (high +
0x8000 >=
0x10000)
5440 emit_move_insn (gen_rtx (SUBREG, SImode, operands[
0],
1),
5442 emit_insn (gen_ashldi3 (operands[
0], operands[
0], GEN_INT(
32)));
5445 HOST_WIDE_INT low_low = low &
0xffff;
5446 HOST_WIDE_INT low_high = low & (~ (HOST_WIDE_INT)
0xffff);
5448 emit_insn (gen_iordi3 (operands[
0], operands[
0],
5449 GEN_INT (low_high)));
5451 emit_insn (gen_iordi3 (operands[
0], operands[
0],
5452 GEN_INT (low_low)));
5456 emit_move_insn (gen_rtx (SUBREG, SImode, operands[
0],
1),
5462 /* Stores between FPR and any non-FPR registers must go through a
5463 temporary stack slot. */
5465 if (GET_CODE (operands[
0]) == REG && GET_CODE (operands[
1]) == REG
5466 && ((FP_REGNO_P (REGNO (operands[
0]))
5467 && ! FP_REGNO_P (REGNO (operands[
1])))
5468 || (FP_REGNO_P (REGNO (operands[
1]))
5469 && ! FP_REGNO_P (REGNO (operands[
0])))))
5471 rtx stack_slot = assign_stack_temp (DImode,
8,
0);
5473 emit_move_insn (stack_slot, operands[
1]);
5474 emit_move_insn (operands[
0], stack_slot);
5480 [(set (match_operand:DI
0 "nonimmediate_operand" "=r,r,m,f,f,m")
5481 (match_operand:DI
1 "input_operand" "r,m,r,f,m,f"))]
5482 "! TARGET_POWERPC64 && (gpc_reg_operand (operands[
0], DImode)
5483 || gpc_reg_operand (operands[
1], DImode))"
5486 switch (which_alternative)
5489 /* We normally copy the low-numbered register first. However, if
5490 the first register operand
0 is the same as the second register of
5491 operand
1, we must copy in the opposite order. */
5492 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5493 return
\"mr %L0,%L1\;mr %
0,%
1\";
5495 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5497 /* If the low-address word is used in the address, we must load it
5498 last. Otherwise, load it first. Note that we cannot have
5499 auto-increment in that case since the address register is known to be
5501 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5503 return
\"{l|lwz} %L0,%L1\;{l|lwz} %
0,%
1\";
5505 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1
\";
5507 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0
\";
5509 return
\"fmr %
0,%
1\";
5511 return
\"lfd%U1%X1 %
0,%
1\";
5513 return
\"stfd%U0%X0 %
1,%
0\";
5516 [(set_attr "type" "*,load,*,fp,fpload,*")
5517 (set_attr "length" "
8,
8,
8,*,*,*")])
5520 [(set (match_operand:DI
0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
5521 (match_operand:DI
1 "input_operand" "r,m,r,I,J,n,R,f,m,f,*h,r,
0"))]
5522 "TARGET_POWERPC64 && (gpc_reg_operand (operands[
0], DImode)
5523 || gpc_reg_operand (operands[
1], DImode))"
5538 [(set_attr "type" "*,load,*,*,*,*,*,fp,fpload,*,*,mtjmpr,*")
5539 (set_attr "length" "
4,
4,
4,
4,
4,
20,
4,
4,
4,
4,
4,
4,
4")])
5541 ;; Split a load of a large constant into the appropriate five-instruction
5542 ;; sequence. The expansion in movdi tries to perform the minimum number of
5543 ;; steps, but here we have to handle anything in a constant number of insns.
5546 [(set (match_operand:DI
0 "gpc_reg_operand" "")
5547 (match_operand:DI
1 "const_double_operand" ""))]
5552 (ior:DI (match_dup
0)
5555 (ashift:DI (match_dup
0)
5558 (ior:DI (match_dup
0)
5561 (ior:DI (match_dup
0)
5568 if (GET_CODE (operands[
1]) == CONST_DOUBLE)
5570 low = CONST_DOUBLE_LOW (operands[
1]);
5571 high = CONST_DOUBLE_HIGH (operands[
1]);
5574 #if HOST_BITS_PER_WIDE_INT == 32
5576 low = INTVAL (operands[
1]);
5577 high = (low <
0) ? ~
0 :
0;
5581 low = INTVAL (operands[
1]) &
0xffffffff;
5582 high = (HOST_WIDE_INT) INTVAL (operands[
1]) >>
32;
5586 if ((high +
0x8000) <
0x10000
5587 && ((low &
0xffff) ==
0 || (low & (~ (HOST_WIDE_INT)
0xffff)) ==
0))
5590 operands[
2] = GEN_INT (high & (~ (HOST_WIDE_INT)
0xffff));
5591 operands[
3] = GEN_INT (high &
0xffff);
5592 operands[
4] = GEN_INT (low & (~ (HOST_WIDE_INT)
0xffff));
5593 operands[
5] = GEN_INT (low &
0xffff);
5597 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
5598 (compare:CC (match_operand:DI
1 "gpc_reg_operand" "r")
5600 (set (match_operand:DI
0 "gpc_reg_operand" "=r") (match_dup
1))]
5603 [(set_attr "type" "compare")])
5605 ;; TImode is similar, except that we usually want to compute the address into
5606 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
5607 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
5608 (define_expand "movti"
5609 [(parallel [(set (match_operand:TI
0 "general_operand" "")
5610 (match_operand:TI
1 "general_operand" ""))
5611 (clobber (scratch:SI))])]
5612 "TARGET_STRING || TARGET_POWERPC64"
5615 if (GET_CODE (operands[
0]) == MEM)
5616 operands[
1] = force_reg (TImode, operands[
1]);
5618 if (GET_CODE (operands[
0]) == MEM
5619 && GET_CODE (XEXP (operands[
0],
0)) != REG
5620 && ! reload_in_progress)
5621 operands[
0] = change_address (operands[
0], TImode,
5622 copy_addr_to_reg (XEXP (operands[
0],
0)));
5624 if (GET_CODE (operands[
1]) == MEM
5625 && GET_CODE (XEXP (operands[
1],
0)) != REG
5626 && ! reload_in_progress)
5627 operands[
1] = change_address (operands[
1], TImode,
5628 copy_addr_to_reg (XEXP (operands[
1],
0)));
5631 ;; We say that MQ is clobbered in the last alternative because the first
5632 ;; alternative would never get used otherwise since it would need a reload
5633 ;; while the
2nd alternative would not. We put memory cases first so they
5634 ;; are preferred. Otherwise, we'd try to reload the output instead of
5635 ;; giving the SCRATCH mq.
5637 [(set (match_operand:TI
0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
5638 (match_operand:TI
1 "reg_or_mem_operand" "r,r,r,Q,m"))
5639 (clobber (match_scratch:SI
2 "=q,q#X,X,X,X"))]
5640 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
5641 && (gpc_reg_operand (operands[
0], TImode) || gpc_reg_operand (operands[
1], TImode))"
5644 switch (which_alternative)
5650 return
\"{stsi|stswi} %
1,%P0,
16\";
5653 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0
\";
5656 /* Normally copy registers with lowest numbered register copied first.
5657 But copy in the other order if the first register of the output
5658 is the second, third, or fourth register in the input. */
5659 if (REGNO (operands[
0]) >= REGNO (operands[
1]) +
1
5660 && REGNO (operands[
0]) <= REGNO (operands[
1]) +
3)
5661 return
\"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %
0,%
1\";
5663 return
\"mr %
0,%
1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1
\";
5665 /* If the address is not used in the output, we can use lsi. Otherwise,
5666 fall through to generating four loads. */
5667 if (! reg_overlap_mentioned_p (operands[
0], operands[
1]))
5668 return
\"{lsi|lswi} %
0,%P1,
16\";
5669 /* ... fall through ... */
5671 /* If the address register is the same as the register for the lowest-
5672 addressed word, load it last. Similarly for the next two words.
5673 Otherwise load lowest address to highest. */
5674 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5676 return
\"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %
0,%
1\";
5677 else if (refers_to_regno_p (REGNO (operands[
0]) +
1,
5678 REGNO (operands[
0]) +
2, operands[
1],
0))
5679 return
\"{l|lwz} %
0,%
1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1
\";
5680 else if (refers_to_regno_p (REGNO (operands[
0]) +
2,
5681 REGNO (operands[
0]) +
3, operands[
1],
0))
5682 return
\"{l|lwz} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1
\";
5684 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1
\";
5687 [(set_attr "type" "*,load,load,*,*")
5688 (set_attr "length" "*,
16,
16,*,
16")])
5691 [(set (match_operand:TI
0 "reg_or_mem_operand" "=m,????r,????r")
5692 (match_operand:TI
1 "reg_or_mem_operand" "r,r,m"))
5693 (clobber (match_scratch:SI
2 "=X,X,X"))]
5694 "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
5695 && (gpc_reg_operand (operands[
0], TImode) || gpc_reg_operand (operands[
1], TImode))"
5698 switch (which_alternative)
5704 return
\"{st%U0|stw%U0} %
1,%
0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0
\";
5707 /* Normally copy registers with lowest numbered register copied first.
5708 But copy in the other order if the first register of the output
5709 is the second, third, or fourth register in the input. */
5710 if (REGNO (operands[
0]) >= REGNO (operands[
1]) +
1
5711 && REGNO (operands[
0]) <= REGNO (operands[
1]) +
3)
5712 return
\"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %
0,%
1\";
5714 return
\"mr %
0,%
1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1
\";
5716 /* If the address register is the same as the register for the lowest-
5717 addressed word, load it last. Similarly for the next two words.
5718 Otherwise load lowest address to highest. */
5719 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5721 return
\"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %
0,%
1\";
5722 else if (refers_to_regno_p (REGNO (operands[
0]) +
1,
5723 REGNO (operands[
0]) +
2, operands[
1],
0))
5724 return
\"{l|lwz} %
0,%
1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1
\";
5725 else if (refers_to_regno_p (REGNO (operands[
0]) +
2,
5726 REGNO (operands[
0]) +
3, operands[
1],
0))
5727 return
\"{l|lwz} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1
\";
5729 return
\"{l%U1|lwz%U1} %
0,%
1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1
\";
5732 [(set_attr "type" "load,*,*")
5733 (set_attr "length" "
16,
16,
16")])
5736 [(set (match_operand:TI
0 "nonimmediate_operand" "=r,r,m")
5737 (match_operand:TI
1 "input_operand" "r,m,r"))]
5738 "TARGET_POWERPC64 && (gpc_reg_operand (operands[
0], TImode)
5739 || gpc_reg_operand (operands[
1], TImode))"
5742 switch (which_alternative)
5745 /* We normally copy the low-numbered register first. However, if
5746 the first register operand
0 is the same as the second register of
5747 operand
1, we must copy in the opposite order. */
5748 if (REGNO (operands[
0]) == REGNO (operands[
1]) +
1)
5749 return
\"mr %L0,%L1\;mr %
0,%
1\";
5751 return
\"mr %
0,%
1\;mr %L0,%L1
\";
5753 /* If the low-address word is used in the address, we must load it
5754 last. Otherwise, load it first. Note that we cannot have
5755 auto-increment in that case since the address register is known to be
5757 if (refers_to_regno_p (REGNO (operands[
0]), REGNO (operands[
0]) +
1,
5759 return
\"ld %L0,%L1\;ld %
0,%
1\";
5761 return
\"ld%U1 %
0,%
1\;ld %L0,%L1
\";
5763 return
\"std%U0 %
1,%
0\;std %L1,%L0
\";
5766 [(set_attr "type" "*,load,*")
5767 (set_attr "length" "
8,
8,
8")])
5769 (define_expand "load_multiple"
5770 [(match_par_dup
3 [(set (match_operand:SI
0 "" "")
5771 (match_operand:SI
1 "" ""))
5772 (use (match_operand:SI
2 "" ""))])]
5781 /* Support only loading a constant number of fixed-point registers from
5782 memory and only bother with this if more than two; the machine
5783 doesn't support more than eight. */
5784 if (GET_CODE (operands[
2]) != CONST_INT
5785 || INTVAL (operands[
2]) <=
2
5786 || INTVAL (operands[
2]) >
8
5787 || GET_CODE (operands[
1]) != MEM
5788 || GET_CODE (operands[
0]) != REG
5789 || REGNO (operands[
0]) >=
32)
5792 count = INTVAL (operands[
2]);
5793 regno = REGNO (operands[
0]);
5795 operands[
3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
5796 from = force_reg (SImode, XEXP (operands[
1],
0));
5798 for (i =
0; i < count; i++)
5799 XVECEXP (operands[
3],
0, i)
5800 = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
5801 gen_rtx (MEM, SImode, plus_constant (from, i *
4)));
5805 [(match_parallel
0 "load_multiple_operation"
5806 [(set (match_operand:SI
1 "gpc_reg_operand" "=r")
5807 (mem:SI (match_operand:SI
2 "register_operand" "b")))])]
5811 /* We have to handle the case where the pseudo used to contain the address
5812 is assigned to one of the output registers. */
5814 int words = XVECLEN (operands[
0],
0);
5817 if (XVECLEN (operands[
0],
0) ==
1)
5818 return
\"{l|lwz} %
1,
0(%
2)
\";
5820 for (i =
0; i < words; i++)
5821 if (refers_to_regno_p (REGNO (operands[
1]) + i,
5822 REGNO (operands[
1]) + i +
1, operands[
2],
0))
5826 xop[
0] = operands[
1];
5827 xop[
1] = operands[
2];
5828 xop[
2] = GEN_INT (
4 * (words-
1));
5829 output_asm_insn (
\"{lsi|lswi} %
0,%
1,%
2\;{l|lwz} %
1,%
2(%
1)
\", xop);
5834 xop[
0] = operands[
1];
5835 xop[
1] = gen_rtx (REG, SImode, REGNO (operands[
1]) +
1);
5836 xop[
2] = GEN_INT (
4 * (words-
1));
5837 output_asm_insn (
\"{cal %
0,
4(%
0)|addi %
0,%
0,
4}\;{lsi|lswi} %
1,%
0,%
2\;{l|lwz} %
0,-
4(%
0)
\", xop);
5842 for (j =
0; j < words; j++)
5845 xop[
0] = gen_rtx (REG, SImode, REGNO (operands[
1]) + j);
5846 xop[
1] = operands[
2];
5847 xop[
2] = GEN_INT (j *
4);
5848 output_asm_insn (
\"{l|lwz} %
0,%
2(%
1)
\", xop);
5850 xop[
0] = operands[
2];
5851 xop[
1] = GEN_INT (i *
4);
5852 output_asm_insn (
\"{l|lwz} %
0,%
1(%
0)
\", xop);
5857 return
\"{lsi|lswi} %
1,%
2,%N0
\";
5859 [(set_attr "type" "load")
5860 (set_attr "length" "
32")])
5863 (define_expand "store_multiple"
5864 [(match_par_dup
3 [(set (match_operand:SI
0 "" "")
5865 (match_operand:SI
1 "" ""))
5866 (clobber (scratch:SI))
5867 (use (match_operand:SI
2 "" ""))])]
5876 /* Support only storing a constant number of fixed-point registers to
5877 memory and only bother with this if more than two; the machine
5878 doesn't support more than eight. */
5879 if (GET_CODE (operands[
2]) != CONST_INT
5880 || INTVAL (operands[
2]) <=
2
5881 || INTVAL (operands[
2]) >
8
5882 || GET_CODE (operands[
0]) != MEM
5883 || GET_CODE (operands[
1]) != REG
5884 || REGNO (operands[
1]) >=
32)
5887 count = INTVAL (operands[
2]);
5888 regno = REGNO (operands[
1]);
5890 operands[
3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count +
1));
5891 to = force_reg (SImode, XEXP (operands[
0],
0));
5893 XVECEXP (operands[
3],
0,
0)
5894 = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[
1]);
5895 XVECEXP (operands[
3],
0,
1) = gen_rtx (CLOBBER, VOIDmode,
5896 gen_rtx (SCRATCH, SImode));
5898 for (i =
1; i < count; i++)
5899 XVECEXP (operands[
3],
0, i +
1)
5900 = gen_rtx (SET, VOIDmode,
5901 gen_rtx (MEM, SImode, plus_constant (to, i *
4)),
5902 gen_rtx (REG, SImode, regno + i));
5906 [(match_parallel
0 "store_multiple_operation"
5907 [(set (match_operand:SI
1 "indirect_operand" "=Q")
5908 (match_operand:SI
2 "gpc_reg_operand" "r"))
5909 (clobber (match_scratch:SI
3 "=q"))])]
5910 "TARGET_STRING && TARGET_POWER"
5911 "{stsi|stswi} %
2,%P1,%O0")
5914 [(match_parallel
0 "store_multiple_operation"
5915 [(set (mem:SI (match_operand:SI
1 "register_operand" "b"))
5916 (match_operand:SI
2 "gpc_reg_operand" "r"))
5917 (clobber (match_scratch:SI
3 "X"))])]
5918 "TARGET_STRING && !TARGET_POWER"
5919 "{stsi|stswi} %
2,%
1,%O0")
5922 ;; String/block move insn.
5923 ;; Argument
0 is the destination
5924 ;; Argument
1 is the source
5925 ;; Argument
2 is the length
5926 ;; Argument
3 is the alignment
5928 (define_expand "movstrsi"
5929 [(parallel [(set (match_operand:BLK
0 "" "")
5930 (match_operand:BLK
1 "" ""))
5931 (use (match_operand:SI
2 "" ""))
5932 (use (match_operand:SI
3 "" ""))])]
5936 if (expand_block_move (operands))
5942 ;; Move up to
32 bytes at a time. The fixed registers are needed because the
5943 ;; register allocator doesn't have a clue about allocating
8 word registers
5944 (define_expand "movstrsi_8reg"
5945 [(parallel [(set (match_operand
0 "" "")
5946 (match_operand
1 "" ""))
5947 (use (match_operand
2 "" ""))
5948 (use (match_operand
3 "" ""))
5949 (clobber (reg:SI
5))
5950 (clobber (reg:SI
6))
5951 (clobber (reg:SI
7))
5952 (clobber (reg:SI
8))
5953 (clobber (reg:SI
9))
5954 (clobber (reg:SI
10))
5955 (clobber (reg:SI
11))
5956 (clobber (reg:SI
12))
5957 (clobber (match_scratch:SI
4 ""))])]
5962 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
5963 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
5964 (use (match_operand:SI
2 "immediate_operand" "i"))
5965 (use (match_operand:SI
3 "immediate_operand" "i"))
5966 (clobber (match_operand:SI
4 "register_operand" "=r"))
5967 (clobber (reg:SI
6))
5968 (clobber (reg:SI
7))
5969 (clobber (reg:SI
8))
5970 (clobber (reg:SI
9))
5971 (clobber (reg:SI
10))
5972 (clobber (reg:SI
11))
5973 (clobber (reg:SI
12))
5974 (clobber (match_scratch:SI
5 "=q"))]
5975 "TARGET_STRING && TARGET_POWER
5976 && ((INTVAL (operands[
2]) >
24 && INTVAL (operands[
2]) <
32) || INTVAL (operands[
2]) ==
0)
5977 && (REGNO (operands[
0]) <
5 || REGNO (operands[
0]) >
12)
5978 && (REGNO (operands[
1]) <
5 || REGNO (operands[
1]) >
12)
5979 && REGNO (operands[
4]) ==
5"
5980 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
5981 [(set_attr "length" "
8")])
5984 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
5985 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
5986 (use (match_operand:SI
2 "immediate_operand" "i"))
5987 (use (match_operand:SI
3 "immediate_operand" "i"))
5988 (clobber (match_operand:SI
4 "register_operand" "=r"))
5989 (clobber (reg:SI
6))
5990 (clobber (reg:SI
7))
5991 (clobber (reg:SI
8))
5992 (clobber (reg:SI
9))
5993 (clobber (reg:SI
10))
5994 (clobber (reg:SI
11))
5995 (clobber (reg:SI
12))
5996 (clobber (match_scratch:SI
5 "X"))]
5997 "TARGET_STRING && !TARGET_POWER
5998 && ((INTVAL (operands[
2]) >
24 && INTVAL (operands[
2]) <
32) || INTVAL (operands[
2]) ==
0)
5999 && (REGNO (operands[
0]) <
5 || REGNO (operands[
0]) >
12)
6000 && (REGNO (operands[
1]) <
5 || REGNO (operands[
1]) >
12)
6001 && REGNO (operands[
4]) ==
5"
6002 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6003 [(set_attr "length" "
8")])
6005 ;; Move up to
24 bytes at a time. The fixed registers are needed because the
6006 ;; register allocator doesn't have a clue about allocating
6 word registers
6007 (define_expand "movstrsi_6reg"
6008 [(parallel [(set (match_operand
0 "" "")
6009 (match_operand
1 "" ""))
6010 (use (match_operand
2 "" ""))
6011 (use (match_operand
3 "" ""))
6012 (clobber (reg:SI
7))
6013 (clobber (reg:SI
8))
6014 (clobber (reg:SI
9))
6015 (clobber (reg:SI
10))
6016 (clobber (reg:SI
11))
6017 (clobber (reg:SI
12))
6018 (clobber (match_scratch:SI
4 ""))])]
6023 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6024 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6025 (use (match_operand:SI
2 "immediate_operand" "i"))
6026 (use (match_operand:SI
3 "immediate_operand" "i"))
6027 (clobber (match_operand:SI
4 "register_operand" "=r"))
6028 (clobber (reg:SI
8))
6029 (clobber (reg:SI
9))
6030 (clobber (reg:SI
10))
6031 (clobber (reg:SI
11))
6032 (clobber (reg:SI
12))
6033 (clobber (match_scratch:SI
5 "=q"))]
6034 "TARGET_STRING && TARGET_POWER
6035 && INTVAL (operands[
2]) >
16 && INTVAL (operands[
2]) <=
24
6036 && (REGNO (operands[
0]) <
7 || REGNO (operands[
0]) >
12)
6037 && (REGNO (operands[
1]) <
7 || REGNO (operands[
1]) >
12)
6038 && REGNO (operands[
4]) ==
7"
6039 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6040 [(set_attr "length" "
8")])
6043 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6044 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6045 (use (match_operand:SI
2 "immediate_operand" "i"))
6046 (use (match_operand:SI
3 "immediate_operand" "i"))
6047 (clobber (match_operand:SI
4 "register_operand" "=r"))
6048 (clobber (reg:SI
8))
6049 (clobber (reg:SI
9))
6050 (clobber (reg:SI
10))
6051 (clobber (reg:SI
11))
6052 (clobber (reg:SI
12))
6053 (clobber (match_scratch:SI
5 "X"))]
6054 "TARGET_STRING && !TARGET_POWER
6055 && INTVAL (operands[
2]) >
16 && INTVAL (operands[
2]) <=
32
6056 && (REGNO (operands[
0]) <
7 || REGNO (operands[
0]) >
12)
6057 && (REGNO (operands[
1]) <
7 || REGNO (operands[
1]) >
12)
6058 && REGNO (operands[
4]) ==
7"
6059 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6060 [(set_attr "length" "
8")])
6062 ;; Move up to
16 bytes at a time, using
4 fixed registers to avoid spill problems
6064 (define_expand "movstrsi_4reg"
6065 [(parallel [(set (match_operand
0 "" "")
6066 (match_operand
1 "" ""))
6067 (use (match_operand
2 "" ""))
6068 (use (match_operand
3 "" ""))
6069 (clobber (reg:SI
9))
6070 (clobber (reg:SI
10))
6071 (clobber (reg:SI
11))
6072 (clobber (reg:SI
12))
6073 (clobber (match_scratch:SI
4 ""))])]
6078 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6079 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6080 (use (match_operand:SI
2 "immediate_operand" "i"))
6081 (use (match_operand:SI
3 "immediate_operand" "i"))
6082 (clobber (match_operand:SI
4 "register_operand" "=r"))
6083 (clobber (reg:SI
10))
6084 (clobber (reg:SI
11))
6085 (clobber (reg:SI
12))
6086 (clobber (match_scratch:SI
5 "=q"))]
6087 "TARGET_STRING && TARGET_POWER
6088 && INTVAL (operands[
2]) >
8 && INTVAL (operands[
2]) <=
16
6089 && (REGNO (operands[
0]) <
9 || REGNO (operands[
0]) >
12)
6090 && (REGNO (operands[
1]) <
9 || REGNO (operands[
1]) >
12)
6091 && REGNO (operands[
4]) ==
9"
6092 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6093 [(set_attr "length" "
8")])
6096 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6097 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6098 (use (match_operand:SI
2 "immediate_operand" "i"))
6099 (use (match_operand:SI
3 "immediate_operand" "i"))
6100 (clobber (match_operand:SI
4 "register_operand" "=r"))
6101 (clobber (reg:SI
10))
6102 (clobber (reg:SI
11))
6103 (clobber (reg:SI
12))
6104 (clobber (match_scratch:SI
5 "X"))]
6105 "TARGET_STRING && !TARGET_POWER
6106 && INTVAL (operands[
2]) >
8 && INTVAL (operands[
2]) <=
16
6107 && (REGNO (operands[
0]) <
9 || REGNO (operands[
0]) >
12)
6108 && (REGNO (operands[
1]) <
9 || REGNO (operands[
1]) >
12)
6109 && REGNO (operands[
4]) ==
9"
6110 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6111 [(set_attr "length" "
8")])
6113 ;; Move up to
8 bytes at a time.
6114 (define_expand "movstrsi_2reg"
6115 [(parallel [(set (match_operand
0 "" "")
6116 (match_operand
1 "" ""))
6117 (use (match_operand
2 "" ""))
6118 (use (match_operand
3 "" ""))
6119 (clobber (match_scratch:DI
4 ""))
6120 (clobber (match_scratch:SI
5 ""))])]
6121 "TARGET_STRING && !TARGET_64BIT"
6125 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6126 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6127 (use (match_operand:SI
2 "immediate_operand" "i"))
6128 (use (match_operand:SI
3 "immediate_operand" "i"))
6129 (clobber (match_scratch:DI
4 "=&r"))
6130 (clobber (match_scratch:SI
5 "=q"))]
6131 "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
6132 && INTVAL (operands[
2]) >
4 && INTVAL (operands[
2]) <=
8"
6133 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6134 [(set_attr "length" "
8")])
6137 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6138 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6139 (use (match_operand:SI
2 "immediate_operand" "i"))
6140 (use (match_operand:SI
3 "immediate_operand" "i"))
6141 (clobber (match_scratch:DI
4 "=&r"))
6142 (clobber (match_scratch:SI
5 "X"))]
6143 "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
6144 && INTVAL (operands[
2]) >
4 && INTVAL (operands[
2]) <=
8"
6145 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6146 [(set_attr "length" "
8")])
6148 ;; Move up to
4 bytes at a time.
6149 (define_expand "movstrsi_1reg"
6150 [(parallel [(set (match_operand
0 "" "")
6151 (match_operand
1 "" ""))
6152 (use (match_operand
2 "" ""))
6153 (use (match_operand
3 "" ""))
6154 (clobber (match_scratch:SI
4 ""))
6155 (clobber (match_scratch:SI
5 ""))])]
6160 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6161 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6162 (use (match_operand:SI
2 "immediate_operand" "i"))
6163 (use (match_operand:SI
3 "immediate_operand" "i"))
6164 (clobber (match_scratch:SI
4 "=&r"))
6165 (clobber (match_scratch:SI
5 "=q"))]
6166 "TARGET_STRING && TARGET_POWER
6167 && INTVAL (operands[
2]) >
0 && INTVAL (operands[
2]) <=
4"
6168 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6169 [(set_attr "length" "
8")])
6172 [(set (mem:BLK (match_operand:SI
0 "register_operand" "b"))
6173 (mem:BLK (match_operand:SI
1 "register_operand" "b")))
6174 (use (match_operand:SI
2 "immediate_operand" "i"))
6175 (use (match_operand:SI
3 "immediate_operand" "i"))
6176 (clobber (match_scratch:SI
4 "=&r"))
6177 (clobber (match_scratch:SI
5 "X"))]
6178 "TARGET_STRING && !TARGET_POWER
6179 && INTVAL (operands[
2]) >
0 && INTVAL (operands[
2]) <=
4"
6180 "{lsi|lswi} %
4,%
1,%
2\;{stsi|stswi} %
4,%
0,%
2"
6181 [(set_attr "length" "
8")])
6184 ;; Define insns that do load or store with update. Some of these we can
6185 ;; get by using pre-decrement or pre-increment, but the hardware can also
6186 ;; do cases where the increment is not the size of the object.
6188 ;; In all these cases, we use operands
0 and
1 for the register being
6189 ;; incremented because those are the operands that local-alloc will
6190 ;; tie and these are the pair most likely to be tieable (and the ones
6191 ;; that will benefit the most).
6194 [(set (match_operand:DI
3 "gpc_reg_operand" "=r,r")
6195 (mem:DI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0,
0")
6196 (match_operand:DI
2 "reg_or_short_operand" "r,I"))))
6197 (set (match_operand:DI
0 "gpc_reg_operand" "=b,b")
6198 (plus:DI (match_dup
1) (match_dup
2)))]
6203 [(set_attr "type" "load")])
6206 [(set (match_operand:DI
3 "gpc_reg_operand" "=r")
6208 (mem:SI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0")
6209 (match_operand:DI
2 "gpc_reg_operand" "r")))))
6210 (set (match_operand:DI
0 "gpc_reg_operand" "=b")
6211 (plus:DI (match_dup
1) (match_dup
2)))]
6214 [(set_attr "type" "load")])
6216 (define_insn "movdi_update"
6217 [(set (mem:DI (plus:DI (match_operand:DI
1 "gpc_reg_operand" "
0,
0")
6218 (match_operand:DI
2 "reg_or_short_operand" "r,I")))
6219 (match_operand:DI
3 "gpc_reg_operand" "r,r"))
6220 (set (match_operand:DI
0 "gpc_reg_operand" "=b,b")
6221 (plus:DI (match_dup
1) (match_dup
2)))]
6228 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6229 (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6230 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6231 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6232 (plus:SI (match_dup
1) (match_dup
2)))]
6235 {lux|lwzux} %
3,%
0,%
2
6236 {lu|lwzu} %
3,%
2(%
0)"
6237 [(set_attr "type" "load")])
6239 (define_insn "movsi_update"
6240 [(set (mem:SI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6241 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6242 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
6243 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6244 (plus:SI (match_dup
1) (match_dup
2)))]
6247 {stux|stwux} %
3,%
0,%
2
6248 {stu|stwu} %
3,%
2(%
0)")
6251 [(set (match_operand:HI
3 "gpc_reg_operand" "=r,r")
6252 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6253 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6254 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6255 (plus:SI (match_dup
1) (match_dup
2)))]
6260 [(set_attr "type" "load")])
6263 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6265 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6266 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
6267 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6268 (plus:SI (match_dup
1) (match_dup
2)))]
6273 [(set_attr "type" "load")])
6276 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6278 (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6279 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
6280 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6281 (plus:SI (match_dup
1) (match_dup
2)))]
6286 [(set_attr "type" "load")])
6289 [(set (mem:HI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6290 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6291 (match_operand:HI
3 "gpc_reg_operand" "r,r"))
6292 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6293 (plus:SI (match_dup
1) (match_dup
2)))]
6300 [(set (match_operand:QI
3 "gpc_reg_operand" "=r,r")
6301 (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6302 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6303 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6304 (plus:SI (match_dup
1) (match_dup
2)))]
6309 [(set_attr "type" "load")])
6312 [(set (match_operand:SI
3 "gpc_reg_operand" "=r,r")
6314 (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6315 (match_operand:SI
2 "reg_or_short_operand" "r,I")))))
6316 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6317 (plus:SI (match_dup
1) (match_dup
2)))]
6322 [(set_attr "type" "load")])
6325 [(set (mem:QI (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6326 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6327 (match_operand:QI
3 "gpc_reg_operand" "r,r"))
6328 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6329 (plus:SI (match_dup
1) (match_dup
2)))]
6336 [(set (match_operand:SF
3 "gpc_reg_operand" "=f,f")
6337 (mem:SF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6338 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6339 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6340 (plus:SI (match_dup
1) (match_dup
2)))]
6345 [(set_attr "type" "fpload")])
6348 [(set (mem:SF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6349 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6350 (match_operand:SF
3 "gpc_reg_operand" "f,f"))
6351 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6352 (plus:SI (match_dup
1) (match_dup
2)))]
6359 [(set (match_operand:DF
3 "gpc_reg_operand" "=f,f")
6360 (mem:DF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6361 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))
6362 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6363 (plus:SI (match_dup
1) (match_dup
2)))]
6368 [(set_attr "type" "fpload")])
6371 [(set (mem:DF (plus:SI (match_operand:SI
1 "gpc_reg_operand" "
0,
0")
6372 (match_operand:SI
2 "reg_or_short_operand" "r,I")))
6373 (match_operand:DF
3 "gpc_reg_operand" "f,f"))
6374 (set (match_operand:SI
0 "gpc_reg_operand" "=b,b")
6375 (plus:SI (match_dup
1) (match_dup
2)))]
6381 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
6384 [(set (match_operand:DF
0 "gpc_reg_operand" "=f")
6385 (match_operand:DF
1 "memory_operand" ""))
6386 (set (match_operand:DF
2 "gpc_reg_operand" "=f")
6387 (match_operand:DF
3 "memory_operand" ""))]
6389 && TARGET_HARD_FLOAT
6390 && registers_ok_for_quad_peep (operands[
0], operands[
2])
6391 && ! MEM_VOLATILE_P (operands[
1]) && ! MEM_VOLATILE_P (operands[
3])
6392 && addrs_ok_for_quad_peep (XEXP (operands[
1],
0), XEXP (operands[
3],
0))"
6396 [(set (match_operand:DF
0 "memory_operand" "")
6397 (match_operand:DF
1 "gpc_reg_operand" "f"))
6398 (set (match_operand:DF
2 "memory_operand" "")
6399 (match_operand:DF
3 "gpc_reg_operand" "f"))]
6401 && TARGET_HARD_FLOAT
6402 && registers_ok_for_quad_peep (operands[
1], operands[
3])
6403 && ! MEM_VOLATILE_P (operands[
0]) && ! MEM_VOLATILE_P (operands[
2])
6404 && addrs_ok_for_quad_peep (XEXP (operands[
0],
0), XEXP (operands[
2],
0))"
6407 ;; Next come insns related to the calling sequence.
6409 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
6410 ;; We move the back-chain and decrement the stack pointer.
6412 (define_expand "allocate_stack"
6414 (minus:SI (reg:SI
1) (match_operand:SI
0 "reg_or_short_operand" "")))]
6417 { rtx chain = gen_reg_rtx (Pmode);
6418 rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
6421 emit_move_insn (chain, stack_bot);
6423 /* Under Windows NT, we need to add stack probes for large/variable allocations,
6424 so do it via a call to the external function alloca, instead of doing it
6426 if (DEFAULT_ABI == ABI_NT
6427 && (GET_CODE (operands[
0]) != CONST_INT || INTVAL (operands[
0]) >
4096))
6429 rtx tmp = gen_reg_rtx (SImode);
6430 emit_library_call_value (gen_rtx (SYMBOL_REF, Pmode,
\"__allocate_stack
\"),
6431 tmp,
0, SImode,
1, operands[
0], Pmode);
6432 emit_insn (gen_set_sp (tmp));
6436 if (GET_CODE (operands[
0]) != CONST_INT
6437 || INTVAL (operands[
0]) < -
32767
6438 || INTVAL (operands[
0]) >
32768)
6440 neg_op0 = gen_reg_rtx (Pmode);
6442 emit_insn (gen_negsi2 (neg_op0, operands[
0]));
6444 emit_insn (gen_negdi2 (neg_op0, operands[
0]));
6447 neg_op0 = GEN_INT (- INTVAL (operands[
0]));
6450 emit_insn (gen_movsi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
6452 emit_insn (gen_movdi_update (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
6457 ;; Marker to indicate that the stack pointer was changed under NT in
6458 ;; ways not known to the compiler
6460 (define_insn "set_sp"
6462 (unspec [(match_operand:SI
0 "register_operand" "r")]
7))]
6465 [(set_attr "length" "
0")])
6467 ;; These patterns say how to save and restore the stack pointer. We need not
6468 ;; save the stack pointer at function level since we are careful to
6469 ;; preserve the backchain. At block level, we have to restore the backchain
6470 ;; when we restore the stack pointer.
6472 ;; For nonlocal gotos, we must save both the stack pointer and its
6473 ;; backchain and restore both. Note that in the nonlocal case, the
6474 ;; save area is a memory location.
6476 (define_expand "save_stack_function"
6477 [(use (const_int
0))]
6481 (define_expand "restore_stack_function"
6482 [(use (const_int
0))]
6486 (define_expand "restore_stack_block"
6487 [(set (match_dup
2) (mem:SI (match_operand:SI
0 "register_operand" "")))
6488 (set (match_dup
0) (match_operand:SI
1 "register_operand" ""))
6489 (set (mem:SI (match_dup
0)) (match_dup
2))]
6492 { operands[
2] = gen_reg_rtx (SImode); }")
6494 (define_expand "save_stack_nonlocal"
6495 [(match_operand:DI
0 "memory_operand" "")
6496 (match_operand:SI
1 "register_operand" "")]
6500 rtx temp = gen_reg_rtx (SImode);
6502 /* Copy the backchain to the first word, sp to the second. */
6503 emit_move_insn (temp, gen_rtx (MEM, SImode, operands[
1]));
6504 emit_move_insn (operand_subword (operands[
0],
0,
0, DImode), temp);
6505 emit_move_insn (operand_subword (operands[
0],
1,
0, DImode), operands[
1]);
6509 (define_expand "restore_stack_nonlocal"
6510 [(match_operand:SI
0 "register_operand" "")
6511 (match_operand:DI
1 "memory_operand" "")]
6515 rtx temp = gen_reg_rtx (SImode);
6517 /* Restore the backchain from the first word, sp from the second. */
6518 emit_move_insn (temp, operand_subword (operands[
1],
0,
0, DImode));
6519 emit_move_insn (operands[
0], operand_subword (operands[
1],
1,
0, DImode));
6520 emit_move_insn (gen_rtx (MEM, SImode, operands[
0]), temp);
6525 ;; A function pointer under AIX is a pointer to a data area whose first word
6526 ;; contains the actual address of the function, whose second word contains a
6527 ;; pointer to its TOC, and whose third word contains a value to place in the
6528 ;; static chain register (r11). Note that if we load the static chain, our
6529 ;; "trampoline" need not have any executable code.
6531 ;; operands[
0] is a register pointing to the
3 word descriptor (aka, the function address)
6532 ;; operands[
1] is the stack size to clean up
6533 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument (must be
0 for AIX)
6534 ;; operands[
3] is location to store the TOC
6535 ;; operands[
4] is the TOC register
6536 ;; operands[
5] is the static chain register
6538 ;; We do not break this into separate insns, so that the scheduler will not try
6539 ;; to move the load of the new TOC before any loads from the TOC.
6541 (define_insn "call_indirect_aix"
6542 [(call (mem:SI (match_operand:SI
0 "register_operand" "b"))
6543 (match_operand
1 "const_int_operand" "n"))
6544 (use (match_operand
2 "const_int_operand" "n"))
6545 (use (match_operand
3 "offsettable_addr_operand" "p"))
6546 (use (match_operand
4 "register_operand" "r"))
6547 (clobber (match_operand
5 "register_operand" "=r"))
6548 (clobber (match_scratch:SI
6 "=&r"))
6549 (clobber (match_scratch:SI
7 "=l"))]
6550 "DEFAULT_ABI == ABI_AIX
6551 && (INTVAL (operands[
2]) == CALL_NORMAL || (INTVAL (operands[
2]) & CALL_LONG) !=
0)"
6552 "{st|stw} %
4,%a3\;{l|lwz} %
6,
0(%
0)\;{l|lwz} %
4,
4(%
0)\;mt%
7 %
6\;{l|lwz} %
5,
8(%
0)\;{brl|blrl}\;{l|lwz} %
4,%a3"
6553 [(set_attr "length" "
28")])
6555 (define_insn "call_value_indirect_aix"
6556 [(set (match_operand
0 "register_operand" "fg")
6557 (call (mem:SI (match_operand:SI
1 "register_operand" "b"))
6558 (match_operand
2 "const_int_operand" "n")))
6559 (use (match_operand
3 "const_int_operand" "n"))
6560 (use (match_operand
4 "offsettable_addr_operand" "p"))
6561 (use (match_operand
5 "register_operand" "r"))
6562 (clobber (match_operand
6 "register_operand" "=r"))
6563 (clobber (match_scratch:SI
7 "=&r"))
6564 (clobber (match_scratch:SI
8 "=l"))]
6565 "DEFAULT_ABI == ABI_AIX
6566 && (INTVAL (operands[
3]) == CALL_NORMAL || (INTVAL (operands[
3]) & CALL_LONG) !=
0)"
6567 "{st|stw} %
5,%a4\;{l|lwz} %
7,
0(%
1)\;{l|lwz} %
5,
4(%
1);\;mt%
8 %
7\;{l|lwz} %
6,
8(%
1)\;{brl|blrl}\;{l|lwz} %
5,%a4"
6568 [(set_attr "length" "
28")])
6570 ;; A function pointer undef NT is a pointer to a data area whose first word
6571 ;; contains the actual address of the function, whose second word contains a
6572 ;; pointer to its TOC. The static chain is not stored under NT, which means
6573 ;; that we need a trampoline.
6575 ;; operands[
0] is an SImode pseudo in which we place the address of the function.
6576 ;; operands[
1] is the stack size to clean up
6577 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument (must be
0 for NT)
6578 ;; operands[
3] is location to store the TOC
6579 ;; operands[
4] is the TOC register
6581 ;; We do not break this into separate insns, so that the scheduler will not try
6582 ;; to move the load of the new TOC before any loads from the TOC.
6584 (define_insn "call_indirect_nt"
6585 [(call (mem:SI (match_operand:SI
0 "register_operand" "b"))
6586 (match_operand
1 "const_int_operand" "n"))
6587 (use (match_operand
2 "const_int_operand" "n"))
6588 (use (match_operand
3 "offsettable_addr_operand" "p"))
6589 (use (match_operand
4 "register_operand" "r"))
6590 (clobber (match_scratch:SI
5 "=&r"))
6591 (clobber (match_scratch:SI
6 "=l"))]
6592 "DEFAULT_ABI == ABI_NT
6593 && (INTVAL (operands[
2]) == CALL_NORMAL || (INTVAL (operands[
2]) & CALL_LONG) !=
0)"
6594 "{st|stw} %
4,%a3\;{l|lwz} %
5,
0(%
0)\;{l|lwz} %
4,
4(%
0)\;mt%
6 %
5\;{brl|blrl}\;{l|lwz} %
4,%a3"
6595 [(set_attr "length" "
24")])
6597 (define_insn "call_value_indirect_nt"
6598 [(set (match_operand
0 "register_operand" "fg")
6599 (call (mem:SI (match_operand:SI
1 "register_operand" "b"))
6600 (match_operand
2 "const_int_operand" "n")))
6601 (use (match_operand
3 "const_int_operand" "n"))
6602 (use (match_operand
4 "offsettable_addr_operand" "p"))
6603 (use (match_operand
5 "register_operand" "r"))
6604 (clobber (match_scratch:SI
6 "=&r"))
6605 (clobber (match_scratch:SI
7 "=l"))]
6606 "DEFAULT_ABI == ABI_NT
6607 && (INTVAL (operands[
3]) == CALL_NORMAL || (INTVAL (operands[
3]) & CALL_LONG) !=
0)"
6608 "{st|stw} %
5,%a4\;{l|lwz} %
6,
0(%
1)\;{l|lwz} %
5,
4(%
1)\;mt%
7 %
6\;{brl|blrl}\;{l|lwz} %
5,%a4"
6609 [(set_attr "length" "
24")])
6611 ;; A function pointer under System V is just a normal pointer
6612 ;; operands[
0] is the function pointer
6613 ;; operands[
1] is the stack size to clean up
6614 ;; operands[
2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
6616 (define_insn "call_indirect_sysv"
6617 [(call (mem:SI (match_operand:SI
0 "register_operand" "l,l"))
6618 (match_operand
1 "const_int_operand" "n,n"))
6619 (use (match_operand
2 "const_int_operand" "O,n"))
6620 (clobber (match_scratch:SI
3 "=l,l"))]
6621 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC"
6624 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
6625 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6627 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
6628 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6630 return
\"{brl|blrl}
\";
6632 [(set_attr "length" "
4,
8")])
6634 (define_insn "call_value_indirect_sysv"
6635 [(set (match_operand
0 "register_operand" "=fg,fg")
6636 (call (mem:SI (match_operand:SI
1 "register_operand" "l,l"))
6637 (match_operand
2 "const_int_operand" "n,n")))
6638 (use (match_operand
3 "const_int_operand" "O,n"))
6639 (clobber (match_scratch:SI
4 "=l,l"))]
6640 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC"
6643 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
6644 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6646 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
6647 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6649 return
\"{brl|blrl}
\";
6651 [(set_attr "length" "
4,
8")])
6653 ;; Now the definitions for the call and call_value insns
6654 (define_expand "call"
6655 [(parallel [(call (mem:SI (match_operand:SI
0 "address_operand" ""))
6656 (match_operand
1 "" ""))
6657 (use (match_operand
2 "" ""))
6658 (clobber (scratch:SI))])]
6662 if (GET_CODE (operands[
0]) != MEM || GET_CODE (operands[
1]) != CONST_INT)
6665 operands[
0] = XEXP (operands[
0],
0);
6667 /* Convert NT DLL imports into an indirect call. */
6668 if (GET_CODE (operands[
0]) == SYMBOL_REF
6669 && (INTVAL (operands[
2]) & CALL_NT_DLLIMPORT) !=
0)
6671 operands[
0] = rs6000_dll_import_ref (operands[
0]);
6672 operands[
2] = GEN_INT ((int)CALL_NORMAL);
6675 if (GET_CODE (operands[
0]) != SYMBOL_REF
6676 || (INTVAL (operands[
2]) & CALL_LONG) !=
0)
6678 if (INTVAL (operands[
2]) & CALL_LONG)
6679 operands[
0] = rs6000_longcall_ref (operands[
0]);
6681 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC)
6682 emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[
0]),
6683 operands[
1], operands[
2]));
6686 rtx toc_reg = gen_rtx (REG, Pmode,
2);
6687 rtx toc_addr = RS6000_SAVE_TOC;
6689 if (DEFAULT_ABI == ABI_AIX)
6691 /* AIX function pointers are really pointers to a three word area */
6692 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
6693 emit_call_insn (gen_call_indirect_aix (force_reg (Pmode, operands[
0]),
6694 operands[
1], operands[
2],
6695 toc_addr, toc_reg, static_chain));
6697 else if (DEFAULT_ABI == ABI_NT)
6699 /* NT function pointers are really pointers to a two word area */
6700 rs6000_save_toc_p =
1;
6701 emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[
0]),
6702 operands[
1], operands[
2],
6703 toc_addr, toc_reg));
6712 (define_expand "call_value"
6713 [(parallel [(set (match_operand
0 "" "")
6714 (call (mem:SI (match_operand:SI
1 "address_operand" ""))
6715 (match_operand
2 "" "")))
6716 (use (match_operand
3 "" ""))
6717 (clobber (scratch:SI))])]
6721 if (GET_CODE (operands[
1]) != MEM || GET_CODE (operands[
2]) != CONST_INT)
6724 operands[
1] = XEXP (operands[
1],
0);
6726 /* Convert NT DLL imports into an indirect call. */
6727 if (GET_CODE (operands[
1]) == SYMBOL_REF
6728 && (INTVAL (operands[
3]) & CALL_NT_DLLIMPORT) !=
0)
6730 operands[
1] = rs6000_dll_import_ref (operands[
1]);
6731 operands[
3] = GEN_INT ((int)CALL_NORMAL);
6734 if (GET_CODE (operands[
1]) != SYMBOL_REF
6735 || (INTVAL (operands[
3]) & CALL_LONG) !=
0)
6737 if (INTVAL (operands[
2]) & CALL_LONG)
6738 operands[
1] = rs6000_longcall_ref (operands[
1]);
6740 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC)
6741 emit_call_insn (gen_call_value_indirect_sysv (operands[
0], operands[
1],
6742 operands[
2], operands[
3]));
6745 rtx toc_reg = gen_rtx (REG, Pmode,
2);
6746 rtx toc_addr = RS6000_SAVE_TOC;
6748 if (DEFAULT_ABI == ABI_AIX)
6750 /* AIX function pointers are really pointers to a three word area */
6751 rtx static_chain = gen_rtx (REG, Pmode, STATIC_CHAIN_REGNUM);
6752 emit_call_insn (gen_call_value_indirect_aix (operands[
0],
6753 force_reg (Pmode, operands[
1]),
6754 operands[
2], operands[
3],
6755 toc_addr, toc_reg, static_chain));
6757 else if (DEFAULT_ABI == ABI_NT)
6759 /* NT function pointers are really pointers to a two word area */
6760 rs6000_save_toc_p =
1;
6761 emit_call_insn (gen_call_value_indirect_nt (operands[
0],
6762 force_reg (Pmode, operands[
1]),
6763 operands[
2], operands[
3],
6764 toc_addr, toc_reg));
6773 ;; Call to function in current module. No TOC pointer reload needed.
6774 ;; Operand2 is non-zero if we are using the V
.4 calling sequence and
6775 ;; either the function was not prototyped, or it was prototyped as a
6776 ;; variable argument function. It is >
0 if FP registers were passed
6777 ;; and <
0 if they were not.
6780 [(call (mem:SI (match_operand:SI
0 "current_file_function_operand" "s,s"))
6781 (match_operand
1 "" "g,g"))
6782 (use (match_operand:SI
2 "immediate_operand" "O,n"))
6783 (clobber (match_scratch:SI
3 "=l,l"))]
6784 "INTVAL (operands[
2]) != CALL_LONG"
6787 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
6788 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6790 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
6791 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6795 [(set_attr "length" "
4,
8")])
6797 ;; Call to function which may be in another module. Restore the TOC
6798 ;; pointer (r2) after the call unless this is System V.
6799 ;; Operand2 is non-zero if we are using the V
.4 calling sequence and
6800 ;; either the function was not prototyped, or it was prototyped as a
6801 ;; variable argument function. It is >
0 if FP registers were passed
6802 ;; and <
0 if they were not.
6805 [(call (mem:SI (match_operand:SI
0 "call_operand" "s,s"))
6806 (match_operand
1 "" "fg,fg"))
6807 (use (match_operand:SI
2 "immediate_operand" "O,n"))
6808 (clobber (match_scratch:SI
3 "=l,l"))]
6809 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
6810 && INTVAL (operands[
2]) != CALL_LONG"
6813 /* Indirect calls should go through call_indirect */
6814 if (GET_CODE (operands[
0]) == REG)
6817 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
6818 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6820 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
6821 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6823 return (TARGET_WINDOWS_NT) ?
\"bl %z0\;.znop %z0
\" :
\"bl %z0\;%.
\";
6825 [(set_attr "length" "
8,
12")])
6828 [(call (mem:SI (match_operand:SI
0 "call_operand" "s,s"))
6829 (match_operand
1 "" "fg,fg"))
6830 (use (match_operand:SI
2 "immediate_operand" "O,n"))
6831 (clobber (match_scratch:SI
3 "=l,l"))]
6832 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4)
6833 && INTVAL (operands[
2]) != CALL_LONG"
6836 /* Indirect calls should go through call_indirect */
6837 if (GET_CODE (operands[
0]) == REG)
6840 if (INTVAL (operands[
2]) & CALL_V4_SET_FP_ARGS)
6841 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6843 else if (INTVAL (operands[
2]) & CALL_V4_CLEAR_FP_ARGS)
6844 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6848 [(set_attr "length" "
4,
8")])
6851 [(set (match_operand
0 "" "=fg,fg")
6852 (call (mem:SI (match_operand:SI
1 "current_file_function_operand" "s,s"))
6853 (match_operand
2 "" "g,g")))
6854 (use (match_operand:SI
3 "immediate_operand" "O,n"))
6855 (clobber (match_scratch:SI
4 "=l,l"))]
6856 "INTVAL (operands[
3]) != CALL_LONG"
6859 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
6860 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6862 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
6863 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6867 [(set_attr "length" "
4,
8")])
6870 [(set (match_operand
0 "" "=fg,fg")
6871 (call (mem:SI (match_operand:SI
1 "call_operand" "s,s"))
6872 (match_operand
2 "" "fg,fg")))
6873 (use (match_operand:SI
3 "immediate_operand" "O,n"))
6874 (clobber (match_scratch:SI
4 "=l,l"))]
6875 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
6876 && INTVAL (operands[
3]) != CALL_LONG"
6879 /* This should be handled by call_value_indirect */
6880 if (GET_CODE (operands[
1]) == REG)
6883 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
6884 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6886 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
6887 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6889 return (TARGET_WINDOWS_NT) ?
\"bl %z1\;.znop %z1
\" :
\"bl %z1\;%.
\";
6891 [(set_attr "length" "
8,
12")])
6894 [(set (match_operand
0 "" "=fg,fg")
6895 (call (mem:SI (match_operand:SI
1 "call_operand" "s,s"))
6896 (match_operand
2 "" "fg,fg")))
6897 (use (match_operand:SI
3 "immediate_operand" "O,n"))
6898 (clobber (match_scratch:SI
4 "=l,l"))]
6899 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4)
6900 && INTVAL (operands[
3]) != CALL_LONG"
6903 /* This should be handled by call_value_indirect */
6904 if (GET_CODE (operands[
1]) == REG)
6907 if (INTVAL (operands[
3]) & CALL_V4_SET_FP_ARGS)
6908 output_asm_insn (
\"crxor
6,
6,
6\", operands);
6910 else if (INTVAL (operands[
3]) & CALL_V4_CLEAR_FP_ARGS)
6911 output_asm_insn (
\"creqv
6,
6,
6\", operands);
6915 [(set_attr "length" "
4,
8")])
6918 ;; Call subroutine returning any type.
6920 (define_expand "untyped_call"
6921 [(parallel [(call (match_operand
0 "" "")
6923 (match_operand
1 "" "")
6924 (match_operand
2 "" "")])]
6930 emit_call_insn (gen_call (operands[
0], const0_rtx, const0_rtx, const0_rtx));
6932 for (i =
0; i < XVECLEN (operands[
2],
0); i++)
6934 rtx set = XVECEXP (operands[
2],
0, i);
6935 emit_move_insn (SET_DEST (set), SET_SRC (set));
6938 /* The optimizer does not know that the call sets the function value
6939 registers we stored in the result block. We avoid problems by
6940 claiming that all hard registers are used and clobbered at this
6942 emit_insn (gen_blockage ());
6947 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6948 ;; all of memory. This blocks insns from being moved across this point.
6950 (define_insn "blockage"
6951 [(unspec_volatile [(const_int
0)]
0)]
6955 ;; Synchronize instructions/data caches for V
.4 trampolines
6956 ;; The extra memory_operand is to prevent the optimizer from
6957 ;; deleting insns with "no" effect.
6959 [(unspec [(match_operand
0 "memory_operand" "=m")
6960 (match_operand
1 "register_operand" "b")
6961 (match_operand
2 "register_operand" "r")]
3)]
6965 (define_insn "dcbst"
6966 [(unspec [(match_operand
0 "memory_operand" "=m")
6967 (match_operand
1 "register_operand" "b")
6968 (match_operand
2 "register_operand" "r")]
4)]
6973 [(unspec [(match_operand
0 "memory_operand" "=m")]
5)]
6977 (define_insn "isync"
6978 [(unspec [(match_operand
0 "memory_operand" "=m")]
6)]
6983 ;; Compare insns are next. Note that the RS/
6000 has two types of compares,
6984 ;; signed & unsigned, and one type of branch.
6986 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
6987 ;; insns, and branches. We store the operands of compares until we see
6989 (define_expand "cmpsi"
6991 (compare (match_operand:SI
0 "gpc_reg_operand" "")
6992 (match_operand:SI
1 "reg_or_short_operand" "")))]
6996 /* Take care of the possibility that operands[
1] might be negative but
6997 this might be a logical operation. That insn doesn't exist. */
6998 if (GET_CODE (operands[
1]) == CONST_INT
6999 && INTVAL (operands[
1]) <
0)
7000 operands[
1] = force_reg (SImode, operands[
1]);
7002 rs6000_compare_op0 = operands[
0];
7003 rs6000_compare_op1 = operands[
1];
7004 rs6000_compare_fp_p =
0;
7008 (define_expand "cmpdi"
7010 (compare (match_operand:DI
0 "gpc_reg_operand" "")
7011 (match_operand:DI
1 "reg_or_short_operand" "")))]
7015 /* Take care of the possibility that operands[
1] might be negative but
7016 this might be a logical operation. That insn doesn't exist. */
7017 if (GET_CODE (operands[
1]) == CONST_INT
7018 && INTVAL (operands[
1]) <
0)
7019 operands[
1] = force_reg (DImode, operands[
1]);
7021 rs6000_compare_op0 = operands[
0];
7022 rs6000_compare_op1 = operands[
1];
7023 rs6000_compare_fp_p =
0;
7027 (define_expand "cmpsf"
7028 [(set (cc0) (compare (match_operand:SF
0 "gpc_reg_operand" "")
7029 (match_operand:SF
1 "gpc_reg_operand" "")))]
7033 rs6000_compare_op0 = operands[
0];
7034 rs6000_compare_op1 = operands[
1];
7035 rs6000_compare_fp_p =
1;
7039 (define_expand "cmpdf"
7040 [(set (cc0) (compare (match_operand:DF
0 "gpc_reg_operand" "")
7041 (match_operand:DF
1 "gpc_reg_operand" "")))]
7045 rs6000_compare_op0 = operands[
0];
7046 rs6000_compare_op1 = operands[
1];
7047 rs6000_compare_fp_p =
1;
7051 (define_expand "beq"
7052 [(set (match_dup
2) (match_dup
1))
7054 (if_then_else (eq (match_dup
2)
7056 (label_ref (match_operand
0 "" ""))
7060 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7061 operands[
1] = gen_rtx (COMPARE, mode,
7062 rs6000_compare_op0, rs6000_compare_op1);
7063 operands[
2] = gen_reg_rtx (mode);
7066 (define_expand "bne"
7067 [(set (match_dup
2) (match_dup
1))
7069 (if_then_else (ne (match_dup
2)
7071 (label_ref (match_operand
0 "" ""))
7075 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7076 operands[
1] = gen_rtx (COMPARE, mode,
7077 rs6000_compare_op0, rs6000_compare_op1);
7078 operands[
2] = gen_reg_rtx (mode);
7081 (define_expand "blt"
7082 [(set (match_dup
2) (match_dup
1))
7084 (if_then_else (lt (match_dup
2)
7086 (label_ref (match_operand
0 "" ""))
7090 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7091 operands[
1] = gen_rtx (COMPARE, mode,
7092 rs6000_compare_op0, rs6000_compare_op1);
7093 operands[
2] = gen_reg_rtx (mode);
7096 (define_expand "bgt"
7097 [(set (match_dup
2) (match_dup
1))
7099 (if_then_else (gt (match_dup
2)
7101 (label_ref (match_operand
0 "" ""))
7105 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7106 operands[
1] = gen_rtx (COMPARE, mode,
7107 rs6000_compare_op0, rs6000_compare_op1);
7108 operands[
2] = gen_reg_rtx (mode);
7111 (define_expand "ble"
7112 [(set (match_dup
2) (match_dup
1))
7114 (if_then_else (le (match_dup
2)
7116 (label_ref (match_operand
0 "" ""))
7120 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7121 operands[
1] = gen_rtx (COMPARE, mode,
7122 rs6000_compare_op0, rs6000_compare_op1);
7123 operands[
2] = gen_reg_rtx (mode);
7126 (define_expand "bge"
7127 [(set (match_dup
2) (match_dup
1))
7129 (if_then_else (ge (match_dup
2)
7131 (label_ref (match_operand
0 "" ""))
7135 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7136 operands[
1] = gen_rtx (COMPARE, mode,
7137 rs6000_compare_op0, rs6000_compare_op1);
7138 operands[
2] = gen_reg_rtx (mode);
7141 (define_expand "bgtu"
7142 [(set (match_dup
2) (match_dup
1))
7144 (if_then_else (gtu (match_dup
2)
7146 (label_ref (match_operand
0 "" ""))
7150 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7151 rs6000_compare_op0, rs6000_compare_op1);
7152 operands[
2] = gen_reg_rtx (CCUNSmode);
7155 (define_expand "bltu"
7156 [(set (match_dup
2) (match_dup
1))
7158 (if_then_else (ltu (match_dup
2)
7160 (label_ref (match_operand
0 "" ""))
7164 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7165 rs6000_compare_op0, rs6000_compare_op1);
7166 operands[
2] = gen_reg_rtx (CCUNSmode);
7169 (define_expand "bgeu"
7170 [(set (match_dup
2) (match_dup
1))
7172 (if_then_else (geu (match_dup
2)
7174 (label_ref (match_operand
0 "" ""))
7178 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7179 rs6000_compare_op0, rs6000_compare_op1);
7180 operands[
2] = gen_reg_rtx (CCUNSmode);
7183 (define_expand "bleu"
7184 [(set (match_dup
2) (match_dup
1))
7186 (if_then_else (leu (match_dup
2)
7188 (label_ref (match_operand
0 "" ""))
7192 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7193 rs6000_compare_op0, rs6000_compare_op1);
7194 operands[
2] = gen_reg_rtx (CCUNSmode);
7197 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
7198 ;; For SEQ, likewise, except that comparisons with zero should be done
7199 ;; with an scc insns. However, due to the order that combine see the
7200 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
7201 ;; the cases we don't want to handle.
7202 (define_expand "seq"
7203 [(set (match_dup
2) (match_dup
1))
7204 (set (match_operand:SI
0 "gpc_reg_operand" "")
7205 (eq:SI (match_dup
2) (const_int
0)))]
7208 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7209 operands[
1] = gen_rtx (COMPARE, mode,
7210 rs6000_compare_op0, rs6000_compare_op1);
7211 operands[
2] = gen_reg_rtx (mode);
7214 (define_expand "sne"
7215 [(set (match_dup
2) (match_dup
1))
7216 (set (match_operand:SI
0 "gpc_reg_operand" "")
7217 (ne:SI (match_dup
2) (const_int
0)))]
7220 { if (! rs6000_compare_fp_p)
7223 operands[
1] = gen_rtx (COMPARE, CCFPmode,
7224 rs6000_compare_op0, rs6000_compare_op1);
7225 operands[
2] = gen_reg_rtx (CCFPmode);
7228 ;; A >
0 is best done using the portable sequence, so fail in that case.
7229 (define_expand "sgt"
7230 [(set (match_dup
2) (match_dup
1))
7231 (set (match_operand:SI
0 "gpc_reg_operand" "")
7232 (gt:SI (match_dup
2) (const_int
0)))]
7235 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7237 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7240 operands[
1] = gen_rtx (COMPARE, mode,
7241 rs6000_compare_op0, rs6000_compare_op1);
7242 operands[
2] = gen_reg_rtx (mode);
7245 ;; A <
0 is best done in the portable way for A an integer.
7246 (define_expand "slt"
7247 [(set (match_dup
2) (match_dup
1))
7248 (set (match_operand:SI
0 "gpc_reg_operand" "")
7249 (lt:SI (match_dup
2) (const_int
0)))]
7252 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7254 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7257 operands[
1] = gen_rtx (COMPARE, mode,
7258 rs6000_compare_op0, rs6000_compare_op1);
7259 operands[
2] = gen_reg_rtx (mode);
7262 (define_expand "sge"
7263 [(set (match_dup
2) (match_dup
1))
7264 (set (match_operand:SI
0 "gpc_reg_operand" "")
7265 (ge:SI (match_dup
2) (const_int
0)))]
7268 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7269 operands[
1] = gen_rtx (COMPARE, mode,
7270 rs6000_compare_op0, rs6000_compare_op1);
7271 operands[
2] = gen_reg_rtx (mode);
7274 ;; A <=
0 is best done the portable way for A an integer.
7275 (define_expand "sle"
7276 [(set (match_dup
2) (match_dup
1))
7277 (set (match_operand:SI
0 "gpc_reg_operand" "")
7278 (le:SI (match_dup
2) (const_int
0)))]
7281 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
7283 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
7286 operands[
1] = gen_rtx (COMPARE, mode,
7287 rs6000_compare_op0, rs6000_compare_op1);
7288 operands[
2] = gen_reg_rtx (mode);
7291 (define_expand "sgtu"
7292 [(set (match_dup
2) (match_dup
1))
7293 (set (match_operand:SI
0 "gpc_reg_operand" "")
7294 (gtu:SI (match_dup
2) (const_int
0)))]
7297 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7298 rs6000_compare_op0, rs6000_compare_op1);
7299 operands[
2] = gen_reg_rtx (CCUNSmode);
7302 (define_expand "sltu"
7303 [(set (match_dup
2) (match_dup
1))
7304 (set (match_operand:SI
0 "gpc_reg_operand" "")
7305 (ltu:SI (match_dup
2) (const_int
0)))]
7308 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7309 rs6000_compare_op0, rs6000_compare_op1);
7310 operands[
2] = gen_reg_rtx (CCUNSmode);
7313 (define_expand "sgeu"
7314 [(set (match_dup
2) (match_dup
1))
7315 (set (match_operand:SI
0 "gpc_reg_operand" "")
7316 (geu:SI (match_dup
2) (const_int
0)))]
7319 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7320 rs6000_compare_op0, rs6000_compare_op1);
7321 operands[
2] = gen_reg_rtx (CCUNSmode);
7324 (define_expand "sleu"
7325 [(set (match_dup
2) (match_dup
1))
7326 (set (match_operand:SI
0 "gpc_reg_operand" "")
7327 (leu:SI (match_dup
2) (const_int
0)))]
7330 { operands[
1] = gen_rtx (COMPARE, CCUNSmode,
7331 rs6000_compare_op0, rs6000_compare_op1);
7332 operands[
2] = gen_reg_rtx (CCUNSmode);
7335 ;; Here are the actual compare insns.
7337 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
7338 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
7339 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
7341 "{cmp%I2|cmpw%I2} %
0,%
1,%
2"
7342 [(set_attr "type" "compare")])
7345 [(set (match_operand:CC
0 "cc_reg_operand" "=y")
7346 (compare:CC (match_operand:DI
1 "gpc_reg_operand" "r")
7347 (match_operand:DI
2 "reg_or_short_operand" "rI")))]
7350 [(set_attr "type" "compare")])
7352 ;; If we are comparing a register for equality with a large constant,
7353 ;; we can do this with an XOR followed by a compare. But we need a scratch
7354 ;; register for the result of the XOR.
7357 [(set (match_operand:CC
0 "cc_reg_operand" "")
7358 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "")
7359 (match_operand:SI
2 "non_short_cint_operand" "")))
7360 (clobber (match_operand:SI
3 "gpc_reg_operand" ""))]
7361 "find_single_use (operands[
0], insn,
0)
7362 && (GET_CODE (*find_single_use (operands[
0], insn,
0)) == EQ
7363 || GET_CODE (*find_single_use (operands[
0], insn,
0)) == NE)"
7364 [(set (match_dup
3) (xor:SI (match_dup
1) (match_dup
4)))
7365 (set (match_dup
0) (compare:CC (match_dup
3) (match_dup
5)))]
7368 /* Get the constant we are comparing against, C, and see what it looks like
7369 sign-extended to
16 bits. Then see what constant could be XOR'ed
7370 with C to get the sign-extended value. */
7372 int c = INTVAL (operands[
2]);
7373 int sextc = (c <<
16) >>
16;
7374 int xorv = c ^ sextc;
7376 operands[
4] = gen_rtx (CONST_INT, VOIDmode, xorv);
7377 operands[
5] = gen_rtx (CONST_INT, VOIDmode, sextc);
7381 [(set (match_operand:CCUNS
0 "cc_reg_operand" "=y")
7382 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "r")
7383 (match_operand:SI
2 "reg_or_u_short_operand" "rI")))]
7385 "{cmpl%I2|cmplw%I2} %
0,%
1,%W2"
7386 [(set_attr "type" "compare")])
7389 [(set (match_operand:CCUNS
0 "cc_reg_operand" "=y")
7390 (compare:CCUNS (match_operand:DI
1 "gpc_reg_operand" "r")
7391 (match_operand:DI
2 "reg_or_u_short_operand" "rI")))]
7393 "cmpld%I2 %
0,%
1,%W2"
7394 [(set_attr "type" "compare")])
7396 ;; The following two insns don't exist as single insns, but if we provide
7397 ;; them, we can swap an add and compare, which will enable us to overlap more
7398 ;; of the required delay between a compare and branch. We generate code for
7399 ;; them by splitting.
7402 [(set (match_operand:CC
3 "cc_reg_operand" "=y")
7403 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "r")
7404 (match_operand:SI
2 "short_cint_operand" "i")))
7405 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7406 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "i")))]
7409 [(set_attr "length" "
8")])
7412 [(set (match_operand:CCUNS
3 "cc_reg_operand" "=y")
7413 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "r")
7414 (match_operand:SI
2 "u_short_cint_operand" "i")))
7415 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7416 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "i")))]
7419 [(set_attr "length" "
8")])
7422 [(set (match_operand:CC
3 "cc_reg_operand" "")
7423 (compare:CC (match_operand:SI
1 "gpc_reg_operand" "")
7424 (match_operand:SI
2 "short_cint_operand" "")))
7425 (set (match_operand:SI
0 "gpc_reg_operand" "")
7426 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "")))]
7428 [(set (match_dup
3) (compare:CC (match_dup
1) (match_dup
2)))
7429 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
4)))])
7432 [(set (match_operand:CCUNS
3 "cc_reg_operand" "")
7433 (compare:CCUNS (match_operand:SI
1 "gpc_reg_operand" "")
7434 (match_operand:SI
2 "u_short_cint_operand" "")))
7435 (set (match_operand:SI
0 "gpc_reg_operand" "")
7436 (plus:SI (match_dup
1) (match_operand:SI
4 "short_cint_operand" "")))]
7438 [(set (match_dup
3) (compare:CCUNS (match_dup
1) (match_dup
2)))
7439 (set (match_dup
0) (plus:SI (match_dup
1) (match_dup
4)))])
7442 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
7443 (compare:CCFP (match_operand:SF
1 "gpc_reg_operand" "f")
7444 (match_operand:SF
2 "gpc_reg_operand" "f")))]
7447 [(set_attr "type" "fpcompare")])
7450 [(set (match_operand:CCFP
0 "cc_reg_operand" "=y")
7451 (compare:CCFP (match_operand:DF
1 "gpc_reg_operand" "f")
7452 (match_operand:DF
2 "gpc_reg_operand" "f")))]
7455 [(set_attr "type" "fpcompare")])
7457 ;; Now we have the scc insns. We can do some combinations because of the
7458 ;; way the machine works.
7460 ;; Note that this is probably faster if we can put an insn between the
7461 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
7462 ;; cases the insns below which don't use an intermediate CR field will
7465 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7466 (match_operator:SI
1 "scc_comparison_operator"
7467 [(match_operand
2 "cc_reg_operand" "y")
7470 "%D1mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%J1,
1"
7471 [(set_attr "length" "
12")])
7474 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
7475 (compare:CC (match_operator:SI
1 "scc_comparison_operator"
7476 [(match_operand
2 "cc_reg_operand" "y")
7479 (set (match_operand:SI
3 "gpc_reg_operand" "=r")
7480 (match_op_dup
1 [(match_dup
2) (const_int
0)]))]
7482 "%D1mfcr %
3\;{rlinm.|rlwinm.} %
3,%
3,%J1,
1"
7483 [(set_attr "type" "delayed_compare")
7484 (set_attr "length" "
12")])
7487 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7488 (ashift:SI (match_operator:SI
1 "scc_comparison_operator"
7489 [(match_operand
2 "cc_reg_operand" "y")
7491 (match_operand:SI
3 "const_int_operand" "n")))]
7495 int is_bit = ccr_bit (operands[
1],
1);
7496 int put_bit =
31 - (INTVAL (operands[
3]) &
31);
7499 if (is_bit >= put_bit)
7500 count = is_bit - put_bit;
7502 count =
32 - (put_bit - is_bit);
7504 operands[
4] = gen_rtx (CONST_INT, VOIDmode, count);
7505 operands[
5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
7507 return
\"%D1mfcr %
0\;{rlinm|rlwinm} %
0,%
0,%
4,%
5,%
5\";
7509 [(set_attr "length" "
12")])
7512 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
7514 (ashift:SI (match_operator:SI
1 "scc_comparison_operator"
7515 [(match_operand
2 "cc_reg_operand" "y")
7517 (match_operand:SI
3 "const_int_operand" "n"))
7519 (set (match_operand:SI
4 "gpc_reg_operand" "=r")
7520 (ashift:SI (match_op_dup
1 [(match_dup
2) (const_int
0)])
7525 int is_bit = ccr_bit (operands[
1],
1);
7526 int put_bit =
31 - (INTVAL (operands[
3]) &
31);
7529 if (is_bit >= put_bit)
7530 count = is_bit - put_bit;
7532 count =
32 - (put_bit - is_bit);
7534 operands[
5] = gen_rtx (CONST_INT, VOIDmode, count);
7535 operands[
6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
7537 return
\"%D1mfcr %
4\;{rlinm.|rlwinm.} %
4,%
4,%
5,%
6,%
6\";
7539 [(set_attr "type" "delayed_compare")
7540 (set_attr "length" "
12")])
7542 ;; If we are comparing the result of two comparisons, this can be done
7543 ;; using creqv or crxor.
7546 [(set (match_operand:CCEQ
0 "cc_reg_operand" "=y")
7547 (compare:CCEQ (match_operator
1 "scc_comparison_operator"
7548 [(match_operand
2 "cc_reg_operand" "y")
7550 (match_operator
3 "scc_comparison_operator"
7551 [(match_operand
4 "cc_reg_operand" "y")
7553 "REGNO (operands[
2]) != REGNO (operands[
4])"
7556 enum rtx_code code1, code2;
7558 code1 = GET_CODE (operands[
1]);
7559 code2 = GET_CODE (operands[
3]);
7561 if ((code1 == EQ || code1 == LT || code1 == GT
7562 || code1 == LTU || code1 == GTU
7563 || (code1 != NE && GET_MODE (operands[
2]) == CCFPmode))
7565 (code2 == EQ || code2 == LT || code2 == GT
7566 || code2 == LTU || code2 == GTU
7567 || (code2 != NE && GET_MODE (operands[
4]) == CCFPmode)))
7568 return
\"%C1%C3crxor %E0,%j1,%j3
\";
7570 return
\"%C1%C3creqv %E0,%j1,%j3
\";
7572 [(set_attr "length" "
12")])
7574 ;; There is a
3 cycle delay between consecutive mfcr instructions
7575 ;; so it is useful to combine
2 scc instructions to use only one mfcr.
7578 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7579 (match_operator:SI
1 "scc_comparison_operator"
7580 [(match_operand
2 "cc_reg_operand" "y")
7582 (set (match_operand:SI
3 "gpc_reg_operand" "=r")
7583 (match_operator:SI
4 "scc_comparison_operator"
7584 [(match_operand
5 "cc_reg_operand" "y")
7586 "REGNO (operands[
2]) != REGNO (operands[
5])"
7587 "%D1%D4mfcr %
3\;{rlinm|rlwinm} %
0,%
3,%J1,
1\;{rlinm|rlwinm} %
3,%
3,%J4,
1"
7588 [(set_attr "length" "
20")])
7590 ;; There are some scc insns that can be done directly, without a compare.
7591 ;; These are faster because they don't involve the communications between
7592 ;; the FXU and branch units. In fact, we will be replacing all of the
7593 ;; integer scc insns here or in the portable methods in emit_store_flag.
7595 ;; Also support (neg (scc ..)) since that construct is used to replace
7596 ;; branches, (plus (scc ..) ..) since that construct is common and
7597 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
7598 ;; cases where it is no more expensive than (neg (scc ..)).
7600 ;; Have reload force a constant into a register for the simple insns that
7601 ;; otherwise won't accept constants. We do this because it is faster than
7602 ;; the cmp/mfcr sequence we would otherwise generate.
7605 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
7606 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
7607 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I")))
7608 (clobber (match_scratch:SI
3 "=r,&r,r,r,r"))]
7611 xor %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
7612 {sfi|subfic} %
3,%
1,
0\;{ae|adde} %
0,%
3,%
1
7613 {xoril|xori} %
0,%
1,%b2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
7614 {xoriu|xoris} %
0,%
1,%u2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0
7615 {sfi|subfic} %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae|adde} %
0,%
3,%
0"
7616 [(set_attr "length" "
12,
8,
12,
12,
12")])
7619 [(set (match_operand:CC
4 "cc_reg_operand" "=x,x,x,x,x")
7621 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
7622 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
7624 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
7625 (eq:SI (match_dup
1) (match_dup
2)))
7626 (clobber (match_scratch:SI
3 "=r,&r,r,r,r"))]
7629 xor %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
7630 {sfi|subfic} %
3,%
1,
0\;{ae.|adde.} %
0,%
3,%
1
7631 {xoril|xori} %
0,%
1,%b2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
7632 {xoriu|xoris} %
0,%
1,%u2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0
7633 {sfi|subfic} %
0,%
1,%
2\;{sfi|subfic} %
3,%
0,
0\;{ae.|adde.} %
0,%
3,%
0"
7634 [(set_attr "type" "compare")
7635 (set_attr "length" "
12,
8,
12,
12,
12")])
7637 ;; We have insns of the form shown by the first define_insn below. If
7638 ;; there is something inside the comparison operation, we must split it.
7640 [(set (match_operand:SI
0 "gpc_reg_operand" "")
7641 (plus:SI (match_operator
1 "comparison_operator"
7642 [(match_operand:SI
2 "" "")
7644 "reg_or_cint_operand" "")])
7645 (match_operand:SI
4 "gpc_reg_operand" "")))
7646 (clobber (match_operand:SI
5 "register_operand" ""))]
7647 "! gpc_reg_operand (operands[
2], SImode)"
7648 [(set (match_dup
5) (match_dup
2))
7649 (set (match_dup
2) (plus:SI (match_op_dup
1 [(match_dup
2) (match_dup
3)])
7653 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
7654 (plus:SI (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
7655 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
7656 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r")))
7657 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
7660 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
7661 {sfi|subfic} %
4,%
1,
0\;{aze|addze} %
0,%
3
7662 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
7663 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
7664 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3"
7665 [(set_attr "length" "
12,
8,
12,
12,
12")])
7668 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x,x,x,x")
7671 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
7672 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
7673 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r"))
7675 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
7678 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
7679 {sfi|subfic} %
4,%
1,
0\;{aze.|addze.} %
0,%
3
7680 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
7681 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
7682 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3"
7683 [(set_attr "type" "compare")
7684 (set_attr "length" "
12,
8,
12,
12,
12")])
7687 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x,x,x,x")
7690 (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
7691 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))
7692 (match_operand:SI
3 "gpc_reg_operand" "r,r,r,r,r"))
7694 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
7695 (plus:SI (eq:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
7696 (clobber (match_scratch:SI
4 "=&r,&r,&r,&r,&r"))]
7699 xor %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
7700 {sfi|subfic} %
4,%
1,
0\;{aze.|addze.} %
4,%
3
7701 {xoril|xori} %
4,%
1,%b2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
7702 {xoriu|xoris} %
4,%
1,%u2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
7703 {sfi|subfic} %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3"
7704 [(set_attr "type" "compare")
7705 (set_attr "length" "
12,
8,
12,
12,
12")])
7708 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r,r")
7709 (neg:SI (eq:SI (match_operand:SI
1 "gpc_reg_operand" "%r,r,r,r,r")
7710 (match_operand:SI
2 "reg_or_cint_operand" "r,O,K,J,I"))))]
7713 xor %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
7714 {ai|addic} %
0,%
1,-
1\;{sfe|subfe} %
0,%
0,%
0
7715 {xoril|xori} %
0,%
1,%b2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
7716 {xoriu|xoris} %
0,%
1,%u2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
7717 {sfi|subfic} %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0"
7718 [(set_attr "length" "
12,
8,
12,
12,
12")])
7720 ;; Simplify (ne X (const_int
0)) on the PowerPC. No need to on the Power,
7721 ;; since it nabs/sr is just as fast.
7723 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7724 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
7726 (clobber (match_scratch:SI
2 "=&r"))]
7728 "{ai|addic} %
2,%
1,-
1\;{sfe|subfe} %
0,%
2,%
1"
7729 [(set_attr "length" "
8")])
7731 ;; This is what (plus (ne X (const_int
0)) Y) looks like.
7733 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7734 (plus:SI (lshiftrt:SI
7735 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
7737 (match_operand:SI
2 "gpc_reg_operand" "r")))
7738 (clobber (match_scratch:SI
3 "=&r"))]
7740 "{ai|addic} %
3,%
1,-
1\;{aze|addze} %
0,%
2"
7741 [(set_attr "length" "
8")])
7744 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
7746 (plus:SI (lshiftrt:SI
7747 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
7749 (match_operand:SI
2 "gpc_reg_operand" "r"))
7751 (clobber (match_scratch:SI
3 "=&r"))]
7753 "{ai|addic} %
3,%
1,-
1\;{aze.|addze.} %
3,%
2"
7754 [(set_attr "type" "compare")
7755 (set_attr "length" "
8")])
7758 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
7760 (plus:SI (lshiftrt:SI
7761 (neg:SI (abs:SI (match_operand:SI
1 "gpc_reg_operand" "r")))
7763 (match_operand:SI
2 "gpc_reg_operand" "r"))
7765 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7766 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup
1))) (const_int
31))
7768 (clobber (match_scratch:SI
3 "=&r"))]
7770 "{ai|addic} %
3,%
1,-
1\;{aze.|addze.} %
0,%
2"
7771 [(set_attr "type" "compare")
7772 (set_attr "length" "
8")])
7775 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
7776 (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
7777 (match_operand:SI
2 "reg_or_short_operand" "r,O")))
7778 (clobber (match_scratch:SI
3 "=r,X"))]
7781 doz %
3,%
2,%
1\;{sfi|subfic} %
0,%
3,
0\;{ae|adde} %
0,%
0,%
3
7782 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{sri|srwi} %
0,%
0,
31"
7783 [(set_attr "length" "
12")])
7786 [(set (match_operand:CC
4 "cc_reg_operand" "=x,x")
7788 (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
7789 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
7791 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
7792 (le:SI (match_dup
1) (match_dup
2)))
7793 (clobber (match_scratch:SI
3 "=r,X"))]
7796 doz %
3,%
2,%
1\;{sfi|subfic} %
0,%
3,
0\;{ae.|adde.} %
0,%
0,%
3
7797 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
7798 [(set_attr "type" "compare,delayed_compare")
7799 (set_attr "length" "
12")])
7802 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
7803 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
7804 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
7805 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
7806 (clobber (match_scratch:SI
4 "=&r,&r"))]
7809 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3
7810 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze|addze} %
0,%
3"
7811 [(set_attr "length" "
12")])
7814 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
7816 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
7817 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
7818 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
7820 (clobber (match_scratch:SI
4 "=&r,&r"))]
7823 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3
7824 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze.|addze.} %
4,%
3"
7825 [(set_attr "type" "compare")
7826 (set_attr "length" "
12")])
7829 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
7831 (plus:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
7832 (match_operand:SI
2 "reg_or_short_operand" "r,O"))
7833 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
7835 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
7836 (plus:SI (le:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
7837 (clobber (match_scratch:SI
4 "=&r,&r"))]
7840 doz %
4,%
2,%
1\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3
7841 {srai|srawi} %
4,%
1,
31\;{sf|subfc} %
4,%
1,%
4\;{aze.|addze.} %
0,%
3"
7842 [(set_attr "type" "compare")
7843 (set_attr "length" "
12")])
7846 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
7847 (neg:SI (le:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
7848 (match_operand:SI
2 "reg_or_short_operand" "r,O"))))]
7851 doz %
0,%
2,%
1\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0
7852 {ai|addic} %
0,%
1,-
1\;{aze|addze} %
0,%
0\;{srai|srawi} %
0,%
0,
31"
7853 [(set_attr "length" "
12")])
7856 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7857 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7858 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
7860 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0"
7861 [(set_attr "length" "
12")])
7864 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
7866 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7867 (match_operand:SI
2 "reg_or_short_operand" "rI"))
7869 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7870 (leu:SI (match_dup
1) (match_dup
2)))]
7872 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0"
7873 [(set_attr "type" "compare")
7874 (set_attr "length" "
12")])
7877 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7878 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7879 (match_operand:SI
2 "reg_or_short_operand" "rI"))
7880 (match_operand:SI
3 "gpc_reg_operand" "r")))
7881 (clobber (match_scratch:SI
4 "=&r"))]
7883 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze|addze} %
0,%
3"
7884 [(set_attr "length" "
8")])
7887 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
7889 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7890 (match_operand:SI
2 "reg_or_short_operand" "rI"))
7891 (match_operand:SI
3 "gpc_reg_operand" "r"))
7893 (clobber (match_scratch:SI
4 "=&r"))]
7895 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze.|addze.} %
4,%
3"
7896 [(set_attr "type" "compare")
7897 (set_attr "length" "
8")])
7900 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
7902 (plus:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7903 (match_operand:SI
2 "reg_or_short_operand" "rI"))
7904 (match_operand:SI
3 "gpc_reg_operand" "r"))
7906 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7907 (plus:SI (leu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
7908 (clobber (match_scratch:SI
4 "=&r"))]
7910 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{aze.|addze.} %
0,%
3"
7911 [(set_attr "type" "compare")
7912 (set_attr "length" "
8")])
7915 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7916 (neg:SI (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7917 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
7919 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;nand %
0,%
0,%
0"
7920 [(set_attr "length" "
12")])
7923 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7925 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7926 (match_operand:SI
2 "reg_or_short_operand" "rI")))
7927 (match_operand:SI
3 "gpc_reg_operand" "r")))
7928 (clobber (match_scratch:SI
4 "=&r"))]
7930 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4"
7931 [(set_attr "length" "
12")])
7934 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
7937 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7938 (match_operand:SI
2 "reg_or_short_operand" "rI")))
7939 (match_operand:SI
3 "gpc_reg_operand" "r"))
7941 (clobber (match_scratch:SI
4 "=&r"))]
7943 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4"
7944 [(set_attr "type" "compare")
7945 (set_attr "length" "
12")])
7948 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
7951 (leu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7952 (match_operand:SI
2 "reg_or_short_operand" "rI")))
7953 (match_operand:SI
3 "gpc_reg_operand" "r"))
7955 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7956 (and:SI (neg:SI (leu:SI (match_dup
1) (match_dup
2))) (match_dup
3)))
7957 (clobber (match_scratch:SI
4 "=&r"))]
7959 "{sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4"
7960 [(set_attr "type" "compare")
7961 (set_attr "length" "
12")])
7964 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7965 (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7966 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
7968 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{sri|srwi} %
0,%
0,
31"
7969 [(set_attr "length" "
12")])
7972 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
7974 (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7975 (match_operand:SI
2 "reg_or_short_operand" "rI"))
7977 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
7978 (lt:SI (match_dup
1) (match_dup
2)))]
7980 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
7981 [(set_attr "type" "delayed_compare")
7982 (set_attr "length" "
12")])
7985 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
7986 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7987 (match_operand:SI
2 "reg_or_short_operand" "rI"))
7988 (match_operand:SI
3 "gpc_reg_operand" "r")))
7989 (clobber (match_scratch:SI
4 "=&r"))]
7991 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze|addze} %
0,%
3"
7992 [(set_attr "length" "
12")])
7995 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
7997 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
7998 (match_operand:SI
2 "reg_or_short_operand" "rI"))
7999 (match_operand:SI
3 "gpc_reg_operand" "r"))
8001 (clobber (match_scratch:SI
4 "=&r"))]
8003 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
4,%
3"
8004 [(set_attr "type" "compare")
8005 (set_attr "length" "
12")])
8008 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8010 (plus:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8011 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8012 (match_operand:SI
3 "gpc_reg_operand" "r"))
8014 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8015 (plus:SI (lt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8016 (clobber (match_scratch:SI
4 "=&r"))]
8018 "doz%I2 %
4,%
1,%
2\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
0,%
3"
8019 [(set_attr "type" "compare")
8020 (set_attr "length" "
12")])
8023 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8024 (neg:SI (lt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8025 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8027 "doz%I2 %
0,%
1,%
2\;nabs %
0,%
0\;{srai|srawi} %
0,%
0,
31"
8028 [(set_attr "length" "
12")])
8031 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8032 (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8033 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))]
8036 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0
8037 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0"
8038 [(set_attr "length" "
12")])
8041 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
8043 (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8044 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8046 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8047 (ltu:SI (match_dup
1) (match_dup
2)))]
8050 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0
8051 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0"
8052 [(set_attr "type" "compare")
8053 (set_attr "length" "
12")])
8056 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r,r")
8057 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r,r")
8058 (match_operand:SI
2 "reg_or_neg_short_operand" "r,r,P,P"))
8059 (match_operand:SI
3 "reg_or_short_operand" "r,I,r,I")))
8060 (clobber (match_scratch:SI
4 "=&r,r,&r,r"))]
8063 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8064 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8065 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8066 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3"
8067 [(set_attr "length" "
12")])
8070 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8072 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8073 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8074 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8076 (clobber (match_scratch:SI
4 "=&r,&r"))]
8079 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
4,%
4,%
3
8080 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
4,%
4,%
3"
8081 [(set_attr "type" "compare")
8082 (set_attr "length" "
12")])
8085 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8087 (plus:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8088 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8089 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8091 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8092 (plus:SI (ltu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8093 (clobber (match_scratch:SI
4 "=&r,&r"))]
8096 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3
8097 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
8098 [(set_attr "type" "compare")
8099 (set_attr "length" "
12")])
8102 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8103 (neg:SI (ltu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8104 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))))]
8107 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0
8108 {ai|addic} %
0,%
1,%n2\;{sfe|subfe} %
0,%
0,%
0"
8109 [(set_attr "length" "
8")])
8112 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8113 (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8114 (match_operand:SI
2 "reg_or_short_operand" "rI")))
8115 (clobber (match_scratch:SI
3 "=r"))]
8117 "doz%I2 %
3,%
1,%
2\;{sfi|subfic} %
0,%
3,
0\;{ae|adde} %
0,%
0,%
3"
8118 [(set_attr "length" "
12")])
8121 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8123 (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8124 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8126 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8127 (ge:SI (match_dup
1) (match_dup
2)))
8128 (clobber (match_scratch:SI
3 "=r"))]
8130 "doz%I2 %
3,%
1,%
2\;{sfi|subfic} %
0,%
3,
0\;{ae.|adde.} %
0,%
0,%
3"
8131 [(set_attr "type" "compare")
8132 (set_attr "length" "
12")])
8135 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8136 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8137 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8138 (match_operand:SI
3 "gpc_reg_operand" "r")))
8139 (clobber (match_scratch:SI
4 "=&r"))]
8141 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze|addze} %
0,%
3"
8142 [(set_attr "length" "
12")])
8145 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8147 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8148 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8149 (match_operand:SI
3 "gpc_reg_operand" "r"))
8151 (clobber (match_scratch:SI
4 "=&r"))]
8153 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
4,%
3"
8154 [(set_attr "type" "compare")
8155 (set_attr "length" "
12")])
8158 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8160 (plus:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8161 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8162 (match_operand:SI
3 "gpc_reg_operand" "r"))
8164 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8165 (plus:SI (ge:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8166 (clobber (match_scratch:SI
4 "=&r"))]
8168 "doz%I2 %
4,%
1,%
2\;{sfi|subfic} %
4,%
4,
0\;{aze.|addze.} %
0,%
3"
8169 [(set_attr "type" "compare")
8170 (set_attr "length" "
12")])
8173 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8174 (neg:SI (ge:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8175 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8177 "doz%I2 %
0,%
1,%
2\;{ai|addic} %
0,%
0,-
1\;{sfe|subfe} %
0,%
0,%
0"
8178 [(set_attr "length" "
12")])
8180 ;; This is (and (neg (ge X (const_int
0))) Y).
8182 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8185 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
8187 (match_operand:SI
2 "gpc_reg_operand" "r")))
8188 (clobber (match_scratch:SI
3 "=&r"))]
8190 "{srai|srawi} %
3,%
1,
31\;andc %
0,%
2,%
3"
8191 [(set_attr "length" "
8")])
8194 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8198 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
8200 (match_operand:SI
2 "gpc_reg_operand" "r"))
8202 (clobber (match_scratch:SI
3 "=&r"))]
8204 "{srai|srawi} %
3,%
1,
31\;andc. %
3,%
2,%
3"
8205 [(set_attr "type" "compare")
8206 (set_attr "length" "
8")])
8209 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8213 (not:SI (match_operand:SI
1 "gpc_reg_operand" "r"))
8215 (match_operand:SI
2 "gpc_reg_operand" "r"))
8217 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8218 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup
1))
8221 (clobber (match_scratch:SI
3 "=&r"))]
8223 "{srai|srawi} %
3,%
1,
31\;andc. %
0,%
2,%
3"
8224 [(set_attr "type" "compare")
8225 (set_attr "length" "
8")])
8228 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8229 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8230 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))]
8233 {sf|subfc} %
0,%
2,%
1\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0
8234 {ai|addic} %
0,%
1,%n2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae|adde} %
0,%
0,%
0"
8235 [(set_attr "length" "
12")])
8238 [(set (match_operand:CC
3 "cc_reg_operand" "=x,x")
8240 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8241 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8243 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8244 (geu:SI (match_dup
1) (match_dup
2)))]
8247 {sf|subfc} %
0,%
2,%
1\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0
8248 {ai|addic} %
0,%
1,%n2\;{cal %
0,
0(
0)|li %
0,
0}\;{ae.|adde.} %
0,%
0,%
0"
8249 [(set_attr "type" "compare")
8250 (set_attr "length" "
12")])
8253 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8254 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8255 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8256 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
8257 (clobber (match_scratch:SI
4 "=&r,&r"))]
8260 {sf|subfc} %
4,%
2,%
1\;{aze|addze} %
0,%
3
8261 {ai|addic} %
4,%
1,%n2\;{aze|addze} %
0,%
3"
8262 [(set_attr "length" "
8")])
8265 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8267 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8268 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8269 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8271 (clobber (match_scratch:SI
4 "=&r,&r"))]
8274 {sf|subfc} %
4,%
2,%
1\;{aze.|addze.} %
4,%
3
8275 {ai|addic} %
4,%
1,%n2\;{aze.|addze.} %
4,%
3"
8276 [(set_attr "type" "compare")
8277 (set_attr "length" "
8")])
8280 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8282 (plus:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8283 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P"))
8284 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8286 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8287 (plus:SI (geu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8288 (clobber (match_scratch:SI
4 "=&r,&r"))]
8291 {sf|subfc} %
4,%
2,%
1\;{aze.|addze.} %
0,%
3
8292 {ai|addic} %
4,%
1,%n2\;{aze.|addze.} %
4,%
3"
8293 [(set_attr "type" "compare")
8294 (set_attr "length" "
8")])
8297 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8298 (neg:SI (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8299 (match_operand:SI
2 "reg_or_short_operand" "r,I"))))]
8302 {sf|subfc} %
0,%
2,%
1\;{sfe|subfe} %
0,%
0,%
0\;nand %
0,%
0,%
0
8303 {sfi|subfic} %
0,%
1,-
1\;{a%I2|add%I2c} %
0,%
0,%
2\;{sfe|subfe} %
0,%
0,%
0"
8304 [(set_attr "length" "
12")])
8307 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8309 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8310 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
8311 (match_operand:SI
3 "gpc_reg_operand" "r,r")))
8312 (clobber (match_scratch:SI
4 "=&r,&r"))]
8315 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4
8316 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc %
0,%
3,%
4"
8317 [(set_attr "length" "
12")])
8320 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8323 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8324 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
8325 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8327 (clobber (match_scratch:SI
4 "=&r,&r"))]
8330 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4
8331 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
4,%
3,%
4"
8332 [(set_attr "type" "compare")
8333 (set_attr "length" "
12")])
8336 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8339 (geu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8340 (match_operand:SI
2 "reg_or_neg_short_operand" "r,P")))
8341 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8343 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8344 (and:SI (neg:SI (geu:SI (match_dup
1) (match_dup
2))) (match_dup
3)))
8345 (clobber (match_scratch:SI
4 "=&r,&r"))]
8348 {sf|subfc} %
4,%
2,%
1\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4
8349 {ai|addic} %
4,%
1,%n2\;{sfe|subfe} %
4,%
4,%
4\;andc. %
0,%
3,%
4"
8350 [(set_attr "type" "compare")
8351 (set_attr "length" "
12")])
8354 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8355 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8358 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8359 [(set_attr "length" "
12")])
8362 [(set (match_operand:CC
2 "cc_reg_operand" "=x")
8364 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8367 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8368 (gt:SI (match_dup
1) (const_int
0)))]
8370 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8371 [(set_attr "type" "delayed_compare")
8372 (set_attr "length" "
12")])
8375 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8376 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8377 (match_operand:SI
2 "reg_or_short_operand" "r")))]
8379 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{sri|srwi} %
0,%
0,
31"
8380 [(set_attr "length" "
12")])
8383 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
8385 (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8386 (match_operand:SI
2 "reg_or_short_operand" "r"))
8388 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8389 (gt:SI (match_dup
1) (match_dup
2)))]
8391 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{sri.|srwi.} %
0,%
0,
31"
8392 [(set_attr "type" "delayed_compare")
8393 (set_attr "length" "
12")])
8396 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8397 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8399 (match_operand:SI
2 "gpc_reg_operand" "r")))
8400 (clobber (match_scratch:SI
3 "=&r"))]
8402 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze|addze} %
0,%
2"
8403 [(set_attr "length" "
12")])
8406 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8408 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8410 (match_operand:SI
2 "gpc_reg_operand" "r"))
8412 (clobber (match_scratch:SI
3 "=&r"))]
8414 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze.|addze.} %
0,%
2"
8415 [(set_attr "type" "compare")
8416 (set_attr "length" "
12")])
8419 [(set (match_operand:CC
4 "cc_reg_operand" "=x")
8421 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8423 (match_operand:SI
2 "gpc_reg_operand" "r"))
8425 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8426 (plus:SI (gt:SI (match_dup
1) (const_int
0)) (match_dup
2)))
8427 (clobber (match_scratch:SI
3 "=&r"))]
8429 "{a|addc} %
3,%
1,%
1\;{sfe|subfe} %
3,%
1,%
3\;{aze.|addze.} %
3,%
2"
8430 [(set_attr "type" "compare")
8431 (set_attr "length" "
12")])
8434 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8435 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8436 (match_operand:SI
2 "reg_or_short_operand" "r"))
8437 (match_operand:SI
3 "gpc_reg_operand" "r")))
8438 (clobber (match_scratch:SI
4 "=&r"))]
8440 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze|addze} %
0,%
3"
8441 [(set_attr "length" "
12")])
8444 [(set (match_operand:CC
0 "cc_reg_operand" "=x")
8446 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8447 (match_operand:SI
2 "reg_or_short_operand" "r"))
8448 (match_operand:SI
3 "gpc_reg_operand" "r"))
8450 (clobber (match_scratch:SI
4 "=&r"))]
8452 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
4,%
3"
8453 [(set_attr "type" "compare")
8454 (set_attr "length" "
12")])
8457 [(set (match_operand:CC
5 "cc_reg_operand" "=x")
8459 (plus:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8460 (match_operand:SI
2 "reg_or_short_operand" "r"))
8461 (match_operand:SI
3 "gpc_reg_operand" "r"))
8463 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8464 (plus:SI (gt:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8465 (clobber (match_scratch:SI
4 "=&r"))]
8467 "doz %
4,%
2,%
1\;{ai|addic} %
4,%
4,-
1\;{aze.|addze.} %
0,%
3"
8468 [(set_attr "type" "compare")
8469 (set_attr "length" "
12")])
8472 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8473 (neg:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8476 "{sfi|subfic} %
0,%
1,
0\;{ame|addme} %
0,%
0\;{srai|srawi} %
0,%
0,
31"
8477 [(set_attr "length" "
12")])
8480 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8481 (neg:SI (gt:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8482 (match_operand:SI
2 "reg_or_short_operand" "r"))))]
8484 "doz %
0,%
2,%
1\;nabs %
0,%
0\;{srai|srawi} %
0,%
0,
31"
8485 [(set_attr "length" "
12")])
8488 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8489 (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8490 (match_operand:SI
2 "reg_or_short_operand" "rI")))]
8492 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;neg %
0,%
0"
8493 [(set_attr "length" "
12")])
8496 [(set (match_operand:CC
3 "cc_reg_operand" "=x")
8498 (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8499 (match_operand:SI
2 "reg_or_short_operand" "rI"))
8501 (set (match_operand:SI
0 "gpc_reg_operand" "=r")
8502 (gtu:SI (match_dup
1) (match_dup
2)))]
8504 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0\;neg. %
0,%
0"
8505 [(set_attr "type" "compare")
8506 (set_attr "length" "
12")])
8509 [(set (match_operand:SI
0 "gpc_reg_operand" "=r,r,r")
8510 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r,r")
8511 (match_operand:SI
2 "reg_or_short_operand" "I,r,rI"))
8512 (match_operand:SI
3 "reg_or_short_operand" "r,r,I")))
8513 (clobber (match_scratch:SI
4 "=&r,&r,&r"))]
8516 {ai|addic} %
4,%
1,%k2\;{aze|addze} %
0,%
3
8517 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3
8518 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf%I3|subf%I3c} %
0,%
4,%
3"
8519 [(set_attr "length" "
8,
12,
12")])
8522 [(set (match_operand:CC
0 "cc_reg_operand" "=x,x")
8524 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8525 (match_operand:SI
2 "reg_or_short_operand" "I,r"))
8526 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8528 (clobber (match_scratch:SI
4 "=&r,&r"))]
8531 {ai|addic} %
4,%
1,%k2\;{aze.|addze.} %
0,%
3
8532 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
8533 [(set_attr "type" "compare")
8534 (set_attr "length" "
8,
12")])
8537 [(set (match_operand:CC
5 "cc_reg_operand" "=x,x")
8539 (plus:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r,r")
8540 (match_operand:SI
2 "reg_or_short_operand" "I,r"))
8541 (match_operand:SI
3 "gpc_reg_operand" "r,r"))
8543 (set (match_operand:SI
0 "gpc_reg_operand" "=r,r")
8544 (plus:SI (gtu:SI (match_dup
1) (match_dup
2)) (match_dup
3)))
8545 (clobber (match_scratch:SI
4 "=&r,&r"))]
8548 {ai|addic} %
4,%
1,%k2\;{aze.|addze.} %
0,%
3
8549 {sf%I2|subf%I2c} %
4,%
1,%
2\;{sfe|subfe} %
4,%
4,%
4\;{sf.|subfc.} %
0,%
4,%
3"
8550 [(set_attr "type" "compare")
8551 (set_attr "length" "
8,
12")])
8554 [(set (match_operand:SI
0 "gpc_reg_operand" "=r")
8555 (neg:SI (gtu:SI (match_operand:SI
1 "gpc_reg_operand" "r")
8556 (match_operand:SI
2 "reg_or_short_operand" "rI"))))]
8558 "{sf%I2|subf%I2c} %
0,%
1,%
2\;{sfe|subfe} %
0,%
0,%
0"
8559 [(set_attr "length" "
8")])
8561 ;; Define both directions of branch and return. If we need a reload
8562 ;; register, we'd rather use CR0 since it is much easier to copy a
8563 ;; register CC value to there.
8567 (if_then_else (match_operator
1 "branch_comparison_operator"
8569 "cc_reg_operand" "x,?y")
8571 (label_ref (match_operand
0 "" ""))
8576 if (get_attr_length (insn) ==
8)
8577 return
\"%C1bc %t1,%j1,%l0
\";
8579 return
\"%C1bc %T1,%j1,$+
8\;b %l0
\";
8581 [(set_attr "type" "branch")])
8585 (if_then_else (match_operator
0 "branch_comparison_operator"
8587 "cc_reg_operand" "x,?y")
8592 "{%C0bcr|%C0bclr} %t0,%j0"
8593 [(set_attr "length" "
8")])
8597 (if_then_else (match_operator
1 "branch_comparison_operator"
8599 "cc_reg_operand" "x,?y")
8602 (label_ref (match_operand
0 "" ""))))]
8606 if (get_attr_length (insn) ==
8)
8607 return
\"%C1bc %T1,%j1,%l0
\";
8609 return
\"%C1bc %t1,%j1,$+
8\;b %l0
\";
8611 [(set_attr "type" "branch")])
8615 (if_then_else (match_operator
0 "branch_comparison_operator"
8617 "cc_reg_operand" "x,?y")
8622 "{%C0bcr|%C0bclr} %T0,%j0"
8623 [(set_attr "length" "
8")])
8625 ;; Unconditional branch and return.
8629 (label_ref (match_operand
0 "" "")))]
8633 (define_insn "return"
8637 [(set_attr "type" "jmpreg")])
8639 (define_insn "indirect_jump"
8640 [(set (pc) (match_operand:SI
0 "register_operand" "c,l"))]
8645 [(set_attr "type" "jmpreg")])
8648 [(set (pc) (match_operand:DI
0 "register_operand" "c,l"))]
8653 [(set_attr "type" "jmpreg")])
8655 ;; Table jump for switch statements:
8656 (define_expand "tablejump"
8657 [(use (match_operand
0 "" ""))
8658 (use (label_ref (match_operand
1 "" "")))]
8663 emit_jump_insn (gen_tablejumpsi (operands[
0], operands[
1]));
8665 emit_jump_insn (gen_tablejumpdi (operands[
0], operands[
1]));
8669 (define_expand "tablejumpsi"
8671 (plus:SI (match_operand:SI
0 "" "")
8673 (parallel [(set (pc) (match_dup
3))
8674 (use (label_ref (match_operand
1 "" "")))])]
8677 { operands[
0] = force_reg (SImode, operands[
0]);
8678 operands[
2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[
1]));
8679 operands[
3] = gen_reg_rtx (SImode);
8682 (define_expand "tablejumpdi"
8684 (plus:DI (match_operand:DI
0 "" "")
8686 (parallel [(set (pc) (match_dup
3))
8687 (use (label_ref (match_operand
1 "" "")))])]
8690 { operands[
0] = force_reg (DImode, operands[
0]);
8691 operands[
2] = force_reg (DImode, gen_rtx (LABEL_REF, VOIDmode, operands[
1]));
8692 operands[
3] = gen_reg_rtx (DImode);
8697 (match_operand:SI
0 "register_operand" "c,l"))
8698 (use (label_ref (match_operand
1 "" "")))]
8703 [(set_attr "type" "jmpreg")])
8707 (match_operand:DI
0 "register_operand" "c,l"))
8708 (use (label_ref (match_operand
1 "" "")))]
8713 [(set_attr "type" "jmpreg")])
8720 ;; Define the subtract-one-and-jump insns, starting with the template
8721 ;; so loop.c knows what to generate.
8723 (define_expand "decrement_and_branch_on_count"
8724 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI
0 "register_operand" "")
8726 (label_ref (match_operand
1 "" ""))
8729 (plus:SI (match_dup
0)
8731 (clobber (match_scratch:CC
2 ""))
8732 (clobber (match_scratch:SI
3 ""))])]
8736 ;; We need to be able to do this for any operand, including MEM, or we
8737 ;; will cause reload to blow up since we don't allow output reloads on
8739 ;; In order that the length attribute is calculated correctly, the
8740 ;; label MUST be operand
0.
8744 (if_then_else (ne (match_operand:SI
1 "register_operand" "c,*r,*r")
8746 (label_ref (match_operand
0 "" ""))
8748 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
8749 (plus:SI (match_dup
1)
8751 (clobber (match_scratch:CC
3 "=X,&x,&x"))
8752 (clobber (match_scratch:SI
4 "=X,X,r"))]
8756 if (which_alternative !=
0)
8758 else if (get_attr_length (insn) ==
8)
8759 return
\"{bdn|bdnz} %l0
\";
8761 return
\"bdz $+
8\;b %l0
\";
8763 [(set_attr "type" "branch")
8764 (set_attr "length" "*,
12,
16")])
8768 (if_then_else (ne (match_operand:SI
1 "register_operand" "c,*r,*r")
8771 (label_ref (match_operand
0 "" ""))))
8772 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
8773 (plus:SI (match_dup
1)
8775 (clobber (match_scratch:CC
3 "=X,&x,&x"))
8776 (clobber (match_scratch:SI
4 "=X,X,r"))]
8780 if (which_alternative !=
0)
8782 else if (get_attr_length (insn) ==
8)
8785 return
\"{bdn|bdnz} $+
8\;b %l0
\";
8787 [(set_attr "type" "branch")
8788 (set_attr "length" "*,
12,
16")])
8790 ;; Similar, but we can use GE since we have a REG_NONNEG.
8793 (if_then_else (ge (match_operand:SI
1 "register_operand" "c,*r,*r")
8795 (label_ref (match_operand
0 "" ""))
8797 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
8798 (plus:SI (match_dup
1)
8800 (clobber (match_scratch:CC
3 "=X,&x,&X"))
8801 (clobber (match_scratch:SI
4 "=X,X,r"))]
8802 "find_reg_note (insn, REG_NONNEG,
0)"
8805 if (which_alternative !=
0)
8807 else if (get_attr_length (insn) ==
8)
8808 return
\"{bdn|bdnz} %l0
\";
8810 return
\"bdz $+
8\;b %l0
\";
8812 [(set_attr "type" "branch")
8813 (set_attr "length" "*,
12,
16")])
8817 (if_then_else (ge (match_operand:SI
1 "register_operand" "c,*r,*r")
8820 (label_ref (match_operand
0 "" ""))))
8821 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
8822 (plus:SI (match_dup
1)
8824 (clobber (match_scratch:CC
3 "=X,&x,&X"))
8825 (clobber (match_scratch:SI
4 "=X,X,r"))]
8826 "find_reg_note (insn, REG_NONNEG,
0)"
8829 if (which_alternative !=
0)
8831 else if (get_attr_length (insn) ==
8)
8834 return
\"{bdn|bdnz} $+
8\;b %l0
\";
8836 [(set_attr "type" "branch")
8837 (set_attr "length" "*,
12,
16")])
8841 (if_then_else (eq (match_operand:SI
1 "register_operand" "c,*r,*r")
8843 (label_ref (match_operand
0 "" ""))
8845 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
8846 (plus:SI (match_dup
1)
8848 (clobber (match_scratch:CC
3 "=X,&x,&x"))
8849 (clobber (match_scratch:SI
4 "=X,X,r"))]
8853 if (which_alternative !=
0)
8855 else if (get_attr_length (insn) ==
8)
8858 return
\"{bdn|bdnz} $+
8\;b %l0
\";
8860 [(set_attr "type" "branch")
8861 (set_attr "length" "*,
12,
16")])
8865 (if_then_else (eq (match_operand:SI
1 "register_operand" "c,*r,*r")
8868 (label_ref (match_operand
0 "" ""))))
8869 (set (match_operand:SI
2 "register_operand" "=
1,*r,m*q*c*l")
8870 (plus:SI (match_dup
1)
8872 (clobber (match_scratch:CC
3 "=X,&x,&x"))
8873 (clobber (match_scratch:SI
4 "=X,X,r"))]
8877 if (which_alternative !=
0)
8879 else if (get_attr_length (insn) ==
8)
8880 return
\"{bdn|bdnz} %l0
\";
8882 return
\"bdz $+
8\;b %l0
\";
8884 [(set_attr "type" "branch")
8885 (set_attr "length" "*,
12,
16")])
8889 (if_then_else (match_operator
2 "comparison_operator"
8890 [(match_operand:SI
1 "gpc_reg_operand" "")
8892 (match_operand
5 "" "")
8893 (match_operand
6 "" "")))
8894 (set (match_operand:SI
0 "gpc_reg_operand" "")
8895 (plus:SI (match_dup
1)
8897 (clobber (match_scratch:CC
3 ""))
8898 (clobber (match_scratch:SI
4 ""))]
8900 [(parallel [(set (match_dup
3)
8901 (compare:CC (plus:SI (match_dup
1)
8905 (plus:SI (match_dup
1)
8907 (set (pc) (if_then_else (match_dup
7)
8911 { operands[
7] = gen_rtx (GET_CODE (operands[
2]), VOIDmode, operands[
3],
8916 (if_then_else (match_operator
2 "comparison_operator"
8917 [(match_operand:SI
1 "gpc_reg_operand" "")
8919 (match_operand
5 "" "")
8920 (match_operand
6 "" "")))
8921 (set (match_operand:SI
0 "general_operand" "")
8922 (plus:SI (match_dup
1) (const_int -
1)))
8923 (clobber (match_scratch:CC
3 ""))
8924 (clobber (match_scratch:SI
4 ""))]
8925 "reload_completed && ! gpc_reg_operand (operands[
0], SImode)"
8926 [(parallel [(set (match_dup
3)
8927 (compare:CC (plus:SI (match_dup
1)
8931 (plus:SI (match_dup
1)
8935 (set (pc) (if_then_else (match_dup
7)
8939 { operands[
7] = gen_rtx (GET_CODE (operands[
2]), VOIDmode, operands[
3],